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bcma: read out some additional sprom attributes
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ssb / pci.c
CommitLineData
61e115a5
MB		 1/*
2 * Sonics Silicon Backplane PCI-Hostbus related functions.
3 *
eb032b98 4 * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
61e115a5
MB		 5 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
6 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
7 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
8 * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
9 *
10 * Derived from the Broadcom 4400 device driver.
11 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
12 * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
13 * Copyright (C) 2006 Broadcom Corporation.
14 *
15 * Licensed under the GNU/GPL. See COPYING for details.
16 */
17
18#include <linux/ssb/ssb.h>
19#include <linux/ssb/ssb_regs.h>
5a0e3ad6 20#include <linux/slab.h>
61e115a5
MB		 21#include <linux/pci.h>
22#include <linux/delay.h>
23
24#include "ssb_private.h"
25
26
27/* Define the following to 1 to enable a printk on each coreswitch. */
28#define SSB_VERBOSE_PCICORESWITCH_DEBUG 0
29
30
31/* Lowlevel coreswitching */
32int ssb_pci_switch_coreidx(struct ssb_bus *bus, u8 coreidx)
33{
34 int err;
35 int attempts = 0;
36 u32 cur_core;
37
38 while (1) {
39 err = pci_write_config_dword(bus->host_pci, SSB_BAR0_WIN,
40 (coreidx * SSB_CORE_SIZE)
41 + SSB_ENUM_BASE);
42 if (err)
43 goto error;
44 err = pci_read_config_dword(bus->host_pci, SSB_BAR0_WIN,
45 &cur_core);
46 if (err)
47 goto error;
48 cur_core = (cur_core - SSB_ENUM_BASE)
49 / SSB_CORE_SIZE;
50 if (cur_core == coreidx)
51 break;
52
53 if (attempts++ > SSB_BAR0_MAX_RETRIES)
54 goto error;
55 udelay(10);
56 }
57 return 0;
58error:
59 ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
60 return -ENODEV;
61}
62
63int ssb_pci_switch_core(struct ssb_bus *bus,
64 struct ssb_device *dev)
65{
66 int err;
67 unsigned long flags;
68
69#if SSB_VERBOSE_PCICORESWITCH_DEBUG
70 ssb_printk(KERN_INFO PFX
71 "Switching to %s core, index %d\n",
72 ssb_core_name(dev->id.coreid),
73 dev->core_index);
74#endif
75
76 spin_lock_irqsave(&bus->bar_lock, flags);
77 err = ssb_pci_switch_coreidx(bus, dev->core_index);
78 if (!err)
79 bus->mapped_device = dev;
80 spin_unlock_irqrestore(&bus->bar_lock, flags);
81
82 return err;
83}
84
85/* Enable/disable the on board crystal oscillator and/or PLL. */
86int ssb_pci_xtal(struct ssb_bus *bus, u32 what, int turn_on)
87{
88 int err;
89 u32 in, out, outenable;
90 u16 pci_status;
91
92 if (bus->bustype != SSB_BUSTYPE_PCI)
93 return 0;
94
95 err = pci_read_config_dword(bus->host_pci, SSB_GPIO_IN, &in);
96 if (err)
97 goto err_pci;
98 err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &out);
99 if (err)
100 goto err_pci;
101 err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, &outenable);
102 if (err)
103 goto err_pci;
104
105 outenable |= what;
106
107 if (turn_on) {
108 /* Avoid glitching the clock if GPRS is already using it.
109 * We can't actually read the state of the PLLPD so we infer it
110 * by the value of XTAL_PU which *is* readable via gpioin.
111 */
112 if (!(in & SSB_GPIO_XTAL)) {
113 if (what & SSB_GPIO_XTAL) {
114 /* Turn the crystal on */
115 out |= SSB_GPIO_XTAL;
116 if (what & SSB_GPIO_PLL)
117 out |= SSB_GPIO_PLL;
118 err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
119 if (err)
120 goto err_pci;
121 err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE,
122 outenable);
123 if (err)
124 goto err_pci;
125 msleep(1);
126 }
127 if (what & SSB_GPIO_PLL) {
128 /* Turn the PLL on */
129 out &= ~SSB_GPIO_PLL;
130 err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
131 if (err)
132 goto err_pci;
133 msleep(5);
134 }
135 }
136
137 err = pci_read_config_word(bus->host_pci, PCI_STATUS, &pci_status);
138 if (err)
139 goto err_pci;
140 pci_status &= ~PCI_STATUS_SIG_TARGET_ABORT;
141 err = pci_write_config_word(bus->host_pci, PCI_STATUS, pci_status);
142 if (err)
143 goto err_pci;
144 } else {
145 if (what & SSB_GPIO_XTAL) {
146 /* Turn the crystal off */
147 out &= ~SSB_GPIO_XTAL;
148 }
149 if (what & SSB_GPIO_PLL) {
150 /* Turn the PLL off */
151 out |= SSB_GPIO_PLL;
152 }
153 err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
154 if (err)
155 goto err_pci;
156 err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, outenable);
157 if (err)
158 goto err_pci;
159 }
160
161out:
162 return err;
163
164err_pci:
165 printk(KERN_ERR PFX "Error: ssb_pci_xtal() could not access PCI config space!\n");
166 err = -EBUSY;
167 goto out;
168}
169
170/* Get the word-offset for a SSB_SPROM_XXX define. */
0a182fd8 171#define SPOFF(offset) ((offset) / sizeof(u16))
61e115a5 172/* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
f679056b 173#define SPEX16(_outvar, _offset, _mask, _shift) \
61e115a5 174 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
f679056b
GS		 175#define SPEX32(_outvar, _offset, _mask, _shift) \
176 out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
177 in[SPOFF(_offset)]) & (_mask)) >> (_shift))
178#define SPEX(_outvar, _offset, _mask, _shift) \
179 SPEX16(_outvar, _offset, _mask, _shift)
180
61e115a5
MB		 181
182static inline u8 ssb_crc8(u8 crc, u8 data)
183{
184 /* Polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1 */
185 static const u8 t[] = {
186 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
187 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
188 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
189 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
190 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
191 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
192 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
193 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
194 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
195 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
196 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
197 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
198 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
199 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
200 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
201 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
202 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
203 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
204 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
205 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
206 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
207 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
208 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
209 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
210 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
211 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
212 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
213 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
214 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
215 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
216 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
217 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
218 };
219 return t[crc ^ data];
220}
221
c272ef44 222static u8 ssb_sprom_crc(const u16 *sprom, u16 size)
61e115a5
MB		 223{
224 int word;
225 u8 crc = 0xFF;
226
c272ef44 227 for (word = 0; word < size - 1; word++) {
61e115a5
MB		 228 crc = ssb_crc8(crc, sprom[word] & 0x00FF);
229 crc = ssb_crc8(crc, (sprom[word] & 0xFF00) >> 8);
230 }
c272ef44 231 crc = ssb_crc8(crc, sprom[size - 1] & 0x00FF);
61e115a5
MB		 232 crc ^= 0xFF;
233
234 return crc;
235}
236
e7ec2e32 237static int sprom_check_crc(const u16 *sprom, size_t size)
61e115a5
MB		 238{
239 u8 crc;
240 u8 expected_crc;
241 u16 tmp;
242
c272ef44
LF		 243 crc = ssb_sprom_crc(sprom, size);
244 tmp = sprom[size - 1] & SSB_SPROM_REVISION_CRC;
61e115a5
MB		 245 expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
246 if (crc != expected_crc)
247 return -EPROTO;
248
249 return 0;
250}
251
e7ec2e32 252static int sprom_do_read(struct ssb_bus *bus, u16 *sprom)
61e115a5
MB		 253{
254 int i;
255
c272ef44 256 for (i = 0; i < bus->sprom_size; i++)
ea2db495 257 sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
e7ec2e32
MB		 258
259 return 0;
61e115a5
MB		 260}
261
262static int sprom_do_write(struct ssb_bus *bus, const u16 *sprom)
263{
264 struct pci_dev *pdev = bus->host_pci;
265 int i, err;
266 u32 spromctl;
c272ef44 267 u16 size = bus->sprom_size;
61e115a5
MB		 268
269 ssb_printk(KERN_NOTICE PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
270 err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
271 if (err)
272 goto err_ctlreg;
273 spromctl |= SSB_SPROMCTL_WE;
274 err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
275 if (err)
276 goto err_ctlreg;
277 ssb_printk(KERN_NOTICE PFX "[ 0%%");
278 msleep(500);
c272ef44
LF		 279 for (i = 0; i < size; i++) {
280 if (i == size / 4)
61e115a5 281 ssb_printk("25%%");
c272ef44 282 else if (i == size / 2)
61e115a5 283 ssb_printk("50%%");
c272ef44 284 else if (i == (size * 3) / 4)
61e115a5
MB		 285 ssb_printk("75%%");
286 else if (i % 2)
287 ssb_printk(".");
ea2db495 288 writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
61e115a5
MB		 289 mmiowb();
290 msleep(20);
291 }
292 err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
293 if (err)
294 goto err_ctlreg;
295 spromctl &= ~SSB_SPROMCTL_WE;
296 err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
297 if (err)
298 goto err_ctlreg;
299 msleep(500);
300 ssb_printk("100%% ]\n");
301 ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
302
303 return 0;
304err_ctlreg:
305 ssb_printk(KERN_ERR PFX "Could not access SPROM control register.\n");
306 return err;
307}
308
e861b98d
MB		 309static s8 r123_extract_antgain(u8 sprom_revision, const u16 *in,
310 u16 mask, u16 shift)
311{
312 u16 v;
313 u8 gain;
314
315 v = in[SPOFF(SSB_SPROM1_AGAIN)];
316 gain = (v & mask) >> shift;
317 if (gain == 0xFF)
318 gain = 2; /* If unset use 2dBm */
319 if (sprom_revision == 1) {
320 /* Convert to Q5.2 */
321 gain <<= 2;
322 } else {
323 /* Q5.2 Fractional part is stored in 0xC0 */
324 gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
325 }
326
327 return (s8)gain;
328}
329
c272ef44 330static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
61e115a5
MB		 331{
332 int i;
333 u16 v;
c272ef44 334 u16 loc[3];
61e115a5 335
31ce12fb 336 if (out->revision == 3) /* rev 3 moved MAC */
c272ef44 337 loc[0] = SSB_SPROM3_IL0MAC;
31ce12fb 338 else {
c272ef44
LF		 339 loc[0] = SSB_SPROM1_IL0MAC;
340 loc[1] = SSB_SPROM1_ET0MAC;
341 loc[2] = SSB_SPROM1_ET1MAC;
342 }
343 for (i = 0; i < 3; i++) {
344 v = in[SPOFF(loc[0]) + i];
345 *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
346 }
31ce12fb
LF		 347 if (out->revision < 3) { /* only rev 1-2 have et0, et1 */
348 for (i = 0; i < 3; i++) {
349 v = in[SPOFF(loc[1]) + i];
350 *(((__be16 *)out->et0mac) + i) = cpu_to_be16(v);
351 }
352 for (i = 0; i < 3; i++) {
353 v = in[SPOFF(loc[2]) + i];
354 *(((__be16 *)out->et1mac) + i) = cpu_to_be16(v);
355 }
61e115a5 356 }
c272ef44
LF		 357 SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
358 SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
359 SSB_SPROM1_ETHPHY_ET1A_SHIFT);
e861b98d
MB		 360 SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
361 SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
362 SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
bf7d420b
HM		 363 if (out->revision == 1)
364 SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
365 SSB_SPROM1_BINF_CCODE_SHIFT);
e861b98d
MB		 366 SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
367 SSB_SPROM1_BINF_ANTA_SHIFT);
368 SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
369 SSB_SPROM1_BINF_ANTBG_SHIFT);
c272ef44
LF		 370 SPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0);
371 SPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0);
372 SPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0);
373 SPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0);
374 SPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0);
375 SPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0);
376 SPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0);
377 SPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1,
378 SSB_SPROM1_GPIOA_P1_SHIFT);
379 SPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0);
380 SPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3,
381 SSB_SPROM1_GPIOB_P3_SHIFT);
382 SPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A,
383 SSB_SPROM1_MAXPWR_A_SHIFT);
384 SPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG, 0);
385 SPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A,
386 SSB_SPROM1_ITSSI_A_SHIFT);
387 SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
388 SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
af4b7450
MB		 389 if (out->revision >= 2)
390 SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
bf7d420b
HM		 391 SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
392 SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
e861b98d
MB		 393
394 /* Extract the antenna gain values. */
f8f8a660
HM		 395 out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
396 SSB_SPROM1_AGAIN_BG,
397 SSB_SPROM1_AGAIN_BG_SHIFT);
398 out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
399 SSB_SPROM1_AGAIN_A,
400 SSB_SPROM1_AGAIN_A_SHIFT);
61e115a5
MB		 401}
402
172c69a4
RM		 403/* Revs 4 5 and 8 have partially shared layout */
404static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
405{
406 SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
407 SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
408 SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
409 SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
410 SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
411 SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
412 SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
413 SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
414
415 SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
416 SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
417 SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
418 SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
419 SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
420 SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
421 SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
422 SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
423
424 SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
425 SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
426 SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
427 SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
428 SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
429 SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
430 SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
431 SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
432
433 SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
434 SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
435 SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
436 SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
437 SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
438 SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
439 SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
440 SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
441}
442
095f695c 443static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
61e115a5 444{
c272ef44
LF		 445 int i;
446 u16 v;
095f695c 447 u16 il0mac_offset;
c272ef44 448
095f695c
LF		 449 if (out->revision == 4)
450 il0mac_offset = SSB_SPROM4_IL0MAC;
451 else
452 il0mac_offset = SSB_SPROM5_IL0MAC;
31ce12fb 453 /* extract the MAC address */
c272ef44 454 for (i = 0; i < 3; i++) {
095f695c 455 v = in[SPOFF(il0mac_offset) + i];
c272ef44
LF		 456 *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
457 }
c272ef44
LF		 458 SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
459 SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
460 SSB_SPROM4_ETHPHY_ET1A_SHIFT);
673335c8 461 SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
095f695c 462 if (out->revision == 4) {
bf7d420b
HM		 463 SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
464 SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
095f695c
LF		 465 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
466 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
6d1d4ea4
RM		 467 SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
468 SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
095f695c 469 } else {
bf7d420b
HM		 470 SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
471 SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
095f695c
LF		 472 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
473 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
6d1d4ea4
RM		 474 SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
475 SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
095f695c 476 }
e861b98d
MB		 477 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
478 SSB_SPROM4_ANTAVAIL_A_SHIFT);
479 SPEX(ant_available_bg, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_BG,
480 SSB_SPROM4_ANTAVAIL_BG_SHIFT);
d3c319f9
LF		 481 SPEX(maxpwr_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_MAXP_BG_MASK, 0);
482 SPEX(itssi_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_ITSSI_BG,
483 SSB_SPROM4_ITSSI_BG_SHIFT);
484 SPEX(maxpwr_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_MAXP_A_MASK, 0);
485 SPEX(itssi_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_ITSSI_A,
486 SSB_SPROM4_ITSSI_A_SHIFT);
095f695c
LF		 487 if (out->revision == 4) {
488 SPEX(gpio0, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P0, 0);
489 SPEX(gpio1, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P1,
490 SSB_SPROM4_GPIOA_P1_SHIFT);
491 SPEX(gpio2, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P2, 0);
492 SPEX(gpio3, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P3,
493 SSB_SPROM4_GPIOB_P3_SHIFT);
494 } else {
495 SPEX(gpio0, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P0, 0);
496 SPEX(gpio1, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P1,
497 SSB_SPROM5_GPIOA_P1_SHIFT);
498 SPEX(gpio2, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P2, 0);
499 SPEX(gpio3, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P3,
500 SSB_SPROM5_GPIOB_P3_SHIFT);
501 }
e861b98d
MB		 502
503 /* Extract the antenna gain values. */
f8f8a660 504 SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
e861b98d 505 SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
f8f8a660 506 SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
e861b98d 507 SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
f8f8a660 508 SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
e861b98d 509 SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
f8f8a660 510 SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
e861b98d 511 SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
e861b98d 512
172c69a4
RM		 513 sprom_extract_r458(out, in);
514
c272ef44 515 /* TODO - get remaining rev 4 stuff needed */
61e115a5
MB		 516}
517
6b1c7c67
MB		 518static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
519{
520 int i;
b0f70292
RM		 521 u16 v, o;
522 u16 pwr_info_offset[] = {
523 SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
524 SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
525 };
526 BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
527 ARRAY_SIZE(out->core_pwr_info));
6b1c7c67
MB		 528
529 /* extract the MAC address */
530 for (i = 0; i < 3; i++) {
f0ea6ce1 531 v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
6b1c7c67
MB		 532 *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
533 }
673335c8 534 SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
bf7d420b
HM		 535 SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
536 SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
6b1c7c67
MB		 537 SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
538 SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
f679056b
GS		 539 SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
540 SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);
6b1c7c67
MB		 541 SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
542 SSB_SPROM8_ANTAVAIL_A_SHIFT);
543 SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
544 SSB_SPROM8_ANTAVAIL_BG_SHIFT);
545 SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
546 SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
547 SSB_SPROM8_ITSSI_BG_SHIFT);
548 SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
549 SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
550 SSB_SPROM8_ITSSI_A_SHIFT);
f679056b
GS		 551 SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
552 SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
553 SSB_SPROM8_MAXP_AL_SHIFT);
6b1c7c67
MB		 554 SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
555 SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
556 SSB_SPROM8_GPIOA_P1_SHIFT);
557 SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
558 SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
559 SSB_SPROM8_GPIOB_P3_SHIFT);
f679056b
GS		 560 SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
561 SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
562 SSB_SPROM8_TRI5G_SHIFT);
563 SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
564 SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
565 SSB_SPROM8_TRI5GH_SHIFT);
566 SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);
567 SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
568 SSB_SPROM8_RXPO5G_SHIFT);
569 SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
570 SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
571 SSB_SPROM8_RSSISMC2G_SHIFT);
572 SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
573 SSB_SPROM8_RSSISAV2G_SHIFT);
574 SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
575 SSB_SPROM8_BXA2G_SHIFT);
576 SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
577 SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
578 SSB_SPROM8_RSSISMC5G_SHIFT);
579 SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
580 SSB_SPROM8_RSSISAV5G_SHIFT);
581 SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
582 SSB_SPROM8_BXA5G_SHIFT);
583 SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);
584 SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);
585 SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);
586 SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);
587 SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);
588 SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);
589 SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);
590 SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);
591 SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);
592 SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);
593 SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);
594 SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);
595 SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);
596 SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);
597 SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);
598 SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);
599 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
6b1c7c67
MB		 600
601 /* Extract the antenna gain values. */
f8f8a660 602 SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
6b1c7c67 603 SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
f8f8a660 604 SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
6b1c7c67 605 SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
f8f8a660 606 SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
6b1c7c67 607 SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
f8f8a660 608 SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
6b1c7c67 609 SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
6b1c7c67 610
b0f70292
RM		 611 /* Extract cores power info info */
612 for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
613 o = pwr_info_offset[i];
614 SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
615 SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
616 SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
617 SSB_SPROM8_2G_MAXP, 0);
618
619 SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
620 SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
621 SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
622
623 SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
624 SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
625 SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
626 SSB_SPROM8_5G_MAXP, 0);
627 SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
628 SSB_SPROM8_5GH_MAXP, 0);
629 SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
630 SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
631
632 SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
633 SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
634 SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
635 SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
636 SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
637 SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
638 SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
639 SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
640 SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
641 }
642
8a5ac6ec
RM		 643 /* Extract FEM info */
644 SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
645 SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
646 SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
647 SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
648 SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
649 SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
650 SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
651 SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
652 SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
653 SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
654
655 SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
656 SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
657 SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
658 SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
659 SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
660 SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
661 SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
662 SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
663 SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
664 SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
665
172c69a4
RM		 666 sprom_extract_r458(out, in);
667
6b1c7c67
MB		 668 /* TODO - get remaining rev 8 stuff needed */
669}
670
c272ef44
LF		 671static int sprom_extract(struct ssb_bus *bus, struct ssb_sprom *out,
672 const u16 *in, u16 size)
61e115a5
MB		 673{
674 memset(out, 0, sizeof(*out));
675
c272ef44 676 out->revision = in[size - 1] & 0x00FF;
e861b98d 677 ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
31ce12fb
LF		 678 memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
679 memset(out->et1mac, 0xFF, 6);
54435f9e 680
61e115a5
MB		 681 if ((bus->chip_id & 0xFF00) == 0x4400) {
682 /* Workaround: The BCM44XX chip has a stupid revision
683 * number stored in the SPROM.
684 * Always extract r1. */
c272ef44 685 out->revision = 1;
54435f9e 686 ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
54435f9e
RM		 687 }
688
689 switch (out->revision) {
690 case 1:
691 case 2:
692 case 3:
693 sprom_extract_r123(out, in);
694 break;
695 case 4:
696 case 5:
095f695c 697 sprom_extract_r45(out, in);
54435f9e
RM		 698 break;
699 case 8:
700 sprom_extract_r8(out, in);
701 break;
702 default:
703 ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
98605c2e 704 " revision %d detected. Will extract"
54435f9e
RM		 705 " v1\n", out->revision);
706 out->revision = 1;
707 sprom_extract_r123(out, in);
61e115a5
MB		 708 }
709
4503183a
LF		 710 if (out->boardflags_lo == 0xFFFF)
711 out->boardflags_lo = 0; /* per specs */
712 if (out->boardflags_hi == 0xFFFF)
713 out->boardflags_hi = 0; /* per specs */
714
61e115a5 715 return 0;
61e115a5
MB		 716}
717
718static int ssb_pci_sprom_get(struct ssb_bus *bus,
719 struct ssb_sprom *sprom)
720{
ca4a0831 721 int err;
61e115a5
MB		 722 u16 *buf;
723
d53cdbb9
JL		 724 if (!ssb_is_sprom_available(bus)) {
725 ssb_printk(KERN_ERR PFX "No SPROM available!\n");
726 return -ENODEV;
727 }
25985edc 728 if (bus->chipco.dev) { /* can be unavailable! */
9d1ac34e
LF		 729 /*
730 * get SPROM offset: SSB_SPROM_BASE1 except for
731 * chipcommon rev >= 31 or chip ID is 0x4312 and
732 * chipcommon status & 3 == 2
733 */
734 if (bus->chipco.dev->id.revision >= 31)
735 bus->sprom_offset = SSB_SPROM_BASE31;
736 else if (bus->chip_id == 0x4312 &&
737 (bus->chipco.status & 0x03) == 2)
738 bus->sprom_offset = SSB_SPROM_BASE31;
739 else
740 bus->sprom_offset = SSB_SPROM_BASE1;
da1fdb02
CF		 741 } else {
742 bus->sprom_offset = SSB_SPROM_BASE1;
743 }
9d1ac34e 744 ssb_dprintk(KERN_INFO PFX "SPROM offset is 0x%x\n", bus->sprom_offset);
ea2db495 745
c272ef44 746 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
61e115a5 747 if (!buf)
ca4a0831 748 return -ENOMEM;
c272ef44 749 bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
61e115a5 750 sprom_do_read(bus, buf);
c272ef44 751 err = sprom_check_crc(buf, bus->sprom_size);
61e115a5 752 if (err) {
2afc4901
LF		 753 /* try for a 440 byte SPROM - revision 4 and higher */
754 kfree(buf);
755 buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
756 GFP_KERNEL);
757 if (!buf)
ca4a0831 758 return -ENOMEM;
2afc4901
LF		 759 bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
760 sprom_do_read(bus, buf);
761 err = sprom_check_crc(buf, bus->sprom_size);
e79c1ba8
MB		 762 if (err) {
763 /* All CRC attempts failed.
764 * Maybe there is no SPROM on the device?
b3ae52b6
HM		 765 * Now we ask the arch code if there is some sprom
766 * available for this device in some other storage */
767 err = ssb_fill_sprom_with_fallback(bus, sprom);
768 if (err) {
769 ssb_printk(KERN_WARNING PFX "WARNING: Using"
770 " fallback SPROM failed (err %d)\n",
771 err);
772 } else {
773 ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
774 " revision %d provided by"
775 " platform.\n", sprom->revision);
e79c1ba8
MB		 776 err = 0;
777 goto out_free;
778 }
c272ef44
LF		 779 ssb_printk(KERN_WARNING PFX "WARNING: Invalid"
780 " SPROM CRC (corrupt SPROM)\n");
e79c1ba8 781 }
61e115a5 782 }
c272ef44 783 err = sprom_extract(bus, sprom, buf, bus->sprom_size);
61e115a5 784
e79c1ba8 785out_free:
61e115a5 786 kfree(buf);
61e115a5
MB		 787 return err;
788}
789
790static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
791 struct ssb_boardinfo *bi)
792{
115f9450
SS		 793 bi->vendor = bus->host_pci->subsystem_vendor;
794 bi->type = bus->host_pci->subsystem_device;
61e115a5
MB		 795}
796
797int ssb_pci_get_invariants(struct ssb_bus *bus,
798 struct ssb_init_invariants *iv)
799{
800 int err;
801
802 err = ssb_pci_sprom_get(bus, &iv->sprom);
803 if (err)
804 goto out;
805 ssb_pci_get_boardinfo(bus, &iv->boardinfo);
806
807out:
808 return err;
809}
810
811#ifdef CONFIG_SSB_DEBUG
812static int ssb_pci_assert_buspower(struct ssb_bus *bus)
813{
814 if (likely(bus->powered_up))
815 return 0;
816
817 printk(KERN_ERR PFX "FATAL ERROR: Bus powered down "
818 "while accessing PCI MMIO space\n");
819 if (bus->power_warn_count <= 10) {
820 bus->power_warn_count++;
821 dump_stack();
822 }
823
824 return -ENODEV;
825}
826#else /* DEBUG */
827static inline int ssb_pci_assert_buspower(struct ssb_bus *bus)
828{
829 return 0;
830}
831#endif /* DEBUG */
832
ffc7689d
MB		 833static u8 ssb_pci_read8(struct ssb_device *dev, u16 offset)
834{
835 struct ssb_bus *bus = dev->bus;
836
837 if (unlikely(ssb_pci_assert_buspower(bus)))
838 return 0xFF;
839 if (unlikely(bus->mapped_device != dev)) {
840 if (unlikely(ssb_pci_switch_core(bus, dev)))
841 return 0xFF;
842 }
843 return ioread8(bus->mmio + offset);
844}
845
61e115a5
MB		 846static u16 ssb_pci_read16(struct ssb_device *dev, u16 offset)
847{
848 struct ssb_bus *bus = dev->bus;
849
850 if (unlikely(ssb_pci_assert_buspower(bus)))
851 return 0xFFFF;
852 if (unlikely(bus->mapped_device != dev)) {
853 if (unlikely(ssb_pci_switch_core(bus, dev)))
854 return 0xFFFF;
855 }
4b402c65 856 return ioread16(bus->mmio + offset);
61e115a5
MB		 857}
858
859static u32 ssb_pci_read32(struct ssb_device *dev, u16 offset)
860{
861 struct ssb_bus *bus = dev->bus;
862
863 if (unlikely(ssb_pci_assert_buspower(bus)))
864 return 0xFFFFFFFF;
865 if (unlikely(bus->mapped_device != dev)) {
866 if (unlikely(ssb_pci_switch_core(bus, dev)))
867 return 0xFFFFFFFF;
868 }
4b402c65 869 return ioread32(bus->mmio + offset);
61e115a5
MB		 870}
871
d625a29b
MB		 872#ifdef CONFIG_SSB_BLOCKIO
873static void ssb_pci_block_read(struct ssb_device *dev, void *buffer,
874 size_t count, u16 offset, u8 reg_width)
875{
876 struct ssb_bus *bus = dev->bus;
877 void __iomem *addr = bus->mmio + offset;
878
879 if (unlikely(ssb_pci_assert_buspower(bus)))
880 goto error;
881 if (unlikely(bus->mapped_device != dev)) {
882 if (unlikely(ssb_pci_switch_core(bus, dev)))
883 goto error;
884 }
885 switch (reg_width) {
886 case sizeof(u8):
887 ioread8_rep(addr, buffer, count);
888 break;
889 case sizeof(u16):
890 SSB_WARN_ON(count & 1);
891 ioread16_rep(addr, buffer, count >> 1);
892 break;
893 case sizeof(u32):
894 SSB_WARN_ON(count & 3);
895 ioread32_rep(addr, buffer, count >> 2);
896 break;
897 default:
898 SSB_WARN_ON(1);
899 }
900
901 return;
902error:
903 memset(buffer, 0xFF, count);
904}
905#endif /* CONFIG_SSB_BLOCKIO */
906
ffc7689d
MB		 907static void ssb_pci_write8(struct ssb_device *dev, u16 offset, u8 value)
908{
909 struct ssb_bus *bus = dev->bus;
910
911 if (unlikely(ssb_pci_assert_buspower(bus)))
912 return;
913 if (unlikely(bus->mapped_device != dev)) {
914 if (unlikely(ssb_pci_switch_core(bus, dev)))
915 return;
916 }
917 iowrite8(value, bus->mmio + offset);
918}
919
61e115a5
MB		 920static void ssb_pci_write16(struct ssb_device *dev, u16 offset, u16 value)
921{
922 struct ssb_bus *bus = dev->bus;
923
924 if (unlikely(ssb_pci_assert_buspower(bus)))
925 return;
926 if (unlikely(bus->mapped_device != dev)) {
927 if (unlikely(ssb_pci_switch_core(bus, dev)))
928 return;
929 }
4b402c65 930 iowrite16(value, bus->mmio + offset);
61e115a5
MB		 931}
932
933static void ssb_pci_write32(struct ssb_device *dev, u16 offset, u32 value)
934{
935 struct ssb_bus *bus = dev->bus;
936
937 if (unlikely(ssb_pci_assert_buspower(bus)))
938 return;
939 if (unlikely(bus->mapped_device != dev)) {
940 if (unlikely(ssb_pci_switch_core(bus, dev)))
941 return;
942 }
4b402c65 943 iowrite32(value, bus->mmio + offset);
61e115a5
MB		 944}
945
d625a29b
MB		 946#ifdef CONFIG_SSB_BLOCKIO
947static void ssb_pci_block_write(struct ssb_device *dev, const void *buffer,
948 size_t count, u16 offset, u8 reg_width)
949{
950 struct ssb_bus *bus = dev->bus;
951 void __iomem *addr = bus->mmio + offset;
952
953 if (unlikely(ssb_pci_assert_buspower(bus)))
954 return;
955 if (unlikely(bus->mapped_device != dev)) {
956 if (unlikely(ssb_pci_switch_core(bus, dev)))
957 return;
958 }
959 switch (reg_width) {
960 case sizeof(u8):
961 iowrite8_rep(addr, buffer, count);
962 break;
963 case sizeof(u16):
964 SSB_WARN_ON(count & 1);
965 iowrite16_rep(addr, buffer, count >> 1);
966 break;
967 case sizeof(u32):
968 SSB_WARN_ON(count & 3);
969 iowrite32_rep(addr, buffer, count >> 2);
970 break;
971 default:
972 SSB_WARN_ON(1);
973 }
974}
975#endif /* CONFIG_SSB_BLOCKIO */
976
61e115a5
MB		 977/* Not "static", as it's used in main.c */
978const struct ssb_bus_ops ssb_pci_ops = {
ffc7689d 979 .read8 = ssb_pci_read8,
61e115a5
MB		 980 .read16 = ssb_pci_read16,
981 .read32 = ssb_pci_read32,
ffc7689d 982 .write8 = ssb_pci_write8,
61e115a5
MB		 983 .write16 = ssb_pci_write16,
984 .write32 = ssb_pci_write32,
d625a29b
MB		 985#ifdef CONFIG_SSB_BLOCKIO
986 .block_read = ssb_pci_block_read,
987 .block_write = ssb_pci_block_write,
988#endif
61e115a5
MB		 989};
990
61e115a5
MB		 991static ssize_t ssb_pci_attr_sprom_show(struct device *pcidev,
992 struct device_attribute *attr,
993 char *buf)
994{
995 struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev);
996 struct ssb_bus *bus;
61e115a5
MB		 997
998 bus = ssb_pci_dev_to_bus(pdev);
999 if (!bus)
e7ec2e32 1000 return -ENODEV;
61e115a5 1001
e7ec2e32 1002 return ssb_attr_sprom_show(bus, buf, sprom_do_read);
61e115a5
MB		 1003}
1004
1005static ssize_t ssb_pci_attr_sprom_store(struct device *pcidev,
1006 struct device_attribute *attr,
1007 const char *buf, size_t count)
1008{
1009 struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev);
1010 struct ssb_bus *bus;
61e115a5
MB		 1011
1012 bus = ssb_pci_dev_to_bus(pdev);
1013 if (!bus)
e7ec2e32 1014 return -ENODEV;
61e115a5 1015
e7ec2e32
MB		 1016 return ssb_attr_sprom_store(bus, buf, count,
1017 sprom_check_crc, sprom_do_write);
61e115a5
MB		 1018}
1019
1020static DEVICE_ATTR(ssb_sprom, 0600,
1021 ssb_pci_attr_sprom_show,
1022 ssb_pci_attr_sprom_store);
1023
1024void ssb_pci_exit(struct ssb_bus *bus)
1025{
1026 struct pci_dev *pdev;
1027
1028 if (bus->bustype != SSB_BUSTYPE_PCI)
1029 return;
1030
1031 pdev = bus->host_pci;
1032 device_remove_file(&pdev->dev, &dev_attr_ssb_sprom);
1033}
1034
1035int ssb_pci_init(struct ssb_bus *bus)
1036{
1037 struct pci_dev *pdev;
1038 int err;
1039
1040 if (bus->bustype != SSB_BUSTYPE_PCI)
1041 return 0;
1042
1043 pdev = bus->host_pci;
e7ec2e32 1044 mutex_init(&bus->sprom_mutex);
61e115a5
MB		 1045 err = device_create_file(&pdev->dev, &dev_attr_ssb_sprom);
1046 if (err)
1047 goto out;
1048
1049out:
1050 return err;
1051}
kernel source for telekom puls (alcatel/mediatek)