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[SCSI] sym53c8xx: Remove ->device_id
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / sym53c8xx_2 / sym_hipd.c
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1da177e4
LT		 1/*
2 * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family
3 * of PCI-SCSI IO processors.
4 *
5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
6 * Copyright (c) 2003-2005 Matthew Wilcox <matthew@wil.cx>
7 *
8 * This driver is derived from the Linux sym53c8xx driver.
9 * Copyright (C) 1998-2000 Gerard Roudier
10 *
11 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
12 * a port of the FreeBSD ncr driver to Linux-1.2.13.
13 *
14 * The original ncr driver has been written for 386bsd and FreeBSD by
15 * Wolfgang Stanglmeier <wolf@cologne.de>
16 * Stefan Esser <se@mi.Uni-Koeln.de>
17 * Copyright (C) 1994 Wolfgang Stanglmeier
18 *
19 * Other major contributions:
20 *
21 * NVRAM detection and reading.
22 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
23 *
24 *-----------------------------------------------------------------------------
25 *
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License as published by
28 * the Free Software Foundation; either version 2 of the License, or
29 * (at your option) any later version.
30 *
31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details.
35 *
36 * You should have received a copy of the GNU General Public License
37 * along with this program; if not, write to the Free Software
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
39 */
4e57b681
TS		 40
41#include <linux/slab.h>
8c65b4a6 42#include <asm/param.h> /* for timeouts in units of HZ */
4e57b681 43
1da177e4
LT		 44#include "sym_glue.h"
45#include "sym_nvram.h"
46
47#if 0
48#define SYM_DEBUG_GENERIC_SUPPORT
49#endif
50
51/*
52 * Needed function prototypes.
53 */
54static void sym_int_ma (struct sym_hcb *np);
55static void sym_int_sir (struct sym_hcb *np);
56static struct sym_ccb *sym_alloc_ccb(struct sym_hcb *np);
57static struct sym_ccb *sym_ccb_from_dsa(struct sym_hcb *np, u32 dsa);
58static void sym_alloc_lcb_tags (struct sym_hcb *np, u_char tn, u_char ln);
59static void sym_complete_error (struct sym_hcb *np, struct sym_ccb *cp);
60static void sym_complete_ok (struct sym_hcb *np, struct sym_ccb *cp);
61static int sym_compute_residual(struct sym_hcb *np, struct sym_ccb *cp);
62
63/*
64 * Print a buffer in hexadecimal format with a ".\n" at end.
65 */
66static void sym_printl_hex(u_char *p, int n)
67{
68 while (n-- > 0)
69 printf (" %x", *p++);
70 printf (".\n");
71}
72
1da177e4
LT		 73static void sym_print_msg(struct sym_ccb *cp, char *label, u_char *msg)
74{
92d578b9
MW		 75 if (label)
76 sym_print_addr(cp->cmd, "%s: ", label);
77 else
78 sym_print_addr(cp->cmd, "");
1da177e4 79
1abfd370 80 spi_print_msg(msg);
33333bac 81 printf("\n");
1da177e4
LT		 82}
83
84static void sym_print_nego_msg(struct sym_hcb *np, int target, char *label, u_char *msg)
85{
86 struct sym_tcb *tp = &np->target[target];
53222b90 87 dev_info(&tp->starget->dev, "%s: ", label);
1da177e4 88
1abfd370 89 spi_print_msg(msg);
33333bac 90 printf("\n");
1da177e4
LT		 91}
92
93/*
94 * Print something that tells about extended errors.
95 */
96void sym_print_xerr(struct scsi_cmnd *cmd, int x_status)
97{
98 if (x_status & XE_PARITY_ERR) {
99 sym_print_addr(cmd, "unrecovered SCSI parity error.\n");
100 }
101 if (x_status & XE_EXTRA_DATA) {
102 sym_print_addr(cmd, "extraneous data discarded.\n");
103 }
104 if (x_status & XE_BAD_PHASE) {
105 sym_print_addr(cmd, "illegal scsi phase (4/5).\n");
106 }
107 if (x_status & XE_SODL_UNRUN) {
108 sym_print_addr(cmd, "ODD transfer in DATA OUT phase.\n");
109 }
110 if (x_status & XE_SWIDE_OVRUN) {
111 sym_print_addr(cmd, "ODD transfer in DATA IN phase.\n");
112 }
113}
114
115/*
116 * Return a string for SCSI BUS mode.
117 */
118static char *sym_scsi_bus_mode(int mode)
119{
120 switch(mode) {
121 case SMODE_HVD: return "HVD";
122 case SMODE_SE: return "SE";
123 case SMODE_LVD: return "LVD";
124 }
125 return "??";
126}
127
128/*
129 * Soft reset the chip.
130 *
131 * Raising SRST when the chip is running may cause
132 * problems on dual function chips (see below).
133 * On the other hand, LVD devices need some delay
134 * to settle and report actual BUS mode in STEST4.
135 */
136static void sym_chip_reset (struct sym_hcb *np)
137{
138 OUTB(np, nc_istat, SRST);
53222b90 139 INB(np, nc_mbox1);
1da177e4
LT		 140 udelay(10);
141 OUTB(np, nc_istat, 0);
53222b90 142 INB(np, nc_mbox1);
1da177e4
LT		 143 udelay(2000); /* For BUS MODE to settle */
144}
145
146/*
147 * Really soft reset the chip.:)
148 *
149 * Some 896 and 876 chip revisions may hang-up if we set
150 * the SRST (soft reset) bit at the wrong time when SCRIPTS
151 * are running.
152 * So, we need to abort the current operation prior to
153 * soft resetting the chip.
154 */
155static void sym_soft_reset (struct sym_hcb *np)
156{
157 u_char istat = 0;
158 int i;
159
160 if (!(np->features & FE_ISTAT1) || !(INB(np, nc_istat1) & SCRUN))
161 goto do_chip_reset;
162
163 OUTB(np, nc_istat, CABRT);
164 for (i = 100000 ; i ; --i) {
165 istat = INB(np, nc_istat);
166 if (istat & SIP) {
167 INW(np, nc_sist);
168 }
169 else if (istat & DIP) {
170 if (INB(np, nc_dstat) & ABRT)
171 break;
172 }
173 udelay(5);
174 }
175 OUTB(np, nc_istat, 0);
176 if (!i)
177 printf("%s: unable to abort current chip operation, "
178 "ISTAT=0x%02x.\n", sym_name(np), istat);
179do_chip_reset:
180 sym_chip_reset(np);
181}
182
183/*
184 * Start reset process.
185 *
186 * The interrupt handler will reinitialize the chip.
187 */
188static void sym_start_reset(struct sym_hcb *np)
189{
190 sym_reset_scsi_bus(np, 1);
191}
192
193int sym_reset_scsi_bus(struct sym_hcb *np, int enab_int)
194{
195 u32 term;
196 int retv = 0;
197
198 sym_soft_reset(np); /* Soft reset the chip */
199 if (enab_int)
200 OUTW(np, nc_sien, RST);
201 /*
202 * Enable Tolerant, reset IRQD if present and
203 * properly set IRQ mode, prior to resetting the bus.
204 */
205 OUTB(np, nc_stest3, TE);
206 OUTB(np, nc_dcntl, (np->rv_dcntl & IRQM));
207 OUTB(np, nc_scntl1, CRST);
53222b90 208 INB(np, nc_mbox1);
1da177e4
LT		 209 udelay(200);
210
211 if (!SYM_SETUP_SCSI_BUS_CHECK)
212 goto out;
213 /*
214 * Check for no terminators or SCSI bus shorts to ground.
215 * Read SCSI data bus, data parity bits and control signals.
216 * We are expecting RESET to be TRUE and other signals to be
217 * FALSE.
218 */
219 term = INB(np, nc_sstat0);
220 term = ((term & 2) << 7) + ((term & 1) << 17); /* rst sdp0 */
221 term |= ((INB(np, nc_sstat2) & 0x01) << 26) | /* sdp1 */
222 ((INW(np, nc_sbdl) & 0xff) << 9) | /* d7-0 */
223 ((INW(np, nc_sbdl) & 0xff00) << 10) | /* d15-8 */
224 INB(np, nc_sbcl); /* req ack bsy sel atn msg cd io */
225
226 if (!np->maxwide)
227 term &= 0x3ffff;
228
229 if (term != (2<<7)) {
230 printf("%s: suspicious SCSI data while resetting the BUS.\n",
231 sym_name(np));
232 printf("%s: %sdp0,d7-0,rst,req,ack,bsy,sel,atn,msg,c/d,i/o = "
233 "0x%lx, expecting 0x%lx\n",
234 sym_name(np),
235 (np->features & FE_WIDE) ? "dp1,d15-8," : "",
236 (u_long)term, (u_long)(2<<7));
237 if (SYM_SETUP_SCSI_BUS_CHECK == 1)
238 retv = 1;
239 }
240out:
241 OUTB(np, nc_scntl1, 0);
242 return retv;
243}
244
245/*
246 * Select SCSI clock frequency
247 */
248static void sym_selectclock(struct sym_hcb *np, u_char scntl3)
249{
250 /*
251 * If multiplier not present or not selected, leave here.
252 */
253 if (np->multiplier <= 1) {
254 OUTB(np, nc_scntl3, scntl3);
255 return;
256 }
257
258 if (sym_verbose >= 2)
259 printf ("%s: enabling clock multiplier\n", sym_name(np));
260
261 OUTB(np, nc_stest1, DBLEN); /* Enable clock multiplier */
262 /*
263 * Wait for the LCKFRQ bit to be set if supported by the chip.
264 * Otherwise wait 50 micro-seconds (at least).
265 */
266 if (np->features & FE_LCKFRQ) {
267 int i = 20;
268 while (!(INB(np, nc_stest4) & LCKFRQ) && --i > 0)
269 udelay(20);
270 if (!i)
271 printf("%s: the chip cannot lock the frequency\n",
272 sym_name(np));
53222b90
MW		 273 } else {
274 INB(np, nc_mbox1);
275 udelay(50+10);
276 }
1da177e4
LT		 277 OUTB(np, nc_stest3, HSC); /* Halt the scsi clock */
278 OUTB(np, nc_scntl3, scntl3);
279 OUTB(np, nc_stest1, (DBLEN|DBLSEL));/* Select clock multiplier */
280 OUTB(np, nc_stest3, 0x00); /* Restart scsi clock */
281}
282
283
284/*
285 * Determine the chip's clock frequency.
286 *
287 * This is essential for the negotiation of the synchronous
288 * transfer rate.
289 *
290 * Note: we have to return the correct value.
291 * THERE IS NO SAFE DEFAULT VALUE.
292 *
293 * Most NCR/SYMBIOS boards are delivered with a 40 Mhz clock.
294 * 53C860 and 53C875 rev. 1 support fast20 transfers but
295 * do not have a clock doubler and so are provided with a
296 * 80 MHz clock. All other fast20 boards incorporate a doubler
297 * and so should be delivered with a 40 MHz clock.
298 * The recent fast40 chips (895/896/895A/1010) use a 40 Mhz base
299 * clock and provide a clock quadrupler (160 Mhz).
300 */
301
302/*
303 * calculate SCSI clock frequency (in KHz)
304 */
305static unsigned getfreq (struct sym_hcb *np, int gen)
306{
307 unsigned int ms = 0;
308 unsigned int f;
309
310 /*
311 * Measure GEN timer delay in order
312 * to calculate SCSI clock frequency
313 *
314 * This code will never execute too
315 * many loop iterations (if DELAY is
316 * reasonably correct). It could get
317 * too low a delay (too high a freq.)
318 * if the CPU is slow executing the
319 * loop for some reason (an NMI, for
320 * example). For this reason we will
321 * if multiple measurements are to be
322 * performed trust the higher delay
323 * (lower frequency returned).
324 */
325 OUTW(np, nc_sien, 0); /* mask all scsi interrupts */
326 INW(np, nc_sist); /* clear pending scsi interrupt */
327 OUTB(np, nc_dien, 0); /* mask all dma interrupts */
328 INW(np, nc_sist); /* another one, just to be sure :) */
329 /*
330 * The C1010-33 core does not report GEN in SIST,
331 * if this interrupt is masked in SIEN.
332 * I don't know yet if the C1010-66 behaves the same way.
333 */
334 if (np->features & FE_C10) {
335 OUTW(np, nc_sien, GEN);
336 OUTB(np, nc_istat1, SIRQD);
337 }
338 OUTB(np, nc_scntl3, 4); /* set pre-scaler to divide by 3 */
339 OUTB(np, nc_stime1, 0); /* disable general purpose timer */
340 OUTB(np, nc_stime1, gen); /* set to nominal delay of 1<<gen * 125us */
341 while (!(INW(np, nc_sist) & GEN) && ms++ < 100000)
342 udelay(1000/4); /* count in 1/4 of ms */
343 OUTB(np, nc_stime1, 0); /* disable general purpose timer */
344 /*
345 * Undo C1010-33 specific settings.
346 */
347 if (np->features & FE_C10) {
348 OUTW(np, nc_sien, 0);
349 OUTB(np, nc_istat1, 0);
350 }
351 /*
352 * set prescaler to divide by whatever 0 means
353 * 0 ought to choose divide by 2, but appears
354 * to set divide by 3.5 mode in my 53c810 ...
355 */
356 OUTB(np, nc_scntl3, 0);
357
358 /*
359 * adjust for prescaler, and convert into KHz
360 */
361 f = ms ? ((1 << gen) * (4340*4)) / ms : 0;
362
363 /*
364 * The C1010-33 result is biased by a factor
365 * of 2/3 compared to earlier chips.
366 */
367 if (np->features & FE_C10)
368 f = (f * 2) / 3;
369
370 if (sym_verbose >= 2)
371 printf ("%s: Delay (GEN=%d): %u msec, %u KHz\n",
372 sym_name(np), gen, ms/4, f);
373
374 return f;
375}
376
377static unsigned sym_getfreq (struct sym_hcb *np)
378{
379 u_int f1, f2;
380 int gen = 8;
381
382 getfreq (np, gen); /* throw away first result */
383 f1 = getfreq (np, gen);
384 f2 = getfreq (np, gen);
385 if (f1 > f2) f1 = f2; /* trust lower result */
386 return f1;
387}
388
389/*
390 * Get/probe chip SCSI clock frequency
391 */
392static void sym_getclock (struct sym_hcb *np, int mult)
393{
394 unsigned char scntl3 = np->sv_scntl3;
395 unsigned char stest1 = np->sv_stest1;
396 unsigned f1;
397
398 np->multiplier = 1;
399 f1 = 40000;
400 /*
401 * True with 875/895/896/895A with clock multiplier selected
402 */
403 if (mult > 1 && (stest1 & (DBLEN+DBLSEL)) == DBLEN+DBLSEL) {
404 if (sym_verbose >= 2)
405 printf ("%s: clock multiplier found\n", sym_name(np));
406 np->multiplier = mult;
407 }
408
409 /*
410 * If multiplier not found or scntl3 not 7,5,3,
411 * reset chip and get frequency from general purpose timer.
412 * Otherwise trust scntl3 BIOS setting.
413 */
414 if (np->multiplier != mult || (scntl3 & 7) < 3 || !(scntl3 & 1)) {
415 OUTB(np, nc_stest1, 0); /* make sure doubler is OFF */
416 f1 = sym_getfreq (np);
417
418 if (sym_verbose)
419 printf ("%s: chip clock is %uKHz\n", sym_name(np), f1);
420
421 if (f1 < 45000) f1 = 40000;
422 else if (f1 < 55000) f1 = 50000;
423 else f1 = 80000;
424
425 if (f1 < 80000 && mult > 1) {
426 if (sym_verbose >= 2)
427 printf ("%s: clock multiplier assumed\n",
428 sym_name(np));
429 np->multiplier = mult;
430 }
431 } else {
432 if ((scntl3 & 7) == 3) f1 = 40000;
433 else if ((scntl3 & 7) == 5) f1 = 80000;
434 else f1 = 160000;
435
436 f1 /= np->multiplier;
437 }
438
439 /*
440 * Compute controller synchronous parameters.
441 */
442 f1 *= np->multiplier;
443 np->clock_khz = f1;
444}
445
446/*
447 * Get/probe PCI clock frequency
448 */
449static int sym_getpciclock (struct sym_hcb *np)
450{
451 int f = 0;
452
453 /*
454 * For now, we only need to know about the actual
455 * PCI BUS clock frequency for C1010-66 chips.
456 */
457#if 1
458 if (np->features & FE_66MHZ) {
459#else
460 if (1) {
461#endif
462 OUTB(np, nc_stest1, SCLK); /* Use the PCI clock as SCSI clock */
463 f = sym_getfreq(np);
464 OUTB(np, nc_stest1, 0);
465 }
466 np->pciclk_khz = f;
467
468 return f;
469}
470
471/*
472 * SYMBIOS chip clock divisor table.
473 *
474 * Divisors are multiplied by 10,000,000 in order to make
475 * calculations more simple.
476 */
477#define _5M 5000000
76789f01 478static const u32 div_10M[] = {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M};
1da177e4
LT		 479
480/*
481 * Get clock factor and sync divisor for a given
482 * synchronous factor period.
483 */
484static int
485sym_getsync(struct sym_hcb *np, u_char dt, u_char sfac, u_char *divp, u_char *fakp)
486{
487 u32 clk = np->clock_khz; /* SCSI clock frequency in kHz */
488 int div = np->clock_divn; /* Number of divisors supported */
489 u32 fak; /* Sync factor in sxfer */
490 u32 per; /* Period in tenths of ns */
491 u32 kpc; /* (per * clk) */
492 int ret;
493
494 /*
495 * Compute the synchronous period in tenths of nano-seconds
496 */
497 if (dt && sfac <= 9) per = 125;
498 else if (sfac <= 10) per = 250;
499 else if (sfac == 11) per = 303;
500 else if (sfac == 12) per = 500;
501 else per = 40 * sfac;
502 ret = per;
503
504 kpc = per * clk;
505 if (dt)
506 kpc <<= 1;
507
508 /*
509 * For earliest C10 revision 0, we cannot use extra
510 * clocks for the setting of the SCSI clocking.
511 * Note that this limits the lowest sync data transfer
512 * to 5 Mega-transfers per second and may result in
513 * using higher clock divisors.
514 */
515#if 1
516 if ((np->features & (FE_C10|FE_U3EN)) == FE_C10) {
517 /*
518 * Look for the lowest clock divisor that allows an
519 * output speed not faster than the period.
520 */
521 while (div > 0) {
522 --div;
523 if (kpc > (div_10M[div] << 2)) {
524 ++div;
525 break;
526 }
527 }
528 fak = 0; /* No extra clocks */
529 if (div == np->clock_divn) { /* Are we too fast ? */
530 ret = -1;
531 }
532 *divp = div;
533 *fakp = fak;
534 return ret;
535 }
536#endif
537
538 /*
539 * Look for the greatest clock divisor that allows an
540 * input speed faster than the period.
541 */
542 while (div-- > 0)
543 if (kpc >= (div_10M[div] << 2)) break;
544
545 /*
546 * Calculate the lowest clock factor that allows an output
547 * speed not faster than the period, and the max output speed.
548 * If fak >= 1 we will set both XCLKH_ST and XCLKH_DT.
549 * If fak >= 2 we will also set XCLKS_ST and XCLKS_DT.
550 */
551 if (dt) {
552 fak = (kpc - 1) / (div_10M[div] << 1) + 1 - 2;
553 /* ret = ((2+fak)*div_10M[div])/np->clock_khz; */
554 } else {
555 fak = (kpc - 1) / div_10M[div] + 1 - 4;
556 /* ret = ((4+fak)*div_10M[div])/np->clock_khz; */
557 }
558
559 /*
560 * Check against our hardware limits, or bugs :).
561 */
562 if (fak > 2) {
563 fak = 2;
564 ret = -1;
565 }
566
567 /*
568 * Compute and return sync parameters.
569 */
570 *divp = div;
571 *fakp = fak;
572
573 return ret;
574}
575
576/*
577 * SYMBIOS chips allow burst lengths of 2, 4, 8, 16, 32, 64,
578 * 128 transfers. All chips support at least 16 transfers
579 * bursts. The 825A, 875 and 895 chips support bursts of up
580 * to 128 transfers and the 895A and 896 support bursts of up
581 * to 64 transfers. All other chips support up to 16
582 * transfers bursts.
583 *
584 * For PCI 32 bit data transfers each transfer is a DWORD.
585 * It is a QUADWORD (8 bytes) for PCI 64 bit data transfers.
586 *
587 * We use log base 2 (burst length) as internal code, with
588 * value 0 meaning "burst disabled".
589 */
590
591/*
592 * Burst length from burst code.
593 */
594#define burst_length(bc) (!(bc))? 0 : 1 << (bc)
595
596/*
597 * Burst code from io register bits.
598 */
599#define burst_code(dmode, ctest4, ctest5) \
600 (ctest4) & 0x80? 0 : (((dmode) & 0xc0) >> 6) + ((ctest5) & 0x04) + 1
601
602/*
603 * Set initial io register bits from burst code.
604 */
605static __inline void sym_init_burst(struct sym_hcb *np, u_char bc)
606{
607 np->rv_ctest4 &= ~0x80;
608 np->rv_dmode &= ~(0x3 << 6);
609 np->rv_ctest5 &= ~0x4;
610
611 if (!bc) {
612 np->rv_ctest4 |= 0x80;
613 }
614 else {
615 --bc;
616 np->rv_dmode |= ((bc & 0x3) << 6);
617 np->rv_ctest5 |= (bc & 0x4);
618 }
619}
620
1da177e4
LT		 621/*
622 * Save initial settings of some IO registers.
623 * Assumed to have been set by BIOS.
624 * We cannot reset the chip prior to reading the
625 * IO registers, since informations will be lost.
626 * Since the SCRIPTS processor may be running, this
627 * is not safe on paper, but it seems to work quite
628 * well. :)
629 */
630static void sym_save_initial_setting (struct sym_hcb *np)
631{
632 np->sv_scntl0 = INB(np, nc_scntl0) & 0x0a;
633 np->sv_scntl3 = INB(np, nc_scntl3) & 0x07;
634 np->sv_dmode = INB(np, nc_dmode) & 0xce;
635 np->sv_dcntl = INB(np, nc_dcntl) & 0xa8;
636 np->sv_ctest3 = INB(np, nc_ctest3) & 0x01;
637 np->sv_ctest4 = INB(np, nc_ctest4) & 0x80;
638 np->sv_gpcntl = INB(np, nc_gpcntl);
639 np->sv_stest1 = INB(np, nc_stest1);
640 np->sv_stest2 = INB(np, nc_stest2) & 0x20;
641 np->sv_stest4 = INB(np, nc_stest4);
642 if (np->features & FE_C10) { /* Always large DMA fifo + ultra3 */
643 np->sv_scntl4 = INB(np, nc_scntl4);
644 np->sv_ctest5 = INB(np, nc_ctest5) & 0x04;
645 }
646 else
647 np->sv_ctest5 = INB(np, nc_ctest5) & 0x24;
648}
649
c2349df9
MW		 650/*
651 * Set SCSI BUS mode.
652 * - LVD capable chips (895/895A/896/1010) report the current BUS mode
653 * through the STEST4 IO register.
654 * - For previous generation chips (825/825A/875), the user has to tell us
655 * how to check against HVD, since a 100% safe algorithm is not possible.
656 */
657static void sym_set_bus_mode(struct sym_hcb *np, struct sym_nvram *nvram)
658{
659 if (np->scsi_mode)
660 return;
661
662 np->scsi_mode = SMODE_SE;
663 if (np->features & (FE_ULTRA2|FE_ULTRA3))
664 np->scsi_mode = (np->sv_stest4 & SMODE);
665 else if (np->features & FE_DIFF) {
666 if (SYM_SETUP_SCSI_DIFF == 1) {
667 if (np->sv_scntl3) {
668 if (np->sv_stest2 & 0x20)
669 np->scsi_mode = SMODE_HVD;
670 } else if (nvram->type == SYM_SYMBIOS_NVRAM) {
671 if (!(INB(np, nc_gpreg) & 0x08))
672 np->scsi_mode = SMODE_HVD;
673 }
674 } else if (SYM_SETUP_SCSI_DIFF == 2)
675 np->scsi_mode = SMODE_HVD;
676 }
677 if (np->scsi_mode == SMODE_HVD)
678 np->rv_stest2 |= 0x20;
679}
680
1da177e4
LT		 681/*
682 * Prepare io register values used by sym_start_up()
683 * according to selected and supported features.
684 */
685static int sym_prepare_setting(struct Scsi_Host *shost, struct sym_hcb *np, struct sym_nvram *nvram)
686{
687 u_char burst_max;
688 u32 period;
689 int i;
690
c2349df9 691 np->maxwide = (np->features & FE_WIDE) ? 1 : 0;
1da177e4
LT		 692
693 /*
694 * Guess the frequency of the chip's clock.
695 */
696 if (np->features & (FE_ULTRA3 | FE_ULTRA2))
697 np->clock_khz = 160000;
698 else if (np->features & FE_ULTRA)
699 np->clock_khz = 80000;
700 else
701 np->clock_khz = 40000;
702
703 /*
704 * Get the clock multiplier factor.
705 */
706 if (np->features & FE_QUAD)
707 np->multiplier = 4;
708 else if (np->features & FE_DBLR)
709 np->multiplier = 2;
710 else
711 np->multiplier = 1;
712
713 /*
714 * Measure SCSI clock frequency for chips
715 * it may vary from assumed one.
716 */
717 if (np->features & FE_VARCLK)
718 sym_getclock(np, np->multiplier);
719
720 /*
721 * Divisor to be used for async (timer pre-scaler).
722 */
723 i = np->clock_divn - 1;
724 while (--i >= 0) {
725 if (10ul * SYM_CONF_MIN_ASYNC * np->clock_khz > div_10M[i]) {
726 ++i;
727 break;
728 }
729 }
730 np->rv_scntl3 = i+1;
731
732 /*
733 * The C1010 uses hardwired divisors for async.
734 * So, we just throw away, the async. divisor.:-)
735 */
736 if (np->features & FE_C10)
737 np->rv_scntl3 = 0;
738
739 /*
740 * Minimum synchronous period factor supported by the chip.
741 * Btw, 'period' is in tenths of nanoseconds.
742 */
743 period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz;
744
745 if (period <= 250) np->minsync = 10;
746 else if (period <= 303) np->minsync = 11;
747 else if (period <= 500) np->minsync = 12;
748 else np->minsync = (period + 40 - 1) / 40;
749
750 /*
751 * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2).
752 */
753 if (np->minsync < 25 &&
754 !(np->features & (FE_ULTRA|FE_ULTRA2|FE_ULTRA3)))
755 np->minsync = 25;
756 else if (np->minsync < 12 &&
757 !(np->features & (FE_ULTRA2|FE_ULTRA3)))
758 np->minsync = 12;
759
760 /*
761 * Maximum synchronous period factor supported by the chip.
762 */
763 period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz);
764 np->maxsync = period > 2540 ? 254 : period / 10;
765
766 /*
767 * If chip is a C1010, guess the sync limits in DT mode.
768 */
769 if ((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) {
770 if (np->clock_khz == 160000) {
771 np->minsync_dt = 9;
772 np->maxsync_dt = 50;
773 np->maxoffs_dt = nvram->type ? 62 : 31;
774 }
775 }
776
777 /*
778 * 64 bit addressing (895A/896/1010) ?
779 */
780 if (np->features & FE_DAC) {
781#if SYM_CONF_DMA_ADDRESSING_MODE == 0
782 np->rv_ccntl1 |= (DDAC);
783#elif SYM_CONF_DMA_ADDRESSING_MODE == 1
784 if (!np->use_dac)
785 np->rv_ccntl1 |= (DDAC);
786 else
787 np->rv_ccntl1 |= (XTIMOD | EXTIBMV);
788#elif SYM_CONF_DMA_ADDRESSING_MODE == 2
789 if (!np->use_dac)
790 np->rv_ccntl1 |= (DDAC);
791 else
792 np->rv_ccntl1 |= (0 | EXTIBMV);
793#endif
794 }
795
796 /*
797 * Phase mismatch handled by SCRIPTS (895A/896/1010) ?
798 */
799 if (np->features & FE_NOPM)
800 np->rv_ccntl0 |= (ENPMJ);
801
802 /*
803 * C1010-33 Errata: Part Number:609-039638 (rev. 1) is fixed.
804 * In dual channel mode, contention occurs if internal cycles
805 * are used. Disable internal cycles.
806 */
e58bc06e 807 if (np->s.device->device == PCI_DEVICE_ID_LSI_53C1010_33 &&
bd678450 808 np->s.device->revision < 0x1)
1da177e4
LT		 809 np->rv_ccntl0 |= DILS;
810
811 /*
812 * Select burst length (dwords)
813 */
814 burst_max = SYM_SETUP_BURST_ORDER;
815 if (burst_max == 255)
816 burst_max = burst_code(np->sv_dmode, np->sv_ctest4,
817 np->sv_ctest5);
818 if (burst_max > 7)
819 burst_max = 7;
820 if (burst_max > np->maxburst)
821 burst_max = np->maxburst;
822
823 /*
824 * DEL 352 - 53C810 Rev x11 - Part Number 609-0392140 - ITEM 2.
825 * This chip and the 860 Rev 1 may wrongly use PCI cache line
826 * based transactions on LOAD/STORE instructions. So we have
827 * to prevent these chips from using such PCI transactions in
828 * this driver. The generic ncr driver that does not use
829 * LOAD/STORE instructions does not need this work-around.
830 */
e58bc06e 831 if ((np->s.device->device == PCI_DEVICE_ID_NCR_53C810 &&
bd678450 832 np->s.device->revision >= 0x10 && np->s.device->revision <= 0x11) ||
e58bc06e 833 (np->s.device->device == PCI_DEVICE_ID_NCR_53C860 &&
bd678450 834 np->s.device->revision <= 0x1))
1da177e4
LT		 835 np->features &= ~(FE_WRIE|FE_ERL|FE_ERMP);
836
837 /*
838 * Select all supported special features.
839 * If we are using on-board RAM for scripts, prefetch (PFEN)
840 * does not help, but burst op fetch (BOF) does.
841 * Disabling PFEN makes sure BOF will be used.
842 */
843 if (np->features & FE_ERL)
844 np->rv_dmode |= ERL; /* Enable Read Line */
845 if (np->features & FE_BOF)
846 np->rv_dmode |= BOF; /* Burst Opcode Fetch */
847 if (np->features & FE_ERMP)
848 np->rv_dmode |= ERMP; /* Enable Read Multiple */
849#if 1
850 if ((np->features & FE_PFEN) && !np->ram_ba)
851#else
852 if (np->features & FE_PFEN)
853#endif
854 np->rv_dcntl |= PFEN; /* Prefetch Enable */
855 if (np->features & FE_CLSE)
856 np->rv_dcntl |= CLSE; /* Cache Line Size Enable */
857 if (np->features & FE_WRIE)
858 np->rv_ctest3 |= WRIE; /* Write and Invalidate */
859 if (np->features & FE_DFS)
860 np->rv_ctest5 |= DFS; /* Dma Fifo Size */
861
862 /*
863 * Select some other
864 */
865 np->rv_ctest4 |= MPEE; /* Master parity checking */
866 np->rv_scntl0 |= 0x0a; /* full arb., ena parity, par->ATN */
867
868 /*
869 * Get parity checking, host ID and verbose mode from NVRAM
870 */
871 np->myaddr = 255;
c2349df9 872 np->scsi_mode = 0;
1da177e4
LT		 873 sym_nvram_setup_host(shost, np, nvram);
874
875 /*
876 * Get SCSI addr of host adapter (set by bios?).
877 */
878 if (np->myaddr == 255) {
879 np->myaddr = INB(np, nc_scid) & 0x07;
880 if (!np->myaddr)
881 np->myaddr = SYM_SETUP_HOST_ID;
882 }
883
884 /*
885 * Prepare initial io register bits for burst length
886 */
887 sym_init_burst(np, burst_max);
888
c2349df9 889 sym_set_bus_mode(np, nvram);
1da177e4
LT		 890
891 /*
892 * Set LED support from SCRIPTS.
893 * Ignore this feature for boards known to use a
894 * specific GPIO wiring and for the 895A, 896
895 * and 1010 that drive the LED directly.
896 */
897 if ((SYM_SETUP_SCSI_LED ||
898 (nvram->type == SYM_SYMBIOS_NVRAM ||
899 (nvram->type == SYM_TEKRAM_NVRAM &&
e58bc06e 900 np->s.device->device == PCI_DEVICE_ID_NCR_53C895))) &&
1da177e4
LT		 901 !(np->features & FE_LEDC) && !(np->sv_gpcntl & 0x01))
902 np->features |= FE_LED0;
903
904 /*
905 * Set irq mode.
906 */
907 switch(SYM_SETUP_IRQ_MODE & 3) {
908 case 2:
909 np->rv_dcntl |= IRQM;
910 break;
911 case 1:
912 np->rv_dcntl |= (np->sv_dcntl & IRQM);
913 break;
914 default:
915 break;
916 }
917
918 /*
919 * Configure targets according to driver setup.
920 * If NVRAM present get targets setup from NVRAM.
921 */
922 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
923 struct sym_tcb *tp = &np->target[i];
924
925 tp->usrflags |= (SYM_DISC_ENABLED | SYM_TAGS_ENABLED);
926 tp->usrtags = SYM_SETUP_MAX_TAG;
23ff51e9
MW		 927 tp->usr_width = np->maxwide;
928 tp->usr_period = 9;
1da177e4 929
b37df489 930 sym_nvram_setup_target(tp, i, nvram);
1da177e4
LT		 931
932 if (!tp->usrtags)
933 tp->usrflags &= ~SYM_TAGS_ENABLED;
934 }
935
936 /*
937 * Let user know about the settings.
938 */
939 printf("%s: %s, ID %d, Fast-%d, %s, %s\n", sym_name(np),
940 sym_nvram_type(nvram), np->myaddr,
941 (np->features & FE_ULTRA3) ? 80 :
942 (np->features & FE_ULTRA2) ? 40 :
943 (np->features & FE_ULTRA) ? 20 : 10,
944 sym_scsi_bus_mode(np->scsi_mode),
945 (np->rv_scntl0 & 0xa) ? "parity checking" : "NO parity");
946 /*
947 * Tell him more on demand.
948 */
949 if (sym_verbose) {
950 printf("%s: %s IRQ line driver%s\n",
951 sym_name(np),
952 np->rv_dcntl & IRQM ? "totem pole" : "open drain",
953 np->ram_ba ? ", using on-chip SRAM" : "");
954 printf("%s: using %s firmware.\n", sym_name(np), np->fw_name);
955 if (np->features & FE_NOPM)
956 printf("%s: handling phase mismatch from SCRIPTS.\n",
957 sym_name(np));
958 }
959 /*
960 * And still more.
961 */
962 if (sym_verbose >= 2) {
963 printf ("%s: initial SCNTL3/DMODE/DCNTL/CTEST3/4/5 = "
964 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n",
965 sym_name(np), np->sv_scntl3, np->sv_dmode, np->sv_dcntl,
966 np->sv_ctest3, np->sv_ctest4, np->sv_ctest5);
967
968 printf ("%s: final SCNTL3/DMODE/DCNTL/CTEST3/4/5 = "
969 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n",
970 sym_name(np), np->rv_scntl3, np->rv_dmode, np->rv_dcntl,
971 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5);
972 }
1da177e4
LT		 973
974 return 0;
975}
976
977/*
978 * Test the pci bus snoop logic :-(
979 *
980 * Has to be called with interrupts disabled.
981 */
1f61d824
MW		 982#ifdef CONFIG_SCSI_SYM53C8XX_MMIO
983static int sym_regtest(struct sym_hcb *np)
1da177e4
LT		 984{
985 register volatile u32 data;
986 /*
987 * chip registers may NOT be cached.
988 * write 0xffffffff to a read only register area,
989 * and try to read it back.
990 */
991 data = 0xffffffff;
992 OUTL(np, nc_dstat, data);
993 data = INL(np, nc_dstat);
994#if 1
995 if (data == 0xffffffff) {
996#else
997 if ((data & 0xe2f0fffd) != 0x02000080) {
998#endif
999 printf ("CACHE TEST FAILED: reg dstat-sstat2 readback %x.\n",
1000 (unsigned) data);
1f61d824 1001 return 0x10;
1da177e4 1002 }
1f61d824
MW		 1003 return 0;
1004}
1005#else
1006static inline int sym_regtest(struct sym_hcb *np)
1007{
1008 return 0;
1da177e4
LT		 1009}
1010#endif
1011
1f61d824 1012static int sym_snooptest(struct sym_hcb *np)
1da177e4 1013{
1f61d824
MW		 1014 u32 sym_rd, sym_wr, sym_bk, host_rd, host_wr, pc, dstat;
1015 int i, err;
1016
1017 err = sym_regtest(np);
1018 if (err)
1019 return err;
1da177e4
LT		 1020restart_test:
1021 /*
1022 * Enable Master Parity Checking as we intend
1023 * to enable it for normal operations.
1024 */
1025 OUTB(np, nc_ctest4, (np->rv_ctest4 & MPEE));
1026 /*
1027 * init
1028 */
1029 pc = SCRIPTZ_BA(np, snooptest);
1030 host_wr = 1;
1031 sym_wr = 2;
1032 /*
1033 * Set memory and register.
1034 */
1035 np->scratch = cpu_to_scr(host_wr);
1036 OUTL(np, nc_temp, sym_wr);
1037 /*
1038 * Start script (exchange values)
1039 */
1040 OUTL(np, nc_dsa, np->hcb_ba);
1041 OUTL_DSP(np, pc);
1042 /*
1043 * Wait 'til done (with timeout)
1044 */
1045 for (i=0; i<SYM_SNOOP_TIMEOUT; i++)
1046 if (INB(np, nc_istat) & (INTF|SIP|DIP))
1047 break;
1048 if (i>=SYM_SNOOP_TIMEOUT) {
1049 printf ("CACHE TEST FAILED: timeout.\n");
1050 return (0x20);
1051 }
1052 /*
1053 * Check for fatal DMA errors.
1054 */
1055 dstat = INB(np, nc_dstat);
1056#if 1 /* Band aiding for broken hardwares that fail PCI parity */
1057 if ((dstat & MDPE) && (np->rv_ctest4 & MPEE)) {
1058 printf ("%s: PCI DATA PARITY ERROR DETECTED - "
1059 "DISABLING MASTER DATA PARITY CHECKING.\n",
1060 sym_name(np));
1061 np->rv_ctest4 &= ~MPEE;
1062 goto restart_test;
1063 }
1064#endif
1065 if (dstat & (MDPE|BF|IID)) {
1066 printf ("CACHE TEST FAILED: DMA error (dstat=0x%02x).", dstat);
1067 return (0x80);
1068 }
1069 /*
1070 * Save termination position.
1071 */
1072 pc = INL(np, nc_dsp);
1073 /*
1074 * Read memory and register.
1075 */
1076 host_rd = scr_to_cpu(np->scratch);
1077 sym_rd = INL(np, nc_scratcha);
1078 sym_bk = INL(np, nc_temp);
1079 /*
1080 * Check termination position.
1081 */
1082 if (pc != SCRIPTZ_BA(np, snoopend)+8) {
1083 printf ("CACHE TEST FAILED: script execution failed.\n");
1084 printf ("start=%08lx, pc=%08lx, end=%08lx\n",
1085 (u_long) SCRIPTZ_BA(np, snooptest), (u_long) pc,
1086 (u_long) SCRIPTZ_BA(np, snoopend) +8);
1087 return (0x40);
1088 }
1089 /*
1090 * Show results.
1091 */
1092 if (host_wr != sym_rd) {
1093 printf ("CACHE TEST FAILED: host wrote %d, chip read %d.\n",
1094 (int) host_wr, (int) sym_rd);
1095 err |= 1;
1096 }
1097 if (host_rd != sym_wr) {
1098 printf ("CACHE TEST FAILED: chip wrote %d, host read %d.\n",
1099 (int) sym_wr, (int) host_rd);
1100 err |= 2;
1101 }
1102 if (sym_bk != sym_wr) {
1103 printf ("CACHE TEST FAILED: chip wrote %d, read back %d.\n",
1104 (int) sym_wr, (int) sym_bk);
1105 err |= 4;
1106 }
1107
1f61d824 1108 return err;
1da177e4
LT		 1109}
1110
1111/*
1112 * log message for real hard errors
1113 *
1114 * sym0 targ 0?: ERROR (ds:si) (so-si-sd) (sx/s3/s4) @ name (dsp:dbc).
1115 * reg: r0 r1 r2 r3 r4 r5 r6 ..... rf.
1116 *
1117 * exception register:
1118 * ds: dstat
1119 * si: sist
1120 *
1121 * SCSI bus lines:
1122 * so: control lines as driven by chip.
1123 * si: control lines as seen by chip.
1124 * sd: scsi data lines as seen by chip.
1125 *
1126 * wide/fastmode:
1127 * sx: sxfer (see the manual)
1128 * s3: scntl3 (see the manual)
1129 * s4: scntl4 (see the manual)
1130 *
1131 * current script command:
1132 * dsp: script address (relative to start of script).
1133 * dbc: first word of script command.
1134 *
1135 * First 24 register of the chip:
1136 * r0..rf
1137 */
1138static void sym_log_hard_error(struct sym_hcb *np, u_short sist, u_char dstat)
1139{
1140 u32 dsp;
1141 int script_ofs;
1142 int script_size;
1143 char *script_name;
1144 u_char *script_base;
1145 int i;
1146
1147 dsp = INL(np, nc_dsp);
1148
1149 if (dsp > np->scripta_ba &&
1150 dsp <= np->scripta_ba + np->scripta_sz) {
1151 script_ofs = dsp - np->scripta_ba;
1152 script_size = np->scripta_sz;
1153 script_base = (u_char *) np->scripta0;
1154 script_name = "scripta";
1155 }
1156 else if (np->scriptb_ba < dsp &&
1157 dsp <= np->scriptb_ba + np->scriptb_sz) {
1158 script_ofs = dsp - np->scriptb_ba;
1159 script_size = np->scriptb_sz;
1160 script_base = (u_char *) np->scriptb0;
1161 script_name = "scriptb";
1162 } else {
1163 script_ofs = dsp;
1164 script_size = 0;
1165 script_base = NULL;
1166 script_name = "mem";
1167 }
1168
1169 printf ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x/%x) @ (%s %x:%08x).\n",
1170 sym_name(np), (unsigned)INB(np, nc_sdid)&0x0f, dstat, sist,
1171 (unsigned)INB(np, nc_socl), (unsigned)INB(np, nc_sbcl),
1172 (unsigned)INB(np, nc_sbdl), (unsigned)INB(np, nc_sxfer),
1173 (unsigned)INB(np, nc_scntl3),
1174 (np->features & FE_C10) ? (unsigned)INB(np, nc_scntl4) : 0,
1175 script_name, script_ofs, (unsigned)INL(np, nc_dbc));
1176
1177 if (((script_ofs & 3) == 0) &&
1178 (unsigned)script_ofs < script_size) {
1179 printf ("%s: script cmd = %08x\n", sym_name(np),
1180 scr_to_cpu((int) *(u32 *)(script_base + script_ofs)));
1181 }
1182
d68cd759
LV		 1183 printf("%s: regdump:", sym_name(np));
1184 for (i = 0; i < 24; i++)
1185 printf(" %02x", (unsigned)INB_OFF(np, i));
1186 printf(".\n");
1da177e4
LT		 1187
1188 /*
1189 * PCI BUS error.
1190 */
1191 if (dstat & (MDPE|BF))
1192 sym_log_bus_error(np);
1193}
1194
d68cd759
LV		 1195void sym_dump_registers(struct sym_hcb *np)
1196{
1197 u_short sist;
1198 u_char dstat;
1199
1200 sist = INW(np, nc_sist);
1201 dstat = INB(np, nc_dstat);
1202 sym_log_hard_error(np, sist, dstat);
1203}
1204
1da177e4
LT		 1205static struct sym_chip sym_dev_table[] = {
1206 {PCI_DEVICE_ID_NCR_53C810, 0x0f, "810", 4, 8, 4, 64,
1207 FE_ERL}
1208 ,
1209#ifdef SYM_DEBUG_GENERIC_SUPPORT
1210 {PCI_DEVICE_ID_NCR_53C810, 0xff, "810a", 4, 8, 4, 1,
1211 FE_BOF}
1212 ,
1213#else
1214 {PCI_DEVICE_ID_NCR_53C810, 0xff, "810a", 4, 8, 4, 1,
1215 FE_CACHE_SET|FE_LDSTR|FE_PFEN|FE_BOF}
1216 ,
1217#endif
1218 {PCI_DEVICE_ID_NCR_53C815, 0xff, "815", 4, 8, 4, 64,
1219 FE_BOF|FE_ERL}
1220 ,
1221 {PCI_DEVICE_ID_NCR_53C825, 0x0f, "825", 6, 8, 4, 64,
1222 FE_WIDE|FE_BOF|FE_ERL|FE_DIFF}
1223 ,
1224 {PCI_DEVICE_ID_NCR_53C825, 0xff, "825a", 6, 8, 4, 2,
1225 FE_WIDE|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM|FE_DIFF}
1226 ,
1227 {PCI_DEVICE_ID_NCR_53C860, 0xff, "860", 4, 8, 5, 1,
1228 FE_ULTRA|FE_CACHE_SET|FE_BOF|FE_LDSTR|FE_PFEN}
1229 ,
1230 {PCI_DEVICE_ID_NCR_53C875, 0x01, "875", 6, 16, 5, 2,
1231 FE_WIDE|FE_ULTRA|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1232 FE_RAM|FE_DIFF|FE_VARCLK}
1233 ,
1234 {PCI_DEVICE_ID_NCR_53C875, 0xff, "875", 6, 16, 5, 2,
1235 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1236 FE_RAM|FE_DIFF|FE_VARCLK}
1237 ,
1238 {PCI_DEVICE_ID_NCR_53C875J, 0xff, "875J", 6, 16, 5, 2,
1239 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1240 FE_RAM|FE_DIFF|FE_VARCLK}
1241 ,
1242 {PCI_DEVICE_ID_NCR_53C885, 0xff, "885", 6, 16, 5, 2,
1243 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1244 FE_RAM|FE_DIFF|FE_VARCLK}
1245 ,
1246#ifdef SYM_DEBUG_GENERIC_SUPPORT
1247 {PCI_DEVICE_ID_NCR_53C895, 0xff, "895", 6, 31, 7, 2,
1248 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|
1249 FE_RAM|FE_LCKFRQ}
1250 ,
1251#else
1252 {PCI_DEVICE_ID_NCR_53C895, 0xff, "895", 6, 31, 7, 2,
1253 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1254 FE_RAM|FE_LCKFRQ}
1255 ,
1256#endif
1257 {PCI_DEVICE_ID_NCR_53C896, 0xff, "896", 6, 31, 7, 4,
1258 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1259 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ}
1260 ,
1261 {PCI_DEVICE_ID_LSI_53C895A, 0xff, "895a", 6, 31, 7, 4,
1262 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1263 FE_RAM|FE_RAM8K|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ}
1264 ,
1265 {PCI_DEVICE_ID_LSI_53C875A, 0xff, "875a", 6, 31, 7, 4,
1266 FE_WIDE|FE_ULTRA|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1267 FE_RAM|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ}
1268 ,
1269 {PCI_DEVICE_ID_LSI_53C1010_33, 0x00, "1010-33", 6, 31, 7, 8,
1270 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN|
1271 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC|
1272 FE_C10}
1273 ,
1274 {PCI_DEVICE_ID_LSI_53C1010_33, 0xff, "1010-33", 6, 31, 7, 8,
1275 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN|
1276 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC|
1277 FE_C10|FE_U3EN}
1278 ,
1279 {PCI_DEVICE_ID_LSI_53C1010_66, 0xff, "1010-66", 6, 31, 7, 8,
1280 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN|
1281 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_66MHZ|FE_CRC|
1282 FE_C10|FE_U3EN}
1283 ,
1284 {PCI_DEVICE_ID_LSI_53C1510, 0xff, "1510d", 6, 31, 7, 4,
1285 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1286 FE_RAM|FE_IO256|FE_LEDC}
1287};
1288
6391a113 1289#define sym_num_devs (ARRAY_SIZE(sym_dev_table))
1da177e4
LT		 1290
1291/*
1292 * Look up the chip table.
1293 *
1294 * Return a pointer to the chip entry if found,
1295 * zero otherwise.
1296 */
1297struct sym_chip *
1298sym_lookup_chip_table (u_short device_id, u_char revision)
1299{
1300 struct sym_chip *chip;
1301 int i;
1302
1303 for (i = 0; i < sym_num_devs; i++) {
1304 chip = &sym_dev_table[i];
1305 if (device_id != chip->device_id)
1306 continue;
1307 if (revision > chip->revision_id)
1308 continue;
1309 return chip;
1310 }
1311
1312 return NULL;
1313}
1314
1315#if SYM_CONF_DMA_ADDRESSING_MODE == 2
1316/*
1317 * Lookup the 64 bit DMA segments map.
1318 * This is only used if the direct mapping
1319 * has been unsuccessful.
1320 */
1321int sym_lookup_dmap(struct sym_hcb *np, u32 h, int s)
1322{
1323 int i;
1324
1325 if (!np->use_dac)
1326 goto weird;
1327
1328 /* Look up existing mappings */
1329 for (i = SYM_DMAP_SIZE-1; i > 0; i--) {
1330 if (h == np->dmap_bah[i])
1331 return i;
1332 }
1333 /* If direct mapping is free, get it */
1334 if (!np->dmap_bah[s])
1335 goto new;
1336 /* Collision -> lookup free mappings */
1337 for (s = SYM_DMAP_SIZE-1; s > 0; s--) {
1338 if (!np->dmap_bah[s])
1339 goto new;
1340 }
1341weird:
1342 panic("sym: ran out of 64 bit DMA segment registers");
1343 return -1;
1344new:
1345 np->dmap_bah[s] = h;
1346 np->dmap_dirty = 1;
1347 return s;
1348}
1349
1350/*
1351 * Update IO registers scratch C..R so they will be
1352 * in sync. with queued CCB expectations.
1353 */
1354static void sym_update_dmap_regs(struct sym_hcb *np)
1355{
1356 int o, i;
1357
1358 if (!np->dmap_dirty)
1359 return;
1360 o = offsetof(struct sym_reg, nc_scrx[0]);
1361 for (i = 0; i < SYM_DMAP_SIZE; i++) {
1362 OUTL_OFF(np, o, np->dmap_bah[i]);
1363 o += 4;
1364 }
1365 np->dmap_dirty = 0;
1366}
1367#endif
1368
1369/* Enforce all the fiddly SPI rules and the chip limitations */
1370static void sym_check_goals(struct sym_hcb *np, struct scsi_target *starget,
1371 struct sym_trans *goal)
1372{
1373 if (!spi_support_wide(starget))
1374 goal->width = 0;
1375
1376 if (!spi_support_sync(starget)) {
1377 goal->iu = 0;
1378 goal->dt = 0;
1379 goal->qas = 0;
1da177e4
LT		 1380 goal->offset = 0;
1381 return;
1382 }
1383
1384 if (spi_support_dt(starget)) {
1385 if (spi_support_dt_only(starget))
1386 goal->dt = 1;
1387
1388 if (goal->offset == 0)
1389 goal->dt = 0;
1390 } else {
1391 goal->dt = 0;
1392 }
1393
1394 /* Some targets fail to properly negotiate DT in SE mode */
1395 if ((np->scsi_mode != SMODE_LVD) || !(np->features & FE_U3EN))
1396 goal->dt = 0;
1397
1398 if (goal->dt) {
1399 /* all DT transfers must be wide */
1400 goal->width = 1;
1401 if (goal->offset > np->maxoffs_dt)
1402 goal->offset = np->maxoffs_dt;
1403 if (goal->period < np->minsync_dt)
1404 goal->period = np->minsync_dt;
1405 if (goal->period > np->maxsync_dt)
1406 goal->period = np->maxsync_dt;
1407 } else {
1408 goal->iu = goal->qas = 0;
1409 if (goal->offset > np->maxoffs)
1410 goal->offset = np->maxoffs;
1411 if (goal->period < np->minsync)
1412 goal->period = np->minsync;
1413 if (goal->period > np->maxsync)
1414 goal->period = np->maxsync;
1415 }
1416}
1417
1418/*
1419 * Prepare the next negotiation message if needed.
1420 *
1421 * Fill in the part of message buffer that contains the
1422 * negotiation and the nego_status field of the CCB.
1423 * Returns the size of the message in bytes.
1424 */
1425static int sym_prepare_nego(struct sym_hcb *np, struct sym_ccb *cp, u_char *msgptr)
1426{
1427 struct sym_tcb *tp = &np->target[cp->target];
53222b90 1428 struct scsi_target *starget = tp->starget;
1da177e4
LT		 1429 struct sym_trans *goal = &tp->tgoal;
1430 int msglen = 0;
1431 int nego;
1432
1433 sym_check_goals(np, starget, goal);
1434
1435 /*
1436 * Many devices implement PPR in a buggy way, so only use it if we
1437 * really want to.
1438 */
322e079f
MW		 1439 if (goal->offset &&
1440 (goal->iu || goal->dt || goal->qas || (goal->period < 0xa))) {
1da177e4
LT		 1441 nego = NS_PPR;
1442 } else if (spi_width(starget) != goal->width) {
1443 nego = NS_WIDE;
1444 } else if (spi_period(starget) != goal->period ||
1445 spi_offset(starget) != goal->offset) {
1446 nego = NS_SYNC;
1447 } else {
1448 goal->check_nego = 0;
1449 nego = 0;
1450 }
1451
1452 switch (nego) {
1453 case NS_SYNC:
6ea3c0b2
MW		 1454 msglen += spi_populate_sync_msg(msgptr + msglen, goal->period,
1455 goal->offset);
1da177e4
LT		 1456 break;
1457 case NS_WIDE:
6ea3c0b2 1458 msglen += spi_populate_width_msg(msgptr + msglen, goal->width);
1da177e4
LT		 1459 break;
1460 case NS_PPR:
6ea3c0b2
MW		 1461 msglen += spi_populate_ppr_msg(msgptr + msglen, goal->period,
1462 goal->offset, goal->width,
1463 (goal->iu ? PPR_OPT_IU : 0) |
1da177e4 1464 (goal->dt ? PPR_OPT_DT : 0) |
6ea3c0b2 1465 (goal->qas ? PPR_OPT_QAS : 0));
1da177e4
LT		 1466 break;
1467 }
1468
1469 cp->nego_status = nego;
1470
1471 if (nego) {
1472 tp->nego_cp = cp; /* Keep track a nego will be performed */
1473 if (DEBUG_FLAGS & DEBUG_NEGO) {
1474 sym_print_nego_msg(np, cp->target,
1475 nego == NS_SYNC ? "sync msgout" :
1476 nego == NS_WIDE ? "wide msgout" :
1477 "ppr msgout", msgptr);
1478 }
1479 }
1480
1481 return msglen;
1482}
1483
1484/*
1485 * Insert a job into the start queue.
1486 */
3bea15a7 1487void sym_put_start_queue(struct sym_hcb *np, struct sym_ccb *cp)
1da177e4
LT		 1488{
1489 u_short qidx;
1490
1491#ifdef SYM_CONF_IARB_SUPPORT
1492 /*
1493 * If the previously queued CCB is not yet done,
1494 * set the IARB hint. The SCRIPTS will go with IARB
1495 * for this job when starting the previous one.
1496 * We leave devices a chance to win arbitration by
1497 * not using more than 'iarb_max' consecutive
1498 * immediate arbitrations.
1499 */
1500 if (np->last_cp && np->iarb_count < np->iarb_max) {
1501 np->last_cp->host_flags |= HF_HINT_IARB;
1502 ++np->iarb_count;
1503 }
1504 else
1505 np->iarb_count = 0;
1506 np->last_cp = cp;
1507#endif
1508
1509#if SYM_CONF_DMA_ADDRESSING_MODE == 2
1510 /*
1511 * Make SCRIPTS aware of the 64 bit DMA
1512 * segment registers not being up-to-date.
1513 */
1514 if (np->dmap_dirty)
1515 cp->host_xflags |= HX_DMAP_DIRTY;
1516#endif
1517
1518 /*
1519 * Insert first the idle task and then our job.
1520 * The MBs should ensure proper ordering.
1521 */
1522 qidx = np->squeueput + 2;
1523 if (qidx >= MAX_QUEUE*2) qidx = 0;
1524
1525 np->squeue [qidx] = cpu_to_scr(np->idletask_ba);
1526 MEMORY_WRITE_BARRIER();
1527 np->squeue [np->squeueput] = cpu_to_scr(cp->ccb_ba);
1528
1529 np->squeueput = qidx;
1530
1531 if (DEBUG_FLAGS & DEBUG_QUEUE)
1532 printf ("%s: queuepos=%d.\n", sym_name (np), np->squeueput);
1533
1534 /*
1535 * Script processor may be waiting for reselect.
1536 * Wake it up.
1537 */
1538 MEMORY_WRITE_BARRIER();
1539 OUTB(np, nc_istat, SIGP|np->istat_sem);
1540}
1541
1542#ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
1543/*
1544 * Start next ready-to-start CCBs.
1545 */
1546void sym_start_next_ccbs(struct sym_hcb *np, struct sym_lcb *lp, int maxn)
1547{
1548 SYM_QUEHEAD *qp;
1549 struct sym_ccb *cp;
1550
1551 /*
1552 * Paranoia, as usual. :-)
1553 */
1554 assert(!lp->started_tags || !lp->started_no_tag);
1555
1556 /*
1557 * Try to start as many commands as asked by caller.
1558 * Prevent from having both tagged and untagged
1559 * commands queued to the device at the same time.
1560 */
1561 while (maxn--) {
1562 qp = sym_remque_head(&lp->waiting_ccbq);
1563 if (!qp)
1564 break;
1565 cp = sym_que_entry(qp, struct sym_ccb, link2_ccbq);
1566 if (cp->tag != NO_TAG) {
1567 if (lp->started_no_tag ||
1568 lp->started_tags >= lp->started_max) {
1569 sym_insque_head(qp, &lp->waiting_ccbq);
1570 break;
1571 }
1572 lp->itlq_tbl[cp->tag] = cpu_to_scr(cp->ccb_ba);
1573 lp->head.resel_sa =
1574 cpu_to_scr(SCRIPTA_BA(np, resel_tag));
1575 ++lp->started_tags;
1576 } else {
1577 if (lp->started_no_tag || lp->started_tags) {
1578 sym_insque_head(qp, &lp->waiting_ccbq);
1579 break;
1580 }
1581 lp->head.itl_task_sa = cpu_to_scr(cp->ccb_ba);
1582 lp->head.resel_sa =
1583 cpu_to_scr(SCRIPTA_BA(np, resel_no_tag));
1584 ++lp->started_no_tag;
1585 }
1586 cp->started = 1;
1587 sym_insque_tail(qp, &lp->started_ccbq);
1588 sym_put_start_queue(np, cp);
1589 }
1590}
1591#endif /* SYM_OPT_HANDLE_DEVICE_QUEUEING */
1592
1593/*
1594 * The chip may have completed jobs. Look at the DONE QUEUE.
1595 *
1596 * On paper, memory read barriers may be needed here to
1597 * prevent out of order LOADs by the CPU from having
1598 * prefetched stale data prior to DMA having occurred.
1599 */
1600static int sym_wakeup_done (struct sym_hcb *np)
1601{
1602 struct sym_ccb *cp;
1603 int i, n;
1604 u32 dsa;
1605
1606 n = 0;
1607 i = np->dqueueget;
1608
1609 /* MEMORY_READ_BARRIER(); */
1610 while (1) {
1611 dsa = scr_to_cpu(np->dqueue[i]);
1612 if (!dsa)
1613 break;
1614 np->dqueue[i] = 0;
1615 if ((i = i+2) >= MAX_QUEUE*2)
1616 i = 0;
1617
1618 cp = sym_ccb_from_dsa(np, dsa);
1619 if (cp) {
1620 MEMORY_READ_BARRIER();
1621 sym_complete_ok (np, cp);
1622 ++n;
1623 }
1624 else
1625 printf ("%s: bad DSA (%x) in done queue.\n",
1626 sym_name(np), (u_int) dsa);
1627 }
1628 np->dqueueget = i;
1629
1630 return n;
1631}
1632
1633/*
1634 * Complete all CCBs queued to the COMP queue.
1635 *
1636 * These CCBs are assumed:
1637 * - Not to be referenced either by devices or
1638 * SCRIPTS-related queues and datas.
1639 * - To have to be completed with an error condition
1640 * or requeued.
1641 *
1642 * The device queue freeze count is incremented
1643 * for each CCB that does not prevent this.
1644 * This function is called when all CCBs involved
1645 * in error handling/recovery have been reaped.
1646 */
1647static void sym_flush_comp_queue(struct sym_hcb *np, int cam_status)
1648{
1649 SYM_QUEHEAD *qp;
1650 struct sym_ccb *cp;
1651
1652 while ((qp = sym_remque_head(&np->comp_ccbq)) != 0) {
1653 struct scsi_cmnd *cmd;
1654 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
1655 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq);
1656 /* Leave quiet CCBs waiting for resources */
1657 if (cp->host_status == HS_WAIT)
1658 continue;
1659 cmd = cp->cmd;
1660 if (cam_status)
1661 sym_set_cam_status(cmd, cam_status);
1662#ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
53222b90 1663 if (sym_get_cam_status(cmd) == DID_SOFT_ERROR) {
1da177e4
LT		 1664 struct sym_tcb *tp = &np->target[cp->target];
1665 struct sym_lcb *lp = sym_lp(tp, cp->lun);
1666 if (lp) {
1667 sym_remque(&cp->link2_ccbq);
1668 sym_insque_tail(&cp->link2_ccbq,
1669 &lp->waiting_ccbq);
1670 if (cp->started) {
1671 if (cp->tag != NO_TAG)
1672 --lp->started_tags;
1673 else
1674 --lp->started_no_tag;
1675 }
1676 }
1677 cp->started = 0;
1678 continue;
1679 }
1680#endif
1681 sym_free_ccb(np, cp);
1682 sym_xpt_done(np, cmd);
1683 }
1684}
1685
1686/*
1687 * Complete all active CCBs with error.
1688 * Used on CHIP/SCSI RESET.
1689 */
1690static void sym_flush_busy_queue (struct sym_hcb *np, int cam_status)
1691{
1692 /*
1693 * Move all active CCBs to the COMP queue
1694 * and flush this queue.
1695 */
1696 sym_que_splice(&np->busy_ccbq, &np->comp_ccbq);
1697 sym_que_init(&np->busy_ccbq);
1698 sym_flush_comp_queue(np, cam_status);
1699}
1700
1701/*
1702 * Start chip.
1703 *
1704 * 'reason' means:
1705 * 0: initialisation.
1706 * 1: SCSI BUS RESET delivered or received.
1707 * 2: SCSI BUS MODE changed.
1708 */
1709void sym_start_up (struct sym_hcb *np, int reason)
1710{
1711 int i;
1712 u32 phys;
1713
1714 /*
1715 * Reset chip if asked, otherwise just clear fifos.
1716 */
1717 if (reason == 1)
1718 sym_soft_reset(np);
1719 else {
1720 OUTB(np, nc_stest3, TE|CSF);
1721 OUTONB(np, nc_ctest3, CLF);
1722 }
1723
1724 /*
1725 * Clear Start Queue
1726 */
1727 phys = np->squeue_ba;
1728 for (i = 0; i < MAX_QUEUE*2; i += 2) {
1729 np->squeue[i] = cpu_to_scr(np->idletask_ba);
1730 np->squeue[i+1] = cpu_to_scr(phys + (i+2)*4);
1731 }
1732 np->squeue[MAX_QUEUE*2-1] = cpu_to_scr(phys);
1733
1734 /*
1735 * Start at first entry.
1736 */
1737 np->squeueput = 0;
1738
1739 /*
1740 * Clear Done Queue
1741 */
1742 phys = np->dqueue_ba;
1743 for (i = 0; i < MAX_QUEUE*2; i += 2) {
1744 np->dqueue[i] = 0;
1745 np->dqueue[i+1] = cpu_to_scr(phys + (i+2)*4);
1746 }
1747 np->dqueue[MAX_QUEUE*2-1] = cpu_to_scr(phys);
1748
1749 /*
1750 * Start at first entry.
1751 */
1752 np->dqueueget = 0;
1753
1754 /*
1755 * Install patches in scripts.
1756 * This also let point to first position the start
1757 * and done queue pointers used from SCRIPTS.
1758 */
1759 np->fw_patch(np);
1760
1761 /*
1762 * Wakeup all pending jobs.
1763 */
53222b90 1764 sym_flush_busy_queue(np, DID_RESET);
1da177e4
LT		 1765
1766 /*
1767 * Init chip.
1768 */
1769 OUTB(np, nc_istat, 0x00); /* Remove Reset, abort */
53222b90 1770 INB(np, nc_mbox1);
1da177e4
LT		 1771 udelay(2000); /* The 895 needs time for the bus mode to settle */
1772
1773 OUTB(np, nc_scntl0, np->rv_scntl0 | 0xc0);
1774 /* full arb., ena parity, par->ATN */
1775 OUTB(np, nc_scntl1, 0x00); /* odd parity, and remove CRST!! */
1776
1777 sym_selectclock(np, np->rv_scntl3); /* Select SCSI clock */
1778
1779 OUTB(np, nc_scid , RRE|np->myaddr); /* Adapter SCSI address */
1780 OUTW(np, nc_respid, 1ul<<np->myaddr); /* Id to respond to */
1781 OUTB(np, nc_istat , SIGP ); /* Signal Process */
1782 OUTB(np, nc_dmode , np->rv_dmode); /* Burst length, dma mode */
1783 OUTB(np, nc_ctest5, np->rv_ctest5); /* Large fifo + large burst */
1784
1785 OUTB(np, nc_dcntl , NOCOM|np->rv_dcntl); /* Protect SFBR */
1786 OUTB(np, nc_ctest3, np->rv_ctest3); /* Write and invalidate */
1787 OUTB(np, nc_ctest4, np->rv_ctest4); /* Master parity checking */
1788
1789 /* Extended Sreq/Sack filtering not supported on the C10 */
1790 if (np->features & FE_C10)
1791 OUTB(np, nc_stest2, np->rv_stest2);
1792 else
1793 OUTB(np, nc_stest2, EXT|np->rv_stest2);
1794
1795 OUTB(np, nc_stest3, TE); /* TolerANT enable */
1796 OUTB(np, nc_stime0, 0x0c); /* HTH disabled STO 0.25 sec */
1797
1798 /*
1799 * For now, disable AIP generation on C1010-66.
1800 */
e58bc06e 1801 if (np->s.device->device == PCI_DEVICE_ID_LSI_53C1010_66)
1da177e4
LT		 1802 OUTB(np, nc_aipcntl1, DISAIP);
1803
1804 /*
1805 * C10101 rev. 0 errata.
1806 * Errant SGE's when in narrow. Write bits 4 & 5 of
1807 * STEST1 register to disable SGE. We probably should do
1808 * that from SCRIPTS for each selection/reselection, but
1809 * I just don't want. :)
1810 */
e58bc06e 1811 if (np->s.device->device == PCI_DEVICE_ID_LSI_53C1010_33 &&
bd678450 1812 np->s.device->revision < 1)
1da177e4
LT		 1813 OUTB(np, nc_stest1, INB(np, nc_stest1) | 0x30);
1814
1815 /*
1816 * DEL 441 - 53C876 Rev 5 - Part Number 609-0392787/2788 - ITEM 2.
1817 * Disable overlapped arbitration for some dual function devices,
1818 * regardless revision id (kind of post-chip-design feature. ;-))
1819 */
e58bc06e 1820 if (np->s.device->device == PCI_DEVICE_ID_NCR_53C875)
1da177e4 1821 OUTB(np, nc_ctest0, (1<<5));
e58bc06e 1822 else if (np->s.device->device == PCI_DEVICE_ID_NCR_53C896)
1da177e4
LT		 1823 np->rv_ccntl0 |= DPR;
1824
1825 /*
1826 * Write CCNTL0/CCNTL1 for chips capable of 64 bit addressing
1827 * and/or hardware phase mismatch, since only such chips
1828 * seem to support those IO registers.
1829 */
1830 if (np->features & (FE_DAC|FE_NOPM)) {
1831 OUTB(np, nc_ccntl0, np->rv_ccntl0);
1832 OUTB(np, nc_ccntl1, np->rv_ccntl1);
1833 }
1834
1835#if SYM_CONF_DMA_ADDRESSING_MODE == 2
1836 /*
1837 * Set up scratch C and DRS IO registers to map the 32 bit
1838 * DMA address range our data structures are located in.
1839 */
1840 if (np->use_dac) {
1841 np->dmap_bah[0] = 0; /* ??? */
1842 OUTL(np, nc_scrx[0], np->dmap_bah[0]);
1843 OUTL(np, nc_drs, np->dmap_bah[0]);
1844 }
1845#endif
1846
1847 /*
1848 * If phase mismatch handled by scripts (895A/896/1010),
1849 * set PM jump addresses.
1850 */
1851 if (np->features & FE_NOPM) {
1852 OUTL(np, nc_pmjad1, SCRIPTB_BA(np, pm_handle));
1853 OUTL(np, nc_pmjad2, SCRIPTB_BA(np, pm_handle));
1854 }
1855
1856 /*
1857 * Enable GPIO0 pin for writing if LED support from SCRIPTS.
1858 * Also set GPIO5 and clear GPIO6 if hardware LED control.
1859 */
1860 if (np->features & FE_LED0)
1861 OUTB(np, nc_gpcntl, INB(np, nc_gpcntl) & ~0x01);
1862 else if (np->features & FE_LEDC)
1863 OUTB(np, nc_gpcntl, (INB(np, nc_gpcntl) & ~0x41) | 0x20);
1864
1865 /*
1866 * enable ints
1867 */
1868 OUTW(np, nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR);
1869 OUTB(np, nc_dien , MDPE|BF|SSI|SIR|IID);
1870
1871 /*
1872 * For 895/6 enable SBMC interrupt and save current SCSI bus mode.
1873 * Try to eat the spurious SBMC interrupt that may occur when
1874 * we reset the chip but not the SCSI BUS (at initialization).
1875 */
1876 if (np->features & (FE_ULTRA2|FE_ULTRA3)) {
1877 OUTONW(np, nc_sien, SBMC);
1878 if (reason == 0) {
53222b90 1879 INB(np, nc_mbox1);
1da177e4
LT		 1880 mdelay(100);
1881 INW(np, nc_sist);
1882 }
1883 np->scsi_mode = INB(np, nc_stest4) & SMODE;
1884 }
1885
1886 /*
1887 * Fill in target structure.
1888 * Reinitialize usrsync.
1889 * Reinitialize usrwide.
1890 * Prepare sync negotiation according to actual SCSI bus mode.
1891 */
1892 for (i=0;i<SYM_CONF_MAX_TARGET;i++) {
1893 struct sym_tcb *tp = &np->target[i];
1894
1895 tp->to_reset = 0;
1896 tp->head.sval = 0;
1897 tp->head.wval = np->rv_scntl3;
1898 tp->head.uval = 0;
1899 }
1900
1901 /*
1902 * Download SCSI SCRIPTS to on-chip RAM if present,
1903 * and start script processor.
1904 * We do the download preferently from the CPU.
1905 * For platforms that may not support PCI memory mapping,
1906 * we use simple SCRIPTS that performs MEMORY MOVEs.
1907 */
1908 phys = SCRIPTA_BA(np, init);
1909 if (np->ram_ba) {
1910 if (sym_verbose >= 2)
1911 printf("%s: Downloading SCSI SCRIPTS.\n", sym_name(np));
1912 memcpy_toio(np->s.ramaddr, np->scripta0, np->scripta_sz);
1913 if (np->ram_ws == 8192) {
1914 memcpy_toio(np->s.ramaddr + 4096, np->scriptb0, np->scriptb_sz);
1915 phys = scr_to_cpu(np->scr_ram_seg);
1916 OUTL(np, nc_mmws, phys);
1917 OUTL(np, nc_mmrs, phys);
1918 OUTL(np, nc_sfs, phys);
1919 phys = SCRIPTB_BA(np, start64);
1920 }
1921 }
1922
1923 np->istat_sem = 0;
1924
1925 OUTL(np, nc_dsa, np->hcb_ba);
1926 OUTL_DSP(np, phys);
1927
1928 /*
1929 * Notify the XPT about the RESET condition.
1930 */
1931 if (reason != 0)
1932 sym_xpt_async_bus_reset(np);
1933}
1934
1935/*
1936 * Switch trans mode for current job and its target.
1937 */
1938static void sym_settrans(struct sym_hcb *np, int target, u_char opts, u_char ofs,
1939 u_char per, u_char wide, u_char div, u_char fak)
1940{
1941 SYM_QUEHEAD *qp;
1942 u_char sval, wval, uval;
1943 struct sym_tcb *tp = &np->target[target];
1944
1945 assert(target == (INB(np, nc_sdid) & 0x0f));
1946
1947 sval = tp->head.sval;
1948 wval = tp->head.wval;
1949 uval = tp->head.uval;
1950
1951#if 0
1952 printf("XXXX sval=%x wval=%x uval=%x (%x)\n",
1953 sval, wval, uval, np->rv_scntl3);
1954#endif
1955 /*
1956 * Set the offset.
1957 */
1958 if (!(np->features & FE_C10))
1959 sval = (sval & ~0x1f) | ofs;
1960 else
1961 sval = (sval & ~0x3f) | ofs;
1962
1963 /*
1964 * Set the sync divisor and extra clock factor.
1965 */
1966 if (ofs != 0) {
1967 wval = (wval & ~0x70) | ((div+1) << 4);
1968 if (!(np->features & FE_C10))
1969 sval = (sval & ~0xe0) | (fak << 5);
1970 else {
1971 uval = uval & ~(XCLKH_ST|XCLKH_DT|XCLKS_ST|XCLKS_DT);
1972 if (fak >= 1) uval |= (XCLKH_ST|XCLKH_DT);
1973 if (fak >= 2) uval |= (XCLKS_ST|XCLKS_DT);
1974 }
1975 }
1976
1977 /*
1978 * Set the bus width.
1979 */
1980 wval = wval & ~EWS;
1981 if (wide != 0)
1982 wval |= EWS;
1983
1984 /*
1985 * Set misc. ultra enable bits.
1986 */
1987 if (np->features & FE_C10) {
1988 uval = uval & ~(U3EN|AIPCKEN);
1989 if (opts) {
1990 assert(np->features & FE_U3EN);
1991 uval |= U3EN;
1992 }
1993 } else {
1994 wval = wval & ~ULTRA;
1995 if (per <= 12) wval |= ULTRA;
1996 }
1997
1998 /*
1999 * Stop there if sync parameters are unchanged.
2000 */
2001 if (tp->head.sval == sval &&
2002 tp->head.wval == wval &&
2003 tp->head.uval == uval)
2004 return;
2005 tp->head.sval = sval;
2006 tp->head.wval = wval;
2007 tp->head.uval = uval;
2008
2009 /*
2010 * Disable extended Sreq/Sack filtering if per < 50.
2011 * Not supported on the C1010.
2012 */
2013 if (per < 50 && !(np->features & FE_C10))
2014 OUTOFFB(np, nc_stest2, EXT);
2015
2016 /*
2017 * set actual value and sync_status
2018 */
2019 OUTB(np, nc_sxfer, tp->head.sval);
2020 OUTB(np, nc_scntl3, tp->head.wval);
2021
2022 if (np->features & FE_C10) {
2023 OUTB(np, nc_scntl4, tp->head.uval);
2024 }
2025
2026 /*
2027 * patch ALL busy ccbs of this target.
2028 */
2029 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
2030 struct sym_ccb *cp;
2031 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
2032 if (cp->target != target)
2033 continue;
2034 cp->phys.select.sel_scntl3 = tp->head.wval;
2035 cp->phys.select.sel_sxfer = tp->head.sval;
2036 if (np->features & FE_C10) {
2037 cp->phys.select.sel_scntl4 = tp->head.uval;
2038 }
2039 }
2040}
2041
2042/*
2043 * We received a WDTR.
2044 * Let everything be aware of the changes.
2045 */
2046static void sym_setwide(struct sym_hcb *np, int target, u_char wide)
2047{
2048 struct sym_tcb *tp = &np->target[target];
53222b90 2049 struct scsi_target *starget = tp->starget;
1da177e4
LT		 2050
2051 if (spi_width(starget) == wide)
2052 return;
2053
2054 sym_settrans(np, target, 0, 0, 0, wide, 0, 0);
2055
2056 tp->tgoal.width = wide;
2057 spi_offset(starget) = 0;
2058 spi_period(starget) = 0;
2059 spi_width(starget) = wide;
2060 spi_iu(starget) = 0;
2061 spi_dt(starget) = 0;
2062 spi_qas(starget) = 0;
2063
2064 if (sym_verbose >= 3)
2065 spi_display_xfer_agreement(starget);
2066}
2067
2068/*
2069 * We received a SDTR.
2070 * Let everything be aware of the changes.
2071 */
2072static void
2073sym_setsync(struct sym_hcb *np, int target,
2074 u_char ofs, u_char per, u_char div, u_char fak)
2075{
2076 struct sym_tcb *tp = &np->target[target];
53222b90 2077 struct scsi_target *starget = tp->starget;
1da177e4
LT		 2078 u_char wide = (tp->head.wval & EWS) ? BUS_16_BIT : BUS_8_BIT;
2079
2080 sym_settrans(np, target, 0, ofs, per, wide, div, fak);
2081
2082 spi_period(starget) = per;
2083 spi_offset(starget) = ofs;
2084 spi_iu(starget) = spi_dt(starget) = spi_qas(starget) = 0;
2085
2086 if (!tp->tgoal.dt && !tp->tgoal.iu && !tp->tgoal.qas) {
2087 tp->tgoal.period = per;
2088 tp->tgoal.offset = ofs;
2089 tp->tgoal.check_nego = 0;
2090 }
2091
2092 spi_display_xfer_agreement(starget);
2093}
2094
2095/*
2096 * We received a PPR.
2097 * Let everything be aware of the changes.
2098 */
2099static void
2100sym_setpprot(struct sym_hcb *np, int target, u_char opts, u_char ofs,
2101 u_char per, u_char wide, u_char div, u_char fak)
2102{
2103 struct sym_tcb *tp = &np->target[target];
53222b90 2104 struct scsi_target *starget = tp->starget;
1da177e4
LT		 2105
2106 sym_settrans(np, target, opts, ofs, per, wide, div, fak);
2107
2108 spi_width(starget) = tp->tgoal.width = wide;
2109 spi_period(starget) = tp->tgoal.period = per;
2110 spi_offset(starget) = tp->tgoal.offset = ofs;
2111 spi_iu(starget) = tp->tgoal.iu = !!(opts & PPR_OPT_IU);
2112 spi_dt(starget) = tp->tgoal.dt = !!(opts & PPR_OPT_DT);
2113 spi_qas(starget) = tp->tgoal.qas = !!(opts & PPR_OPT_QAS);
2114 tp->tgoal.check_nego = 0;
2115
2116 spi_display_xfer_agreement(starget);
2117}
2118
2119/*
2120 * generic recovery from scsi interrupt
2121 *
2122 * The doc says that when the chip gets an SCSI interrupt,
2123 * it tries to stop in an orderly fashion, by completing
2124 * an instruction fetch that had started or by flushing
2125 * the DMA fifo for a write to memory that was executing.
2126 * Such a fashion is not enough to know if the instruction
2127 * that was just before the current DSP value has been
2128 * executed or not.
2129 *
2130 * There are some small SCRIPTS sections that deal with
2131 * the start queue and the done queue that may break any
2132 * assomption from the C code if we are interrupted
2133 * inside, so we reset if this happens. Btw, since these
2134 * SCRIPTS sections are executed while the SCRIPTS hasn't
2135 * started SCSI operations, it is very unlikely to happen.
2136 *
2137 * All the driver data structures are supposed to be
2138 * allocated from the same 4 GB memory window, so there
2139 * is a 1 to 1 relationship between DSA and driver data
2140 * structures. Since we are careful :) to invalidate the
2141 * DSA when we complete a command or when the SCRIPTS
2142 * pushes a DSA into a queue, we can trust it when it
2143 * points to a CCB.
2144 */
2145static void sym_recover_scsi_int (struct sym_hcb *np, u_char hsts)
2146{
2147 u32 dsp = INL(np, nc_dsp);
2148 u32 dsa = INL(np, nc_dsa);
2149 struct sym_ccb *cp = sym_ccb_from_dsa(np, dsa);
2150
2151 /*
2152 * If we haven't been interrupted inside the SCRIPTS
2153 * critical pathes, we can safely restart the SCRIPTS
2154 * and trust the DSA value if it matches a CCB.
2155 */
2156 if ((!(dsp > SCRIPTA_BA(np, getjob_begin) &&
2157 dsp < SCRIPTA_BA(np, getjob_end) + 1)) &&
2158 (!(dsp > SCRIPTA_BA(np, ungetjob) &&
2159 dsp < SCRIPTA_BA(np, reselect) + 1)) &&
2160 (!(dsp > SCRIPTB_BA(np, sel_for_abort) &&
2161 dsp < SCRIPTB_BA(np, sel_for_abort_1) + 1)) &&
2162 (!(dsp > SCRIPTA_BA(np, done) &&
2163 dsp < SCRIPTA_BA(np, done_end) + 1))) {
2164 OUTB(np, nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */
2165 OUTB(np, nc_stest3, TE|CSF); /* clear scsi fifo */
2166 /*
2167 * If we have a CCB, let the SCRIPTS call us back for
2168 * the handling of the error with SCRATCHA filled with
2169 * STARTPOS. This way, we will be able to freeze the
2170 * device queue and requeue awaiting IOs.
2171 */
2172 if (cp) {
2173 cp->host_status = hsts;
2174 OUTL_DSP(np, SCRIPTA_BA(np, complete_error));
2175 }
2176 /*
2177 * Otherwise just restart the SCRIPTS.
2178 */
2179 else {
2180 OUTL(np, nc_dsa, 0xffffff);
2181 OUTL_DSP(np, SCRIPTA_BA(np, start));
2182 }
2183 }
2184 else
2185 goto reset_all;
2186
2187 return;
2188
2189reset_all:
2190 sym_start_reset(np);
2191}
2192
2193/*
2194 * chip exception handler for selection timeout
2195 */
2196static void sym_int_sto (struct sym_hcb *np)
2197{
2198 u32 dsp = INL(np, nc_dsp);
2199
2200 if (DEBUG_FLAGS & DEBUG_TINY) printf ("T");
2201
2202 if (dsp == SCRIPTA_BA(np, wf_sel_done) + 8)
2203 sym_recover_scsi_int(np, HS_SEL_TIMEOUT);
2204 else
2205 sym_start_reset(np);
2206}
2207
2208/*
2209 * chip exception handler for unexpected disconnect
2210 */
2211static void sym_int_udc (struct sym_hcb *np)
2212{
2213 printf ("%s: unexpected disconnect\n", sym_name(np));
2214 sym_recover_scsi_int(np, HS_UNEXPECTED);
2215}
2216
2217/*
2218 * chip exception handler for SCSI bus mode change
2219 *
2220 * spi2-r12 11.2.3 says a transceiver mode change must
2221 * generate a reset event and a device that detects a reset
2222 * event shall initiate a hard reset. It says also that a
2223 * device that detects a mode change shall set data transfer
2224 * mode to eight bit asynchronous, etc...
2225 * So, just reinitializing all except chip should be enough.
2226 */
2227static void sym_int_sbmc (struct sym_hcb *np)
2228{
2229 u_char scsi_mode = INB(np, nc_stest4) & SMODE;
2230
2231 /*
2232 * Notify user.
2233 */
2234 printf("%s: SCSI BUS mode change from %s to %s.\n", sym_name(np),
2235 sym_scsi_bus_mode(np->scsi_mode), sym_scsi_bus_mode(scsi_mode));
2236
2237 /*
2238 * Should suspend command processing for a few seconds and
2239 * reinitialize all except the chip.
2240 */
2241 sym_start_up (np, 2);
2242}
2243
2244/*
2245 * chip exception handler for SCSI parity error.
2246 *
2247 * When the chip detects a SCSI parity error and is
2248 * currently executing a (CH)MOV instruction, it does
2249 * not interrupt immediately, but tries to finish the
2250 * transfer of the current scatter entry before
2251 * interrupting. The following situations may occur:
2252 *
2253 * - The complete scatter entry has been transferred
2254 * without the device having changed phase.
2255 * The chip will then interrupt with the DSP pointing
2256 * to the instruction that follows the MOV.
2257 *
2258 * - A phase mismatch occurs before the MOV finished
2259 * and phase errors are to be handled by the C code.
2260 * The chip will then interrupt with both PAR and MA
2261 * conditions set.
2262 *
2263 * - A phase mismatch occurs before the MOV finished and
2264 * phase errors are to be handled by SCRIPTS.
2265 * The chip will load the DSP with the phase mismatch
2266 * JUMP address and interrupt the host processor.
2267 */
2268static void sym_int_par (struct sym_hcb *np, u_short sist)
2269{
2270 u_char hsts = INB(np, HS_PRT);
2271 u32 dsp = INL(np, nc_dsp);
2272 u32 dbc = INL(np, nc_dbc);
2273 u32 dsa = INL(np, nc_dsa);
2274 u_char sbcl = INB(np, nc_sbcl);
2275 u_char cmd = dbc >> 24;
2276 int phase = cmd & 7;
2277 struct sym_ccb *cp = sym_ccb_from_dsa(np, dsa);
2278
2279 printf("%s: SCSI parity error detected: SCR1=%d DBC=%x SBCL=%x\n",
2280 sym_name(np), hsts, dbc, sbcl);
2281
2282 /*
2283 * Check that the chip is connected to the SCSI BUS.
2284 */
2285 if (!(INB(np, nc_scntl1) & ISCON)) {
2286 sym_recover_scsi_int(np, HS_UNEXPECTED);
2287 return;
2288 }
2289
2290 /*
2291 * If the nexus is not clearly identified, reset the bus.
2292 * We will try to do better later.
2293 */
2294 if (!cp)
2295 goto reset_all;
2296
2297 /*
2298 * Check instruction was a MOV, direction was INPUT and
2299 * ATN is asserted.
2300 */
2301 if ((cmd & 0xc0) || !(phase & 1) || !(sbcl & 0x8))
2302 goto reset_all;
2303
2304 /*
2305 * Keep track of the parity error.
2306 */
2307 OUTONB(np, HF_PRT, HF_EXT_ERR);
2308 cp->xerr_status |= XE_PARITY_ERR;
2309
2310 /*
2311 * Prepare the message to send to the device.
2312 */
2313 np->msgout[0] = (phase == 7) ? M_PARITY : M_ID_ERROR;
2314
2315 /*
2316 * If the old phase was DATA IN phase, we have to deal with
2317 * the 3 situations described above.
2318 * For other input phases (MSG IN and STATUS), the device
2319 * must resend the whole thing that failed parity checking
2320 * or signal error. So, jumping to dispatcher should be OK.
2321 */
2322 if (phase == 1 || phase == 5) {
2323 /* Phase mismatch handled by SCRIPTS */
2324 if (dsp == SCRIPTB_BA(np, pm_handle))
2325 OUTL_DSP(np, dsp);
2326 /* Phase mismatch handled by the C code */
2327 else if (sist & MA)
2328 sym_int_ma (np);
2329 /* No phase mismatch occurred */
2330 else {
2331 sym_set_script_dp (np, cp, dsp);
2332 OUTL_DSP(np, SCRIPTA_BA(np, dispatch));
2333 }
2334 }
2335 else if (phase == 7) /* We definitely cannot handle parity errors */
2336#if 1 /* in message-in phase due to the relection */
2337 goto reset_all; /* path and various message anticipations. */
2338#else
2339 OUTL_DSP(np, SCRIPTA_BA(np, clrack));
2340#endif
2341 else
2342 OUTL_DSP(np, SCRIPTA_BA(np, dispatch));
2343 return;
2344
2345reset_all:
2346 sym_start_reset(np);
2347 return;
2348}
2349
2350/*
2351 * chip exception handler for phase errors.
2352 *
2353 * We have to construct a new transfer descriptor,
2354 * to transfer the rest of the current block.
2355 */
2356static void sym_int_ma (struct sym_hcb *np)
2357{
2358 u32 dbc;
2359 u32 rest;
2360 u32 dsp;
2361 u32 dsa;
2362 u32 nxtdsp;
2363 u32 *vdsp;
2364 u32 oadr, olen;
2365 u32 *tblp;
2366 u32 newcmd;
2367 u_int delta;
2368 u_char cmd;
2369 u_char hflags, hflags0;
2370 struct sym_pmc *pm;
2371 struct sym_ccb *cp;
2372
2373 dsp = INL(np, nc_dsp);
2374 dbc = INL(np, nc_dbc);
2375 dsa = INL(np, nc_dsa);
2376
2377 cmd = dbc >> 24;
2378 rest = dbc & 0xffffff;
2379 delta = 0;
2380
2381 /*
2382 * locate matching cp if any.
2383 */
2384 cp = sym_ccb_from_dsa(np, dsa);
2385
2386 /*
2387 * Donnot take into account dma fifo and various buffers in
2388 * INPUT phase since the chip flushes everything before
2389 * raising the MA interrupt for interrupted INPUT phases.
2390 * For DATA IN phase, we will check for the SWIDE later.
2391 */
2392 if ((cmd & 7) != 1 && (cmd & 7) != 5) {
2393 u_char ss0, ss2;
2394
2395 if (np->features & FE_DFBC)
2396 delta = INW(np, nc_dfbc);
2397 else {
2398 u32 dfifo;
2399
2400 /*
2401 * Read DFIFO, CTEST[4-6] using 1 PCI bus ownership.
2402 */
2403 dfifo = INL(np, nc_dfifo);
2404
2405 /*
2406 * Calculate remaining bytes in DMA fifo.
2407 * (CTEST5 = dfifo >> 16)
2408 */
2409 if (dfifo & (DFS << 16))
2410 delta = ((((dfifo >> 8) & 0x300) |
2411 (dfifo & 0xff)) - rest) & 0x3ff;
2412 else
2413 delta = ((dfifo & 0xff) - rest) & 0x7f;
2414 }
2415
2416 /*
2417 * The data in the dma fifo has not been transfered to
2418 * the target -> add the amount to the rest
2419 * and clear the data.
2420 * Check the sstat2 register in case of wide transfer.
2421 */
2422 rest += delta;
2423 ss0 = INB(np, nc_sstat0);
2424 if (ss0 & OLF) rest++;
2425 if (!(np->features & FE_C10))
2426 if (ss0 & ORF) rest++;
2427 if (cp && (cp->phys.select.sel_scntl3 & EWS)) {
2428 ss2 = INB(np, nc_sstat2);
2429 if (ss2 & OLF1) rest++;
2430 if (!(np->features & FE_C10))
2431 if (ss2 & ORF1) rest++;
2432 }
2433
2434 /*
2435 * Clear fifos.
2436 */
2437 OUTB(np, nc_ctest3, np->rv_ctest3 | CLF); /* dma fifo */
2438 OUTB(np, nc_stest3, TE|CSF); /* scsi fifo */
2439 }
2440
2441 /*
2442 * log the information
2443 */
2444 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_PHASE))
2445 printf ("P%x%x RL=%d D=%d ", cmd&7, INB(np, nc_sbcl)&7,
2446 (unsigned) rest, (unsigned) delta);
2447
2448 /*
2449 * try to find the interrupted script command,
2450 * and the address at which to continue.
2451 */
2452 vdsp = NULL;
2453 nxtdsp = 0;
2454 if (dsp > np->scripta_ba &&
2455 dsp <= np->scripta_ba + np->scripta_sz) {
2456 vdsp = (u32 *)((char*)np->scripta0 + (dsp-np->scripta_ba-8));
2457 nxtdsp = dsp;
2458 }
2459 else if (dsp > np->scriptb_ba &&
2460 dsp <= np->scriptb_ba + np->scriptb_sz) {
2461 vdsp = (u32 *)((char*)np->scriptb0 + (dsp-np->scriptb_ba-8));
2462 nxtdsp = dsp;
2463 }
2464
2465 /*
2466 * log the information
2467 */
2468 if (DEBUG_FLAGS & DEBUG_PHASE) {
2469 printf ("\nCP=%p DSP=%x NXT=%x VDSP=%p CMD=%x ",
2470 cp, (unsigned)dsp, (unsigned)nxtdsp, vdsp, cmd);
2471 }
2472
2473 if (!vdsp) {
2474 printf ("%s: interrupted SCRIPT address not found.\n",
2475 sym_name (np));
2476 goto reset_all;
2477 }
2478
2479 if (!cp) {
2480 printf ("%s: SCSI phase error fixup: CCB already dequeued.\n",
2481 sym_name (np));
2482 goto reset_all;
2483 }
2484
2485 /*
2486 * get old startaddress and old length.
2487 */
2488 oadr = scr_to_cpu(vdsp[1]);
2489
2490 if (cmd & 0x10) { /* Table indirect */
2491 tblp = (u32 *) ((char*) &cp->phys + oadr);
2492 olen = scr_to_cpu(tblp[0]);
2493 oadr = scr_to_cpu(tblp[1]);
2494 } else {
2495 tblp = (u32 *) 0;
2496 olen = scr_to_cpu(vdsp[0]) & 0xffffff;
2497 }
2498
2499 if (DEBUG_FLAGS & DEBUG_PHASE) {
2500 printf ("OCMD=%x\nTBLP=%p OLEN=%x OADR=%x\n",
2501 (unsigned) (scr_to_cpu(vdsp[0]) >> 24),
2502 tblp,
2503 (unsigned) olen,
2504 (unsigned) oadr);
2505 }
2506
2507 /*
2508 * check cmd against assumed interrupted script command.
2509 * If dt data phase, the MOVE instruction hasn't bit 4 of
2510 * the phase.
2511 */
2512 if (((cmd & 2) ? cmd : (cmd & ~4)) != (scr_to_cpu(vdsp[0]) >> 24)) {
2513 sym_print_addr(cp->cmd,
2514 "internal error: cmd=%02x != %02x=(vdsp[0] >> 24)\n",
2515 cmd, scr_to_cpu(vdsp[0]) >> 24);
2516
2517 goto reset_all;
2518 }
2519
2520 /*
2521 * if old phase not dataphase, leave here.
2522 */
2523 if (cmd & 2) {
2524 sym_print_addr(cp->cmd,
2525 "phase change %x-%x %d@%08x resid=%d.\n",
2526 cmd&7, INB(np, nc_sbcl)&7, (unsigned)olen,
2527 (unsigned)oadr, (unsigned)rest);
2528 goto unexpected_phase;
2529 }
2530
2531 /*
2532 * Choose the correct PM save area.
2533 *
2534 * Look at the PM_SAVE SCRIPT if you want to understand
2535 * this stuff. The equivalent code is implemented in
2536 * SCRIPTS for the 895A, 896 and 1010 that are able to
2537 * handle PM from the SCRIPTS processor.
2538 */
2539 hflags0 = INB(np, HF_PRT);
2540 hflags = hflags0;
2541
2542 if (hflags & (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED)) {
2543 if (hflags & HF_IN_PM0)
2544 nxtdsp = scr_to_cpu(cp->phys.pm0.ret);
2545 else if (hflags & HF_IN_PM1)
2546 nxtdsp = scr_to_cpu(cp->phys.pm1.ret);
2547
2548 if (hflags & HF_DP_SAVED)
2549 hflags ^= HF_ACT_PM;
2550 }
2551
2552 if (!(hflags & HF_ACT_PM)) {
2553 pm = &cp->phys.pm0;
2554 newcmd = SCRIPTA_BA(np, pm0_data);
2555 }
2556 else {
2557 pm = &cp->phys.pm1;
2558 newcmd = SCRIPTA_BA(np, pm1_data);
2559 }
2560
2561 hflags &= ~(HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED);
2562 if (hflags != hflags0)
2563 OUTB(np, HF_PRT, hflags);
2564
2565 /*
2566 * fillin the phase mismatch context
2567 */
2568 pm->sg.addr = cpu_to_scr(oadr + olen - rest);
2569 pm->sg.size = cpu_to_scr(rest);
2570 pm->ret = cpu_to_scr(nxtdsp);
2571
2572 /*
2573 * If we have a SWIDE,
2574 * - prepare the address to write the SWIDE from SCRIPTS,
2575 * - compute the SCRIPTS address to restart from,
2576 * - move current data pointer context by one byte.
2577 */
2578 nxtdsp = SCRIPTA_BA(np, dispatch);
2579 if ((cmd & 7) == 1 && cp && (cp->phys.select.sel_scntl3 & EWS) &&
2580 (INB(np, nc_scntl2) & WSR)) {
2581 u32 tmp;
2582
2583 /*
2584 * Set up the table indirect for the MOVE
2585 * of the residual byte and adjust the data
2586 * pointer context.
2587 */
2588 tmp = scr_to_cpu(pm->sg.addr);
2589 cp->phys.wresid.addr = cpu_to_scr(tmp);
2590 pm->sg.addr = cpu_to_scr(tmp + 1);
2591 tmp = scr_to_cpu(pm->sg.size);
2592 cp->phys.wresid.size = cpu_to_scr((tmp&0xff000000) | 1);
2593 pm->sg.size = cpu_to_scr(tmp - 1);
2594
2595 /*
2596 * If only the residual byte is to be moved,
2597 * no PM context is needed.
2598 */
2599 if ((tmp&0xffffff) == 1)
2600 newcmd = pm->ret;
2601
2602 /*
2603 * Prepare the address of SCRIPTS that will
2604 * move the residual byte to memory.
2605 */
2606 nxtdsp = SCRIPTB_BA(np, wsr_ma_helper);
2607 }
2608
2609 if (DEBUG_FLAGS & DEBUG_PHASE) {
2610 sym_print_addr(cp->cmd, "PM %x %x %x / %x %x %x.\n",
2611 hflags0, hflags, newcmd,
2612 (unsigned)scr_to_cpu(pm->sg.addr),
2613 (unsigned)scr_to_cpu(pm->sg.size),
2614 (unsigned)scr_to_cpu(pm->ret));
2615 }
2616
2617 /*
2618 * Restart the SCRIPTS processor.
2619 */
2620 sym_set_script_dp (np, cp, newcmd);
2621 OUTL_DSP(np, nxtdsp);
2622 return;
2623
2624 /*
2625 * Unexpected phase changes that occurs when the current phase
2626 * is not a DATA IN or DATA OUT phase are due to error conditions.
2627 * Such event may only happen when the SCRIPTS is using a
2628 * multibyte SCSI MOVE.
2629 *
2630 * Phase change Some possible cause
2631 *
2632 * COMMAND --> MSG IN SCSI parity error detected by target.
2633 * COMMAND --> STATUS Bad command or refused by target.
2634 * MSG OUT --> MSG IN Message rejected by target.
2635 * MSG OUT --> COMMAND Bogus target that discards extended
2636 * negotiation messages.
2637 *
2638 * The code below does not care of the new phase and so
2639 * trusts the target. Why to annoy it ?
2640 * If the interrupted phase is COMMAND phase, we restart at
2641 * dispatcher.
2642 * If a target does not get all the messages after selection,
2643 * the code assumes blindly that the target discards extended
2644 * messages and clears the negotiation status.
2645 * If the target does not want all our response to negotiation,
2646 * we force a SIR_NEGO_PROTO interrupt (it is a hack that avoids
2647 * bloat for such a should_not_happen situation).
2648 * In all other situation, we reset the BUS.
2649 * Are these assumptions reasonnable ? (Wait and see ...)
2650 */
2651unexpected_phase:
2652 dsp -= 8;
2653 nxtdsp = 0;
2654
2655 switch (cmd & 7) {
2656 case 2: /* COMMAND phase */
2657 nxtdsp = SCRIPTA_BA(np, dispatch);
2658 break;
2659#if 0
2660 case 3: /* STATUS phase */
2661 nxtdsp = SCRIPTA_BA(np, dispatch);
2662 break;
2663#endif
2664 case 6: /* MSG OUT phase */
2665 /*
2666 * If the device may want to use untagged when we want
2667 * tagged, we prepare an IDENTIFY without disc. granted,
2668 * since we will not be able to handle reselect.
2669 * Otherwise, we just don't care.
2670 */
2671 if (dsp == SCRIPTA_BA(np, send_ident)) {
2672 if (cp->tag != NO_TAG && olen - rest <= 3) {
2673 cp->host_status = HS_BUSY;
2674 np->msgout[0] = IDENTIFY(0, cp->lun);
2675 nxtdsp = SCRIPTB_BA(np, ident_break_atn);
2676 }
2677 else
2678 nxtdsp = SCRIPTB_BA(np, ident_break);
2679 }
2680 else if (dsp == SCRIPTB_BA(np, send_wdtr) ||
2681 dsp == SCRIPTB_BA(np, send_sdtr) ||
2682 dsp == SCRIPTB_BA(np, send_ppr)) {
2683 nxtdsp = SCRIPTB_BA(np, nego_bad_phase);
2684 if (dsp == SCRIPTB_BA(np, send_ppr)) {
2685 struct scsi_device *dev = cp->cmd->device;
2686 dev->ppr = 0;
2687 }
2688 }
2689 break;
2690#if 0
2691 case 7: /* MSG IN phase */
2692 nxtdsp = SCRIPTA_BA(np, clrack);
2693 break;
2694#endif
2695 }
2696
2697 if (nxtdsp) {
2698 OUTL_DSP(np, nxtdsp);
2699 return;
2700 }
2701
2702reset_all:
2703 sym_start_reset(np);
2704}
2705
2706/*
2707 * chip interrupt handler
2708 *
2709 * In normal situations, interrupt conditions occur one at
2710 * a time. But when something bad happens on the SCSI BUS,
2711 * the chip may raise several interrupt flags before
2712 * stopping and interrupting the CPU. The additionnal
2713 * interrupt flags are stacked in some extra registers
2714 * after the SIP and/or DIP flag has been raised in the
2715 * ISTAT. After the CPU has read the interrupt condition
2716 * flag from SIST or DSTAT, the chip unstacks the other
2717 * interrupt flags and sets the corresponding bits in
2718 * SIST or DSTAT. Since the chip starts stacking once the
2719 * SIP or DIP flag is set, there is a small window of time
2720 * where the stacking does not occur.
2721 *
2722 * Typically, multiple interrupt conditions may happen in
2723 * the following situations:
2724 *
2725 * - SCSI parity error + Phase mismatch (PAR|MA)
2726 * When an parity error is detected in input phase
2727 * and the device switches to msg-in phase inside a
2728 * block MOV.
2729 * - SCSI parity error + Unexpected disconnect (PAR|UDC)
2730 * When a stupid device does not want to handle the
2731 * recovery of an SCSI parity error.
2732 * - Some combinations of STO, PAR, UDC, ...
2733 * When using non compliant SCSI stuff, when user is
2734 * doing non compliant hot tampering on the BUS, when
2735 * something really bad happens to a device, etc ...
2736 *
2737 * The heuristic suggested by SYMBIOS to handle
2738 * multiple interrupts is to try unstacking all
2739 * interrupts conditions and to handle them on some
2740 * priority based on error severity.
2741 * This will work when the unstacking has been
2742 * successful, but we cannot be 100 % sure of that,
2743 * since the CPU may have been faster to unstack than
2744 * the chip is able to stack. Hmmm ... But it seems that
2745 * such a situation is very unlikely to happen.
2746 *
2747 * If this happen, for example STO caught by the CPU
2748 * then UDC happenning before the CPU have restarted
2749 * the SCRIPTS, the driver may wrongly complete the
2750 * same command on UDC, since the SCRIPTS didn't restart
2751 * and the DSA still points to the same command.
2752 * We avoid this situation by setting the DSA to an
2753 * invalid value when the CCB is completed and before
2754 * restarting the SCRIPTS.
2755 *
2756 * Another issue is that we need some section of our
2757 * recovery procedures to be somehow uninterruptible but
2758 * the SCRIPTS processor does not provides such a
2759 * feature. For this reason, we handle recovery preferently
2760 * from the C code and check against some SCRIPTS critical
2761 * sections from the C code.
2762 *
2763 * Hopefully, the interrupt handling of the driver is now
2764 * able to resist to weird BUS error conditions, but donnot
2765 * ask me for any guarantee that it will never fail. :-)
2766 * Use at your own decision and risk.
2767 */
2768
2769void sym_interrupt (struct sym_hcb *np)
2770{
2771 u_char istat, istatc;
2772 u_char dstat;
2773 u_short sist;
2774
2775 /*
2776 * interrupt on the fly ?
2777 * (SCRIPTS may still be running)
2778 *
2779 * A `dummy read' is needed to ensure that the
2780 * clear of the INTF flag reaches the device
2781 * and that posted writes are flushed to memory
2782 * before the scanning of the DONE queue.
2783 * Note that SCRIPTS also (dummy) read to memory
2784 * prior to deliver the INTF interrupt condition.
2785 */
2786 istat = INB(np, nc_istat);
2787 if (istat & INTF) {
2788 OUTB(np, nc_istat, (istat & SIGP) | INTF | np->istat_sem);
2789 istat = INB(np, nc_istat); /* DUMMY READ */
2790 if (DEBUG_FLAGS & DEBUG_TINY) printf ("F ");
2791 sym_wakeup_done(np);
2792 }
2793
2794 if (!(istat & (SIP|DIP)))
2795 return;
2796
2797#if 0 /* We should never get this one */
2798 if (istat & CABRT)
2799 OUTB(np, nc_istat, CABRT);
2800#endif
2801
2802 /*
2803 * PAR and MA interrupts may occur at the same time,
2804 * and we need to know of both in order to handle
2805 * this situation properly. We try to unstack SCSI
2806 * interrupts for that reason. BTW, I dislike a LOT
2807 * such a loop inside the interrupt routine.
2808 * Even if DMA interrupt stacking is very unlikely to
2809 * happen, we also try unstacking these ones, since
2810 * this has no performance impact.
2811 */
2812 sist = 0;
2813 dstat = 0;
2814 istatc = istat;
2815 do {
2816 if (istatc & SIP)
2817 sist |= INW(np, nc_sist);
2818 if (istatc & DIP)
2819 dstat |= INB(np, nc_dstat);
2820 istatc = INB(np, nc_istat);
2821 istat |= istatc;
d68cd759
LV		 2822
2823 /* Prevent deadlock waiting on a condition that may
2824 * never clear. */
2825 if (unlikely(sist == 0xffff && dstat == 0xff)) {
2826 if (pci_channel_offline(np->s.device))
2827 return;
2828 }
1da177e4
LT		 2829 } while (istatc & (SIP|DIP));
2830
2831 if (DEBUG_FLAGS & DEBUG_TINY)
2832 printf ("<%d|%x:%x|%x:%x>",
2833 (int)INB(np, nc_scr0),
2834 dstat,sist,
2835 (unsigned)INL(np, nc_dsp),
2836 (unsigned)INL(np, nc_dbc));
2837 /*
2838 * On paper, a memory read barrier may be needed here to
2839 * prevent out of order LOADs by the CPU from having
2840 * prefetched stale data prior to DMA having occurred.
2841 * And since we are paranoid ... :)
2842 */
2843 MEMORY_READ_BARRIER();
2844
2845 /*
2846 * First, interrupts we want to service cleanly.
2847 *
2848 * Phase mismatch (MA) is the most frequent interrupt
2849 * for chip earlier than the 896 and so we have to service
2850 * it as quickly as possible.
2851 * A SCSI parity error (PAR) may be combined with a phase
2852 * mismatch condition (MA).
2853 * Programmed interrupts (SIR) are used to call the C code
2854 * from SCRIPTS.
2855 * The single step interrupt (SSI) is not used in this
2856 * driver.
2857 */
2858 if (!(sist & (STO|GEN|HTH|SGE|UDC|SBMC|RST)) &&
2859 !(dstat & (MDPE|BF|ABRT|IID))) {
2860 if (sist & PAR) sym_int_par (np, sist);
2861 else if (sist & MA) sym_int_ma (np);
2862 else if (dstat & SIR) sym_int_sir (np);
2863 else if (dstat & SSI) OUTONB_STD();
2864 else goto unknown_int;
2865 return;
2866 }
2867
2868 /*
2869 * Now, interrupts that donnot happen in normal
2870 * situations and that we may need to recover from.
2871 *
2872 * On SCSI RESET (RST), we reset everything.
2873 * On SCSI BUS MODE CHANGE (SBMC), we complete all
2874 * active CCBs with RESET status, prepare all devices
2875 * for negotiating again and restart the SCRIPTS.
2876 * On STO and UDC, we complete the CCB with the corres-
2877 * ponding status and restart the SCRIPTS.
2878 */
2879 if (sist & RST) {
2880 printf("%s: SCSI BUS reset detected.\n", sym_name(np));
2881 sym_start_up (np, 1);
2882 return;
2883 }
2884
2885 OUTB(np, nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */
2886 OUTB(np, nc_stest3, TE|CSF); /* clear scsi fifo */
2887
2888 if (!(sist & (GEN|HTH|SGE)) &&
2889 !(dstat & (MDPE|BF|ABRT|IID))) {
2890 if (sist & SBMC) sym_int_sbmc (np);
2891 else if (sist & STO) sym_int_sto (np);
2892 else if (sist & UDC) sym_int_udc (np);
2893 else goto unknown_int;
2894 return;
2895 }
2896
2897 /*
2898 * Now, interrupts we are not able to recover cleanly.
2899 *
2900 * Log message for hard errors.
2901 * Reset everything.
2902 */
2903
2904 sym_log_hard_error(np, sist, dstat);
2905
2906 if ((sist & (GEN|HTH|SGE)) ||
2907 (dstat & (MDPE|BF|ABRT|IID))) {
2908 sym_start_reset(np);
2909 return;
2910 }
2911
2912unknown_int:
2913 /*
2914 * We just miss the cause of the interrupt. :(
2915 * Print a message. The timeout will do the real work.
2916 */
2917 printf( "%s: unknown interrupt(s) ignored, "
2918 "ISTAT=0x%x DSTAT=0x%x SIST=0x%x\n",
2919 sym_name(np), istat, dstat, sist);
2920}
2921
2922/*
2923 * Dequeue from the START queue all CCBs that match
2924 * a given target/lun/task condition (-1 means all),
2925 * and move them from the BUSY queue to the COMP queue
53222b90 2926 * with DID_SOFT_ERROR status condition.
1da177e4
LT		 2927 * This function is used during error handling/recovery.
2928 * It is called with SCRIPTS not running.
2929 */
2930static int
2931sym_dequeue_from_squeue(struct sym_hcb *np, int i, int target, int lun, int task)
2932{
2933 int j;
2934 struct sym_ccb *cp;
2935
2936 /*
2937 * Make sure the starting index is within range.
2938 */
2939 assert((i >= 0) && (i < 2*MAX_QUEUE));
2940
2941 /*
2942 * Walk until end of START queue and dequeue every job
2943 * that matches the target/lun/task condition.
2944 */
2945 j = i;
2946 while (i != np->squeueput) {
2947 cp = sym_ccb_from_dsa(np, scr_to_cpu(np->squeue[i]));
2948 assert(cp);
2949#ifdef SYM_CONF_IARB_SUPPORT
2950 /* Forget hints for IARB, they may be no longer relevant */
2951 cp->host_flags &= ~HF_HINT_IARB;
2952#endif
2953 if ((target == -1 || cp->target == target) &&
2954 (lun == -1 || cp->lun == lun) &&
2955 (task == -1 || cp->tag == task)) {
53222b90 2956 sym_set_cam_status(cp->cmd, DID_SOFT_ERROR);
1da177e4
LT		 2957 sym_remque(&cp->link_ccbq);
2958 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq);
2959 }
2960 else {
2961 if (i != j)
2962 np->squeue[j] = np->squeue[i];
2963 if ((j += 2) >= MAX_QUEUE*2) j = 0;
2964 }
2965 if ((i += 2) >= MAX_QUEUE*2) i = 0;
2966 }
2967 if (i != j) /* Copy back the idle task if needed */
2968 np->squeue[j] = np->squeue[i];
2969 np->squeueput = j; /* Update our current start queue pointer */
2970
2971 return (i - j) / 2;
2972}
2973
2974/*
2975 * chip handler for bad SCSI status condition
2976 *
2977 * In case of bad SCSI status, we unqueue all the tasks
2978 * currently queued to the controller but not yet started
2979 * and then restart the SCRIPTS processor immediately.
2980 *
2981 * QUEUE FULL and BUSY conditions are handled the same way.
2982 * Basically all the not yet started tasks are requeued in
2983 * device queue and the queue is frozen until a completion.
2984 *
2985 * For CHECK CONDITION and COMMAND TERMINATED status, we use
2986 * the CCB of the failed command to prepare a REQUEST SENSE
2987 * SCSI command and queue it to the controller queue.
2988 *
2989 * SCRATCHA is assumed to have been loaded with STARTPOS
2990 * before the SCRIPTS called the C code.
2991 */
2992static void sym_sir_bad_scsi_status(struct sym_hcb *np, int num, struct sym_ccb *cp)
2993{
2994 u32 startp;
2995 u_char s_status = cp->ssss_status;
2996 u_char h_flags = cp->host_flags;
2997 int msglen;
2998 int i;
2999
3000 /*
3001 * Compute the index of the next job to start from SCRIPTS.
3002 */
3003 i = (INL(np, nc_scratcha) - np->squeue_ba) / 4;
3004
3005 /*
3006 * The last CCB queued used for IARB hint may be
3007 * no longer relevant. Forget it.
3008 */
3009#ifdef SYM_CONF_IARB_SUPPORT
3010 if (np->last_cp)
3011 np->last_cp = 0;
3012#endif
3013
3014 /*
3015 * Now deal with the SCSI status.
3016 */
3017 switch(s_status) {
3018 case S_BUSY:
3019 case S_QUEUE_FULL:
3020 if (sym_verbose >= 2) {
3021 sym_print_addr(cp->cmd, "%s\n",
3022 s_status == S_BUSY ? "BUSY" : "QUEUE FULL\n");
3023 }
3024 default: /* S_INT, S_INT_COND_MET, S_CONFLICT */
3025 sym_complete_error (np, cp);
3026 break;
3027 case S_TERMINATED:
3028 case S_CHECK_COND:
3029 /*
3030 * If we get an SCSI error when requesting sense, give up.
3031 */
3032 if (h_flags & HF_SENSE) {
3033 sym_complete_error (np, cp);
3034 break;
3035 }
3036
3037 /*
3038 * Dequeue all queued CCBs for that device not yet started,
3039 * and restart the SCRIPTS processor immediately.
3040 */
3041 sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1);
3042 OUTL_DSP(np, SCRIPTA_BA(np, start));
3043
3044 /*
3045 * Save some info of the actual IO.
3046 * Compute the data residual.
3047 */
3048 cp->sv_scsi_status = cp->ssss_status;
3049 cp->sv_xerr_status = cp->xerr_status;
3050 cp->sv_resid = sym_compute_residual(np, cp);
3051
3052 /*
3053 * Prepare all needed data structures for
3054 * requesting sense data.
3055 */
3056
3057 cp->scsi_smsg2[0] = IDENTIFY(0, cp->lun);
3058 msglen = 1;
3059
3060 /*
3061 * If we are currently using anything different from
3062 * async. 8 bit data transfers with that target,
3063 * start a negotiation, since the device may want
3064 * to report us a UNIT ATTENTION condition due to
3065 * a cause we currently ignore, and we donnot want
3066 * to be stuck with WIDE and/or SYNC data transfer.
3067 *
3068 * cp->nego_status is filled by sym_prepare_nego().
3069 */
3070 cp->nego_status = 0;
3071 msglen += sym_prepare_nego(np, cp, &cp->scsi_smsg2[msglen]);
3072 /*
3073 * Message table indirect structure.
3074 */
53222b90 3075 cp->phys.smsg.addr = CCB_BA(cp, scsi_smsg2);
1da177e4
LT		 3076 cp->phys.smsg.size = cpu_to_scr(msglen);
3077
3078 /*
3079 * sense command
3080 */
53222b90 3081 cp->phys.cmd.addr = CCB_BA(cp, sensecmd);
1da177e4
LT		 3082 cp->phys.cmd.size = cpu_to_scr(6);
3083
3084 /*
3085 * patch requested size into sense command
3086 */
3087 cp->sensecmd[0] = REQUEST_SENSE;
3088 cp->sensecmd[1] = 0;
3089 if (cp->cmd->device->scsi_level <= SCSI_2 && cp->lun <= 7)
3090 cp->sensecmd[1] = cp->lun << 5;
3091 cp->sensecmd[4] = SYM_SNS_BBUF_LEN;
3092 cp->data_len = SYM_SNS_BBUF_LEN;
3093
3094 /*
3095 * sense data
3096 */
3097 memset(cp->sns_bbuf, 0, SYM_SNS_BBUF_LEN);
53222b90 3098 cp->phys.sense.addr = CCB_BA(cp, sns_bbuf);
1da177e4
LT		 3099 cp->phys.sense.size = cpu_to_scr(SYM_SNS_BBUF_LEN);
3100
3101 /*
3102 * requeue the command.
3103 */
3104 startp = SCRIPTB_BA(np, sdata_in);
3105
3106 cp->phys.head.savep = cpu_to_scr(startp);
3107 cp->phys.head.lastp = cpu_to_scr(startp);
3108 cp->startp = cpu_to_scr(startp);
3109 cp->goalp = cpu_to_scr(startp + 16);
3110
3111 cp->host_xflags = 0;
3112 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY;
3113 cp->ssss_status = S_ILLEGAL;
3114 cp->host_flags = (HF_SENSE|HF_DATA_IN);
3115 cp->xerr_status = 0;
3116 cp->extra_bytes = 0;
3117
3118 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA(np, select));
3119
3120 /*
3121 * Requeue the command.
3122 */
3123 sym_put_start_queue(np, cp);
3124
3125 /*
3126 * Give back to upper layer everything we have dequeued.
3127 */
3128 sym_flush_comp_queue(np, 0);
3129 break;
3130 }
3131}
3132
3133/*
3134 * After a device has accepted some management message
3135 * as BUS DEVICE RESET, ABORT TASK, etc ..., or when
3136 * a device signals a UNIT ATTENTION condition, some
3137 * tasks are thrown away by the device. We are required
3138 * to reflect that on our tasks list since the device
3139 * will never complete these tasks.
3140 *
3141 * This function move from the BUSY queue to the COMP
3142 * queue all disconnected CCBs for a given target that
3143 * match the following criteria:
3144 * - lun=-1 means any logical UNIT otherwise a given one.
3145 * - task=-1 means any task, otherwise a given one.
3146 */
3147int sym_clear_tasks(struct sym_hcb *np, int cam_status, int target, int lun, int task)
3148{
3149 SYM_QUEHEAD qtmp, *qp;
3150 int i = 0;
3151 struct sym_ccb *cp;
3152
3153 /*
3154 * Move the entire BUSY queue to our temporary queue.
3155 */
3156 sym_que_init(&qtmp);
3157 sym_que_splice(&np->busy_ccbq, &qtmp);
3158 sym_que_init(&np->busy_ccbq);
3159
3160 /*
3161 * Put all CCBs that matches our criteria into
3162 * the COMP queue and put back other ones into
3163 * the BUSY queue.
3164 */
3165 while ((qp = sym_remque_head(&qtmp)) != 0) {
3166 struct scsi_cmnd *cmd;
3167 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
3168 cmd = cp->cmd;
3169 if (cp->host_status != HS_DISCONNECT ||
3170 cp->target != target ||
3171 (lun != -1 && cp->lun != lun) ||
3172 (task != -1 &&
3173 (cp->tag != NO_TAG && cp->scsi_smsg[2] != task))) {
3174 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq);
3175 continue;
3176 }
3177 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq);
3178
3179 /* Preserve the software timeout condition */
53222b90 3180 if (sym_get_cam_status(cmd) != DID_TIME_OUT)
1da177e4
LT		 3181 sym_set_cam_status(cmd, cam_status);
3182 ++i;
3183#if 0
3184printf("XXXX TASK @%p CLEARED\n", cp);
3185#endif
3186 }
3187 return i;
3188}
3189
3190/*
3191 * chip handler for TASKS recovery
3192 *
3193 * We cannot safely abort a command, while the SCRIPTS
3194 * processor is running, since we just would be in race
3195 * with it.
3196 *
3197 * As long as we have tasks to abort, we keep the SEM
3198 * bit set in the ISTAT. When this bit is set, the
3199 * SCRIPTS processor interrupts (SIR_SCRIPT_STOPPED)
3200 * each time it enters the scheduler.
3201 *
3202 * If we have to reset a target, clear tasks of a unit,
3203 * or to perform the abort of a disconnected job, we
3204 * restart the SCRIPTS for selecting the target. Once
3205 * selected, the SCRIPTS interrupts (SIR_TARGET_SELECTED).
3206 * If it loses arbitration, the SCRIPTS will interrupt again
3207 * the next time it will enter its scheduler, and so on ...
3208 *
3209 * On SIR_TARGET_SELECTED, we scan for the more
3210 * appropriate thing to do:
3211 *
3212 * - If nothing, we just sent a M_ABORT message to the
3213 * target to get rid of the useless SCSI bus ownership.
3214 * According to the specs, no tasks shall be affected.
3215 * - If the target is to be reset, we send it a M_RESET
3216 * message.
3217 * - If a logical UNIT is to be cleared , we send the
3218 * IDENTIFY(lun) + M_ABORT.
3219 * - If an untagged task is to be aborted, we send the
3220 * IDENTIFY(lun) + M_ABORT.
3221 * - If a tagged task is to be aborted, we send the
3222 * IDENTIFY(lun) + task attributes + M_ABORT_TAG.
3223 *
3224 * Once our 'kiss of death' :) message has been accepted
3225 * by the target, the SCRIPTS interrupts again
3226 * (SIR_ABORT_SENT). On this interrupt, we complete
3227 * all the CCBs that should have been aborted by the
3228 * target according to our message.
3229 */
3230static void sym_sir_task_recovery(struct sym_hcb *np, int num)
3231{
3232 SYM_QUEHEAD *qp;
3233 struct sym_ccb *cp;
3234 struct sym_tcb *tp = NULL; /* gcc isn't quite smart enough yet */
3235 struct scsi_target *starget;
3236 int target=-1, lun=-1, task;
3237 int i, k;
3238
3239 switch(num) {
3240 /*
3241 * The SCRIPTS processor stopped before starting
3242 * the next command in order to allow us to perform
3243 * some task recovery.
3244 */
3245 case SIR_SCRIPT_STOPPED:
3246 /*
3247 * Do we have any target to reset or unit to clear ?
3248 */
3249 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
3250 tp = &np->target[i];
3251 if (tp->to_reset ||
3252 (tp->lun0p && tp->lun0p->to_clear)) {
3253 target = i;
3254 break;
3255 }
3256 if (!tp->lunmp)
3257 continue;
3258 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) {
3259 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) {
3260 target = i;
3261 break;
3262 }
3263 }
3264 if (target != -1)
3265 break;
3266 }
3267
3268 /*
3269 * If not, walk the busy queue for any
3270 * disconnected CCB to be aborted.
3271 */
3272 if (target == -1) {
3273 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
3274 cp = sym_que_entry(qp,struct sym_ccb,link_ccbq);
3275 if (cp->host_status != HS_DISCONNECT)
3276 continue;
3277 if (cp->to_abort) {
3278 target = cp->target;
3279 break;
3280 }
3281 }
3282 }
3283
3284 /*
3285 * If some target is to be selected,
3286 * prepare and start the selection.
3287 */
3288 if (target != -1) {
3289 tp = &np->target[target];
3290 np->abrt_sel.sel_id = target;
3291 np->abrt_sel.sel_scntl3 = tp->head.wval;
3292 np->abrt_sel.sel_sxfer = tp->head.sval;
3293 OUTL(np, nc_dsa, np->hcb_ba);
3294 OUTL_DSP(np, SCRIPTB_BA(np, sel_for_abort));
3295 return;
3296 }
3297
3298 /*
3299 * Now look for a CCB to abort that haven't started yet.
3300 * Btw, the SCRIPTS processor is still stopped, so
3301 * we are not in race.
3302 */
3303 i = 0;
3304 cp = NULL;
3305 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
3306 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
3307 if (cp->host_status != HS_BUSY &&
3308 cp->host_status != HS_NEGOTIATE)
3309 continue;
3310 if (!cp->to_abort)
3311 continue;
3312#ifdef SYM_CONF_IARB_SUPPORT
3313 /*
3314 * If we are using IMMEDIATE ARBITRATION, we donnot
3315 * want to cancel the last queued CCB, since the
3316 * SCRIPTS may have anticipated the selection.
3317 */
3318 if (cp == np->last_cp) {
3319 cp->to_abort = 0;
3320 continue;
3321 }
3322#endif
3323 i = 1; /* Means we have found some */
3324 break;
3325 }
3326 if (!i) {
3327 /*
3328 * We are done, so we donnot need
3329 * to synchronize with the SCRIPTS anylonger.
3330 * Remove the SEM flag from the ISTAT.
3331 */
3332 np->istat_sem = 0;
3333 OUTB(np, nc_istat, SIGP);
3334 break;
3335 }
3336 /*
3337 * Compute index of next position in the start
3338 * queue the SCRIPTS intends to start and dequeue
3339 * all CCBs for that device that haven't been started.
3340 */
3341 i = (INL(np, nc_scratcha) - np->squeue_ba) / 4;
3342 i = sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1);
3343
3344 /*
3345 * Make sure at least our IO to abort has been dequeued.
3346 */
3347#ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING
53222b90 3348 assert(i && sym_get_cam_status(cp->cmd) == DID_SOFT_ERROR);
1da177e4
LT		 3349#else
3350 sym_remque(&cp->link_ccbq);
3351 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq);
3352#endif
3353 /*
3354 * Keep track in cam status of the reason of the abort.
3355 */
3356 if (cp->to_abort == 2)
53222b90 3357 sym_set_cam_status(cp->cmd, DID_TIME_OUT);
1da177e4 3358 else
53222b90 3359 sym_set_cam_status(cp->cmd, DID_ABORT);
1da177e4
LT		 3360
3361 /*
3362 * Complete with error everything that we have dequeued.
3363 */
3364 sym_flush_comp_queue(np, 0);
3365 break;
3366 /*
3367 * The SCRIPTS processor has selected a target
3368 * we may have some manual recovery to perform for.
3369 */
3370 case SIR_TARGET_SELECTED:
3371 target = INB(np, nc_sdid) & 0xf;
3372 tp = &np->target[target];
3373
3374 np->abrt_tbl.addr = cpu_to_scr(vtobus(np->abrt_msg));
3375
3376 /*
3377 * If the target is to be reset, prepare a
3378 * M_RESET message and clear the to_reset flag
3379 * since we donnot expect this operation to fail.
3380 */
3381 if (tp->to_reset) {
3382 np->abrt_msg[0] = M_RESET;
3383 np->abrt_tbl.size = 1;
3384 tp->to_reset = 0;
3385 break;
3386 }
3387
3388 /*
3389 * Otherwise, look for some logical unit to be cleared.
3390 */
3391 if (tp->lun0p && tp->lun0p->to_clear)
3392 lun = 0;
3393 else if (tp->lunmp) {
3394 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) {
3395 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) {
3396 lun = k;
3397 break;
3398 }
3399 }
3400 }
3401
3402 /*
3403 * If a logical unit is to be cleared, prepare
3404 * an IDENTIFY(lun) + ABORT MESSAGE.
3405 */
3406 if (lun != -1) {
3407 struct sym_lcb *lp = sym_lp(tp, lun);
3408 lp->to_clear = 0; /* We don't expect to fail here */
3409 np->abrt_msg[0] = IDENTIFY(0, lun);
3410 np->abrt_msg[1] = M_ABORT;
3411 np->abrt_tbl.size = 2;
3412 break;
3413 }
3414
3415 /*
3416 * Otherwise, look for some disconnected job to
3417 * abort for this target.
3418 */
3419 i = 0;
3420 cp = NULL;
3421 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
3422 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
3423 if (cp->host_status != HS_DISCONNECT)
3424 continue;
3425 if (cp->target != target)
3426 continue;
3427 if (!cp->to_abort)
3428 continue;
3429 i = 1; /* Means we have some */
3430 break;
3431 }
3432
3433 /*
3434 * If we have none, probably since the device has
3435 * completed the command before we won abitration,
3436 * send a M_ABORT message without IDENTIFY.
3437 * According to the specs, the device must just
3438 * disconnect the BUS and not abort any task.
3439 */
3440 if (!i) {
3441 np->abrt_msg[0] = M_ABORT;
3442 np->abrt_tbl.size = 1;
3443 break;
3444 }
3445
3446 /*
3447 * We have some task to abort.
3448 * Set the IDENTIFY(lun)
3449 */
3450 np->abrt_msg[0] = IDENTIFY(0, cp->lun);
3451
3452 /*
3453 * If we want to abort an untagged command, we
3454 * will send a IDENTIFY + M_ABORT.
3455 * Otherwise (tagged command), we will send
3456 * a IDENTITFY + task attributes + ABORT TAG.
3457 */
3458 if (cp->tag == NO_TAG) {
3459 np->abrt_msg[1] = M_ABORT;
3460 np->abrt_tbl.size = 2;
3461 } else {
3462 np->abrt_msg[1] = cp->scsi_smsg[1];
3463 np->abrt_msg[2] = cp->scsi_smsg[2];
3464 np->abrt_msg[3] = M_ABORT_TAG;
3465 np->abrt_tbl.size = 4;
3466 }
3467 /*
3468 * Keep track of software timeout condition, since the
3469 * peripheral driver may not count retries on abort
3470 * conditions not due to timeout.
3471 */
3472 if (cp->to_abort == 2)
53222b90 3473 sym_set_cam_status(cp->cmd, DID_TIME_OUT);
1da177e4
LT		 3474 cp->to_abort = 0; /* We donnot expect to fail here */
3475 break;
3476
3477 /*
3478 * The target has accepted our message and switched
3479 * to BUS FREE phase as we expected.
3480 */
3481 case SIR_ABORT_SENT:
3482 target = INB(np, nc_sdid) & 0xf;
3483 tp = &np->target[target];
53222b90 3484 starget = tp->starget;
1da177e4
LT		 3485
3486 /*
3487 ** If we didn't abort anything, leave here.
3488 */
3489 if (np->abrt_msg[0] == M_ABORT)
3490 break;
3491
3492 /*
3493 * If we sent a M_RESET, then a hardware reset has
3494 * been performed by the target.
3495 * - Reset everything to async 8 bit
3496 * - Tell ourself to negotiate next time :-)
3497 * - Prepare to clear all disconnected CCBs for
3498 * this target from our task list (lun=task=-1)
3499 */
3500 lun = -1;
3501 task = -1;
3502 if (np->abrt_msg[0] == M_RESET) {
3503 tp->head.sval = 0;
3504 tp->head.wval = np->rv_scntl3;
3505 tp->head.uval = 0;
3506 spi_period(starget) = 0;
3507 spi_offset(starget) = 0;
3508 spi_width(starget) = 0;
3509 spi_iu(starget) = 0;
3510 spi_dt(starget) = 0;
3511 spi_qas(starget) = 0;
3512 tp->tgoal.check_nego = 1;
3513 }
3514
3515 /*
3516 * Otherwise, check for the LUN and TASK(s)
3517 * concerned by the cancelation.
3518 * If it is not ABORT_TAG then it is CLEAR_QUEUE
3519 * or an ABORT message :-)
3520 */
3521 else {
3522 lun = np->abrt_msg[0] & 0x3f;
3523 if (np->abrt_msg[1] == M_ABORT_TAG)
3524 task = np->abrt_msg[2];
3525 }
3526
3527 /*
3528 * Complete all the CCBs the device should have
3529 * aborted due to our 'kiss of death' message.
3530 */
3531 i = (INL(np, nc_scratcha) - np->squeue_ba) / 4;
3532 sym_dequeue_from_squeue(np, i, target, lun, -1);
53222b90 3533 sym_clear_tasks(np, DID_ABORT, target, lun, task);
1da177e4
LT		 3534 sym_flush_comp_queue(np, 0);
3535
3536 /*
3537 * If we sent a BDR, make upper layer aware of that.
3538 */
3539 if (np->abrt_msg[0] == M_RESET)
3540 sym_xpt_async_sent_bdr(np, target);
3541 break;
3542 }
3543
3544 /*
3545 * Print to the log the message we intend to send.
3546 */
3547 if (num == SIR_TARGET_SELECTED) {
53222b90 3548 dev_info(&tp->starget->dev, "control msgout:");
1da177e4
LT		 3549 sym_printl_hex(np->abrt_msg, np->abrt_tbl.size);
3550 np->abrt_tbl.size = cpu_to_scr(np->abrt_tbl.size);
3551 }
3552
3553 /*
3554 * Let the SCRIPTS processor continue.
3555 */
3556 OUTONB_STD();
3557}
3558
3559/*
3560 * Gerard's alchemy:) that deals with with the data
3561 * pointer for both MDP and the residual calculation.
3562 *
3563 * I didn't want to bloat the code by more than 200
3564 * lines for the handling of both MDP and the residual.
3565 * This has been achieved by using a data pointer
3566 * representation consisting in an index in the data
3567 * array (dp_sg) and a negative offset (dp_ofs) that
3568 * have the following meaning:
3569 *
3570 * - dp_sg = SYM_CONF_MAX_SG
3571 * we are at the end of the data script.
3572 * - dp_sg < SYM_CONF_MAX_SG
3573 * dp_sg points to the next entry of the scatter array
3574 * we want to transfer.
3575 * - dp_ofs < 0
3576 * dp_ofs represents the residual of bytes of the
3577 * previous entry scatter entry we will send first.
3578 * - dp_ofs = 0
3579 * no residual to send first.
3580 *
3581 * The function sym_evaluate_dp() accepts an arbitray
3582 * offset (basically from the MDP message) and returns
3583 * the corresponding values of dp_sg and dp_ofs.
3584 */
3585
3586static int sym_evaluate_dp(struct sym_hcb *np, struct sym_ccb *cp, u32 scr, int *ofs)
3587{
3588 u32 dp_scr;
3589 int dp_ofs, dp_sg, dp_sgmin;
3590 int tmp;
3591 struct sym_pmc *pm;
3592
3593 /*
3594 * Compute the resulted data pointer in term of a script
3595 * address within some DATA script and a signed byte offset.
3596 */
3597 dp_scr = scr;
3598 dp_ofs = *ofs;
3599 if (dp_scr == SCRIPTA_BA(np, pm0_data))
3600 pm = &cp->phys.pm0;
3601 else if (dp_scr == SCRIPTA_BA(np, pm1_data))
3602 pm = &cp->phys.pm1;
3603 else
3604 pm = NULL;
3605
3606 if (pm) {
3607 dp_scr = scr_to_cpu(pm->ret);
e2230eac 3608 dp_ofs -= scr_to_cpu(pm->sg.size) & 0x00ffffff;
1da177e4
LT		 3609 }
3610
3611 /*
3612 * If we are auto-sensing, then we are done.
3613 */
3614 if (cp->host_flags & HF_SENSE) {
3615 *ofs = dp_ofs;
3616 return 0;
3617 }
3618
3619 /*
3620 * Deduce the index of the sg entry.
3621 * Keep track of the index of the first valid entry.
3622 * If result is dp_sg = SYM_CONF_MAX_SG, then we are at the
3623 * end of the data.
3624 */
44f30b0f 3625 tmp = scr_to_cpu(cp->goalp);
1da177e4
LT		 3626 dp_sg = SYM_CONF_MAX_SG;
3627 if (dp_scr != tmp)
3628 dp_sg -= (tmp - 8 - (int)dp_scr) / (2*4);
3629 dp_sgmin = SYM_CONF_MAX_SG - cp->segments;
3630
3631 /*
3632 * Move to the sg entry the data pointer belongs to.
3633 *
3634 * If we are inside the data area, we expect result to be:
3635 *
3636 * Either,
3637 * dp_ofs = 0 and dp_sg is the index of the sg entry
3638 * the data pointer belongs to (or the end of the data)
3639 * Or,
3640 * dp_ofs < 0 and dp_sg is the index of the sg entry
3641 * the data pointer belongs to + 1.
3642 */
3643 if (dp_ofs < 0) {
3644 int n;
3645 while (dp_sg > dp_sgmin) {
3646 --dp_sg;
3647 tmp = scr_to_cpu(cp->phys.data[dp_sg].size);
3648 n = dp_ofs + (tmp & 0xffffff);
3649 if (n > 0) {
3650 ++dp_sg;
3651 break;
3652 }
3653 dp_ofs = n;
3654 }
3655 }
3656 else if (dp_ofs > 0) {
3657 while (dp_sg < SYM_CONF_MAX_SG) {
3658 tmp = scr_to_cpu(cp->phys.data[dp_sg].size);
3659 dp_ofs -= (tmp & 0xffffff);
3660 ++dp_sg;
3661 if (dp_ofs <= 0)
3662 break;
3663 }
3664 }
3665
3666 /*
3667 * Make sure the data pointer is inside the data area.
3668 * If not, return some error.
3669 */
3670 if (dp_sg < dp_sgmin || (dp_sg == dp_sgmin && dp_ofs < 0))
3671 goto out_err;
3672 else if (dp_sg > SYM_CONF_MAX_SG ||
3673 (dp_sg == SYM_CONF_MAX_SG && dp_ofs > 0))
3674 goto out_err;
3675
3676 /*
3677 * Save the extreme pointer if needed.
3678 */
3679 if (dp_sg > cp->ext_sg ||
3680 (dp_sg == cp->ext_sg && dp_ofs > cp->ext_ofs)) {
3681 cp->ext_sg = dp_sg;
3682 cp->ext_ofs = dp_ofs;
3683 }
3684
3685 /*
3686 * Return data.
3687 */
3688 *ofs = dp_ofs;
3689 return dp_sg;
3690
3691out_err:
3692 return -1;
3693}
3694
3695/*
3696 * chip handler for MODIFY DATA POINTER MESSAGE
3697 *
3698 * We also call this function on IGNORE WIDE RESIDUE
3699 * messages that do not match a SWIDE full condition.
3700 * Btw, we assume in that situation that such a message
3701 * is equivalent to a MODIFY DATA POINTER (offset=-1).
3702 */
3703
3704static void sym_modify_dp(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp, int ofs)
3705{
3706 int dp_ofs = ofs;
3707 u32 dp_scr = sym_get_script_dp (np, cp);
3708 u32 dp_ret;
3709 u32 tmp;
3710 u_char hflags;
3711 int dp_sg;
3712 struct sym_pmc *pm;
3713
3714 /*
3715 * Not supported for auto-sense.
3716 */
3717 if (cp->host_flags & HF_SENSE)
3718 goto out_reject;
3719
3720 /*
3721 * Apply our alchemy:) (see comments in sym_evaluate_dp()),
3722 * to the resulted data pointer.
3723 */
3724 dp_sg = sym_evaluate_dp(np, cp, dp_scr, &dp_ofs);
3725 if (dp_sg < 0)
3726 goto out_reject;
3727
3728 /*
3729 * And our alchemy:) allows to easily calculate the data
3730 * script address we want to return for the next data phase.
3731 */
44f30b0f 3732 dp_ret = cpu_to_scr(cp->goalp);
1da177e4
LT		 3733 dp_ret = dp_ret - 8 - (SYM_CONF_MAX_SG - dp_sg) * (2*4);
3734
3735 /*
3736 * If offset / scatter entry is zero we donnot need
3737 * a context for the new current data pointer.
3738 */
3739 if (dp_ofs == 0) {
3740 dp_scr = dp_ret;
3741 goto out_ok;
3742 }
3743
3744 /*
3745 * Get a context for the new current data pointer.
3746 */
3747 hflags = INB(np, HF_PRT);
3748
3749 if (hflags & HF_DP_SAVED)
3750 hflags ^= HF_ACT_PM;
3751
3752 if (!(hflags & HF_ACT_PM)) {
3753 pm = &cp->phys.pm0;
3754 dp_scr = SCRIPTA_BA(np, pm0_data);
3755 }
3756 else {
3757 pm = &cp->phys.pm1;
3758 dp_scr = SCRIPTA_BA(np, pm1_data);
3759 }
3760
3761 hflags &= ~(HF_DP_SAVED);
3762
3763 OUTB(np, HF_PRT, hflags);
3764
3765 /*
3766 * Set up the new current data pointer.
3767 * ofs < 0 there, and for the next data phase, we
3768 * want to transfer part of the data of the sg entry
3769 * corresponding to index dp_sg-1 prior to returning
3770 * to the main data script.
3771 */
3772 pm->ret = cpu_to_scr(dp_ret);
3773 tmp = scr_to_cpu(cp->phys.data[dp_sg-1].addr);
3774 tmp += scr_to_cpu(cp->phys.data[dp_sg-1].size) + dp_ofs;
3775 pm->sg.addr = cpu_to_scr(tmp);
3776 pm->sg.size = cpu_to_scr(-dp_ofs);
3777
3778out_ok:
3779 sym_set_script_dp (np, cp, dp_scr);
3780 OUTL_DSP(np, SCRIPTA_BA(np, clrack));
3781 return;
3782
3783out_reject:
3784 OUTL_DSP(np, SCRIPTB_BA(np, msg_bad));
3785}
3786
3787
3788/*
3789 * chip calculation of the data residual.
3790 *
3791 * As I used to say, the requirement of data residual
3792 * in SCSI is broken, useless and cannot be achieved
3793 * without huge complexity.
3794 * But most OSes and even the official CAM require it.
3795 * When stupidity happens to be so widely spread inside
3796 * a community, it gets hard to convince.
3797 *
3798 * Anyway, I don't care, since I am not going to use
3799 * any software that considers this data residual as
3800 * a relevant information. :)
3801 */
3802
3803int sym_compute_residual(struct sym_hcb *np, struct sym_ccb *cp)
3804{
3805 int dp_sg, dp_sgmin, resid = 0;
3806 int dp_ofs = 0;
3807
3808 /*
3809 * Check for some data lost or just thrown away.
3810 * We are not required to be quite accurate in this
3811 * situation. Btw, if we are odd for output and the
3812 * device claims some more data, it may well happen
3813 * than our residual be zero. :-)
3814 */
3815 if (cp->xerr_status & (XE_EXTRA_DATA|XE_SODL_UNRUN|XE_SWIDE_OVRUN)) {
3816 if (cp->xerr_status & XE_EXTRA_DATA)
3817 resid -= cp->extra_bytes;
3818 if (cp->xerr_status & XE_SODL_UNRUN)
3819 ++resid;
3820 if (cp->xerr_status & XE_SWIDE_OVRUN)
3821 --resid;
3822 }
3823
3824 /*
3825 * If all data has been transferred,
3826 * there is no residual.
3827 */
44f30b0f 3828 if (cp->phys.head.lastp == cp->goalp)
1da177e4
LT		 3829 return resid;
3830
3831 /*
3832 * If no data transfer occurs, or if the data
3833 * pointer is weird, return full residual.
3834 */
3835 if (cp->startp == cp->phys.head.lastp ||
3836 sym_evaluate_dp(np, cp, scr_to_cpu(cp->phys.head.lastp),
3837 &dp_ofs) < 0) {
3838 return cp->data_len;
3839 }
3840
3841 /*
3842 * If we were auto-sensing, then we are done.
3843 */
3844 if (cp->host_flags & HF_SENSE) {
3845 return -dp_ofs;
3846 }
3847
3848 /*
3849 * We are now full comfortable in the computation
3850 * of the data residual (2's complement).
3851 */
3852 dp_sgmin = SYM_CONF_MAX_SG - cp->segments;
3853 resid = -cp->ext_ofs;
3854 for (dp_sg = cp->ext_sg; dp_sg < SYM_CONF_MAX_SG; ++dp_sg) {
3855 u_int tmp = scr_to_cpu(cp->phys.data[dp_sg].size);
3856 resid += (tmp & 0xffffff);
3857 }
3858
53222b90
MW		 3859 resid -= cp->odd_byte_adjustment;
3860
1da177e4
LT		 3861 /*
3862 * Hopefully, the result is not too wrong.
3863 */
3864 return resid;
3865}
3866
3867/*
3868 * Negotiation for WIDE and SYNCHRONOUS DATA TRANSFER.
3869 *
3870 * When we try to negotiate, we append the negotiation message
3871 * to the identify and (maybe) simple tag message.
3872 * The host status field is set to HS_NEGOTIATE to mark this
3873 * situation.
3874 *
3875 * If the target doesn't answer this message immediately
3876 * (as required by the standard), the SIR_NEGO_FAILED interrupt
3877 * will be raised eventually.
3878 * The handler removes the HS_NEGOTIATE status, and sets the
3879 * negotiated value to the default (async / nowide).
3880 *
3881 * If we receive a matching answer immediately, we check it
3882 * for validity, and set the values.
3883 *
3884 * If we receive a Reject message immediately, we assume the
3885 * negotiation has failed, and fall back to standard values.
3886 *
3887 * If we receive a negotiation message while not in HS_NEGOTIATE
3888 * state, it's a target initiated negotiation. We prepare a
3889 * (hopefully) valid answer, set our parameters, and send back
3890 * this answer to the target.
3891 *
3892 * If the target doesn't fetch the answer (no message out phase),
3893 * we assume the negotiation has failed, and fall back to default
3894 * settings (SIR_NEGO_PROTO interrupt).
3895 *
3896 * When we set the values, we adjust them in all ccbs belonging
3897 * to this target, in the controller's register, and in the "phys"
3898 * field of the controller's struct sym_hcb.
3899 */
3900
3901/*
3902 * chip handler for SYNCHRONOUS DATA TRANSFER REQUEST (SDTR) message.
3903 */
3904static int
3905sym_sync_nego_check(struct sym_hcb *np, int req, struct sym_ccb *cp)
3906{
3907 int target = cp->target;
3908 u_char chg, ofs, per, fak, div;
3909
3910 if (DEBUG_FLAGS & DEBUG_NEGO) {
3911 sym_print_nego_msg(np, target, "sync msgin", np->msgin);
3912 }
3913
3914 /*
3915 * Get requested values.
3916 */
3917 chg = 0;
3918 per = np->msgin[3];
3919 ofs = np->msgin[4];
3920
3921 /*
3922 * Check values against our limits.
3923 */
3924 if (ofs) {
3925 if (ofs > np->maxoffs)
3926 {chg = 1; ofs = np->maxoffs;}
3927 }
3928
3929 if (ofs) {
3930 if (per < np->minsync)
3931 {chg = 1; per = np->minsync;}
3932 }
3933
3934 /*
3935 * Get new chip synchronous parameters value.
3936 */
3937 div = fak = 0;
3938 if (ofs && sym_getsync(np, 0, per, &div, &fak) < 0)
3939 goto reject_it;
3940
3941 if (DEBUG_FLAGS & DEBUG_NEGO) {
3942 sym_print_addr(cp->cmd,
3943 "sdtr: ofs=%d per=%d div=%d fak=%d chg=%d.\n",
3944 ofs, per, div, fak, chg);
3945 }
3946
3947 /*
3948 * If it was an answer we want to change,
3949 * then it isn't acceptable. Reject it.
3950 */
3951 if (!req && chg)
3952 goto reject_it;
3953
3954 /*
3955 * Apply new values.
3956 */
3957 sym_setsync (np, target, ofs, per, div, fak);
3958
3959 /*
3960 * It was an answer. We are done.
3961 */
3962 if (!req)
3963 return 0;
3964
3965 /*
3966 * It was a request. Prepare an answer message.
3967 */
6ea3c0b2 3968 spi_populate_sync_msg(np->msgout, per, ofs);
1da177e4
LT		 3969
3970 if (DEBUG_FLAGS & DEBUG_NEGO) {
3971 sym_print_nego_msg(np, target, "sync msgout", np->msgout);
3972 }
3973
3974 np->msgin [0] = M_NOOP;
3975
3976 return 0;
3977
3978reject_it:
3979 sym_setsync (np, target, 0, 0, 0, 0);
3980 return -1;
3981}
3982
3983static void sym_sync_nego(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp)
3984{
3985 int req = 1;
3986 int result;
3987
3988 /*
3989 * Request or answer ?
3990 */
3991 if (INB(np, HS_PRT) == HS_NEGOTIATE) {
3992 OUTB(np, HS_PRT, HS_BUSY);
3993 if (cp->nego_status && cp->nego_status != NS_SYNC)
3994 goto reject_it;
3995 req = 0;
3996 }
3997
3998 /*
3999 * Check and apply new values.
4000 */
4001 result = sym_sync_nego_check(np, req, cp);
4002 if (result) /* Not acceptable, reject it */
4003 goto reject_it;
4004 if (req) { /* Was a request, send response. */
4005 cp->nego_status = NS_SYNC;
4006 OUTL_DSP(np, SCRIPTB_BA(np, sdtr_resp));
4007 }
4008 else /* Was a response, we are done. */
4009 OUTL_DSP(np, SCRIPTA_BA(np, clrack));
4010 return;
4011
4012reject_it:
4013 OUTL_DSP(np, SCRIPTB_BA(np, msg_bad));
4014}
4015
4016/*
4017 * chip handler for PARALLEL PROTOCOL REQUEST (PPR) message.
4018 */
4019static int
4020sym_ppr_nego_check(struct sym_hcb *np, int req, int target)
4021{
4022 struct sym_tcb *tp = &np->target[target];
4023 unsigned char fak, div;
4024 int dt, chg = 0;
4025
4026 unsigned char per = np->msgin[3];
4027 unsigned char ofs = np->msgin[5];
4028 unsigned char wide = np->msgin[6];
4029 unsigned char opts = np->msgin[7] & PPR_OPT_MASK;
4030
4031 if (DEBUG_FLAGS & DEBUG_NEGO) {
4032 sym_print_nego_msg(np, target, "ppr msgin", np->msgin);
4033 }
4034
4035 /*
4036 * Check values against our limits.
4037 */
4038 if (wide > np->maxwide) {
4039 chg = 1;
4040 wide = np->maxwide;
4041 }
4042 if (!wide || !(np->features & FE_U3EN))
4043 opts = 0;
4044
4045 if (opts != (np->msgin[7] & PPR_OPT_MASK))
4046 chg = 1;
4047
4048 dt = opts & PPR_OPT_DT;
4049
4050 if (ofs) {
4051 unsigned char maxoffs = dt ? np->maxoffs_dt : np->maxoffs;
4052 if (ofs > maxoffs) {
4053 chg = 1;
4054 ofs = maxoffs;
4055 }
4056 }
4057
4058 if (ofs) {
4059 unsigned char minsync = dt ? np->minsync_dt : np->minsync;
4060 if (per < minsync) {
4061 chg = 1;
4062 per = minsync;
4063 }
4064 }
4065
4066 /*
4067 * Get new chip synchronous parameters value.
4068 */
4069 div = fak = 0;
4070 if (ofs && sym_getsync(np, dt, per, &div, &fak) < 0)
4071 goto reject_it;
4072
4073 /*
4074 * If it was an answer we want to change,
4075 * then it isn't acceptable. Reject it.
4076 */
4077 if (!req && chg)
4078 goto reject_it;
4079
4080 /*
4081 * Apply new values.
4082 */
4083 sym_setpprot(np, target, opts, ofs, per, wide, div, fak);
4084
4085 /*
4086 * It was an answer. We are done.
4087 */
4088 if (!req)
4089 return 0;
4090
4091 /*
4092 * It was a request. Prepare an answer message.
4093 */
6ea3c0b2 4094 spi_populate_ppr_msg(np->msgout, per, ofs, wide, opts);
1da177e4
LT		 4095
4096 if (DEBUG_FLAGS & DEBUG_NEGO) {
4097 sym_print_nego_msg(np, target, "ppr msgout", np->msgout);
4098 }
4099
4100 np->msgin [0] = M_NOOP;
4101
4102 return 0;
4103
4104reject_it:
4105 sym_setpprot (np, target, 0, 0, 0, 0, 0, 0);
4106 /*
4107 * If it is a device response that should result in
4108 * ST, we may want to try a legacy negotiation later.
4109 */
4110 if (!req && !opts) {
4111 tp->tgoal.period = per;
4112 tp->tgoal.offset = ofs;
4113 tp->tgoal.width = wide;
4114 tp->tgoal.iu = tp->tgoal.dt = tp->tgoal.qas = 0;
4115 tp->tgoal.check_nego = 1;
4116 }
4117 return -1;
4118}
4119
4120static void sym_ppr_nego(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp)
4121{
4122 int req = 1;
4123 int result;
4124
4125 /*
4126 * Request or answer ?
4127 */
4128 if (INB(np, HS_PRT) == HS_NEGOTIATE) {
4129 OUTB(np, HS_PRT, HS_BUSY);
4130 if (cp->nego_status && cp->nego_status != NS_PPR)
4131 goto reject_it;
4132 req = 0;
4133 }
4134
4135 /*
4136 * Check and apply new values.
4137 */
4138 result = sym_ppr_nego_check(np, req, cp->target);
4139 if (result) /* Not acceptable, reject it */
4140 goto reject_it;
4141 if (req) { /* Was a request, send response. */
4142 cp->nego_status = NS_PPR;
4143 OUTL_DSP(np, SCRIPTB_BA(np, ppr_resp));
4144 }
4145 else /* Was a response, we are done. */
4146 OUTL_DSP(np, SCRIPTA_BA(np, clrack));
4147 return;
4148
4149reject_it:
4150 OUTL_DSP(np, SCRIPTB_BA(np, msg_bad));
4151}
4152
4153/*
4154 * chip handler for WIDE DATA TRANSFER REQUEST (WDTR) message.
4155 */
4156static int
4157sym_wide_nego_check(struct sym_hcb *np, int req, struct sym_ccb *cp)
4158{
4159 int target = cp->target;
4160 u_char chg, wide;
4161
4162 if (DEBUG_FLAGS & DEBUG_NEGO) {
4163 sym_print_nego_msg(np, target, "wide msgin", np->msgin);
4164 }
4165
4166 /*
4167 * Get requested values.
4168 */
4169 chg = 0;
4170 wide = np->msgin[3];
4171
4172 /*
4173 * Check values against our limits.
4174 */
4175 if (wide > np->maxwide) {
4176 chg = 1;
4177 wide = np->maxwide;
4178 }
4179
4180 if (DEBUG_FLAGS & DEBUG_NEGO) {
4181 sym_print_addr(cp->cmd, "wdtr: wide=%d chg=%d.\n",
4182 wide, chg);
4183 }
4184
4185 /*
4186 * If it was an answer we want to change,
4187 * then it isn't acceptable. Reject it.
4188 */
4189 if (!req && chg)
4190 goto reject_it;
4191
4192 /*
4193 * Apply new values.
4194 */
4195 sym_setwide (np, target, wide);
4196
4197 /*
4198 * It was an answer. We are done.
4199 */
4200 if (!req)
4201 return 0;
4202
4203 /*
4204 * It was a request. Prepare an answer message.
4205 */
6ea3c0b2 4206 spi_populate_width_msg(np->msgout, wide);
1da177e4
LT		 4207
4208 np->msgin [0] = M_NOOP;
4209
4210 if (DEBUG_FLAGS & DEBUG_NEGO) {
4211 sym_print_nego_msg(np, target, "wide msgout", np->msgout);
4212 }
4213
4214 return 0;
4215
4216reject_it:
4217 return -1;
4218}
4219
4220static void sym_wide_nego(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp)
4221{
4222 int req = 1;
4223 int result;
4224
4225 /*
4226 * Request or answer ?
4227 */
4228 if (INB(np, HS_PRT) == HS_NEGOTIATE) {
4229 OUTB(np, HS_PRT, HS_BUSY);
4230 if (cp->nego_status && cp->nego_status != NS_WIDE)
4231 goto reject_it;
4232 req = 0;
4233 }
4234
4235 /*
4236 * Check and apply new values.
4237 */
4238 result = sym_wide_nego_check(np, req, cp);
4239 if (result) /* Not acceptable, reject it */
4240 goto reject_it;
4241 if (req) { /* Was a request, send response. */
4242 cp->nego_status = NS_WIDE;
4243 OUTL_DSP(np, SCRIPTB_BA(np, wdtr_resp));
4244 } else { /* Was a response. */
4245 /*
4246 * Negotiate for SYNC immediately after WIDE response.
4247 * This allows to negotiate for both WIDE and SYNC on
4248 * a single SCSI command (Suggested by Justin Gibbs).
4249 */
4250 if (tp->tgoal.offset) {
6ea3c0b2
MW		 4251 spi_populate_sync_msg(np->msgout, tp->tgoal.period,
4252 tp->tgoal.offset);
1da177e4
LT		 4253
4254 if (DEBUG_FLAGS & DEBUG_NEGO) {
4255 sym_print_nego_msg(np, cp->target,
4256 "sync msgout", np->msgout);
4257 }
4258
4259 cp->nego_status = NS_SYNC;
4260 OUTB(np, HS_PRT, HS_NEGOTIATE);
4261 OUTL_DSP(np, SCRIPTB_BA(np, sdtr_resp));
4262 return;
4263 } else
4264 OUTL_DSP(np, SCRIPTA_BA(np, clrack));
4265 }
4266
4267 return;
4268
4269reject_it:
4270 OUTL_DSP(np, SCRIPTB_BA(np, msg_bad));
4271}
4272
4273/*
4274 * Reset DT, SYNC or WIDE to default settings.
4275 *
4276 * Called when a negotiation does not succeed either
4277 * on rejection or on protocol error.
4278 *
4279 * A target that understands a PPR message should never
4280 * reject it, and messing with it is very unlikely.
4281 * So, if a PPR makes problems, we may just want to
4282 * try a legacy negotiation later.
4283 */
4284static void sym_nego_default(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp)
4285{
4286 switch (cp->nego_status) {
4287 case NS_PPR:
4288#if 0
4289 sym_setpprot (np, cp->target, 0, 0, 0, 0, 0, 0);
4290#else
4291 if (tp->tgoal.period < np->minsync)
4292 tp->tgoal.period = np->minsync;
4293 if (tp->tgoal.offset > np->maxoffs)
4294 tp->tgoal.offset = np->maxoffs;
4295 tp->tgoal.iu = tp->tgoal.dt = tp->tgoal.qas = 0;
4296 tp->tgoal.check_nego = 1;
4297#endif
4298 break;
4299 case NS_SYNC:
4300 sym_setsync (np, cp->target, 0, 0, 0, 0);
4301 break;
4302 case NS_WIDE:
4303 sym_setwide (np, cp->target, 0);
4304 break;
4305 }
4306 np->msgin [0] = M_NOOP;
4307 np->msgout[0] = M_NOOP;
4308 cp->nego_status = 0;
4309}
4310
4311/*
4312 * chip handler for MESSAGE REJECT received in response to
4313 * PPR, WIDE or SYNCHRONOUS negotiation.
4314 */
4315static void sym_nego_rejected(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp)
4316{
4317 sym_nego_default(np, tp, cp);
4318 OUTB(np, HS_PRT, HS_BUSY);
4319}
4320
4321/*
4322 * chip exception handler for programmed interrupts.
4323 */
4324static void sym_int_sir (struct sym_hcb *np)
4325{
4326 u_char num = INB(np, nc_dsps);
4327 u32 dsa = INL(np, nc_dsa);
4328 struct sym_ccb *cp = sym_ccb_from_dsa(np, dsa);
4329 u_char target = INB(np, nc_sdid) & 0x0f;
4330 struct sym_tcb *tp = &np->target[target];
4331 int tmp;
4332
4333 if (DEBUG_FLAGS & DEBUG_TINY) printf ("I#%d", num);
4334
4335 switch (num) {
4336#if SYM_CONF_DMA_ADDRESSING_MODE == 2
4337 /*
4338 * SCRIPTS tell us that we may have to update
4339 * 64 bit DMA segment registers.
4340 */
4341 case SIR_DMAP_DIRTY:
4342 sym_update_dmap_regs(np);
4343 goto out;
4344#endif
4345 /*
4346 * Command has been completed with error condition
4347 * or has been auto-sensed.
4348 */
4349 case SIR_COMPLETE_ERROR:
4350 sym_complete_error(np, cp);
4351 return;
4352 /*
4353 * The C code is currently trying to recover from something.
4354 * Typically, user want to abort some command.
4355 */
4356 case SIR_SCRIPT_STOPPED:
4357 case SIR_TARGET_SELECTED:
4358 case SIR_ABORT_SENT:
4359 sym_sir_task_recovery(np, num);
4360 return;
4361 /*
4362 * The device didn't go to MSG OUT phase after having
4363 * been selected with ATN. We donnot want to handle
4364 * that.
4365 */
4366 case SIR_SEL_ATN_NO_MSG_OUT:
4367 printf ("%s:%d: No MSG OUT phase after selection with ATN.\n",
4368 sym_name (np), target);
4369 goto out_stuck;
4370 /*
4371 * The device didn't switch to MSG IN phase after
4372 * having reseleted the initiator.
4373 */
4374 case SIR_RESEL_NO_MSG_IN:
4375 printf ("%s:%d: No MSG IN phase after reselection.\n",
4376 sym_name (np), target);
4377 goto out_stuck;
4378 /*
4379 * After reselection, the device sent a message that wasn't
4380 * an IDENTIFY.
4381 */
4382 case SIR_RESEL_NO_IDENTIFY:
4383 printf ("%s:%d: No IDENTIFY after reselection.\n",
4384 sym_name (np), target);
4385 goto out_stuck;
4386 /*
4387 * The device reselected a LUN we donnot know about.
4388 */
4389 case SIR_RESEL_BAD_LUN:
4390 np->msgout[0] = M_RESET;
4391 goto out;
4392 /*
4393 * The device reselected for an untagged nexus and we
4394 * haven't any.
4395 */
4396 case SIR_RESEL_BAD_I_T_L:
4397 np->msgout[0] = M_ABORT;
4398 goto out;
4399 /*
4400 * The device reselected for a tagged nexus that we donnot
4401 * have.
4402 */
4403 case SIR_RESEL_BAD_I_T_L_Q:
4404 np->msgout[0] = M_ABORT_TAG;
4405 goto out;
4406 /*
4407 * The SCRIPTS let us know that the device has grabbed
4408 * our message and will abort the job.
4409 */
4410 case SIR_RESEL_ABORTED:
4411 np->lastmsg = np->msgout[0];
4412 np->msgout[0] = M_NOOP;
4413 printf ("%s:%d: message %x sent on bad reselection.\n",
4414 sym_name (np), target, np->lastmsg);
4415 goto out;
4416 /*
4417 * The SCRIPTS let us know that a message has been
4418 * successfully sent to the device.
4419 */
4420 case SIR_MSG_OUT_DONE:
4421 np->lastmsg = np->msgout[0];
4422 np->msgout[0] = M_NOOP;
4423 /* Should we really care of that */
4424 if (np->lastmsg == M_PARITY || np->lastmsg == M_ID_ERROR) {
4425 if (cp) {
4426 cp->xerr_status &= ~XE_PARITY_ERR;
4427 if (!cp->xerr_status)
4428 OUTOFFB(np, HF_PRT, HF_EXT_ERR);
4429 }
4430 }
4431 goto out;
4432 /*
4433 * The device didn't send a GOOD SCSI status.
4434 * We may have some work to do prior to allow
4435 * the SCRIPTS processor to continue.
4436 */
4437 case SIR_BAD_SCSI_STATUS:
4438 if (!cp)
4439 goto out;
4440 sym_sir_bad_scsi_status(np, num, cp);
4441 return;
4442 /*
4443 * We are asked by the SCRIPTS to prepare a
4444 * REJECT message.
4445 */
4446 case SIR_REJECT_TO_SEND:
4447 sym_print_msg(cp, "M_REJECT to send for ", np->msgin);
4448 np->msgout[0] = M_REJECT;
4449 goto out;
4450 /*
4451 * We have been ODD at the end of a DATA IN
4452 * transfer and the device didn't send a
4453 * IGNORE WIDE RESIDUE message.
4454 * It is a data overrun condition.
4455 */
4456 case SIR_SWIDE_OVERRUN:
4457 if (cp) {
4458 OUTONB(np, HF_PRT, HF_EXT_ERR);
4459 cp->xerr_status |= XE_SWIDE_OVRUN;
4460 }
4461 goto out;
4462 /*
4463 * We have been ODD at the end of a DATA OUT
4464 * transfer.
4465 * It is a data underrun condition.
4466 */
4467 case SIR_SODL_UNDERRUN:
4468 if (cp) {
4469 OUTONB(np, HF_PRT, HF_EXT_ERR);
4470 cp->xerr_status |= XE_SODL_UNRUN;
4471 }
4472 goto out;
4473 /*
4474 * The device wants us to tranfer more data than
4475 * expected or in the wrong direction.
4476 * The number of extra bytes is in scratcha.
4477 * It is a data overrun condition.
4478 */
4479 case SIR_DATA_OVERRUN:
4480 if (cp) {
4481 OUTONB(np, HF_PRT, HF_EXT_ERR);
4482 cp->xerr_status |= XE_EXTRA_DATA;
4483 cp->extra_bytes += INL(np, nc_scratcha);
4484 }
4485 goto out;
4486 /*
4487 * The device switched to an illegal phase (4/5).
4488 */
4489 case SIR_BAD_PHASE:
4490 if (cp) {
4491 OUTONB(np, HF_PRT, HF_EXT_ERR);
4492 cp->xerr_status |= XE_BAD_PHASE;
4493 }
4494 goto out;
4495 /*
4496 * We received a message.
4497 */
4498 case SIR_MSG_RECEIVED:
4499 if (!cp)
4500 goto out_stuck;
4501 switch (np->msgin [0]) {
4502 /*
4503 * We received an extended message.
4504 * We handle MODIFY DATA POINTER, SDTR, WDTR
4505 * and reject all other extended messages.
4506 */
4507 case M_EXTENDED:
4508 switch (np->msgin [2]) {
4509 case M_X_MODIFY_DP:
4510 if (DEBUG_FLAGS & DEBUG_POINTER)
92d578b9 4511 sym_print_msg(cp, NULL, np->msgin);
1da177e4
LT		 4512 tmp = (np->msgin[3]<<24) + (np->msgin[4]<<16) +
4513 (np->msgin[5]<<8) + (np->msgin[6]);
4514 sym_modify_dp(np, tp, cp, tmp);
4515 return;
4516 case M_X_SYNC_REQ:
4517 sym_sync_nego(np, tp, cp);
4518 return;
4519 case M_X_PPR_REQ:
4520 sym_ppr_nego(np, tp, cp);
4521 return;
4522 case M_X_WIDE_REQ:
4523 sym_wide_nego(np, tp, cp);
4524 return;
4525 default:
4526 goto out_reject;
4527 }
4528 break;
4529 /*
4530 * We received a 1/2 byte message not handled from SCRIPTS.
4531 * We are only expecting MESSAGE REJECT and IGNORE WIDE
4532 * RESIDUE messages that haven't been anticipated by
4533 * SCRIPTS on SWIDE full condition. Unanticipated IGNORE
4534 * WIDE RESIDUE messages are aliased as MODIFY DP (-1).
4535 */
4536 case M_IGN_RESIDUE:
4537 if (DEBUG_FLAGS & DEBUG_POINTER)
92d578b9 4538 sym_print_msg(cp, NULL, np->msgin);
1da177e4
LT		 4539 if (cp->host_flags & HF_SENSE)
4540 OUTL_DSP(np, SCRIPTA_BA(np, clrack));
4541 else
4542 sym_modify_dp(np, tp, cp, -1);
4543 return;
4544 case M_REJECT:
4545 if (INB(np, HS_PRT) == HS_NEGOTIATE)
4546 sym_nego_rejected(np, tp, cp);
4547 else {
4548 sym_print_addr(cp->cmd,
4549 "M_REJECT received (%x:%x).\n",
4550 scr_to_cpu(np->lastmsg), np->msgout[0]);
4551 }
4552 goto out_clrack;
4553 break;
4554 default:
4555 goto out_reject;
4556 }
4557 break;
4558 /*
4559 * We received an unknown message.
4560 * Ignore all MSG IN phases and reject it.
4561 */
4562 case SIR_MSG_WEIRD:
4563 sym_print_msg(cp, "WEIRD message received", np->msgin);
4564 OUTL_DSP(np, SCRIPTB_BA(np, msg_weird));
4565 return;
4566 /*
4567 * Negotiation failed.
4568 * Target does not send us the reply.
4569 * Remove the HS_NEGOTIATE status.
4570 */
4571 case SIR_NEGO_FAILED:
4572 OUTB(np, HS_PRT, HS_BUSY);
4573 /*
4574 * Negotiation failed.
4575 * Target does not want answer message.
4576 */
4577 case SIR_NEGO_PROTO:
4578 sym_nego_default(np, tp, cp);
4579 goto out;
4580 }
4581
4582out:
4583 OUTONB_STD();
4584 return;
4585out_reject:
4586 OUTL_DSP(np, SCRIPTB_BA(np, msg_bad));
4587 return;
4588out_clrack:
4589 OUTL_DSP(np, SCRIPTA_BA(np, clrack));
4590 return;
4591out_stuck:
4592 return;
4593}
4594
4595/*
4596 * Acquire a control block
4597 */
4598struct sym_ccb *sym_get_ccb (struct sym_hcb *np, struct scsi_cmnd *cmd, u_char tag_order)
4599{
4600 u_char tn = cmd->device->id;
4601 u_char ln = cmd->device->lun;
4602 struct sym_tcb *tp = &np->target[tn];
4603 struct sym_lcb *lp = sym_lp(tp, ln);
4604 u_short tag = NO_TAG;
4605 SYM_QUEHEAD *qp;
4606 struct sym_ccb *cp = NULL;
4607
4608 /*
4609 * Look for a free CCB
4610 */
4611 if (sym_que_empty(&np->free_ccbq))
4612 sym_alloc_ccb(np);
4613 qp = sym_remque_head(&np->free_ccbq);
4614 if (!qp)
4615 goto out;
4616 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
4617
84e203a2 4618 {
1da177e4
LT		 4619 /*
4620 * If we have been asked for a tagged command.
4621 */
4622 if (tag_order) {
4623 /*
4624 * Debugging purpose.
4625 */
4626#ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING
3bea15a7
MW		 4627 if (lp->busy_itl != 0)
4628 goto out_free;
1da177e4
LT		 4629#endif
4630 /*
4631 * Allocate resources for tags if not yet.
4632 */
4633 if (!lp->cb_tags) {
4634 sym_alloc_lcb_tags(np, tn, ln);
4635 if (!lp->cb_tags)
4636 goto out_free;
4637 }
4638 /*
4639 * Get a tag for this SCSI IO and set up
4640 * the CCB bus address for reselection,
4641 * and count it for this LUN.
4642 * Toggle reselect path to tagged.
4643 */
4644 if (lp->busy_itlq < SYM_CONF_MAX_TASK) {
4645 tag = lp->cb_tags[lp->ia_tag];
4646 if (++lp->ia_tag == SYM_CONF_MAX_TASK)
4647 lp->ia_tag = 0;
4648 ++lp->busy_itlq;
4649#ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING
4650 lp->itlq_tbl[tag] = cpu_to_scr(cp->ccb_ba);
4651 lp->head.resel_sa =
4652 cpu_to_scr(SCRIPTA_BA(np, resel_tag));
4653#endif
4654#ifdef SYM_OPT_LIMIT_COMMAND_REORDERING
4655 cp->tags_si = lp->tags_si;
4656 ++lp->tags_sum[cp->tags_si];
4657 ++lp->tags_since;
4658#endif
4659 }
4660 else
4661 goto out_free;
4662 }
4663 /*
4664 * This command will not be tagged.
4665 * If we already have either a tagged or untagged
4666 * one, refuse to overlap this untagged one.
4667 */
4668 else {
4669 /*
4670 * Debugging purpose.
4671 */
4672#ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING
3bea15a7
MW		 4673 if (lp->busy_itl != 0 || lp->busy_itlq != 0)
4674 goto out_free;
1da177e4
LT		 4675#endif
4676 /*
4677 * Count this nexus for this LUN.
4678 * Set up the CCB bus address for reselection.
4679 * Toggle reselect path to untagged.
4680 */
4681 ++lp->busy_itl;
4682#ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING
4683 if (lp->busy_itl == 1) {
4684 lp->head.itl_task_sa = cpu_to_scr(cp->ccb_ba);
4685 lp->head.resel_sa =
4686 cpu_to_scr(SCRIPTA_BA(np, resel_no_tag));
4687 }
4688 else
4689 goto out_free;
4690#endif
4691 }
4692 }
4693 /*
4694 * Put the CCB into the busy queue.
4695 */
4696 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq);
4697#ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
4698 if (lp) {
4699 sym_remque(&cp->link2_ccbq);
4700 sym_insque_tail(&cp->link2_ccbq, &lp->waiting_ccbq);
4701 }
4702
4703#endif
1da177e4 4704 cp->to_abort = 0;
53222b90 4705 cp->odd_byte_adjustment = 0;
1da177e4
LT		 4706 cp->tag = tag;
4707 cp->order = tag_order;
4708 cp->target = tn;
4709 cp->lun = ln;
4710
4711 if (DEBUG_FLAGS & DEBUG_TAGS) {
4712 sym_print_addr(cmd, "ccb @%p using tag %d.\n", cp, tag);
4713 }
4714
4715out:
4716 return cp;
4717out_free:
4718 sym_insque_head(&cp->link_ccbq, &np->free_ccbq);
4719 return NULL;
4720}
4721
4722/*
4723 * Release one control block
4724 */
4725void sym_free_ccb (struct sym_hcb *np, struct sym_ccb *cp)
4726{
4727 struct sym_tcb *tp = &np->target[cp->target];
4728 struct sym_lcb *lp = sym_lp(tp, cp->lun);
4729
4730 if (DEBUG_FLAGS & DEBUG_TAGS) {
4731 sym_print_addr(cp->cmd, "ccb @%p freeing tag %d.\n",
4732 cp, cp->tag);
4733 }
4734
4735 /*
4736 * If LCB available,
4737 */
4738 if (lp) {
4739 /*
4740 * If tagged, release the tag, set the relect path
4741 */
4742 if (cp->tag != NO_TAG) {
4743#ifdef SYM_OPT_LIMIT_COMMAND_REORDERING
4744 --lp->tags_sum[cp->tags_si];
4745#endif
4746 /*
4747 * Free the tag value.
4748 */
4749 lp->cb_tags[lp->if_tag] = cp->tag;
4750 if (++lp->if_tag == SYM_CONF_MAX_TASK)
4751 lp->if_tag = 0;
4752 /*
4753 * Make the reselect path invalid,
4754 * and uncount this CCB.
4755 */
4756 lp->itlq_tbl[cp->tag] = cpu_to_scr(np->bad_itlq_ba);
4757 --lp->busy_itlq;
4758 } else { /* Untagged */
4759 /*
4760 * Make the reselect path invalid,
4761 * and uncount this CCB.
4762 */
4763 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba);
4764 --lp->busy_itl;
4765 }
4766 /*
4767 * If no JOB active, make the LUN reselect path invalid.
4768 */
4769 if (lp->busy_itlq == 0 && lp->busy_itl == 0)
4770 lp->head.resel_sa =
4771 cpu_to_scr(SCRIPTB_BA(np, resel_bad_lun));
4772 }
1da177e4
LT		 4773
4774 /*
4775 * We donnot queue more than 1 ccb per target
4776 * with negotiation at any time. If this ccb was
4777 * used for negotiation, clear this info in the tcb.
4778 */
4779 if (cp == tp->nego_cp)
4780 tp->nego_cp = NULL;
4781
4782#ifdef SYM_CONF_IARB_SUPPORT
4783 /*
4784 * If we just complete the last queued CCB,
4785 * clear this info that is no longer relevant.
4786 */
4787 if (cp == np->last_cp)
4788 np->last_cp = 0;
4789#endif
4790
4791 /*
4792 * Make this CCB available.
4793 */
4794 cp->cmd = NULL;
4795 cp->host_status = HS_IDLE;
4796 sym_remque(&cp->link_ccbq);
4797 sym_insque_head(&cp->link_ccbq, &np->free_ccbq);
4798
4799#ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
4800 if (lp) {
4801 sym_remque(&cp->link2_ccbq);
4802 sym_insque_tail(&cp->link2_ccbq, &np->dummy_ccbq);
4803 if (cp->started) {
4804 if (cp->tag != NO_TAG)
4805 --lp->started_tags;
4806 else
4807 --lp->started_no_tag;
4808 }
4809 }
4810 cp->started = 0;
4811#endif
4812}
4813
4814/*
4815 * Allocate a CCB from memory and initialize its fixed part.
4816 */
4817static struct sym_ccb *sym_alloc_ccb(struct sym_hcb *np)
4818{
4819 struct sym_ccb *cp = NULL;
4820 int hcode;
4821
4822 /*
4823 * Prevent from allocating more CCBs than we can
4824 * queue to the controller.
4825 */
4826 if (np->actccbs >= SYM_CONF_MAX_START)
4827 return NULL;
4828
4829 /*
4830 * Allocate memory for this CCB.
4831 */
4832 cp = sym_calloc_dma(sizeof(struct sym_ccb), "CCB");
4833 if (!cp)
4834 goto out_free;
4835
4836 /*
4837 * Count it.
4838 */
4839 np->actccbs++;
4840
4841 /*
4842 * Compute the bus address of this ccb.
4843 */
4844 cp->ccb_ba = vtobus(cp);
4845
4846 /*
4847 * Insert this ccb into the hashed list.
4848 */
4849 hcode = CCB_HASH_CODE(cp->ccb_ba);
4850 cp->link_ccbh = np->ccbh[hcode];
4851 np->ccbh[hcode] = cp;
4852
4853 /*
4854 * Initialyze the start and restart actions.
4855 */
4856 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA(np, idle));
4857 cp->phys.head.go.restart = cpu_to_scr(SCRIPTB_BA(np, bad_i_t_l));
4858
4859 /*
4860 * Initilialyze some other fields.
4861 */
4862 cp->phys.smsg_ext.addr = cpu_to_scr(HCB_BA(np, msgin[2]));
4863
4864 /*
4865 * Chain into free ccb queue.
4866 */
4867 sym_insque_head(&cp->link_ccbq, &np->free_ccbq);
4868
4869 /*
4870 * Chain into optionnal lists.
4871 */
4872#ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
4873 sym_insque_head(&cp->link2_ccbq, &np->dummy_ccbq);
4874#endif
4875 return cp;
4876out_free:
4877 if (cp)
4878 sym_mfree_dma(cp, sizeof(*cp), "CCB");
4879 return NULL;
4880}
4881
4882/*
4883 * Look up a CCB from a DSA value.
4884 */
4885static struct sym_ccb *sym_ccb_from_dsa(struct sym_hcb *np, u32 dsa)
4886{
4887 int hcode;
4888 struct sym_ccb *cp;
4889
4890 hcode = CCB_HASH_CODE(dsa);
4891 cp = np->ccbh[hcode];
4892 while (cp) {
4893 if (cp->ccb_ba == dsa)
4894 break;
4895 cp = cp->link_ccbh;
4896 }
4897
4898 return cp;
4899}
4900
4901/*
4902 * Target control block initialisation.
4903 * Nothing important to do at the moment.
4904 */
4905static void sym_init_tcb (struct sym_hcb *np, u_char tn)
4906{
4907#if 0 /* Hmmm... this checking looks paranoid. */
4908 /*
4909 * Check some alignments required by the chip.
4910 */
4911 assert (((offsetof(struct sym_reg, nc_sxfer) ^
4912 offsetof(struct sym_tcb, head.sval)) &3) == 0);
4913 assert (((offsetof(struct sym_reg, nc_scntl3) ^
4914 offsetof(struct sym_tcb, head.wval)) &3) == 0);
4915#endif
4916}
4917
4918/*
4919 * Lun control block allocation and initialization.
4920 */
4921struct sym_lcb *sym_alloc_lcb (struct sym_hcb *np, u_char tn, u_char ln)
4922{
4923 struct sym_tcb *tp = &np->target[tn];
84e203a2 4924 struct sym_lcb *lp = NULL;
1da177e4
LT		 4925
4926 /*
4927 * Initialize the target control block if not yet.
4928 */
4929 sym_init_tcb (np, tn);
4930
4931 /*
4932 * Allocate the LCB bus address array.
4933 * Compute the bus address of this table.
4934 */
4935 if (ln && !tp->luntbl) {
4936 int i;
4937
4938 tp->luntbl = sym_calloc_dma(256, "LUNTBL");
4939 if (!tp->luntbl)
4940 goto fail;
4941 for (i = 0 ; i < 64 ; i++)
4942 tp->luntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa));
4943 tp->head.luntbl_sa = cpu_to_scr(vtobus(tp->luntbl));
4944 }
4945
4946 /*
4947 * Allocate the table of pointers for LUN(s) > 0, if needed.
4948 */
4949 if (ln && !tp->lunmp) {
4950 tp->lunmp = kcalloc(SYM_CONF_MAX_LUN, sizeof(struct sym_lcb *),
4951 GFP_KERNEL);
4952 if (!tp->lunmp)
4953 goto fail;
4954 }
4955
4956 /*
4957 * Allocate the lcb.
4958 * Make it available to the chip.
4959 */
4960 lp = sym_calloc_dma(sizeof(struct sym_lcb), "LCB");
4961 if (!lp)
4962 goto fail;
4963 if (ln) {
4964 tp->lunmp[ln] = lp;
4965 tp->luntbl[ln] = cpu_to_scr(vtobus(lp));
4966 }
4967 else {
4968 tp->lun0p = lp;
4969 tp->head.lun0_sa = cpu_to_scr(vtobus(lp));
4970 }
4971
4972 /*
4973 * Let the itl task point to error handling.
4974 */
4975 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba);
4976
4977 /*
4978 * Set the reselect pattern to our default. :)
4979 */
4980 lp->head.resel_sa = cpu_to_scr(SCRIPTB_BA(np, resel_bad_lun));
4981
4982 /*
4983 * Set user capabilities.
4984 */
4985 lp->user_flags = tp->usrflags & (SYM_DISC_ENABLED | SYM_TAGS_ENABLED);
4986
4987#ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
4988 /*
4989 * Initialize device queueing.
4990 */
4991 sym_que_init(&lp->waiting_ccbq);
4992 sym_que_init(&lp->started_ccbq);
4993 lp->started_max = SYM_CONF_MAX_TASK;
4994 lp->started_limit = SYM_CONF_MAX_TASK;
4995#endif
84e203a2 4996
1da177e4
LT		 4997fail:
4998 return lp;
4999}
5000
5001/*
5002 * Allocate LCB resources for tagged command queuing.
5003 */
5004static void sym_alloc_lcb_tags (struct sym_hcb *np, u_char tn, u_char ln)
5005{
5006 struct sym_tcb *tp = &np->target[tn];
5007 struct sym_lcb *lp = sym_lp(tp, ln);
5008 int i;
5009
1da177e4
LT		 5010 /*
5011 * Allocate the task table and and the tag allocation
5012 * circular buffer. We want both or none.
5013 */
5014 lp->itlq_tbl = sym_calloc_dma(SYM_CONF_MAX_TASK*4, "ITLQ_TBL");
5015 if (!lp->itlq_tbl)
5016 goto fail;
53222b90 5017 lp->cb_tags = kcalloc(SYM_CONF_MAX_TASK, 1, GFP_ATOMIC);
1da177e4
LT		 5018 if (!lp->cb_tags) {
5019 sym_mfree_dma(lp->itlq_tbl, SYM_CONF_MAX_TASK*4, "ITLQ_TBL");
5020 lp->itlq_tbl = NULL;
5021 goto fail;
5022 }
5023
5024 /*
5025 * Initialize the task table with invalid entries.
5026 */
5027 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++)
5028 lp->itlq_tbl[i] = cpu_to_scr(np->notask_ba);
5029
5030 /*
5031 * Fill up the tag buffer with tag numbers.
5032 */
5033 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++)
5034 lp->cb_tags[i] = i;
5035
5036 /*
5037 * Make the task table available to SCRIPTS,
5038 * And accept tagged commands now.
5039 */
5040 lp->head.itlq_tbl_sa = cpu_to_scr(vtobus(lp->itlq_tbl));
5041
5042 return;
5043fail:
5044 return;
5045}
5046
5047/*
5048 * Queue a SCSI IO to the controller.
5049 */
5050int sym_queue_scsiio(struct sym_hcb *np, struct scsi_cmnd *cmd, struct sym_ccb *cp)
5051{
5052 struct scsi_device *sdev = cmd->device;
5053 struct sym_tcb *tp;
5054 struct sym_lcb *lp;
5055 u_char *msgptr;
5056 u_int msglen;
5057 int can_disconnect;
5058
5059 /*
5060 * Keep track of the IO in our CCB.
5061 */
5062 cp->cmd = cmd;
5063
5064 /*
5065 * Retrieve the target descriptor.
5066 */
5067 tp = &np->target[cp->target];
5068
5069 /*
5070 * Retrieve the lun descriptor.
5071 */
5072 lp = sym_lp(tp, sdev->lun);
5073
5074 can_disconnect = (cp->tag != NO_TAG) ||
5075 (lp && (lp->curr_flags & SYM_DISC_ENABLED));
5076
5077 msgptr = cp->scsi_smsg;
5078 msglen = 0;
5079 msgptr[msglen++] = IDENTIFY(can_disconnect, sdev->lun);
5080
5081 /*
5082 * Build the tag message if present.
5083 */
5084 if (cp->tag != NO_TAG) {
5085 u_char order = cp->order;
5086
5087 switch(order) {
5088 case M_ORDERED_TAG:
5089 break;
5090 case M_HEAD_TAG:
5091 break;
5092 default:
5093 order = M_SIMPLE_TAG;
5094 }
5095#ifdef SYM_OPT_LIMIT_COMMAND_REORDERING
5096 /*
5097 * Avoid too much reordering of SCSI commands.
5098 * The algorithm tries to prevent completion of any
5099 * tagged command from being delayed against more
5100 * than 3 times the max number of queued commands.
5101 */
5102 if (lp && lp->tags_since > 3*SYM_CONF_MAX_TAG) {
5103 lp->tags_si = !(lp->tags_si);
5104 if (lp->tags_sum[lp->tags_si]) {
5105 order = M_ORDERED_TAG;
5106 if ((DEBUG_FLAGS & DEBUG_TAGS)||sym_verbose>1) {
5107 sym_print_addr(cmd,
5108 "ordered tag forced.\n");
5109 }
5110 }
5111 lp->tags_since = 0;
5112 }
5113#endif
5114 msgptr[msglen++] = order;
5115
5116 /*
5117 * For less than 128 tags, actual tags are numbered
5118 * 1,3,5,..2*MAXTAGS+1,since we may have to deal
5119 * with devices that have problems with #TAG 0 or too
5120 * great #TAG numbers. For more tags (up to 256),
5121 * we use directly our tag number.
5122 */
5123#if SYM_CONF_MAX_TASK > (512/4)
5124 msgptr[msglen++] = cp->tag;
5125#else
5126 msgptr[msglen++] = (cp->tag << 1) + 1;
5127#endif
5128 }
5129
5130 /*
5131 * Build a negotiation message if needed.
5132 * (nego_status is filled by sym_prepare_nego())
5133 */
5134 cp->nego_status = 0;
5135 if (tp->tgoal.check_nego && !tp->nego_cp && lp) {
5136 msglen += sym_prepare_nego(np, cp, msgptr + msglen);
5137 }
5138
5139 /*
5140 * Startqueue
5141 */
5142 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA(np, select));
5143 cp->phys.head.go.restart = cpu_to_scr(SCRIPTA_BA(np, resel_dsa));
5144
5145 /*
5146 * select
5147 */
5148 cp->phys.select.sel_id = cp->target;
5149 cp->phys.select.sel_scntl3 = tp->head.wval;
5150 cp->phys.select.sel_sxfer = tp->head.sval;
5151 cp->phys.select.sel_scntl4 = tp->head.uval;
5152
5153 /*
5154 * message
5155 */
53222b90 5156 cp->phys.smsg.addr = CCB_BA(cp, scsi_smsg);
1da177e4
LT		 5157 cp->phys.smsg.size = cpu_to_scr(msglen);
5158
5159 /*
5160 * status
5161 */
5162 cp->host_xflags = 0;
5163 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY;
5164 cp->ssss_status = S_ILLEGAL;
5165 cp->xerr_status = 0;
5166 cp->host_flags = 0;
5167 cp->extra_bytes = 0;
5168
5169 /*
5170 * extreme data pointer.
5171 * shall be positive, so -1 is lower than lowest.:)
5172 */
5173 cp->ext_sg = -1;
5174 cp->ext_ofs = 0;
5175
5176 /*
5177 * Build the CDB and DATA descriptor block
5178 * and start the IO.
5179 */
5180 return sym_setup_data_and_start(np, cmd, cp);
5181}
5182
5183/*
5184 * Reset a SCSI target (all LUNs of this target).
5185 */
5186int sym_reset_scsi_target(struct sym_hcb *np, int target)
5187{
5188 struct sym_tcb *tp;
5189
5190 if (target == np->myaddr || (u_int)target >= SYM_CONF_MAX_TARGET)
5191 return -1;
5192
5193 tp = &np->target[target];
5194 tp->to_reset = 1;
5195
5196 np->istat_sem = SEM;
5197 OUTB(np, nc_istat, SIGP|SEM);
5198
5199 return 0;
5200}
5201
5202/*
5203 * Abort a SCSI IO.
5204 */
5205static int sym_abort_ccb(struct sym_hcb *np, struct sym_ccb *cp, int timed_out)
5206{
5207 /*
5208 * Check that the IO is active.
5209 */
5210 if (!cp || !cp->host_status || cp->host_status == HS_WAIT)
5211 return -1;
5212
5213 /*
5214 * If a previous abort didn't succeed in time,
5215 * perform a BUS reset.
5216 */
5217 if (cp->to_abort) {
5218 sym_reset_scsi_bus(np, 1);
5219 return 0;
5220 }
5221
5222 /*
5223 * Mark the CCB for abort and allow time for.
5224 */
5225 cp->to_abort = timed_out ? 2 : 1;
5226
5227 /*
5228 * Tell the SCRIPTS processor to stop and synchronize with us.
5229 */
5230 np->istat_sem = SEM;
5231 OUTB(np, nc_istat, SIGP|SEM);
5232 return 0;
5233}
5234
5235int sym_abort_scsiio(struct sym_hcb *np, struct scsi_cmnd *cmd, int timed_out)
5236{
5237 struct sym_ccb *cp;
5238 SYM_QUEHEAD *qp;
5239
5240 /*
5241 * Look up our CCB control block.
5242 */
5243 cp = NULL;
5244 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
5245 struct sym_ccb *cp2 = sym_que_entry(qp, struct sym_ccb, link_ccbq);
5246 if (cp2->cmd == cmd) {
5247 cp = cp2;
5248 break;
5249 }
5250 }
5251
5252 return sym_abort_ccb(np, cp, timed_out);
5253}
5254
5255/*
53222b90 5256 * Complete execution of a SCSI command with extended
1da177e4
LT		 5257 * error, SCSI status error, or having been auto-sensed.
5258 *
5259 * The SCRIPTS processor is not running there, so we
5260 * can safely access IO registers and remove JOBs from
5261 * the START queue.
5262 * SCRATCHA is assumed to have been loaded with STARTPOS
5263 * before the SCRIPTS called the C code.
5264 */
5265void sym_complete_error(struct sym_hcb *np, struct sym_ccb *cp)
5266{
5267 struct scsi_device *sdev;
5268 struct scsi_cmnd *cmd;
5269 struct sym_tcb *tp;
5270 struct sym_lcb *lp;
5271 int resid;
5272 int i;
5273
5274 /*
5275 * Paranoid check. :)
5276 */
5277 if (!cp || !cp->cmd)
5278 return;
5279
5280 cmd = cp->cmd;
5281 sdev = cmd->device;
5282 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_RESULT)) {
5283 dev_info(&sdev->sdev_gendev, "CCB=%p STAT=%x/%x/%x\n", cp,
5284 cp->host_status, cp->ssss_status, cp->host_flags);
5285 }
5286
5287 /*
5288 * Get target and lun pointers.
5289 */
5290 tp = &np->target[cp->target];
5291 lp = sym_lp(tp, sdev->lun);
5292
5293 /*
5294 * Check for extended errors.
5295 */
5296 if (cp->xerr_status) {
5297 if (sym_verbose)
5298 sym_print_xerr(cmd, cp->xerr_status);
5299 if (cp->host_status == HS_COMPLETE)
5300 cp->host_status = HS_COMP_ERR;
5301 }
5302
5303 /*
5304 * Calculate the residual.
5305 */
5306 resid = sym_compute_residual(np, cp);
5307
5308 if (!SYM_SETUP_RESIDUAL_SUPPORT) {/* If user does not want residuals */
5309 resid = 0; /* throw them away. :) */
5310 cp->sv_resid = 0;
5311 }
5312#ifdef DEBUG_2_0_X
5313if (resid)
5314 printf("XXXX RESID= %d - 0x%x\n", resid, resid);
5315#endif
5316
5317 /*
5318 * Dequeue all queued CCBs for that device
5319 * not yet started by SCRIPTS.
5320 */
5321 i = (INL(np, nc_scratcha) - np->squeue_ba) / 4;
5322 i = sym_dequeue_from_squeue(np, i, cp->target, sdev->lun, -1);
5323
5324 /*
5325 * Restart the SCRIPTS processor.
5326 */
5327 OUTL_DSP(np, SCRIPTA_BA(np, start));
5328
5329#ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
5330 if (cp->host_status == HS_COMPLETE &&
5331 cp->ssss_status == S_QUEUE_FULL) {
5332 if (!lp || lp->started_tags - i < 2)
5333 goto weirdness;
5334 /*
5335 * Decrease queue depth as needed.
5336 */
5337 lp->started_max = lp->started_tags - i - 1;
5338 lp->num_sgood = 0;
5339
5340 if (sym_verbose >= 2) {
5341 sym_print_addr(cmd, " queue depth is now %d\n",
5342 lp->started_max);
5343 }
5344
5345 /*
5346 * Repair the CCB.
5347 */
5348 cp->host_status = HS_BUSY;
5349 cp->ssss_status = S_ILLEGAL;
5350
5351 /*
5352 * Let's requeue it to device.
5353 */
53222b90 5354 sym_set_cam_status(cmd, DID_SOFT_ERROR);
1da177e4
LT		 5355 goto finish;
5356 }
5357weirdness:
5358#endif
5359 /*
5360 * Build result in CAM ccb.
5361 */
5362 sym_set_cam_result_error(np, cp, resid);
5363
5364#ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
5365finish:
5366#endif
5367 /*
5368 * Add this one to the COMP queue.
5369 */
5370 sym_remque(&cp->link_ccbq);
5371 sym_insque_head(&cp->link_ccbq, &np->comp_ccbq);
5372
5373 /*
5374 * Complete all those commands with either error
5375 * or requeue condition.
5376 */
5377 sym_flush_comp_queue(np, 0);
5378
5379#ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
5380 /*
5381 * Donnot start more than 1 command after an error.
5382 */
84e203a2 5383 sym_start_next_ccbs(np, lp, 1);
1da177e4
LT		 5384#endif
5385}
5386
5387/*
5388 * Complete execution of a successful SCSI command.
5389 *
5390 * Only successful commands go to the DONE queue,
5391 * since we need to have the SCRIPTS processor
5392 * stopped on any error condition.
5393 * The SCRIPTS processor is running while we are
5394 * completing successful commands.
5395 */
5396void sym_complete_ok (struct sym_hcb *np, struct sym_ccb *cp)
5397{
5398 struct sym_tcb *tp;
5399 struct sym_lcb *lp;
5400 struct scsi_cmnd *cmd;
5401 int resid;
5402
5403 /*
5404 * Paranoid check. :)
5405 */
5406 if (!cp || !cp->cmd)
5407 return;
5408 assert (cp->host_status == HS_COMPLETE);
5409
5410 /*
5411 * Get user command.
5412 */
5413 cmd = cp->cmd;
5414
5415 /*
5416 * Get target and lun pointers.
5417 */
5418 tp = &np->target[cp->target];
5419 lp = sym_lp(tp, cp->lun);
5420
1da177e4
LT		 5421 /*
5422 * If all data have been transferred, given than no
5423 * extended error did occur, there is no residual.
5424 */
5425 resid = 0;
44f30b0f 5426 if (cp->phys.head.lastp != cp->goalp)
1da177e4
LT		 5427 resid = sym_compute_residual(np, cp);
5428
5429 /*
5430 * Wrong transfer residuals may be worse than just always
5431 * returning zero. User can disable this feature in
5432 * sym53c8xx.h. Residual support is enabled by default.
5433 */
5434 if (!SYM_SETUP_RESIDUAL_SUPPORT)
5435 resid = 0;
5436#ifdef DEBUG_2_0_X
5437if (resid)
5438 printf("XXXX RESID= %d - 0x%x\n", resid, resid);
5439#endif
5440
5441 /*
5442 * Build result in CAM ccb.
5443 */
5444 sym_set_cam_result_ok(cp, cmd, resid);
5445
1da177e4
LT		 5446#ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
5447 /*
5448 * If max number of started ccbs had been reduced,
5449 * increase it if 200 good status received.
5450 */
5451 if (lp && lp->started_max < lp->started_limit) {
5452 ++lp->num_sgood;
5453 if (lp->num_sgood >= 200) {
5454 lp->num_sgood = 0;
5455 ++lp->started_max;
5456 if (sym_verbose >= 2) {
5457 sym_print_addr(cmd, " queue depth is now %d\n",
5458 lp->started_max);
5459 }
5460 }
5461 }
5462#endif
5463
5464 /*
5465 * Free our CCB.
5466 */
5467 sym_free_ccb (np, cp);
5468
5469#ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
5470 /*
5471 * Requeue a couple of awaiting scsi commands.
5472 */
84e203a2 5473 if (!sym_que_empty(&lp->waiting_ccbq))
1da177e4
LT		 5474 sym_start_next_ccbs(np, lp, 2);
5475#endif
5476 /*
5477 * Complete the command.
5478 */
5479 sym_xpt_done(np, cmd);
5480}
5481
5482/*
5483 * Soft-attach the controller.
5484 */
5485int sym_hcb_attach(struct Scsi_Host *shost, struct sym_fw *fw, struct sym_nvram *nvram)
5486{
5487 struct sym_hcb *np = sym_get_hcb(shost);
5488 int i;
5489
5490 /*
5491 * Get some info about the firmware.
5492 */
5493 np->scripta_sz = fw->a_size;
5494 np->scriptb_sz = fw->b_size;
5495 np->scriptz_sz = fw->z_size;
5496 np->fw_setup = fw->setup;
5497 np->fw_patch = fw->patch;
5498 np->fw_name = fw->name;
5499
5500 /*
5501 * Save setting of some IO registers, so we will
5502 * be able to probe specific implementations.
5503 */
5504 sym_save_initial_setting (np);
5505
5506 /*
5507 * Reset the chip now, since it has been reported
5508 * that SCSI clock calibration may not work properly
5509 * if the chip is currently active.
5510 */
5511 sym_chip_reset(np);
5512
5513 /*
5514 * Prepare controller and devices settings, according
5515 * to chip features, user set-up and driver set-up.
5516 */
5517 sym_prepare_setting(shost, np, nvram);
5518
5519 /*
5520 * Check the PCI clock frequency.
5521 * Must be performed after prepare_setting since it destroys
5522 * STEST1 that is used to probe for the clock doubler.
5523 */
5524 i = sym_getpciclock(np);
5525 if (i > 37000 && !(np->features & FE_66MHZ))
5526 printf("%s: PCI BUS clock seems too high: %u KHz.\n",
5527 sym_name(np), i);
5528
5529 /*
5530 * Allocate the start queue.
5531 */
5532 np->squeue = sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"SQUEUE");
5533 if (!np->squeue)
5534 goto attach_failed;
5535 np->squeue_ba = vtobus(np->squeue);
5536
5537 /*
5538 * Allocate the done queue.
5539 */
5540 np->dqueue = sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"DQUEUE");
5541 if (!np->dqueue)
5542 goto attach_failed;
5543 np->dqueue_ba = vtobus(np->dqueue);
5544
5545 /*
5546 * Allocate the target bus address array.
5547 */
5548 np->targtbl = sym_calloc_dma(256, "TARGTBL");
5549 if (!np->targtbl)
5550 goto attach_failed;
5551 np->targtbl_ba = vtobus(np->targtbl);
5552
5553 /*
5554 * Allocate SCRIPTS areas.
5555 */
5556 np->scripta0 = sym_calloc_dma(np->scripta_sz, "SCRIPTA0");
5557 np->scriptb0 = sym_calloc_dma(np->scriptb_sz, "SCRIPTB0");
5558 np->scriptz0 = sym_calloc_dma(np->scriptz_sz, "SCRIPTZ0");
5559 if (!np->scripta0 || !np->scriptb0 || !np->scriptz0)
5560 goto attach_failed;
5561
5562 /*
5563 * Allocate the array of lists of CCBs hashed by DSA.
5564 */
cd861280 5565 np->ccbh = kcalloc(CCB_HASH_SIZE, sizeof(struct sym_ccb **), GFP_KERNEL);
1da177e4
LT		 5566 if (!np->ccbh)
5567 goto attach_failed;
5568
5569 /*
5570 * Initialyze the CCB free and busy queues.
5571 */
5572 sym_que_init(&np->free_ccbq);
5573 sym_que_init(&np->busy_ccbq);
5574 sym_que_init(&np->comp_ccbq);
5575
5576 /*
5577 * Initialization for optional handling
5578 * of device queueing.
5579 */
5580#ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
5581 sym_que_init(&np->dummy_ccbq);
5582#endif
5583 /*
5584 * Allocate some CCB. We need at least ONE.
5585 */
5586 if (!sym_alloc_ccb(np))
5587 goto attach_failed;
5588
5589 /*
5590 * Calculate BUS addresses where we are going
5591 * to load the SCRIPTS.
5592 */
5593 np->scripta_ba = vtobus(np->scripta0);
5594 np->scriptb_ba = vtobus(np->scriptb0);
5595 np->scriptz_ba = vtobus(np->scriptz0);
5596
5597 if (np->ram_ba) {
5598 np->scripta_ba = np->ram_ba;
5599 if (np->features & FE_RAM8K) {
5600 np->ram_ws = 8192;
5601 np->scriptb_ba = np->scripta_ba + 4096;
5602#if 0 /* May get useful for 64 BIT PCI addressing */
5603 np->scr_ram_seg = cpu_to_scr(np->scripta_ba >> 32);
5604#endif
5605 }
5606 else
5607 np->ram_ws = 4096;
5608 }
5609
5610 /*
5611 * Copy scripts to controller instance.
5612 */
5613 memcpy(np->scripta0, fw->a_base, np->scripta_sz);
5614 memcpy(np->scriptb0, fw->b_base, np->scriptb_sz);
5615 memcpy(np->scriptz0, fw->z_base, np->scriptz_sz);
5616
5617 /*
5618 * Setup variable parts in scripts and compute
5619 * scripts bus addresses used from the C code.
5620 */
5621 np->fw_setup(np, fw);
5622
5623 /*
5624 * Bind SCRIPTS with physical addresses usable by the
5625 * SCRIPTS processor (as seen from the BUS = BUS addresses).
5626 */
5627 sym_fw_bind_script(np, (u32 *) np->scripta0, np->scripta_sz);
5628 sym_fw_bind_script(np, (u32 *) np->scriptb0, np->scriptb_sz);
5629 sym_fw_bind_script(np, (u32 *) np->scriptz0, np->scriptz_sz);
5630
5631#ifdef SYM_CONF_IARB_SUPPORT
5632 /*
5633 * If user wants IARB to be set when we win arbitration
5634 * and have other jobs, compute the max number of consecutive
5635 * settings of IARB hints before we leave devices a chance to
5636 * arbitrate for reselection.
5637 */
5638#ifdef SYM_SETUP_IARB_MAX
5639 np->iarb_max = SYM_SETUP_IARB_MAX;
5640#else
5641 np->iarb_max = 4;
5642#endif
5643#endif
5644
5645 /*
5646 * Prepare the idle and invalid task actions.
5647 */
5648 np->idletask.start = cpu_to_scr(SCRIPTA_BA(np, idle));
5649 np->idletask.restart = cpu_to_scr(SCRIPTB_BA(np, bad_i_t_l));
5650 np->idletask_ba = vtobus(&np->idletask);
5651
5652 np->notask.start = cpu_to_scr(SCRIPTA_BA(np, idle));
5653 np->notask.restart = cpu_to_scr(SCRIPTB_BA(np, bad_i_t_l));
5654 np->notask_ba = vtobus(&np->notask);
5655
5656 np->bad_itl.start = cpu_to_scr(SCRIPTA_BA(np, idle));
5657 np->bad_itl.restart = cpu_to_scr(SCRIPTB_BA(np, bad_i_t_l));
5658 np->bad_itl_ba = vtobus(&np->bad_itl);
5659
5660 np->bad_itlq.start = cpu_to_scr(SCRIPTA_BA(np, idle));
5661 np->bad_itlq.restart = cpu_to_scr(SCRIPTB_BA(np,bad_i_t_l_q));
5662 np->bad_itlq_ba = vtobus(&np->bad_itlq);
5663
5664 /*
5665 * Allocate and prepare the lun JUMP table that is used
5666 * for a target prior the probing of devices (bad lun table).
5667 * A private table will be allocated for the target on the
5668 * first INQUIRY response received.
5669 */
5670 np->badluntbl = sym_calloc_dma(256, "BADLUNTBL");
5671 if (!np->badluntbl)
5672 goto attach_failed;
5673
5674 np->badlun_sa = cpu_to_scr(SCRIPTB_BA(np, resel_bad_lun));
5675 for (i = 0 ; i < 64 ; i++) /* 64 luns/target, no less */
5676 np->badluntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa));
5677
5678 /*
5679 * Prepare the bus address array that contains the bus
5680 * address of each target control block.
5681 * For now, assume all logical units are wrong. :)
5682 */
5683 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
5684 np->targtbl[i] = cpu_to_scr(vtobus(&np->target[i]));
5685 np->target[i].head.luntbl_sa =
5686 cpu_to_scr(vtobus(np->badluntbl));
5687 np->target[i].head.lun0_sa =
5688 cpu_to_scr(vtobus(&np->badlun_sa));
5689 }
5690
5691 /*
5692 * Now check the cache handling of the pci chipset.
5693 */
5694 if (sym_snooptest (np)) {
5695 printf("%s: CACHE INCORRECTLY CONFIGURED.\n", sym_name(np));
5696 goto attach_failed;
5697 }
5698
5699 /*
5700 * Sigh! we are done.
5701 */
5702 return 0;
5703
5704attach_failed:
5705 return -ENXIO;
5706}
5707
5708/*
5709 * Free everything that has been allocated for this device.
5710 */
5711void sym_hcb_free(struct sym_hcb *np)
5712{
5713 SYM_QUEHEAD *qp;
5714 struct sym_ccb *cp;
5715 struct sym_tcb *tp;
84e203a2 5716 int target;
1da177e4
LT		 5717
5718 if (np->scriptz0)
5719 sym_mfree_dma(np->scriptz0, np->scriptz_sz, "SCRIPTZ0");
5720 if (np->scriptb0)
5721 sym_mfree_dma(np->scriptb0, np->scriptb_sz, "SCRIPTB0");
5722 if (np->scripta0)
5723 sym_mfree_dma(np->scripta0, np->scripta_sz, "SCRIPTA0");
5724 if (np->squeue)
5725 sym_mfree_dma(np->squeue, sizeof(u32)*(MAX_QUEUE*2), "SQUEUE");
5726 if (np->dqueue)
5727 sym_mfree_dma(np->dqueue, sizeof(u32)*(MAX_QUEUE*2), "DQUEUE");
5728
5729 if (np->actccbs) {
5730 while ((qp = sym_remque_head(&np->free_ccbq)) != 0) {
5731 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
5732 sym_mfree_dma(cp, sizeof(*cp), "CCB");
5733 }
5734 }
5735 kfree(np->ccbh);
5736
5737 if (np->badluntbl)
5738 sym_mfree_dma(np->badluntbl, 256,"BADLUNTBL");
5739
5740 for (target = 0; target < SYM_CONF_MAX_TARGET ; target++) {
5741 tp = &np->target[target];
1da177e4
LT		 5742#if SYM_CONF_MAX_LUN > 1
5743 kfree(tp->lunmp);
5744#endif
5745 }
5746 if (np->targtbl)
5747 sym_mfree_dma(np->targtbl, 256, "TARGTBL");
5748}
kernel source for telekom puls (alcatel/mediatek)