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[SCSI] mvsas: Add driver version and interrupt coalescing to device attributes in...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / mvsas / mv_sas.c
CommitLineData
b5762948 1/*
20b09c29
AY		 2 * Marvell 88SE64xx/88SE94xx main function
3 *
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
0b15fb1f 6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
20b09c29
AY		 7 *
8 * This file is licensed under GPLv2.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; version 2 of the
13 * License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
23 * USA
24*/
b5762948 25
dd4969a8 26#include "mv_sas.h"
b5762948 27
dd4969a8
JG		 28static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
29{
30 if (task->lldd_task) {
31 struct mvs_slot_info *slot;
f9da3be5 32 slot = task->lldd_task;
20b09c29 33 *tag = slot->slot_tag;
dd4969a8
JG		 34 return 1;
35 }
36 return 0;
37}
8f261aaf 38
20b09c29 39void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
dd4969a8 40{
f9da3be5 41 void *bitmap = &mvi->tags;
dd4969a8
JG		 42 clear_bit(tag, bitmap);
43}
8f261aaf 44
20b09c29 45void mvs_tag_free(struct mvs_info *mvi, u32 tag)
dd4969a8
JG		 46{
47 mvs_tag_clear(mvi, tag);
48}
8f261aaf 49
20b09c29 50void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
dd4969a8 51{
f9da3be5 52 void *bitmap = &mvi->tags;
dd4969a8
JG		 53 set_bit(tag, bitmap);
54}
8f261aaf 55
20b09c29 56inline int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
dd4969a8
JG		 57{
58 unsigned int index, tag;
f9da3be5 59 void *bitmap = &mvi->tags;
b5762948 60
20b09c29 61 index = find_first_zero_bit(bitmap, mvi->tags_num);
dd4969a8 62 tag = index;
20b09c29 63 if (tag >= mvi->tags_num)
dd4969a8
JG		 64 return -SAS_QUEUE_FULL;
65 mvs_tag_set(mvi, tag);
66 *tag_out = tag;
67 return 0;
68}
b5762948 69
dd4969a8
JG		 70void mvs_tag_init(struct mvs_info *mvi)
71{
72 int i;
20b09c29 73 for (i = 0; i < mvi->tags_num; ++i)
dd4969a8
JG		 74 mvs_tag_clear(mvi, i);
75}
b5762948 76
20b09c29 77void mvs_hexdump(u32 size, u8 *data, u32 baseaddr)
8f261aaf
KW		 78{
79 u32 i;
80 u32 run;
81 u32 offset;
82
83 offset = 0;
84 while (size) {
20b09c29 85 printk(KERN_DEBUG"%08X : ", baseaddr + offset);
8f261aaf
KW		 86 if (size >= 16)
87 run = 16;
88 else
89 run = size;
90 size -= run;
91 for (i = 0; i < 16; i++) {
92 if (i < run)
20b09c29 93 printk(KERN_DEBUG"%02X ", (u32)data[i]);
8f261aaf 94 else
20b09c29 95 printk(KERN_DEBUG" ");
8f261aaf 96 }
20b09c29 97 printk(KERN_DEBUG": ");
8f261aaf 98 for (i = 0; i < run; i++)
20b09c29
AY		 99 printk(KERN_DEBUG"%c",
100 isalnum(data[i]) ? data[i] : '.');
101 printk(KERN_DEBUG"\n");
8f261aaf
KW		 102 data = &data[16];
103 offset += run;
104 }
20b09c29 105 printk(KERN_DEBUG"\n");
8f261aaf
KW		 106}
107
20b09c29 108#if (_MV_DUMP > 1)
8f261aaf
KW		 109static void mvs_hba_sb_dump(struct mvs_info *mvi, u32 tag,
110 enum sas_protocol proto)
111{
8f261aaf 112 u32 offset;
8f261aaf
KW		 113 struct mvs_slot_info *slot = &mvi->slot_info[tag];
114
115 offset = slot->cmd_size + MVS_OAF_SZ +
20b09c29
AY		 116 MVS_CHIP_DISP->prd_size() * slot->n_elem;
117 dev_printk(KERN_DEBUG, mvi->dev, "+---->Status buffer[%d] :\n",
8f261aaf
KW		 118 tag);
119 mvs_hexdump(32, (u8 *) slot->response,
120 (u32) slot->buf_dma + offset);
8f261aaf 121}
ee1f1c2e 122#endif
8f261aaf
KW		 123
124static void mvs_hba_memory_dump(struct mvs_info *mvi, u32 tag,
125 enum sas_protocol proto)
126{
20b09c29 127#if (_MV_DUMP > 1)
ee1f1c2e 128 u32 sz, w_ptr;
8f261aaf 129 u64 addr;
8f261aaf
KW		 130 struct mvs_slot_info *slot = &mvi->slot_info[tag];
131
132 /*Delivery Queue */
20b09c29 133 sz = MVS_CHIP_SLOT_SZ;
ee1f1c2e 134 w_ptr = slot->tx;
20b09c29
AY		 135 addr = mvi->tx_dma;
136 dev_printk(KERN_DEBUG, mvi->dev,
ee1f1c2e 137 "Delivery Queue Size=%04d , WRT_PTR=%04X\n", sz, w_ptr);
20b09c29 138 dev_printk(KERN_DEBUG, mvi->dev,
8f261aaf
KW		 139 "Delivery Queue Base Address=0x%llX (PA)"
140 "(tx_dma=0x%llX), Entry=%04d\n",
20b09c29 141 addr, (unsigned long long)mvi->tx_dma, w_ptr);
8f261aaf
KW		 142 mvs_hexdump(sizeof(u32), (u8 *)(&mvi->tx[mvi->tx_prod]),
143 (u32) mvi->tx_dma + sizeof(u32) * w_ptr);
144 /*Command List */
ee1f1c2e 145 addr = mvi->slot_dma;
20b09c29 146 dev_printk(KERN_DEBUG, mvi->dev,
8f261aaf
KW		 147 "Command List Base Address=0x%llX (PA)"
148 "(slot_dma=0x%llX), Header=%03d\n",
20b09c29
AY		 149 addr, (unsigned long long)slot->buf_dma, tag);
150 dev_printk(KERN_DEBUG, mvi->dev, "Command Header[%03d]:\n", tag);
8f261aaf
KW		 151 /*mvs_cmd_hdr */
152 mvs_hexdump(sizeof(struct mvs_cmd_hdr), (u8 *)(&mvi->slot[tag]),
153 (u32) mvi->slot_dma + tag * sizeof(struct mvs_cmd_hdr));
154 /*1.command table area */
20b09c29 155 dev_printk(KERN_DEBUG, mvi->dev, "+---->Command Table :\n");
8f261aaf
KW		 156 mvs_hexdump(slot->cmd_size, (u8 *) slot->buf, (u32) slot->buf_dma);
157 /*2.open address frame area */
20b09c29 158 dev_printk(KERN_DEBUG, mvi->dev, "+---->Open Address Frame :\n");
8f261aaf
KW		 159 mvs_hexdump(MVS_OAF_SZ, (u8 *) slot->buf + slot->cmd_size,
160 (u32) slot->buf_dma + slot->cmd_size);
161 /*3.status buffer */
162 mvs_hba_sb_dump(mvi, tag, proto);
163 /*4.PRD table */
20b09c29
AY		 164 dev_printk(KERN_DEBUG, mvi->dev, "+---->PRD table :\n");
165 mvs_hexdump(MVS_CHIP_DISP->prd_size() * slot->n_elem,
8f261aaf
KW		 166 (u8 *) slot->buf + slot->cmd_size + MVS_OAF_SZ,
167 (u32) slot->buf_dma + slot->cmd_size + MVS_OAF_SZ);
168#endif
169}
170
171static void mvs_hba_cq_dump(struct mvs_info *mvi)
172{
ee1f1c2e 173#if (_MV_DUMP > 2)
8f261aaf
KW		 174 u64 addr;
175 void __iomem *regs = mvi->regs;
8f261aaf
KW		 176 u32 entry = mvi->rx_cons + 1;
177 u32 rx_desc = le32_to_cpu(mvi->rx[entry]);
178
179 /*Completion Queue */
180 addr = mr32(RX_HI) << 16 << 16 | mr32(RX_LO);
20b09c29 181 dev_printk(KERN_DEBUG, mvi->dev, "Completion Task = 0x%p\n",
ee1f1c2e 182 mvi->slot_info[rx_desc & RXQ_SLOT_MASK].task);
20b09c29 183 dev_printk(KERN_DEBUG, mvi->dev,
8f261aaf
KW		 184 "Completion List Base Address=0x%llX (PA), "
185 "CQ_Entry=%04d, CQ_WP=0x%08X\n",
186 addr, entry - 1, mvi->rx[0]);
187 mvs_hexdump(sizeof(u32), (u8 *)(&rx_desc),
188 mvi->rx_dma + sizeof(u32) * entry);
189#endif
190}
191
20b09c29 192void mvs_get_sas_addr(void *buf, u32 buflen)
8f261aaf 193{
20b09c29
AY		 194 /*memcpy(buf, "\x50\x05\x04\x30\x11\xab\x64\x40", 8);*/
195}
8f261aaf 196
20b09c29
AY		 197struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev)
198{
199 unsigned long i = 0, j = 0, hi = 0;
200 struct sas_ha_struct *sha = dev->port->ha;
201 struct mvs_info *mvi = NULL;
202 struct asd_sas_phy *phy;
203
204 while (sha->sas_port[i]) {
205 if (sha->sas_port[i] == dev->port) {
206 phy = container_of(sha->sas_port[i]->phy_list.next,
207 struct asd_sas_phy, port_phy_el);
208 j = 0;
209 while (sha->sas_phy[j]) {
210 if (sha->sas_phy[j] == phy)
211 break;
212 j++;
213 }
214 break;
215 }
216 i++;
217 }
218 hi = j/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
219 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
8f261aaf 220
20b09c29 221 return mvi;
8f261aaf 222
20b09c29 223}
8f261aaf 224
20b09c29
AY		 225/* FIXME */
226int mvs_find_dev_phyno(struct domain_device *dev, int *phyno)
227{
228 unsigned long i = 0, j = 0, n = 0, num = 0;
9870d9a2
AY		 229 struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
230 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY		 231 struct sas_ha_struct *sha = dev->port->ha;
232
233 while (sha->sas_port[i]) {
234 if (sha->sas_port[i] == dev->port) {
235 struct asd_sas_phy *phy;
236 list_for_each_entry(phy,
237 &sha->sas_port[i]->phy_list, port_phy_el) {
238 j = 0;
239 while (sha->sas_phy[j]) {
240 if (sha->sas_phy[j] == phy)
241 break;
242 j++;
243 }
244 phyno[n] = (j >= mvi->chip->n_phy) ?
245 (j - mvi->chip->n_phy) : j;
246 num++;
247 n++;
dd4969a8 248 }
dd4969a8
JG		 249 break;
250 }
20b09c29
AY		 251 i++;
252 }
253 return num;
254}
255
534ff101
XY		 256struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi,
257 u8 reg_set)
258{
259 u32 dev_no;
260 for (dev_no = 0; dev_no < MVS_MAX_DEVICES; dev_no++) {
261 if (mvi->devices[dev_no].taskfileset == MVS_ID_NOT_MAPPED)
262 continue;
263
264 if (mvi->devices[dev_no].taskfileset == reg_set)
265 return &mvi->devices[dev_no];
266 }
267 return NULL;
268}
269
20b09c29
AY		 270static inline void mvs_free_reg_set(struct mvs_info *mvi,
271 struct mvs_device *dev)
272{
273 if (!dev) {
274 mv_printk("device has been free.\n");
275 return;
276 }
20b09c29
AY		 277 if (dev->taskfileset == MVS_ID_NOT_MAPPED)
278 return;
279 MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);
280}
281
282static inline u8 mvs_assign_reg_set(struct mvs_info *mvi,
283 struct mvs_device *dev)
284{
285 if (dev->taskfileset != MVS_ID_NOT_MAPPED)
286 return 0;
287 return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);
288}
289
290void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard)
291{
292 u32 no;
293 for_each_phy(phy_mask, phy_mask, no) {
294 if (!(phy_mask & 1))
295 continue;
296 MVS_CHIP_DISP->phy_reset(mvi, no, hard);
297 }
298}
299
300/* FIXME: locking? */
301int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
302 void *funcdata)
303{
304 int rc = 0, phy_id = sas_phy->id;
305 u32 tmp, i = 0, hi;
306 struct sas_ha_struct *sha = sas_phy->ha;
307 struct mvs_info *mvi = NULL;
308
309 while (sha->sas_phy[i]) {
310 if (sha->sas_phy[i] == sas_phy)
311 break;
312 i++;
313 }
314 hi = i/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
315 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
316
317 switch (func) {
318 case PHY_FUNC_SET_LINK_RATE:
319 MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);
320 break;
8f261aaf 321
dd4969a8 322 case PHY_FUNC_HARD_RESET:
20b09c29 323 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
dd4969a8
JG		 324 if (tmp & PHY_RST_HARD)
325 break;
20b09c29 326 MVS_CHIP_DISP->phy_reset(mvi, phy_id, 1);
dd4969a8 327 break;
b5762948 328
dd4969a8 329 case PHY_FUNC_LINK_RESET:
20b09c29
AY		 330 MVS_CHIP_DISP->phy_enable(mvi, phy_id);
331 MVS_CHIP_DISP->phy_reset(mvi, phy_id, 0);
dd4969a8 332 break;
b5762948 333
dd4969a8 334 case PHY_FUNC_DISABLE:
20b09c29
AY		 335 MVS_CHIP_DISP->phy_disable(mvi, phy_id);
336 break;
dd4969a8
JG		 337 case PHY_FUNC_RELEASE_SPINUP_HOLD:
338 default:
339 rc = -EOPNOTSUPP;
b5762948 340 }
20b09c29 341 msleep(200);
b5762948
JG		 342 return rc;
343}
344
20b09c29
AY		 345void __devinit mvs_set_sas_addr(struct mvs_info *mvi, int port_id,
346 u32 off_lo, u32 off_hi, u64 sas_addr)
347{
348 u32 lo = (u32)sas_addr;
349 u32 hi = (u32)(sas_addr>>32);
350
351 MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);
352 MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);
353 MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);
354 MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);
355}
356
dd4969a8 357static void mvs_bytes_dmaed(struct mvs_info *mvi, int i)
ee1f1c2e 358{
dd4969a8 359 struct mvs_phy *phy = &mvi->phy[i];
20b09c29
AY		 360 struct asd_sas_phy *sas_phy = &phy->sas_phy;
361 struct sas_ha_struct *sas_ha;
dd4969a8
JG		 362 if (!phy->phy_attached)
363 return;
364
20b09c29
AY		 365 if (!(phy->att_dev_info & PORT_DEV_TRGT_MASK)
366 && phy->phy_type & PORT_TYPE_SAS) {
367 return;
368 }
369
370 sas_ha = mvi->sas;
371 sas_ha->notify_phy_event(sas_phy, PHYE_OOB_DONE);
372
dd4969a8
JG		 373 if (sas_phy->phy) {
374 struct sas_phy *sphy = sas_phy->phy;
375
376 sphy->negotiated_linkrate = sas_phy->linkrate;
377 sphy->minimum_linkrate = phy->minimum_linkrate;
378 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
379 sphy->maximum_linkrate = phy->maximum_linkrate;
20b09c29 380 sphy->maximum_linkrate_hw = MVS_CHIP_DISP->phy_max_link_rate();
ee1f1c2e 381 }
ee1f1c2e 382
dd4969a8
JG		 383 if (phy->phy_type & PORT_TYPE_SAS) {
384 struct sas_identify_frame *id;
b5762948 385
dd4969a8
JG		 386 id = (struct sas_identify_frame *)phy->frame_rcvd;
387 id->dev_type = phy->identify.device_type;
388 id->initiator_bits = SAS_PROTOCOL_ALL;
389 id->target_bits = phy->identify.target_port_protocols;
390 } else if (phy->phy_type & PORT_TYPE_SATA) {
20b09c29 391 /*Nothing*/
dd4969a8 392 }
20b09c29
AY		 393 mv_dprintk("phy %d byte dmaded.\n", i + mvi->id * mvi->chip->n_phy);
394
395 sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
396
397 mvi->sas->notify_port_event(sas_phy,
dd4969a8 398 PORTE_BYTES_DMAED);
ee1f1c2e
KW		 399}
400
20b09c29
AY		 401int mvs_slave_alloc(struct scsi_device *scsi_dev)
402{
403 struct domain_device *dev = sdev_to_domain_dev(scsi_dev);
404 if (dev_is_sata(dev)) {
405 /* We don't need to rescan targets
406 * if REPORT_LUNS request is failed
407 */
408 if (scsi_dev->lun > 0)
409 return -ENXIO;
410 scsi_dev->tagged_supported = 1;
411 }
412
413 return sas_slave_alloc(scsi_dev);
414}
415
dd4969a8 416int mvs_slave_configure(struct scsi_device *sdev)
ee1f1c2e 417{
dd4969a8
JG		 418 struct domain_device *dev = sdev_to_domain_dev(sdev);
419 int ret = sas_slave_configure(sdev);
b5762948 420
dd4969a8
JG		 421 if (ret)
422 return ret;
dd4969a8 423 if (dev_is_sata(dev)) {
20b09c29
AY		 424 /* may set PIO mode */
425 #if MV_DISABLE_NCQ
426 struct ata_port *ap = dev->sata_dev.ap;
427 struct ata_device *adev = ap->link.device;
428 adev->flags |= ATA_DFLAG_NCQ_OFF;
dd4969a8 429 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, 1);
20b09c29 430 #endif
dd4969a8 431 }
ee1f1c2e 432 return 0;
b5762948
JG		 433}
434
dd4969a8 435void mvs_scan_start(struct Scsi_Host *shost)
b5762948 436{
20b09c29
AY		 437 int i, j;
438 unsigned short core_nr;
439 struct mvs_info *mvi;
440 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
441
442 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
dd4969a8 443
20b09c29
AY		 444 for (j = 0; j < core_nr; j++) {
445 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
446 for (i = 0; i < mvi->chip->n_phy; ++i)
447 mvs_bytes_dmaed(mvi, i);
dd4969a8 448 }
b5762948
JG		 449}
450
dd4969a8 451int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time)
b5762948 452{
dd4969a8
JG		 453 /* give the phy enabling interrupt event time to come in (1s
454 * is empirically about all it takes) */
455 if (time < HZ)
456 return 0;
457 /* Wait for discovery to finish */
458 scsi_flush_work(shost);
459 return 1;
b5762948
JG		 460}
461
dd4969a8
JG		 462static int mvs_task_prep_smp(struct mvs_info *mvi,
463 struct mvs_task_exec_info *tei)
b5762948 464{
dd4969a8
JG		 465 int elem, rc, i;
466 struct sas_task *task = tei->task;
467 struct mvs_cmd_hdr *hdr = tei->hdr;
20b09c29
AY		 468 struct domain_device *dev = task->dev;
469 struct asd_sas_port *sas_port = dev->port;
dd4969a8
JG		 470 struct scatterlist *sg_req, *sg_resp;
471 u32 req_len, resp_len, tag = tei->tag;
472 void *buf_tmp;
473 u8 *buf_oaf;
474 dma_addr_t buf_tmp_dma;
20b09c29 475 void *buf_prd;
dd4969a8 476 struct mvs_slot_info *slot = &mvi->slot_info[tag];
dd4969a8
JG		 477 u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
478#if _MV_DUMP
479 u8 *buf_cmd;
480 void *from;
481#endif
482 /*
483 * DMA-map SMP request, response buffers
484 */
485 sg_req = &task->smp_task.smp_req;
20b09c29 486 elem = dma_map_sg(mvi->dev, sg_req, 1, PCI_DMA_TODEVICE);
dd4969a8
JG		 487 if (!elem)
488 return -ENOMEM;
489 req_len = sg_dma_len(sg_req);
b5762948 490
dd4969a8 491 sg_resp = &task->smp_task.smp_resp;
20b09c29 492 elem = dma_map_sg(mvi->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
dd4969a8
JG		 493 if (!elem) {
494 rc = -ENOMEM;
495 goto err_out;
496 }
20b09c29 497 resp_len = SB_RFB_MAX;
b5762948 498
dd4969a8
JG		 499 /* must be in dwords */
500 if ((req_len & 0x3) || (resp_len & 0x3)) {
501 rc = -EINVAL;
502 goto err_out_2;
b5762948
JG		 503 }
504
dd4969a8
JG		 505 /*
506 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
507 */
b5762948 508
20b09c29 509 /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ***** */
dd4969a8
JG		 510 buf_tmp = slot->buf;
511 buf_tmp_dma = slot->buf_dma;
b5762948 512
dd4969a8
JG		 513#if _MV_DUMP
514 buf_cmd = buf_tmp;
515 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
516 buf_tmp += req_len;
517 buf_tmp_dma += req_len;
518 slot->cmd_size = req_len;
519#else
520 hdr->cmd_tbl = cpu_to_le64(sg_dma_address(sg_req));
521#endif
b5762948 522
dd4969a8
JG		 523 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
524 buf_oaf = buf_tmp;
525 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
b5762948 526
dd4969a8
JG		 527 buf_tmp += MVS_OAF_SZ;
528 buf_tmp_dma += MVS_OAF_SZ;
b5762948 529
20b09c29 530 /* region 3: PRD table *********************************** */
dd4969a8
JG		 531 buf_prd = buf_tmp;
532 if (tei->n_elem)
533 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
534 else
535 hdr->prd_tbl = 0;
b5762948 536
20b09c29 537 i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
dd4969a8
JG		 538 buf_tmp += i;
539 buf_tmp_dma += i;
b5762948 540
dd4969a8
JG		 541 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
542 slot->response = buf_tmp;
543 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
20b09c29
AY		 544 if (mvi->flags & MVF_FLAG_SOC)
545 hdr->reserved[0] = 0;
b5762948 546
dd4969a8
JG		 547 /*
548 * Fill in TX ring and command slot header
549 */
550 slot->tx = mvi->tx_prod;
551 mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
552 TXQ_MODE_I | tag |
553 (sas_port->phy_mask << TXQ_PHY_SHIFT));
b5762948 554
dd4969a8
JG		 555 hdr->flags |= flags;
556 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | ((req_len - 4) / 4));
557 hdr->tags = cpu_to_le32(tag);
558 hdr->data_len = 0;
b5762948 559
dd4969a8 560 /* generate open address frame hdr (first 12 bytes) */
20b09c29
AY		 561 /* initiator, SMP, ftype 1h */
562 buf_oaf[0] = (1 << 7) | (PROTOCOL_SMP << 4) | 0x01;
563 buf_oaf[1] = dev->linkrate & 0xf;
dd4969a8 564 *(u16 *)(buf_oaf + 2) = 0xFFFF; /* SAS SPEC */
20b09c29 565 memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
dd4969a8
JG		 566
567 /* fill in PRD (scatter/gather) table, if any */
20b09c29 568 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
b5762948 569
dd4969a8
JG		 570#if _MV_DUMP
571 /* copy cmd table */
572 from = kmap_atomic(sg_page(sg_req), KM_IRQ0);
573 memcpy(buf_cmd, from + sg_req->offset, req_len);
574 kunmap_atomic(from, KM_IRQ0);
575#endif
b5762948
JG		 576 return 0;
577
dd4969a8 578err_out_2:
20b09c29 579 dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_resp, 1,
dd4969a8 580 PCI_DMA_FROMDEVICE);
b5762948 581err_out:
20b09c29 582 dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_req, 1,
dd4969a8 583 PCI_DMA_TODEVICE);
8f261aaf 584 return rc;
8f261aaf
KW		 585}
586
dd4969a8 587static u32 mvs_get_ncq_tag(struct sas_task *task, u32 *tag)
8f261aaf 588{
dd4969a8 589 struct ata_queued_cmd *qc = task->uldd_task;
8f261aaf 590
dd4969a8
JG		 591 if (qc) {
592 if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
593 qc->tf.command == ATA_CMD_FPDMA_READ) {
594 *tag = qc->tag;
595 return 1;
596 }
8f261aaf 597 }
8f261aaf 598
dd4969a8 599 return 0;
8f261aaf
KW		 600}
601
dd4969a8
JG		 602static int mvs_task_prep_ata(struct mvs_info *mvi,
603 struct mvs_task_exec_info *tei)
b5762948
JG		 604{
605 struct sas_task *task = tei->task;
606 struct domain_device *dev = task->dev;
f9da3be5 607 struct mvs_device *mvi_dev = dev->lldd_dev;
b5762948
JG		 608 struct mvs_cmd_hdr *hdr = tei->hdr;
609 struct asd_sas_port *sas_port = dev->port;
8f261aaf 610 struct mvs_slot_info *slot;
20b09c29
AY		 611 void *buf_prd;
612 u32 tag = tei->tag, hdr_tag;
613 u32 flags, del_q;
b5762948
JG		 614 void *buf_tmp;
615 u8 *buf_cmd, *buf_oaf;
616 dma_addr_t buf_tmp_dma;
8f261aaf
KW		 617 u32 i, req_len, resp_len;
618 const u32 max_resp_len = SB_RFB_MAX;
619
20b09c29
AY		 620 if (mvs_assign_reg_set(mvi, mvi_dev) == MVS_ID_NOT_MAPPED) {
621 mv_dprintk("Have not enough regiset for dev %d.\n",
622 mvi_dev->device_id);
8f261aaf 623 return -EBUSY;
20b09c29 624 }
8f261aaf
KW		 625 slot = &mvi->slot_info[tag];
626 slot->tx = mvi->tx_prod;
20b09c29
AY		 627 del_q = TXQ_MODE_I | tag |
628 (TXQ_CMD_STP << TXQ_CMD_SHIFT) |
629 (sas_port->phy_mask << TXQ_PHY_SHIFT) |
630 (mvi_dev->taskfileset << TXQ_SRS_SHIFT);
631 mvi->tx[mvi->tx_prod] = cpu_to_le32(del_q);
632
633#ifndef DISABLE_HOTPLUG_DMA_FIX
634 if (task->data_dir == DMA_FROM_DEVICE)
635 flags = (MVS_CHIP_DISP->prd_count() << MCH_PRD_LEN_SHIFT);
636 else
637 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
638#else
639 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
640#endif
b5762948
JG		 641 if (task->ata_task.use_ncq)
642 flags |= MCH_FPDMA;
8f261aaf
KW		 643 if (dev->sata_dev.command_set == ATAPI_COMMAND_SET) {
644 if (task->ata_task.fis.command != ATA_CMD_ID_ATAPI)
645 flags |= MCH_ATAPI;
646 }
647
b5762948
JG		 648 /* FIXME: fill in port multiplier number */
649
650 hdr->flags = cpu_to_le32(flags);
8f261aaf
KW		 651
652 /* FIXME: the low order order 5 bits for the TAG if enable NCQ */
20b09c29
AY		 653 if (task->ata_task.use_ncq && mvs_get_ncq_tag(task, &hdr_tag))
654 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4e52fc0a 655 else
20b09c29
AY		 656 hdr_tag = tag;
657
658 hdr->tags = cpu_to_le32(hdr_tag);
659
b5762948
JG		 660 hdr->data_len = cpu_to_le32(task->total_xfer_len);
661
662 /*
663 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
664 */
b5762948 665
8f261aaf
KW		 666 /* region 1: command table area (MVS_ATA_CMD_SZ bytes) ************** */
667 buf_cmd = buf_tmp = slot->buf;
b5762948
JG		 668 buf_tmp_dma = slot->buf_dma;
669
670 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
671
672 buf_tmp += MVS_ATA_CMD_SZ;
673 buf_tmp_dma += MVS_ATA_CMD_SZ;
8f261aaf
KW		 674#if _MV_DUMP
675 slot->cmd_size = MVS_ATA_CMD_SZ;
676#endif
b5762948 677
8f261aaf 678 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
b5762948
JG		 679 /* used for STP. unused for SATA? */
680 buf_oaf = buf_tmp;
681 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
682
683 buf_tmp += MVS_OAF_SZ;
684 buf_tmp_dma += MVS_OAF_SZ;
685
8f261aaf 686 /* region 3: PRD table ********************************************* */
b5762948 687 buf_prd = buf_tmp;
20b09c29 688
8f261aaf
KW		 689 if (tei->n_elem)
690 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
691 else
692 hdr->prd_tbl = 0;
20b09c29 693 i = MVS_CHIP_DISP->prd_size() * MVS_CHIP_DISP->prd_count();
b5762948 694
b5762948
JG		 695 buf_tmp += i;
696 buf_tmp_dma += i;
697
8f261aaf 698 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
b5762948
JG		 699 /* FIXME: probably unused, for SATA. kept here just in case
700 * we get a STP/SATA error information record
701 */
702 slot->response = buf_tmp;
703 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
20b09c29
AY		 704 if (mvi->flags & MVF_FLAG_SOC)
705 hdr->reserved[0] = 0;
b5762948 706
8f261aaf 707 req_len = sizeof(struct host_to_dev_fis);
b5762948 708 resp_len = MVS_SLOT_BUF_SZ - MVS_ATA_CMD_SZ -
8f261aaf 709 sizeof(struct mvs_err_info) - i;
b5762948
JG		 710
711 /* request, response lengths */
8f261aaf 712 resp_len = min(resp_len, max_resp_len);
b5762948
JG		 713 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
714
20b09c29
AY		 715 if (likely(!task->ata_task.device_control_reg_update))
716 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
b5762948 717 /* fill in command FIS and ATAPI CDB */
8f261aaf
KW		 718 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
719 if (dev->sata_dev.command_set == ATAPI_COMMAND_SET)
720 memcpy(buf_cmd + STP_ATAPI_CMD,
721 task->ata_task.atapi_packet, 16);
722
723 /* generate open address frame hdr (first 12 bytes) */
20b09c29
AY		 724 /* initiator, STP, ftype 1h */
725 buf_oaf[0] = (1 << 7) | (PROTOCOL_STP << 4) | 0x1;
726 buf_oaf[1] = dev->linkrate & 0xf;
727 *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
728 memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
b5762948
JG		 729
730 /* fill in PRD (scatter/gather) table, if any */
20b09c29
AY		 731 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
732#ifndef DISABLE_HOTPLUG_DMA_FIX
733 if (task->data_dir == DMA_FROM_DEVICE)
734 MVS_CHIP_DISP->dma_fix(mvi->bulk_buffer_dma,
735 TRASH_BUCKET_SIZE, tei->n_elem, buf_prd);
736#endif
b5762948
JG		 737 return 0;
738}
739
740static int mvs_task_prep_ssp(struct mvs_info *mvi,
20b09c29
AY		 741 struct mvs_task_exec_info *tei, int is_tmf,
742 struct mvs_tmf_task *tmf)
b5762948
JG		 743{
744 struct sas_task *task = tei->task;
b5762948 745 struct mvs_cmd_hdr *hdr = tei->hdr;
8f261aaf 746 struct mvs_port *port = tei->port;
20b09c29 747 struct domain_device *dev = task->dev;
f9da3be5 748 struct mvs_device *mvi_dev = dev->lldd_dev;
20b09c29 749 struct asd_sas_port *sas_port = dev->port;
b5762948 750 struct mvs_slot_info *slot;
20b09c29 751 void *buf_prd;
b5762948
JG		 752 struct ssp_frame_hdr *ssp_hdr;
753 void *buf_tmp;
754 u8 *buf_cmd, *buf_oaf, fburst = 0;
755 dma_addr_t buf_tmp_dma;
756 u32 flags;
8f261aaf
KW		 757 u32 resp_len, req_len, i, tag = tei->tag;
758 const u32 max_resp_len = SB_RFB_MAX;
20b09c29 759 u32 phy_mask;
b5762948
JG		 760
761 slot = &mvi->slot_info[tag];
762
20b09c29
AY		 763 phy_mask = ((port->wide_port_phymap) ? port->wide_port_phymap :
764 sas_port->phy_mask) & TXQ_PHY_MASK;
765
8f261aaf
KW		 766 slot->tx = mvi->tx_prod;
767 mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
768 (TXQ_CMD_SSP << TXQ_CMD_SHIFT) |
4e52fc0a 769 (phy_mask << TXQ_PHY_SHIFT));
b5762948
JG		 770
771 flags = MCH_RETRY;
772 if (task->ssp_task.enable_first_burst) {
773 flags |= MCH_FBURST;
774 fburst = (1 << 7);
775 }
2b288133
AY		 776 if (is_tmf)
777 flags |= (MCH_SSP_FR_TASK << MCH_SSP_FR_TYPE_SHIFT);
2b288133 778 hdr->flags = cpu_to_le32(flags | (tei->n_elem << MCH_PRD_LEN_SHIFT));
b5762948
JG		 779 hdr->tags = cpu_to_le32(tag);
780 hdr->data_len = cpu_to_le32(task->total_xfer_len);
781
782 /*
783 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
784 */
b5762948 785
8f261aaf
KW		 786 /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
787 buf_cmd = buf_tmp = slot->buf;
b5762948
JG		 788 buf_tmp_dma = slot->buf_dma;
789
790 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
791
792 buf_tmp += MVS_SSP_CMD_SZ;
793 buf_tmp_dma += MVS_SSP_CMD_SZ;
8f261aaf
KW		 794#if _MV_DUMP
795 slot->cmd_size = MVS_SSP_CMD_SZ;
796#endif
b5762948 797
8f261aaf 798 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
b5762948
JG		 799 buf_oaf = buf_tmp;
800 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
801
802 buf_tmp += MVS_OAF_SZ;
803 buf_tmp_dma += MVS_OAF_SZ;
804
8f261aaf 805 /* region 3: PRD table ********************************************* */
b5762948 806 buf_prd = buf_tmp;
8f261aaf
KW		 807 if (tei->n_elem)
808 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
809 else
810 hdr->prd_tbl = 0;
b5762948 811
20b09c29 812 i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
b5762948
JG		 813 buf_tmp += i;
814 buf_tmp_dma += i;
815
8f261aaf 816 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
b5762948
JG		 817 slot->response = buf_tmp;
818 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
20b09c29
AY		 819 if (mvi->flags & MVF_FLAG_SOC)
820 hdr->reserved[0] = 0;
b5762948 821
b5762948 822 resp_len = MVS_SLOT_BUF_SZ - MVS_SSP_CMD_SZ - MVS_OAF_SZ -
8f261aaf
KW		 823 sizeof(struct mvs_err_info) - i;
824 resp_len = min(resp_len, max_resp_len);
825
826 req_len = sizeof(struct ssp_frame_hdr) + 28;
b5762948
JG		 827
828 /* request, response lengths */
829 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
830
831 /* generate open address frame hdr (first 12 bytes) */
20b09c29
AY		 832 /* initiator, SSP, ftype 1h */
833 buf_oaf[0] = (1 << 7) | (PROTOCOL_SSP << 4) | 0x1;
834 buf_oaf[1] = dev->linkrate & 0xf;
835 *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
836 memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
b5762948 837
8f261aaf
KW		 838 /* fill in SSP frame header (Command Table.SSP frame header) */
839 ssp_hdr = (struct ssp_frame_hdr *)buf_cmd;
20b09c29
AY		 840
841 if (is_tmf)
842 ssp_hdr->frame_type = SSP_TASK;
843 else
844 ssp_hdr->frame_type = SSP_COMMAND;
845
846 memcpy(ssp_hdr->hashed_dest_addr, dev->hashed_sas_addr,
b5762948
JG		 847 HASHED_SAS_ADDR_SIZE);
848 memcpy(ssp_hdr->hashed_src_addr,
20b09c29 849 dev->hashed_sas_addr, HASHED_SAS_ADDR_SIZE);
b5762948
JG		 850 ssp_hdr->tag = cpu_to_be16(tag);
851
20b09c29 852 /* fill in IU for TASK and Command Frame */
b5762948
JG		 853 buf_cmd += sizeof(*ssp_hdr);
854 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
b5762948 855
20b09c29
AY		 856 if (ssp_hdr->frame_type != SSP_TASK) {
857 buf_cmd[9] = fburst | task->ssp_task.task_attr |
858 (task->ssp_task.task_prio << 3);
859 memcpy(buf_cmd + 12, &task->ssp_task.cdb, 16);
860 } else{
861 buf_cmd[10] = tmf->tmf;
862 switch (tmf->tmf) {
863 case TMF_ABORT_TASK:
864 case TMF_QUERY_TASK:
865 buf_cmd[12] =
866 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
867 buf_cmd[13] =
868 tmf->tag_of_task_to_be_managed & 0xff;
869 break;
870 default:
871 break;
872 }
b5762948 873 }
20b09c29
AY		 874 /* fill in PRD (scatter/gather) table, if any */
875 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
b5762948
JG		 876 return 0;
877}
878
20b09c29 879#define DEV_IS_GONE(mvi_dev) ((!mvi_dev || (mvi_dev->dev_type == NO_DEVICE)))
0b15fb1f
XY		 880static int mvs_task_prep(struct sas_task *task, struct mvs_info *mvi, int is_tmf,
881 struct mvs_tmf_task *tmf, int *pass)
b5762948 882{
8f261aaf 883 struct domain_device *dev = task->dev;
0b15fb1f 884 struct mvs_device *mvi_dev = dev->lldd_dev;
b5762948 885 struct mvs_task_exec_info tei;
4e52fc0a 886 struct mvs_slot_info *slot;
0b15fb1f
XY		 887 u32 tag = 0xdeadbeef, n_elem = 0;
888 int rc = 0;
b5762948 889
20b09c29 890 if (!dev->port) {
0b15fb1f 891 struct task_status_struct *tsm = &task->task_status;
20b09c29
AY		 892
893 tsm->resp = SAS_TASK_UNDELIVERED;
894 tsm->stat = SAS_PHY_DOWN;
0b15fb1f
XY		 895 /*
896 * libsas will use dev->port, should
897 * not call task_done for sata
898 */
9dc9fd94 899 if (dev->dev_type != SATA_DEV)
0b15fb1f
XY		 900 task->task_done(task);
901 return rc;
20b09c29
AY		 902 }
903
0b15fb1f
XY		 904 if (DEV_IS_GONE(mvi_dev)) {
905 if (mvi_dev)
906 mv_dprintk("device %d not ready.\n",
907 mvi_dev->device_id);
908 else
909 mv_dprintk("device %016llx not ready.\n",
910 SAS_ADDR(dev->sas_addr));
20b09c29
AY		 911
912 rc = SAS_PHY_DOWN;
0b15fb1f
XY		 913 return rc;
914 }
915 tei.port = dev->port->lldd_port;
916 if (tei.port && !tei.port->port_attached && !tmf) {
917 if (sas_protocol_ata(task->task_proto)) {
918 struct task_status_struct *ts = &task->task_status;
919 mv_dprintk("SATA/STP port %d does not attach"
920 "device.\n", dev->port->id);
921 ts->resp = SAS_TASK_COMPLETE;
922 ts->stat = SAS_PHY_DOWN;
20b09c29 923
0b15fb1f 924 task->task_done(task);
dd4969a8 925
dd4969a8 926 } else {
0b15fb1f
XY		 927 struct task_status_struct *ts = &task->task_status;
928 mv_dprintk("SAS port %d does not attach"
929 "device.\n", dev->port->id);
930 ts->resp = SAS_TASK_UNDELIVERED;
931 ts->stat = SAS_PHY_DOWN;
932 task->task_done(task);
dd4969a8 933 }
0b15fb1f
XY		 934 return rc;
935 }
dd4969a8 936
0b15fb1f
XY		 937 if (!sas_protocol_ata(task->task_proto)) {
938 if (task->num_scatter) {
939 n_elem = dma_map_sg(mvi->dev,
940 task->scatter,
941 task->num_scatter,
942 task->data_dir);
943 if (!n_elem) {
944 rc = -ENOMEM;
945 goto prep_out;
946 }
947 }
948 } else {
949 n_elem = task->num_scatter;
950 }
20b09c29 951
0b15fb1f
XY		 952 rc = mvs_tag_alloc(mvi, &tag);
953 if (rc)
954 goto err_out;
20b09c29 955
0b15fb1f 956 slot = &mvi->slot_info[tag];
20b09c29 957
0b15fb1f
XY		 958 task->lldd_task = NULL;
959 slot->n_elem = n_elem;
960 slot->slot_tag = tag;
961
962 slot->buf = pci_pool_alloc(mvi->dma_pool, GFP_ATOMIC, &slot->buf_dma);
963 if (!slot->buf)
964 goto err_out_tag;
965 memset(slot->buf, 0, MVS_SLOT_BUF_SZ);
966
967 tei.task = task;
968 tei.hdr = &mvi->slot[tag];
969 tei.tag = tag;
970 tei.n_elem = n_elem;
971 switch (task->task_proto) {
972 case SAS_PROTOCOL_SMP:
973 rc = mvs_task_prep_smp(mvi, &tei);
974 break;
975 case SAS_PROTOCOL_SSP:
976 rc = mvs_task_prep_ssp(mvi, &tei, is_tmf, tmf);
977 break;
978 case SAS_PROTOCOL_SATA:
979 case SAS_PROTOCOL_STP:
980 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
981 rc = mvs_task_prep_ata(mvi, &tei);
982 break;
983 default:
984 dev_printk(KERN_ERR, mvi->dev,
985 "unknown sas_task proto: 0x%x\n",
986 task->task_proto);
987 rc = -EINVAL;
988 break;
989 }
dd4969a8 990
0b15fb1f
XY		 991 if (rc) {
992 mv_dprintk("rc is %x\n", rc);
993 goto err_out_slot_buf;
994 }
995 slot->task = task;
996 slot->port = tei.port;
997 task->lldd_task = slot;
998 list_add_tail(&slot->entry, &tei.port->list);
999 spin_lock(&task->task_state_lock);
1000 task->task_state_flags |= SAS_TASK_AT_INITIATOR;
1001 spin_unlock(&task->task_state_lock);
1002
1003 mvs_hba_memory_dump(mvi, tag, task->task_proto);
1004 mvi_dev->running_req++;
1005 ++(*pass);
1006 mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
9dc9fd94 1007
0b15fb1f 1008 return rc;
dd4969a8 1009
0b15fb1f
XY		 1010err_out_slot_buf:
1011 pci_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
dd4969a8
JG		 1012err_out_tag:
1013 mvs_tag_free(mvi, tag);
1014err_out:
20b09c29 1015
0b15fb1f
XY		 1016 dev_printk(KERN_ERR, mvi->dev, "mvsas prep failed[%d]!\n", rc);
1017 if (!sas_protocol_ata(task->task_proto))
dd4969a8 1018 if (n_elem)
0b15fb1f
XY		 1019 dma_unmap_sg(mvi->dev, task->scatter, n_elem,
1020 task->data_dir);
1021prep_out:
1022 return rc;
1023}
1024
1025static struct mvs_task_list *mvs_task_alloc_list(int *num, gfp_t gfp_flags)
1026{
1027 struct mvs_task_list *first = NULL;
1028
1029 for (; *num > 0; --*num) {
1030 struct mvs_task_list *mvs_list = kmem_cache_zalloc(mvs_task_list_cache, gfp_flags);
1031
1032 if (!mvs_list)
1033 break;
1034
1035 INIT_LIST_HEAD(&mvs_list->list);
1036 if (!first)
1037 first = mvs_list;
1038 else
1039 list_add_tail(&mvs_list->list, &first->list);
1040
1041 }
1042
1043 return first;
1044}
1045
1046static inline void mvs_task_free_list(struct mvs_task_list *mvs_list)
1047{
1048 LIST_HEAD(list);
1049 struct list_head *pos, *a;
1050 struct mvs_task_list *mlist = NULL;
1051
1052 __list_add(&list, mvs_list->list.prev, &mvs_list->list);
1053
1054 list_for_each_safe(pos, a, &list) {
1055 list_del_init(pos);
1056 mlist = list_entry(pos, struct mvs_task_list, list);
1057 kmem_cache_free(mvs_task_list_cache, mlist);
1058 }
1059}
1060
1061static int mvs_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags,
1062 struct completion *completion, int is_tmf,
1063 struct mvs_tmf_task *tmf)
1064{
1065 struct domain_device *dev = task->dev;
1066 struct mvs_info *mvi = NULL;
1067 u32 rc = 0;
1068 u32 pass = 0;
1069 unsigned long flags = 0;
1070
1071 mvi = ((struct mvs_device *)task->dev->lldd_dev)->mvi_info;
1072
1073 if ((dev->dev_type == SATA_DEV) && (dev->sata_dev.ap != NULL))
1074 spin_unlock_irq(dev->sata_dev.ap->lock);
1075
1076 spin_lock_irqsave(&mvi->lock, flags);
1077 rc = mvs_task_prep(task, mvi, is_tmf, tmf, &pass);
1078 if (rc)
1079 dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
1080
1081 if (likely(pass))
1082 MVS_CHIP_DISP->start_delivery(mvi, (mvi->tx_prod - 1) &
1083 (MVS_CHIP_SLOT_SZ - 1));
0b84b709 1084 spin_unlock_irqrestore(&mvi->lock, flags);
0b15fb1f
XY		 1085
1086 if ((dev->dev_type == SATA_DEV) && (dev->sata_dev.ap != NULL))
1087 spin_lock_irq(dev->sata_dev.ap->lock);
1088
1089 return rc;
1090}
1091
1092static int mvs_collector_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags,
1093 struct completion *completion, int is_tmf,
1094 struct mvs_tmf_task *tmf)
1095{
1096 struct domain_device *dev = task->dev;
1097 struct mvs_prv_info *mpi = dev->port->ha->lldd_ha;
1098 struct mvs_info *mvi = NULL;
1099 struct sas_task *t = task;
1100 struct mvs_task_list *mvs_list = NULL, *a;
1101 LIST_HEAD(q);
1102 int pass[2] = {0};
1103 u32 rc = 0;
1104 u32 n = num;
1105 unsigned long flags = 0;
1106
1107 mvs_list = mvs_task_alloc_list(&n, gfp_flags);
1108 if (n) {
1109 printk(KERN_ERR "%s: mvs alloc list failed.\n", __func__);
1110 rc = -ENOMEM;
1111 goto free_list;
1112 }
1113
1114 __list_add(&q, mvs_list->list.prev, &mvs_list->list);
1115
1116 list_for_each_entry(a, &q, list) {
1117 a->task = t;
1118 t = list_entry(t->list.next, struct sas_task, list);
1119 }
1120
1121 list_for_each_entry(a, &q , list) {
1122
1123 t = a->task;
1124 mvi = ((struct mvs_device *)t->dev->lldd_dev)->mvi_info;
1125
1126 spin_lock_irqsave(&mvi->lock, flags);
1127 rc = mvs_task_prep(t, mvi, is_tmf, tmf, &pass[mvi->id]);
1128 if (rc)
1129 dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
1130 spin_unlock_irqrestore(&mvi->lock, flags);
1131 }
1132
1133 if (likely(pass[0]))
1134 MVS_CHIP_DISP->start_delivery(mpi->mvi[0],
1135 (mpi->mvi[0]->tx_prod - 1) & (MVS_CHIP_SLOT_SZ - 1));
1136
1137 if (likely(pass[1]))
1138 MVS_CHIP_DISP->start_delivery(mpi->mvi[1],
1139 (mpi->mvi[1]->tx_prod - 1) & (MVS_CHIP_SLOT_SZ - 1));
1140
1141 list_del_init(&q);
1142
1143free_list:
1144 if (mvs_list)
1145 mvs_task_free_list(mvs_list);
1146
dd4969a8
JG		 1147 return rc;
1148}
1149
20b09c29
AY		 1150int mvs_queue_command(struct sas_task *task, const int num,
1151 gfp_t gfp_flags)
1152{
0b15fb1f
XY		 1153 struct mvs_device *mvi_dev = task->dev->lldd_dev;
1154 struct sas_ha_struct *sas = mvi_dev->mvi_info->sas;
1155
1156 if (sas->lldd_max_execute_num < 2)
1157 return mvs_task_exec(task, num, gfp_flags, NULL, 0, NULL);
1158 else
1159 return mvs_collector_task_exec(task, num, gfp_flags, NULL, 0, NULL);
20b09c29
AY		 1160}
1161
dd4969a8
JG		 1162static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)
1163{
1164 u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
1165 mvs_tag_clear(mvi, slot_idx);
1166}
1167
1168static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task,
1169 struct mvs_slot_info *slot, u32 slot_idx)
1170{
20b09c29
AY		 1171 if (!slot->task)
1172 return;
dd4969a8
JG		 1173 if (!sas_protocol_ata(task->task_proto))
1174 if (slot->n_elem)
20b09c29 1175 dma_unmap_sg(mvi->dev, task->scatter,
dd4969a8
JG		 1176 slot->n_elem, task->data_dir);
1177
1178 switch (task->task_proto) {
1179 case SAS_PROTOCOL_SMP:
20b09c29 1180 dma_unmap_sg(mvi->dev, &task->smp_task.smp_resp, 1,
dd4969a8 1181 PCI_DMA_FROMDEVICE);
20b09c29 1182 dma_unmap_sg(mvi->dev, &task->smp_task.smp_req, 1,
dd4969a8
JG		 1183 PCI_DMA_TODEVICE);
1184 break;
1185
1186 case SAS_PROTOCOL_SATA:
1187 case SAS_PROTOCOL_STP:
1188 case SAS_PROTOCOL_SSP:
1189 default:
1190 /* do nothing */
1191 break;
1192 }
0b15fb1f
XY		 1193
1194 if (slot->buf) {
1195 pci_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
1196 slot->buf = NULL;
1197 }
20b09c29 1198 list_del_init(&slot->entry);
dd4969a8
JG		 1199 task->lldd_task = NULL;
1200 slot->task = NULL;
1201 slot->port = NULL;
20b09c29
AY		 1202 slot->slot_tag = 0xFFFFFFFF;
1203 mvs_slot_free(mvi, slot_idx);
dd4969a8
JG		 1204}
1205
1206static void mvs_update_wideport(struct mvs_info *mvi, int i)
1207{
1208 struct mvs_phy *phy = &mvi->phy[i];
1209 struct mvs_port *port = phy->port;
1210 int j, no;
1211
20b09c29
AY		 1212 for_each_phy(port->wide_port_phymap, j, no) {
1213 if (j & 1) {
1214 MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
1215 PHYR_WIDE_PORT);
1216 MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
dd4969a8
JG		 1217 port->wide_port_phymap);
1218 } else {
20b09c29
AY		 1219 MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
1220 PHYR_WIDE_PORT);
1221 MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
1222 0);
dd4969a8 1223 }
20b09c29 1224 }
dd4969a8
JG		 1225}
1226
1227static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
1228{
1229 u32 tmp;
1230 struct mvs_phy *phy = &mvi->phy[i];
20b09c29 1231 struct mvs_port *port = phy->port;
dd4969a8 1232
20b09c29 1233 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);
dd4969a8
JG		 1234 if ((tmp & PHY_READY_MASK) && !(phy->irq_status & PHYEV_POOF)) {
1235 if (!port)
1236 phy->phy_attached = 1;
1237 return tmp;
1238 }
1239
1240 if (port) {
1241 if (phy->phy_type & PORT_TYPE_SAS) {
1242 port->wide_port_phymap &= ~(1U << i);
1243 if (!port->wide_port_phymap)
1244 port->port_attached = 0;
1245 mvs_update_wideport(mvi, i);
1246 } else if (phy->phy_type & PORT_TYPE_SATA)
1247 port->port_attached = 0;
dd4969a8
JG		 1248 phy->port = NULL;
1249 phy->phy_attached = 0;
1250 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1251 }
1252 return 0;
1253}
1254
1255static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
1256{
1257 u32 *s = (u32 *) buf;
1258
1259 if (!s)
1260 return NULL;
1261
20b09c29
AY		 1262 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
1263 s[3] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
dd4969a8 1264
20b09c29
AY		 1265 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
1266 s[2] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
dd4969a8 1267
20b09c29
AY		 1268 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
1269 s[1] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
dd4969a8 1270
20b09c29
AY		 1271 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
1272 s[0] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
1273
1274 /* Workaround: take some ATAPI devices for ATA */
1275 if (((s[1] & 0x00FFFFFF) == 0x00EB1401) && (*(u8 *)&s[3] == 0x01))
1276 s[1] = 0x00EB1401 | (*((u8 *)&s[1] + 3) & 0x10);
dd4969a8 1277
f9da3be5 1278 return s;
dd4969a8
JG		 1279}
1280
1281static u32 mvs_is_sig_fis_received(u32 irq_status)
1282{
1283 return irq_status & PHYEV_SIG_FIS;
1284}
1285
20b09c29 1286void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st)
dd4969a8
JG		 1287{
1288 struct mvs_phy *phy = &mvi->phy[i];
20b09c29 1289 struct sas_identify_frame *id;
b5762948 1290
20b09c29 1291 id = (struct sas_identify_frame *)phy->frame_rcvd;
b5762948 1292
dd4969a8 1293 if (get_st) {
20b09c29 1294 phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);
dd4969a8
JG		 1295 phy->phy_status = mvs_is_phy_ready(mvi, i);
1296 }
8f261aaf 1297
dd4969a8 1298 if (phy->phy_status) {
20b09c29
AY		 1299 int oob_done = 0;
1300 struct asd_sas_phy *sas_phy = &mvi->phy[i].sas_phy;
b5762948 1301
20b09c29
AY		 1302 oob_done = MVS_CHIP_DISP->oob_done(mvi, i);
1303
1304 MVS_CHIP_DISP->fix_phy_info(mvi, i, id);
1305 if (phy->phy_type & PORT_TYPE_SATA) {
1306 phy->identify.target_port_protocols = SAS_PROTOCOL_STP;
1307 if (mvs_is_sig_fis_received(phy->irq_status)) {
1308 phy->phy_attached = 1;
1309 phy->att_dev_sas_addr =
1310 i + mvi->id * mvi->chip->n_phy;
1311 if (oob_done)
1312 sas_phy->oob_mode = SATA_OOB_MODE;
1313 phy->frame_rcvd_size =
1314 sizeof(struct dev_to_host_fis);
f9da3be5 1315 mvs_get_d2h_reg(mvi, i, id);
20b09c29
AY		 1316 } else {
1317 u32 tmp;
1318 dev_printk(KERN_DEBUG, mvi->dev,
1319 "Phy%d : No sig fis\n", i);
1320 tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);
1321 MVS_CHIP_DISP->write_port_irq_mask(mvi, i,
1322 tmp | PHYEV_SIG_FIS);
1323 phy->phy_attached = 0;
1324 phy->phy_type &= ~PORT_TYPE_SATA;
1325 MVS_CHIP_DISP->phy_reset(mvi, i, 0);
1326 goto out_done;
1327 }
9dc9fd94 1328 } else if (phy->phy_type & PORT_TYPE_SAS
20b09c29
AY		 1329 || phy->att_dev_info & PORT_SSP_INIT_MASK) {
1330 phy->phy_attached = 1;
dd4969a8 1331 phy->identify.device_type =
20b09c29 1332 phy->att_dev_info & PORT_DEV_TYPE_MASK;
b5762948 1333
dd4969a8
JG		 1334 if (phy->identify.device_type == SAS_END_DEV)
1335 phy->identify.target_port_protocols =
1336 SAS_PROTOCOL_SSP;
1337 else if (phy->identify.device_type != NO_DEVICE)
1338 phy->identify.target_port_protocols =
1339 SAS_PROTOCOL_SMP;
20b09c29 1340 if (oob_done)
dd4969a8
JG		 1341 sas_phy->oob_mode = SAS_OOB_MODE;
1342 phy->frame_rcvd_size =
1343 sizeof(struct sas_identify_frame);
dd4969a8 1344 }
20b09c29
AY		 1345 memcpy(sas_phy->attached_sas_addr,
1346 &phy->att_dev_sas_addr, SAS_ADDR_SIZE);
b5762948 1347
20b09c29
AY		 1348 if (MVS_CHIP_DISP->phy_work_around)
1349 MVS_CHIP_DISP->phy_work_around(mvi, i);
dd4969a8 1350 }
20b09c29
AY		 1351 mv_dprintk("port %d attach dev info is %x\n",
1352 i + mvi->id * mvi->chip->n_phy, phy->att_dev_info);
1353 mv_dprintk("port %d attach sas addr is %llx\n",
1354 i + mvi->id * mvi->chip->n_phy, phy->att_dev_sas_addr);
4e52fc0a 1355out_done:
dd4969a8 1356 if (get_st)
20b09c29 1357 MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);
b5762948
JG		 1358}
1359
20b09c29 1360static void mvs_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
8f261aaf 1361{
dd4969a8 1362 struct sas_ha_struct *sas_ha = sas_phy->ha;
20b09c29 1363 struct mvs_info *mvi = NULL; int i = 0, hi;
dd4969a8 1364 struct mvs_phy *phy = sas_phy->lldd_phy;
20b09c29
AY		 1365 struct asd_sas_port *sas_port = sas_phy->port;
1366 struct mvs_port *port;
1367 unsigned long flags = 0;
1368 if (!sas_port)
1369 return;
8f261aaf 1370
20b09c29
AY		 1371 while (sas_ha->sas_phy[i]) {
1372 if (sas_ha->sas_phy[i] == sas_phy)
1373 break;
1374 i++;
1375 }
1376 hi = i/((struct mvs_prv_info *)sas_ha->lldd_ha)->n_phy;
1377 mvi = ((struct mvs_prv_info *)sas_ha->lldd_ha)->mvi[hi];
1378 if (sas_port->id >= mvi->chip->n_phy)
1379 port = &mvi->port[sas_port->id - mvi->chip->n_phy];
1380 else
1381 port = &mvi->port[sas_port->id];
1382 if (lock)
1383 spin_lock_irqsave(&mvi->lock, flags);
dd4969a8
JG		 1384 port->port_attached = 1;
1385 phy->port = port;
0b15fb1f 1386 sas_port->lldd_port = port;
dd4969a8
JG		 1387 if (phy->phy_type & PORT_TYPE_SAS) {
1388 port->wide_port_phymap = sas_port->phy_mask;
20b09c29 1389 mv_printk("set wide port phy map %x\n", sas_port->phy_mask);
dd4969a8 1390 mvs_update_wideport(mvi, sas_phy->id);
8f261aaf 1391 }
20b09c29
AY		 1392 if (lock)
1393 spin_unlock_irqrestore(&mvi->lock, flags);
dd4969a8
JG		 1394}
1395
20b09c29 1396static void mvs_port_notify_deformed(struct asd_sas_phy *sas_phy, int lock)
dd4969a8 1397{
9dc9fd94
S		 1398 struct domain_device *dev;
1399 struct mvs_phy *phy = sas_phy->lldd_phy;
1400 struct mvs_info *mvi = phy->mvi;
1401 struct asd_sas_port *port = sas_phy->port;
1402 int phy_no = 0;
1403
1404 while (phy != &mvi->phy[phy_no]) {
1405 phy_no++;
1406 if (phy_no >= MVS_MAX_PHYS)
1407 return;
1408 }
1409 list_for_each_entry(dev, &port->dev_list, dev_list_node)
1410 mvs_do_release_task(phy->mvi, phy_no, NULL);
1411
dd4969a8
JG		 1412}
1413
dd4969a8 1414
20b09c29
AY		 1415void mvs_port_formed(struct asd_sas_phy *sas_phy)
1416{
1417 mvs_port_notify_formed(sas_phy, 1);
dd4969a8
JG		 1418}
1419
20b09c29 1420void mvs_port_deformed(struct asd_sas_phy *sas_phy)
dd4969a8 1421{
20b09c29
AY		 1422 mvs_port_notify_deformed(sas_phy, 1);
1423}
8f261aaf 1424
20b09c29
AY		 1425struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
1426{
1427 u32 dev;
1428 for (dev = 0; dev < MVS_MAX_DEVICES; dev++) {
1429 if (mvi->devices[dev].dev_type == NO_DEVICE) {
1430 mvi->devices[dev].device_id = dev;
1431 return &mvi->devices[dev];
1432 }
8f261aaf 1433 }
8121ed42 1434
20b09c29
AY		 1435 if (dev == MVS_MAX_DEVICES)
1436 mv_printk("max support %d devices, ignore ..\n",
1437 MVS_MAX_DEVICES);
1438
1439 return NULL;
8f261aaf
KW		 1440}
1441
20b09c29 1442void mvs_free_dev(struct mvs_device *mvi_dev)
b5762948 1443{
20b09c29
AY		 1444 u32 id = mvi_dev->device_id;
1445 memset(mvi_dev, 0, sizeof(*mvi_dev));
1446 mvi_dev->device_id = id;
1447 mvi_dev->dev_type = NO_DEVICE;
1448 mvi_dev->dev_status = MVS_DEV_NORMAL;
1449 mvi_dev->taskfileset = MVS_ID_NOT_MAPPED;
1450}
b5762948 1451
20b09c29
AY		 1452int mvs_dev_found_notify(struct domain_device *dev, int lock)
1453{
1454 unsigned long flags = 0;
1455 int res = 0;
1456 struct mvs_info *mvi = NULL;
1457 struct domain_device *parent_dev = dev->parent;
1458 struct mvs_device *mvi_device;
b5762948 1459
20b09c29 1460 mvi = mvs_find_dev_mvi(dev);
b5762948 1461
20b09c29
AY		 1462 if (lock)
1463 spin_lock_irqsave(&mvi->lock, flags);
1464
1465 mvi_device = mvs_alloc_dev(mvi);
1466 if (!mvi_device) {
1467 res = -1;
1468 goto found_out;
b5762948 1469 }
f9da3be5 1470 dev->lldd_dev = mvi_device;
9dc9fd94 1471 mvi_device->dev_status = MVS_DEV_NORMAL;
20b09c29 1472 mvi_device->dev_type = dev->dev_type;
9870d9a2 1473 mvi_device->mvi_info = mvi;
20b09c29
AY		 1474 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) {
1475 int phy_id;
1476 u8 phy_num = parent_dev->ex_dev.num_phys;
1477 struct ex_phy *phy;
1478 for (phy_id = 0; phy_id < phy_num; phy_id++) {
1479 phy = &parent_dev->ex_dev.ex_phy[phy_id];
1480 if (SAS_ADDR(phy->attached_sas_addr) ==
1481 SAS_ADDR(dev->sas_addr)) {
1482 mvi_device->attached_phy = phy_id;
1483 break;
1484 }
1485 }
b5762948 1486
20b09c29
AY		 1487 if (phy_id == phy_num) {
1488 mv_printk("Error: no attached dev:%016llx"
1489 "at ex:%016llx.\n",
1490 SAS_ADDR(dev->sas_addr),
1491 SAS_ADDR(parent_dev->sas_addr));
1492 res = -1;
1493 }
dd4969a8 1494 }
b5762948 1495
20b09c29
AY		 1496found_out:
1497 if (lock)
1498 spin_unlock_irqrestore(&mvi->lock, flags);
1499 return res;
1500}
b5762948 1501
20b09c29
AY		 1502int mvs_dev_found(struct domain_device *dev)
1503{
1504 return mvs_dev_found_notify(dev, 1);
1505}
b5762948 1506
9dc9fd94 1507void mvs_dev_gone_notify(struct domain_device *dev)
20b09c29
AY		 1508{
1509 unsigned long flags = 0;
f9da3be5 1510 struct mvs_device *mvi_dev = dev->lldd_dev;
9870d9a2 1511 struct mvs_info *mvi = mvi_dev->mvi_info;
b5762948 1512
9dc9fd94 1513 spin_lock_irqsave(&mvi->lock, flags);
b5762948 1514
20b09c29
AY		 1515 if (mvi_dev) {
1516 mv_dprintk("found dev[%d:%x] is gone.\n",
1517 mvi_dev->device_id, mvi_dev->dev_type);
9dc9fd94 1518 mvs_release_task(mvi, dev);
20b09c29
AY		 1519 mvs_free_reg_set(mvi, mvi_dev);
1520 mvs_free_dev(mvi_dev);
1521 } else {
1522 mv_dprintk("found dev has gone.\n");
b5762948 1523 }
20b09c29 1524 dev->lldd_dev = NULL;
b5762948 1525
9dc9fd94 1526 spin_unlock_irqrestore(&mvi->lock, flags);
b5762948
JG		 1527}
1528
b5762948 1529
20b09c29
AY		 1530void mvs_dev_gone(struct domain_device *dev)
1531{
9dc9fd94 1532 mvs_dev_gone_notify(dev);
20b09c29 1533}
b5762948 1534
20b09c29
AY		 1535static struct sas_task *mvs_alloc_task(void)
1536{
1537 struct sas_task *task = kzalloc(sizeof(struct sas_task), GFP_KERNEL);
1538
1539 if (task) {
1540 INIT_LIST_HEAD(&task->list);
1541 spin_lock_init(&task->task_state_lock);
1542 task->task_state_flags = SAS_TASK_STATE_PENDING;
1543 init_timer(&task->timer);
1544 init_completion(&task->completion);
b5762948 1545 }
20b09c29 1546 return task;
dd4969a8 1547}
b5762948 1548
20b09c29 1549static void mvs_free_task(struct sas_task *task)
dd4969a8 1550{
20b09c29
AY		 1551 if (task) {
1552 BUG_ON(!list_empty(&task->list));
1553 kfree(task);
b5762948 1554 }
20b09c29 1555}
b5762948 1556
20b09c29
AY		 1557static void mvs_task_done(struct sas_task *task)
1558{
1559 if (!del_timer(&task->timer))
1560 return;
1561 complete(&task->completion);
b5762948 1562}
b5762948 1563
20b09c29 1564static void mvs_tmf_timedout(unsigned long data)
b5762948 1565{
20b09c29 1566 struct sas_task *task = (struct sas_task *)data;
8f261aaf 1567
20b09c29
AY		 1568 task->task_state_flags |= SAS_TASK_STATE_ABORTED;
1569 complete(&task->completion);
1570}
8f261aaf 1571
20b09c29
AY		 1572/* XXX */
1573#define MVS_TASK_TIMEOUT 20
1574static int mvs_exec_internal_tmf_task(struct domain_device *dev,
1575 void *parameter, u32 para_len, struct mvs_tmf_task *tmf)
1576{
1577 int res, retry;
1578 struct sas_task *task = NULL;
8f261aaf 1579
20b09c29
AY		 1580 for (retry = 0; retry < 3; retry++) {
1581 task = mvs_alloc_task();
1582 if (!task)
1583 return -ENOMEM;
8f261aaf 1584
20b09c29
AY		 1585 task->dev = dev;
1586 task->task_proto = dev->tproto;
8f261aaf 1587
20b09c29
AY		 1588 memcpy(&task->ssp_task, parameter, para_len);
1589 task->task_done = mvs_task_done;
8f261aaf 1590
20b09c29
AY		 1591 task->timer.data = (unsigned long) task;
1592 task->timer.function = mvs_tmf_timedout;
1593 task->timer.expires = jiffies + MVS_TASK_TIMEOUT*HZ;
1594 add_timer(&task->timer);
8f261aaf 1595
0b84b709 1596 res = mvs_task_exec(task, 1, GFP_KERNEL, NULL, 1, tmf);
8f261aaf 1597
20b09c29
AY		 1598 if (res) {
1599 del_timer(&task->timer);
1600 mv_printk("executing internel task failed:%d\n", res);
1601 goto ex_err;
1602 }
8f261aaf 1603
20b09c29
AY		 1604 wait_for_completion(&task->completion);
1605 res = -TMF_RESP_FUNC_FAILED;
1606 /* Even TMF timed out, return direct. */
1607 if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
1608 if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
1609 mv_printk("TMF task[%x] timeout.\n", tmf->tmf);
1610 goto ex_err;
1611 }
1612 }
8f261aaf 1613
20b09c29 1614 if (task->task_status.resp == SAS_TASK_COMPLETE &&
df64d3ca 1615 task->task_status.stat == SAM_STAT_GOOD) {
20b09c29
AY		 1616 res = TMF_RESP_FUNC_COMPLETE;
1617 break;
1618 }
b5762948 1619
20b09c29
AY		 1620 if (task->task_status.resp == SAS_TASK_COMPLETE &&
1621 task->task_status.stat == SAS_DATA_UNDERRUN) {
1622 /* no error, but return the number of bytes of
1623 * underrun */
1624 res = task->task_status.residual;
1625 break;
1626 }
b5762948 1627
20b09c29
AY		 1628 if (task->task_status.resp == SAS_TASK_COMPLETE &&
1629 task->task_status.stat == SAS_DATA_OVERRUN) {
1630 mv_dprintk("blocked task error.\n");
1631 res = -EMSGSIZE;
1632 break;
1633 } else {
1634 mv_dprintk(" task to dev %016llx response: 0x%x "
1635 "status 0x%x\n",
1636 SAS_ADDR(dev->sas_addr),
1637 task->task_status.resp,
1638 task->task_status.stat);
1639 mvs_free_task(task);
1640 task = NULL;
b5762948 1641
dd4969a8 1642 }
dd4969a8 1643 }
20b09c29
AY		 1644ex_err:
1645 BUG_ON(retry == 3 && task != NULL);
1646 if (task != NULL)
1647 mvs_free_task(task);
1648 return res;
dd4969a8 1649}
b5762948 1650
20b09c29
AY		 1651static int mvs_debug_issue_ssp_tmf(struct domain_device *dev,
1652 u8 *lun, struct mvs_tmf_task *tmf)
dd4969a8 1653{
20b09c29
AY		 1654 struct sas_ssp_task ssp_task;
1655 DECLARE_COMPLETION_ONSTACK(completion);
1656 if (!(dev->tproto & SAS_PROTOCOL_SSP))
1657 return TMF_RESP_FUNC_ESUPP;
b5762948 1658
20b09c29 1659 strncpy((u8 *)&ssp_task.LUN, lun, 8);
b5762948 1660
20b09c29
AY		 1661 return mvs_exec_internal_tmf_task(dev, &ssp_task,
1662 sizeof(ssp_task), tmf);
1663}
8f261aaf 1664
8f261aaf 1665
20b09c29
AY		 1666/* Standard mandates link reset for ATA (type 0)
1667 and hard reset for SSP (type 1) , only for RECOVERY */
1668static int mvs_debug_I_T_nexus_reset(struct domain_device *dev)
1669{
1670 int rc;
1671 struct sas_phy *phy = sas_find_local_phy(dev);
1672 int reset_type = (dev->dev_type == SATA_DEV ||
1673 (dev->tproto & SAS_PROTOCOL_STP)) ? 0 : 1;
1674 rc = sas_phy_reset(phy, reset_type);
1675 msleep(2000);
1676 return rc;
1677}
8f261aaf 1678
20b09c29
AY		 1679/* mandatory SAM-3 */
1680int mvs_lu_reset(struct domain_device *dev, u8 *lun)
1681{
1682 unsigned long flags;
1683 int i, phyno[WIDE_PORT_MAX_PHY], num , rc = TMF_RESP_FUNC_FAILED;
1684 struct mvs_tmf_task tmf_task;
f9da3be5 1685 struct mvs_device * mvi_dev = dev->lldd_dev;
9870d9a2 1686 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY		 1687
1688 tmf_task.tmf = TMF_LU_RESET;
1689 mvi_dev->dev_status = MVS_DEV_EH;
1690 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
1691 if (rc == TMF_RESP_FUNC_COMPLETE) {
1692 num = mvs_find_dev_phyno(dev, phyno);
1693 spin_lock_irqsave(&mvi->lock, flags);
1694 for (i = 0; i < num; i++)
9dc9fd94 1695 mvs_release_task(mvi, dev);
20b09c29 1696 spin_unlock_irqrestore(&mvi->lock, flags);
dd4969a8 1697 }
20b09c29
AY		 1698 /* If failed, fall-through I_T_Nexus reset */
1699 mv_printk("%s for device[%x]:rc= %d\n", __func__,
1700 mvi_dev->device_id, rc);
1701 return rc;
1702}
8f261aaf 1703
20b09c29
AY		 1704int mvs_I_T_nexus_reset(struct domain_device *dev)
1705{
1706 unsigned long flags;
9dc9fd94
S		 1707 int rc = TMF_RESP_FUNC_FAILED;
1708 struct mvs_device * mvi_dev = (struct mvs_device *)dev->lldd_dev;
9870d9a2 1709 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY		 1710
1711 if (mvi_dev->dev_status != MVS_DEV_EH)
1712 return TMF_RESP_FUNC_COMPLETE;
1713 rc = mvs_debug_I_T_nexus_reset(dev);
1714 mv_printk("%s for device[%x]:rc= %d\n",
1715 __func__, mvi_dev->device_id, rc);
1716
1717 /* housekeeper */
20b09c29 1718 spin_lock_irqsave(&mvi->lock, flags);
9dc9fd94 1719 mvs_release_task(mvi, dev);
20b09c29
AY		 1720 spin_unlock_irqrestore(&mvi->lock, flags);
1721
1722 return rc;
1723}
1724/* optional SAM-3 */
1725int mvs_query_task(struct sas_task *task)
1726{
1727 u32 tag;
1728 struct scsi_lun lun;
1729 struct mvs_tmf_task tmf_task;
1730 int rc = TMF_RESP_FUNC_FAILED;
1731
1732 if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
1733 struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
1734 struct domain_device *dev = task->dev;
9870d9a2
AY		 1735 struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
1736 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY		 1737
1738 int_to_scsilun(cmnd->device->lun, &lun);
1739 rc = mvs_find_tag(mvi, task, &tag);
1740 if (rc == 0) {
1741 rc = TMF_RESP_FUNC_FAILED;
dd4969a8 1742 return rc;
20b09c29 1743 }
8f261aaf 1744
20b09c29
AY		 1745 tmf_task.tmf = TMF_QUERY_TASK;
1746 tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
8f261aaf 1747
20b09c29
AY		 1748 rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
1749 switch (rc) {
1750 /* The task is still in Lun, release it then */
1751 case TMF_RESP_FUNC_SUCC:
1752 /* The task is not in Lun or failed, reset the phy */
1753 case TMF_RESP_FUNC_FAILED:
1754 case TMF_RESP_FUNC_COMPLETE:
1755 break;
9dc9fd94
S		 1756 default:
1757 rc = TMF_RESP_FUNC_COMPLETE;
1758 break;
20b09c29 1759 }
dd4969a8 1760 }
20b09c29
AY		 1761 mv_printk("%s:rc= %d\n", __func__, rc);
1762 return rc;
8f261aaf
KW		 1763}
1764
20b09c29
AY		 1765/* mandatory SAM-3, still need free task/slot info */
1766int mvs_abort_task(struct sas_task *task)
8f261aaf 1767{
20b09c29
AY		 1768 struct scsi_lun lun;
1769 struct mvs_tmf_task tmf_task;
1770 struct domain_device *dev = task->dev;
9870d9a2 1771 struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
24ae163e 1772 struct mvs_info *mvi;
20b09c29
AY		 1773 int rc = TMF_RESP_FUNC_FAILED;
1774 unsigned long flags;
1775 u32 tag;
9870d9a2 1776
9dc9fd94
S		 1777 if (!mvi_dev) {
1778 mv_printk("%s:%d TMF_RESP_FUNC_FAILED\n", __func__, __LINE__);
1779 rc = TMF_RESP_FUNC_FAILED;
1780 }
1781
24ae163e
JS		 1782 mvi = mvi_dev->mvi_info;
1783
20b09c29
AY		 1784 spin_lock_irqsave(&task->task_state_lock, flags);
1785 if (task->task_state_flags & SAS_TASK_STATE_DONE) {
1786 spin_unlock_irqrestore(&task->task_state_lock, flags);
1787 rc = TMF_RESP_FUNC_COMPLETE;
1788 goto out;
dd4969a8 1789 }
20b09c29 1790 spin_unlock_irqrestore(&task->task_state_lock, flags);
9dc9fd94 1791 mvi_dev->dev_status = MVS_DEV_EH;
20b09c29
AY		 1792 if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
1793 struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
1794
1795 int_to_scsilun(cmnd->device->lun, &lun);
1796 rc = mvs_find_tag(mvi, task, &tag);
1797 if (rc == 0) {
1798 mv_printk("No such tag in %s\n", __func__);
1799 rc = TMF_RESP_FUNC_FAILED;
1800 return rc;
1801 }
8f261aaf 1802
20b09c29
AY		 1803 tmf_task.tmf = TMF_ABORT_TASK;
1804 tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
8f261aaf 1805
20b09c29 1806 rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
8f261aaf 1807
20b09c29
AY		 1808 /* if successful, clear the task and callback forwards.*/
1809 if (rc == TMF_RESP_FUNC_COMPLETE) {
1810 u32 slot_no;
1811 struct mvs_slot_info *slot;
8f261aaf 1812
20b09c29 1813 if (task->lldd_task) {
f9da3be5 1814 slot = task->lldd_task;
20b09c29 1815 slot_no = (u32) (slot - mvi->slot_info);
9dc9fd94 1816 spin_lock_irqsave(&mvi->lock, flags);
20b09c29 1817 mvs_slot_complete(mvi, slot_no, 1);
9dc9fd94 1818 spin_unlock_irqrestore(&mvi->lock, flags);
20b09c29
AY		 1819 }
1820 }
9dc9fd94 1821
20b09c29
AY		 1822 } else if (task->task_proto & SAS_PROTOCOL_SATA ||
1823 task->task_proto & SAS_PROTOCOL_STP) {
1824 /* to do free register_set */
9dc9fd94
S		 1825 if (SATA_DEV == dev->dev_type) {
1826 struct mvs_slot_info *slot = task->lldd_task;
1827 struct task_status_struct *tstat;
1828 u32 slot_idx = (u32)(slot - mvi->slot_info);
1829 tstat = &task->task_status;
1830 mv_dprintk(KERN_DEBUG "mv_abort_task() mvi=%p task=%p "
1831 "slot=%p slot_idx=x%x\n",
1832 mvi, task, slot, slot_idx);
1833 tstat->stat = SAS_ABORTED_TASK;
1834 if (mvi_dev && mvi_dev->running_req)
1835 mvi_dev->running_req--;
1836 if (sas_protocol_ata(task->task_proto))
1837 mvs_free_reg_set(mvi, mvi_dev);
1838 mvs_slot_task_free(mvi, task, slot, slot_idx);
1839 return -1;
1840 }
20b09c29
AY		 1841 } else {
1842 /* SMP */
8f261aaf 1843
20b09c29
AY		 1844 }
1845out:
1846 if (rc != TMF_RESP_FUNC_COMPLETE)
1847 mv_printk("%s:rc= %d\n", __func__, rc);
dd4969a8 1848 return rc;
8f261aaf
KW		 1849}
1850
20b09c29 1851int mvs_abort_task_set(struct domain_device *dev, u8 *lun)
8f261aaf 1852{
20b09c29
AY		 1853 int rc = TMF_RESP_FUNC_FAILED;
1854 struct mvs_tmf_task tmf_task;
8f261aaf 1855
20b09c29
AY		 1856 tmf_task.tmf = TMF_ABORT_TASK_SET;
1857 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
dd4969a8 1858
20b09c29 1859 return rc;
8f261aaf
KW		 1860}
1861
20b09c29 1862int mvs_clear_aca(struct domain_device *dev, u8 *lun)
8f261aaf 1863{
20b09c29
AY		 1864 int rc = TMF_RESP_FUNC_FAILED;
1865 struct mvs_tmf_task tmf_task;
8f261aaf 1866
20b09c29
AY		 1867 tmf_task.tmf = TMF_CLEAR_ACA;
1868 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
8f261aaf 1869
20b09c29
AY		 1870 return rc;
1871}
8f261aaf 1872
20b09c29
AY		 1873int mvs_clear_task_set(struct domain_device *dev, u8 *lun)
1874{
1875 int rc = TMF_RESP_FUNC_FAILED;
1876 struct mvs_tmf_task tmf_task;
8f261aaf 1877
20b09c29
AY		 1878 tmf_task.tmf = TMF_CLEAR_TASK_SET;
1879 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
8f261aaf 1880
20b09c29 1881 return rc;
dd4969a8 1882}
8f261aaf 1883
20b09c29
AY		 1884static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
1885 u32 slot_idx, int err)
dd4969a8 1886{
f9da3be5 1887 struct mvs_device *mvi_dev = task->dev->lldd_dev;
20b09c29
AY		 1888 struct task_status_struct *tstat = &task->task_status;
1889 struct ata_task_resp *resp = (struct ata_task_resp *)tstat->buf;
df64d3ca 1890 int stat = SAM_STAT_GOOD;
e9ff91b6 1891
8f261aaf 1892
20b09c29
AY		 1893 resp->frame_len = sizeof(struct dev_to_host_fis);
1894 memcpy(&resp->ending_fis[0],
1895 SATA_RECEIVED_D2H_FIS(mvi_dev->taskfileset),
1896 sizeof(struct dev_to_host_fis));
1897 tstat->buf_valid_size = sizeof(*resp);
9dc9fd94
S		 1898 if (unlikely(err)) {
1899 if (unlikely(err & CMD_ISS_STPD))
1900 stat = SAS_OPEN_REJECT;
1901 else
1902 stat = SAS_PROTO_RESPONSE;
1903 }
1904
20b09c29 1905 return stat;
8f261aaf
KW		 1906}
1907
20b09c29
AY		 1908static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
1909 u32 slot_idx)
8f261aaf 1910{
20b09c29
AY		 1911 struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1912 int stat;
1913 u32 err_dw0 = le32_to_cpu(*(u32 *) (slot->response));
1914 u32 tfs = 0;
1915 enum mvs_port_type type = PORT_TYPE_SAS;
8f261aaf 1916
20b09c29
AY		 1917 if (err_dw0 & CMD_ISS_STPD)
1918 MVS_CHIP_DISP->issue_stop(mvi, type, tfs);
1919
1920 MVS_CHIP_DISP->command_active(mvi, slot_idx);
b5762948 1921
df64d3ca 1922 stat = SAM_STAT_CHECK_CONDITION;
dd4969a8 1923 switch (task->task_proto) {
dd4969a8 1924 case SAS_PROTOCOL_SSP:
20b09c29
AY		 1925 stat = SAS_ABORTED_TASK;
1926 break;
1927 case SAS_PROTOCOL_SMP:
df64d3ca 1928 stat = SAM_STAT_CHECK_CONDITION;
dd4969a8 1929 break;
20b09c29 1930
dd4969a8
JG		 1931 case SAS_PROTOCOL_SATA:
1932 case SAS_PROTOCOL_STP:
20b09c29
AY		 1933 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1934 {
1935 if (err_dw0 == 0x80400002)
1936 mv_printk("find reserved error, why?\n");
1937
1938 task->ata_task.use_ncq = 0;
9dc9fd94 1939 mvs_sata_done(mvi, task, slot_idx, err_dw0);
dd4969a8 1940 }
20b09c29 1941 break;
dd4969a8
JG		 1942 default:
1943 break;
1944 }
1945
20b09c29 1946 return stat;
e9ff91b6
KW		 1947}
1948
20b09c29 1949int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
b5762948 1950{
20b09c29
AY		 1951 u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
1952 struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1953 struct sas_task *task = slot->task;
1954 struct mvs_device *mvi_dev = NULL;
1955 struct task_status_struct *tstat;
9dc9fd94
S		 1956 struct domain_device *dev;
1957 u32 aborted;
20b09c29 1958
20b09c29
AY		 1959 void *to;
1960 enum exec_status sts;
1961
1962 if (mvi->exp_req)
1963 mvi->exp_req--;
9dc9fd94 1964 if (unlikely(!task || !task->lldd_task || !task->dev))
20b09c29
AY		 1965 return -1;
1966
1967 tstat = &task->task_status;
9dc9fd94
S		 1968 dev = task->dev;
1969 mvi_dev = dev->lldd_dev;
b5762948 1970
20b09c29
AY		 1971 mvs_hba_cq_dump(mvi);
1972
1973 spin_lock(&task->task_state_lock);
1974 task->task_state_flags &=
1975 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1976 task->task_state_flags |= SAS_TASK_STATE_DONE;
1977 /* race condition*/
1978 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
1979 spin_unlock(&task->task_state_lock);
1980
1981 memset(tstat, 0, sizeof(*tstat));
1982 tstat->resp = SAS_TASK_COMPLETE;
1983
1984 if (unlikely(aborted)) {
1985 tstat->stat = SAS_ABORTED_TASK;
9dc9fd94
S		 1986 if (mvi_dev && mvi_dev->running_req)
1987 mvi_dev->running_req--;
20b09c29
AY		 1988 if (sas_protocol_ata(task->task_proto))
1989 mvs_free_reg_set(mvi, mvi_dev);
1990
1991 mvs_slot_task_free(mvi, task, slot, slot_idx);
1992 return -1;
b5762948
JG		 1993 }
1994
9dc9fd94
S		 1995 if (unlikely(!mvi_dev || flags)) {
1996 if (!mvi_dev)
1997 mv_dprintk("port has not device.\n");
20b09c29
AY		 1998 tstat->stat = SAS_PHY_DOWN;
1999 goto out;
2000 }
b5762948 2001
20b09c29
AY		 2002 /* error info record present */
2003 if (unlikely((rx_desc & RXQ_ERR) && (*(u64 *) slot->response))) {
2004 tstat->stat = mvs_slot_err(mvi, task, slot_idx);
9dc9fd94 2005 tstat->resp = SAS_TASK_COMPLETE;
20b09c29 2006 goto out;
b5762948
JG		 2007 }
2008
20b09c29
AY		 2009 switch (task->task_proto) {
2010 case SAS_PROTOCOL_SSP:
2011 /* hw says status == 0, datapres == 0 */
2012 if (rx_desc & RXQ_GOOD) {
df64d3ca 2013 tstat->stat = SAM_STAT_GOOD;
20b09c29
AY		 2014 tstat->resp = SAS_TASK_COMPLETE;
2015 }
2016 /* response frame present */
2017 else if (rx_desc & RXQ_RSP) {
2018 struct ssp_response_iu *iu = slot->response +
2019 sizeof(struct mvs_err_info);
2020 sas_ssp_task_response(mvi->dev, task, iu);
2021 } else
df64d3ca 2022 tstat->stat = SAM_STAT_CHECK_CONDITION;
20b09c29 2023 break;
b5762948 2024
20b09c29
AY		 2025 case SAS_PROTOCOL_SMP: {
2026 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
df64d3ca 2027 tstat->stat = SAM_STAT_GOOD;
20b09c29
AY		 2028 to = kmap_atomic(sg_page(sg_resp), KM_IRQ0);
2029 memcpy(to + sg_resp->offset,
2030 slot->response + sizeof(struct mvs_err_info),
2031 sg_dma_len(sg_resp));
2032 kunmap_atomic(to, KM_IRQ0);
2033 break;
2034 }
8f261aaf 2035
20b09c29
AY		 2036 case SAS_PROTOCOL_SATA:
2037 case SAS_PROTOCOL_STP:
2038 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: {
2039 tstat->stat = mvs_sata_done(mvi, task, slot_idx, 0);
2040 break;
2041 }
b5762948 2042
20b09c29 2043 default:
df64d3ca 2044 tstat->stat = SAM_STAT_CHECK_CONDITION;
20b09c29
AY		 2045 break;
2046 }
9dc9fd94
S		 2047 if (!slot->port->port_attached) {
2048 mv_dprintk("port %d has removed.\n", slot->port->sas_port.id);
2049 tstat->stat = SAS_PHY_DOWN;
2050 }
2051
b5762948 2052
20b09c29 2053out:
9dc9fd94
S		 2054 if (mvi_dev && mvi_dev->running_req) {
2055 mvi_dev->running_req--;
2056 if (sas_protocol_ata(task->task_proto) && !mvi_dev->running_req)
0f980a87
AY		 2057 mvs_free_reg_set(mvi, mvi_dev);
2058 }
20b09c29
AY		 2059 mvs_slot_task_free(mvi, task, slot, slot_idx);
2060 sts = tstat->stat;
8f261aaf 2061
20b09c29
AY		 2062 spin_unlock(&mvi->lock);
2063 if (task->task_done)
2064 task->task_done(task);
2065 else
2066 mv_dprintk("why has not task_done.\n");
2067 spin_lock(&mvi->lock);
b5762948 2068
20b09c29
AY		 2069 return sts;
2070}
b5762948 2071
9dc9fd94 2072void mvs_do_release_task(struct mvs_info *mvi,
20b09c29
AY		 2073 int phy_no, struct domain_device *dev)
2074{
9dc9fd94 2075 u32 slot_idx;
20b09c29
AY		 2076 struct mvs_phy *phy;
2077 struct mvs_port *port;
2078 struct mvs_slot_info *slot, *slot2;
b5762948 2079
20b09c29
AY		 2080 phy = &mvi->phy[phy_no];
2081 port = phy->port;
2082 if (!port)
2083 return;
9dc9fd94
S		 2084 /* clean cmpl queue in case request is already finished */
2085 mvs_int_rx(mvi, false);
2086
2087
b5762948 2088
20b09c29
AY		 2089 list_for_each_entry_safe(slot, slot2, &port->list, entry) {
2090 struct sas_task *task;
2091 slot_idx = (u32) (slot - mvi->slot_info);
2092 task = slot->task;
b5762948 2093
20b09c29
AY		 2094 if (dev && task->dev != dev)
2095 continue;
8f261aaf 2096
20b09c29
AY		 2097 mv_printk("Release slot [%x] tag[%x], task [%p]:\n",
2098 slot_idx, slot->slot_tag, task);
9dc9fd94 2099 MVS_CHIP_DISP->command_active(mvi, slot_idx);
b5762948 2100
20b09c29 2101 mvs_slot_complete(mvi, slot_idx, 1);
b5762948 2102 }
20b09c29 2103}
b5762948 2104
9dc9fd94
S		 2105void mvs_release_task(struct mvs_info *mvi,
2106 struct domain_device *dev)
2107{
2108 int i, phyno[WIDE_PORT_MAX_PHY], num;
2109 /* housekeeper */
2110 num = mvs_find_dev_phyno(dev, phyno);
2111 for (i = 0; i < num; i++)
2112 mvs_do_release_task(mvi, phyno[i], dev);
2113}
2114
20b09c29
AY		 2115static void mvs_phy_disconnected(struct mvs_phy *phy)
2116{
2117 phy->phy_attached = 0;
2118 phy->att_dev_info = 0;
2119 phy->att_dev_sas_addr = 0;
2120}
2121
2122static void mvs_work_queue(struct work_struct *work)
2123{
2124 struct delayed_work *dw = container_of(work, struct delayed_work, work);
2125 struct mvs_wq *mwq = container_of(dw, struct mvs_wq, work_q);
2126 struct mvs_info *mvi = mwq->mvi;
2127 unsigned long flags;
b5762948 2128
20b09c29
AY		 2129 spin_lock_irqsave(&mvi->lock, flags);
2130 if (mwq->handler & PHY_PLUG_EVENT) {
2131 u32 phy_no = (unsigned long) mwq->data;
2132 struct sas_ha_struct *sas_ha = mvi->sas;
2133 struct mvs_phy *phy = &mvi->phy[phy_no];
2134 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2135
2136 if (phy->phy_event & PHY_PLUG_OUT) {
2137 u32 tmp;
2138 struct sas_identify_frame *id;
2139 id = (struct sas_identify_frame *)phy->frame_rcvd;
2140 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);
2141 phy->phy_event &= ~PHY_PLUG_OUT;
2142 if (!(tmp & PHY_READY_MASK)) {
2143 sas_phy_disconnected(sas_phy);
2144 mvs_phy_disconnected(phy);
2145 sas_ha->notify_phy_event(sas_phy,
2146 PHYE_LOSS_OF_SIGNAL);
2147 mv_dprintk("phy%d Removed Device\n", phy_no);
2148 } else {
2149 MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
2150 mvs_update_phyinfo(mvi, phy_no, 1);
2151 mvs_bytes_dmaed(mvi, phy_no);
2152 mvs_port_notify_formed(sas_phy, 0);
2153 mv_dprintk("phy%d Attached Device\n", phy_no);
2154 }
2155 }
2156 }
2157 list_del(&mwq->entry);
2158 spin_unlock_irqrestore(&mvi->lock, flags);
2159 kfree(mwq);
2160}
8f261aaf 2161
20b09c29
AY		 2162static int mvs_handle_event(struct mvs_info *mvi, void *data, int handler)
2163{
2164 struct mvs_wq *mwq;
2165 int ret = 0;
2166
2167 mwq = kmalloc(sizeof(struct mvs_wq), GFP_ATOMIC);
2168 if (mwq) {
2169 mwq->mvi = mvi;
2170 mwq->data = data;
2171 mwq->handler = handler;
2172 MV_INIT_DELAYED_WORK(&mwq->work_q, mvs_work_queue, mwq);
2173 list_add_tail(&mwq->entry, &mvi->wq_list);
2174 schedule_delayed_work(&mwq->work_q, HZ * 2);
2175 } else
2176 ret = -ENOMEM;
2177
2178 return ret;
2179}
b5762948 2180
20b09c29
AY		 2181static void mvs_sig_time_out(unsigned long tphy)
2182{
2183 struct mvs_phy *phy = (struct mvs_phy *)tphy;
2184 struct mvs_info *mvi = phy->mvi;
2185 u8 phy_no;
2186
2187 for (phy_no = 0; phy_no < mvi->chip->n_phy; phy_no++) {
2188 if (&mvi->phy[phy_no] == phy) {
2189 mv_dprintk("Get signature time out, reset phy %d\n",
2190 phy_no+mvi->id*mvi->chip->n_phy);
2191 MVS_CHIP_DISP->phy_reset(mvi, phy_no, 1);
2192 }
b5762948 2193 }
20b09c29 2194}
b5762948 2195
20b09c29
AY		 2196static void mvs_sig_remove_timer(struct mvs_phy *phy)
2197{
2198 if (phy->timer.function)
2199 del_timer(&phy->timer);
2200 phy->timer.function = NULL;
2201}
b5762948 2202
20b09c29
AY		 2203void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
2204{
2205 u32 tmp;
2206 struct sas_ha_struct *sas_ha = mvi->sas;
2207 struct mvs_phy *phy = &mvi->phy[phy_no];
2208 struct asd_sas_phy *sas_phy = &phy->sas_phy;
8f261aaf 2209
20b09c29
AY		 2210 phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
2211 mv_dprintk("port %d ctrl sts=0x%X.\n", phy_no+mvi->id*mvi->chip->n_phy,
2212 MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));
2213 mv_dprintk("Port %d irq sts = 0x%X\n", phy_no+mvi->id*mvi->chip->n_phy,
2214 phy->irq_status);
8f261aaf 2215
20b09c29
AY		 2216 /*
2217 * events is port event now ,
2218 * we need check the interrupt status which belongs to per port.
2219 */
b5762948 2220
9dc9fd94 2221 if (phy->irq_status & PHYEV_DCDR_ERR) {
20b09c29 2222 mv_dprintk("port %d STP decoding error.\n",
9dc9fd94
S		 2223 phy_no + mvi->id*mvi->chip->n_phy);
2224 }
20b09c29
AY		 2225
2226 if (phy->irq_status & PHYEV_POOF) {
2227 if (!(phy->phy_event & PHY_PLUG_OUT)) {
2228 int dev_sata = phy->phy_type & PORT_TYPE_SATA;
2229 int ready;
9dc9fd94 2230 mvs_do_release_task(mvi, phy_no, NULL);
20b09c29 2231 phy->phy_event |= PHY_PLUG_OUT;
9dc9fd94 2232 MVS_CHIP_DISP->clear_srs_irq(mvi, 0, 1);
20b09c29
AY		 2233 mvs_handle_event(mvi,
2234 (void *)(unsigned long)phy_no,
2235 PHY_PLUG_EVENT);
2236 ready = mvs_is_phy_ready(mvi, phy_no);
2237 if (!ready)
2238 mv_dprintk("phy%d Unplug Notice\n",
2239 phy_no +
2240 mvi->id * mvi->chip->n_phy);
2241 if (ready || dev_sata) {
2242 if (MVS_CHIP_DISP->stp_reset)
2243 MVS_CHIP_DISP->stp_reset(mvi,
2244 phy_no);
2245 else
2246 MVS_CHIP_DISP->phy_reset(mvi,
2247 phy_no, 0);
2248 return;
2249 }
2250 }
2251 }
b5762948 2252
20b09c29
AY		 2253 if (phy->irq_status & PHYEV_COMWAKE) {
2254 tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);
2255 MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,
2256 tmp | PHYEV_SIG_FIS);
2257 if (phy->timer.function == NULL) {
2258 phy->timer.data = (unsigned long)phy;
2259 phy->timer.function = mvs_sig_time_out;
2260 phy->timer.expires = jiffies + 10*HZ;
2261 add_timer(&phy->timer);
2262 }
2263 }
2264 if (phy->irq_status & (PHYEV_SIG_FIS | PHYEV_ID_DONE)) {
2265 phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
2266 mvs_sig_remove_timer(phy);
2267 mv_dprintk("notify plug in on phy[%d]\n", phy_no);
2268 if (phy->phy_status) {
2269 mdelay(10);
2270 MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
2271 if (phy->phy_type & PORT_TYPE_SATA) {
2272 tmp = MVS_CHIP_DISP->read_port_irq_mask(
2273 mvi, phy_no);
2274 tmp &= ~PHYEV_SIG_FIS;
2275 MVS_CHIP_DISP->write_port_irq_mask(mvi,
2276 phy_no, tmp);
2277 }
2278 mvs_update_phyinfo(mvi, phy_no, 0);
9dc9fd94
S		 2279 if (phy->phy_type & PORT_TYPE_SAS) {
2280 MVS_CHIP_DISP->phy_reset(mvi, phy_no, 2);
2281 mdelay(10);
2282 }
2283
20b09c29
AY		 2284 mvs_bytes_dmaed(mvi, phy_no);
2285 /* whether driver is going to handle hot plug */
2286 if (phy->phy_event & PHY_PLUG_OUT) {
2287 mvs_port_notify_formed(sas_phy, 0);
2288 phy->phy_event &= ~PHY_PLUG_OUT;
2289 }
2290 } else {
2291 mv_dprintk("plugin interrupt but phy%d is gone\n",
2292 phy_no + mvi->id*mvi->chip->n_phy);
2293 }
2294 } else if (phy->irq_status & PHYEV_BROAD_CH) {
2295 mv_dprintk("port %d broadcast change.\n",
2296 phy_no + mvi->id*mvi->chip->n_phy);
2297 /* exception for Samsung disk drive*/
2298 mdelay(1000);
2299 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2300 }
2301 MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
b5762948
JG		 2302}
2303
20b09c29 2304int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
b5762948 2305{
20b09c29
AY		 2306 u32 rx_prod_idx, rx_desc;
2307 bool attn = false;
b5762948 2308
20b09c29
AY		 2309 /* the first dword in the RX ring is special: it contains
2310 * a mirror of the hardware's RX producer index, so that
2311 * we don't have to stall the CPU reading that register.
2312 * The actual RX ring is offset by one dword, due to this.
2313 */
2314 rx_prod_idx = mvi->rx_cons;
2315 mvi->rx_cons = le32_to_cpu(mvi->rx[0]);
2316 if (mvi->rx_cons == 0xfff) /* h/w hasn't touched RX ring yet */
2317 return 0;
b5762948 2318
20b09c29
AY		 2319 /* The CMPL_Q may come late, read from register and try again
2320 * note: if coalescing is enabled,
2321 * it will need to read from register every time for sure
2322 */
2323 if (unlikely(mvi->rx_cons == rx_prod_idx))
2324 mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;
2325
2326 if (mvi->rx_cons == rx_prod_idx)
2327 return 0;
2328
2329 while (mvi->rx_cons != rx_prod_idx) {
2330 /* increment our internal RX consumer pointer */
2331 rx_prod_idx = (rx_prod_idx + 1) & (MVS_RX_RING_SZ - 1);
2332 rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);
2333
2334 if (likely(rx_desc & RXQ_DONE))
2335 mvs_slot_complete(mvi, rx_desc, 0);
2336 if (rx_desc & RXQ_ATTN) {
2337 attn = true;
2338 } else if (rx_desc & RXQ_ERR) {
2339 if (!(rx_desc & RXQ_DONE))
2340 mvs_slot_complete(mvi, rx_desc, 0);
2341 } else if (rx_desc & RXQ_SLOT_RESET) {
2342 mvs_slot_free(mvi, rx_desc);
2343 }
2344 }
2345
2346 if (attn && self_clear)
2347 MVS_CHIP_DISP->int_full(mvi);
2348 return 0;
b5762948
JG		 2349}
2350
kernel source for telekom puls (alcatel/mediatek)