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[SCSI] mvsas: bug fix with setting task management frame type
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / mvsas / mv_sas.c
CommitLineData
b5762948 1/*
20b09c29
AY		 2 * Marvell 88SE64xx/88SE94xx main function
3 *
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
6 *
7 * This file is licensed under GPLv2.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; version 2 of the
12 * License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA
23*/
b5762948 24
dd4969a8 25#include "mv_sas.h"
b5762948 26
dd4969a8
JG		 27static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
28{
29 if (task->lldd_task) {
30 struct mvs_slot_info *slot;
31 slot = (struct mvs_slot_info *) task->lldd_task;
20b09c29 32 *tag = slot->slot_tag;
dd4969a8
JG		 33 return 1;
34 }
35 return 0;
36}
8f261aaf 37
20b09c29 38void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
dd4969a8
JG		 39{
40 void *bitmap = (void *) &mvi->tags;
41 clear_bit(tag, bitmap);
42}
8f261aaf 43
20b09c29 44void mvs_tag_free(struct mvs_info *mvi, u32 tag)
dd4969a8
JG		 45{
46 mvs_tag_clear(mvi, tag);
47}
8f261aaf 48
20b09c29 49void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
dd4969a8
JG		 50{
51 void *bitmap = (void *) &mvi->tags;
52 set_bit(tag, bitmap);
53}
8f261aaf 54
20b09c29 55inline int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
dd4969a8
JG		 56{
57 unsigned int index, tag;
58 void *bitmap = (void *) &mvi->tags;
b5762948 59
20b09c29 60 index = find_first_zero_bit(bitmap, mvi->tags_num);
dd4969a8 61 tag = index;
20b09c29 62 if (tag >= mvi->tags_num)
dd4969a8
JG		 63 return -SAS_QUEUE_FULL;
64 mvs_tag_set(mvi, tag);
65 *tag_out = tag;
66 return 0;
67}
b5762948 68
dd4969a8
JG		 69void mvs_tag_init(struct mvs_info *mvi)
70{
71 int i;
20b09c29 72 for (i = 0; i < mvi->tags_num; ++i)
dd4969a8
JG		 73 mvs_tag_clear(mvi, i);
74}
b5762948 75
20b09c29 76void mvs_hexdump(u32 size, u8 *data, u32 baseaddr)
8f261aaf
KW		 77{
78 u32 i;
79 u32 run;
80 u32 offset;
81
82 offset = 0;
83 while (size) {
20b09c29 84 printk(KERN_DEBUG"%08X : ", baseaddr + offset);
8f261aaf
KW		 85 if (size >= 16)
86 run = 16;
87 else
88 run = size;
89 size -= run;
90 for (i = 0; i < 16; i++) {
91 if (i < run)
20b09c29 92 printk(KERN_DEBUG"%02X ", (u32)data[i]);
8f261aaf 93 else
20b09c29 94 printk(KERN_DEBUG" ");
8f261aaf 95 }
20b09c29 96 printk(KERN_DEBUG": ");
8f261aaf 97 for (i = 0; i < run; i++)
20b09c29
AY		 98 printk(KERN_DEBUG"%c",
99 isalnum(data[i]) ? data[i] : '.');
100 printk(KERN_DEBUG"\n");
8f261aaf
KW		 101 data = &data[16];
102 offset += run;
103 }
20b09c29 104 printk(KERN_DEBUG"\n");
8f261aaf
KW		 105}
106
20b09c29 107#if (_MV_DUMP > 1)
8f261aaf
KW		 108static void mvs_hba_sb_dump(struct mvs_info *mvi, u32 tag,
109 enum sas_protocol proto)
110{
8f261aaf 111 u32 offset;
8f261aaf
KW		 112 struct mvs_slot_info *slot = &mvi->slot_info[tag];
113
114 offset = slot->cmd_size + MVS_OAF_SZ +
20b09c29
AY		 115 MVS_CHIP_DISP->prd_size() * slot->n_elem;
116 dev_printk(KERN_DEBUG, mvi->dev, "+---->Status buffer[%d] :\n",
8f261aaf
KW		 117 tag);
118 mvs_hexdump(32, (u8 *) slot->response,
119 (u32) slot->buf_dma + offset);
8f261aaf 120}
ee1f1c2e 121#endif
8f261aaf
KW		 122
123static void mvs_hba_memory_dump(struct mvs_info *mvi, u32 tag,
124 enum sas_protocol proto)
125{
20b09c29 126#if (_MV_DUMP > 1)
ee1f1c2e 127 u32 sz, w_ptr;
8f261aaf 128 u64 addr;
8f261aaf
KW		 129 struct mvs_slot_info *slot = &mvi->slot_info[tag];
130
131 /*Delivery Queue */
20b09c29 132 sz = MVS_CHIP_SLOT_SZ;
ee1f1c2e 133 w_ptr = slot->tx;
20b09c29
AY		 134 addr = mvi->tx_dma;
135 dev_printk(KERN_DEBUG, mvi->dev,
ee1f1c2e 136 "Delivery Queue Size=%04d , WRT_PTR=%04X\n", sz, w_ptr);
20b09c29 137 dev_printk(KERN_DEBUG, mvi->dev,
8f261aaf
KW		 138 "Delivery Queue Base Address=0x%llX (PA)"
139 "(tx_dma=0x%llX), Entry=%04d\n",
20b09c29 140 addr, (unsigned long long)mvi->tx_dma, w_ptr);
8f261aaf
KW		 141 mvs_hexdump(sizeof(u32), (u8 *)(&mvi->tx[mvi->tx_prod]),
142 (u32) mvi->tx_dma + sizeof(u32) * w_ptr);
143 /*Command List */
ee1f1c2e 144 addr = mvi->slot_dma;
20b09c29 145 dev_printk(KERN_DEBUG, mvi->dev,
8f261aaf
KW		 146 "Command List Base Address=0x%llX (PA)"
147 "(slot_dma=0x%llX), Header=%03d\n",
20b09c29
AY		 148 addr, (unsigned long long)slot->buf_dma, tag);
149 dev_printk(KERN_DEBUG, mvi->dev, "Command Header[%03d]:\n", tag);
8f261aaf
KW		 150 /*mvs_cmd_hdr */
151 mvs_hexdump(sizeof(struct mvs_cmd_hdr), (u8 *)(&mvi->slot[tag]),
152 (u32) mvi->slot_dma + tag * sizeof(struct mvs_cmd_hdr));
153 /*1.command table area */
20b09c29 154 dev_printk(KERN_DEBUG, mvi->dev, "+---->Command Table :\n");
8f261aaf
KW		 155 mvs_hexdump(slot->cmd_size, (u8 *) slot->buf, (u32) slot->buf_dma);
156 /*2.open address frame area */
20b09c29 157 dev_printk(KERN_DEBUG, mvi->dev, "+---->Open Address Frame :\n");
8f261aaf
KW		 158 mvs_hexdump(MVS_OAF_SZ, (u8 *) slot->buf + slot->cmd_size,
159 (u32) slot->buf_dma + slot->cmd_size);
160 /*3.status buffer */
161 mvs_hba_sb_dump(mvi, tag, proto);
162 /*4.PRD table */
20b09c29
AY		 163 dev_printk(KERN_DEBUG, mvi->dev, "+---->PRD table :\n");
164 mvs_hexdump(MVS_CHIP_DISP->prd_size() * slot->n_elem,
8f261aaf
KW		 165 (u8 *) slot->buf + slot->cmd_size + MVS_OAF_SZ,
166 (u32) slot->buf_dma + slot->cmd_size + MVS_OAF_SZ);
167#endif
168}
169
170static void mvs_hba_cq_dump(struct mvs_info *mvi)
171{
ee1f1c2e 172#if (_MV_DUMP > 2)
8f261aaf
KW		 173 u64 addr;
174 void __iomem *regs = mvi->regs;
8f261aaf
KW		 175 u32 entry = mvi->rx_cons + 1;
176 u32 rx_desc = le32_to_cpu(mvi->rx[entry]);
177
178 /*Completion Queue */
179 addr = mr32(RX_HI) << 16 << 16 | mr32(RX_LO);
20b09c29 180 dev_printk(KERN_DEBUG, mvi->dev, "Completion Task = 0x%p\n",
ee1f1c2e 181 mvi->slot_info[rx_desc & RXQ_SLOT_MASK].task);
20b09c29 182 dev_printk(KERN_DEBUG, mvi->dev,
8f261aaf
KW		 183 "Completion List Base Address=0x%llX (PA), "
184 "CQ_Entry=%04d, CQ_WP=0x%08X\n",
185 addr, entry - 1, mvi->rx[0]);
186 mvs_hexdump(sizeof(u32), (u8 *)(&rx_desc),
187 mvi->rx_dma + sizeof(u32) * entry);
188#endif
189}
190
20b09c29 191void mvs_get_sas_addr(void *buf, u32 buflen)
8f261aaf 192{
20b09c29
AY		 193 /*memcpy(buf, "\x50\x05\x04\x30\x11\xab\x64\x40", 8);*/
194}
8f261aaf 195
20b09c29
AY		 196struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev)
197{
198 unsigned long i = 0, j = 0, hi = 0;
199 struct sas_ha_struct *sha = dev->port->ha;
200 struct mvs_info *mvi = NULL;
201 struct asd_sas_phy *phy;
202
203 while (sha->sas_port[i]) {
204 if (sha->sas_port[i] == dev->port) {
205 phy = container_of(sha->sas_port[i]->phy_list.next,
206 struct asd_sas_phy, port_phy_el);
207 j = 0;
208 while (sha->sas_phy[j]) {
209 if (sha->sas_phy[j] == phy)
210 break;
211 j++;
212 }
213 break;
214 }
215 i++;
216 }
217 hi = j/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
218 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
8f261aaf 219
20b09c29 220 return mvi;
8f261aaf 221
20b09c29 222}
8f261aaf 223
20b09c29
AY		 224/* FIXME */
225int mvs_find_dev_phyno(struct domain_device *dev, int *phyno)
226{
227 unsigned long i = 0, j = 0, n = 0, num = 0;
228 struct mvs_info *mvi = mvs_find_dev_mvi(dev);
229 struct sas_ha_struct *sha = dev->port->ha;
230
231 while (sha->sas_port[i]) {
232 if (sha->sas_port[i] == dev->port) {
233 struct asd_sas_phy *phy;
234 list_for_each_entry(phy,
235 &sha->sas_port[i]->phy_list, port_phy_el) {
236 j = 0;
237 while (sha->sas_phy[j]) {
238 if (sha->sas_phy[j] == phy)
239 break;
240 j++;
241 }
242 phyno[n] = (j >= mvi->chip->n_phy) ?
243 (j - mvi->chip->n_phy) : j;
244 num++;
245 n++;
dd4969a8 246 }
dd4969a8
JG		 247 break;
248 }
20b09c29
AY		 249 i++;
250 }
251 return num;
252}
253
254static inline void mvs_free_reg_set(struct mvs_info *mvi,
255 struct mvs_device *dev)
256{
257 if (!dev) {
258 mv_printk("device has been free.\n");
259 return;
260 }
261 if (dev->runing_req != 0)
262 return;
263 if (dev->taskfileset == MVS_ID_NOT_MAPPED)
264 return;
265 MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);
266}
267
268static inline u8 mvs_assign_reg_set(struct mvs_info *mvi,
269 struct mvs_device *dev)
270{
271 if (dev->taskfileset != MVS_ID_NOT_MAPPED)
272 return 0;
273 return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);
274}
275
276void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard)
277{
278 u32 no;
279 for_each_phy(phy_mask, phy_mask, no) {
280 if (!(phy_mask & 1))
281 continue;
282 MVS_CHIP_DISP->phy_reset(mvi, no, hard);
283 }
284}
285
286/* FIXME: locking? */
287int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
288 void *funcdata)
289{
290 int rc = 0, phy_id = sas_phy->id;
291 u32 tmp, i = 0, hi;
292 struct sas_ha_struct *sha = sas_phy->ha;
293 struct mvs_info *mvi = NULL;
294
295 while (sha->sas_phy[i]) {
296 if (sha->sas_phy[i] == sas_phy)
297 break;
298 i++;
299 }
300 hi = i/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
301 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
302
303 switch (func) {
304 case PHY_FUNC_SET_LINK_RATE:
305 MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);
306 break;
8f261aaf 307
dd4969a8 308 case PHY_FUNC_HARD_RESET:
20b09c29 309 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
dd4969a8
JG		 310 if (tmp & PHY_RST_HARD)
311 break;
20b09c29 312 MVS_CHIP_DISP->phy_reset(mvi, phy_id, 1);
dd4969a8 313 break;
b5762948 314
dd4969a8 315 case PHY_FUNC_LINK_RESET:
20b09c29
AY		 316 MVS_CHIP_DISP->phy_enable(mvi, phy_id);
317 MVS_CHIP_DISP->phy_reset(mvi, phy_id, 0);
dd4969a8 318 break;
b5762948 319
dd4969a8 320 case PHY_FUNC_DISABLE:
20b09c29
AY		 321 MVS_CHIP_DISP->phy_disable(mvi, phy_id);
322 break;
dd4969a8
JG		 323 case PHY_FUNC_RELEASE_SPINUP_HOLD:
324 default:
325 rc = -EOPNOTSUPP;
b5762948 326 }
20b09c29 327 msleep(200);
b5762948
JG		 328 return rc;
329}
330
20b09c29
AY		 331void __devinit mvs_set_sas_addr(struct mvs_info *mvi, int port_id,
332 u32 off_lo, u32 off_hi, u64 sas_addr)
333{
334 u32 lo = (u32)sas_addr;
335 u32 hi = (u32)(sas_addr>>32);
336
337 MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);
338 MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);
339 MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);
340 MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);
341}
342
dd4969a8 343static void mvs_bytes_dmaed(struct mvs_info *mvi, int i)
ee1f1c2e 344{
dd4969a8 345 struct mvs_phy *phy = &mvi->phy[i];
20b09c29
AY		 346 struct asd_sas_phy *sas_phy = &phy->sas_phy;
347 struct sas_ha_struct *sas_ha;
dd4969a8
JG		 348 if (!phy->phy_attached)
349 return;
350
20b09c29
AY		 351 if (!(phy->att_dev_info & PORT_DEV_TRGT_MASK)
352 && phy->phy_type & PORT_TYPE_SAS) {
353 return;
354 }
355
356 sas_ha = mvi->sas;
357 sas_ha->notify_phy_event(sas_phy, PHYE_OOB_DONE);
358
dd4969a8
JG		 359 if (sas_phy->phy) {
360 struct sas_phy *sphy = sas_phy->phy;
361
362 sphy->negotiated_linkrate = sas_phy->linkrate;
363 sphy->minimum_linkrate = phy->minimum_linkrate;
364 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
365 sphy->maximum_linkrate = phy->maximum_linkrate;
20b09c29 366 sphy->maximum_linkrate_hw = MVS_CHIP_DISP->phy_max_link_rate();
ee1f1c2e 367 }
ee1f1c2e 368
dd4969a8
JG		 369 if (phy->phy_type & PORT_TYPE_SAS) {
370 struct sas_identify_frame *id;
b5762948 371
dd4969a8
JG		 372 id = (struct sas_identify_frame *)phy->frame_rcvd;
373 id->dev_type = phy->identify.device_type;
374 id->initiator_bits = SAS_PROTOCOL_ALL;
375 id->target_bits = phy->identify.target_port_protocols;
376 } else if (phy->phy_type & PORT_TYPE_SATA) {
20b09c29 377 /*Nothing*/
dd4969a8 378 }
20b09c29
AY		 379 mv_dprintk("phy %d byte dmaded.\n", i + mvi->id * mvi->chip->n_phy);
380
381 sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
382
383 mvi->sas->notify_port_event(sas_phy,
dd4969a8 384 PORTE_BYTES_DMAED);
ee1f1c2e
KW		 385}
386
20b09c29
AY		 387int mvs_slave_alloc(struct scsi_device *scsi_dev)
388{
389 struct domain_device *dev = sdev_to_domain_dev(scsi_dev);
390 if (dev_is_sata(dev)) {
391 /* We don't need to rescan targets
392 * if REPORT_LUNS request is failed
393 */
394 if (scsi_dev->lun > 0)
395 return -ENXIO;
396 scsi_dev->tagged_supported = 1;
397 }
398
399 return sas_slave_alloc(scsi_dev);
400}
401
dd4969a8 402int mvs_slave_configure(struct scsi_device *sdev)
ee1f1c2e 403{
dd4969a8
JG		 404 struct domain_device *dev = sdev_to_domain_dev(sdev);
405 int ret = sas_slave_configure(sdev);
b5762948 406
dd4969a8
JG		 407 if (ret)
408 return ret;
dd4969a8 409 if (dev_is_sata(dev)) {
20b09c29
AY		 410 /* may set PIO mode */
411 #if MV_DISABLE_NCQ
412 struct ata_port *ap = dev->sata_dev.ap;
413 struct ata_device *adev = ap->link.device;
414 adev->flags |= ATA_DFLAG_NCQ_OFF;
dd4969a8 415 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, 1);
20b09c29 416 #endif
dd4969a8 417 }
ee1f1c2e 418 return 0;
b5762948
JG		 419}
420
dd4969a8 421void mvs_scan_start(struct Scsi_Host *shost)
b5762948 422{
20b09c29
AY		 423 int i, j;
424 unsigned short core_nr;
425 struct mvs_info *mvi;
426 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
427
428 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
dd4969a8 429
20b09c29
AY		 430 for (j = 0; j < core_nr; j++) {
431 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
432 for (i = 0; i < mvi->chip->n_phy; ++i)
433 mvs_bytes_dmaed(mvi, i);
dd4969a8 434 }
b5762948
JG		 435}
436
dd4969a8 437int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time)
b5762948 438{
dd4969a8
JG		 439 /* give the phy enabling interrupt event time to come in (1s
440 * is empirically about all it takes) */
441 if (time < HZ)
442 return 0;
443 /* Wait for discovery to finish */
444 scsi_flush_work(shost);
445 return 1;
b5762948
JG		 446}
447
dd4969a8
JG		 448static int mvs_task_prep_smp(struct mvs_info *mvi,
449 struct mvs_task_exec_info *tei)
b5762948 450{
dd4969a8
JG		 451 int elem, rc, i;
452 struct sas_task *task = tei->task;
453 struct mvs_cmd_hdr *hdr = tei->hdr;
20b09c29
AY		 454 struct domain_device *dev = task->dev;
455 struct asd_sas_port *sas_port = dev->port;
dd4969a8
JG		 456 struct scatterlist *sg_req, *sg_resp;
457 u32 req_len, resp_len, tag = tei->tag;
458 void *buf_tmp;
459 u8 *buf_oaf;
460 dma_addr_t buf_tmp_dma;
20b09c29 461 void *buf_prd;
dd4969a8 462 struct mvs_slot_info *slot = &mvi->slot_info[tag];
dd4969a8
JG		 463 u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
464#if _MV_DUMP
465 u8 *buf_cmd;
466 void *from;
467#endif
468 /*
469 * DMA-map SMP request, response buffers
470 */
471 sg_req = &task->smp_task.smp_req;
20b09c29 472 elem = dma_map_sg(mvi->dev, sg_req, 1, PCI_DMA_TODEVICE);
dd4969a8
JG		 473 if (!elem)
474 return -ENOMEM;
475 req_len = sg_dma_len(sg_req);
b5762948 476
dd4969a8 477 sg_resp = &task->smp_task.smp_resp;
20b09c29 478 elem = dma_map_sg(mvi->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
dd4969a8
JG		 479 if (!elem) {
480 rc = -ENOMEM;
481 goto err_out;
482 }
20b09c29 483 resp_len = SB_RFB_MAX;
b5762948 484
dd4969a8
JG		 485 /* must be in dwords */
486 if ((req_len & 0x3) || (resp_len & 0x3)) {
487 rc = -EINVAL;
488 goto err_out_2;
b5762948
JG		 489 }
490
dd4969a8
JG		 491 /*
492 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
493 */
b5762948 494
20b09c29 495 /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ***** */
dd4969a8
JG		 496 buf_tmp = slot->buf;
497 buf_tmp_dma = slot->buf_dma;
b5762948 498
dd4969a8
JG		 499#if _MV_DUMP
500 buf_cmd = buf_tmp;
501 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
502 buf_tmp += req_len;
503 buf_tmp_dma += req_len;
504 slot->cmd_size = req_len;
505#else
506 hdr->cmd_tbl = cpu_to_le64(sg_dma_address(sg_req));
507#endif
b5762948 508
dd4969a8
JG		 509 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
510 buf_oaf = buf_tmp;
511 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
b5762948 512
dd4969a8
JG		 513 buf_tmp += MVS_OAF_SZ;
514 buf_tmp_dma += MVS_OAF_SZ;
b5762948 515
20b09c29 516 /* region 3: PRD table *********************************** */
dd4969a8
JG		 517 buf_prd = buf_tmp;
518 if (tei->n_elem)
519 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
520 else
521 hdr->prd_tbl = 0;
b5762948 522
20b09c29 523 i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
dd4969a8
JG		 524 buf_tmp += i;
525 buf_tmp_dma += i;
b5762948 526
dd4969a8
JG		 527 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
528 slot->response = buf_tmp;
529 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
20b09c29
AY		 530 if (mvi->flags & MVF_FLAG_SOC)
531 hdr->reserved[0] = 0;
b5762948 532
dd4969a8
JG		 533 /*
534 * Fill in TX ring and command slot header
535 */
536 slot->tx = mvi->tx_prod;
537 mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
538 TXQ_MODE_I | tag |
539 (sas_port->phy_mask << TXQ_PHY_SHIFT));
b5762948 540
dd4969a8
JG		 541 hdr->flags |= flags;
542 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | ((req_len - 4) / 4));
543 hdr->tags = cpu_to_le32(tag);
544 hdr->data_len = 0;
b5762948 545
dd4969a8 546 /* generate open address frame hdr (first 12 bytes) */
20b09c29
AY		 547 /* initiator, SMP, ftype 1h */
548 buf_oaf[0] = (1 << 7) | (PROTOCOL_SMP << 4) | 0x01;
549 buf_oaf[1] = dev->linkrate & 0xf;
dd4969a8 550 *(u16 *)(buf_oaf + 2) = 0xFFFF; /* SAS SPEC */
20b09c29 551 memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
dd4969a8
JG		 552
553 /* fill in PRD (scatter/gather) table, if any */
20b09c29 554 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
b5762948 555
dd4969a8
JG		 556#if _MV_DUMP
557 /* copy cmd table */
558 from = kmap_atomic(sg_page(sg_req), KM_IRQ0);
559 memcpy(buf_cmd, from + sg_req->offset, req_len);
560 kunmap_atomic(from, KM_IRQ0);
561#endif
b5762948
JG		 562 return 0;
563
dd4969a8 564err_out_2:
20b09c29 565 dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_resp, 1,
dd4969a8 566 PCI_DMA_FROMDEVICE);
b5762948 567err_out:
20b09c29 568 dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_req, 1,
dd4969a8 569 PCI_DMA_TODEVICE);
8f261aaf 570 return rc;
8f261aaf
KW		 571}
572
dd4969a8 573static u32 mvs_get_ncq_tag(struct sas_task *task, u32 *tag)
8f261aaf 574{
dd4969a8 575 struct ata_queued_cmd *qc = task->uldd_task;
8f261aaf 576
dd4969a8
JG		 577 if (qc) {
578 if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
579 qc->tf.command == ATA_CMD_FPDMA_READ) {
580 *tag = qc->tag;
581 return 1;
582 }
8f261aaf 583 }
8f261aaf 584
dd4969a8 585 return 0;
8f261aaf
KW		 586}
587
dd4969a8
JG		 588static int mvs_task_prep_ata(struct mvs_info *mvi,
589 struct mvs_task_exec_info *tei)
b5762948
JG		 590{
591 struct sas_task *task = tei->task;
592 struct domain_device *dev = task->dev;
20b09c29
AY		 593 struct mvs_device *mvi_dev =
594 (struct mvs_device *)dev->lldd_dev;
b5762948
JG		 595 struct mvs_cmd_hdr *hdr = tei->hdr;
596 struct asd_sas_port *sas_port = dev->port;
8f261aaf 597 struct mvs_slot_info *slot;
20b09c29
AY		 598 void *buf_prd;
599 u32 tag = tei->tag, hdr_tag;
600 u32 flags, del_q;
b5762948
JG		 601 void *buf_tmp;
602 u8 *buf_cmd, *buf_oaf;
603 dma_addr_t buf_tmp_dma;
8f261aaf
KW		 604 u32 i, req_len, resp_len;
605 const u32 max_resp_len = SB_RFB_MAX;
606
20b09c29
AY		 607 if (mvs_assign_reg_set(mvi, mvi_dev) == MVS_ID_NOT_MAPPED) {
608 mv_dprintk("Have not enough regiset for dev %d.\n",
609 mvi_dev->device_id);
8f261aaf 610 return -EBUSY;
20b09c29 611 }
8f261aaf
KW		 612 slot = &mvi->slot_info[tag];
613 slot->tx = mvi->tx_prod;
20b09c29
AY		 614 del_q = TXQ_MODE_I | tag |
615 (TXQ_CMD_STP << TXQ_CMD_SHIFT) |
616 (sas_port->phy_mask << TXQ_PHY_SHIFT) |
617 (mvi_dev->taskfileset << TXQ_SRS_SHIFT);
618 mvi->tx[mvi->tx_prod] = cpu_to_le32(del_q);
619
620#ifndef DISABLE_HOTPLUG_DMA_FIX
621 if (task->data_dir == DMA_FROM_DEVICE)
622 flags = (MVS_CHIP_DISP->prd_count() << MCH_PRD_LEN_SHIFT);
623 else
624 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
625#else
626 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
627#endif
b5762948
JG		 628 if (task->ata_task.use_ncq)
629 flags |= MCH_FPDMA;
8f261aaf
KW		 630 if (dev->sata_dev.command_set == ATAPI_COMMAND_SET) {
631 if (task->ata_task.fis.command != ATA_CMD_ID_ATAPI)
632 flags |= MCH_ATAPI;
633 }
634
b5762948
JG		 635 /* FIXME: fill in port multiplier number */
636
637 hdr->flags = cpu_to_le32(flags);
8f261aaf
KW		 638
639 /* FIXME: the low order order 5 bits for the TAG if enable NCQ */
20b09c29
AY		 640 if (task->ata_task.use_ncq && mvs_get_ncq_tag(task, &hdr_tag))
641 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4e52fc0a 642 else
20b09c29
AY		 643 hdr_tag = tag;
644
645 hdr->tags = cpu_to_le32(hdr_tag);
646
b5762948
JG		 647 hdr->data_len = cpu_to_le32(task->total_xfer_len);
648
649 /*
650 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
651 */
b5762948 652
8f261aaf
KW		 653 /* region 1: command table area (MVS_ATA_CMD_SZ bytes) ************** */
654 buf_cmd = buf_tmp = slot->buf;
b5762948
JG		 655 buf_tmp_dma = slot->buf_dma;
656
657 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
658
659 buf_tmp += MVS_ATA_CMD_SZ;
660 buf_tmp_dma += MVS_ATA_CMD_SZ;
8f261aaf
KW		 661#if _MV_DUMP
662 slot->cmd_size = MVS_ATA_CMD_SZ;
663#endif
b5762948 664
8f261aaf 665 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
b5762948
JG		 666 /* used for STP. unused for SATA? */
667 buf_oaf = buf_tmp;
668 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
669
670 buf_tmp += MVS_OAF_SZ;
671 buf_tmp_dma += MVS_OAF_SZ;
672
8f261aaf 673 /* region 3: PRD table ********************************************* */
b5762948 674 buf_prd = buf_tmp;
20b09c29 675
8f261aaf
KW		 676 if (tei->n_elem)
677 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
678 else
679 hdr->prd_tbl = 0;
20b09c29 680 i = MVS_CHIP_DISP->prd_size() * MVS_CHIP_DISP->prd_count();
b5762948 681
b5762948
JG		 682 buf_tmp += i;
683 buf_tmp_dma += i;
684
8f261aaf 685 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
b5762948
JG		 686 /* FIXME: probably unused, for SATA. kept here just in case
687 * we get a STP/SATA error information record
688 */
689 slot->response = buf_tmp;
690 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
20b09c29
AY		 691 if (mvi->flags & MVF_FLAG_SOC)
692 hdr->reserved[0] = 0;
b5762948 693
8f261aaf 694 req_len = sizeof(struct host_to_dev_fis);
b5762948 695 resp_len = MVS_SLOT_BUF_SZ - MVS_ATA_CMD_SZ -
8f261aaf 696 sizeof(struct mvs_err_info) - i;
b5762948
JG		 697
698 /* request, response lengths */
8f261aaf 699 resp_len = min(resp_len, max_resp_len);
b5762948
JG		 700 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
701
20b09c29
AY		 702 if (likely(!task->ata_task.device_control_reg_update))
703 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
b5762948 704 /* fill in command FIS and ATAPI CDB */
8f261aaf
KW		 705 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
706 if (dev->sata_dev.command_set == ATAPI_COMMAND_SET)
707 memcpy(buf_cmd + STP_ATAPI_CMD,
708 task->ata_task.atapi_packet, 16);
709
710 /* generate open address frame hdr (first 12 bytes) */
20b09c29
AY		 711 /* initiator, STP, ftype 1h */
712 buf_oaf[0] = (1 << 7) | (PROTOCOL_STP << 4) | 0x1;
713 buf_oaf[1] = dev->linkrate & 0xf;
714 *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
715 memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
b5762948
JG		 716
717 /* fill in PRD (scatter/gather) table, if any */
20b09c29
AY		 718 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
719#ifndef DISABLE_HOTPLUG_DMA_FIX
720 if (task->data_dir == DMA_FROM_DEVICE)
721 MVS_CHIP_DISP->dma_fix(mvi->bulk_buffer_dma,
722 TRASH_BUCKET_SIZE, tei->n_elem, buf_prd);
723#endif
b5762948
JG		 724 return 0;
725}
726
727static int mvs_task_prep_ssp(struct mvs_info *mvi,
20b09c29
AY		 728 struct mvs_task_exec_info *tei, int is_tmf,
729 struct mvs_tmf_task *tmf)
b5762948
JG		 730{
731 struct sas_task *task = tei->task;
b5762948 732 struct mvs_cmd_hdr *hdr = tei->hdr;
8f261aaf 733 struct mvs_port *port = tei->port;
20b09c29
AY		 734 struct domain_device *dev = task->dev;
735 struct mvs_device *mvi_dev =
736 (struct mvs_device *)dev->lldd_dev;
737 struct asd_sas_port *sas_port = dev->port;
b5762948 738 struct mvs_slot_info *slot;
20b09c29 739 void *buf_prd;
b5762948
JG		 740 struct ssp_frame_hdr *ssp_hdr;
741 void *buf_tmp;
742 u8 *buf_cmd, *buf_oaf, fburst = 0;
743 dma_addr_t buf_tmp_dma;
744 u32 flags;
8f261aaf
KW		 745 u32 resp_len, req_len, i, tag = tei->tag;
746 const u32 max_resp_len = SB_RFB_MAX;
20b09c29 747 u32 phy_mask;
b5762948
JG		 748
749 slot = &mvi->slot_info[tag];
750
20b09c29
AY		 751 phy_mask = ((port->wide_port_phymap) ? port->wide_port_phymap :
752 sas_port->phy_mask) & TXQ_PHY_MASK;
753
8f261aaf
KW		 754 slot->tx = mvi->tx_prod;
755 mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
756 (TXQ_CMD_SSP << TXQ_CMD_SHIFT) |
4e52fc0a 757 (phy_mask << TXQ_PHY_SHIFT));
b5762948
JG		 758
759 flags = MCH_RETRY;
760 if (task->ssp_task.enable_first_burst) {
761 flags |= MCH_FBURST;
762 fburst = (1 << 7);
763 }
2b288133
AY		 764 if (is_tmf)
765 flags |= (MCH_SSP_FR_TASK << MCH_SSP_FR_TYPE_SHIFT);
766 else
767 flags |= (MCH_SSP_FR_CMD << MCH_SSP_FR_TYPE_SHIFT);
768 hdr->flags = cpu_to_le32(flags | (tei->n_elem << MCH_PRD_LEN_SHIFT));
b5762948
JG		 769 hdr->tags = cpu_to_le32(tag);
770 hdr->data_len = cpu_to_le32(task->total_xfer_len);
771
772 /*
773 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
774 */
b5762948 775
8f261aaf
KW		 776 /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
777 buf_cmd = buf_tmp = slot->buf;
b5762948
JG		 778 buf_tmp_dma = slot->buf_dma;
779
780 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
781
782 buf_tmp += MVS_SSP_CMD_SZ;
783 buf_tmp_dma += MVS_SSP_CMD_SZ;
8f261aaf
KW		 784#if _MV_DUMP
785 slot->cmd_size = MVS_SSP_CMD_SZ;
786#endif
b5762948 787
8f261aaf 788 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
b5762948
JG		 789 buf_oaf = buf_tmp;
790 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
791
792 buf_tmp += MVS_OAF_SZ;
793 buf_tmp_dma += MVS_OAF_SZ;
794
8f261aaf 795 /* region 3: PRD table ********************************************* */
b5762948 796 buf_prd = buf_tmp;
8f261aaf
KW		 797 if (tei->n_elem)
798 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
799 else
800 hdr->prd_tbl = 0;
b5762948 801
20b09c29 802 i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
b5762948
JG		 803 buf_tmp += i;
804 buf_tmp_dma += i;
805
8f261aaf 806 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
b5762948
JG		 807 slot->response = buf_tmp;
808 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
20b09c29
AY		 809 if (mvi->flags & MVF_FLAG_SOC)
810 hdr->reserved[0] = 0;
b5762948 811
b5762948 812 resp_len = MVS_SLOT_BUF_SZ - MVS_SSP_CMD_SZ - MVS_OAF_SZ -
8f261aaf
KW		 813 sizeof(struct mvs_err_info) - i;
814 resp_len = min(resp_len, max_resp_len);
815
816 req_len = sizeof(struct ssp_frame_hdr) + 28;
b5762948
JG		 817
818 /* request, response lengths */
819 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
820
821 /* generate open address frame hdr (first 12 bytes) */
20b09c29
AY		 822 /* initiator, SSP, ftype 1h */
823 buf_oaf[0] = (1 << 7) | (PROTOCOL_SSP << 4) | 0x1;
824 buf_oaf[1] = dev->linkrate & 0xf;
825 *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
826 memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
b5762948 827
8f261aaf
KW		 828 /* fill in SSP frame header (Command Table.SSP frame header) */
829 ssp_hdr = (struct ssp_frame_hdr *)buf_cmd;
20b09c29
AY		 830
831 if (is_tmf)
832 ssp_hdr->frame_type = SSP_TASK;
833 else
834 ssp_hdr->frame_type = SSP_COMMAND;
835
836 memcpy(ssp_hdr->hashed_dest_addr, dev->hashed_sas_addr,
b5762948
JG		 837 HASHED_SAS_ADDR_SIZE);
838 memcpy(ssp_hdr->hashed_src_addr,
20b09c29 839 dev->hashed_sas_addr, HASHED_SAS_ADDR_SIZE);
b5762948
JG		 840 ssp_hdr->tag = cpu_to_be16(tag);
841
20b09c29 842 /* fill in IU for TASK and Command Frame */
b5762948
JG		 843 buf_cmd += sizeof(*ssp_hdr);
844 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
b5762948 845
20b09c29
AY		 846 if (ssp_hdr->frame_type != SSP_TASK) {
847 buf_cmd[9] = fburst | task->ssp_task.task_attr |
848 (task->ssp_task.task_prio << 3);
849 memcpy(buf_cmd + 12, &task->ssp_task.cdb, 16);
850 } else{
851 buf_cmd[10] = tmf->tmf;
852 switch (tmf->tmf) {
853 case TMF_ABORT_TASK:
854 case TMF_QUERY_TASK:
855 buf_cmd[12] =
856 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
857 buf_cmd[13] =
858 tmf->tag_of_task_to_be_managed & 0xff;
859 break;
860 default:
861 break;
862 }
b5762948 863 }
20b09c29
AY		 864 /* fill in PRD (scatter/gather) table, if any */
865 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
b5762948
JG		 866 return 0;
867}
868
20b09c29
AY		 869#define DEV_IS_GONE(mvi_dev) ((!mvi_dev || (mvi_dev->dev_type == NO_DEVICE)))
870static int mvs_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags,
871 struct completion *completion, int lock,
872 int is_tmf, struct mvs_tmf_task *tmf)
b5762948 873{
8f261aaf 874 struct domain_device *dev = task->dev;
20b09c29
AY		 875 struct mvs_info *mvi;
876 struct mvs_device *mvi_dev;
b5762948 877 struct mvs_task_exec_info tei;
8f261aaf 878 struct sas_task *t = task;
4e52fc0a 879 struct mvs_slot_info *slot;
8f261aaf 880 u32 tag = 0xdeadbeef, rc, n_elem = 0;
8f261aaf 881 u32 n = num, pass = 0;
20b09c29 882 unsigned long flags = 0;
b5762948 883
20b09c29
AY		 884 if (!dev->port) {
885 struct task_status_struct *tsm = &t->task_status;
886
887 tsm->resp = SAS_TASK_UNDELIVERED;
888 tsm->stat = SAS_PHY_DOWN;
889 t->task_done(t);
890 return 0;
891 }
892
893 mvi = mvs_find_dev_mvi(task->dev);
894
895 if (lock)
896 spin_lock_irqsave(&mvi->lock, flags);
8f261aaf 897 do {
4e52fc0a 898 dev = t->dev;
20b09c29
AY		 899 mvi_dev = (struct mvs_device *)dev->lldd_dev;
900 if (DEV_IS_GONE(mvi_dev)) {
901 if (mvi_dev)
902 mv_dprintk("device %d not ready.\n",
903 mvi_dev->device_id);
904 else
905 mv_dprintk("device %016llx not ready.\n",
906 SAS_ADDR(dev->sas_addr));
907
908 rc = SAS_PHY_DOWN;
909 goto out_done;
910 }
911
912 if (dev->port->id >= mvi->chip->n_phy)
913 tei.port = &mvi->port[dev->port->id - mvi->chip->n_phy];
914 else
915 tei.port = &mvi->port[dev->port->id];
b5762948 916
dd4969a8
JG		 917 if (!tei.port->port_attached) {
918 if (sas_protocol_ata(t->task_proto)) {
20b09c29
AY		 919 mv_dprintk("port %d does not"
920 "attached device.\n", dev->port->id);
dd4969a8
JG		 921 rc = SAS_PHY_DOWN;
922 goto out_done;
923 } else {
924 struct task_status_struct *ts = &t->task_status;
925 ts->resp = SAS_TASK_UNDELIVERED;
926 ts->stat = SAS_PHY_DOWN;
927 t->task_done(t);
928 if (n > 1)
929 t = list_entry(t->list.next,
930 struct sas_task, list);
931 continue;
932 }
933 }
934
935 if (!sas_protocol_ata(t->task_proto)) {
936 if (t->num_scatter) {
20b09c29
AY		 937 n_elem = dma_map_sg(mvi->dev,
938 t->scatter,
dd4969a8
JG		 939 t->num_scatter,
940 t->data_dir);
941 if (!n_elem) {
942 rc = -ENOMEM;
943 goto err_out;
944 }
945 }
946 } else {
947 n_elem = t->num_scatter;
948 }
949
950 rc = mvs_tag_alloc(mvi, &tag);
951 if (rc)
952 goto err_out;
953
954 slot = &mvi->slot_info[tag];
20b09c29
AY		 955
956
dd4969a8
JG		 957 t->lldd_task = NULL;
958 slot->n_elem = n_elem;
20b09c29 959 slot->slot_tag = tag;
dd4969a8 960 memset(slot->buf, 0, MVS_SLOT_BUF_SZ);
20b09c29 961
dd4969a8
JG		 962 tei.task = t;
963 tei.hdr = &mvi->slot[tag];
964 tei.tag = tag;
965 tei.n_elem = n_elem;
dd4969a8
JG		 966 switch (t->task_proto) {
967 case SAS_PROTOCOL_SMP:
968 rc = mvs_task_prep_smp(mvi, &tei);
969 break;
970 case SAS_PROTOCOL_SSP:
20b09c29 971 rc = mvs_task_prep_ssp(mvi, &tei, is_tmf, tmf);
dd4969a8
JG		 972 break;
973 case SAS_PROTOCOL_SATA:
974 case SAS_PROTOCOL_STP:
975 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
976 rc = mvs_task_prep_ata(mvi, &tei);
977 break;
978 default:
20b09c29 979 dev_printk(KERN_ERR, mvi->dev,
dd4969a8
JG		 980 "unknown sas_task proto: 0x%x\n",
981 t->task_proto);
982 rc = -EINVAL;
983 break;
984 }
985
20b09c29
AY		 986 if (rc) {
987 mv_dprintk("rc is %x\n", rc);
dd4969a8 988 goto err_out_tag;
20b09c29 989 }
dd4969a8
JG		 990 slot->task = t;
991 slot->port = tei.port;
992 t->lldd_task = (void *) slot;
20b09c29 993 list_add_tail(&slot->entry, &tei.port->list);
dd4969a8 994 /* TODO: select normal or high priority */
dd4969a8
JG		 995 spin_lock(&t->task_state_lock);
996 t->task_state_flags |= SAS_TASK_AT_INITIATOR;
997 spin_unlock(&t->task_state_lock);
998
999 mvs_hba_memory_dump(mvi, tag, t->task_proto);
20b09c29 1000 mvi_dev->runing_req++;
dd4969a8
JG		 1001 ++pass;
1002 mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
1003 if (n > 1)
1004 t = list_entry(t->list.next, struct sas_task, list);
1005 } while (--n);
dd4969a8
JG		 1006 rc = 0;
1007 goto out_done;
1008
1009err_out_tag:
1010 mvs_tag_free(mvi, tag);
1011err_out:
20b09c29
AY		 1012
1013 dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
dd4969a8
JG		 1014 if (!sas_protocol_ata(t->task_proto))
1015 if (n_elem)
20b09c29 1016 dma_unmap_sg(mvi->dev, t->scatter, n_elem,
dd4969a8
JG		 1017 t->data_dir);
1018out_done:
20b09c29
AY		 1019 if (likely(pass)) {
1020 MVS_CHIP_DISP->start_delivery(mvi,
1021 (mvi->tx_prod - 1) & (MVS_CHIP_SLOT_SZ - 1));
1022 }
1023 if (lock)
1024 spin_unlock_irqrestore(&mvi->lock, flags);
dd4969a8
JG		 1025 return rc;
1026}
1027
20b09c29
AY		 1028int mvs_queue_command(struct sas_task *task, const int num,
1029 gfp_t gfp_flags)
1030{
1031 return mvs_task_exec(task, num, gfp_flags, NULL, 1, 0, NULL);
1032}
1033
dd4969a8
JG		 1034static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)
1035{
1036 u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
1037 mvs_tag_clear(mvi, slot_idx);
1038}
1039
1040static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task,
1041 struct mvs_slot_info *slot, u32 slot_idx)
1042{
20b09c29
AY		 1043 if (!slot->task)
1044 return;
dd4969a8
JG		 1045 if (!sas_protocol_ata(task->task_proto))
1046 if (slot->n_elem)
20b09c29 1047 dma_unmap_sg(mvi->dev, task->scatter,
dd4969a8
JG		 1048 slot->n_elem, task->data_dir);
1049
1050 switch (task->task_proto) {
1051 case SAS_PROTOCOL_SMP:
20b09c29 1052 dma_unmap_sg(mvi->dev, &task->smp_task.smp_resp, 1,
dd4969a8 1053 PCI_DMA_FROMDEVICE);
20b09c29 1054 dma_unmap_sg(mvi->dev, &task->smp_task.smp_req, 1,
dd4969a8
JG		 1055 PCI_DMA_TODEVICE);
1056 break;
1057
1058 case SAS_PROTOCOL_SATA:
1059 case SAS_PROTOCOL_STP:
1060 case SAS_PROTOCOL_SSP:
1061 default:
1062 /* do nothing */
1063 break;
1064 }
20b09c29 1065 list_del_init(&slot->entry);
dd4969a8
JG		 1066 task->lldd_task = NULL;
1067 slot->task = NULL;
1068 slot->port = NULL;
20b09c29
AY		 1069 slot->slot_tag = 0xFFFFFFFF;
1070 mvs_slot_free(mvi, slot_idx);
dd4969a8
JG		 1071}
1072
1073static void mvs_update_wideport(struct mvs_info *mvi, int i)
1074{
1075 struct mvs_phy *phy = &mvi->phy[i];
1076 struct mvs_port *port = phy->port;
1077 int j, no;
1078
20b09c29
AY		 1079 for_each_phy(port->wide_port_phymap, j, no) {
1080 if (j & 1) {
1081 MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
1082 PHYR_WIDE_PORT);
1083 MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
dd4969a8
JG		 1084 port->wide_port_phymap);
1085 } else {
20b09c29
AY		 1086 MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
1087 PHYR_WIDE_PORT);
1088 MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
1089 0);
dd4969a8 1090 }
20b09c29 1091 }
dd4969a8
JG		 1092}
1093
1094static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
1095{
1096 u32 tmp;
1097 struct mvs_phy *phy = &mvi->phy[i];
20b09c29 1098 struct mvs_port *port = phy->port;
dd4969a8 1099
20b09c29 1100 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);
dd4969a8
JG		 1101 if ((tmp & PHY_READY_MASK) && !(phy->irq_status & PHYEV_POOF)) {
1102 if (!port)
1103 phy->phy_attached = 1;
1104 return tmp;
1105 }
1106
1107 if (port) {
1108 if (phy->phy_type & PORT_TYPE_SAS) {
1109 port->wide_port_phymap &= ~(1U << i);
1110 if (!port->wide_port_phymap)
1111 port->port_attached = 0;
1112 mvs_update_wideport(mvi, i);
1113 } else if (phy->phy_type & PORT_TYPE_SATA)
1114 port->port_attached = 0;
dd4969a8
JG		 1115 phy->port = NULL;
1116 phy->phy_attached = 0;
1117 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1118 }
1119 return 0;
1120}
1121
1122static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
1123{
1124 u32 *s = (u32 *) buf;
1125
1126 if (!s)
1127 return NULL;
1128
20b09c29
AY		 1129 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
1130 s[3] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
dd4969a8 1131
20b09c29
AY		 1132 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
1133 s[2] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
dd4969a8 1134
20b09c29
AY		 1135 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
1136 s[1] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
dd4969a8 1137
20b09c29
AY		 1138 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
1139 s[0] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
1140
1141 /* Workaround: take some ATAPI devices for ATA */
1142 if (((s[1] & 0x00FFFFFF) == 0x00EB1401) && (*(u8 *)&s[3] == 0x01))
1143 s[1] = 0x00EB1401 | (*((u8 *)&s[1] + 3) & 0x10);
dd4969a8
JG		 1144
1145 return (void *)s;
1146}
1147
1148static u32 mvs_is_sig_fis_received(u32 irq_status)
1149{
1150 return irq_status & PHYEV_SIG_FIS;
1151}
1152
20b09c29 1153void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st)
dd4969a8
JG		 1154{
1155 struct mvs_phy *phy = &mvi->phy[i];
20b09c29 1156 struct sas_identify_frame *id;
b5762948 1157
20b09c29 1158 id = (struct sas_identify_frame *)phy->frame_rcvd;
b5762948 1159
dd4969a8 1160 if (get_st) {
20b09c29 1161 phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);
dd4969a8
JG		 1162 phy->phy_status = mvs_is_phy_ready(mvi, i);
1163 }
8f261aaf 1164
dd4969a8 1165 if (phy->phy_status) {
20b09c29
AY		 1166 int oob_done = 0;
1167 struct asd_sas_phy *sas_phy = &mvi->phy[i].sas_phy;
b5762948 1168
20b09c29
AY		 1169 oob_done = MVS_CHIP_DISP->oob_done(mvi, i);
1170
1171 MVS_CHIP_DISP->fix_phy_info(mvi, i, id);
1172 if (phy->phy_type & PORT_TYPE_SATA) {
1173 phy->identify.target_port_protocols = SAS_PROTOCOL_STP;
1174 if (mvs_is_sig_fis_received(phy->irq_status)) {
1175 phy->phy_attached = 1;
1176 phy->att_dev_sas_addr =
1177 i + mvi->id * mvi->chip->n_phy;
1178 if (oob_done)
1179 sas_phy->oob_mode = SATA_OOB_MODE;
1180 phy->frame_rcvd_size =
1181 sizeof(struct dev_to_host_fis);
1182 mvs_get_d2h_reg(mvi, i, (void *)id);
1183 } else {
1184 u32 tmp;
1185 dev_printk(KERN_DEBUG, mvi->dev,
1186 "Phy%d : No sig fis\n", i);
1187 tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);
1188 MVS_CHIP_DISP->write_port_irq_mask(mvi, i,
1189 tmp | PHYEV_SIG_FIS);
1190 phy->phy_attached = 0;
1191 phy->phy_type &= ~PORT_TYPE_SATA;
1192 MVS_CHIP_DISP->phy_reset(mvi, i, 0);
1193 goto out_done;
1194 }
1195 } else if (phy->phy_type & PORT_TYPE_SAS
1196 || phy->att_dev_info & PORT_SSP_INIT_MASK) {
1197 phy->phy_attached = 1;
dd4969a8 1198 phy->identify.device_type =
20b09c29 1199 phy->att_dev_info & PORT_DEV_TYPE_MASK;
b5762948 1200
dd4969a8
JG		 1201 if (phy->identify.device_type == SAS_END_DEV)
1202 phy->identify.target_port_protocols =
1203 SAS_PROTOCOL_SSP;
1204 else if (phy->identify.device_type != NO_DEVICE)
1205 phy->identify.target_port_protocols =
1206 SAS_PROTOCOL_SMP;
20b09c29 1207 if (oob_done)
dd4969a8
JG		 1208 sas_phy->oob_mode = SAS_OOB_MODE;
1209 phy->frame_rcvd_size =
1210 sizeof(struct sas_identify_frame);
dd4969a8 1211 }
20b09c29
AY		 1212 memcpy(sas_phy->attached_sas_addr,
1213 &phy->att_dev_sas_addr, SAS_ADDR_SIZE);
b5762948 1214
20b09c29
AY		 1215 if (MVS_CHIP_DISP->phy_work_around)
1216 MVS_CHIP_DISP->phy_work_around(mvi, i);
dd4969a8 1217 }
20b09c29
AY		 1218 mv_dprintk("port %d attach dev info is %x\n",
1219 i + mvi->id * mvi->chip->n_phy, phy->att_dev_info);
1220 mv_dprintk("port %d attach sas addr is %llx\n",
1221 i + mvi->id * mvi->chip->n_phy, phy->att_dev_sas_addr);
4e52fc0a 1222out_done:
dd4969a8 1223 if (get_st)
20b09c29 1224 MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);
b5762948
JG		 1225}
1226
20b09c29 1227static void mvs_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
8f261aaf 1228{
dd4969a8 1229 struct sas_ha_struct *sas_ha = sas_phy->ha;
20b09c29 1230 struct mvs_info *mvi = NULL; int i = 0, hi;
dd4969a8 1231 struct mvs_phy *phy = sas_phy->lldd_phy;
20b09c29
AY		 1232 struct asd_sas_port *sas_port = sas_phy->port;
1233 struct mvs_port *port;
1234 unsigned long flags = 0;
1235 if (!sas_port)
1236 return;
8f261aaf 1237
20b09c29
AY		 1238 while (sas_ha->sas_phy[i]) {
1239 if (sas_ha->sas_phy[i] == sas_phy)
1240 break;
1241 i++;
1242 }
1243 hi = i/((struct mvs_prv_info *)sas_ha->lldd_ha)->n_phy;
1244 mvi = ((struct mvs_prv_info *)sas_ha->lldd_ha)->mvi[hi];
1245 if (sas_port->id >= mvi->chip->n_phy)
1246 port = &mvi->port[sas_port->id - mvi->chip->n_phy];
1247 else
1248 port = &mvi->port[sas_port->id];
1249 if (lock)
1250 spin_lock_irqsave(&mvi->lock, flags);
dd4969a8
JG		 1251 port->port_attached = 1;
1252 phy->port = port;
dd4969a8
JG		 1253 if (phy->phy_type & PORT_TYPE_SAS) {
1254 port->wide_port_phymap = sas_port->phy_mask;
20b09c29 1255 mv_printk("set wide port phy map %x\n", sas_port->phy_mask);
dd4969a8 1256 mvs_update_wideport(mvi, sas_phy->id);
8f261aaf 1257 }
20b09c29
AY		 1258 if (lock)
1259 spin_unlock_irqrestore(&mvi->lock, flags);
dd4969a8
JG		 1260}
1261
20b09c29 1262static void mvs_port_notify_deformed(struct asd_sas_phy *sas_phy, int lock)
dd4969a8 1263{
20b09c29 1264 /*Nothing*/
dd4969a8
JG		 1265}
1266
dd4969a8 1267
20b09c29
AY		 1268void mvs_port_formed(struct asd_sas_phy *sas_phy)
1269{
1270 mvs_port_notify_formed(sas_phy, 1);
dd4969a8
JG		 1271}
1272
20b09c29 1273void mvs_port_deformed(struct asd_sas_phy *sas_phy)
dd4969a8 1274{
20b09c29
AY		 1275 mvs_port_notify_deformed(sas_phy, 1);
1276}
8f261aaf 1277
20b09c29
AY		 1278struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
1279{
1280 u32 dev;
1281 for (dev = 0; dev < MVS_MAX_DEVICES; dev++) {
1282 if (mvi->devices[dev].dev_type == NO_DEVICE) {
1283 mvi->devices[dev].device_id = dev;
1284 return &mvi->devices[dev];
1285 }
8f261aaf 1286 }
8121ed42 1287
20b09c29
AY		 1288 if (dev == MVS_MAX_DEVICES)
1289 mv_printk("max support %d devices, ignore ..\n",
1290 MVS_MAX_DEVICES);
1291
1292 return NULL;
8f261aaf
KW		 1293}
1294
20b09c29 1295void mvs_free_dev(struct mvs_device *mvi_dev)
b5762948 1296{
20b09c29
AY		 1297 u32 id = mvi_dev->device_id;
1298 memset(mvi_dev, 0, sizeof(*mvi_dev));
1299 mvi_dev->device_id = id;
1300 mvi_dev->dev_type = NO_DEVICE;
1301 mvi_dev->dev_status = MVS_DEV_NORMAL;
1302 mvi_dev->taskfileset = MVS_ID_NOT_MAPPED;
1303}
b5762948 1304
20b09c29
AY		 1305int mvs_dev_found_notify(struct domain_device *dev, int lock)
1306{
1307 unsigned long flags = 0;
1308 int res = 0;
1309 struct mvs_info *mvi = NULL;
1310 struct domain_device *parent_dev = dev->parent;
1311 struct mvs_device *mvi_device;
b5762948 1312
20b09c29 1313 mvi = mvs_find_dev_mvi(dev);
b5762948 1314
20b09c29
AY		 1315 if (lock)
1316 spin_lock_irqsave(&mvi->lock, flags);
1317
1318 mvi_device = mvs_alloc_dev(mvi);
1319 if (!mvi_device) {
1320 res = -1;
1321 goto found_out;
b5762948 1322 }
20b09c29
AY		 1323 dev->lldd_dev = (void *)mvi_device;
1324 mvi_device->dev_type = dev->dev_type;
1325
1326 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) {
1327 int phy_id;
1328 u8 phy_num = parent_dev->ex_dev.num_phys;
1329 struct ex_phy *phy;
1330 for (phy_id = 0; phy_id < phy_num; phy_id++) {
1331 phy = &parent_dev->ex_dev.ex_phy[phy_id];
1332 if (SAS_ADDR(phy->attached_sas_addr) ==
1333 SAS_ADDR(dev->sas_addr)) {
1334 mvi_device->attached_phy = phy_id;
1335 break;
1336 }
1337 }
b5762948 1338
20b09c29
AY		 1339 if (phy_id == phy_num) {
1340 mv_printk("Error: no attached dev:%016llx"
1341 "at ex:%016llx.\n",
1342 SAS_ADDR(dev->sas_addr),
1343 SAS_ADDR(parent_dev->sas_addr));
1344 res = -1;
1345 }
dd4969a8 1346 }
b5762948 1347
20b09c29
AY		 1348found_out:
1349 if (lock)
1350 spin_unlock_irqrestore(&mvi->lock, flags);
1351 return res;
1352}
b5762948 1353
20b09c29
AY		 1354int mvs_dev_found(struct domain_device *dev)
1355{
1356 return mvs_dev_found_notify(dev, 1);
1357}
b5762948 1358
20b09c29
AY		 1359void mvs_dev_gone_notify(struct domain_device *dev, int lock)
1360{
1361 unsigned long flags = 0;
1362 struct mvs_info *mvi;
1363 struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
dd4969a8 1364
20b09c29 1365 mvi = mvs_find_dev_mvi(dev);
b5762948 1366
20b09c29
AY		 1367 if (lock)
1368 spin_lock_irqsave(&mvi->lock, flags);
b5762948 1369
20b09c29
AY		 1370 if (mvi_dev) {
1371 mv_dprintk("found dev[%d:%x] is gone.\n",
1372 mvi_dev->device_id, mvi_dev->dev_type);
1373 mvs_free_reg_set(mvi, mvi_dev);
1374 mvs_free_dev(mvi_dev);
1375 } else {
1376 mv_dprintk("found dev has gone.\n");
b5762948 1377 }
20b09c29 1378 dev->lldd_dev = NULL;
b5762948 1379
20b09c29
AY		 1380 if (lock)
1381 spin_unlock_irqrestore(&mvi->lock, flags);
b5762948
JG		 1382}
1383
b5762948 1384
20b09c29
AY		 1385void mvs_dev_gone(struct domain_device *dev)
1386{
1387 mvs_dev_gone_notify(dev, 1);
1388}
b5762948 1389
20b09c29
AY		 1390static struct sas_task *mvs_alloc_task(void)
1391{
1392 struct sas_task *task = kzalloc(sizeof(struct sas_task), GFP_KERNEL);
1393
1394 if (task) {
1395 INIT_LIST_HEAD(&task->list);
1396 spin_lock_init(&task->task_state_lock);
1397 task->task_state_flags = SAS_TASK_STATE_PENDING;
1398 init_timer(&task->timer);
1399 init_completion(&task->completion);
b5762948 1400 }
20b09c29 1401 return task;
dd4969a8 1402}
b5762948 1403
20b09c29 1404static void mvs_free_task(struct sas_task *task)
dd4969a8 1405{
20b09c29
AY		 1406 if (task) {
1407 BUG_ON(!list_empty(&task->list));
1408 kfree(task);
b5762948 1409 }
20b09c29 1410}
b5762948 1411
20b09c29
AY		 1412static void mvs_task_done(struct sas_task *task)
1413{
1414 if (!del_timer(&task->timer))
1415 return;
1416 complete(&task->completion);
b5762948 1417}
b5762948 1418
20b09c29 1419static void mvs_tmf_timedout(unsigned long data)
b5762948 1420{
20b09c29 1421 struct sas_task *task = (struct sas_task *)data;
8f261aaf 1422
20b09c29
AY		 1423 task->task_state_flags |= SAS_TASK_STATE_ABORTED;
1424 complete(&task->completion);
1425}
8f261aaf 1426
20b09c29
AY		 1427/* XXX */
1428#define MVS_TASK_TIMEOUT 20
1429static int mvs_exec_internal_tmf_task(struct domain_device *dev,
1430 void *parameter, u32 para_len, struct mvs_tmf_task *tmf)
1431{
1432 int res, retry;
1433 struct sas_task *task = NULL;
8f261aaf 1434
20b09c29
AY		 1435 for (retry = 0; retry < 3; retry++) {
1436 task = mvs_alloc_task();
1437 if (!task)
1438 return -ENOMEM;
8f261aaf 1439
20b09c29
AY		 1440 task->dev = dev;
1441 task->task_proto = dev->tproto;
8f261aaf 1442
20b09c29
AY		 1443 memcpy(&task->ssp_task, parameter, para_len);
1444 task->task_done = mvs_task_done;
8f261aaf 1445
20b09c29
AY		 1446 task->timer.data = (unsigned long) task;
1447 task->timer.function = mvs_tmf_timedout;
1448 task->timer.expires = jiffies + MVS_TASK_TIMEOUT*HZ;
1449 add_timer(&task->timer);
8f261aaf 1450
20b09c29 1451 res = mvs_task_exec(task, 1, GFP_KERNEL, NULL, 0, 1, tmf);
8f261aaf 1452
20b09c29
AY		 1453 if (res) {
1454 del_timer(&task->timer);
1455 mv_printk("executing internel task failed:%d\n", res);
1456 goto ex_err;
1457 }
8f261aaf 1458
20b09c29
AY		 1459 wait_for_completion(&task->completion);
1460 res = -TMF_RESP_FUNC_FAILED;
1461 /* Even TMF timed out, return direct. */
1462 if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
1463 if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
1464 mv_printk("TMF task[%x] timeout.\n", tmf->tmf);
1465 goto ex_err;
1466 }
1467 }
8f261aaf 1468
20b09c29
AY		 1469 if (task->task_status.resp == SAS_TASK_COMPLETE &&
1470 task->task_status.stat == SAM_GOOD) {
1471 res = TMF_RESP_FUNC_COMPLETE;
1472 break;
1473 }
b5762948 1474
20b09c29
AY		 1475 if (task->task_status.resp == SAS_TASK_COMPLETE &&
1476 task->task_status.stat == SAS_DATA_UNDERRUN) {
1477 /* no error, but return the number of bytes of
1478 * underrun */
1479 res = task->task_status.residual;
1480 break;
1481 }
b5762948 1482
20b09c29
AY		 1483 if (task->task_status.resp == SAS_TASK_COMPLETE &&
1484 task->task_status.stat == SAS_DATA_OVERRUN) {
1485 mv_dprintk("blocked task error.\n");
1486 res = -EMSGSIZE;
1487 break;
1488 } else {
1489 mv_dprintk(" task to dev %016llx response: 0x%x "
1490 "status 0x%x\n",
1491 SAS_ADDR(dev->sas_addr),
1492 task->task_status.resp,
1493 task->task_status.stat);
1494 mvs_free_task(task);
1495 task = NULL;
b5762948 1496
dd4969a8 1497 }
dd4969a8 1498 }
20b09c29
AY		 1499ex_err:
1500 BUG_ON(retry == 3 && task != NULL);
1501 if (task != NULL)
1502 mvs_free_task(task);
1503 return res;
dd4969a8 1504}
b5762948 1505
20b09c29
AY		 1506static int mvs_debug_issue_ssp_tmf(struct domain_device *dev,
1507 u8 *lun, struct mvs_tmf_task *tmf)
dd4969a8 1508{
20b09c29
AY		 1509 struct sas_ssp_task ssp_task;
1510 DECLARE_COMPLETION_ONSTACK(completion);
1511 if (!(dev->tproto & SAS_PROTOCOL_SSP))
1512 return TMF_RESP_FUNC_ESUPP;
b5762948 1513
20b09c29 1514 strncpy((u8 *)&ssp_task.LUN, lun, 8);
b5762948 1515
20b09c29
AY		 1516 return mvs_exec_internal_tmf_task(dev, &ssp_task,
1517 sizeof(ssp_task), tmf);
1518}
8f261aaf 1519
8f261aaf 1520
20b09c29
AY		 1521/* Standard mandates link reset for ATA (type 0)
1522 and hard reset for SSP (type 1) , only for RECOVERY */
1523static int mvs_debug_I_T_nexus_reset(struct domain_device *dev)
1524{
1525 int rc;
1526 struct sas_phy *phy = sas_find_local_phy(dev);
1527 int reset_type = (dev->dev_type == SATA_DEV ||
1528 (dev->tproto & SAS_PROTOCOL_STP)) ? 0 : 1;
1529 rc = sas_phy_reset(phy, reset_type);
1530 msleep(2000);
1531 return rc;
1532}
8f261aaf 1533
20b09c29
AY		 1534/* mandatory SAM-3 */
1535int mvs_lu_reset(struct domain_device *dev, u8 *lun)
1536{
1537 unsigned long flags;
1538 int i, phyno[WIDE_PORT_MAX_PHY], num , rc = TMF_RESP_FUNC_FAILED;
1539 struct mvs_tmf_task tmf_task;
1540 struct mvs_info *mvi = mvs_find_dev_mvi(dev);
1541 struct mvs_device * mvi_dev = (struct mvs_device *)dev->lldd_dev;
1542
1543 tmf_task.tmf = TMF_LU_RESET;
1544 mvi_dev->dev_status = MVS_DEV_EH;
1545 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
1546 if (rc == TMF_RESP_FUNC_COMPLETE) {
1547 num = mvs_find_dev_phyno(dev, phyno);
1548 spin_lock_irqsave(&mvi->lock, flags);
1549 for (i = 0; i < num; i++)
1550 mvs_release_task(mvi, phyno[i], dev);
1551 spin_unlock_irqrestore(&mvi->lock, flags);
dd4969a8 1552 }
20b09c29
AY		 1553 /* If failed, fall-through I_T_Nexus reset */
1554 mv_printk("%s for device[%x]:rc= %d\n", __func__,
1555 mvi_dev->device_id, rc);
1556 return rc;
1557}
8f261aaf 1558
20b09c29
AY		 1559int mvs_I_T_nexus_reset(struct domain_device *dev)
1560{
1561 unsigned long flags;
1562 int i, phyno[WIDE_PORT_MAX_PHY], num , rc = TMF_RESP_FUNC_FAILED;
1563 struct mvs_info *mvi = mvs_find_dev_mvi(dev);
1564 struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
1565
1566 if (mvi_dev->dev_status != MVS_DEV_EH)
1567 return TMF_RESP_FUNC_COMPLETE;
1568 rc = mvs_debug_I_T_nexus_reset(dev);
1569 mv_printk("%s for device[%x]:rc= %d\n",
1570 __func__, mvi_dev->device_id, rc);
1571
1572 /* housekeeper */
1573 num = mvs_find_dev_phyno(dev, phyno);
1574 spin_lock_irqsave(&mvi->lock, flags);
1575 for (i = 0; i < num; i++)
1576 mvs_release_task(mvi, phyno[i], dev);
1577 spin_unlock_irqrestore(&mvi->lock, flags);
1578
1579 return rc;
1580}
1581/* optional SAM-3 */
1582int mvs_query_task(struct sas_task *task)
1583{
1584 u32 tag;
1585 struct scsi_lun lun;
1586 struct mvs_tmf_task tmf_task;
1587 int rc = TMF_RESP_FUNC_FAILED;
1588
1589 if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
1590 struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
1591 struct domain_device *dev = task->dev;
1592 struct mvs_info *mvi = mvs_find_dev_mvi(dev);
1593
1594 int_to_scsilun(cmnd->device->lun, &lun);
1595 rc = mvs_find_tag(mvi, task, &tag);
1596 if (rc == 0) {
1597 rc = TMF_RESP_FUNC_FAILED;
dd4969a8 1598 return rc;
20b09c29 1599 }
8f261aaf 1600
20b09c29
AY		 1601 tmf_task.tmf = TMF_QUERY_TASK;
1602 tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
8f261aaf 1603
20b09c29
AY		 1604 rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
1605 switch (rc) {
1606 /* The task is still in Lun, release it then */
1607 case TMF_RESP_FUNC_SUCC:
1608 /* The task is not in Lun or failed, reset the phy */
1609 case TMF_RESP_FUNC_FAILED:
1610 case TMF_RESP_FUNC_COMPLETE:
1611 break;
1612 }
dd4969a8 1613 }
20b09c29
AY		 1614 mv_printk("%s:rc= %d\n", __func__, rc);
1615 return rc;
8f261aaf
KW		 1616}
1617
20b09c29
AY		 1618/* mandatory SAM-3, still need free task/slot info */
1619int mvs_abort_task(struct sas_task *task)
8f261aaf 1620{
20b09c29
AY		 1621 struct scsi_lun lun;
1622 struct mvs_tmf_task tmf_task;
1623 struct domain_device *dev = task->dev;
1624 struct mvs_info *mvi = mvs_find_dev_mvi(dev);
1625 int rc = TMF_RESP_FUNC_FAILED;
1626 unsigned long flags;
1627 u32 tag;
1628 if (mvi->exp_req)
1629 mvi->exp_req--;
1630 spin_lock_irqsave(&task->task_state_lock, flags);
1631 if (task->task_state_flags & SAS_TASK_STATE_DONE) {
1632 spin_unlock_irqrestore(&task->task_state_lock, flags);
1633 rc = TMF_RESP_FUNC_COMPLETE;
1634 goto out;
dd4969a8 1635 }
20b09c29
AY		 1636 spin_unlock_irqrestore(&task->task_state_lock, flags);
1637 if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
1638 struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
1639
1640 int_to_scsilun(cmnd->device->lun, &lun);
1641 rc = mvs_find_tag(mvi, task, &tag);
1642 if (rc == 0) {
1643 mv_printk("No such tag in %s\n", __func__);
1644 rc = TMF_RESP_FUNC_FAILED;
1645 return rc;
1646 }
8f261aaf 1647
20b09c29
AY		 1648 tmf_task.tmf = TMF_ABORT_TASK;
1649 tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
8f261aaf 1650
20b09c29 1651 rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
8f261aaf 1652
20b09c29
AY		 1653 /* if successful, clear the task and callback forwards.*/
1654 if (rc == TMF_RESP_FUNC_COMPLETE) {
1655 u32 slot_no;
1656 struct mvs_slot_info *slot;
1657 struct mvs_info *mvi = mvs_find_dev_mvi(dev);
8f261aaf 1658
20b09c29
AY		 1659 if (task->lldd_task) {
1660 slot = (struct mvs_slot_info *)task->lldd_task;
1661 slot_no = (u32) (slot - mvi->slot_info);
1662 mvs_slot_complete(mvi, slot_no, 1);
1663 }
1664 }
1665 } else if (task->task_proto & SAS_PROTOCOL_SATA ||
1666 task->task_proto & SAS_PROTOCOL_STP) {
1667 /* to do free register_set */
1668 } else {
1669 /* SMP */
8f261aaf 1670
20b09c29
AY		 1671 }
1672out:
1673 if (rc != TMF_RESP_FUNC_COMPLETE)
1674 mv_printk("%s:rc= %d\n", __func__, rc);
dd4969a8 1675 return rc;
8f261aaf
KW		 1676}
1677
20b09c29 1678int mvs_abort_task_set(struct domain_device *dev, u8 *lun)
8f261aaf 1679{
20b09c29
AY		 1680 int rc = TMF_RESP_FUNC_FAILED;
1681 struct mvs_tmf_task tmf_task;
8f261aaf 1682
20b09c29
AY		 1683 tmf_task.tmf = TMF_ABORT_TASK_SET;
1684 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
dd4969a8 1685
20b09c29 1686 return rc;
8f261aaf
KW		 1687}
1688
20b09c29 1689int mvs_clear_aca(struct domain_device *dev, u8 *lun)
8f261aaf 1690{
20b09c29
AY		 1691 int rc = TMF_RESP_FUNC_FAILED;
1692 struct mvs_tmf_task tmf_task;
8f261aaf 1693
20b09c29
AY		 1694 tmf_task.tmf = TMF_CLEAR_ACA;
1695 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
8f261aaf 1696
20b09c29
AY		 1697 return rc;
1698}
8f261aaf 1699
20b09c29
AY		 1700int mvs_clear_task_set(struct domain_device *dev, u8 *lun)
1701{
1702 int rc = TMF_RESP_FUNC_FAILED;
1703 struct mvs_tmf_task tmf_task;
8f261aaf 1704
20b09c29
AY		 1705 tmf_task.tmf = TMF_CLEAR_TASK_SET;
1706 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
8f261aaf 1707
20b09c29 1708 return rc;
dd4969a8 1709}
8f261aaf 1710
20b09c29
AY		 1711static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
1712 u32 slot_idx, int err)
dd4969a8 1713{
20b09c29
AY		 1714 struct mvs_device *mvi_dev = (struct mvs_device *)task->dev->lldd_dev;
1715 struct task_status_struct *tstat = &task->task_status;
1716 struct ata_task_resp *resp = (struct ata_task_resp *)tstat->buf;
1717 int stat = SAM_GOOD;
e9ff91b6 1718
8f261aaf 1719
20b09c29
AY		 1720 resp->frame_len = sizeof(struct dev_to_host_fis);
1721 memcpy(&resp->ending_fis[0],
1722 SATA_RECEIVED_D2H_FIS(mvi_dev->taskfileset),
1723 sizeof(struct dev_to_host_fis));
1724 tstat->buf_valid_size = sizeof(*resp);
1725 if (unlikely(err))
1726 stat = SAS_PROTO_RESPONSE;
1727 return stat;
8f261aaf
KW		 1728}
1729
20b09c29
AY		 1730static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
1731 u32 slot_idx)
8f261aaf 1732{
20b09c29
AY		 1733 struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1734 int stat;
1735 u32 err_dw0 = le32_to_cpu(*(u32 *) (slot->response));
1736 u32 tfs = 0;
1737 enum mvs_port_type type = PORT_TYPE_SAS;
8f261aaf 1738
20b09c29
AY		 1739 if (err_dw0 & CMD_ISS_STPD)
1740 MVS_CHIP_DISP->issue_stop(mvi, type, tfs);
1741
1742 MVS_CHIP_DISP->command_active(mvi, slot_idx);
b5762948 1743
20b09c29 1744 stat = SAM_CHECK_COND;
dd4969a8 1745 switch (task->task_proto) {
dd4969a8 1746 case SAS_PROTOCOL_SSP:
20b09c29
AY		 1747 stat = SAS_ABORTED_TASK;
1748 break;
1749 case SAS_PROTOCOL_SMP:
1750 stat = SAM_CHECK_COND;
dd4969a8 1751 break;
20b09c29 1752
dd4969a8
JG		 1753 case SAS_PROTOCOL_SATA:
1754 case SAS_PROTOCOL_STP:
20b09c29
AY		 1755 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1756 {
1757 if (err_dw0 == 0x80400002)
1758 mv_printk("find reserved error, why?\n");
1759
1760 task->ata_task.use_ncq = 0;
1761 stat = SAS_PROTO_RESPONSE;
1762 mvs_sata_done(mvi, task, slot_idx, 1);
1763
dd4969a8 1764 }
20b09c29 1765 break;
dd4969a8
JG		 1766 default:
1767 break;
1768 }
1769
20b09c29 1770 return stat;
e9ff91b6
KW		 1771}
1772
20b09c29 1773int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
b5762948 1774{
20b09c29
AY		 1775 u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
1776 struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1777 struct sas_task *task = slot->task;
1778 struct mvs_device *mvi_dev = NULL;
1779 struct task_status_struct *tstat;
1780
1781 bool aborted;
1782 void *to;
1783 enum exec_status sts;
1784
1785 if (mvi->exp_req)
1786 mvi->exp_req--;
1787 if (unlikely(!task || !task->lldd_task))
1788 return -1;
1789
1790 tstat = &task->task_status;
1791 mvi_dev = (struct mvs_device *)task->dev->lldd_dev;
b5762948 1792
20b09c29
AY		 1793 mvs_hba_cq_dump(mvi);
1794
1795 spin_lock(&task->task_state_lock);
1796 task->task_state_flags &=
1797 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1798 task->task_state_flags |= SAS_TASK_STATE_DONE;
1799 /* race condition*/
1800 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
1801 spin_unlock(&task->task_state_lock);
1802
1803 memset(tstat, 0, sizeof(*tstat));
1804 tstat->resp = SAS_TASK_COMPLETE;
1805
1806 if (unlikely(aborted)) {
1807 tstat->stat = SAS_ABORTED_TASK;
1808 if (mvi_dev)
1809 mvi_dev->runing_req--;
1810 if (sas_protocol_ata(task->task_proto))
1811 mvs_free_reg_set(mvi, mvi_dev);
1812
1813 mvs_slot_task_free(mvi, task, slot, slot_idx);
1814 return -1;
b5762948
JG		 1815 }
1816
20b09c29
AY		 1817 if (unlikely(!mvi_dev || !slot->port->port_attached || flags)) {
1818 mv_dprintk("port has not device.\n");
1819 tstat->stat = SAS_PHY_DOWN;
1820 goto out;
1821 }
b5762948 1822
20b09c29
AY		 1823 /*
1824 if (unlikely((rx_desc & RXQ_ERR) || (*(u64 *) slot->response))) {
1825 mv_dprintk("Find device[%016llx] RXQ_ERR %X,
1826 err info:%016llx\n",
1827 SAS_ADDR(task->dev->sas_addr),
1828 rx_desc, (u64)(*(u64 *) slot->response));
b5762948 1829 }
20b09c29
AY		 1830 */
1831
1832 /* error info record present */
1833 if (unlikely((rx_desc & RXQ_ERR) && (*(u64 *) slot->response))) {
1834 tstat->stat = mvs_slot_err(mvi, task, slot_idx);
1835 goto out;
b5762948
JG		 1836 }
1837
20b09c29
AY		 1838 switch (task->task_proto) {
1839 case SAS_PROTOCOL_SSP:
1840 /* hw says status == 0, datapres == 0 */
1841 if (rx_desc & RXQ_GOOD) {
1842 tstat->stat = SAM_GOOD;
1843 tstat->resp = SAS_TASK_COMPLETE;
1844 }
1845 /* response frame present */
1846 else if (rx_desc & RXQ_RSP) {
1847 struct ssp_response_iu *iu = slot->response +
1848 sizeof(struct mvs_err_info);
1849 sas_ssp_task_response(mvi->dev, task, iu);
1850 } else
1851 tstat->stat = SAM_CHECK_COND;
1852 break;
b5762948 1853
20b09c29
AY		 1854 case SAS_PROTOCOL_SMP: {
1855 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1856 tstat->stat = SAM_GOOD;
1857 to = kmap_atomic(sg_page(sg_resp), KM_IRQ0);
1858 memcpy(to + sg_resp->offset,
1859 slot->response + sizeof(struct mvs_err_info),
1860 sg_dma_len(sg_resp));
1861 kunmap_atomic(to, KM_IRQ0);
1862 break;
1863 }
8f261aaf 1864
20b09c29
AY		 1865 case SAS_PROTOCOL_SATA:
1866 case SAS_PROTOCOL_STP:
1867 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: {
1868 tstat->stat = mvs_sata_done(mvi, task, slot_idx, 0);
1869 break;
1870 }
b5762948 1871
20b09c29
AY		 1872 default:
1873 tstat->stat = SAM_CHECK_COND;
1874 break;
1875 }
b5762948 1876
20b09c29
AY		 1877out:
1878 if (mvi_dev)
1879 mvi_dev->runing_req--;
1880 if (sas_protocol_ata(task->task_proto))
1881 mvs_free_reg_set(mvi, mvi_dev);
b5762948 1882
20b09c29
AY		 1883 mvs_slot_task_free(mvi, task, slot, slot_idx);
1884 sts = tstat->stat;
8f261aaf 1885
20b09c29
AY		 1886 spin_unlock(&mvi->lock);
1887 if (task->task_done)
1888 task->task_done(task);
1889 else
1890 mv_dprintk("why has not task_done.\n");
1891 spin_lock(&mvi->lock);
b5762948 1892
20b09c29
AY		 1893 return sts;
1894}
b5762948 1895
20b09c29
AY		 1896void mvs_release_task(struct mvs_info *mvi,
1897 int phy_no, struct domain_device *dev)
1898{
1899 int i = 0; u32 slot_idx;
1900 struct mvs_phy *phy;
1901 struct mvs_port *port;
1902 struct mvs_slot_info *slot, *slot2;
b5762948 1903
20b09c29
AY		 1904 phy = &mvi->phy[phy_no];
1905 port = phy->port;
1906 if (!port)
1907 return;
b5762948 1908
20b09c29
AY		 1909 list_for_each_entry_safe(slot, slot2, &port->list, entry) {
1910 struct sas_task *task;
1911 slot_idx = (u32) (slot - mvi->slot_info);
1912 task = slot->task;
b5762948 1913
20b09c29
AY		 1914 if (dev && task->dev != dev)
1915 continue;
8f261aaf 1916
20b09c29
AY		 1917 mv_printk("Release slot [%x] tag[%x], task [%p]:\n",
1918 slot_idx, slot->slot_tag, task);
b5762948 1919
20b09c29
AY		 1920 if (task->task_proto & SAS_PROTOCOL_SSP) {
1921 mv_printk("attached with SSP task CDB[");
1922 for (i = 0; i < 16; i++)
1923 mv_printk(" %02x", task->ssp_task.cdb[i]);
1924 mv_printk(" ]\n");
1925 }
b5762948 1926
20b09c29 1927 mvs_slot_complete(mvi, slot_idx, 1);
b5762948 1928 }
20b09c29 1929}
b5762948 1930
20b09c29
AY		 1931static void mvs_phy_disconnected(struct mvs_phy *phy)
1932{
1933 phy->phy_attached = 0;
1934 phy->att_dev_info = 0;
1935 phy->att_dev_sas_addr = 0;
1936}
1937
1938static void mvs_work_queue(struct work_struct *work)
1939{
1940 struct delayed_work *dw = container_of(work, struct delayed_work, work);
1941 struct mvs_wq *mwq = container_of(dw, struct mvs_wq, work_q);
1942 struct mvs_info *mvi = mwq->mvi;
1943 unsigned long flags;
b5762948 1944
20b09c29
AY		 1945 spin_lock_irqsave(&mvi->lock, flags);
1946 if (mwq->handler & PHY_PLUG_EVENT) {
1947 u32 phy_no = (unsigned long) mwq->data;
1948 struct sas_ha_struct *sas_ha = mvi->sas;
1949 struct mvs_phy *phy = &mvi->phy[phy_no];
1950 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1951
1952 if (phy->phy_event & PHY_PLUG_OUT) {
1953 u32 tmp;
1954 struct sas_identify_frame *id;
1955 id = (struct sas_identify_frame *)phy->frame_rcvd;
1956 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);
1957 phy->phy_event &= ~PHY_PLUG_OUT;
1958 if (!(tmp & PHY_READY_MASK)) {
1959 sas_phy_disconnected(sas_phy);
1960 mvs_phy_disconnected(phy);
1961 sas_ha->notify_phy_event(sas_phy,
1962 PHYE_LOSS_OF_SIGNAL);
1963 mv_dprintk("phy%d Removed Device\n", phy_no);
1964 } else {
1965 MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
1966 mvs_update_phyinfo(mvi, phy_no, 1);
1967 mvs_bytes_dmaed(mvi, phy_no);
1968 mvs_port_notify_formed(sas_phy, 0);
1969 mv_dprintk("phy%d Attached Device\n", phy_no);
1970 }
1971 }
1972 }
1973 list_del(&mwq->entry);
1974 spin_unlock_irqrestore(&mvi->lock, flags);
1975 kfree(mwq);
1976}
8f261aaf 1977
20b09c29
AY		 1978static int mvs_handle_event(struct mvs_info *mvi, void *data, int handler)
1979{
1980 struct mvs_wq *mwq;
1981 int ret = 0;
1982
1983 mwq = kmalloc(sizeof(struct mvs_wq), GFP_ATOMIC);
1984 if (mwq) {
1985 mwq->mvi = mvi;
1986 mwq->data = data;
1987 mwq->handler = handler;
1988 MV_INIT_DELAYED_WORK(&mwq->work_q, mvs_work_queue, mwq);
1989 list_add_tail(&mwq->entry, &mvi->wq_list);
1990 schedule_delayed_work(&mwq->work_q, HZ * 2);
1991 } else
1992 ret = -ENOMEM;
1993
1994 return ret;
1995}
b5762948 1996
20b09c29
AY		 1997static void mvs_sig_time_out(unsigned long tphy)
1998{
1999 struct mvs_phy *phy = (struct mvs_phy *)tphy;
2000 struct mvs_info *mvi = phy->mvi;
2001 u8 phy_no;
2002
2003 for (phy_no = 0; phy_no < mvi->chip->n_phy; phy_no++) {
2004 if (&mvi->phy[phy_no] == phy) {
2005 mv_dprintk("Get signature time out, reset phy %d\n",
2006 phy_no+mvi->id*mvi->chip->n_phy);
2007 MVS_CHIP_DISP->phy_reset(mvi, phy_no, 1);
2008 }
b5762948 2009 }
20b09c29 2010}
b5762948 2011
20b09c29
AY		 2012static void mvs_sig_remove_timer(struct mvs_phy *phy)
2013{
2014 if (phy->timer.function)
2015 del_timer(&phy->timer);
2016 phy->timer.function = NULL;
2017}
b5762948 2018
20b09c29
AY		 2019void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
2020{
2021 u32 tmp;
2022 struct sas_ha_struct *sas_ha = mvi->sas;
2023 struct mvs_phy *phy = &mvi->phy[phy_no];
2024 struct asd_sas_phy *sas_phy = &phy->sas_phy;
8f261aaf 2025
20b09c29
AY		 2026 phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
2027 mv_dprintk("port %d ctrl sts=0x%X.\n", phy_no+mvi->id*mvi->chip->n_phy,
2028 MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));
2029 mv_dprintk("Port %d irq sts = 0x%X\n", phy_no+mvi->id*mvi->chip->n_phy,
2030 phy->irq_status);
8f261aaf 2031
20b09c29
AY		 2032 /*
2033 * events is port event now ,
2034 * we need check the interrupt status which belongs to per port.
2035 */
b5762948 2036
20b09c29
AY		 2037 if (phy->irq_status & PHYEV_DCDR_ERR)
2038 mv_dprintk("port %d STP decoding error.\n",
2039 phy_no+mvi->id*mvi->chip->n_phy);
2040
2041 if (phy->irq_status & PHYEV_POOF) {
2042 if (!(phy->phy_event & PHY_PLUG_OUT)) {
2043 int dev_sata = phy->phy_type & PORT_TYPE_SATA;
2044 int ready;
2045 mvs_release_task(mvi, phy_no, NULL);
2046 phy->phy_event |= PHY_PLUG_OUT;
2047 mvs_handle_event(mvi,
2048 (void *)(unsigned long)phy_no,
2049 PHY_PLUG_EVENT);
2050 ready = mvs_is_phy_ready(mvi, phy_no);
2051 if (!ready)
2052 mv_dprintk("phy%d Unplug Notice\n",
2053 phy_no +
2054 mvi->id * mvi->chip->n_phy);
2055 if (ready || dev_sata) {
2056 if (MVS_CHIP_DISP->stp_reset)
2057 MVS_CHIP_DISP->stp_reset(mvi,
2058 phy_no);
2059 else
2060 MVS_CHIP_DISP->phy_reset(mvi,
2061 phy_no, 0);
2062 return;
2063 }
2064 }
2065 }
b5762948 2066
20b09c29
AY		 2067 if (phy->irq_status & PHYEV_COMWAKE) {
2068 tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);
2069 MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,
2070 tmp | PHYEV_SIG_FIS);
2071 if (phy->timer.function == NULL) {
2072 phy->timer.data = (unsigned long)phy;
2073 phy->timer.function = mvs_sig_time_out;
2074 phy->timer.expires = jiffies + 10*HZ;
2075 add_timer(&phy->timer);
2076 }
2077 }
2078 if (phy->irq_status & (PHYEV_SIG_FIS | PHYEV_ID_DONE)) {
2079 phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
2080 mvs_sig_remove_timer(phy);
2081 mv_dprintk("notify plug in on phy[%d]\n", phy_no);
2082 if (phy->phy_status) {
2083 mdelay(10);
2084 MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
2085 if (phy->phy_type & PORT_TYPE_SATA) {
2086 tmp = MVS_CHIP_DISP->read_port_irq_mask(
2087 mvi, phy_no);
2088 tmp &= ~PHYEV_SIG_FIS;
2089 MVS_CHIP_DISP->write_port_irq_mask(mvi,
2090 phy_no, tmp);
2091 }
2092 mvs_update_phyinfo(mvi, phy_no, 0);
2093 mvs_bytes_dmaed(mvi, phy_no);
2094 /* whether driver is going to handle hot plug */
2095 if (phy->phy_event & PHY_PLUG_OUT) {
2096 mvs_port_notify_formed(sas_phy, 0);
2097 phy->phy_event &= ~PHY_PLUG_OUT;
2098 }
2099 } else {
2100 mv_dprintk("plugin interrupt but phy%d is gone\n",
2101 phy_no + mvi->id*mvi->chip->n_phy);
2102 }
2103 } else if (phy->irq_status & PHYEV_BROAD_CH) {
2104 mv_dprintk("port %d broadcast change.\n",
2105 phy_no + mvi->id*mvi->chip->n_phy);
2106 /* exception for Samsung disk drive*/
2107 mdelay(1000);
2108 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2109 }
2110 MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
b5762948
JG		 2111}
2112
20b09c29 2113int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
b5762948 2114{
20b09c29
AY		 2115 u32 rx_prod_idx, rx_desc;
2116 bool attn = false;
b5762948 2117
20b09c29
AY		 2118 /* the first dword in the RX ring is special: it contains
2119 * a mirror of the hardware's RX producer index, so that
2120 * we don't have to stall the CPU reading that register.
2121 * The actual RX ring is offset by one dword, due to this.
2122 */
2123 rx_prod_idx = mvi->rx_cons;
2124 mvi->rx_cons = le32_to_cpu(mvi->rx[0]);
2125 if (mvi->rx_cons == 0xfff) /* h/w hasn't touched RX ring yet */
2126 return 0;
b5762948 2127
20b09c29
AY		 2128 /* The CMPL_Q may come late, read from register and try again
2129 * note: if coalescing is enabled,
2130 * it will need to read from register every time for sure
2131 */
2132 if (unlikely(mvi->rx_cons == rx_prod_idx))
2133 mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;
2134
2135 if (mvi->rx_cons == rx_prod_idx)
2136 return 0;
2137
2138 while (mvi->rx_cons != rx_prod_idx) {
2139 /* increment our internal RX consumer pointer */
2140 rx_prod_idx = (rx_prod_idx + 1) & (MVS_RX_RING_SZ - 1);
2141 rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);
2142
2143 if (likely(rx_desc & RXQ_DONE))
2144 mvs_slot_complete(mvi, rx_desc, 0);
2145 if (rx_desc & RXQ_ATTN) {
2146 attn = true;
2147 } else if (rx_desc & RXQ_ERR) {
2148 if (!(rx_desc & RXQ_DONE))
2149 mvs_slot_complete(mvi, rx_desc, 0);
2150 } else if (rx_desc & RXQ_SLOT_RESET) {
2151 mvs_slot_free(mvi, rx_desc);
2152 }
2153 }
2154
2155 if (attn && self_clear)
2156 MVS_CHIP_DISP->int_full(mvi);
2157 return 0;
b5762948
JG		 2158}
2159
kernel source for telekom puls (alcatel/mediatek)