[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pinctrl / sh-pfc / pinctrl.c

/*
 * SuperH Pin Function Controller pinmux support.
 *
 * Copyright (C) 2012  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#define DRV_NAME "sh-pfc"
#define pr_fmt(fmt) KBUILD_MODNAME " pinctrl: " fmt

#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#include "core.h"

struct sh_pfc_pinctrl {
	struct pinctrl_dev *pctl;
	struct pinctrl_desc pctl_desc;

	struct sh_pfc *pfc;

	struct pinctrl_pin_desc *pins;
};

static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pfc->info->nr_groups;
}

static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
					 unsigned selector)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pfc->info->groups[selector].name;
}

static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
				 const unsigned **pins, unsigned *num_pins)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	*pins = pmx->pfc->info->groups[selector].pins;
	*num_pins = pmx->pfc->info->groups[selector].nr_pins;

	return 0;
}

static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
				unsigned offset)
{
	seq_printf(s, "%s", DRV_NAME);
}

static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
	.get_groups_count	= sh_pfc_get_groups_count,
	.get_group_name		= sh_pfc_get_group_name,
	.get_group_pins		= sh_pfc_get_group_pins,
	.pin_dbg_show		= sh_pfc_pin_dbg_show,
};

static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pfc->info->nr_functions;
}

static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
					    unsigned selector)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pfc->info->functions[selector].name;
}

static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
				      unsigned selector,
				      const char * const **groups,
				      unsigned * const num_groups)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	*groups = pmx->pfc->info->functions[selector].groups;
	*num_groups = pmx->pfc->info->functions[selector].nr_groups;

	return 0;
}

static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
			      unsigned group)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
	unsigned long flags;
	unsigned int i;
	int ret = -EINVAL;

	spin_lock_irqsave(&pfc->lock, flags);

	for (i = 0; i < grp->nr_pins; ++i) {
		if (sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION,
				      GPIO_CFG_DRYRUN))
			goto done;

		if (sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION,
				      GPIO_CFG_REQ))
			goto done;
	}

	ret = 0;

done:
	spin_unlock_irqrestore(&pfc->lock, flags);
	return ret;
}

static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
				unsigned group)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
	unsigned long flags;
	unsigned int i;

	spin_lock_irqsave(&pfc->lock, flags);

	for (i = 0; i < grp->nr_pins; ++i)
		sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION,
				  GPIO_CFG_FREE);

	spin_unlock_irqrestore(&pfc->lock, flags);
}

static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
			       int new_type)
{
	struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset);
	unsigned int mark = pin->enum_id;
	unsigned long flags;
	int pinmux_type;
	int ret = -EINVAL;

	spin_lock_irqsave(&pfc->lock, flags);

	pinmux_type = pin->flags & PINMUX_FLAG_TYPE;

	/*
	 * See if the present config needs to first be de-configured.
	 */
	switch (pinmux_type) {
	case PINMUX_TYPE_GPIO:
		break;
	case PINMUX_TYPE_OUTPUT:
	case PINMUX_TYPE_INPUT:
	case PINMUX_TYPE_INPUT_PULLUP:
	case PINMUX_TYPE_INPUT_PULLDOWN:
		sh_pfc_config_mux(pfc, mark, pinmux_type, GPIO_CFG_FREE);
		break;
	default:
		goto err;
	}

	/*
	 * Dry run
	 */
	if (sh_pfc_config_mux(pfc, mark, new_type, GPIO_CFG_DRYRUN) != 0)
		goto err;

	/*
	 * Request
	 */
	if (sh_pfc_config_mux(pfc, mark, new_type, GPIO_CFG_REQ) != 0)
		goto err;

	pin->flags &= ~PINMUX_FLAG_TYPE;
	pin->flags |= new_type;

	ret = 0;

err:
	spin_unlock_irqrestore(&pfc->lock, flags);

	return ret;
}

static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
				      struct pinctrl_gpio_range *range,
				      unsigned offset)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset);
	unsigned long flags;
	int ret, pinmux_type;

	spin_lock_irqsave(&pfc->lock, flags);

	pinmux_type = pin->flags & PINMUX_FLAG_TYPE;

	switch (pinmux_type) {
	case PINMUX_TYPE_GPIO:
	case PINMUX_TYPE_INPUT:
	case PINMUX_TYPE_OUTPUT:
		break;
	case PINMUX_TYPE_FUNCTION:
	default:
		pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type);
		ret = -ENOTSUPP;
		goto err;
	}

	ret = 0;

err:
	spin_unlock_irqrestore(&pfc->lock, flags);

	return ret;
}

static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
				     struct pinctrl_gpio_range *range,
				     unsigned offset)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset);
	unsigned long flags;
	int pinmux_type;

	spin_lock_irqsave(&pfc->lock, flags);

	pinmux_type = pin->flags & PINMUX_FLAG_TYPE;

	sh_pfc_config_mux(pfc, pin->enum_id, pinmux_type, GPIO_CFG_FREE);

	spin_unlock_irqrestore(&pfc->lock, flags);
}

static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
				     struct pinctrl_gpio_range *range,
				     unsigned offset, bool input)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;

	return sh_pfc_reconfig_pin(pmx->pfc, offset, type);
}

static const struct pinmux_ops sh_pfc_pinmux_ops = {
	.get_functions_count	= sh_pfc_get_functions_count,
	.get_function_name	= sh_pfc_get_function_name,
	.get_function_groups	= sh_pfc_get_function_groups,
	.enable			= sh_pfc_func_enable,
	.disable		= sh_pfc_func_disable,
	.gpio_request_enable	= sh_pfc_gpio_request_enable,
	.gpio_disable_free	= sh_pfc_gpio_disable_free,
	.gpio_set_direction	= sh_pfc_gpio_set_direction,
};

static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
			      unsigned long *config)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, _pin);

	*config = pin->flags & PINMUX_FLAG_TYPE;

	return 0;
}

static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
			      unsigned long config)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	/* Validate the new type */
	if (config >= PINMUX_FLAG_TYPE)
		return -EINVAL;

	return sh_pfc_reconfig_pin(pmx->pfc, pin, config);
}

static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev,
				    struct seq_file *s, unsigned pin)
{
	const char *pinmux_type_str[] = {
		[PINMUX_TYPE_NONE]		= "none",
		[PINMUX_TYPE_FUNCTION]		= "function",
		[PINMUX_TYPE_GPIO]		= "gpio",
		[PINMUX_TYPE_OUTPUT]		= "output",
		[PINMUX_TYPE_INPUT]		= "input",
		[PINMUX_TYPE_INPUT_PULLUP]	= "input bias pull up",
		[PINMUX_TYPE_INPUT_PULLDOWN]	= "input bias pull down",
	};
	unsigned long config;
	int rc;

	rc = sh_pfc_pinconf_get(pctldev, pin, &config);
	if (unlikely(rc != 0))
		return;

	seq_printf(s, " %s", pinmux_type_str[config]);
}

static const struct pinconf_ops sh_pfc_pinconf_ops = {
	.pin_config_get		= sh_pfc_pinconf_get,
	.pin_config_set		= sh_pfc_pinconf_set,
	.pin_config_dbg_show	= sh_pfc_pinconf_dbg_show,
};

/* PFC ranges -> pinctrl pin descs */
static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
{
	const struct pinmux_range *ranges;
	struct pinmux_range def_range;
	unsigned int nr_ranges;
	unsigned int nr_pins;
	unsigned int i;

	if (pfc->info->ranges == NULL) {
		def_range.begin = 0;
		def_range.end = pfc->info->nr_pins - 1;
		ranges = &def_range;
		nr_ranges = 1;
	} else {
		ranges = pfc->info->ranges;
		nr_ranges = pfc->info->nr_ranges;
	}

	pmx->pins = devm_kzalloc(pfc->dev,
				 sizeof(*pmx->pins) * pfc->info->nr_pins,
				 GFP_KERNEL);
	if (unlikely(!pmx->pins))
		return -ENOMEM;

	for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
		const struct pinmux_range *range = &ranges[i];
		unsigned int number;

		for (number = range->begin; number <= range->end;
		     number++, nr_pins++) {
			struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
			struct sh_pfc_pin *info = &pfc->info->pins[nr_pins];

			pin->number = number;
			pin->name = info->name;
		}
	}

	pfc->nr_pins = ranges[nr_ranges-1].end + 1;

	return nr_ranges;
}

int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
{
	struct sh_pfc_pinctrl *pmx;
	int nr_ranges;

	pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
	if (unlikely(!pmx))
		return -ENOMEM;

	pmx->pfc = pfc;
	pfc->pinctrl = pmx;

	nr_ranges = sh_pfc_map_pins(pfc, pmx);
	if (unlikely(nr_ranges < 0))
		return nr_ranges;

	pmx->pctl_desc.name = DRV_NAME;
	pmx->pctl_desc.owner = THIS_MODULE;
	pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
	pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
	pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
	pmx->pctl_desc.pins = pmx->pins;
	pmx->pctl_desc.npins = pfc->info->nr_pins;

	pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
	if (pmx->pctl == NULL)
		return -EINVAL;

	return 0;
}

int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc)
{
	struct sh_pfc_pinctrl *pmx = pfc->pinctrl;

	pinctrl_unregister(pmx->pctl);

	pfc->pinctrl = NULL;
	return 0;
}
Commit	Line	Data
ca5481c6 PM	1	/*
	2	* SuperH Pin Function Controller pinmux support.
	3	*
	4	* Copyright (C) 2012 Paul Mundt
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
54407110	10
c6193eac	11	#define DRV_NAME "sh-pfc"
f9492fda	12	#define pr_fmt(fmt) KBUILD_MODNAME " pinctrl: " fmt
ca5481c6	13
1724acfd	14	#include <linux/device.h>
90efde22	15	#include <linux/err.h>
ca5481c6 PM	16	#include <linux/init.h>
ca5481c6 PM	17	#include <linux/module.h>
ca5481c6	18	#include <linux/pinctrl/consumer.h>
ca5481c6	19	#include <linux/pinctrl/pinconf.h>
ca5481c6	20	#include <linux/pinctrl/pinconf-generic.h>
90efde22 LP	21	#include <linux/pinctrl/pinctrl.h>
90efde22 LP	22	#include <linux/pinctrl/pinmux.h>
90efde22 LP	23	#include <linux/slab.h>
90efde22 LP	24	#include <linux/spinlock.h>
ca5481c6	25
f9165132 LP	26	#include "core.h"
f9165132 LP	27
ca5481c6 PM	28	struct sh_pfc_pinctrl {
ca5481c6 PM	29	struct pinctrl_dev *pctl;
dcc427e1	30	struct pinctrl_desc pctl_desc;
dcc427e1	31
ca5481c6 PM	32	struct sh_pfc *pfc;
ca5481c6 PM	33
3d8d9f1d	34	struct pinctrl_pin_desc *pins;
ca5481c6 PM	35	};
ca5481c6 PM	36
e3f805e8	37	static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
ca5481c6	38	{
e3f805e8 PM	39	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
e3f805e8 PM	40
3d8d9f1d	41	return pmx->pfc->info->nr_groups;
ca5481c6 PM	42	}
ca5481c6 PM	43
e3f805e8	44	static const char sh_pfc_get_group_name(struct pinctrl_dev pctldev,
ca5481c6 PM	45	unsigned selector)
ca5481c6 PM	46	{
e3f805e8 PM	47	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
e3f805e8 PM	48
3d8d9f1d	49	return pmx->pfc->info->groups[selector].name;
ca5481c6 PM	50	}
ca5481c6 PM	51
3d8d9f1d	52	static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
ca5481c6 PM	53	const unsigned *pins, unsigned num_pins)
ca5481c6 PM	54	{
e3f805e8 PM	55	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
e3f805e8 PM	56
3d8d9f1d LP	57	*pins = pmx->pfc->info->groups[selector].pins;
3d8d9f1d LP	58	*num_pins = pmx->pfc->info->groups[selector].nr_pins;
e3f805e8 PM	59
e3f805e8 PM	60	return 0;
ca5481c6 PM	61	}
ca5481c6 PM	62
fdd85ec3 PM	63	static void sh_pfc_pin_dbg_show(struct pinctrl_dev pctldev, struct seq_file s,
	64	unsigned offset)
	65	{
	66	seq_printf(s, "%s", DRV_NAME);
	67	}
	68
fe330ce8	69	static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
e3f805e8 PM	70	.get_groups_count = sh_pfc_get_groups_count,
e3f805e8 PM	71	.get_group_name = sh_pfc_get_group_name,
ca5481c6	72	.get_group_pins = sh_pfc_get_group_pins,
fdd85ec3	73	.pin_dbg_show = sh_pfc_pin_dbg_show,
ca5481c6 PM	74	};
ca5481c6 PM	75
d93a891f PM	76	static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
	77	{
	78	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	79
3d8d9f1d	80	return pmx->pfc->info->nr_functions;
d93a891f PM	81	}
	82
	83	static const char sh_pfc_get_function_name(struct pinctrl_dev pctldev,
	84	unsigned selector)
	85	{
	86	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	87
3d8d9f1d	88	return pmx->pfc->info->functions[selector].name;
d93a891f	89	}
ca5481c6	90
3d8d9f1d LP	91	static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
3d8d9f1d LP	92	unsigned selector,
ca5481c6 PM	93	const char * const **groups,
	94	unsigned * const num_groups)
	95	{
d93a891f PM	96	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
d93a891f PM	97
3d8d9f1d LP	98	*groups = pmx->pfc->info->functions[selector].groups;
3d8d9f1d LP	99	*num_groups = pmx->pfc->info->functions[selector].nr_groups;
d93a891f	100
ca5481c6 PM	101	return 0;
	102	}
	103
3d8d9f1d	104	static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
ca5481c6 PM	105	unsigned group)
ca5481c6 PM	106	{
3d8d9f1d LP	107	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	108	struct sh_pfc *pfc = pmx->pfc;
	109	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
	110	unsigned long flags;
	111	unsigned int i;
	112	int ret = -EINVAL;
	113
	114	spin_lock_irqsave(&pfc->lock, flags);
	115
	116	for (i = 0; i < grp->nr_pins; ++i) {
	117	if (sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION,
	118	GPIO_CFG_DRYRUN))
	119	goto done;
	120
	121	if (sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION,
	122	GPIO_CFG_REQ))
	123	goto done;
	124	}
	125
	126	ret = 0;
	127
	128	done:
	129	spin_unlock_irqrestore(&pfc->lock, flags);
	130	return ret;
ca5481c6 PM	131	}
ca5481c6 PM	132
3d8d9f1d	133	static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
ca5481c6 PM	134	unsigned group)
ca5481c6 PM	135	{
3d8d9f1d LP	136	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	137	struct sh_pfc *pfc = pmx->pfc;
	138	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
	139	unsigned long flags;
	140	unsigned int i;
	141
	142	spin_lock_irqsave(&pfc->lock, flags);
	143
	144	for (i = 0; i < grp->nr_pins; ++i)
	145	sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION,
	146	GPIO_CFG_FREE);
	147
	148	spin_unlock_irqrestore(&pfc->lock, flags);
ca5481c6 PM	149	}
ca5481c6 PM	150
fdd85ec3 PM	151	static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
	152	int new_type)
	153	{
934cb02b LP	154	struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset);
934cb02b LP	155	unsigned int mark = pin->enum_id;
fdd85ec3 PM	156	unsigned long flags;
	157	int pinmux_type;
	158	int ret = -EINVAL;
	159
	160	spin_lock_irqsave(&pfc->lock, flags);
	161
934cb02b	162	pinmux_type = pin->flags & PINMUX_FLAG_TYPE;
fdd85ec3 PM	163
	164	/*
	165	* See if the present config needs to first be de-configured.
	166	*/
	167	switch (pinmux_type) {
	168	case PINMUX_TYPE_GPIO:
	169	break;
	170	case PINMUX_TYPE_OUTPUT:
	171	case PINMUX_TYPE_INPUT:
	172	case PINMUX_TYPE_INPUT_PULLUP:
	173	case PINMUX_TYPE_INPUT_PULLDOWN:
a68fdca9	174	sh_pfc_config_mux(pfc, mark, pinmux_type, GPIO_CFG_FREE);
fdd85ec3 PM	175	break;
	176	default:
	177	goto err;
	178	}
	179
	180	/*
	181	* Dry run
	182	*/
a68fdca9	183	if (sh_pfc_config_mux(pfc, mark, new_type, GPIO_CFG_DRYRUN) != 0)
fdd85ec3 PM	184	goto err;
	185
	186	/*
	187	* Request
	188	*/
a68fdca9	189	if (sh_pfc_config_mux(pfc, mark, new_type, GPIO_CFG_REQ) != 0)
fdd85ec3 PM	190	goto err;
fdd85ec3 PM	191
934cb02b LP	192	pin->flags &= ~PINMUX_FLAG_TYPE;
934cb02b LP	193	pin->flags \|= new_type;
fdd85ec3 PM	194
	195	ret = 0;
	196
	197	err:
	198	spin_unlock_irqrestore(&pfc->lock, flags);
	199
	200	return ret;
	201	}
	202
ca5481c6 PM	203	static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
	204	struct pinctrl_gpio_range *range,
	205	unsigned offset)
	206	{
	207	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	208	struct sh_pfc *pfc = pmx->pfc;
934cb02b	209	struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset);
ca5481c6	210	unsigned long flags;
d93a891f	211	int ret, pinmux_type;
ca5481c6 PM	212
	213	spin_lock_irqsave(&pfc->lock, flags);
	214
934cb02b	215	pinmux_type = pin->flags & PINMUX_FLAG_TYPE;
ca5481c6	216
d93a891f	217	switch (pinmux_type) {
d93a891f	218	case PINMUX_TYPE_GPIO:
16d74ebe PM	219	case PINMUX_TYPE_INPUT:
16d74ebe PM	220	case PINMUX_TYPE_OUTPUT:
d93a891f	221	break;
2119f7c9	222	case PINMUX_TYPE_FUNCTION:
d93a891f PM	223	default:
d93a891f PM	224	pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type);
077664a2 LP	225	ret = -ENOTSUPP;
077664a2 LP	226	goto err;
d93a891f	227	}
ca5481c6 PM	228
	229	ret = 0;
	230
	231	err:
	232	spin_unlock_irqrestore(&pfc->lock, flags);
	233
	234	return ret;
	235	}
	236
	237	static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
	238	struct pinctrl_gpio_range *range,
	239	unsigned offset)
	240	{
	241	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	242	struct sh_pfc *pfc = pmx->pfc;
934cb02b	243	struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset);
ca5481c6 PM	244	unsigned long flags;
	245	int pinmux_type;
	246
	247	spin_lock_irqsave(&pfc->lock, flags);
	248
934cb02b	249	pinmux_type = pin->flags & PINMUX_FLAG_TYPE;
ca5481c6	250
934cb02b	251	sh_pfc_config_mux(pfc, pin->enum_id, pinmux_type, GPIO_CFG_FREE);
ca5481c6	252
ca5481c6 PM	253	spin_unlock_irqrestore(&pfc->lock, flags);
	254	}
	255
	256	static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
	257	struct pinctrl_gpio_range *range,
	258	unsigned offset, bool input)
	259	{
	260	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
fdd85ec3	261	int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
ca5481c6	262
fdd85ec3	263	return sh_pfc_reconfig_pin(pmx->pfc, offset, type);
ca5481c6 PM	264	}
ca5481c6 PM	265
fe330ce8	266	static const struct pinmux_ops sh_pfc_pinmux_ops = {
d93a891f PM	267	.get_functions_count = sh_pfc_get_functions_count,
d93a891f PM	268	.get_function_name = sh_pfc_get_function_name,
ca5481c6	269	.get_function_groups = sh_pfc_get_function_groups,
3d8d9f1d LP	270	.enable = sh_pfc_func_enable,
3d8d9f1d LP	271	.disable = sh_pfc_func_disable,
ca5481c6 PM	272	.gpio_request_enable = sh_pfc_gpio_request_enable,
	273	.gpio_disable_free = sh_pfc_gpio_disable_free,
	274	.gpio_set_direction = sh_pfc_gpio_set_direction,
	275	};
	276
934cb02b	277	static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
ca5481c6 PM	278	unsigned long *config)
ca5481c6 PM	279	{
fdd85ec3 PM	280	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
fdd85ec3 PM	281	struct sh_pfc *pfc = pmx->pfc;
934cb02b	282	struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, _pin);
d93a891f	283
934cb02b	284	*config = pin->flags & PINMUX_FLAG_TYPE;
d93a891f	285
fdd85ec3	286	return 0;
ca5481c6 PM	287	}
	288
	289	static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
	290	unsigned long config)
	291	{
fdd85ec3	292	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
fdd85ec3 PM	293
	294	/* Validate the new type */
	295	if (config >= PINMUX_FLAG_TYPE)
	296	return -EINVAL;
	297
	298	return sh_pfc_reconfig_pin(pmx->pfc, pin, config);
	299	}
	300
	301	static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev,
	302	struct seq_file *s, unsigned pin)
	303	{
	304	const char *pinmux_type_str[] = {
	305	[PINMUX_TYPE_NONE] = "none",
	306	[PINMUX_TYPE_FUNCTION] = "function",
	307	[PINMUX_TYPE_GPIO] = "gpio",
	308	[PINMUX_TYPE_OUTPUT] = "output",
	309	[PINMUX_TYPE_INPUT] = "input",
	310	[PINMUX_TYPE_INPUT_PULLUP] = "input bias pull up",
	311	[PINMUX_TYPE_INPUT_PULLDOWN] = "input bias pull down",
	312	};
	313	unsigned long config;
	314	int rc;
	315
	316	rc = sh_pfc_pinconf_get(pctldev, pin, &config);
	317	if (unlikely(rc != 0))
	318	return;
	319
	320	seq_printf(s, " %s", pinmux_type_str[config]);
ca5481c6 PM	321	}
ca5481c6 PM	322
fe330ce8	323	static const struct pinconf_ops sh_pfc_pinconf_ops = {
ca5481c6 PM	324	.pin_config_get = sh_pfc_pinconf_get,
ca5481c6 PM	325	.pin_config_set = sh_pfc_pinconf_set,
fdd85ec3	326	.pin_config_dbg_show = sh_pfc_pinconf_dbg_show,
ca5481c6 PM	327	};
ca5481c6 PM	328
63d57383 LP	329	/* PFC ranges -> pinctrl pin descs */
63d57383 LP	330	static int sh_pfc_map_pins(struct sh_pfc pfc, struct sh_pfc_pinctrl pmx)
ca5481c6	331	{
63d57383 LP	332	const struct pinmux_range *ranges;
	333	struct pinmux_range def_range;
	334	unsigned int nr_ranges;
	335	unsigned int nr_pins;
	336	unsigned int i;
	337
	338	if (pfc->info->ranges == NULL) {
	339	def_range.begin = 0;
	340	def_range.end = pfc->info->nr_pins - 1;
	341	ranges = &def_range;
	342	nr_ranges = 1;
	343	} else {
	344	ranges = pfc->info->ranges;
	345	nr_ranges = pfc->info->nr_ranges;
	346	}
ca5481c6	347
3d8d9f1d LP	348	pmx->pins = devm_kzalloc(pfc->dev,
3d8d9f1d LP	349	sizeof(pmx->pins) pfc->info->nr_pins,
1724acfd	350	GFP_KERNEL);
3d8d9f1d	351	if (unlikely(!pmx->pins))
ca5481c6	352	return -ENOMEM;
ca5481c6	353
63d57383 LP	354	for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
	355	const struct pinmux_range *range = &ranges[i];
	356	unsigned int number;
	357
	358	for (number = range->begin; number <= range->end;
	359	number++, nr_pins++) {
3d8d9f1d	360	struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
63d57383	361	struct sh_pfc_pin *info = &pfc->info->pins[nr_pins];
ca5481c6	362
63d57383 LP	363	pin->number = number;
	364	pin->name = info->name;
	365	}
ca5481c6 PM	366	}
ca5481c6 PM	367
63d57383 LP	368	pfc->nr_pins = ranges[nr_ranges-1].end + 1;
	369
	370	return nr_ranges;
ca5481c6 PM	371	}
ca5481c6 PM	372
c6193eac	373	int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
ca5481c6	374	{
c6193eac	375	struct sh_pfc_pinctrl *pmx;
63d57383	376	int nr_ranges;
ca5481c6	377
1724acfd	378	pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
c6193eac LP	379	if (unlikely(!pmx))
	380	return -ENOMEM;
	381
c6193eac LP	382	pmx->pfc = pfc;
c6193eac LP	383	pfc->pinctrl = pmx;
ca5481c6	384
63d57383 LP	385	nr_ranges = sh_pfc_map_pins(pfc, pmx);
	386	if (unlikely(nr_ranges < 0))
	387	return nr_ranges;
ca5481c6	388
dcc427e1 LP	389	pmx->pctl_desc.name = DRV_NAME;
	390	pmx->pctl_desc.owner = THIS_MODULE;
	391	pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
	392	pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
	393	pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
3d8d9f1d	394	pmx->pctl_desc.pins = pmx->pins;
63d57383	395	pmx->pctl_desc.npins = pfc->info->nr_pins;
dcc427e1 LP	396
dcc427e1 LP	397	pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
fd9d05b0 WY	398	if (pmx->pctl == NULL)
fd9d05b0 WY	399	return -EINVAL;
ca5481c6	400
ca5481c6	401	return 0;
ca5481c6 PM	402	}
ca5481c6 PM	403
c6193eac	404	int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc)
ca5481c6	405	{
c6193eac	406	struct sh_pfc_pinctrl *pmx = pfc->pinctrl;
ca5481c6	407
ca5481c6 PM	408	pinctrl_unregister(pmx->pctl);
ca5481c6 PM	409
c6193eac	410	pfc->pinctrl = NULL;
ca5481c6 PM	411	return 0;
ca5481c6 PM	412	}