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e1000e: enable ECC on I217/I218 to catch packet buffer memory errors
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / vmxnet3 / vmxnet3_drv.c
CommitLineData
d1a890fa
SB		 1/*
2 * Linux driver for VMware's vmxnet3 ethernet NIC.
3 *
4 * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 *
23 * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
24 *
25 */
26
9d9779e7 27#include <linux/module.h>
b038b040
SR		 28#include <net/ip6_checksum.h>
29
d1a890fa
SB		 30#include "vmxnet3_int.h"
31
32char vmxnet3_driver_name[] = "vmxnet3";
33#define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
34
d1a890fa
SB		 35/*
36 * PCI Device ID Table
37 * Last entry must be all 0s
38 */
a3aa1884 39static DEFINE_PCI_DEVICE_TABLE(vmxnet3_pciid_table) = {
d1a890fa
SB		 40 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
41 {0}
42};
43
44MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
45
46static atomic_t devices_found;
47
09c5088e
SB		 48#define VMXNET3_MAX_DEVICES 10
49static int enable_mq = 1;
50static int irq_share_mode;
d1a890fa 51
f9f25026
SB		 52static void
53vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac);
54
d1a890fa
SB		 55/*
56 * Enable/Disable the given intr
57 */
58static void
59vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
60{
61 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
62}
63
64
65static void
66vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
67{
68 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
69}
70
71
72/*
73 * Enable/Disable all intrs used by the device
74 */
75static void
76vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
77{
78 int i;
79
80 for (i = 0; i < adapter->intr.num_intrs; i++)
81 vmxnet3_enable_intr(adapter, i);
6929fe8a
RZ		 82 adapter->shared->devRead.intrConf.intrCtrl &=
83 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 84}
85
86
87static void
88vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
89{
90 int i;
91
6929fe8a
RZ		 92 adapter->shared->devRead.intrConf.intrCtrl |=
93 cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 94 for (i = 0; i < adapter->intr.num_intrs; i++)
95 vmxnet3_disable_intr(adapter, i);
96}
97
98
99static void
100vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
101{
102 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
103}
104
105
106static bool
107vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
108{
09c5088e 109 return tq->stopped;
d1a890fa
SB		 110}
111
112
113static void
114vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
115{
116 tq->stopped = false;
09c5088e 117 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
d1a890fa
SB		 118}
119
120
121static void
122vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
123{
124 tq->stopped = false;
09c5088e 125 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
d1a890fa
SB		 126}
127
128
129static void
130vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
131{
132 tq->stopped = true;
133 tq->num_stop++;
09c5088e 134 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
d1a890fa
SB		 135}
136
137
138/*
139 * Check the link state. This may start or stop the tx queue.
140 */
141static void
4a1745fc 142vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
d1a890fa
SB		 143{
144 u32 ret;
09c5088e 145 int i;
83d0feff 146 unsigned long flags;
d1a890fa 147
83d0feff 148 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 149 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
150 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
83d0feff
SB		 151 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
152
d1a890fa
SB		 153 adapter->link_speed = ret >> 16;
154 if (ret & 1) { /* Link is up. */
155 printk(KERN_INFO "%s: NIC Link is Up %d Mbps\n",
156 adapter->netdev->name, adapter->link_speed);
157 if (!netif_carrier_ok(adapter->netdev))
158 netif_carrier_on(adapter->netdev);
159
09c5088e
SB		 160 if (affectTxQueue) {
161 for (i = 0; i < adapter->num_tx_queues; i++)
162 vmxnet3_tq_start(&adapter->tx_queue[i],
163 adapter);
164 }
d1a890fa
SB		 165 } else {
166 printk(KERN_INFO "%s: NIC Link is Down\n",
167 adapter->netdev->name);
168 if (netif_carrier_ok(adapter->netdev))
169 netif_carrier_off(adapter->netdev);
170
09c5088e
SB		 171 if (affectTxQueue) {
172 for (i = 0; i < adapter->num_tx_queues; i++)
173 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
174 }
d1a890fa
SB		 175 }
176}
177
d1a890fa
SB		 178static void
179vmxnet3_process_events(struct vmxnet3_adapter *adapter)
180{
09c5088e 181 int i;
e328d410 182 unsigned long flags;
115924b6 183 u32 events = le32_to_cpu(adapter->shared->ecr);
d1a890fa
SB		 184 if (!events)
185 return;
186
187 vmxnet3_ack_events(adapter, events);
188
189 /* Check if link state has changed */
190 if (events & VMXNET3_ECR_LINK)
4a1745fc 191 vmxnet3_check_link(adapter, true);
d1a890fa
SB		 192
193 /* Check if there is an error on xmit/recv queues */
194 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
e328d410 195 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 196 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
197 VMXNET3_CMD_GET_QUEUE_STATUS);
e328d410 198 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa 199
09c5088e
SB		 200 for (i = 0; i < adapter->num_tx_queues; i++)
201 if (adapter->tqd_start[i].status.stopped)
202 dev_err(&adapter->netdev->dev,
203 "%s: tq[%d] error 0x%x\n",
204 adapter->netdev->name, i, le32_to_cpu(
205 adapter->tqd_start[i].status.error));
206 for (i = 0; i < adapter->num_rx_queues; i++)
207 if (adapter->rqd_start[i].status.stopped)
208 dev_err(&adapter->netdev->dev,
209 "%s: rq[%d] error 0x%x\n",
210 adapter->netdev->name, i,
211 adapter->rqd_start[i].status.error);
d1a890fa
SB		 212
213 schedule_work(&adapter->work);
214 }
215}
216
115924b6
SB		 217#ifdef __BIG_ENDIAN_BITFIELD
218/*
219 * The device expects the bitfields in shared structures to be written in
220 * little endian. When CPU is big endian, the following routines are used to
221 * correctly read and write into ABI.
222 * The general technique used here is : double word bitfields are defined in
223 * opposite order for big endian architecture. Then before reading them in
224 * driver the complete double word is translated using le32_to_cpu. Similarly
225 * After the driver writes into bitfields, cpu_to_le32 is used to translate the
226 * double words into required format.
227 * In order to avoid touching bits in shared structure more than once, temporary
228 * descriptors are used. These are passed as srcDesc to following functions.
229 */
230static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
231 struct Vmxnet3_RxDesc *dstDesc)
232{
233 u32 *src = (u32 *)srcDesc + 2;
234 u32 *dst = (u32 *)dstDesc + 2;
235 dstDesc->addr = le64_to_cpu(srcDesc->addr);
236 *dst = le32_to_cpu(*src);
237 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
238}
239
240static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
241 struct Vmxnet3_TxDesc *dstDesc)
242{
243 int i;
244 u32 *src = (u32 *)(srcDesc + 1);
245 u32 *dst = (u32 *)(dstDesc + 1);
246
247 /* Working backwards so that the gen bit is set at the end. */
248 for (i = 2; i > 0; i--) {
249 src--;
250 dst--;
251 *dst = cpu_to_le32(*src);
252 }
253}
254
255
256static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
257 struct Vmxnet3_RxCompDesc *dstDesc)
258{
259 int i = 0;
260 u32 *src = (u32 *)srcDesc;
261 u32 *dst = (u32 *)dstDesc;
262 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
263 *dst = le32_to_cpu(*src);
264 src++;
265 dst++;
266 }
267}
268
269
270/* Used to read bitfield values from double words. */
271static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
272{
273 u32 temp = le32_to_cpu(*bitfield);
274 u32 mask = ((1 << size) - 1) << pos;
275 temp &= mask;
276 temp >>= pos;
277 return temp;
278}
279
280
281
282#endif /* __BIG_ENDIAN_BITFIELD */
283
284#ifdef __BIG_ENDIAN_BITFIELD
285
286# define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
287 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
288 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
289# define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
290 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
291 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
292# define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
293 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
294 VMXNET3_TCD_GEN_SIZE)
295# define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
296 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
297# define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
298 (dstrcd) = (tmp); \
299 vmxnet3_RxCompToCPU((rcd), (tmp)); \
300 } while (0)
301# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
302 (dstrxd) = (tmp); \
303 vmxnet3_RxDescToCPU((rxd), (tmp)); \
304 } while (0)
305
306#else
307
308# define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
309# define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
310# define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
311# define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
312# define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
313# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
314
315#endif /* __BIG_ENDIAN_BITFIELD */
316
d1a890fa
SB		 317
318static void
319vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
320 struct pci_dev *pdev)
321{
322 if (tbi->map_type == VMXNET3_MAP_SINGLE)
323 pci_unmap_single(pdev, tbi->dma_addr, tbi->len,
324 PCI_DMA_TODEVICE);
325 else if (tbi->map_type == VMXNET3_MAP_PAGE)
326 pci_unmap_page(pdev, tbi->dma_addr, tbi->len,
327 PCI_DMA_TODEVICE);
328 else
329 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE);
330
331 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
332}
333
334
335static int
336vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
337 struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
338{
339 struct sk_buff *skb;
340 int entries = 0;
341
342 /* no out of order completion */
343 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
115924b6 344 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
d1a890fa
SB		 345
346 skb = tq->buf_info[eop_idx].skb;
347 BUG_ON(skb == NULL);
348 tq->buf_info[eop_idx].skb = NULL;
349
350 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
351
352 while (tq->tx_ring.next2comp != eop_idx) {
353 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
354 pdev);
355
356 /* update next2comp w/o tx_lock. Since we are marking more,
357 * instead of less, tx ring entries avail, the worst case is
358 * that the tx routine incorrectly re-queues a pkt due to
359 * insufficient tx ring entries.
360 */
361 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
362 entries++;
363 }
364
365 dev_kfree_skb_any(skb);
366 return entries;
367}
368
369
370static int
371vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
372 struct vmxnet3_adapter *adapter)
373{
374 int completed = 0;
375 union Vmxnet3_GenericDesc *gdesc;
376
377 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
115924b6
SB		 378 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
379 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
380 &gdesc->tcd), tq, adapter->pdev,
381 adapter);
d1a890fa
SB		 382
383 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
384 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
385 }
386
387 if (completed) {
388 spin_lock(&tq->tx_lock);
389 if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
390 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
391 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
392 netif_carrier_ok(adapter->netdev))) {
393 vmxnet3_tq_wake(tq, adapter);
394 }
395 spin_unlock(&tq->tx_lock);
396 }
397 return completed;
398}
399
400
401static void
402vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
403 struct vmxnet3_adapter *adapter)
404{
405 int i;
406
407 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
408 struct vmxnet3_tx_buf_info *tbi;
d1a890fa
SB		 409
410 tbi = tq->buf_info + tq->tx_ring.next2comp;
d1a890fa
SB		 411
412 vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
413 if (tbi->skb) {
414 dev_kfree_skb_any(tbi->skb);
415 tbi->skb = NULL;
416 }
417 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
418 }
419
420 /* sanity check, verify all buffers are indeed unmapped and freed */
421 for (i = 0; i < tq->tx_ring.size; i++) {
422 BUG_ON(tq->buf_info[i].skb != NULL ||
423 tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
424 }
425
426 tq->tx_ring.gen = VMXNET3_INIT_GEN;
427 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
428
429 tq->comp_ring.gen = VMXNET3_INIT_GEN;
430 tq->comp_ring.next2proc = 0;
431}
432
433
09c5088e 434static void
d1a890fa
SB		 435vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
436 struct vmxnet3_adapter *adapter)
437{
438 if (tq->tx_ring.base) {
439 pci_free_consistent(adapter->pdev, tq->tx_ring.size *
440 sizeof(struct Vmxnet3_TxDesc),
441 tq->tx_ring.base, tq->tx_ring.basePA);
442 tq->tx_ring.base = NULL;
443 }
444 if (tq->data_ring.base) {
445 pci_free_consistent(adapter->pdev, tq->data_ring.size *
446 sizeof(struct Vmxnet3_TxDataDesc),
447 tq->data_ring.base, tq->data_ring.basePA);
448 tq->data_ring.base = NULL;
449 }
450 if (tq->comp_ring.base) {
451 pci_free_consistent(adapter->pdev, tq->comp_ring.size *
452 sizeof(struct Vmxnet3_TxCompDesc),
453 tq->comp_ring.base, tq->comp_ring.basePA);
454 tq->comp_ring.base = NULL;
455 }
456 kfree(tq->buf_info);
457 tq->buf_info = NULL;
458}
459
460
09c5088e
SB		 461/* Destroy all tx queues */
462void
463vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
464{
465 int i;
466
467 for (i = 0; i < adapter->num_tx_queues; i++)
468 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
469}
470
471
d1a890fa
SB		 472static void
473vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
474 struct vmxnet3_adapter *adapter)
475{
476 int i;
477
478 /* reset the tx ring contents to 0 and reset the tx ring states */
479 memset(tq->tx_ring.base, 0, tq->tx_ring.size *
480 sizeof(struct Vmxnet3_TxDesc));
481 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
482 tq->tx_ring.gen = VMXNET3_INIT_GEN;
483
484 memset(tq->data_ring.base, 0, tq->data_ring.size *
485 sizeof(struct Vmxnet3_TxDataDesc));
486
487 /* reset the tx comp ring contents to 0 and reset comp ring states */
488 memset(tq->comp_ring.base, 0, tq->comp_ring.size *
489 sizeof(struct Vmxnet3_TxCompDesc));
490 tq->comp_ring.next2proc = 0;
491 tq->comp_ring.gen = VMXNET3_INIT_GEN;
492
493 /* reset the bookkeeping data */
494 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
495 for (i = 0; i < tq->tx_ring.size; i++)
496 tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
497
498 /* stats are not reset */
499}
500
501
502static int
503vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
504 struct vmxnet3_adapter *adapter)
505{
506 BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
507 tq->comp_ring.base || tq->buf_info);
508
509 tq->tx_ring.base = pci_alloc_consistent(adapter->pdev, tq->tx_ring.size
510 * sizeof(struct Vmxnet3_TxDesc),
511 &tq->tx_ring.basePA);
512 if (!tq->tx_ring.base) {
513 printk(KERN_ERR "%s: failed to allocate tx ring\n",
514 adapter->netdev->name);
515 goto err;
516 }
517
518 tq->data_ring.base = pci_alloc_consistent(adapter->pdev,
519 tq->data_ring.size *
520 sizeof(struct Vmxnet3_TxDataDesc),
521 &tq->data_ring.basePA);
522 if (!tq->data_ring.base) {
523 printk(KERN_ERR "%s: failed to allocate data ring\n",
524 adapter->netdev->name);
525 goto err;
526 }
527
528 tq->comp_ring.base = pci_alloc_consistent(adapter->pdev,
529 tq->comp_ring.size *
530 sizeof(struct Vmxnet3_TxCompDesc),
531 &tq->comp_ring.basePA);
532 if (!tq->comp_ring.base) {
533 printk(KERN_ERR "%s: failed to allocate tx comp ring\n",
534 adapter->netdev->name);
535 goto err;
536 }
537
538 tq->buf_info = kcalloc(tq->tx_ring.size, sizeof(tq->buf_info[0]),
539 GFP_KERNEL);
e404decb 540 if (!tq->buf_info)
d1a890fa 541 goto err;
d1a890fa
SB		 542
543 return 0;
544
545err:
546 vmxnet3_tq_destroy(tq, adapter);
547 return -ENOMEM;
548}
549
09c5088e
SB		 550static void
551vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
552{
553 int i;
554
555 for (i = 0; i < adapter->num_tx_queues; i++)
556 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
557}
d1a890fa
SB		 558
559/*
560 * starting from ring->next2fill, allocate rx buffers for the given ring
561 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers
562 * are allocated or allocation fails
563 */
564
565static int
566vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
567 int num_to_alloc, struct vmxnet3_adapter *adapter)
568{
569 int num_allocated = 0;
570 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
571 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
572 u32 val;
573
5318d809 574 while (num_allocated <= num_to_alloc) {
d1a890fa
SB		 575 struct vmxnet3_rx_buf_info *rbi;
576 union Vmxnet3_GenericDesc *gd;
577
578 rbi = rbi_base + ring->next2fill;
579 gd = ring->base + ring->next2fill;
580
581 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
582 if (rbi->skb == NULL) {
583 rbi->skb = dev_alloc_skb(rbi->len +
584 NET_IP_ALIGN);
585 if (unlikely(rbi->skb == NULL)) {
586 rq->stats.rx_buf_alloc_failure++;
587 break;
588 }
589 rbi->skb->dev = adapter->netdev;
590
591 skb_reserve(rbi->skb, NET_IP_ALIGN);
592 rbi->dma_addr = pci_map_single(adapter->pdev,
593 rbi->skb->data, rbi->len,
594 PCI_DMA_FROMDEVICE);
595 } else {
596 /* rx buffer skipped by the device */
597 }
598 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
599 } else {
600 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
601 rbi->len != PAGE_SIZE);
602
603 if (rbi->page == NULL) {
604 rbi->page = alloc_page(GFP_ATOMIC);
605 if (unlikely(rbi->page == NULL)) {
606 rq->stats.rx_buf_alloc_failure++;
607 break;
608 }
609 rbi->dma_addr = pci_map_page(adapter->pdev,
610 rbi->page, 0, PAGE_SIZE,
611 PCI_DMA_FROMDEVICE);
612 } else {
613 /* rx buffers skipped by the device */
614 }
615 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
616 }
617
618 BUG_ON(rbi->dma_addr == 0);
115924b6 619 gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
5318d809 620 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT)
115924b6 621 | val | rbi->len);
d1a890fa 622
5318d809
SB		 623 /* Fill the last buffer but dont mark it ready, or else the
624 * device will think that the queue is full */
625 if (num_allocated == num_to_alloc)
626 break;
627
628 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT);
d1a890fa
SB		 629 num_allocated++;
630 vmxnet3_cmd_ring_adv_next2fill(ring);
631 }
632 rq->uncommitted[ring_idx] += num_allocated;
633
f6965582
RD		 634 dev_dbg(&adapter->netdev->dev,
635 "alloc_rx_buf: %d allocated, next2fill %u, next2comp "
c3ca881f 636 "%u, uncommitted %u\n", num_allocated, ring->next2fill,
d1a890fa
SB		 637 ring->next2comp, rq->uncommitted[ring_idx]);
638
639 /* so that the device can distinguish a full ring and an empty ring */
640 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
641
642 return num_allocated;
643}
644
645
646static void
647vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
648 struct vmxnet3_rx_buf_info *rbi)
649{
650 struct skb_frag_struct *frag = skb_shinfo(skb)->frags +
651 skb_shinfo(skb)->nr_frags;
652
653 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
654
0e0634d2 655 __skb_frag_set_page(frag, rbi->page);
d1a890fa 656 frag->page_offset = 0;
9e903e08
ED		 657 skb_frag_size_set(frag, rcd->len);
658 skb->data_len += rcd->len;
5e6c355c 659 skb->truesize += PAGE_SIZE;
d1a890fa
SB		 660 skb_shinfo(skb)->nr_frags++;
661}
662
663
664static void
665vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
666 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
667 struct vmxnet3_adapter *adapter)
668{
669 u32 dw2, len;
670 unsigned long buf_offset;
671 int i;
672 union Vmxnet3_GenericDesc *gdesc;
673 struct vmxnet3_tx_buf_info *tbi = NULL;
674
675 BUG_ON(ctx->copy_size > skb_headlen(skb));
676
677 /* use the previous gen bit for the SOP desc */
678 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
679
680 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
681 gdesc = ctx->sop_txd; /* both loops below can be skipped */
682
683 /* no need to map the buffer if headers are copied */
684 if (ctx->copy_size) {
115924b6 685 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
d1a890fa 686 tq->tx_ring.next2fill *
115924b6
SB		 687 sizeof(struct Vmxnet3_TxDataDesc));
688 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
d1a890fa
SB		 689 ctx->sop_txd->dword[3] = 0;
690
691 tbi = tq->buf_info + tq->tx_ring.next2fill;
692 tbi->map_type = VMXNET3_MAP_NONE;
693
f6965582
RD		 694 dev_dbg(&adapter->netdev->dev,
695 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
115924b6
SB		 696 tq->tx_ring.next2fill,
697 le64_to_cpu(ctx->sop_txd->txd.addr),
d1a890fa
SB		 698 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
699 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
700
701 /* use the right gen for non-SOP desc */
702 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
703 }
704
705 /* linear part can use multiple tx desc if it's big */
706 len = skb_headlen(skb) - ctx->copy_size;
707 buf_offset = ctx->copy_size;
708 while (len) {
709 u32 buf_size;
710
1f4b1612
BD		 711 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
712 buf_size = len;
713 dw2 |= len;
714 } else {
715 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
716 /* spec says that for TxDesc.len, 0 == 2^14 */
717 }
d1a890fa
SB		 718
719 tbi = tq->buf_info + tq->tx_ring.next2fill;
720 tbi->map_type = VMXNET3_MAP_SINGLE;
721 tbi->dma_addr = pci_map_single(adapter->pdev,
722 skb->data + buf_offset, buf_size,
723 PCI_DMA_TODEVICE);
724
1f4b1612 725 tbi->len = buf_size;
d1a890fa
SB		 726
727 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
728 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
729
115924b6 730 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
1f4b1612 731 gdesc->dword[2] = cpu_to_le32(dw2);
d1a890fa
SB		 732 gdesc->dword[3] = 0;
733
f6965582
RD		 734 dev_dbg(&adapter->netdev->dev,
735 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
115924b6
SB		 736 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
737 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
d1a890fa
SB		 738 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
739 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
740
741 len -= buf_size;
742 buf_offset += buf_size;
743 }
744
745 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
9e903e08 746 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
a4d7e485 747 u32 buf_size;
d1a890fa 748
a4d7e485
ED		 749 buf_offset = 0;
750 len = skb_frag_size(frag);
751 while (len) {
752 tbi = tq->buf_info + tq->tx_ring.next2fill;
753 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
754 buf_size = len;
755 dw2 |= len;
756 } else {
757 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
758 /* spec says that for TxDesc.len, 0 == 2^14 */
759 }
760 tbi->map_type = VMXNET3_MAP_PAGE;
761 tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag,
762 buf_offset, buf_size,
763 DMA_TO_DEVICE);
d1a890fa 764
a4d7e485 765 tbi->len = buf_size;
d1a890fa 766
a4d7e485
ED		 767 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
768 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
d1a890fa 769
a4d7e485
ED		 770 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
771 gdesc->dword[2] = cpu_to_le32(dw2);
772 gdesc->dword[3] = 0;
d1a890fa 773
a4d7e485
ED		 774 dev_dbg(&adapter->netdev->dev,
775 "txd[%u]: 0x%llu %u %u\n",
776 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
777 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
778 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
779 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
780
781 len -= buf_size;
782 buf_offset += buf_size;
783 }
d1a890fa
SB		 784 }
785
786 ctx->eop_txd = gdesc;
787
788 /* set the last buf_info for the pkt */
789 tbi->skb = skb;
790 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
791}
792
793
09c5088e
SB		 794/* Init all tx queues */
795static void
796vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
797{
798 int i;
799
800 for (i = 0; i < adapter->num_tx_queues; i++)
801 vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
802}
803
804
d1a890fa
SB		 805/*
806 * parse and copy relevant protocol headers:
807 * For a tso pkt, relevant headers are L2/3/4 including options
808 * For a pkt requesting csum offloading, they are L2/3 and may include L4
809 * if it's a TCP/UDP pkt
810 *
811 * Returns:
812 * -1: error happens during parsing
813 * 0: protocol headers parsed, but too big to be copied
814 * 1: protocol headers parsed and copied
815 *
816 * Other effects:
817 * 1. related *ctx fields are updated.
818 * 2. ctx->copy_size is # of bytes copied
819 * 3. the portion copied is guaranteed to be in the linear part
820 *
821 */
822static int
823vmxnet3_parse_and_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
824 struct vmxnet3_tx_ctx *ctx,
825 struct vmxnet3_adapter *adapter)
826{
827 struct Vmxnet3_TxDataDesc *tdd;
828
0d0b1672 829 if (ctx->mss) { /* TSO */
d1a890fa 830 ctx->eth_ip_hdr_size = skb_transport_offset(skb);
8bca5d1e 831 ctx->l4_hdr_size = tcp_hdrlen(skb);
d1a890fa
SB		 832 ctx->copy_size = ctx->eth_ip_hdr_size + ctx->l4_hdr_size;
833 } else {
d1a890fa 834 if (skb->ip_summed == CHECKSUM_PARTIAL) {
0d0b1672 835 ctx->eth_ip_hdr_size = skb_checksum_start_offset(skb);
d1a890fa
SB		 836
837 if (ctx->ipv4) {
8bca5d1e
ED		 838 const struct iphdr *iph = ip_hdr(skb);
839
39d4a96f 840 if (iph->protocol == IPPROTO_TCP)
8bca5d1e 841 ctx->l4_hdr_size = tcp_hdrlen(skb);
39d4a96f 842 else if (iph->protocol == IPPROTO_UDP)
f6a1ad42 843 ctx->l4_hdr_size = sizeof(struct udphdr);
39d4a96f 844 else
d1a890fa 845 ctx->l4_hdr_size = 0;
d1a890fa
SB		 846 } else {
847 /* for simplicity, don't copy L4 headers */
848 ctx->l4_hdr_size = 0;
849 }
b203262d
NH		 850 ctx->copy_size = min(ctx->eth_ip_hdr_size +
851 ctx->l4_hdr_size, skb->len);
d1a890fa
SB		 852 } else {
853 ctx->eth_ip_hdr_size = 0;
854 ctx->l4_hdr_size = 0;
855 /* copy as much as allowed */
856 ctx->copy_size = min((unsigned int)VMXNET3_HDR_COPY_SIZE
857 , skb_headlen(skb));
858 }
859
860 /* make sure headers are accessible directly */
861 if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
862 goto err;
863 }
864
865 if (unlikely(ctx->copy_size > VMXNET3_HDR_COPY_SIZE)) {
866 tq->stats.oversized_hdr++;
867 ctx->copy_size = 0;
868 return 0;
869 }
870
871 tdd = tq->data_ring.base + tq->tx_ring.next2fill;
872
873 memcpy(tdd->data, skb->data, ctx->copy_size);
f6965582
RD		 874 dev_dbg(&adapter->netdev->dev,
875 "copy %u bytes to dataRing[%u]\n",
d1a890fa
SB		 876 ctx->copy_size, tq->tx_ring.next2fill);
877 return 1;
878
879err:
880 return -1;
881}
882
883
884static void
885vmxnet3_prepare_tso(struct sk_buff *skb,
886 struct vmxnet3_tx_ctx *ctx)
887{
8bca5d1e
ED		 888 struct tcphdr *tcph = tcp_hdr(skb);
889
d1a890fa 890 if (ctx->ipv4) {
8bca5d1e
ED		 891 struct iphdr *iph = ip_hdr(skb);
892
d1a890fa
SB		 893 iph->check = 0;
894 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
895 IPPROTO_TCP, 0);
896 } else {
8bca5d1e
ED		 897 struct ipv6hdr *iph = ipv6_hdr(skb);
898
d1a890fa
SB		 899 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
900 IPPROTO_TCP, 0);
901 }
902}
903
a4d7e485
ED		 904static int txd_estimate(const struct sk_buff *skb)
905{
906 int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
907 int i;
908
909 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
910 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
911
912 count += VMXNET3_TXD_NEEDED(skb_frag_size(frag));
913 }
914 return count;
915}
d1a890fa
SB		 916
917/*
918 * Transmits a pkt thru a given tq
919 * Returns:
920 * NETDEV_TX_OK: descriptors are setup successfully
25985edc 921 * NETDEV_TX_OK: error occurred, the pkt is dropped
d1a890fa
SB		 922 * NETDEV_TX_BUSY: tx ring is full, queue is stopped
923 *
924 * Side-effects:
925 * 1. tx ring may be changed
926 * 2. tq stats may be updated accordingly
927 * 3. shared->txNumDeferred may be updated
928 */
929
930static int
931vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
932 struct vmxnet3_adapter *adapter, struct net_device *netdev)
933{
934 int ret;
935 u32 count;
936 unsigned long flags;
937 struct vmxnet3_tx_ctx ctx;
938 union Vmxnet3_GenericDesc *gdesc;
115924b6
SB		 939#ifdef __BIG_ENDIAN_BITFIELD
940 /* Use temporary descriptor to avoid touching bits multiple times */
941 union Vmxnet3_GenericDesc tempTxDesc;
942#endif
d1a890fa 943
a4d7e485 944 count = txd_estimate(skb);
d1a890fa 945
72e85c45 946 ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP));
d1a890fa
SB		 947
948 ctx.mss = skb_shinfo(skb)->gso_size;
949 if (ctx.mss) {
950 if (skb_header_cloned(skb)) {
951 if (unlikely(pskb_expand_head(skb, 0, 0,
952 GFP_ATOMIC) != 0)) {
953 tq->stats.drop_tso++;
954 goto drop_pkt;
955 }
956 tq->stats.copy_skb_header++;
957 }
958 vmxnet3_prepare_tso(skb, &ctx);
959 } else {
960 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
961
962 /* non-tso pkts must not use more than
963 * VMXNET3_MAX_TXD_PER_PKT entries
964 */
965 if (skb_linearize(skb) != 0) {
966 tq->stats.drop_too_many_frags++;
967 goto drop_pkt;
968 }
969 tq->stats.linearized++;
970
971 /* recalculate the # of descriptors to use */
972 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
973 }
974 }
975
09c5088e
SB		 976 spin_lock_irqsave(&tq->tx_lock, flags);
977
978 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
979 tq->stats.tx_ring_full++;
980 dev_dbg(&adapter->netdev->dev,
981 "tx queue stopped on %s, next2comp %u"
982 " next2fill %u\n", adapter->netdev->name,
983 tq->tx_ring.next2comp, tq->tx_ring.next2fill);
984
985 vmxnet3_tq_stop(tq, adapter);
986 spin_unlock_irqrestore(&tq->tx_lock, flags);
987 return NETDEV_TX_BUSY;
988 }
989
990
d1a890fa
SB		 991 ret = vmxnet3_parse_and_copy_hdr(skb, tq, &ctx, adapter);
992 if (ret >= 0) {
993 BUG_ON(ret <= 0 && ctx.copy_size != 0);
994 /* hdrs parsed, check against other limits */
995 if (ctx.mss) {
996 if (unlikely(ctx.eth_ip_hdr_size + ctx.l4_hdr_size >
997 VMXNET3_MAX_TX_BUF_SIZE)) {
998 goto hdr_too_big;
999 }
1000 } else {
1001 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1002 if (unlikely(ctx.eth_ip_hdr_size +
1003 skb->csum_offset >
1004 VMXNET3_MAX_CSUM_OFFSET)) {
1005 goto hdr_too_big;
1006 }
1007 }
1008 }
1009 } else {
1010 tq->stats.drop_hdr_inspect_err++;
f955e141 1011 goto unlock_drop_pkt;
d1a890fa
SB		 1012 }
1013
d1a890fa
SB		 1014 /* fill tx descs related to addr & len */
1015 vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter);
1016
1017 /* setup the EOP desc */
115924b6 1018 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
d1a890fa
SB		 1019
1020 /* setup the SOP desc */
115924b6
SB		 1021#ifdef __BIG_ENDIAN_BITFIELD
1022 gdesc = &tempTxDesc;
1023 gdesc->dword[2] = ctx.sop_txd->dword[2];
1024 gdesc->dword[3] = ctx.sop_txd->dword[3];
1025#else
d1a890fa 1026 gdesc = ctx.sop_txd;
115924b6 1027#endif
d1a890fa
SB		 1028 if (ctx.mss) {
1029 gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size;
1030 gdesc->txd.om = VMXNET3_OM_TSO;
1031 gdesc->txd.msscof = ctx.mss;
115924b6
SB		 1032 le32_add_cpu(&tq->shared->txNumDeferred, (skb->len -
1033 gdesc->txd.hlen + ctx.mss - 1) / ctx.mss);
d1a890fa
SB		 1034 } else {
1035 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1036 gdesc->txd.hlen = ctx.eth_ip_hdr_size;
1037 gdesc->txd.om = VMXNET3_OM_CSUM;
1038 gdesc->txd.msscof = ctx.eth_ip_hdr_size +
1039 skb->csum_offset;
1040 } else {
1041 gdesc->txd.om = 0;
1042 gdesc->txd.msscof = 0;
1043 }
115924b6 1044 le32_add_cpu(&tq->shared->txNumDeferred, 1);
d1a890fa
SB		 1045 }
1046
1047 if (vlan_tx_tag_present(skb)) {
1048 gdesc->txd.ti = 1;
1049 gdesc->txd.tci = vlan_tx_tag_get(skb);
1050 }
1051
115924b6
SB		 1052 /* finally flips the GEN bit of the SOP desc. */
1053 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
1054 VMXNET3_TXD_GEN);
1055#ifdef __BIG_ENDIAN_BITFIELD
1056 /* Finished updating in bitfields of Tx Desc, so write them in original
1057 * place.
1058 */
1059 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
1060 (struct Vmxnet3_TxDesc *)ctx.sop_txd);
1061 gdesc = ctx.sop_txd;
1062#endif
f6965582
RD		 1063 dev_dbg(&adapter->netdev->dev,
1064 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
c2fd03a0 1065 (u32)(ctx.sop_txd -
115924b6
SB		 1066 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
1067 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
d1a890fa
SB		 1068
1069 spin_unlock_irqrestore(&tq->tx_lock, flags);
1070
115924b6
SB		 1071 if (le32_to_cpu(tq->shared->txNumDeferred) >=
1072 le32_to_cpu(tq->shared->txThreshold)) {
d1a890fa 1073 tq->shared->txNumDeferred = 0;
09c5088e
SB		 1074 VMXNET3_WRITE_BAR0_REG(adapter,
1075 VMXNET3_REG_TXPROD + tq->qid * 8,
d1a890fa
SB		 1076 tq->tx_ring.next2fill);
1077 }
d1a890fa
SB		 1078
1079 return NETDEV_TX_OK;
1080
1081hdr_too_big:
1082 tq->stats.drop_oversized_hdr++;
f955e141
DC		 1083unlock_drop_pkt:
1084 spin_unlock_irqrestore(&tq->tx_lock, flags);
d1a890fa
SB		 1085drop_pkt:
1086 tq->stats.drop_total++;
1087 dev_kfree_skb(skb);
1088 return NETDEV_TX_OK;
1089}
1090
1091
1092static netdev_tx_t
1093vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1094{
1095 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 1096
96800ee7 1097 BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
1098 return vmxnet3_tq_xmit(skb,
1099 &adapter->tx_queue[skb->queue_mapping],
1100 adapter, netdev);
d1a890fa
SB		 1101}
1102
1103
1104static void
1105vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
1106 struct sk_buff *skb,
1107 union Vmxnet3_GenericDesc *gdesc)
1108{
a0d2730c 1109 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) {
d1a890fa 1110 /* typical case: TCP/UDP over IP and both csums are correct */
115924b6 1111 if ((le32_to_cpu(gdesc->dword[3]) & VMXNET3_RCD_CSUM_OK) ==
d1a890fa
SB		 1112 VMXNET3_RCD_CSUM_OK) {
1113 skb->ip_summed = CHECKSUM_UNNECESSARY;
1114 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp));
1115 BUG_ON(!(gdesc->rcd.v4 || gdesc->rcd.v6));
1116 BUG_ON(gdesc->rcd.frg);
1117 } else {
1118 if (gdesc->rcd.csum) {
1119 skb->csum = htons(gdesc->rcd.csum);
1120 skb->ip_summed = CHECKSUM_PARTIAL;
1121 } else {
bc8acf2c 1122 skb_checksum_none_assert(skb);
d1a890fa
SB		 1123 }
1124 }
1125 } else {
bc8acf2c 1126 skb_checksum_none_assert(skb);
d1a890fa
SB		 1127 }
1128}
1129
1130
1131static void
1132vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
1133 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter)
1134{
1135 rq->stats.drop_err++;
1136 if (!rcd->fcs)
1137 rq->stats.drop_fcs++;
1138
1139 rq->stats.drop_total++;
1140
1141 /*
1142 * We do not unmap and chain the rx buffer to the skb.
1143 * We basically pretend this buffer is not used and will be recycled
1144 * by vmxnet3_rq_alloc_rx_buf()
1145 */
1146
1147 /*
1148 * ctx->skb may be NULL if this is the first and the only one
1149 * desc for the pkt
1150 */
1151 if (ctx->skb)
1152 dev_kfree_skb_irq(ctx->skb);
1153
1154 ctx->skb = NULL;
1155}
1156
1157
1158static int
1159vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
1160 struct vmxnet3_adapter *adapter, int quota)
1161{
215faf9c
JP		 1162 static const u32 rxprod_reg[2] = {
1163 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2
1164 };
d1a890fa 1165 u32 num_rxd = 0;
5318d809 1166 bool skip_page_frags = false;
d1a890fa
SB		 1167 struct Vmxnet3_RxCompDesc *rcd;
1168 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
115924b6
SB		 1169#ifdef __BIG_ENDIAN_BITFIELD
1170 struct Vmxnet3_RxDesc rxCmdDesc;
1171 struct Vmxnet3_RxCompDesc rxComp;
1172#endif
1173 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
1174 &rxComp);
d1a890fa
SB		 1175 while (rcd->gen == rq->comp_ring.gen) {
1176 struct vmxnet3_rx_buf_info *rbi;
5318d809
SB		 1177 struct sk_buff *skb, *new_skb = NULL;
1178 struct page *new_page = NULL;
d1a890fa
SB		 1179 int num_to_alloc;
1180 struct Vmxnet3_RxDesc *rxd;
1181 u32 idx, ring_idx;
5318d809 1182 struct vmxnet3_cmd_ring *ring = NULL;
d1a890fa
SB		 1183 if (num_rxd >= quota) {
1184 /* we may stop even before we see the EOP desc of
1185 * the current pkt
1186 */
1187 break;
1188 }
1189 num_rxd++;
09c5088e 1190 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2);
d1a890fa 1191 idx = rcd->rxdIdx;
09c5088e 1192 ring_idx = rcd->rqID < adapter->num_rx_queues ? 0 : 1;
5318d809 1193 ring = rq->rx_ring + ring_idx;
115924b6
SB		 1194 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
1195 &rxCmdDesc);
d1a890fa
SB		 1196 rbi = rq->buf_info[ring_idx] + idx;
1197
115924b6
SB		 1198 BUG_ON(rxd->addr != rbi->dma_addr ||
1199 rxd->len != rbi->len);
d1a890fa
SB		 1200
1201 if (unlikely(rcd->eop && rcd->err)) {
1202 vmxnet3_rx_error(rq, rcd, ctx, adapter);
1203 goto rcd_done;
1204 }
1205
1206 if (rcd->sop) { /* first buf of the pkt */
1207 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
1208 rcd->rqID != rq->qid);
1209
1210 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB);
1211 BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
1212
1213 if (unlikely(rcd->len == 0)) {
1214 /* Pretend the rx buffer is skipped. */
1215 BUG_ON(!(rcd->sop && rcd->eop));
f6965582
RD		 1216 dev_dbg(&adapter->netdev->dev,
1217 "rxRing[%u][%u] 0 length\n",
d1a890fa
SB		 1218 ring_idx, idx);
1219 goto rcd_done;
1220 }
1221
5318d809 1222 skip_page_frags = false;
d1a890fa 1223 ctx->skb = rbi->skb;
5318d809
SB		 1224 new_skb = dev_alloc_skb(rbi->len + NET_IP_ALIGN);
1225 if (new_skb == NULL) {
1226 /* Skb allocation failed, do not handover this
1227 * skb to stack. Reuse it. Drop the existing pkt
1228 */
1229 rq->stats.rx_buf_alloc_failure++;
1230 ctx->skb = NULL;
1231 rq->stats.drop_total++;
1232 skip_page_frags = true;
1233 goto rcd_done;
1234 }
d1a890fa
SB		 1235
1236 pci_unmap_single(adapter->pdev, rbi->dma_addr, rbi->len,
1237 PCI_DMA_FROMDEVICE);
1238
1239 skb_put(ctx->skb, rcd->len);
5318d809
SB		 1240
1241 /* Immediate refill */
1242 new_skb->dev = adapter->netdev;
1243 skb_reserve(new_skb, NET_IP_ALIGN);
1244 rbi->skb = new_skb;
1245 rbi->dma_addr = pci_map_single(adapter->pdev,
96800ee7 1246 rbi->skb->data, rbi->len,
1247 PCI_DMA_FROMDEVICE);
5318d809
SB		 1248 rxd->addr = cpu_to_le64(rbi->dma_addr);
1249 rxd->len = rbi->len;
1250
d1a890fa 1251 } else {
5318d809
SB		 1252 BUG_ON(ctx->skb == NULL && !skip_page_frags);
1253
d1a890fa 1254 /* non SOP buffer must be type 1 in most cases */
5318d809
SB		 1255 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE);
1256 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
d1a890fa 1257
5318d809
SB		 1258 /* If an sop buffer was dropped, skip all
1259 * following non-sop fragments. They will be reused.
1260 */
1261 if (skip_page_frags)
1262 goto rcd_done;
d1a890fa 1263
5318d809
SB		 1264 new_page = alloc_page(GFP_ATOMIC);
1265 if (unlikely(new_page == NULL)) {
1266 /* Replacement page frag could not be allocated.
1267 * Reuse this page. Drop the pkt and free the
1268 * skb which contained this page as a frag. Skip
1269 * processing all the following non-sop frags.
d1a890fa 1270 */
5318d809
SB		 1271 rq->stats.rx_buf_alloc_failure++;
1272 dev_kfree_skb(ctx->skb);
1273 ctx->skb = NULL;
1274 skip_page_frags = true;
1275 goto rcd_done;
1276 }
1277
1278 if (rcd->len) {
1279 pci_unmap_page(adapter->pdev,
1280 rbi->dma_addr, rbi->len,
1281 PCI_DMA_FROMDEVICE);
1282
1283 vmxnet3_append_frag(ctx->skb, rcd, rbi);
d1a890fa 1284 }
5318d809
SB		 1285
1286 /* Immediate refill */
1287 rbi->page = new_page;
1288 rbi->dma_addr = pci_map_page(adapter->pdev, rbi->page,
1289 0, PAGE_SIZE,
1290 PCI_DMA_FROMDEVICE);
1291 rxd->addr = cpu_to_le64(rbi->dma_addr);
1292 rxd->len = rbi->len;
d1a890fa
SB		 1293 }
1294
5318d809 1295
d1a890fa
SB		 1296 skb = ctx->skb;
1297 if (rcd->eop) {
1298 skb->len += skb->data_len;
d1a890fa
SB		 1299
1300 vmxnet3_rx_csum(adapter, skb,
1301 (union Vmxnet3_GenericDesc *)rcd);
1302 skb->protocol = eth_type_trans(skb, adapter->netdev);
1303
72e85c45
JG		 1304 if (unlikely(rcd->ts))
1305 __vlan_hwaccel_put_tag(skb, rcd->tci);
1306
213ade8c
JG		 1307 if (adapter->netdev->features & NETIF_F_LRO)
1308 netif_receive_skb(skb);
1309 else
1310 napi_gro_receive(&rq->napi, skb);
d1a890fa 1311
d1a890fa
SB		 1312 ctx->skb = NULL;
1313 }
1314
1315rcd_done:
5318d809
SB		 1316 /* device may have skipped some rx descs */
1317 ring->next2comp = idx;
1318 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring);
1319 ring = rq->rx_ring + ring_idx;
1320 while (num_to_alloc) {
1321 vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd,
1322 &rxCmdDesc);
1323 BUG_ON(!rxd->addr);
1324
1325 /* Recv desc is ready to be used by the device */
1326 rxd->gen = ring->gen;
1327 vmxnet3_cmd_ring_adv_next2fill(ring);
1328 num_to_alloc--;
1329 }
1330
1331 /* if needed, update the register */
1332 if (unlikely(rq->shared->updateRxProd)) {
1333 VMXNET3_WRITE_BAR0_REG(adapter,
96800ee7 1334 rxprod_reg[ring_idx] + rq->qid * 8,
1335 ring->next2fill);
5318d809 1336 rq->uncommitted[ring_idx] = 0;
d1a890fa
SB		 1337 }
1338
1339 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
115924b6 1340 vmxnet3_getRxComp(rcd,
96800ee7 1341 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
d1a890fa
SB		 1342 }
1343
1344 return num_rxd;
1345}
1346
1347
1348static void
1349vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
1350 struct vmxnet3_adapter *adapter)
1351{
1352 u32 i, ring_idx;
1353 struct Vmxnet3_RxDesc *rxd;
1354
1355 for (ring_idx = 0; ring_idx < 2; ring_idx++) {
1356 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
115924b6
SB		 1357#ifdef __BIG_ENDIAN_BITFIELD
1358 struct Vmxnet3_RxDesc rxDesc;
1359#endif
1360 vmxnet3_getRxDesc(rxd,
1361 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
d1a890fa
SB		 1362
1363 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
1364 rq->buf_info[ring_idx][i].skb) {
1365 pci_unmap_single(adapter->pdev, rxd->addr,
1366 rxd->len, PCI_DMA_FROMDEVICE);
1367 dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
1368 rq->buf_info[ring_idx][i].skb = NULL;
1369 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
1370 rq->buf_info[ring_idx][i].page) {
1371 pci_unmap_page(adapter->pdev, rxd->addr,
1372 rxd->len, PCI_DMA_FROMDEVICE);
1373 put_page(rq->buf_info[ring_idx][i].page);
1374 rq->buf_info[ring_idx][i].page = NULL;
1375 }
1376 }
1377
1378 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
1379 rq->rx_ring[ring_idx].next2fill =
1380 rq->rx_ring[ring_idx].next2comp = 0;
1381 rq->uncommitted[ring_idx] = 0;
1382 }
1383
1384 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1385 rq->comp_ring.next2proc = 0;
1386}
1387
1388
09c5088e
SB		 1389static void
1390vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
1391{
1392 int i;
1393
1394 for (i = 0; i < adapter->num_rx_queues; i++)
1395 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
1396}
1397
1398
d1a890fa
SB		 1399void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
1400 struct vmxnet3_adapter *adapter)
1401{
1402 int i;
1403 int j;
1404
1405 /* all rx buffers must have already been freed */
1406 for (i = 0; i < 2; i++) {
1407 if (rq->buf_info[i]) {
1408 for (j = 0; j < rq->rx_ring[i].size; j++)
1409 BUG_ON(rq->buf_info[i][j].page != NULL);
1410 }
1411 }
1412
1413
1414 kfree(rq->buf_info[0]);
1415
1416 for (i = 0; i < 2; i++) {
1417 if (rq->rx_ring[i].base) {
1418 pci_free_consistent(adapter->pdev, rq->rx_ring[i].size
1419 * sizeof(struct Vmxnet3_RxDesc),
1420 rq->rx_ring[i].base,
1421 rq->rx_ring[i].basePA);
1422 rq->rx_ring[i].base = NULL;
1423 }
1424 rq->buf_info[i] = NULL;
1425 }
1426
1427 if (rq->comp_ring.base) {
1428 pci_free_consistent(adapter->pdev, rq->comp_ring.size *
1429 sizeof(struct Vmxnet3_RxCompDesc),
1430 rq->comp_ring.base, rq->comp_ring.basePA);
1431 rq->comp_ring.base = NULL;
1432 }
1433}
1434
1435
1436static int
1437vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
1438 struct vmxnet3_adapter *adapter)
1439{
1440 int i;
1441
1442 /* initialize buf_info */
1443 for (i = 0; i < rq->rx_ring[0].size; i++) {
1444
1445 /* 1st buf for a pkt is skbuff */
1446 if (i % adapter->rx_buf_per_pkt == 0) {
1447 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB;
1448 rq->buf_info[0][i].len = adapter->skb_buf_size;
1449 } else { /* subsequent bufs for a pkt is frag */
1450 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
1451 rq->buf_info[0][i].len = PAGE_SIZE;
1452 }
1453 }
1454 for (i = 0; i < rq->rx_ring[1].size; i++) {
1455 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
1456 rq->buf_info[1][i].len = PAGE_SIZE;
1457 }
1458
1459 /* reset internal state and allocate buffers for both rings */
1460 for (i = 0; i < 2; i++) {
1461 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
1462 rq->uncommitted[i] = 0;
1463
1464 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
1465 sizeof(struct Vmxnet3_RxDesc));
1466 rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
1467 }
1468 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
1469 adapter) == 0) {
1470 /* at least has 1 rx buffer for the 1st ring */
1471 return -ENOMEM;
1472 }
1473 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
1474
1475 /* reset the comp ring */
1476 rq->comp_ring.next2proc = 0;
1477 memset(rq->comp_ring.base, 0, rq->comp_ring.size *
1478 sizeof(struct Vmxnet3_RxCompDesc));
1479 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1480
1481 /* reset rxctx */
1482 rq->rx_ctx.skb = NULL;
1483
1484 /* stats are not reset */
1485 return 0;
1486}
1487
1488
09c5088e
SB		 1489static int
1490vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
1491{
1492 int i, err = 0;
1493
1494 for (i = 0; i < adapter->num_rx_queues; i++) {
1495 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
1496 if (unlikely(err)) {
1497 dev_err(&adapter->netdev->dev, "%s: failed to "
1498 "initialize rx queue%i\n",
1499 adapter->netdev->name, i);
1500 break;
1501 }
1502 }
1503 return err;
1504
1505}
1506
1507
d1a890fa
SB		 1508static int
1509vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
1510{
1511 int i;
1512 size_t sz;
1513 struct vmxnet3_rx_buf_info *bi;
1514
1515 for (i = 0; i < 2; i++) {
1516
1517 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
1518 rq->rx_ring[i].base = pci_alloc_consistent(adapter->pdev, sz,
1519 &rq->rx_ring[i].basePA);
1520 if (!rq->rx_ring[i].base) {
1521 printk(KERN_ERR "%s: failed to allocate rx ring %d\n",
1522 adapter->netdev->name, i);
1523 goto err;
1524 }
1525 }
1526
1527 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
1528 rq->comp_ring.base = pci_alloc_consistent(adapter->pdev, sz,
1529 &rq->comp_ring.basePA);
1530 if (!rq->comp_ring.base) {
1531 printk(KERN_ERR "%s: failed to allocate rx comp ring\n",
1532 adapter->netdev->name);
1533 goto err;
1534 }
1535
1536 sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size +
1537 rq->rx_ring[1].size);
476c609e 1538 bi = kzalloc(sz, GFP_KERNEL);
e404decb 1539 if (!bi)
d1a890fa 1540 goto err;
e404decb 1541
d1a890fa
SB		 1542 rq->buf_info[0] = bi;
1543 rq->buf_info[1] = bi + rq->rx_ring[0].size;
1544
1545 return 0;
1546
1547err:
1548 vmxnet3_rq_destroy(rq, adapter);
1549 return -ENOMEM;
1550}
1551
1552
09c5088e
SB		 1553static int
1554vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
1555{
1556 int i, err = 0;
1557
1558 for (i = 0; i < adapter->num_rx_queues; i++) {
1559 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
1560 if (unlikely(err)) {
1561 dev_err(&adapter->netdev->dev,
1562 "%s: failed to create rx queue%i\n",
1563 adapter->netdev->name, i);
1564 goto err_out;
1565 }
1566 }
1567 return err;
1568err_out:
1569 vmxnet3_rq_destroy_all(adapter);
1570 return err;
1571
1572}
1573
1574/* Multiple queue aware polling function for tx and rx */
1575
d1a890fa
SB		 1576static int
1577vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
1578{
09c5088e 1579 int rcd_done = 0, i;
d1a890fa
SB		 1580 if (unlikely(adapter->shared->ecr))
1581 vmxnet3_process_events(adapter);
09c5088e
SB		 1582 for (i = 0; i < adapter->num_tx_queues; i++)
1583 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
d1a890fa 1584
09c5088e
SB		 1585 for (i = 0; i < adapter->num_rx_queues; i++)
1586 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
1587 adapter, budget);
1588 return rcd_done;
d1a890fa
SB		 1589}
1590
1591
1592static int
1593vmxnet3_poll(struct napi_struct *napi, int budget)
1594{
09c5088e
SB		 1595 struct vmxnet3_rx_queue *rx_queue = container_of(napi,
1596 struct vmxnet3_rx_queue, napi);
1597 int rxd_done;
1598
1599 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
1600
1601 if (rxd_done < budget) {
1602 napi_complete(napi);
1603 vmxnet3_enable_all_intrs(rx_queue->adapter);
1604 }
1605 return rxd_done;
1606}
1607
1608/*
1609 * NAPI polling function for MSI-X mode with multiple Rx queues
1610 * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
1611 */
1612
1613static int
1614vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
1615{
1616 struct vmxnet3_rx_queue *rq = container_of(napi,
1617 struct vmxnet3_rx_queue, napi);
1618 struct vmxnet3_adapter *adapter = rq->adapter;
d1a890fa
SB		 1619 int rxd_done;
1620
09c5088e
SB		 1621 /* When sharing interrupt with corresponding tx queue, process
1622 * tx completions in that queue as well
1623 */
1624 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
1625 struct vmxnet3_tx_queue *tq =
1626 &adapter->tx_queue[rq - adapter->rx_queue];
1627 vmxnet3_tq_tx_complete(tq, adapter);
1628 }
1629
1630 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
d1a890fa
SB		 1631
1632 if (rxd_done < budget) {
1633 napi_complete(napi);
09c5088e 1634 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
d1a890fa
SB		 1635 }
1636 return rxd_done;
1637}
1638
1639
09c5088e
SB		 1640#ifdef CONFIG_PCI_MSI
1641
1642/*
1643 * Handle completion interrupts on tx queues
1644 * Returns whether or not the intr is handled
1645 */
1646
1647static irqreturn_t
1648vmxnet3_msix_tx(int irq, void *data)
1649{
1650 struct vmxnet3_tx_queue *tq = data;
1651 struct vmxnet3_adapter *adapter = tq->adapter;
1652
1653 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1654 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
1655
1656 /* Handle the case where only one irq is allocate for all tx queues */
1657 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
1658 int i;
1659 for (i = 0; i < adapter->num_tx_queues; i++) {
1660 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
1661 vmxnet3_tq_tx_complete(txq, adapter);
1662 }
1663 } else {
1664 vmxnet3_tq_tx_complete(tq, adapter);
1665 }
1666 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
1667
1668 return IRQ_HANDLED;
1669}
1670
1671
1672/*
1673 * Handle completion interrupts on rx queues. Returns whether or not the
1674 * intr is handled
1675 */
1676
1677static irqreturn_t
1678vmxnet3_msix_rx(int irq, void *data)
1679{
1680 struct vmxnet3_rx_queue *rq = data;
1681 struct vmxnet3_adapter *adapter = rq->adapter;
1682
1683 /* disable intr if needed */
1684 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1685 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
1686 napi_schedule(&rq->napi);
1687
1688 return IRQ_HANDLED;
1689}
1690
1691/*
1692 *----------------------------------------------------------------------------
1693 *
1694 * vmxnet3_msix_event --
1695 *
1696 * vmxnet3 msix event intr handler
1697 *
1698 * Result:
1699 * whether or not the intr is handled
1700 *
1701 *----------------------------------------------------------------------------
1702 */
1703
1704static irqreturn_t
1705vmxnet3_msix_event(int irq, void *data)
1706{
1707 struct net_device *dev = data;
1708 struct vmxnet3_adapter *adapter = netdev_priv(dev);
1709
1710 /* disable intr if needed */
1711 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1712 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
1713
1714 if (adapter->shared->ecr)
1715 vmxnet3_process_events(adapter);
1716
1717 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
1718
1719 return IRQ_HANDLED;
1720}
1721
1722#endif /* CONFIG_PCI_MSI */
1723
1724
d1a890fa
SB		 1725/* Interrupt handler for vmxnet3 */
1726static irqreturn_t
1727vmxnet3_intr(int irq, void *dev_id)
1728{
1729 struct net_device *dev = dev_id;
1730 struct vmxnet3_adapter *adapter = netdev_priv(dev);
1731
09c5088e 1732 if (adapter->intr.type == VMXNET3_IT_INTX) {
d1a890fa
SB		 1733 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
1734 if (unlikely(icr == 0))
1735 /* not ours */
1736 return IRQ_NONE;
1737 }
1738
1739
1740 /* disable intr if needed */
1741 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
09c5088e 1742 vmxnet3_disable_all_intrs(adapter);
d1a890fa 1743
09c5088e 1744 napi_schedule(&adapter->rx_queue[0].napi);
d1a890fa
SB		 1745
1746 return IRQ_HANDLED;
1747}
1748
1749#ifdef CONFIG_NET_POLL_CONTROLLER
1750
d1a890fa
SB		 1751/* netpoll callback. */
1752static void
1753vmxnet3_netpoll(struct net_device *netdev)
1754{
1755 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 1756
09c5088e
SB		 1757 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1758 vmxnet3_disable_all_intrs(adapter);
1759
1760 vmxnet3_do_poll(adapter, adapter->rx_queue[0].rx_ring[0].size);
1761 vmxnet3_enable_all_intrs(adapter);
d1a890fa 1762
d1a890fa 1763}
09c5088e 1764#endif /* CONFIG_NET_POLL_CONTROLLER */
d1a890fa
SB		 1765
1766static int
1767vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
1768{
09c5088e
SB		 1769 struct vmxnet3_intr *intr = &adapter->intr;
1770 int err = 0, i;
1771 int vector = 0;
d1a890fa 1772
8f7e524c 1773#ifdef CONFIG_PCI_MSI
d1a890fa 1774 if (adapter->intr.type == VMXNET3_IT_MSIX) {
09c5088e
SB		 1775 for (i = 0; i < adapter->num_tx_queues; i++) {
1776 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
1777 sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
1778 adapter->netdev->name, vector);
1779 err = request_irq(
1780 intr->msix_entries[vector].vector,
1781 vmxnet3_msix_tx, 0,
1782 adapter->tx_queue[i].name,
1783 &adapter->tx_queue[i]);
1784 } else {
1785 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
1786 adapter->netdev->name, vector);
1787 }
1788 if (err) {
1789 dev_err(&adapter->netdev->dev,
1790 "Failed to request irq for MSIX, %s, "
1791 "error %d\n",
1792 adapter->tx_queue[i].name, err);
1793 return err;
1794 }
1795
1796 /* Handle the case where only 1 MSIx was allocated for
1797 * all tx queues */
1798 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
1799 for (; i < adapter->num_tx_queues; i++)
1800 adapter->tx_queue[i].comp_ring.intr_idx
1801 = vector;
1802 vector++;
1803 break;
1804 } else {
1805 adapter->tx_queue[i].comp_ring.intr_idx
1806 = vector++;
1807 }
1808 }
1809 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
1810 vector = 0;
1811
1812 for (i = 0; i < adapter->num_rx_queues; i++) {
1813 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
1814 sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
1815 adapter->netdev->name, vector);
1816 else
1817 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
1818 adapter->netdev->name, vector);
1819 err = request_irq(intr->msix_entries[vector].vector,
1820 vmxnet3_msix_rx, 0,
1821 adapter->rx_queue[i].name,
1822 &(adapter->rx_queue[i]));
1823 if (err) {
1824 printk(KERN_ERR "Failed to request irq for MSIX"
1825 ", %s, error %d\n",
1826 adapter->rx_queue[i].name, err);
1827 return err;
1828 }
1829
1830 adapter->rx_queue[i].comp_ring.intr_idx = vector++;
1831 }
1832
1833 sprintf(intr->event_msi_vector_name, "%s-event-%d",
1834 adapter->netdev->name, vector);
1835 err = request_irq(intr->msix_entries[vector].vector,
1836 vmxnet3_msix_event, 0,
1837 intr->event_msi_vector_name, adapter->netdev);
1838 intr->event_intr_idx = vector;
1839
1840 } else if (intr->type == VMXNET3_IT_MSI) {
1841 adapter->num_rx_queues = 1;
d1a890fa
SB		 1842 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
1843 adapter->netdev->name, adapter->netdev);
09c5088e 1844 } else {
115924b6 1845#endif
09c5088e 1846 adapter->num_rx_queues = 1;
d1a890fa
SB		 1847 err = request_irq(adapter->pdev->irq, vmxnet3_intr,
1848 IRQF_SHARED, adapter->netdev->name,
1849 adapter->netdev);
09c5088e 1850#ifdef CONFIG_PCI_MSI
d1a890fa 1851 }
09c5088e
SB		 1852#endif
1853 intr->num_intrs = vector + 1;
1854 if (err) {
d1a890fa 1855 printk(KERN_ERR "Failed to request irq %s (intr type:%d), error"
09c5088e
SB		 1856 ":%d\n", adapter->netdev->name, intr->type, err);
1857 } else {
1858 /* Number of rx queues will not change after this */
1859 for (i = 0; i < adapter->num_rx_queues; i++) {
1860 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
1861 rq->qid = i;
1862 rq->qid2 = i + adapter->num_rx_queues;
1863 }
d1a890fa
SB		 1864
1865
d1a890fa 1866
09c5088e
SB		 1867 /* init our intr settings */
1868 for (i = 0; i < intr->num_intrs; i++)
1869 intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
1870 if (adapter->intr.type != VMXNET3_IT_MSIX) {
1871 adapter->intr.event_intr_idx = 0;
1872 for (i = 0; i < adapter->num_tx_queues; i++)
1873 adapter->tx_queue[i].comp_ring.intr_idx = 0;
1874 adapter->rx_queue[0].comp_ring.intr_idx = 0;
1875 }
d1a890fa
SB		 1876
1877 printk(KERN_INFO "%s: intr type %u, mode %u, %u vectors "
09c5088e
SB		 1878 "allocated\n", adapter->netdev->name, intr->type,
1879 intr->mask_mode, intr->num_intrs);
d1a890fa
SB		 1880 }
1881
1882 return err;
1883}
1884
1885
1886static void
1887vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
1888{
09c5088e
SB		 1889 struct vmxnet3_intr *intr = &adapter->intr;
1890 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
d1a890fa 1891
09c5088e 1892 switch (intr->type) {
8f7e524c 1893#ifdef CONFIG_PCI_MSI
d1a890fa
SB		 1894 case VMXNET3_IT_MSIX:
1895 {
09c5088e 1896 int i, vector = 0;
d1a890fa 1897
09c5088e
SB		 1898 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
1899 for (i = 0; i < adapter->num_tx_queues; i++) {
1900 free_irq(intr->msix_entries[vector++].vector,
1901 &(adapter->tx_queue[i]));
1902 if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
1903 break;
1904 }
1905 }
1906
1907 for (i = 0; i < adapter->num_rx_queues; i++) {
1908 free_irq(intr->msix_entries[vector++].vector,
1909 &(adapter->rx_queue[i]));
1910 }
1911
1912 free_irq(intr->msix_entries[vector].vector,
1913 adapter->netdev);
1914 BUG_ON(vector >= intr->num_intrs);
d1a890fa
SB		 1915 break;
1916 }
8f7e524c 1917#endif
d1a890fa
SB		 1918 case VMXNET3_IT_MSI:
1919 free_irq(adapter->pdev->irq, adapter->netdev);
1920 break;
1921 case VMXNET3_IT_INTX:
1922 free_irq(adapter->pdev->irq, adapter->netdev);
1923 break;
1924 default:
c068e777 1925 BUG();
d1a890fa
SB		 1926 }
1927}
1928
d1a890fa
SB		 1929
1930static void
1931vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
1932{
72e85c45
JG		 1933 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1934 u16 vid;
d1a890fa 1935
72e85c45
JG		 1936 /* allow untagged pkts */
1937 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
1938
1939 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
1940 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
d1a890fa
SB		 1941}
1942
1943
8e586137 1944static int
d1a890fa
SB		 1945vmxnet3_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1946{
1947 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 1948
f6957f88
JG		 1949 if (!(netdev->flags & IFF_PROMISC)) {
1950 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1951 unsigned long flags;
1952
1953 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
1954 spin_lock_irqsave(&adapter->cmd_lock, flags);
1955 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1956 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1957 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
1958 }
72e85c45
JG		 1959
1960 set_bit(vid, adapter->active_vlans);
8e586137
JP		 1961
1962 return 0;
d1a890fa
SB		 1963}
1964
1965
8e586137 1966static int
d1a890fa
SB		 1967vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1968{
1969 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 1970
f6957f88
JG		 1971 if (!(netdev->flags & IFF_PROMISC)) {
1972 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1973 unsigned long flags;
1974
1975 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
1976 spin_lock_irqsave(&adapter->cmd_lock, flags);
1977 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1978 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1979 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
1980 }
72e85c45
JG		 1981
1982 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 1983
1984 return 0;
d1a890fa
SB		 1985}
1986
1987
1988static u8 *
1989vmxnet3_copy_mc(struct net_device *netdev)
1990{
1991 u8 *buf = NULL;
4cd24eaf 1992 u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
d1a890fa
SB		 1993
1994 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
1995 if (sz <= 0xffff) {
1996 /* We may be called with BH disabled */
1997 buf = kmalloc(sz, GFP_ATOMIC);
1998 if (buf) {
22bedad3 1999 struct netdev_hw_addr *ha;
567ec874 2000 int i = 0;
d1a890fa 2001
22bedad3
JP		 2002 netdev_for_each_mc_addr(ha, netdev)
2003 memcpy(buf + i++ * ETH_ALEN, ha->addr,
d1a890fa 2004 ETH_ALEN);
d1a890fa
SB		 2005 }
2006 }
2007 return buf;
2008}
2009
2010
2011static void
2012vmxnet3_set_mc(struct net_device *netdev)
2013{
2014 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
83d0feff 2015 unsigned long flags;
d1a890fa
SB		 2016 struct Vmxnet3_RxFilterConf *rxConf =
2017 &adapter->shared->devRead.rxFilterConf;
2018 u8 *new_table = NULL;
2019 u32 new_mode = VMXNET3_RXM_UCAST;
2020
72e85c45
JG		 2021 if (netdev->flags & IFF_PROMISC) {
2022 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2023 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable));
2024
d1a890fa 2025 new_mode |= VMXNET3_RXM_PROMISC;
72e85c45
JG		 2026 } else {
2027 vmxnet3_restore_vlan(adapter);
2028 }
d1a890fa
SB		 2029
2030 if (netdev->flags & IFF_BROADCAST)
2031 new_mode |= VMXNET3_RXM_BCAST;
2032
2033 if (netdev->flags & IFF_ALLMULTI)
2034 new_mode |= VMXNET3_RXM_ALL_MULTI;
2035 else
4cd24eaf 2036 if (!netdev_mc_empty(netdev)) {
d1a890fa
SB		 2037 new_table = vmxnet3_copy_mc(netdev);
2038 if (new_table) {
2039 new_mode |= VMXNET3_RXM_MCAST;
115924b6 2040 rxConf->mfTableLen = cpu_to_le16(
4cd24eaf 2041 netdev_mc_count(netdev) * ETH_ALEN);
115924b6
SB		 2042 rxConf->mfTablePA = cpu_to_le64(virt_to_phys(
2043 new_table));
d1a890fa
SB		 2044 } else {
2045 printk(KERN_INFO "%s: failed to copy mcast list"
2046 ", setting ALL_MULTI\n", netdev->name);
2047 new_mode |= VMXNET3_RXM_ALL_MULTI;
2048 }
2049 }
2050
2051
2052 if (!(new_mode & VMXNET3_RXM_MCAST)) {
2053 rxConf->mfTableLen = 0;
2054 rxConf->mfTablePA = 0;
2055 }
2056
83d0feff 2057 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa 2058 if (new_mode != rxConf->rxMode) {
115924b6 2059 rxConf->rxMode = cpu_to_le32(new_mode);
d1a890fa
SB		 2060 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2061 VMXNET3_CMD_UPDATE_RX_MODE);
72e85c45
JG		 2062 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2063 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
d1a890fa
SB		 2064 }
2065
2066 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2067 VMXNET3_CMD_UPDATE_MAC_FILTERS);
83d0feff 2068 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2069
2070 kfree(new_table);
2071}
2072
09c5088e
SB		 2073void
2074vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
2075{
2076 int i;
2077
2078 for (i = 0; i < adapter->num_rx_queues; i++)
2079 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
2080}
2081
d1a890fa
SB		 2082
2083/*
2084 * Set up driver_shared based on settings in adapter.
2085 */
2086
2087static void
2088vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
2089{
2090 struct Vmxnet3_DriverShared *shared = adapter->shared;
2091 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
2092 struct Vmxnet3_TxQueueConf *tqc;
2093 struct Vmxnet3_RxQueueConf *rqc;
2094 int i;
2095
2096 memset(shared, 0, sizeof(*shared));
2097
2098 /* driver settings */
115924b6
SB		 2099 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
2100 devRead->misc.driverInfo.version = cpu_to_le32(
2101 VMXNET3_DRIVER_VERSION_NUM);
d1a890fa
SB		 2102 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
2103 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
2104 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
115924b6
SB		 2105 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
2106 *((u32 *)&devRead->misc.driverInfo.gos));
2107 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
2108 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
d1a890fa 2109
115924b6
SB		 2110 devRead->misc.ddPA = cpu_to_le64(virt_to_phys(adapter));
2111 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
d1a890fa
SB		 2112
2113 /* set up feature flags */
a0d2730c 2114 if (adapter->netdev->features & NETIF_F_RXCSUM)
3843e515 2115 devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
d1a890fa 2116
a0d2730c 2117 if (adapter->netdev->features & NETIF_F_LRO) {
3843e515 2118 devRead->misc.uptFeatures |= UPT1_F_LRO;
115924b6 2119 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
d1a890fa 2120 }
54da3d00 2121 if (adapter->netdev->features & NETIF_F_HW_VLAN_RX)
3843e515 2122 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
d1a890fa 2123
115924b6
SB		 2124 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
2125 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
2126 devRead->misc.queueDescLen = cpu_to_le32(
09c5088e
SB		 2127 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
2128 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
d1a890fa
SB		 2129
2130 /* tx queue settings */
09c5088e
SB		 2131 devRead->misc.numTxQueues = adapter->num_tx_queues;
2132 for (i = 0; i < adapter->num_tx_queues; i++) {
2133 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2134 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
2135 tqc = &adapter->tqd_start[i].conf;
2136 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA);
2137 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
2138 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
2139 tqc->ddPA = cpu_to_le64(virt_to_phys(tq->buf_info));
2140 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size);
2141 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size);
2142 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size);
2143 tqc->ddLen = cpu_to_le32(
2144 sizeof(struct vmxnet3_tx_buf_info) *
2145 tqc->txRingSize);
2146 tqc->intrIdx = tq->comp_ring.intr_idx;
2147 }
d1a890fa
SB		 2148
2149 /* rx queue settings */
09c5088e
SB		 2150 devRead->misc.numRxQueues = adapter->num_rx_queues;
2151 for (i = 0; i < adapter->num_rx_queues; i++) {
2152 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2153 rqc = &adapter->rqd_start[i].conf;
2154 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
2155 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
2156 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA);
2157 rqc->ddPA = cpu_to_le64(virt_to_phys(
2158 rq->buf_info));
2159 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size);
2160 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size);
2161 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size);
2162 rqc->ddLen = cpu_to_le32(
2163 sizeof(struct vmxnet3_rx_buf_info) *
2164 (rqc->rxRingSize[0] +
2165 rqc->rxRingSize[1]));
2166 rqc->intrIdx = rq->comp_ring.intr_idx;
2167 }
2168
2169#ifdef VMXNET3_RSS
2170 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
2171
2172 if (adapter->rss) {
2173 struct UPT1_RSSConf *rssConf = adapter->rss_conf;
2174 devRead->misc.uptFeatures |= UPT1_F_RSS;
2175 devRead->misc.numRxQueues = adapter->num_rx_queues;
2176 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
2177 UPT1_RSS_HASH_TYPE_IPV4 |
2178 UPT1_RSS_HASH_TYPE_TCP_IPV6 |
2179 UPT1_RSS_HASH_TYPE_IPV6;
2180 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
2181 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
2182 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
2183 get_random_bytes(&rssConf->hashKey[0], rssConf->hashKeySize);
2184 for (i = 0; i < rssConf->indTableSize; i++)
278bc429
BH		 2185 rssConf->indTable[i] = ethtool_rxfh_indir_default(
2186 i, adapter->num_rx_queues);
09c5088e
SB		 2187
2188 devRead->rssConfDesc.confVer = 1;
2189 devRead->rssConfDesc.confLen = sizeof(*rssConf);
2190 devRead->rssConfDesc.confPA = virt_to_phys(rssConf);
2191 }
2192
2193#endif /* VMXNET3_RSS */
d1a890fa
SB		 2194
2195 /* intr settings */
2196 devRead->intrConf.autoMask = adapter->intr.mask_mode ==
2197 VMXNET3_IMM_AUTO;
2198 devRead->intrConf.numIntrs = adapter->intr.num_intrs;
2199 for (i = 0; i < adapter->intr.num_intrs; i++)
2200 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
2201
2202 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
6929fe8a 2203 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 2204
2205 /* rx filter settings */
2206 devRead->rxFilterConf.rxMode = 0;
2207 vmxnet3_restore_vlan(adapter);
f9f25026
SB		 2208 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr);
2209
d1a890fa
SB		 2210 /* the rest are already zeroed */
2211}
2212
2213
2214int
2215vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
2216{
09c5088e 2217 int err, i;
d1a890fa 2218 u32 ret;
83d0feff 2219 unsigned long flags;
d1a890fa 2220
09c5088e
SB		 2221 dev_dbg(&adapter->netdev->dev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
2222 " ring sizes %u %u %u\n", adapter->netdev->name,
2223 adapter->skb_buf_size, adapter->rx_buf_per_pkt,
2224 adapter->tx_queue[0].tx_ring.size,
2225 adapter->rx_queue[0].rx_ring[0].size,
2226 adapter->rx_queue[0].rx_ring[1].size);
2227
2228 vmxnet3_tq_init_all(adapter);
2229 err = vmxnet3_rq_init_all(adapter);
d1a890fa
SB		 2230 if (err) {
2231 printk(KERN_ERR "Failed to init rx queue for %s: error %d\n",
2232 adapter->netdev->name, err);
2233 goto rq_err;
2234 }
2235
2236 err = vmxnet3_request_irqs(adapter);
2237 if (err) {
2238 printk(KERN_ERR "Failed to setup irq for %s: error %d\n",
2239 adapter->netdev->name, err);
2240 goto irq_err;
2241 }
2242
2243 vmxnet3_setup_driver_shared(adapter);
2244
115924b6
SB		 2245 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
2246 adapter->shared_pa));
2247 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
2248 adapter->shared_pa));
83d0feff 2249 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 2250 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2251 VMXNET3_CMD_ACTIVATE_DEV);
2252 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
83d0feff 2253 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2254
2255 if (ret != 0) {
2256 printk(KERN_ERR "Failed to activate dev %s: error %u\n",
2257 adapter->netdev->name, ret);
2258 err = -EINVAL;
2259 goto activate_err;
2260 }
09c5088e
SB		 2261
2262 for (i = 0; i < adapter->num_rx_queues; i++) {
2263 VMXNET3_WRITE_BAR0_REG(adapter,
2264 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
2265 adapter->rx_queue[i].rx_ring[0].next2fill);
2266 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
2267 (i * VMXNET3_REG_ALIGN)),
2268 adapter->rx_queue[i].rx_ring[1].next2fill);
2269 }
d1a890fa
SB		 2270
2271 /* Apply the rx filter settins last. */
2272 vmxnet3_set_mc(adapter->netdev);
2273
2274 /*
2275 * Check link state when first activating device. It will start the
2276 * tx queue if the link is up.
2277 */
4a1745fc 2278 vmxnet3_check_link(adapter, true);
09c5088e
SB		 2279 for (i = 0; i < adapter->num_rx_queues; i++)
2280 napi_enable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2281 vmxnet3_enable_all_intrs(adapter);
2282 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
2283 return 0;
2284
2285activate_err:
2286 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
2287 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
2288 vmxnet3_free_irqs(adapter);
2289irq_err:
2290rq_err:
2291 /* free up buffers we allocated */
09c5088e 2292 vmxnet3_rq_cleanup_all(adapter);
d1a890fa
SB		 2293 return err;
2294}
2295
2296
2297void
2298vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
2299{
83d0feff
SB		 2300 unsigned long flags;
2301 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa 2302 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
83d0feff 2303 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2304}
2305
2306
2307int
2308vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
2309{
09c5088e 2310 int i;
83d0feff 2311 unsigned long flags;
d1a890fa
SB		 2312 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
2313 return 0;
2314
2315
83d0feff 2316 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 2317 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2318 VMXNET3_CMD_QUIESCE_DEV);
83d0feff 2319 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2320 vmxnet3_disable_all_intrs(adapter);
2321
09c5088e
SB		 2322 for (i = 0; i < adapter->num_rx_queues; i++)
2323 napi_disable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2324 netif_tx_disable(adapter->netdev);
2325 adapter->link_speed = 0;
2326 netif_carrier_off(adapter->netdev);
2327
09c5088e
SB		 2328 vmxnet3_tq_cleanup_all(adapter);
2329 vmxnet3_rq_cleanup_all(adapter);
d1a890fa
SB		 2330 vmxnet3_free_irqs(adapter);
2331 return 0;
2332}
2333
2334
2335static void
2336vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2337{
2338 u32 tmp;
2339
2340 tmp = *(u32 *)mac;
2341 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
2342
2343 tmp = (mac[5] << 8) | mac[4];
2344 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
2345}
2346
2347
2348static int
2349vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
2350{
2351 struct sockaddr *addr = p;
2352 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2353
2354 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2355 vmxnet3_write_mac_addr(adapter, addr->sa_data);
2356
2357 return 0;
2358}
2359
2360
2361/* ==================== initialization and cleanup routines ============ */
2362
2363static int
2364vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter, bool *dma64)
2365{
2366 int err;
2367 unsigned long mmio_start, mmio_len;
2368 struct pci_dev *pdev = adapter->pdev;
2369
2370 err = pci_enable_device(pdev);
2371 if (err) {
2372 printk(KERN_ERR "Failed to enable adapter %s: error %d\n",
2373 pci_name(pdev), err);
2374 return err;
2375 }
2376
2377 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
2378 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
2379 printk(KERN_ERR "pci_set_consistent_dma_mask failed "
2380 "for adapter %s\n", pci_name(pdev));
2381 err = -EIO;
2382 goto err_set_mask;
2383 }
2384 *dma64 = true;
2385 } else {
2386 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
2387 printk(KERN_ERR "pci_set_dma_mask failed for adapter "
2388 "%s\n", pci_name(pdev));
2389 err = -EIO;
2390 goto err_set_mask;
2391 }
2392 *dma64 = false;
2393 }
2394
2395 err = pci_request_selected_regions(pdev, (1 << 2) - 1,
2396 vmxnet3_driver_name);
2397 if (err) {
2398 printk(KERN_ERR "Failed to request region for adapter %s: "
2399 "error %d\n", pci_name(pdev), err);
2400 goto err_set_mask;
2401 }
2402
2403 pci_set_master(pdev);
2404
2405 mmio_start = pci_resource_start(pdev, 0);
2406 mmio_len = pci_resource_len(pdev, 0);
2407 adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
2408 if (!adapter->hw_addr0) {
2409 printk(KERN_ERR "Failed to map bar0 for adapter %s\n",
2410 pci_name(pdev));
2411 err = -EIO;
2412 goto err_ioremap;
2413 }
2414
2415 mmio_start = pci_resource_start(pdev, 1);
2416 mmio_len = pci_resource_len(pdev, 1);
2417 adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
2418 if (!adapter->hw_addr1) {
2419 printk(KERN_ERR "Failed to map bar1 for adapter %s\n",
2420 pci_name(pdev));
2421 err = -EIO;
2422 goto err_bar1;
2423 }
2424 return 0;
2425
2426err_bar1:
2427 iounmap(adapter->hw_addr0);
2428err_ioremap:
2429 pci_release_selected_regions(pdev, (1 << 2) - 1);
2430err_set_mask:
2431 pci_disable_device(pdev);
2432 return err;
2433}
2434
2435
2436static void
2437vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
2438{
2439 BUG_ON(!adapter->pdev);
2440
2441 iounmap(adapter->hw_addr0);
2442 iounmap(adapter->hw_addr1);
2443 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
2444 pci_disable_device(adapter->pdev);
2445}
2446
2447
2448static void
2449vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
2450{
09c5088e
SB		 2451 size_t sz, i, ring0_size, ring1_size, comp_size;
2452 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[0];
2453
d1a890fa
SB		 2454
2455 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
2456 VMXNET3_MAX_ETH_HDR_SIZE) {
2457 adapter->skb_buf_size = adapter->netdev->mtu +
2458 VMXNET3_MAX_ETH_HDR_SIZE;
2459 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
2460 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
2461
2462 adapter->rx_buf_per_pkt = 1;
2463 } else {
2464 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
2465 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
2466 VMXNET3_MAX_ETH_HDR_SIZE;
2467 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
2468 }
2469
2470 /*
2471 * for simplicity, force the ring0 size to be a multiple of
2472 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
2473 */
2474 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
09c5088e
SB		 2475 ring0_size = adapter->rx_queue[0].rx_ring[0].size;
2476 ring0_size = (ring0_size + sz - 1) / sz * sz;
a53255d3 2477 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE /
09c5088e
SB		 2478 sz * sz);
2479 ring1_size = adapter->rx_queue[0].rx_ring[1].size;
2480 comp_size = ring0_size + ring1_size;
2481
2482 for (i = 0; i < adapter->num_rx_queues; i++) {
2483 rq = &adapter->rx_queue[i];
2484 rq->rx_ring[0].size = ring0_size;
2485 rq->rx_ring[1].size = ring1_size;
2486 rq->comp_ring.size = comp_size;
2487 }
d1a890fa
SB		 2488}
2489
2490
2491int
2492vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
2493 u32 rx_ring_size, u32 rx_ring2_size)
2494{
09c5088e
SB		 2495 int err = 0, i;
2496
2497 for (i = 0; i < adapter->num_tx_queues; i++) {
2498 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2499 tq->tx_ring.size = tx_ring_size;
2500 tq->data_ring.size = tx_ring_size;
2501 tq->comp_ring.size = tx_ring_size;
2502 tq->shared = &adapter->tqd_start[i].ctrl;
2503 tq->stopped = true;
2504 tq->adapter = adapter;
2505 tq->qid = i;
2506 err = vmxnet3_tq_create(tq, adapter);
2507 /*
2508 * Too late to change num_tx_queues. We cannot do away with
2509 * lesser number of queues than what we asked for
2510 */
2511 if (err)
2512 goto queue_err;
2513 }
d1a890fa 2514
09c5088e
SB		 2515 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
2516 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
d1a890fa 2517 vmxnet3_adjust_rx_ring_size(adapter);
09c5088e
SB		 2518 for (i = 0; i < adapter->num_rx_queues; i++) {
2519 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2520 /* qid and qid2 for rx queues will be assigned later when num
2521 * of rx queues is finalized after allocating intrs */
2522 rq->shared = &adapter->rqd_start[i].ctrl;
2523 rq->adapter = adapter;
2524 err = vmxnet3_rq_create(rq, adapter);
2525 if (err) {
2526 if (i == 0) {
2527 printk(KERN_ERR "Could not allocate any rx"
2528 "queues. Aborting.\n");
2529 goto queue_err;
2530 } else {
2531 printk(KERN_INFO "Number of rx queues changed "
2532 "to : %d.\n", i);
2533 adapter->num_rx_queues = i;
2534 err = 0;
2535 break;
2536 }
2537 }
2538 }
2539 return err;
2540queue_err:
2541 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2542 return err;
2543}
2544
2545static int
2546vmxnet3_open(struct net_device *netdev)
2547{
2548 struct vmxnet3_adapter *adapter;
09c5088e 2549 int err, i;
d1a890fa
SB		 2550
2551 adapter = netdev_priv(netdev);
2552
09c5088e
SB		 2553 for (i = 0; i < adapter->num_tx_queues; i++)
2554 spin_lock_init(&adapter->tx_queue[i].tx_lock);
d1a890fa
SB		 2555
2556 err = vmxnet3_create_queues(adapter, VMXNET3_DEF_TX_RING_SIZE,
2557 VMXNET3_DEF_RX_RING_SIZE,
2558 VMXNET3_DEF_RX_RING_SIZE);
2559 if (err)
2560 goto queue_err;
2561
2562 err = vmxnet3_activate_dev(adapter);
2563 if (err)
2564 goto activate_err;
2565
2566 return 0;
2567
2568activate_err:
09c5088e
SB		 2569 vmxnet3_rq_destroy_all(adapter);
2570 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2571queue_err:
2572 return err;
2573}
2574
2575
2576static int
2577vmxnet3_close(struct net_device *netdev)
2578{
2579 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2580
2581 /*
2582 * Reset_work may be in the middle of resetting the device, wait for its
2583 * completion.
2584 */
2585 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2586 msleep(1);
2587
2588 vmxnet3_quiesce_dev(adapter);
2589
09c5088e
SB		 2590 vmxnet3_rq_destroy_all(adapter);
2591 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2592
2593 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2594
2595
2596 return 0;
2597}
2598
2599
2600void
2601vmxnet3_force_close(struct vmxnet3_adapter *adapter)
2602{
09c5088e
SB		 2603 int i;
2604
d1a890fa
SB		 2605 /*
2606 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
2607 * vmxnet3_close() will deadlock.
2608 */
2609 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
2610
2611 /* we need to enable NAPI, otherwise dev_close will deadlock */
09c5088e
SB		 2612 for (i = 0; i < adapter->num_rx_queues; i++)
2613 napi_enable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2614 dev_close(adapter->netdev);
2615}
2616
2617
2618static int
2619vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
2620{
2621 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2622 int err = 0;
2623
2624 if (new_mtu < VMXNET3_MIN_MTU || new_mtu > VMXNET3_MAX_MTU)
2625 return -EINVAL;
2626
d1a890fa
SB		 2627 netdev->mtu = new_mtu;
2628
2629 /*
2630 * Reset_work may be in the middle of resetting the device, wait for its
2631 * completion.
2632 */
2633 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2634 msleep(1);
2635
2636 if (netif_running(netdev)) {
2637 vmxnet3_quiesce_dev(adapter);
2638 vmxnet3_reset_dev(adapter);
2639
2640 /* we need to re-create the rx queue based on the new mtu */
09c5088e 2641 vmxnet3_rq_destroy_all(adapter);
d1a890fa 2642 vmxnet3_adjust_rx_ring_size(adapter);
09c5088e 2643 err = vmxnet3_rq_create_all(adapter);
d1a890fa 2644 if (err) {
09c5088e 2645 printk(KERN_ERR "%s: failed to re-create rx queues,"
d1a890fa
SB		 2646 " error %d. Closing it.\n", netdev->name, err);
2647 goto out;
2648 }
2649
2650 err = vmxnet3_activate_dev(adapter);
2651 if (err) {
2652 printk(KERN_ERR "%s: failed to re-activate, error %d. "
2653 "Closing it\n", netdev->name, err);
2654 goto out;
2655 }
2656 }
2657
2658out:
2659 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2660 if (err)
2661 vmxnet3_force_close(adapter);
2662
2663 return err;
2664}
2665
2666
2667static void
2668vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64)
2669{
2670 struct net_device *netdev = adapter->netdev;
2671
a0d2730c
MM		 2672 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
2673 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_TX |
72e85c45
JG		 2674 NETIF_F_HW_VLAN_RX | NETIF_F_TSO | NETIF_F_TSO6 |
2675 NETIF_F_LRO;
a0d2730c 2676 if (dma64)
ebbf9295 2677 netdev->hw_features |= NETIF_F_HIGHDMA;
72e85c45
JG		 2678 netdev->vlan_features = netdev->hw_features &
2679 ~(NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
2680 netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_FILTER;
d1a890fa 2681
a0d2730c
MM		 2682 netdev_info(adapter->netdev,
2683 "features: sg csum vlan jf tso tsoIPv6 lro%s\n",
2684 dma64 ? " highDMA" : "");
d1a890fa
SB		 2685}
2686
2687
2688static void
2689vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2690{
2691 u32 tmp;
2692
2693 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
2694 *(u32 *)mac = tmp;
2695
2696 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
2697 mac[4] = tmp & 0xff;
2698 mac[5] = (tmp >> 8) & 0xff;
2699}
2700
09c5088e
SB		 2701#ifdef CONFIG_PCI_MSI
2702
2703/*
2704 * Enable MSIx vectors.
2705 * Returns :
2706 * 0 on successful enabling of required vectors,
25985edc 2707 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required
09c5088e
SB		 2708 * could be enabled.
2709 * number of vectors which can be enabled otherwise (this number is smaller
2710 * than VMXNET3_LINUX_MIN_MSIX_VECT)
2711 */
2712
2713static int
2714vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter,
2715 int vectors)
2716{
2717 int err = 0, vector_threshold;
2718 vector_threshold = VMXNET3_LINUX_MIN_MSIX_VECT;
2719
2720 while (vectors >= vector_threshold) {
2721 err = pci_enable_msix(adapter->pdev, adapter->intr.msix_entries,
2722 vectors);
2723 if (!err) {
2724 adapter->intr.num_intrs = vectors;
2725 return 0;
2726 } else if (err < 0) {
4c1dc80a
SB		 2727 netdev_err(adapter->netdev,
2728 "Failed to enable MSI-X, error: %d\n", err);
09c5088e
SB		 2729 vectors = 0;
2730 } else if (err < vector_threshold) {
2731 break;
2732 } else {
2733 /* If fails to enable required number of MSI-x vectors
7e96fbf2 2734 * try enabling minimum number of vectors required.
09c5088e 2735 */
4c1dc80a
SB		 2736 netdev_err(adapter->netdev,
2737 "Failed to enable %d MSI-X, trying %d instead\n",
2738 vectors, vector_threshold);
09c5088e 2739 vectors = vector_threshold;
09c5088e
SB		 2740 }
2741 }
2742
4c1dc80a
SB		 2743 netdev_info(adapter->netdev,
2744 "Number of MSI-X interrupts which can be allocated are lower than min threshold required.\n");
09c5088e
SB		 2745 return err;
2746}
2747
2748
2749#endif /* CONFIG_PCI_MSI */
d1a890fa
SB		 2750
2751static void
2752vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
2753{
2754 u32 cfg;
e328d410 2755 unsigned long flags;
d1a890fa
SB		 2756
2757 /* intr settings */
e328d410 2758 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 2759 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2760 VMXNET3_CMD_GET_CONF_INTR);
2761 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
e328d410 2762 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2763 adapter->intr.type = cfg & 0x3;
2764 adapter->intr.mask_mode = (cfg >> 2) & 0x3;
2765
2766 if (adapter->intr.type == VMXNET3_IT_AUTO) {
0bdc0d70
SB		 2767 adapter->intr.type = VMXNET3_IT_MSIX;
2768 }
d1a890fa 2769
8f7e524c 2770#ifdef CONFIG_PCI_MSI
0bdc0d70 2771 if (adapter->intr.type == VMXNET3_IT_MSIX) {
09c5088e
SB		 2772 int vector, err = 0;
2773
2774 adapter->intr.num_intrs = (adapter->share_intr ==
2775 VMXNET3_INTR_TXSHARE) ? 1 :
2776 adapter->num_tx_queues;
2777 adapter->intr.num_intrs += (adapter->share_intr ==
2778 VMXNET3_INTR_BUDDYSHARE) ? 0 :
2779 adapter->num_rx_queues;
2780 adapter->intr.num_intrs += 1; /* for link event */
2781
2782 adapter->intr.num_intrs = (adapter->intr.num_intrs >
2783 VMXNET3_LINUX_MIN_MSIX_VECT
2784 ? adapter->intr.num_intrs :
2785 VMXNET3_LINUX_MIN_MSIX_VECT);
2786
2787 for (vector = 0; vector < adapter->intr.num_intrs; vector++)
2788 adapter->intr.msix_entries[vector].entry = vector;
2789
2790 err = vmxnet3_acquire_msix_vectors(adapter,
2791 adapter->intr.num_intrs);
2792 /* If we cannot allocate one MSIx vector per queue
2793 * then limit the number of rx queues to 1
2794 */
2795 if (err == VMXNET3_LINUX_MIN_MSIX_VECT) {
2796 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
7e96fbf2 2797 || adapter->num_rx_queues != 1) {
09c5088e
SB		 2798 adapter->share_intr = VMXNET3_INTR_TXSHARE;
2799 printk(KERN_ERR "Number of rx queues : 1\n");
2800 adapter->num_rx_queues = 1;
2801 adapter->intr.num_intrs =
2802 VMXNET3_LINUX_MIN_MSIX_VECT;
2803 }
d1a890fa
SB		 2804 return;
2805 }
09c5088e
SB		 2806 if (!err)
2807 return;
2808
2809 /* If we cannot allocate MSIx vectors use only one rx queue */
4c1dc80a
SB		 2810 netdev_info(adapter->netdev,
2811 "Failed to enable MSI-X, error %d . Limiting #rx queues to 1, try MSI.\n",
2812 err);
09c5088e 2813
0bdc0d70
SB		 2814 adapter->intr.type = VMXNET3_IT_MSI;
2815 }
d1a890fa 2816
0bdc0d70
SB		 2817 if (adapter->intr.type == VMXNET3_IT_MSI) {
2818 int err;
d1a890fa
SB		 2819 err = pci_enable_msi(adapter->pdev);
2820 if (!err) {
09c5088e 2821 adapter->num_rx_queues = 1;
d1a890fa 2822 adapter->intr.num_intrs = 1;
d1a890fa
SB		 2823 return;
2824 }
2825 }
0bdc0d70 2826#endif /* CONFIG_PCI_MSI */
d1a890fa 2827
09c5088e
SB		 2828 adapter->num_rx_queues = 1;
2829 printk(KERN_INFO "Using INTx interrupt, #Rx queues: 1.\n");
d1a890fa
SB		 2830 adapter->intr.type = VMXNET3_IT_INTX;
2831
2832 /* INT-X related setting */
2833 adapter->intr.num_intrs = 1;
2834}
2835
2836
2837static void
2838vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
2839{
2840 if (adapter->intr.type == VMXNET3_IT_MSIX)
2841 pci_disable_msix(adapter->pdev);
2842 else if (adapter->intr.type == VMXNET3_IT_MSI)
2843 pci_disable_msi(adapter->pdev);
2844 else
2845 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
2846}
2847
2848
2849static void
2850vmxnet3_tx_timeout(struct net_device *netdev)
2851{
2852 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2853 adapter->tx_timeout_count++;
2854
2855 printk(KERN_ERR "%s: tx hang\n", adapter->netdev->name);
2856 schedule_work(&adapter->work);
09c5088e 2857 netif_wake_queue(adapter->netdev);
d1a890fa
SB		 2858}
2859
2860
2861static void
2862vmxnet3_reset_work(struct work_struct *data)
2863{
2864 struct vmxnet3_adapter *adapter;
2865
2866 adapter = container_of(data, struct vmxnet3_adapter, work);
2867
2868 /* if another thread is resetting the device, no need to proceed */
2869 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2870 return;
2871
2872 /* if the device is closed, we must leave it alone */
d9a5f210 2873 rtnl_lock();
d1a890fa
SB		 2874 if (netif_running(adapter->netdev)) {
2875 printk(KERN_INFO "%s: resetting\n", adapter->netdev->name);
2876 vmxnet3_quiesce_dev(adapter);
2877 vmxnet3_reset_dev(adapter);
2878 vmxnet3_activate_dev(adapter);
2879 } else {
2880 printk(KERN_INFO "%s: already closed\n", adapter->netdev->name);
2881 }
d9a5f210 2882 rtnl_unlock();
d1a890fa
SB		 2883
2884 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2885}
2886
2887
3a4751a3 2888static int
d1a890fa
SB		 2889vmxnet3_probe_device(struct pci_dev *pdev,
2890 const struct pci_device_id *id)
2891{
2892 static const struct net_device_ops vmxnet3_netdev_ops = {
2893 .ndo_open = vmxnet3_open,
2894 .ndo_stop = vmxnet3_close,
2895 .ndo_start_xmit = vmxnet3_xmit_frame,
2896 .ndo_set_mac_address = vmxnet3_set_mac_addr,
2897 .ndo_change_mtu = vmxnet3_change_mtu,
a0d2730c 2898 .ndo_set_features = vmxnet3_set_features,
95305f6c 2899 .ndo_get_stats64 = vmxnet3_get_stats64,
d1a890fa 2900 .ndo_tx_timeout = vmxnet3_tx_timeout,
afc4b13d 2901 .ndo_set_rx_mode = vmxnet3_set_mc,
d1a890fa
SB		 2902 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
2903 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
2904#ifdef CONFIG_NET_POLL_CONTROLLER
2905 .ndo_poll_controller = vmxnet3_netpoll,
2906#endif
2907 };
2908 int err;
2909 bool dma64 = false; /* stupid gcc */
2910 u32 ver;
2911 struct net_device *netdev;
2912 struct vmxnet3_adapter *adapter;
2913 u8 mac[ETH_ALEN];
09c5088e
SB		 2914 int size;
2915 int num_tx_queues;
2916 int num_rx_queues;
2917
e154b639
SB		 2918 if (!pci_msi_enabled())
2919 enable_mq = 0;
2920
09c5088e
SB		 2921#ifdef VMXNET3_RSS
2922 if (enable_mq)
2923 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
2924 (int)num_online_cpus());
2925 else
2926#endif
2927 num_rx_queues = 1;
eebb02b1 2928 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
09c5088e
SB		 2929
2930 if (enable_mq)
2931 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
2932 (int)num_online_cpus());
2933 else
2934 num_tx_queues = 1;
2935
eebb02b1 2936 num_tx_queues = rounddown_pow_of_two(num_tx_queues);
09c5088e
SB		 2937 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
2938 max(num_tx_queues, num_rx_queues));
2939 printk(KERN_INFO "# of Tx queues : %d, # of Rx queues : %d\n",
2940 num_tx_queues, num_rx_queues);
d1a890fa 2941
41de8d4c 2942 if (!netdev)
d1a890fa 2943 return -ENOMEM;
d1a890fa
SB		 2944
2945 pci_set_drvdata(pdev, netdev);
2946 adapter = netdev_priv(netdev);
2947 adapter->netdev = netdev;
2948 adapter->pdev = pdev;
2949
83d0feff 2950 spin_lock_init(&adapter->cmd_lock);
d1a890fa 2951 adapter->shared = pci_alloc_consistent(adapter->pdev,
96800ee7 2952 sizeof(struct Vmxnet3_DriverShared),
2953 &adapter->shared_pa);
d1a890fa
SB		 2954 if (!adapter->shared) {
2955 printk(KERN_ERR "Failed to allocate memory for %s\n",
96800ee7 2956 pci_name(pdev));
d1a890fa
SB		 2957 err = -ENOMEM;
2958 goto err_alloc_shared;
2959 }
2960
09c5088e
SB		 2961 adapter->num_rx_queues = num_rx_queues;
2962 adapter->num_tx_queues = num_tx_queues;
2963
2964 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
2965 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
2966 adapter->tqd_start = pci_alloc_consistent(adapter->pdev, size,
96800ee7 2967 &adapter->queue_desc_pa);
d1a890fa
SB		 2968
2969 if (!adapter->tqd_start) {
2970 printk(KERN_ERR "Failed to allocate memory for %s\n",
96800ee7 2971 pci_name(pdev));
d1a890fa
SB		 2972 err = -ENOMEM;
2973 goto err_alloc_queue_desc;
2974 }
09c5088e 2975 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
96800ee7 2976 adapter->num_tx_queues);
d1a890fa
SB		 2977
2978 adapter->pm_conf = kmalloc(sizeof(struct Vmxnet3_PMConf), GFP_KERNEL);
2979 if (adapter->pm_conf == NULL) {
d1a890fa
SB		 2980 err = -ENOMEM;
2981 goto err_alloc_pm;
2982 }
2983
09c5088e
SB		 2984#ifdef VMXNET3_RSS
2985
2986 adapter->rss_conf = kmalloc(sizeof(struct UPT1_RSSConf), GFP_KERNEL);
2987 if (adapter->rss_conf == NULL) {
09c5088e
SB		 2988 err = -ENOMEM;
2989 goto err_alloc_rss;
2990 }
2991#endif /* VMXNET3_RSS */
2992
d1a890fa
SB		 2993 err = vmxnet3_alloc_pci_resources(adapter, &dma64);
2994 if (err < 0)
2995 goto err_alloc_pci;
2996
2997 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
2998 if (ver & 1) {
2999 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_VRRS, 1);
3000 } else {
3001 printk(KERN_ERR "Incompatible h/w version (0x%x) for adapter"
3002 " %s\n", ver, pci_name(pdev));
3003 err = -EBUSY;
3004 goto err_ver;
3005 }
3006
3007 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
3008 if (ver & 1) {
3009 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
3010 } else {
3011 printk(KERN_ERR "Incompatible upt version (0x%x) for "
3012 "adapter %s\n", ver, pci_name(pdev));
3013 err = -EBUSY;
3014 goto err_ver;
3015 }
3016
e101e7dd 3017 SET_NETDEV_DEV(netdev, &pdev->dev);
d1a890fa
SB		 3018 vmxnet3_declare_features(adapter, dma64);
3019
3020 adapter->dev_number = atomic_read(&devices_found);
09c5088e 3021
96800ee7 3022 adapter->share_intr = irq_share_mode;
09c5088e
SB		 3023 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE &&
3024 adapter->num_tx_queues != adapter->num_rx_queues)
3025 adapter->share_intr = VMXNET3_INTR_DONTSHARE;
3026
d1a890fa
SB		 3027 vmxnet3_alloc_intr_resources(adapter);
3028
09c5088e
SB		 3029#ifdef VMXNET3_RSS
3030 if (adapter->num_rx_queues > 1 &&
3031 adapter->intr.type == VMXNET3_IT_MSIX) {
3032 adapter->rss = true;
3033 printk(KERN_INFO "RSS is enabled.\n");
3034 } else {
3035 adapter->rss = false;
3036 }
3037#endif
3038
d1a890fa
SB		 3039 vmxnet3_read_mac_addr(adapter, mac);
3040 memcpy(netdev->dev_addr, mac, netdev->addr_len);
3041
3042 netdev->netdev_ops = &vmxnet3_netdev_ops;
d1a890fa 3043 vmxnet3_set_ethtool_ops(netdev);
09c5088e 3044 netdev->watchdog_timeo = 5 * HZ;
d1a890fa
SB		 3045
3046 INIT_WORK(&adapter->work, vmxnet3_reset_work);
e3bc4ffb 3047 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
d1a890fa 3048
09c5088e
SB		 3049 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3050 int i;
3051 for (i = 0; i < adapter->num_rx_queues; i++) {
3052 netif_napi_add(adapter->netdev,
3053 &adapter->rx_queue[i].napi,
3054 vmxnet3_poll_rx_only, 64);
3055 }
3056 } else {
3057 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
3058 vmxnet3_poll, 64);
3059 }
3060
3061 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
3062 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
3063
d1a890fa
SB		 3064 err = register_netdev(netdev);
3065
3066 if (err) {
3067 printk(KERN_ERR "Failed to register adapter %s\n",
96800ee7 3068 pci_name(pdev));
d1a890fa
SB		 3069 goto err_register;
3070 }
3071
4a1745fc 3072 vmxnet3_check_link(adapter, false);
d1a890fa
SB		 3073 atomic_inc(&devices_found);
3074 return 0;
3075
3076err_register:
3077 vmxnet3_free_intr_resources(adapter);
3078err_ver:
3079 vmxnet3_free_pci_resources(adapter);
3080err_alloc_pci:
09c5088e
SB		 3081#ifdef VMXNET3_RSS
3082 kfree(adapter->rss_conf);
3083err_alloc_rss:
3084#endif
d1a890fa
SB		 3085 kfree(adapter->pm_conf);
3086err_alloc_pm:
09c5088e
SB		 3087 pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
3088 adapter->queue_desc_pa);
d1a890fa
SB		 3089err_alloc_queue_desc:
3090 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
3091 adapter->shared, adapter->shared_pa);
3092err_alloc_shared:
3093 pci_set_drvdata(pdev, NULL);
3094 free_netdev(netdev);
3095 return err;
3096}
3097
3098
3a4751a3 3099static void
d1a890fa
SB		 3100vmxnet3_remove_device(struct pci_dev *pdev)
3101{
3102 struct net_device *netdev = pci_get_drvdata(pdev);
3103 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
09c5088e
SB		 3104 int size = 0;
3105 int num_rx_queues;
3106
3107#ifdef VMXNET3_RSS
3108 if (enable_mq)
3109 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3110 (int)num_online_cpus());
3111 else
3112#endif
3113 num_rx_queues = 1;
eebb02b1 3114 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
d1a890fa 3115
23f333a2 3116 cancel_work_sync(&adapter->work);
d1a890fa
SB		 3117
3118 unregister_netdev(netdev);
3119
3120 vmxnet3_free_intr_resources(adapter);
3121 vmxnet3_free_pci_resources(adapter);
09c5088e
SB		 3122#ifdef VMXNET3_RSS
3123 kfree(adapter->rss_conf);
3124#endif
d1a890fa 3125 kfree(adapter->pm_conf);
09c5088e
SB		 3126
3127 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3128 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
3129 pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
3130 adapter->queue_desc_pa);
d1a890fa
SB		 3131 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
3132 adapter->shared, adapter->shared_pa);
3133 free_netdev(netdev);
3134}
3135
3136
3137#ifdef CONFIG_PM
3138
3139static int
3140vmxnet3_suspend(struct device *device)
3141{
3142 struct pci_dev *pdev = to_pci_dev(device);
3143 struct net_device *netdev = pci_get_drvdata(pdev);
3144 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3145 struct Vmxnet3_PMConf *pmConf;
3146 struct ethhdr *ehdr;
3147 struct arphdr *ahdr;
3148 u8 *arpreq;
3149 struct in_device *in_dev;
3150 struct in_ifaddr *ifa;
83d0feff 3151 unsigned long flags;
d1a890fa
SB		 3152 int i = 0;
3153
3154 if (!netif_running(netdev))
3155 return 0;
3156
51956cd6
SB		 3157 for (i = 0; i < adapter->num_rx_queues; i++)
3158 napi_disable(&adapter->rx_queue[i].napi);
3159
d1a890fa
SB		 3160 vmxnet3_disable_all_intrs(adapter);
3161 vmxnet3_free_irqs(adapter);
3162 vmxnet3_free_intr_resources(adapter);
3163
3164 netif_device_detach(netdev);
09c5088e 3165 netif_tx_stop_all_queues(netdev);
d1a890fa
SB		 3166
3167 /* Create wake-up filters. */
3168 pmConf = adapter->pm_conf;
3169 memset(pmConf, 0, sizeof(*pmConf));
3170
3171 if (adapter->wol & WAKE_UCAST) {
3172 pmConf->filters[i].patternSize = ETH_ALEN;
3173 pmConf->filters[i].maskSize = 1;
3174 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
3175 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
3176
3843e515 3177 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
d1a890fa
SB		 3178 i++;
3179 }
3180
3181 if (adapter->wol & WAKE_ARP) {
3182 in_dev = in_dev_get(netdev);
3183 if (!in_dev)
3184 goto skip_arp;
3185
3186 ifa = (struct in_ifaddr *)in_dev->ifa_list;
3187 if (!ifa)
3188 goto skip_arp;
3189
3190 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
3191 sizeof(struct arphdr) + /* ARP header */
3192 2 * ETH_ALEN + /* 2 Ethernet addresses*/
3193 2 * sizeof(u32); /*2 IPv4 addresses */
3194 pmConf->filters[i].maskSize =
3195 (pmConf->filters[i].patternSize - 1) / 8 + 1;
3196
3197 /* ETH_P_ARP in Ethernet header. */
3198 ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
3199 ehdr->h_proto = htons(ETH_P_ARP);
3200
3201 /* ARPOP_REQUEST in ARP header. */
3202 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
3203 ahdr->ar_op = htons(ARPOP_REQUEST);
3204 arpreq = (u8 *)(ahdr + 1);
3205
3206 /* The Unicast IPv4 address in 'tip' field. */
3207 arpreq += 2 * ETH_ALEN + sizeof(u32);
3208 *(u32 *)arpreq = ifa->ifa_address;
3209
3210 /* The mask for the relevant bits. */
3211 pmConf->filters[i].mask[0] = 0x00;
3212 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
3213 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
3214 pmConf->filters[i].mask[3] = 0x00;
3215 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
3216 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
3217 in_dev_put(in_dev);
3218
3843e515 3219 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
d1a890fa
SB		 3220 i++;
3221 }
3222
3223skip_arp:
3224 if (adapter->wol & WAKE_MAGIC)
3843e515 3225 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
d1a890fa
SB		 3226
3227 pmConf->numFilters = i;
3228
115924b6
SB		 3229 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3230 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3231 *pmConf));
3232 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
3233 pmConf));
d1a890fa 3234
83d0feff 3235 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 3236 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3237 VMXNET3_CMD_UPDATE_PMCFG);
83d0feff 3238 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 3239
3240 pci_save_state(pdev);
3241 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
3242 adapter->wol);
3243 pci_disable_device(pdev);
3244 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
3245
3246 return 0;
3247}
3248
3249
3250static int
3251vmxnet3_resume(struct device *device)
3252{
51956cd6 3253 int err, i = 0;
83d0feff 3254 unsigned long flags;
d1a890fa
SB		 3255 struct pci_dev *pdev = to_pci_dev(device);
3256 struct net_device *netdev = pci_get_drvdata(pdev);
3257 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3258 struct Vmxnet3_PMConf *pmConf;
3259
3260 if (!netif_running(netdev))
3261 return 0;
3262
3263 /* Destroy wake-up filters. */
3264 pmConf = adapter->pm_conf;
3265 memset(pmConf, 0, sizeof(*pmConf));
3266
115924b6
SB		 3267 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3268 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3269 *pmConf));
0561cf3d 3270 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
115924b6 3271 pmConf));
d1a890fa
SB		 3272
3273 netif_device_attach(netdev);
3274 pci_set_power_state(pdev, PCI_D0);
3275 pci_restore_state(pdev);
3276 err = pci_enable_device_mem(pdev);
3277 if (err != 0)
3278 return err;
3279
3280 pci_enable_wake(pdev, PCI_D0, 0);
3281
83d0feff 3282 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 3283 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3284 VMXNET3_CMD_UPDATE_PMCFG);
83d0feff 3285 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 3286 vmxnet3_alloc_intr_resources(adapter);
3287 vmxnet3_request_irqs(adapter);
51956cd6
SB		 3288 for (i = 0; i < adapter->num_rx_queues; i++)
3289 napi_enable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 3290 vmxnet3_enable_all_intrs(adapter);
3291
3292 return 0;
3293}
3294
47145210 3295static const struct dev_pm_ops vmxnet3_pm_ops = {
d1a890fa
SB		 3296 .suspend = vmxnet3_suspend,
3297 .resume = vmxnet3_resume,
3298};
3299#endif
3300
3301static struct pci_driver vmxnet3_driver = {
3302 .name = vmxnet3_driver_name,
3303 .id_table = vmxnet3_pciid_table,
3304 .probe = vmxnet3_probe_device,
3a4751a3 3305 .remove = vmxnet3_remove_device,
d1a890fa
SB		 3306#ifdef CONFIG_PM
3307 .driver.pm = &vmxnet3_pm_ops,
3308#endif
3309};
3310
3311
3312static int __init
3313vmxnet3_init_module(void)
3314{
3315 printk(KERN_INFO "%s - version %s\n", VMXNET3_DRIVER_DESC,
3316 VMXNET3_DRIVER_VERSION_REPORT);
3317 return pci_register_driver(&vmxnet3_driver);
3318}
3319
3320module_init(vmxnet3_init_module);
3321
3322
3323static void
3324vmxnet3_exit_module(void)
3325{
3326 pci_unregister_driver(&vmxnet3_driver);
3327}
3328
3329module_exit(vmxnet3_exit_module);
3330
3331MODULE_AUTHOR("VMware, Inc.");
3332MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
3333MODULE_LICENSE("GPL v2");
3334MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);
kernel source for telekom puls (alcatel/mediatek)