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cxgb3: Fix LRO misalignment
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / korina.c
CommitLineData
ef11291b
FF		 1/*
2 * Driver for the IDT RC32434 (Korina) on-chip ethernet controller.
3 *
4 * Copyright 2004 IDT Inc. (rischelp@idt.com)
5 * Copyright 2006 Felix Fietkau <nbd@openwrt.org>
6 * Copyright 2008 Florian Fainelli <florian@openwrt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 *
28 * Writing to a DMA status register:
29 *
30 * When writing to the status register, you should mask the bit you have
31 * been testing the status register with. Both Tx and Rx DMA registers
32 * should stick to this procedure.
33 */
34
35#include <linux/module.h>
36#include <linux/kernel.h>
37#include <linux/moduleparam.h>
38#include <linux/sched.h>
39#include <linux/ctype.h>
40#include <linux/types.h>
41#include <linux/interrupt.h>
42#include <linux/init.h>
43#include <linux/ioport.h>
44#include <linux/in.h>
45#include <linux/slab.h>
46#include <linux/string.h>
47#include <linux/delay.h>
48#include <linux/netdevice.h>
49#include <linux/etherdevice.h>
50#include <linux/skbuff.h>
51#include <linux/errno.h>
52#include <linux/platform_device.h>
53#include <linux/mii.h>
54#include <linux/ethtool.h>
55#include <linux/crc32.h>
56
57#include <asm/bootinfo.h>
58#include <asm/system.h>
59#include <asm/bitops.h>
60#include <asm/pgtable.h>
61#include <asm/segment.h>
62#include <asm/io.h>
63#include <asm/dma.h>
64
65#include <asm/mach-rc32434/rb.h>
66#include <asm/mach-rc32434/rc32434.h>
67#include <asm/mach-rc32434/eth.h>
68#include <asm/mach-rc32434/dma_v.h>
69
70#define DRV_NAME "korina"
71#define DRV_VERSION "0.10"
72#define DRV_RELDATE "04Mar2008"
73
74#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
75 ((dev)->dev_addr[1]))
76#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
77 ((dev)->dev_addr[3] << 16) | \
78 ((dev)->dev_addr[4] << 8) | \
79 ((dev)->dev_addr[5]))
80
81#define MII_CLOCK 1250000 /* no more than 2.5MHz */
82
83/* the following must be powers of two */
84#define KORINA_NUM_RDS 64 /* number of receive descriptors */
85#define KORINA_NUM_TDS 64 /* number of transmit descriptors */
86
a13b2782
PS		 87/* KORINA_RBSIZE is the hardware's default maximum receive
88 * frame size in bytes. Having this hardcoded means that there
89 * is no support for MTU sizes greater than 1500. */
90#define KORINA_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
ef11291b
FF		 91#define KORINA_RDS_MASK (KORINA_NUM_RDS - 1)
92#define KORINA_TDS_MASK (KORINA_NUM_TDS - 1)
93#define RD_RING_SIZE (KORINA_NUM_RDS * sizeof(struct dma_desc))
94#define TD_RING_SIZE (KORINA_NUM_TDS * sizeof(struct dma_desc))
95
96#define TX_TIMEOUT (6000 * HZ / 1000)
97
98enum chain_status { desc_filled, desc_empty };
99#define IS_DMA_FINISHED(X) (((X) & (DMA_DESC_FINI)) != 0)
100#define IS_DMA_DONE(X) (((X) & (DMA_DESC_DONE)) != 0)
101#define RCVPKT_LENGTH(X) (((X) & ETH_RX_LEN) >> ETH_RX_LEN_BIT)
102
103/* Information that need to be kept for each board. */
104struct korina_private {
105 struct eth_regs *eth_regs;
106 struct dma_reg *rx_dma_regs;
107 struct dma_reg *tx_dma_regs;
108 struct dma_desc *td_ring; /* transmit descriptor ring */
109 struct dma_desc *rd_ring; /* receive descriptor ring */
110
111 struct sk_buff *tx_skb[KORINA_NUM_TDS];
112 struct sk_buff *rx_skb[KORINA_NUM_RDS];
113
114 int rx_next_done;
115 int rx_chain_head;
116 int rx_chain_tail;
117 enum chain_status rx_chain_status;
118
119 int tx_next_done;
120 int tx_chain_head;
121 int tx_chain_tail;
122 enum chain_status tx_chain_status;
123 int tx_count;
124 int tx_full;
125
126 int rx_irq;
127 int tx_irq;
128 int ovr_irq;
129 int und_irq;
130
131 spinlock_t lock; /* NIC xmit lock */
132
133 int dma_halt_cnt;
134 int dma_run_cnt;
135 struct napi_struct napi;
136 struct mii_if_info mii_if;
137 struct net_device *dev;
138 int phy_addr;
139};
140
141extern unsigned int idt_cpu_freq;
142
143static inline void korina_start_dma(struct dma_reg *ch, u32 dma_addr)
144{
145 writel(0, &ch->dmandptr);
146 writel(dma_addr, &ch->dmadptr);
147}
148
149static inline void korina_abort_dma(struct net_device *dev,
150 struct dma_reg *ch)
151{
152 if (readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
153 writel(0x10, &ch->dmac);
154
155 while (!(readl(&ch->dmas) & DMA_STAT_HALT))
156 dev->trans_start = jiffies;
157
158 writel(0, &ch->dmas);
159 }
160
161 writel(0, &ch->dmadptr);
162 writel(0, &ch->dmandptr);
163}
164
165static inline void korina_chain_dma(struct dma_reg *ch, u32 dma_addr)
166{
167 writel(dma_addr, &ch->dmandptr);
168}
169
170static void korina_abort_tx(struct net_device *dev)
171{
172 struct korina_private *lp = netdev_priv(dev);
173
174 korina_abort_dma(dev, lp->tx_dma_regs);
175}
176
177static void korina_abort_rx(struct net_device *dev)
178{
179 struct korina_private *lp = netdev_priv(dev);
180
181 korina_abort_dma(dev, lp->rx_dma_regs);
182}
183
184static void korina_start_rx(struct korina_private *lp,
185 struct dma_desc *rd)
186{
187 korina_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
188}
189
190static void korina_chain_rx(struct korina_private *lp,
191 struct dma_desc *rd)
192{
193 korina_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
194}
195
196/* transmit packet */
197static int korina_send_packet(struct sk_buff *skb, struct net_device *dev)
198{
199 struct korina_private *lp = netdev_priv(dev);
200 unsigned long flags;
201 u32 length;
97bc477c 202 u32 chain_prev, chain_next;
ef11291b
FF		 203 struct dma_desc *td;
204
205 spin_lock_irqsave(&lp->lock, flags);
206
207 td = &lp->td_ring[lp->tx_chain_tail];
208
209 /* stop queue when full, drop pkts if queue already full */
210 if (lp->tx_count >= (KORINA_NUM_TDS - 2)) {
211 lp->tx_full = 1;
212
213 if (lp->tx_count == (KORINA_NUM_TDS - 2))
214 netif_stop_queue(dev);
215 else {
216 dev->stats.tx_dropped++;
217 dev_kfree_skb_any(skb);
218 spin_unlock_irqrestore(&lp->lock, flags);
219
220 return NETDEV_TX_BUSY;
221 }
222 }
223
224 lp->tx_count++;
225
226 lp->tx_skb[lp->tx_chain_tail] = skb;
227
228 length = skb->len;
229 dma_cache_wback((u32)skb->data, skb->len);
230
231 /* Setup the transmit descriptor. */
232 dma_cache_inv((u32) td, sizeof(*td));
233 td->ca = CPHYSADDR(skb->data);
97bc477c
PS		 234 chain_prev = (lp->tx_chain_tail - 1) & KORINA_TDS_MASK;
235 chain_next = (lp->tx_chain_tail + 1) & KORINA_TDS_MASK;
ef11291b
FF		 236
237 if (readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
238 if (lp->tx_chain_status == desc_empty) {
239 /* Update tail */
240 td->control = DMA_COUNT(length) |
241 DMA_DESC_COF | DMA_DESC_IOF;
242 /* Move tail */
97bc477c 243 lp->tx_chain_tail = chain_next;
ef11291b
FF		 244 /* Write to NDPTR */
245 writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
246 &lp->tx_dma_regs->dmandptr);
247 /* Move head to tail */
248 lp->tx_chain_head = lp->tx_chain_tail;
249 } else {
250 /* Update tail */
251 td->control = DMA_COUNT(length) |
252 DMA_DESC_COF | DMA_DESC_IOF;
253 /* Link to prev */
97bc477c 254 lp->td_ring[chain_prev].control &=
ef11291b
FF		 255 ~DMA_DESC_COF;
256 /* Link to prev */
97bc477c 257 lp->td_ring[chain_prev].link = CPHYSADDR(td);
ef11291b 258 /* Move tail */
97bc477c 259 lp->tx_chain_tail = chain_next;
ef11291b
FF		 260 /* Write to NDPTR */
261 writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
262 &(lp->tx_dma_regs->dmandptr));
263 /* Move head to tail */
264 lp->tx_chain_head = lp->tx_chain_tail;
265 lp->tx_chain_status = desc_empty;
266 }
267 } else {
268 if (lp->tx_chain_status == desc_empty) {
269 /* Update tail */
270 td->control = DMA_COUNT(length) |
271 DMA_DESC_COF | DMA_DESC_IOF;
272 /* Move tail */
97bc477c 273 lp->tx_chain_tail = chain_next;
ef11291b 274 lp->tx_chain_status = desc_filled;
ef11291b
FF		 275 } else {
276 /* Update tail */
277 td->control = DMA_COUNT(length) |
278 DMA_DESC_COF | DMA_DESC_IOF;
97bc477c 279 lp->td_ring[chain_prev].control &=
ef11291b 280 ~DMA_DESC_COF;
97bc477c
PS		 281 lp->td_ring[chain_prev].link = CPHYSADDR(td);
282 lp->tx_chain_tail = chain_next;
ef11291b
FF		 283 }
284 }
285 dma_cache_wback((u32) td, sizeof(*td));
286
287 dev->trans_start = jiffies;
288 spin_unlock_irqrestore(&lp->lock, flags);
289
290 return NETDEV_TX_OK;
291}
292
293static int mdio_read(struct net_device *dev, int mii_id, int reg)
294{
295 struct korina_private *lp = netdev_priv(dev);
296 int ret;
297
298 mii_id = ((lp->rx_irq == 0x2c ? 1 : 0) << 8);
299
300 writel(0, &lp->eth_regs->miimcfg);
301 writel(0, &lp->eth_regs->miimcmd);
302 writel(mii_id | reg, &lp->eth_regs->miimaddr);
303 writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd);
304
305 ret = (int)(readl(&lp->eth_regs->miimrdd));
306 return ret;
307}
308
309static void mdio_write(struct net_device *dev, int mii_id, int reg, int val)
310{
311 struct korina_private *lp = netdev_priv(dev);
312
313 mii_id = ((lp->rx_irq == 0x2c ? 1 : 0) << 8);
314
315 writel(0, &lp->eth_regs->miimcfg);
316 writel(1, &lp->eth_regs->miimcmd);
317 writel(mii_id | reg, &lp->eth_regs->miimaddr);
318 writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd);
319 writel(val, &lp->eth_regs->miimwtd);
320}
321
322/* Ethernet Rx DMA interrupt */
323static irqreturn_t korina_rx_dma_interrupt(int irq, void *dev_id)
324{
325 struct net_device *dev = dev_id;
326 struct korina_private *lp = netdev_priv(dev);
327 u32 dmas, dmasm;
328 irqreturn_t retval;
329
330 dmas = readl(&lp->rx_dma_regs->dmas);
331 if (dmas & (DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR)) {
ef11291b
FF		 332 dmasm = readl(&lp->rx_dma_regs->dmasm);
333 writel(dmasm | (DMA_STAT_DONE |
334 DMA_STAT_HALT | DMA_STAT_ERR),
335 &lp->rx_dma_regs->dmasm);
336
60d3f982
PS		 337 netif_rx_schedule(&lp->napi);
338
ef11291b
FF		 339 if (dmas & DMA_STAT_ERR)
340 printk(KERN_ERR DRV_NAME "%s: DMA error\n", dev->name);
341
342 retval = IRQ_HANDLED;
343 } else
344 retval = IRQ_NONE;
345
346 return retval;
347}
348
349static int korina_rx(struct net_device *dev, int limit)
350{
351 struct korina_private *lp = netdev_priv(dev);
352 struct dma_desc *rd = &lp->rd_ring[lp->rx_next_done];
353 struct sk_buff *skb, *skb_new;
354 u8 *pkt_buf;
4cf83b66 355 u32 devcs, pkt_len, dmas;
ef11291b
FF		 356 int count;
357
358 dma_cache_inv((u32)rd, sizeof(*rd));
359
360 for (count = 0; count < limit; count++) {
4cf83b66
PS		 361 skb = lp->rx_skb[lp->rx_next_done];
362 skb_new = NULL;
ef11291b
FF		 363
364 devcs = rd->devcs;
365
4cf83b66
PS		 366 if ((KORINA_RBSIZE - (u32)DMA_COUNT(rd->control)) == 0)
367 break;
368
ef11291b
FF		 369 /* Update statistics counters */
370 if (devcs & ETH_RX_CRC)
371 dev->stats.rx_crc_errors++;
372 if (devcs & ETH_RX_LOR)
373 dev->stats.rx_length_errors++;
374 if (devcs & ETH_RX_LE)
375 dev->stats.rx_length_errors++;
376 if (devcs & ETH_RX_OVR)
377 dev->stats.rx_over_errors++;
378 if (devcs & ETH_RX_CV)
379 dev->stats.rx_frame_errors++;
380 if (devcs & ETH_RX_CES)
381 dev->stats.rx_length_errors++;
382 if (devcs & ETH_RX_MP)
383 dev->stats.multicast++;
384
385 if ((devcs & ETH_RX_LD) != ETH_RX_LD) {
386 /* check that this is a whole packet
387 * WARNING: DMA_FD bit incorrectly set
388 * in Rc32434 (errata ref #077) */
389 dev->stats.rx_errors++;
390 dev->stats.rx_dropped++;
4cf83b66 391 } else if ((devcs & ETH_RX_ROK)) {
ef11291b 392 pkt_len = RCVPKT_LENGTH(devcs);
4cf83b66
PS		 393
394 /* must be the (first and) last
395 * descriptor then */
396 pkt_buf = (u8 *)lp->rx_skb[lp->rx_next_done]->data;
397
398 /* invalidate the cache */
399 dma_cache_inv((unsigned long)pkt_buf, pkt_len - 4);
400
401 /* Malloc up new buffer. */
402 skb_new = netdev_alloc_skb(dev, KORINA_RBSIZE + 2);
403
404 if (!skb_new)
405 break;
406 /* Do not count the CRC */
407 skb_put(skb, pkt_len - 4);
408 skb->protocol = eth_type_trans(skb, dev);
409
410 /* Pass the packet to upper layers */
411 netif_receive_skb(skb);
412 dev->stats.rx_packets++;
413 dev->stats.rx_bytes += pkt_len;
414
415 /* Update the mcast stats */
416 if (devcs & ETH_RX_MP)
417 dev->stats.multicast++;
418
419 lp->rx_skb[lp->rx_next_done] = skb_new;
ef11291b 420 }
4cf83b66
PS		 421
422 rd->devcs = 0;
423
424 /* Restore descriptor's curr_addr */
425 if (skb_new)
426 rd->ca = CPHYSADDR(skb_new->data);
427 else
428 rd->ca = CPHYSADDR(skb->data);
429
430 rd->control = DMA_COUNT(KORINA_RBSIZE) |
431 DMA_DESC_COD | DMA_DESC_IOD;
432 lp->rd_ring[(lp->rx_next_done - 1) &
433 KORINA_RDS_MASK].control &=
434 ~DMA_DESC_COD;
435
436 lp->rx_next_done = (lp->rx_next_done + 1) & KORINA_RDS_MASK;
437 dma_cache_wback((u32)rd, sizeof(*rd));
438 rd = &lp->rd_ring[lp->rx_next_done];
439 writel(~DMA_STAT_DONE, &lp->rx_dma_regs->dmas);
ef11291b
FF		 440 }
441
442 dmas = readl(&lp->rx_dma_regs->dmas);
443
444 if (dmas & DMA_STAT_HALT) {
445 writel(~(DMA_STAT_HALT | DMA_STAT_ERR),
446 &lp->rx_dma_regs->dmas);
447
448 lp->dma_halt_cnt++;
449 rd->devcs = 0;
450 skb = lp->rx_skb[lp->rx_next_done];
451 rd->ca = CPHYSADDR(skb->data);
452 dma_cache_wback((u32)rd, sizeof(*rd));
453 korina_chain_rx(lp, rd);
454 }
455
456 return count;
457}
458
459static int korina_poll(struct napi_struct *napi, int budget)
460{
461 struct korina_private *lp =
462 container_of(napi, struct korina_private, napi);
463 struct net_device *dev = lp->dev;
464 int work_done;
465
466 work_done = korina_rx(dev, budget);
467 if (work_done < budget) {
908a7a16 468 netif_rx_complete(napi);
ef11291b
FF		 469
470 writel(readl(&lp->rx_dma_regs->dmasm) &
471 ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR),
472 &lp->rx_dma_regs->dmasm);
473 }
474 return work_done;
475}
476
477/*
478 * Set or clear the multicast filter for this adaptor.
479 */
480static void korina_multicast_list(struct net_device *dev)
481{
482 struct korina_private *lp = netdev_priv(dev);
483 unsigned long flags;
484 struct dev_mc_list *dmi = dev->mc_list;
485 u32 recognise = ETH_ARC_AB; /* always accept broadcasts */
486 int i;
487
488 /* Set promiscuous mode */
489 if (dev->flags & IFF_PROMISC)
490 recognise |= ETH_ARC_PRO;
491
492 else if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 4))
493 /* All multicast and broadcast */
494 recognise |= ETH_ARC_AM;
495
496 /* Build the hash table */
497 if (dev->mc_count > 4) {
498 u16 hash_table[4];
499 u32 crc;
500
501 for (i = 0; i < 4; i++)
502 hash_table[i] = 0;
503
504 for (i = 0; i < dev->mc_count; i++) {
505 char *addrs = dmi->dmi_addr;
506
507 dmi = dmi->next;
508
509 if (!(*addrs & 1))
510 continue;
511
512 crc = ether_crc_le(6, addrs);
513 crc >>= 26;
514 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
515 }
516 /* Accept filtered multicast */
517 recognise |= ETH_ARC_AFM;
518
519 /* Fill the MAC hash tables with their values */
520 writel((u32)(hash_table[1] << 16 | hash_table[0]),
521 &lp->eth_regs->ethhash0);
522 writel((u32)(hash_table[3] << 16 | hash_table[2]),
523 &lp->eth_regs->ethhash1);
524 }
525
526 spin_lock_irqsave(&lp->lock, flags);
527 writel(recognise, &lp->eth_regs->etharc);
528 spin_unlock_irqrestore(&lp->lock, flags);
529}
530
531static void korina_tx(struct net_device *dev)
532{
533 struct korina_private *lp = netdev_priv(dev);
534 struct dma_desc *td = &lp->td_ring[lp->tx_next_done];
535 u32 devcs;
536 u32 dmas;
537
538 spin_lock(&lp->lock);
539
540 /* Process all desc that are done */
541 while (IS_DMA_FINISHED(td->control)) {
542 if (lp->tx_full == 1) {
543 netif_wake_queue(dev);
544 lp->tx_full = 0;
545 }
546
547 devcs = lp->td_ring[lp->tx_next_done].devcs;
548 if ((devcs & (ETH_TX_FD | ETH_TX_LD)) !=
549 (ETH_TX_FD | ETH_TX_LD)) {
550 dev->stats.tx_errors++;
551 dev->stats.tx_dropped++;
552
553 /* Should never happen */
554 printk(KERN_ERR DRV_NAME "%s: split tx ignored\n",
555 dev->name);
556 } else if (devcs & ETH_TX_TOK) {
557 dev->stats.tx_packets++;
558 dev->stats.tx_bytes +=
559 lp->tx_skb[lp->tx_next_done]->len;
560 } else {
561 dev->stats.tx_errors++;
562 dev->stats.tx_dropped++;
563
564 /* Underflow */
565 if (devcs & ETH_TX_UND)
566 dev->stats.tx_fifo_errors++;
567
568 /* Oversized frame */
569 if (devcs & ETH_TX_OF)
570 dev->stats.tx_aborted_errors++;
571
572 /* Excessive deferrals */
573 if (devcs & ETH_TX_ED)
574 dev->stats.tx_carrier_errors++;
575
576 /* Collisions: medium busy */
577 if (devcs & ETH_TX_EC)
578 dev->stats.collisions++;
579
580 /* Late collision */
581 if (devcs & ETH_TX_LC)
582 dev->stats.tx_window_errors++;
583 }
584
585 /* We must always free the original skb */
586 if (lp->tx_skb[lp->tx_next_done]) {
587 dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
588 lp->tx_skb[lp->tx_next_done] = NULL;
589 }
590
591 lp->td_ring[lp->tx_next_done].control = DMA_DESC_IOF;
592 lp->td_ring[lp->tx_next_done].devcs = ETH_TX_FD | ETH_TX_LD;
593 lp->td_ring[lp->tx_next_done].link = 0;
594 lp->td_ring[lp->tx_next_done].ca = 0;
595 lp->tx_count--;
596
597 /* Go on to next transmission */
598 lp->tx_next_done = (lp->tx_next_done + 1) & KORINA_TDS_MASK;
599 td = &lp->td_ring[lp->tx_next_done];
600
601 }
602
603 /* Clear the DMA status register */
604 dmas = readl(&lp->tx_dma_regs->dmas);
605 writel(~dmas, &lp->tx_dma_regs->dmas);
606
607 writel(readl(&lp->tx_dma_regs->dmasm) &
608 ~(DMA_STAT_FINI | DMA_STAT_ERR),
609 &lp->tx_dma_regs->dmasm);
610
611 spin_unlock(&lp->lock);
612}
613
614static irqreturn_t
615korina_tx_dma_interrupt(int irq, void *dev_id)
616{
617 struct net_device *dev = dev_id;
618 struct korina_private *lp = netdev_priv(dev);
619 u32 dmas, dmasm;
620 irqreturn_t retval;
621
622 dmas = readl(&lp->tx_dma_regs->dmas);
623
624 if (dmas & (DMA_STAT_FINI | DMA_STAT_ERR)) {
ef11291b
FF		 625 dmasm = readl(&lp->tx_dma_regs->dmasm);
626 writel(dmasm | (DMA_STAT_FINI | DMA_STAT_ERR),
627 &lp->tx_dma_regs->dmasm);
628
60d3f982
PS		 629 korina_tx(dev);
630
ef11291b
FF		 631 if (lp->tx_chain_status == desc_filled &&
632 (readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
633 writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
634 &(lp->tx_dma_regs->dmandptr));
635 lp->tx_chain_status = desc_empty;
636 lp->tx_chain_head = lp->tx_chain_tail;
637 dev->trans_start = jiffies;
638 }
639 if (dmas & DMA_STAT_ERR)
640 printk(KERN_ERR DRV_NAME "%s: DMA error\n", dev->name);
641
642 retval = IRQ_HANDLED;
643 } else
644 retval = IRQ_NONE;
645
646 return retval;
647}
648
649
650static void korina_check_media(struct net_device *dev, unsigned int init_media)
651{
652 struct korina_private *lp = netdev_priv(dev);
653
654 mii_check_media(&lp->mii_if, 0, init_media);
655
656 if (lp->mii_if.full_duplex)
657 writel(readl(&lp->eth_regs->ethmac2) | ETH_MAC2_FD,
658 &lp->eth_regs->ethmac2);
659 else
660 writel(readl(&lp->eth_regs->ethmac2) & ~ETH_MAC2_FD,
661 &lp->eth_regs->ethmac2);
662}
663
664static void korina_set_carrier(struct mii_if_info *mii)
665{
666 if (mii->force_media) {
667 /* autoneg is off: Link is always assumed to be up */
668 if (!netif_carrier_ok(mii->dev))
669 netif_carrier_on(mii->dev);
670 } else /* Let MMI library update carrier status */
671 korina_check_media(mii->dev, 0);
672}
673
674static int korina_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
675{
676 struct korina_private *lp = netdev_priv(dev);
677 struct mii_ioctl_data *data = if_mii(rq);
678 int rc;
679
680 if (!netif_running(dev))
681 return -EINVAL;
682 spin_lock_irq(&lp->lock);
683 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
684 spin_unlock_irq(&lp->lock);
685 korina_set_carrier(&lp->mii_if);
686
687 return rc;
688}
689
690/* ethtool helpers */
691static void netdev_get_drvinfo(struct net_device *dev,
692 struct ethtool_drvinfo *info)
693{
694 struct korina_private *lp = netdev_priv(dev);
695
696 strcpy(info->driver, DRV_NAME);
697 strcpy(info->version, DRV_VERSION);
698 strcpy(info->bus_info, lp->dev->name);
699}
700
701static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
702{
703 struct korina_private *lp = netdev_priv(dev);
704 int rc;
705
706 spin_lock_irq(&lp->lock);
707 rc = mii_ethtool_gset(&lp->mii_if, cmd);
708 spin_unlock_irq(&lp->lock);
709
710 return rc;
711}
712
713static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
714{
715 struct korina_private *lp = netdev_priv(dev);
716 int rc;
717
718 spin_lock_irq(&lp->lock);
719 rc = mii_ethtool_sset(&lp->mii_if, cmd);
720 spin_unlock_irq(&lp->lock);
721 korina_set_carrier(&lp->mii_if);
722
723 return rc;
724}
725
726static u32 netdev_get_link(struct net_device *dev)
727{
728 struct korina_private *lp = netdev_priv(dev);
729
730 return mii_link_ok(&lp->mii_if);
731}
732
733static struct ethtool_ops netdev_ethtool_ops = {
734 .get_drvinfo = netdev_get_drvinfo,
735 .get_settings = netdev_get_settings,
736 .set_settings = netdev_set_settings,
737 .get_link = netdev_get_link,
738};
739
740static void korina_alloc_ring(struct net_device *dev)
741{
742 struct korina_private *lp = netdev_priv(dev);
743 int i;
744
745 /* Initialize the transmit descriptors */
746 for (i = 0; i < KORINA_NUM_TDS; i++) {
747 lp->td_ring[i].control = DMA_DESC_IOF;
748 lp->td_ring[i].devcs = ETH_TX_FD | ETH_TX_LD;
749 lp->td_ring[i].ca = 0;
750 lp->td_ring[i].link = 0;
751 }
752 lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail =
753 lp->tx_full = lp->tx_count = 0;
754 lp->tx_chain_status = desc_empty;
755
756 /* Initialize the receive descriptors */
757 for (i = 0; i < KORINA_NUM_RDS; i++) {
758 struct sk_buff *skb = lp->rx_skb[i];
759
760 skb = dev_alloc_skb(KORINA_RBSIZE + 2);
761 if (!skb)
762 break;
763 skb_reserve(skb, 2);
764 lp->rx_skb[i] = skb;
765 lp->rd_ring[i].control = DMA_DESC_IOD |
766 DMA_COUNT(KORINA_RBSIZE);
767 lp->rd_ring[i].devcs = 0;
768 lp->rd_ring[i].ca = CPHYSADDR(skb->data);
769 lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
770 }
771
772 /* loop back */
773 lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[0]);
774 lp->rx_next_done = 0;
775
776 lp->rd_ring[i].control |= DMA_DESC_COD;
777 lp->rx_chain_head = 0;
778 lp->rx_chain_tail = 0;
779 lp->rx_chain_status = desc_empty;
780}
781
782static void korina_free_ring(struct net_device *dev)
783{
784 struct korina_private *lp = netdev_priv(dev);
785 int i;
786
787 for (i = 0; i < KORINA_NUM_RDS; i++) {
788 lp->rd_ring[i].control = 0;
789 if (lp->rx_skb[i])
790 dev_kfree_skb_any(lp->rx_skb[i]);
791 lp->rx_skb[i] = NULL;
792 }
793
794 for (i = 0; i < KORINA_NUM_TDS; i++) {
795 lp->td_ring[i].control = 0;
796 if (lp->tx_skb[i])
797 dev_kfree_skb_any(lp->tx_skb[i]);
798 lp->tx_skb[i] = NULL;
799 }
800}
801
802/*
803 * Initialize the RC32434 ethernet controller.
804 */
805static int korina_init(struct net_device *dev)
806{
807 struct korina_private *lp = netdev_priv(dev);
808
809 /* Disable DMA */
810 korina_abort_tx(dev);
811 korina_abort_rx(dev);
812
813 /* reset ethernet logic */
814 writel(0, &lp->eth_regs->ethintfc);
815 while ((readl(&lp->eth_regs->ethintfc) & ETH_INT_FC_RIP))
816 dev->trans_start = jiffies;
817
818 /* Enable Ethernet Interface */
819 writel(ETH_INT_FC_EN, &lp->eth_regs->ethintfc);
820
821 /* Allocate rings */
822 korina_alloc_ring(dev);
823
824 writel(0, &lp->rx_dma_regs->dmas);
825 /* Start Rx DMA */
826 korina_start_rx(lp, &lp->rd_ring[0]);
827
828 writel(readl(&lp->tx_dma_regs->dmasm) &
829 ~(DMA_STAT_FINI | DMA_STAT_ERR),
830 &lp->tx_dma_regs->dmasm);
831 writel(readl(&lp->rx_dma_regs->dmasm) &
832 ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR),
833 &lp->rx_dma_regs->dmasm);
834
835 /* Accept only packets destined for this Ethernet device address */
836 writel(ETH_ARC_AB, &lp->eth_regs->etharc);
837
838 /* Set all Ether station address registers to their initial values */
839 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
840 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
841
842 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
843 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
844
845 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
846 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
847
848 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
849 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
850
851
852 /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
853 writel(ETH_MAC2_PE | ETH_MAC2_CEN | ETH_MAC2_FD,
854 &lp->eth_regs->ethmac2);
855
856 /* Back to back inter-packet-gap */
857 writel(0x15, &lp->eth_regs->ethipgt);
858 /* Non - Back to back inter-packet-gap */
859 writel(0x12, &lp->eth_regs->ethipgr);
860
861 /* Management Clock Prescaler Divisor
862 * Clock independent setting */
863 writel(((idt_cpu_freq) / MII_CLOCK + 1) & ~1,
864 &lp->eth_regs->ethmcp);
865
866 /* don't transmit until fifo contains 48b */
867 writel(48, &lp->eth_regs->ethfifott);
868
869 writel(ETH_MAC1_RE, &lp->eth_regs->ethmac1);
870
871 napi_enable(&lp->napi);
872 netif_start_queue(dev);
873
874 return 0;
875}
876
877/*
878 * Restart the RC32434 ethernet controller.
879 * FIXME: check the return status where we call it
880 */
881static int korina_restart(struct net_device *dev)
882{
883 struct korina_private *lp = netdev_priv(dev);
e3152ab9 884 int ret;
ef11291b
FF		 885
886 /*
887 * Disable interrupts
888 */
889 disable_irq(lp->rx_irq);
890 disable_irq(lp->tx_irq);
891 disable_irq(lp->ovr_irq);
892 disable_irq(lp->und_irq);
893
894 writel(readl(&lp->tx_dma_regs->dmasm) |
895 DMA_STAT_FINI | DMA_STAT_ERR,
896 &lp->tx_dma_regs->dmasm);
897 writel(readl(&lp->rx_dma_regs->dmasm) |
898 DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR,
899 &lp->rx_dma_regs->dmasm);
900
901 korina_free_ring(dev);
902
beb0babf
PS		 903 napi_disable(&lp->napi);
904
ef11291b
FF		 905 ret = korina_init(dev);
906 if (ret < 0) {
907 printk(KERN_ERR DRV_NAME "%s: cannot restart device\n",
908 dev->name);
909 return ret;
910 }
911 korina_multicast_list(dev);
912
913 enable_irq(lp->und_irq);
914 enable_irq(lp->ovr_irq);
915 enable_irq(lp->tx_irq);
916 enable_irq(lp->rx_irq);
917
918 return ret;
919}
920
921static void korina_clear_and_restart(struct net_device *dev, u32 value)
922{
923 struct korina_private *lp = netdev_priv(dev);
924
925 netif_stop_queue(dev);
926 writel(value, &lp->eth_regs->ethintfc);
927 korina_restart(dev);
928}
929
930/* Ethernet Tx Underflow interrupt */
931static irqreturn_t korina_und_interrupt(int irq, void *dev_id)
932{
933 struct net_device *dev = dev_id;
934 struct korina_private *lp = netdev_priv(dev);
935 unsigned int und;
936
937 spin_lock(&lp->lock);
938
939 und = readl(&lp->eth_regs->ethintfc);
940
941 if (und & ETH_INT_FC_UND)
942 korina_clear_and_restart(dev, und & ~ETH_INT_FC_UND);
943
944 spin_unlock(&lp->lock);
945
946 return IRQ_HANDLED;
947}
948
949static void korina_tx_timeout(struct net_device *dev)
950{
951 struct korina_private *lp = netdev_priv(dev);
952 unsigned long flags;
953
954 spin_lock_irqsave(&lp->lock, flags);
955 korina_restart(dev);
956 spin_unlock_irqrestore(&lp->lock, flags);
957}
958
959/* Ethernet Rx Overflow interrupt */
960static irqreturn_t
961korina_ovr_interrupt(int irq, void *dev_id)
962{
963 struct net_device *dev = dev_id;
964 struct korina_private *lp = netdev_priv(dev);
965 unsigned int ovr;
966
967 spin_lock(&lp->lock);
968 ovr = readl(&lp->eth_regs->ethintfc);
969
970 if (ovr & ETH_INT_FC_OVR)
971 korina_clear_and_restart(dev, ovr & ~ETH_INT_FC_OVR);
972
973 spin_unlock(&lp->lock);
974
975 return IRQ_HANDLED;
976}
977
978#ifdef CONFIG_NET_POLL_CONTROLLER
979static void korina_poll_controller(struct net_device *dev)
980{
981 disable_irq(dev->irq);
982 korina_tx_dma_interrupt(dev->irq, dev);
983 enable_irq(dev->irq);
984}
985#endif
986
987static int korina_open(struct net_device *dev)
988{
989 struct korina_private *lp = netdev_priv(dev);
e3152ab9 990 int ret;
ef11291b
FF		 991
992 /* Initialize */
993 ret = korina_init(dev);
994 if (ret < 0) {
995 printk(KERN_ERR DRV_NAME "%s: cannot open device\n", dev->name);
996 goto out;
997 }
998
999 /* Install the interrupt handler
1000 * that handles the Done Finished
1001 * Ovr and Und Events */
1002 ret = request_irq(lp->rx_irq, &korina_rx_dma_interrupt,
1c5625cf 1003 IRQF_DISABLED, "Korina ethernet Rx", dev);
ef11291b
FF		 1004 if (ret < 0) {
1005 printk(KERN_ERR DRV_NAME "%s: unable to get Rx DMA IRQ %d\n",
1006 dev->name, lp->rx_irq);
1007 goto err_release;
1008 }
1009 ret = request_irq(lp->tx_irq, &korina_tx_dma_interrupt,
1c5625cf 1010 IRQF_DISABLED, "Korina ethernet Tx", dev);
ef11291b
FF		 1011 if (ret < 0) {
1012 printk(KERN_ERR DRV_NAME "%s: unable to get Tx DMA IRQ %d\n",
1013 dev->name, lp->tx_irq);
1014 goto err_free_rx_irq;
1015 }
1016
1017 /* Install handler for overrun error. */
1018 ret = request_irq(lp->ovr_irq, &korina_ovr_interrupt,
1c5625cf 1019 IRQF_DISABLED, "Ethernet Overflow", dev);
ef11291b
FF		 1020 if (ret < 0) {
1021 printk(KERN_ERR DRV_NAME"%s: unable to get OVR IRQ %d\n",
1022 dev->name, lp->ovr_irq);
1023 goto err_free_tx_irq;
1024 }
1025
1026 /* Install handler for underflow error. */
1027 ret = request_irq(lp->und_irq, &korina_und_interrupt,
1c5625cf 1028 IRQF_DISABLED, "Ethernet Underflow", dev);
ef11291b
FF		 1029 if (ret < 0) {
1030 printk(KERN_ERR DRV_NAME "%s: unable to get UND IRQ %d\n",
1031 dev->name, lp->und_irq);
1032 goto err_free_ovr_irq;
1033 }
751c2e47
FR		 1034out:
1035 return ret;
ef11291b
FF		 1036
1037err_free_ovr_irq:
1038 free_irq(lp->ovr_irq, dev);
1039err_free_tx_irq:
1040 free_irq(lp->tx_irq, dev);
1041err_free_rx_irq:
1042 free_irq(lp->rx_irq, dev);
1043err_release:
1044 korina_free_ring(dev);
1045 goto out;
ef11291b
FF		 1046}
1047
1048static int korina_close(struct net_device *dev)
1049{
1050 struct korina_private *lp = netdev_priv(dev);
1051 u32 tmp;
1052
1053 /* Disable interrupts */
1054 disable_irq(lp->rx_irq);
1055 disable_irq(lp->tx_irq);
1056 disable_irq(lp->ovr_irq);
1057 disable_irq(lp->und_irq);
1058
1059 korina_abort_tx(dev);
1060 tmp = readl(&lp->tx_dma_regs->dmasm);
1061 tmp = tmp | DMA_STAT_FINI | DMA_STAT_ERR;
1062 writel(tmp, &lp->tx_dma_regs->dmasm);
1063
1064 korina_abort_rx(dev);
1065 tmp = readl(&lp->rx_dma_regs->dmasm);
1066 tmp = tmp | DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR;
1067 writel(tmp, &lp->rx_dma_regs->dmasm);
1068
1069 korina_free_ring(dev);
1070
beb0babf
PS		 1071 napi_disable(&lp->napi);
1072
ef11291b
FF		 1073 free_irq(lp->rx_irq, dev);
1074 free_irq(lp->tx_irq, dev);
1075 free_irq(lp->ovr_irq, dev);
1076 free_irq(lp->und_irq, dev);
1077
1078 return 0;
1079}
1080
1081static int korina_probe(struct platform_device *pdev)
1082{
1083 struct korina_device *bif = platform_get_drvdata(pdev);
1084 struct korina_private *lp;
1085 struct net_device *dev;
1086 struct resource *r;
e3152ab9 1087 int rc;
ef11291b
FF		 1088
1089 dev = alloc_etherdev(sizeof(struct korina_private));
1090 if (!dev) {
1091 printk(KERN_ERR DRV_NAME ": alloc_etherdev failed\n");
1092 return -ENOMEM;
1093 }
1094 SET_NETDEV_DEV(dev, &pdev->dev);
ef11291b
FF		 1095 lp = netdev_priv(dev);
1096
1097 bif->dev = dev;
1098 memcpy(dev->dev_addr, bif->mac, 6);
1099
1100 lp->rx_irq = platform_get_irq_byname(pdev, "korina_rx");
1101 lp->tx_irq = platform_get_irq_byname(pdev, "korina_tx");
1102 lp->ovr_irq = platform_get_irq_byname(pdev, "korina_ovr");
1103 lp->und_irq = platform_get_irq_byname(pdev, "korina_und");
1104
1105 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_regs");
1106 dev->base_addr = r->start;
1107 lp->eth_regs = ioremap_nocache(r->start, r->end - r->start);
1108 if (!lp->eth_regs) {
1109 printk(KERN_ERR DRV_NAME "cannot remap registers\n");
e3152ab9 1110 rc = -ENXIO;
ef11291b
FF		 1111 goto probe_err_out;
1112 }
1113
1114 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_rx");
1115 lp->rx_dma_regs = ioremap_nocache(r->start, r->end - r->start);
1116 if (!lp->rx_dma_regs) {
1117 printk(KERN_ERR DRV_NAME "cannot remap Rx DMA registers\n");
e3152ab9 1118 rc = -ENXIO;
ef11291b
FF		 1119 goto probe_err_dma_rx;
1120 }
1121
1122 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_tx");
1123 lp->tx_dma_regs = ioremap_nocache(r->start, r->end - r->start);
1124 if (!lp->tx_dma_regs) {
1125 printk(KERN_ERR DRV_NAME "cannot remap Tx DMA registers\n");
e3152ab9 1126 rc = -ENXIO;
ef11291b
FF		 1127 goto probe_err_dma_tx;
1128 }
1129
1130 lp->td_ring = kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1131 if (!lp->td_ring) {
1132 printk(KERN_ERR DRV_NAME "cannot allocate descriptors\n");
e3152ab9 1133 rc = -ENXIO;
ef11291b
FF		 1134 goto probe_err_td_ring;
1135 }
1136
1137 dma_cache_inv((unsigned long)(lp->td_ring),
1138 TD_RING_SIZE + RD_RING_SIZE);
1139
1140 /* now convert TD_RING pointer to KSEG1 */
1141 lp->td_ring = (struct dma_desc *)KSEG1ADDR(lp->td_ring);
1142 lp->rd_ring = &lp->td_ring[KORINA_NUM_TDS];
1143
1144 spin_lock_init(&lp->lock);
1145 /* just use the rx dma irq */
1146 dev->irq = lp->rx_irq;
1147 lp->dev = dev;
1148
1149 dev->open = korina_open;
1150 dev->stop = korina_close;
1151 dev->hard_start_xmit = korina_send_packet;
1152 dev->set_multicast_list = &korina_multicast_list;
1153 dev->ethtool_ops = &netdev_ethtool_ops;
1154 dev->tx_timeout = korina_tx_timeout;
1155 dev->watchdog_timeo = TX_TIMEOUT;
1156 dev->do_ioctl = &korina_ioctl;
1157#ifdef CONFIG_NET_POLL_CONTROLLER
1158 dev->poll_controller = korina_poll_controller;
1159#endif
1160 netif_napi_add(dev, &lp->napi, korina_poll, 64);
1161
1162 lp->phy_addr = (((lp->rx_irq == 0x2c? 1:0) << 8) | 0x05);
1163 lp->mii_if.dev = dev;
1164 lp->mii_if.mdio_read = mdio_read;
1165 lp->mii_if.mdio_write = mdio_write;
1166 lp->mii_if.phy_id = lp->phy_addr;
1167 lp->mii_if.phy_id_mask = 0x1f;
1168 lp->mii_if.reg_num_mask = 0x1f;
1169
e3152ab9
FR		 1170 rc = register_netdev(dev);
1171 if (rc < 0) {
ef11291b 1172 printk(KERN_ERR DRV_NAME
e3152ab9 1173 ": cannot register net device %d\n", rc);
ef11291b
FF		 1174 goto probe_err_register;
1175 }
e3152ab9
FR		 1176out:
1177 return rc;
ef11291b
FF		 1178
1179probe_err_register:
1180 kfree(lp->td_ring);
1181probe_err_td_ring:
1182 iounmap(lp->tx_dma_regs);
1183probe_err_dma_tx:
1184 iounmap(lp->rx_dma_regs);
1185probe_err_dma_rx:
1186 iounmap(lp->eth_regs);
1187probe_err_out:
1188 free_netdev(dev);
e3152ab9 1189 goto out;
ef11291b
FF		 1190}
1191
1192static int korina_remove(struct platform_device *pdev)
1193{
1194 struct korina_device *bif = platform_get_drvdata(pdev);
1195 struct korina_private *lp = netdev_priv(bif->dev);
1196
e3152ab9
FR		 1197 iounmap(lp->eth_regs);
1198 iounmap(lp->rx_dma_regs);
1199 iounmap(lp->tx_dma_regs);
ef11291b
FF		 1200
1201 platform_set_drvdata(pdev, NULL);
1202 unregister_netdev(bif->dev);
1203 free_netdev(bif->dev);
1204
1205 return 0;
1206}
1207
1208static struct platform_driver korina_driver = {
1209 .driver.name = "korina",
1210 .probe = korina_probe,
1211 .remove = korina_remove,
1212};
1213
1214static int __init korina_init_module(void)
1215{
1216 return platform_driver_register(&korina_driver);
1217}
1218
1219static void korina_cleanup_module(void)
1220{
1221 return platform_driver_unregister(&korina_driver);
1222}
1223
1224module_init(korina_init_module);
1225module_exit(korina_cleanup_module);
1226
1227MODULE_AUTHOR("Philip Rischel <rischelp@idt.com>");
1228MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>");
1229MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
1230MODULE_DESCRIPTION("IDT RC32434 (Korina) Ethernet driver");
1231MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)