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korina: do tx at the right position
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / korina.c
CommitLineData
ef11291b
FF		 1/*
2 * Driver for the IDT RC32434 (Korina) on-chip ethernet controller.
3 *
4 * Copyright 2004 IDT Inc. (rischelp@idt.com)
5 * Copyright 2006 Felix Fietkau <nbd@openwrt.org>
6 * Copyright 2008 Florian Fainelli <florian@openwrt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 *
28 * Writing to a DMA status register:
29 *
30 * When writing to the status register, you should mask the bit you have
31 * been testing the status register with. Both Tx and Rx DMA registers
32 * should stick to this procedure.
33 */
34
35#include <linux/module.h>
36#include <linux/kernel.h>
37#include <linux/moduleparam.h>
38#include <linux/sched.h>
39#include <linux/ctype.h>
40#include <linux/types.h>
41#include <linux/interrupt.h>
42#include <linux/init.h>
43#include <linux/ioport.h>
44#include <linux/in.h>
45#include <linux/slab.h>
46#include <linux/string.h>
47#include <linux/delay.h>
48#include <linux/netdevice.h>
49#include <linux/etherdevice.h>
50#include <linux/skbuff.h>
51#include <linux/errno.h>
52#include <linux/platform_device.h>
53#include <linux/mii.h>
54#include <linux/ethtool.h>
55#include <linux/crc32.h>
56
57#include <asm/bootinfo.h>
58#include <asm/system.h>
59#include <asm/bitops.h>
60#include <asm/pgtable.h>
61#include <asm/segment.h>
62#include <asm/io.h>
63#include <asm/dma.h>
64
65#include <asm/mach-rc32434/rb.h>
66#include <asm/mach-rc32434/rc32434.h>
67#include <asm/mach-rc32434/eth.h>
68#include <asm/mach-rc32434/dma_v.h>
69
70#define DRV_NAME "korina"
71#define DRV_VERSION "0.10"
72#define DRV_RELDATE "04Mar2008"
73
74#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
75 ((dev)->dev_addr[1]))
76#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
77 ((dev)->dev_addr[3] << 16) | \
78 ((dev)->dev_addr[4] << 8) | \
79 ((dev)->dev_addr[5]))
80
81#define MII_CLOCK 1250000 /* no more than 2.5MHz */
82
83/* the following must be powers of two */
84#define KORINA_NUM_RDS 64 /* number of receive descriptors */
85#define KORINA_NUM_TDS 64 /* number of transmit descriptors */
86
a13b2782
PS		 87/* KORINA_RBSIZE is the hardware's default maximum receive
88 * frame size in bytes. Having this hardcoded means that there
89 * is no support for MTU sizes greater than 1500. */
90#define KORINA_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
ef11291b
FF		 91#define KORINA_RDS_MASK (KORINA_NUM_RDS - 1)
92#define KORINA_TDS_MASK (KORINA_NUM_TDS - 1)
93#define RD_RING_SIZE (KORINA_NUM_RDS * sizeof(struct dma_desc))
94#define TD_RING_SIZE (KORINA_NUM_TDS * sizeof(struct dma_desc))
95
96#define TX_TIMEOUT (6000 * HZ / 1000)
97
98enum chain_status { desc_filled, desc_empty };
99#define IS_DMA_FINISHED(X) (((X) & (DMA_DESC_FINI)) != 0)
100#define IS_DMA_DONE(X) (((X) & (DMA_DESC_DONE)) != 0)
101#define RCVPKT_LENGTH(X) (((X) & ETH_RX_LEN) >> ETH_RX_LEN_BIT)
102
103/* Information that need to be kept for each board. */
104struct korina_private {
105 struct eth_regs *eth_regs;
106 struct dma_reg *rx_dma_regs;
107 struct dma_reg *tx_dma_regs;
108 struct dma_desc *td_ring; /* transmit descriptor ring */
109 struct dma_desc *rd_ring; /* receive descriptor ring */
110
111 struct sk_buff *tx_skb[KORINA_NUM_TDS];
112 struct sk_buff *rx_skb[KORINA_NUM_RDS];
113
114 int rx_next_done;
115 int rx_chain_head;
116 int rx_chain_tail;
117 enum chain_status rx_chain_status;
118
119 int tx_next_done;
120 int tx_chain_head;
121 int tx_chain_tail;
122 enum chain_status tx_chain_status;
123 int tx_count;
124 int tx_full;
125
126 int rx_irq;
127 int tx_irq;
128 int ovr_irq;
129 int und_irq;
130
131 spinlock_t lock; /* NIC xmit lock */
132
133 int dma_halt_cnt;
134 int dma_run_cnt;
135 struct napi_struct napi;
136 struct mii_if_info mii_if;
137 struct net_device *dev;
138 int phy_addr;
139};
140
141extern unsigned int idt_cpu_freq;
142
143static inline void korina_start_dma(struct dma_reg *ch, u32 dma_addr)
144{
145 writel(0, &ch->dmandptr);
146 writel(dma_addr, &ch->dmadptr);
147}
148
149static inline void korina_abort_dma(struct net_device *dev,
150 struct dma_reg *ch)
151{
152 if (readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
153 writel(0x10, &ch->dmac);
154
155 while (!(readl(&ch->dmas) & DMA_STAT_HALT))
156 dev->trans_start = jiffies;
157
158 writel(0, &ch->dmas);
159 }
160
161 writel(0, &ch->dmadptr);
162 writel(0, &ch->dmandptr);
163}
164
165static inline void korina_chain_dma(struct dma_reg *ch, u32 dma_addr)
166{
167 writel(dma_addr, &ch->dmandptr);
168}
169
170static void korina_abort_tx(struct net_device *dev)
171{
172 struct korina_private *lp = netdev_priv(dev);
173
174 korina_abort_dma(dev, lp->tx_dma_regs);
175}
176
177static void korina_abort_rx(struct net_device *dev)
178{
179 struct korina_private *lp = netdev_priv(dev);
180
181 korina_abort_dma(dev, lp->rx_dma_regs);
182}
183
184static void korina_start_rx(struct korina_private *lp,
185 struct dma_desc *rd)
186{
187 korina_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
188}
189
190static void korina_chain_rx(struct korina_private *lp,
191 struct dma_desc *rd)
192{
193 korina_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
194}
195
196/* transmit packet */
197static int korina_send_packet(struct sk_buff *skb, struct net_device *dev)
198{
199 struct korina_private *lp = netdev_priv(dev);
200 unsigned long flags;
201 u32 length;
202 u32 chain_index;
203 struct dma_desc *td;
204
205 spin_lock_irqsave(&lp->lock, flags);
206
207 td = &lp->td_ring[lp->tx_chain_tail];
208
209 /* stop queue when full, drop pkts if queue already full */
210 if (lp->tx_count >= (KORINA_NUM_TDS - 2)) {
211 lp->tx_full = 1;
212
213 if (lp->tx_count == (KORINA_NUM_TDS - 2))
214 netif_stop_queue(dev);
215 else {
216 dev->stats.tx_dropped++;
217 dev_kfree_skb_any(skb);
218 spin_unlock_irqrestore(&lp->lock, flags);
219
220 return NETDEV_TX_BUSY;
221 }
222 }
223
224 lp->tx_count++;
225
226 lp->tx_skb[lp->tx_chain_tail] = skb;
227
228 length = skb->len;
229 dma_cache_wback((u32)skb->data, skb->len);
230
231 /* Setup the transmit descriptor. */
232 dma_cache_inv((u32) td, sizeof(*td));
233 td->ca = CPHYSADDR(skb->data);
234 chain_index = (lp->tx_chain_tail - 1) &
235 KORINA_TDS_MASK;
236
237 if (readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
238 if (lp->tx_chain_status == desc_empty) {
239 /* Update tail */
240 td->control = DMA_COUNT(length) |
241 DMA_DESC_COF | DMA_DESC_IOF;
242 /* Move tail */
243 lp->tx_chain_tail = chain_index;
244 /* Write to NDPTR */
245 writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
246 &lp->tx_dma_regs->dmandptr);
247 /* Move head to tail */
248 lp->tx_chain_head = lp->tx_chain_tail;
249 } else {
250 /* Update tail */
251 td->control = DMA_COUNT(length) |
252 DMA_DESC_COF | DMA_DESC_IOF;
253 /* Link to prev */
254 lp->td_ring[chain_index].control &=
255 ~DMA_DESC_COF;
256 /* Link to prev */
257 lp->td_ring[chain_index].link = CPHYSADDR(td);
258 /* Move tail */
259 lp->tx_chain_tail = chain_index;
260 /* Write to NDPTR */
261 writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
262 &(lp->tx_dma_regs->dmandptr));
263 /* Move head to tail */
264 lp->tx_chain_head = lp->tx_chain_tail;
265 lp->tx_chain_status = desc_empty;
266 }
267 } else {
268 if (lp->tx_chain_status == desc_empty) {
269 /* Update tail */
270 td->control = DMA_COUNT(length) |
271 DMA_DESC_COF | DMA_DESC_IOF;
272 /* Move tail */
273 lp->tx_chain_tail = chain_index;
274 lp->tx_chain_status = desc_filled;
275 netif_stop_queue(dev);
276 } else {
277 /* Update tail */
278 td->control = DMA_COUNT(length) |
279 DMA_DESC_COF | DMA_DESC_IOF;
280 lp->td_ring[chain_index].control &=
281 ~DMA_DESC_COF;
282 lp->td_ring[chain_index].link = CPHYSADDR(td);
283 lp->tx_chain_tail = chain_index;
284 }
285 }
286 dma_cache_wback((u32) td, sizeof(*td));
287
288 dev->trans_start = jiffies;
289 spin_unlock_irqrestore(&lp->lock, flags);
290
291 return NETDEV_TX_OK;
292}
293
294static int mdio_read(struct net_device *dev, int mii_id, int reg)
295{
296 struct korina_private *lp = netdev_priv(dev);
297 int ret;
298
299 mii_id = ((lp->rx_irq == 0x2c ? 1 : 0) << 8);
300
301 writel(0, &lp->eth_regs->miimcfg);
302 writel(0, &lp->eth_regs->miimcmd);
303 writel(mii_id | reg, &lp->eth_regs->miimaddr);
304 writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd);
305
306 ret = (int)(readl(&lp->eth_regs->miimrdd));
307 return ret;
308}
309
310static void mdio_write(struct net_device *dev, int mii_id, int reg, int val)
311{
312 struct korina_private *lp = netdev_priv(dev);
313
314 mii_id = ((lp->rx_irq == 0x2c ? 1 : 0) << 8);
315
316 writel(0, &lp->eth_regs->miimcfg);
317 writel(1, &lp->eth_regs->miimcmd);
318 writel(mii_id | reg, &lp->eth_regs->miimaddr);
319 writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd);
320 writel(val, &lp->eth_regs->miimwtd);
321}
322
323/* Ethernet Rx DMA interrupt */
324static irqreturn_t korina_rx_dma_interrupt(int irq, void *dev_id)
325{
326 struct net_device *dev = dev_id;
327 struct korina_private *lp = netdev_priv(dev);
328 u32 dmas, dmasm;
329 irqreturn_t retval;
330
331 dmas = readl(&lp->rx_dma_regs->dmas);
332 if (dmas & (DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR)) {
ef11291b
FF		 333 dmasm = readl(&lp->rx_dma_regs->dmasm);
334 writel(dmasm | (DMA_STAT_DONE |
335 DMA_STAT_HALT | DMA_STAT_ERR),
336 &lp->rx_dma_regs->dmasm);
337
60d3f982
PS		 338 netif_rx_schedule(&lp->napi);
339
ef11291b
FF		 340 if (dmas & DMA_STAT_ERR)
341 printk(KERN_ERR DRV_NAME "%s: DMA error\n", dev->name);
342
343 retval = IRQ_HANDLED;
344 } else
345 retval = IRQ_NONE;
346
347 return retval;
348}
349
350static int korina_rx(struct net_device *dev, int limit)
351{
352 struct korina_private *lp = netdev_priv(dev);
353 struct dma_desc *rd = &lp->rd_ring[lp->rx_next_done];
354 struct sk_buff *skb, *skb_new;
355 u8 *pkt_buf;
4cf83b66 356 u32 devcs, pkt_len, dmas;
ef11291b
FF		 357 int count;
358
359 dma_cache_inv((u32)rd, sizeof(*rd));
360
361 for (count = 0; count < limit; count++) {
4cf83b66
PS		 362 skb = lp->rx_skb[lp->rx_next_done];
363 skb_new = NULL;
ef11291b
FF		 364
365 devcs = rd->devcs;
366
4cf83b66
PS		 367 if ((KORINA_RBSIZE - (u32)DMA_COUNT(rd->control)) == 0)
368 break;
369
ef11291b
FF		 370 /* Update statistics counters */
371 if (devcs & ETH_RX_CRC)
372 dev->stats.rx_crc_errors++;
373 if (devcs & ETH_RX_LOR)
374 dev->stats.rx_length_errors++;
375 if (devcs & ETH_RX_LE)
376 dev->stats.rx_length_errors++;
377 if (devcs & ETH_RX_OVR)
378 dev->stats.rx_over_errors++;
379 if (devcs & ETH_RX_CV)
380 dev->stats.rx_frame_errors++;
381 if (devcs & ETH_RX_CES)
382 dev->stats.rx_length_errors++;
383 if (devcs & ETH_RX_MP)
384 dev->stats.multicast++;
385
386 if ((devcs & ETH_RX_LD) != ETH_RX_LD) {
387 /* check that this is a whole packet
388 * WARNING: DMA_FD bit incorrectly set
389 * in Rc32434 (errata ref #077) */
390 dev->stats.rx_errors++;
391 dev->stats.rx_dropped++;
4cf83b66 392 } else if ((devcs & ETH_RX_ROK)) {
ef11291b 393 pkt_len = RCVPKT_LENGTH(devcs);
4cf83b66
PS		 394
395 /* must be the (first and) last
396 * descriptor then */
397 pkt_buf = (u8 *)lp->rx_skb[lp->rx_next_done]->data;
398
399 /* invalidate the cache */
400 dma_cache_inv((unsigned long)pkt_buf, pkt_len - 4);
401
402 /* Malloc up new buffer. */
403 skb_new = netdev_alloc_skb(dev, KORINA_RBSIZE + 2);
404
405 if (!skb_new)
406 break;
407 /* Do not count the CRC */
408 skb_put(skb, pkt_len - 4);
409 skb->protocol = eth_type_trans(skb, dev);
410
411 /* Pass the packet to upper layers */
412 netif_receive_skb(skb);
413 dev->stats.rx_packets++;
414 dev->stats.rx_bytes += pkt_len;
415
416 /* Update the mcast stats */
417 if (devcs & ETH_RX_MP)
418 dev->stats.multicast++;
419
420 lp->rx_skb[lp->rx_next_done] = skb_new;
ef11291b 421 }
4cf83b66
PS		 422
423 rd->devcs = 0;
424
425 /* Restore descriptor's curr_addr */
426 if (skb_new)
427 rd->ca = CPHYSADDR(skb_new->data);
428 else
429 rd->ca = CPHYSADDR(skb->data);
430
431 rd->control = DMA_COUNT(KORINA_RBSIZE) |
432 DMA_DESC_COD | DMA_DESC_IOD;
433 lp->rd_ring[(lp->rx_next_done - 1) &
434 KORINA_RDS_MASK].control &=
435 ~DMA_DESC_COD;
436
437 lp->rx_next_done = (lp->rx_next_done + 1) & KORINA_RDS_MASK;
438 dma_cache_wback((u32)rd, sizeof(*rd));
439 rd = &lp->rd_ring[lp->rx_next_done];
440 writel(~DMA_STAT_DONE, &lp->rx_dma_regs->dmas);
ef11291b
FF		 441 }
442
443 dmas = readl(&lp->rx_dma_regs->dmas);
444
445 if (dmas & DMA_STAT_HALT) {
446 writel(~(DMA_STAT_HALT | DMA_STAT_ERR),
447 &lp->rx_dma_regs->dmas);
448
449 lp->dma_halt_cnt++;
450 rd->devcs = 0;
451 skb = lp->rx_skb[lp->rx_next_done];
452 rd->ca = CPHYSADDR(skb->data);
453 dma_cache_wback((u32)rd, sizeof(*rd));
454 korina_chain_rx(lp, rd);
455 }
456
457 return count;
458}
459
460static int korina_poll(struct napi_struct *napi, int budget)
461{
462 struct korina_private *lp =
463 container_of(napi, struct korina_private, napi);
464 struct net_device *dev = lp->dev;
465 int work_done;
466
467 work_done = korina_rx(dev, budget);
468 if (work_done < budget) {
908a7a16 469 netif_rx_complete(napi);
ef11291b
FF		 470
471 writel(readl(&lp->rx_dma_regs->dmasm) &
472 ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR),
473 &lp->rx_dma_regs->dmasm);
474 }
475 return work_done;
476}
477
478/*
479 * Set or clear the multicast filter for this adaptor.
480 */
481static void korina_multicast_list(struct net_device *dev)
482{
483 struct korina_private *lp = netdev_priv(dev);
484 unsigned long flags;
485 struct dev_mc_list *dmi = dev->mc_list;
486 u32 recognise = ETH_ARC_AB; /* always accept broadcasts */
487 int i;
488
489 /* Set promiscuous mode */
490 if (dev->flags & IFF_PROMISC)
491 recognise |= ETH_ARC_PRO;
492
493 else if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 4))
494 /* All multicast and broadcast */
495 recognise |= ETH_ARC_AM;
496
497 /* Build the hash table */
498 if (dev->mc_count > 4) {
499 u16 hash_table[4];
500 u32 crc;
501
502 for (i = 0; i < 4; i++)
503 hash_table[i] = 0;
504
505 for (i = 0; i < dev->mc_count; i++) {
506 char *addrs = dmi->dmi_addr;
507
508 dmi = dmi->next;
509
510 if (!(*addrs & 1))
511 continue;
512
513 crc = ether_crc_le(6, addrs);
514 crc >>= 26;
515 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
516 }
517 /* Accept filtered multicast */
518 recognise |= ETH_ARC_AFM;
519
520 /* Fill the MAC hash tables with their values */
521 writel((u32)(hash_table[1] << 16 | hash_table[0]),
522 &lp->eth_regs->ethhash0);
523 writel((u32)(hash_table[3] << 16 | hash_table[2]),
524 &lp->eth_regs->ethhash1);
525 }
526
527 spin_lock_irqsave(&lp->lock, flags);
528 writel(recognise, &lp->eth_regs->etharc);
529 spin_unlock_irqrestore(&lp->lock, flags);
530}
531
532static void korina_tx(struct net_device *dev)
533{
534 struct korina_private *lp = netdev_priv(dev);
535 struct dma_desc *td = &lp->td_ring[lp->tx_next_done];
536 u32 devcs;
537 u32 dmas;
538
539 spin_lock(&lp->lock);
540
541 /* Process all desc that are done */
542 while (IS_DMA_FINISHED(td->control)) {
543 if (lp->tx_full == 1) {
544 netif_wake_queue(dev);
545 lp->tx_full = 0;
546 }
547
548 devcs = lp->td_ring[lp->tx_next_done].devcs;
549 if ((devcs & (ETH_TX_FD | ETH_TX_LD)) !=
550 (ETH_TX_FD | ETH_TX_LD)) {
551 dev->stats.tx_errors++;
552 dev->stats.tx_dropped++;
553
554 /* Should never happen */
555 printk(KERN_ERR DRV_NAME "%s: split tx ignored\n",
556 dev->name);
557 } else if (devcs & ETH_TX_TOK) {
558 dev->stats.tx_packets++;
559 dev->stats.tx_bytes +=
560 lp->tx_skb[lp->tx_next_done]->len;
561 } else {
562 dev->stats.tx_errors++;
563 dev->stats.tx_dropped++;
564
565 /* Underflow */
566 if (devcs & ETH_TX_UND)
567 dev->stats.tx_fifo_errors++;
568
569 /* Oversized frame */
570 if (devcs & ETH_TX_OF)
571 dev->stats.tx_aborted_errors++;
572
573 /* Excessive deferrals */
574 if (devcs & ETH_TX_ED)
575 dev->stats.tx_carrier_errors++;
576
577 /* Collisions: medium busy */
578 if (devcs & ETH_TX_EC)
579 dev->stats.collisions++;
580
581 /* Late collision */
582 if (devcs & ETH_TX_LC)
583 dev->stats.tx_window_errors++;
584 }
585
586 /* We must always free the original skb */
587 if (lp->tx_skb[lp->tx_next_done]) {
588 dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
589 lp->tx_skb[lp->tx_next_done] = NULL;
590 }
591
592 lp->td_ring[lp->tx_next_done].control = DMA_DESC_IOF;
593 lp->td_ring[lp->tx_next_done].devcs = ETH_TX_FD | ETH_TX_LD;
594 lp->td_ring[lp->tx_next_done].link = 0;
595 lp->td_ring[lp->tx_next_done].ca = 0;
596 lp->tx_count--;
597
598 /* Go on to next transmission */
599 lp->tx_next_done = (lp->tx_next_done + 1) & KORINA_TDS_MASK;
600 td = &lp->td_ring[lp->tx_next_done];
601
602 }
603
604 /* Clear the DMA status register */
605 dmas = readl(&lp->tx_dma_regs->dmas);
606 writel(~dmas, &lp->tx_dma_regs->dmas);
607
608 writel(readl(&lp->tx_dma_regs->dmasm) &
609 ~(DMA_STAT_FINI | DMA_STAT_ERR),
610 &lp->tx_dma_regs->dmasm);
611
612 spin_unlock(&lp->lock);
613}
614
615static irqreturn_t
616korina_tx_dma_interrupt(int irq, void *dev_id)
617{
618 struct net_device *dev = dev_id;
619 struct korina_private *lp = netdev_priv(dev);
620 u32 dmas, dmasm;
621 irqreturn_t retval;
622
623 dmas = readl(&lp->tx_dma_regs->dmas);
624
625 if (dmas & (DMA_STAT_FINI | DMA_STAT_ERR)) {
ef11291b
FF		 626 dmasm = readl(&lp->tx_dma_regs->dmasm);
627 writel(dmasm | (DMA_STAT_FINI | DMA_STAT_ERR),
628 &lp->tx_dma_regs->dmasm);
629
60d3f982
PS		 630 korina_tx(dev);
631
ef11291b
FF		 632 if (lp->tx_chain_status == desc_filled &&
633 (readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
634 writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
635 &(lp->tx_dma_regs->dmandptr));
636 lp->tx_chain_status = desc_empty;
637 lp->tx_chain_head = lp->tx_chain_tail;
638 dev->trans_start = jiffies;
639 }
640 if (dmas & DMA_STAT_ERR)
641 printk(KERN_ERR DRV_NAME "%s: DMA error\n", dev->name);
642
643 retval = IRQ_HANDLED;
644 } else
645 retval = IRQ_NONE;
646
647 return retval;
648}
649
650
651static void korina_check_media(struct net_device *dev, unsigned int init_media)
652{
653 struct korina_private *lp = netdev_priv(dev);
654
655 mii_check_media(&lp->mii_if, 0, init_media);
656
657 if (lp->mii_if.full_duplex)
658 writel(readl(&lp->eth_regs->ethmac2) | ETH_MAC2_FD,
659 &lp->eth_regs->ethmac2);
660 else
661 writel(readl(&lp->eth_regs->ethmac2) & ~ETH_MAC2_FD,
662 &lp->eth_regs->ethmac2);
663}
664
665static void korina_set_carrier(struct mii_if_info *mii)
666{
667 if (mii->force_media) {
668 /* autoneg is off: Link is always assumed to be up */
669 if (!netif_carrier_ok(mii->dev))
670 netif_carrier_on(mii->dev);
671 } else /* Let MMI library update carrier status */
672 korina_check_media(mii->dev, 0);
673}
674
675static int korina_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
676{
677 struct korina_private *lp = netdev_priv(dev);
678 struct mii_ioctl_data *data = if_mii(rq);
679 int rc;
680
681 if (!netif_running(dev))
682 return -EINVAL;
683 spin_lock_irq(&lp->lock);
684 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
685 spin_unlock_irq(&lp->lock);
686 korina_set_carrier(&lp->mii_if);
687
688 return rc;
689}
690
691/* ethtool helpers */
692static void netdev_get_drvinfo(struct net_device *dev,
693 struct ethtool_drvinfo *info)
694{
695 struct korina_private *lp = netdev_priv(dev);
696
697 strcpy(info->driver, DRV_NAME);
698 strcpy(info->version, DRV_VERSION);
699 strcpy(info->bus_info, lp->dev->name);
700}
701
702static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
703{
704 struct korina_private *lp = netdev_priv(dev);
705 int rc;
706
707 spin_lock_irq(&lp->lock);
708 rc = mii_ethtool_gset(&lp->mii_if, cmd);
709 spin_unlock_irq(&lp->lock);
710
711 return rc;
712}
713
714static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
715{
716 struct korina_private *lp = netdev_priv(dev);
717 int rc;
718
719 spin_lock_irq(&lp->lock);
720 rc = mii_ethtool_sset(&lp->mii_if, cmd);
721 spin_unlock_irq(&lp->lock);
722 korina_set_carrier(&lp->mii_if);
723
724 return rc;
725}
726
727static u32 netdev_get_link(struct net_device *dev)
728{
729 struct korina_private *lp = netdev_priv(dev);
730
731 return mii_link_ok(&lp->mii_if);
732}
733
734static struct ethtool_ops netdev_ethtool_ops = {
735 .get_drvinfo = netdev_get_drvinfo,
736 .get_settings = netdev_get_settings,
737 .set_settings = netdev_set_settings,
738 .get_link = netdev_get_link,
739};
740
741static void korina_alloc_ring(struct net_device *dev)
742{
743 struct korina_private *lp = netdev_priv(dev);
744 int i;
745
746 /* Initialize the transmit descriptors */
747 for (i = 0; i < KORINA_NUM_TDS; i++) {
748 lp->td_ring[i].control = DMA_DESC_IOF;
749 lp->td_ring[i].devcs = ETH_TX_FD | ETH_TX_LD;
750 lp->td_ring[i].ca = 0;
751 lp->td_ring[i].link = 0;
752 }
753 lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail =
754 lp->tx_full = lp->tx_count = 0;
755 lp->tx_chain_status = desc_empty;
756
757 /* Initialize the receive descriptors */
758 for (i = 0; i < KORINA_NUM_RDS; i++) {
759 struct sk_buff *skb = lp->rx_skb[i];
760
761 skb = dev_alloc_skb(KORINA_RBSIZE + 2);
762 if (!skb)
763 break;
764 skb_reserve(skb, 2);
765 lp->rx_skb[i] = skb;
766 lp->rd_ring[i].control = DMA_DESC_IOD |
767 DMA_COUNT(KORINA_RBSIZE);
768 lp->rd_ring[i].devcs = 0;
769 lp->rd_ring[i].ca = CPHYSADDR(skb->data);
770 lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
771 }
772
773 /* loop back */
774 lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[0]);
775 lp->rx_next_done = 0;
776
777 lp->rd_ring[i].control |= DMA_DESC_COD;
778 lp->rx_chain_head = 0;
779 lp->rx_chain_tail = 0;
780 lp->rx_chain_status = desc_empty;
781}
782
783static void korina_free_ring(struct net_device *dev)
784{
785 struct korina_private *lp = netdev_priv(dev);
786 int i;
787
788 for (i = 0; i < KORINA_NUM_RDS; i++) {
789 lp->rd_ring[i].control = 0;
790 if (lp->rx_skb[i])
791 dev_kfree_skb_any(lp->rx_skb[i]);
792 lp->rx_skb[i] = NULL;
793 }
794
795 for (i = 0; i < KORINA_NUM_TDS; i++) {
796 lp->td_ring[i].control = 0;
797 if (lp->tx_skb[i])
798 dev_kfree_skb_any(lp->tx_skb[i]);
799 lp->tx_skb[i] = NULL;
800 }
801}
802
803/*
804 * Initialize the RC32434 ethernet controller.
805 */
806static int korina_init(struct net_device *dev)
807{
808 struct korina_private *lp = netdev_priv(dev);
809
810 /* Disable DMA */
811 korina_abort_tx(dev);
812 korina_abort_rx(dev);
813
814 /* reset ethernet logic */
815 writel(0, &lp->eth_regs->ethintfc);
816 while ((readl(&lp->eth_regs->ethintfc) & ETH_INT_FC_RIP))
817 dev->trans_start = jiffies;
818
819 /* Enable Ethernet Interface */
820 writel(ETH_INT_FC_EN, &lp->eth_regs->ethintfc);
821
822 /* Allocate rings */
823 korina_alloc_ring(dev);
824
825 writel(0, &lp->rx_dma_regs->dmas);
826 /* Start Rx DMA */
827 korina_start_rx(lp, &lp->rd_ring[0]);
828
829 writel(readl(&lp->tx_dma_regs->dmasm) &
830 ~(DMA_STAT_FINI | DMA_STAT_ERR),
831 &lp->tx_dma_regs->dmasm);
832 writel(readl(&lp->rx_dma_regs->dmasm) &
833 ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR),
834 &lp->rx_dma_regs->dmasm);
835
836 /* Accept only packets destined for this Ethernet device address */
837 writel(ETH_ARC_AB, &lp->eth_regs->etharc);
838
839 /* Set all Ether station address registers to their initial values */
840 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
841 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
842
843 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
844 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
845
846 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
847 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
848
849 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
850 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
851
852
853 /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
854 writel(ETH_MAC2_PE | ETH_MAC2_CEN | ETH_MAC2_FD,
855 &lp->eth_regs->ethmac2);
856
857 /* Back to back inter-packet-gap */
858 writel(0x15, &lp->eth_regs->ethipgt);
859 /* Non - Back to back inter-packet-gap */
860 writel(0x12, &lp->eth_regs->ethipgr);
861
862 /* Management Clock Prescaler Divisor
863 * Clock independent setting */
864 writel(((idt_cpu_freq) / MII_CLOCK + 1) & ~1,
865 &lp->eth_regs->ethmcp);
866
867 /* don't transmit until fifo contains 48b */
868 writel(48, &lp->eth_regs->ethfifott);
869
870 writel(ETH_MAC1_RE, &lp->eth_regs->ethmac1);
871
872 napi_enable(&lp->napi);
873 netif_start_queue(dev);
874
875 return 0;
876}
877
878/*
879 * Restart the RC32434 ethernet controller.
880 * FIXME: check the return status where we call it
881 */
882static int korina_restart(struct net_device *dev)
883{
884 struct korina_private *lp = netdev_priv(dev);
e3152ab9 885 int ret;
ef11291b
FF		 886
887 /*
888 * Disable interrupts
889 */
890 disable_irq(lp->rx_irq);
891 disable_irq(lp->tx_irq);
892 disable_irq(lp->ovr_irq);
893 disable_irq(lp->und_irq);
894
895 writel(readl(&lp->tx_dma_regs->dmasm) |
896 DMA_STAT_FINI | DMA_STAT_ERR,
897 &lp->tx_dma_regs->dmasm);
898 writel(readl(&lp->rx_dma_regs->dmasm) |
899 DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR,
900 &lp->rx_dma_regs->dmasm);
901
902 korina_free_ring(dev);
903
beb0babf
PS		 904 napi_disable(&lp->napi);
905
ef11291b
FF		 906 ret = korina_init(dev);
907 if (ret < 0) {
908 printk(KERN_ERR DRV_NAME "%s: cannot restart device\n",
909 dev->name);
910 return ret;
911 }
912 korina_multicast_list(dev);
913
914 enable_irq(lp->und_irq);
915 enable_irq(lp->ovr_irq);
916 enable_irq(lp->tx_irq);
917 enable_irq(lp->rx_irq);
918
919 return ret;
920}
921
922static void korina_clear_and_restart(struct net_device *dev, u32 value)
923{
924 struct korina_private *lp = netdev_priv(dev);
925
926 netif_stop_queue(dev);
927 writel(value, &lp->eth_regs->ethintfc);
928 korina_restart(dev);
929}
930
931/* Ethernet Tx Underflow interrupt */
932static irqreturn_t korina_und_interrupt(int irq, void *dev_id)
933{
934 struct net_device *dev = dev_id;
935 struct korina_private *lp = netdev_priv(dev);
936 unsigned int und;
937
938 spin_lock(&lp->lock);
939
940 und = readl(&lp->eth_regs->ethintfc);
941
942 if (und & ETH_INT_FC_UND)
943 korina_clear_and_restart(dev, und & ~ETH_INT_FC_UND);
944
945 spin_unlock(&lp->lock);
946
947 return IRQ_HANDLED;
948}
949
950static void korina_tx_timeout(struct net_device *dev)
951{
952 struct korina_private *lp = netdev_priv(dev);
953 unsigned long flags;
954
955 spin_lock_irqsave(&lp->lock, flags);
956 korina_restart(dev);
957 spin_unlock_irqrestore(&lp->lock, flags);
958}
959
960/* Ethernet Rx Overflow interrupt */
961static irqreturn_t
962korina_ovr_interrupt(int irq, void *dev_id)
963{
964 struct net_device *dev = dev_id;
965 struct korina_private *lp = netdev_priv(dev);
966 unsigned int ovr;
967
968 spin_lock(&lp->lock);
969 ovr = readl(&lp->eth_regs->ethintfc);
970
971 if (ovr & ETH_INT_FC_OVR)
972 korina_clear_and_restart(dev, ovr & ~ETH_INT_FC_OVR);
973
974 spin_unlock(&lp->lock);
975
976 return IRQ_HANDLED;
977}
978
979#ifdef CONFIG_NET_POLL_CONTROLLER
980static void korina_poll_controller(struct net_device *dev)
981{
982 disable_irq(dev->irq);
983 korina_tx_dma_interrupt(dev->irq, dev);
984 enable_irq(dev->irq);
985}
986#endif
987
988static int korina_open(struct net_device *dev)
989{
990 struct korina_private *lp = netdev_priv(dev);
e3152ab9 991 int ret;
ef11291b
FF		 992
993 /* Initialize */
994 ret = korina_init(dev);
995 if (ret < 0) {
996 printk(KERN_ERR DRV_NAME "%s: cannot open device\n", dev->name);
997 goto out;
998 }
999
1000 /* Install the interrupt handler
1001 * that handles the Done Finished
1002 * Ovr and Und Events */
1003 ret = request_irq(lp->rx_irq, &korina_rx_dma_interrupt,
1004 IRQF_SHARED | IRQF_DISABLED, "Korina ethernet Rx", dev);
1005 if (ret < 0) {
1006 printk(KERN_ERR DRV_NAME "%s: unable to get Rx DMA IRQ %d\n",
1007 dev->name, lp->rx_irq);
1008 goto err_release;
1009 }
1010 ret = request_irq(lp->tx_irq, &korina_tx_dma_interrupt,
1011 IRQF_SHARED | IRQF_DISABLED, "Korina ethernet Tx", dev);
1012 if (ret < 0) {
1013 printk(KERN_ERR DRV_NAME "%s: unable to get Tx DMA IRQ %d\n",
1014 dev->name, lp->tx_irq);
1015 goto err_free_rx_irq;
1016 }
1017
1018 /* Install handler for overrun error. */
1019 ret = request_irq(lp->ovr_irq, &korina_ovr_interrupt,
1020 IRQF_SHARED | IRQF_DISABLED, "Ethernet Overflow", dev);
1021 if (ret < 0) {
1022 printk(KERN_ERR DRV_NAME"%s: unable to get OVR IRQ %d\n",
1023 dev->name, lp->ovr_irq);
1024 goto err_free_tx_irq;
1025 }
1026
1027 /* Install handler for underflow error. */
1028 ret = request_irq(lp->und_irq, &korina_und_interrupt,
1029 IRQF_SHARED | IRQF_DISABLED, "Ethernet Underflow", dev);
1030 if (ret < 0) {
1031 printk(KERN_ERR DRV_NAME "%s: unable to get UND IRQ %d\n",
1032 dev->name, lp->und_irq);
1033 goto err_free_ovr_irq;
1034 }
751c2e47
FR		 1035out:
1036 return ret;
ef11291b
FF		 1037
1038err_free_ovr_irq:
1039 free_irq(lp->ovr_irq, dev);
1040err_free_tx_irq:
1041 free_irq(lp->tx_irq, dev);
1042err_free_rx_irq:
1043 free_irq(lp->rx_irq, dev);
1044err_release:
1045 korina_free_ring(dev);
1046 goto out;
ef11291b
FF		 1047}
1048
1049static int korina_close(struct net_device *dev)
1050{
1051 struct korina_private *lp = netdev_priv(dev);
1052 u32 tmp;
1053
1054 /* Disable interrupts */
1055 disable_irq(lp->rx_irq);
1056 disable_irq(lp->tx_irq);
1057 disable_irq(lp->ovr_irq);
1058 disable_irq(lp->und_irq);
1059
1060 korina_abort_tx(dev);
1061 tmp = readl(&lp->tx_dma_regs->dmasm);
1062 tmp = tmp | DMA_STAT_FINI | DMA_STAT_ERR;
1063 writel(tmp, &lp->tx_dma_regs->dmasm);
1064
1065 korina_abort_rx(dev);
1066 tmp = readl(&lp->rx_dma_regs->dmasm);
1067 tmp = tmp | DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR;
1068 writel(tmp, &lp->rx_dma_regs->dmasm);
1069
1070 korina_free_ring(dev);
1071
beb0babf
PS		 1072 napi_disable(&lp->napi);
1073
ef11291b
FF		 1074 free_irq(lp->rx_irq, dev);
1075 free_irq(lp->tx_irq, dev);
1076 free_irq(lp->ovr_irq, dev);
1077 free_irq(lp->und_irq, dev);
1078
1079 return 0;
1080}
1081
1082static int korina_probe(struct platform_device *pdev)
1083{
1084 struct korina_device *bif = platform_get_drvdata(pdev);
1085 struct korina_private *lp;
1086 struct net_device *dev;
1087 struct resource *r;
e3152ab9 1088 int rc;
ef11291b
FF		 1089
1090 dev = alloc_etherdev(sizeof(struct korina_private));
1091 if (!dev) {
1092 printk(KERN_ERR DRV_NAME ": alloc_etherdev failed\n");
1093 return -ENOMEM;
1094 }
1095 SET_NETDEV_DEV(dev, &pdev->dev);
ef11291b
FF		 1096 lp = netdev_priv(dev);
1097
1098 bif->dev = dev;
1099 memcpy(dev->dev_addr, bif->mac, 6);
1100
1101 lp->rx_irq = platform_get_irq_byname(pdev, "korina_rx");
1102 lp->tx_irq = platform_get_irq_byname(pdev, "korina_tx");
1103 lp->ovr_irq = platform_get_irq_byname(pdev, "korina_ovr");
1104 lp->und_irq = platform_get_irq_byname(pdev, "korina_und");
1105
1106 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_regs");
1107 dev->base_addr = r->start;
1108 lp->eth_regs = ioremap_nocache(r->start, r->end - r->start);
1109 if (!lp->eth_regs) {
1110 printk(KERN_ERR DRV_NAME "cannot remap registers\n");
e3152ab9 1111 rc = -ENXIO;
ef11291b
FF		 1112 goto probe_err_out;
1113 }
1114
1115 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_rx");
1116 lp->rx_dma_regs = ioremap_nocache(r->start, r->end - r->start);
1117 if (!lp->rx_dma_regs) {
1118 printk(KERN_ERR DRV_NAME "cannot remap Rx DMA registers\n");
e3152ab9 1119 rc = -ENXIO;
ef11291b
FF		 1120 goto probe_err_dma_rx;
1121 }
1122
1123 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_tx");
1124 lp->tx_dma_regs = ioremap_nocache(r->start, r->end - r->start);
1125 if (!lp->tx_dma_regs) {
1126 printk(KERN_ERR DRV_NAME "cannot remap Tx DMA registers\n");
e3152ab9 1127 rc = -ENXIO;
ef11291b
FF		 1128 goto probe_err_dma_tx;
1129 }
1130
1131 lp->td_ring = kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1132 if (!lp->td_ring) {
1133 printk(KERN_ERR DRV_NAME "cannot allocate descriptors\n");
e3152ab9 1134 rc = -ENXIO;
ef11291b
FF		 1135 goto probe_err_td_ring;
1136 }
1137
1138 dma_cache_inv((unsigned long)(lp->td_ring),
1139 TD_RING_SIZE + RD_RING_SIZE);
1140
1141 /* now convert TD_RING pointer to KSEG1 */
1142 lp->td_ring = (struct dma_desc *)KSEG1ADDR(lp->td_ring);
1143 lp->rd_ring = &lp->td_ring[KORINA_NUM_TDS];
1144
1145 spin_lock_init(&lp->lock);
1146 /* just use the rx dma irq */
1147 dev->irq = lp->rx_irq;
1148 lp->dev = dev;
1149
1150 dev->open = korina_open;
1151 dev->stop = korina_close;
1152 dev->hard_start_xmit = korina_send_packet;
1153 dev->set_multicast_list = &korina_multicast_list;
1154 dev->ethtool_ops = &netdev_ethtool_ops;
1155 dev->tx_timeout = korina_tx_timeout;
1156 dev->watchdog_timeo = TX_TIMEOUT;
1157 dev->do_ioctl = &korina_ioctl;
1158#ifdef CONFIG_NET_POLL_CONTROLLER
1159 dev->poll_controller = korina_poll_controller;
1160#endif
1161 netif_napi_add(dev, &lp->napi, korina_poll, 64);
1162
1163 lp->phy_addr = (((lp->rx_irq == 0x2c? 1:0) << 8) | 0x05);
1164 lp->mii_if.dev = dev;
1165 lp->mii_if.mdio_read = mdio_read;
1166 lp->mii_if.mdio_write = mdio_write;
1167 lp->mii_if.phy_id = lp->phy_addr;
1168 lp->mii_if.phy_id_mask = 0x1f;
1169 lp->mii_if.reg_num_mask = 0x1f;
1170
e3152ab9
FR		 1171 rc = register_netdev(dev);
1172 if (rc < 0) {
ef11291b 1173 printk(KERN_ERR DRV_NAME
e3152ab9 1174 ": cannot register net device %d\n", rc);
ef11291b
FF		 1175 goto probe_err_register;
1176 }
e3152ab9
FR		 1177out:
1178 return rc;
ef11291b
FF		 1179
1180probe_err_register:
1181 kfree(lp->td_ring);
1182probe_err_td_ring:
1183 iounmap(lp->tx_dma_regs);
1184probe_err_dma_tx:
1185 iounmap(lp->rx_dma_regs);
1186probe_err_dma_rx:
1187 iounmap(lp->eth_regs);
1188probe_err_out:
1189 free_netdev(dev);
e3152ab9 1190 goto out;
ef11291b
FF		 1191}
1192
1193static int korina_remove(struct platform_device *pdev)
1194{
1195 struct korina_device *bif = platform_get_drvdata(pdev);
1196 struct korina_private *lp = netdev_priv(bif->dev);
1197
e3152ab9
FR		 1198 iounmap(lp->eth_regs);
1199 iounmap(lp->rx_dma_regs);
1200 iounmap(lp->tx_dma_regs);
ef11291b
FF		 1201
1202 platform_set_drvdata(pdev, NULL);
1203 unregister_netdev(bif->dev);
1204 free_netdev(bif->dev);
1205
1206 return 0;
1207}
1208
1209static struct platform_driver korina_driver = {
1210 .driver.name = "korina",
1211 .probe = korina_probe,
1212 .remove = korina_remove,
1213};
1214
1215static int __init korina_init_module(void)
1216{
1217 return platform_driver_register(&korina_driver);
1218}
1219
1220static void korina_cleanup_module(void)
1221{
1222 return platform_driver_unregister(&korina_driver);
1223}
1224
1225module_init(korina_init_module);
1226module_exit(korina_cleanup_module);
1227
1228MODULE_AUTHOR("Philip Rischel <rischelp@idt.com>");
1229MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>");
1230MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
1231MODULE_DESCRIPTION("IDT RC32434 (Korina) Ethernet driver");
1232MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)