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ff4569c7 DB |
1 | /* |
2 | * davinci_nand.c - NAND Flash Driver for DaVinci family chips | |
3 | * | |
4 | * Copyright © 2006 Texas Instruments. | |
5 | * | |
6 | * Port to 2.6.23 Copyright © 2008 by: | |
7 | * Sander Huijsen <Shuijsen@optelecom-nkf.com> | |
8 | * Troy Kisky <troy.kisky@boundarydevices.com> | |
9 | * Dirk Behme <Dirk.Behme@gmail.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | */ | |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/err.h> | |
31 | #include <linux/clk.h> | |
32 | #include <linux/io.h> | |
33 | #include <linux/mtd/nand.h> | |
34 | #include <linux/mtd/partitions.h> | |
5a0e3ad6 | 35 | #include <linux/slab.h> |
ff4569c7 | 36 | |
ff4569c7 DB |
37 | #include <mach/nand.h> |
38 | ||
39 | #include <asm/mach-types.h> | |
40 | ||
41 | ||
ff4569c7 DB |
42 | /* |
43 | * This is a device driver for the NAND flash controller found on the | |
44 | * various DaVinci family chips. It handles up to four SoC chipselects, | |
45 | * and some flavors of secondary chipselect (e.g. based on A12) as used | |
46 | * with multichip packages. | |
47 | * | |
6a4123e5 | 48 | * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC |
ff4569c7 DB |
49 | * available on chips like the DM355 and OMAP-L137 and needed with the |
50 | * more error-prone MLC NAND chips. | |
51 | * | |
52 | * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY | |
53 | * outputs in a "wire-AND" configuration, with no per-chip signals. | |
54 | */ | |
55 | struct davinci_nand_info { | |
56 | struct mtd_info mtd; | |
57 | struct nand_chip chip; | |
6a4123e5 | 58 | struct nand_ecclayout ecclayout; |
ff4569c7 DB |
59 | |
60 | struct device *dev; | |
61 | struct clk *clk; | |
62 | bool partitioned; | |
63 | ||
6a4123e5 DB |
64 | bool is_readmode; |
65 | ||
ff4569c7 DB |
66 | void __iomem *base; |
67 | void __iomem *vaddr; | |
68 | ||
69 | uint32_t ioaddr; | |
70 | uint32_t current_cs; | |
71 | ||
72 | uint32_t mask_chipsel; | |
73 | uint32_t mask_ale; | |
74 | uint32_t mask_cle; | |
75 | ||
76 | uint32_t core_chipsel; | |
77 | }; | |
78 | ||
79 | static DEFINE_SPINLOCK(davinci_nand_lock); | |
6a4123e5 | 80 | static bool ecc4_busy; |
ff4569c7 DB |
81 | |
82 | #define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd) | |
83 | ||
84 | ||
85 | static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info, | |
86 | int offset) | |
87 | { | |
88 | return __raw_readl(info->base + offset); | |
89 | } | |
90 | ||
91 | static inline void davinci_nand_writel(struct davinci_nand_info *info, | |
92 | int offset, unsigned long value) | |
93 | { | |
94 | __raw_writel(value, info->base + offset); | |
95 | } | |
96 | ||
97 | /*----------------------------------------------------------------------*/ | |
98 | ||
99 | /* | |
100 | * Access to hardware control lines: ALE, CLE, secondary chipselect. | |
101 | */ | |
102 | ||
103 | static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, | |
104 | unsigned int ctrl) | |
105 | { | |
106 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
107 | uint32_t addr = info->current_cs; | |
108 | struct nand_chip *nand = mtd->priv; | |
109 | ||
110 | /* Did the control lines change? */ | |
111 | if (ctrl & NAND_CTRL_CHANGE) { | |
112 | if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE) | |
113 | addr |= info->mask_cle; | |
114 | else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE) | |
115 | addr |= info->mask_ale; | |
116 | ||
117 | nand->IO_ADDR_W = (void __iomem __force *)addr; | |
118 | } | |
119 | ||
120 | if (cmd != NAND_CMD_NONE) | |
121 | iowrite8(cmd, nand->IO_ADDR_W); | |
122 | } | |
123 | ||
124 | static void nand_davinci_select_chip(struct mtd_info *mtd, int chip) | |
125 | { | |
126 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
127 | uint32_t addr = info->ioaddr; | |
128 | ||
129 | /* maybe kick in a second chipselect */ | |
130 | if (chip > 0) | |
131 | addr |= info->mask_chipsel; | |
132 | info->current_cs = addr; | |
133 | ||
134 | info->chip.IO_ADDR_W = (void __iomem __force *)addr; | |
135 | info->chip.IO_ADDR_R = info->chip.IO_ADDR_W; | |
136 | } | |
137 | ||
138 | /*----------------------------------------------------------------------*/ | |
139 | ||
140 | /* | |
141 | * 1-bit hardware ECC ... context maintained for each core chipselect | |
142 | */ | |
143 | ||
144 | static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd) | |
145 | { | |
146 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
147 | ||
148 | return davinci_nand_readl(info, NANDF1ECC_OFFSET | |
149 | + 4 * info->core_chipsel); | |
150 | } | |
151 | ||
152 | static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode) | |
153 | { | |
154 | struct davinci_nand_info *info; | |
155 | uint32_t nandcfr; | |
156 | unsigned long flags; | |
157 | ||
158 | info = to_davinci_nand(mtd); | |
159 | ||
160 | /* Reset ECC hardware */ | |
161 | nand_davinci_readecc_1bit(mtd); | |
162 | ||
163 | spin_lock_irqsave(&davinci_nand_lock, flags); | |
164 | ||
165 | /* Restart ECC hardware */ | |
166 | nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET); | |
167 | nandcfr |= BIT(8 + info->core_chipsel); | |
168 | davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr); | |
169 | ||
170 | spin_unlock_irqrestore(&davinci_nand_lock, flags); | |
171 | } | |
172 | ||
173 | /* | |
174 | * Read hardware ECC value and pack into three bytes | |
175 | */ | |
176 | static int nand_davinci_calculate_1bit(struct mtd_info *mtd, | |
177 | const u_char *dat, u_char *ecc_code) | |
178 | { | |
179 | unsigned int ecc_val = nand_davinci_readecc_1bit(mtd); | |
180 | unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4); | |
181 | ||
182 | /* invert so that erased block ecc is correct */ | |
183 | ecc24 = ~ecc24; | |
184 | ecc_code[0] = (u_char)(ecc24); | |
185 | ecc_code[1] = (u_char)(ecc24 >> 8); | |
186 | ecc_code[2] = (u_char)(ecc24 >> 16); | |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
191 | static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat, | |
192 | u_char *read_ecc, u_char *calc_ecc) | |
193 | { | |
194 | struct nand_chip *chip = mtd->priv; | |
195 | uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) | | |
196 | (read_ecc[2] << 16); | |
197 | uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) | | |
198 | (calc_ecc[2] << 16); | |
199 | uint32_t diff = eccCalc ^ eccNand; | |
200 | ||
201 | if (diff) { | |
202 | if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) { | |
203 | /* Correctable error */ | |
204 | if ((diff >> (12 + 3)) < chip->ecc.size) { | |
205 | dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7); | |
206 | return 1; | |
207 | } else { | |
208 | return -1; | |
209 | } | |
210 | } else if (!(diff & (diff - 1))) { | |
211 | /* Single bit ECC error in the ECC itself, | |
212 | * nothing to fix */ | |
213 | return 1; | |
214 | } else { | |
215 | /* Uncorrectable error */ | |
216 | return -1; | |
217 | } | |
218 | ||
219 | } | |
220 | return 0; | |
221 | } | |
222 | ||
223 | /*----------------------------------------------------------------------*/ | |
224 | ||
6a4123e5 DB |
225 | /* |
226 | * 4-bit hardware ECC ... context maintained over entire AEMIF | |
227 | * | |
228 | * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME | |
229 | * since that forces use of a problematic "infix OOB" layout. | |
230 | * Among other things, it trashes manufacturer bad block markers. | |
231 | * Also, and specific to this hardware, it ECC-protects the "prepad" | |
232 | * in the OOB ... while having ECC protection for parts of OOB would | |
233 | * seem useful, the current MTD stack sometimes wants to update the | |
234 | * OOB without recomputing ECC. | |
235 | */ | |
236 | ||
237 | static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode) | |
238 | { | |
239 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
240 | unsigned long flags; | |
241 | u32 val; | |
242 | ||
243 | spin_lock_irqsave(&davinci_nand_lock, flags); | |
244 | ||
245 | /* Start 4-bit ECC calculation for read/write */ | |
246 | val = davinci_nand_readl(info, NANDFCR_OFFSET); | |
247 | val &= ~(0x03 << 4); | |
248 | val |= (info->core_chipsel << 4) | BIT(12); | |
249 | davinci_nand_writel(info, NANDFCR_OFFSET, val); | |
250 | ||
251 | info->is_readmode = (mode == NAND_ECC_READ); | |
252 | ||
253 | spin_unlock_irqrestore(&davinci_nand_lock, flags); | |
254 | } | |
255 | ||
256 | /* Read raw ECC code after writing to NAND. */ | |
257 | static void | |
258 | nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4]) | |
259 | { | |
260 | const u32 mask = 0x03ff03ff; | |
261 | ||
262 | code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask; | |
263 | code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask; | |
264 | code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask; | |
265 | code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask; | |
266 | } | |
267 | ||
268 | /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */ | |
269 | static int nand_davinci_calculate_4bit(struct mtd_info *mtd, | |
270 | const u_char *dat, u_char *ecc_code) | |
271 | { | |
272 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
273 | u32 raw_ecc[4], *p; | |
274 | unsigned i; | |
275 | ||
276 | /* After a read, terminate ECC calculation by a dummy read | |
277 | * of some 4-bit ECC register. ECC covers everything that | |
278 | * was read; correct() just uses the hardware state, so | |
279 | * ecc_code is not needed. | |
280 | */ | |
281 | if (info->is_readmode) { | |
282 | davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET); | |
283 | return 0; | |
284 | } | |
285 | ||
286 | /* Pack eight raw 10-bit ecc values into ten bytes, making | |
287 | * two passes which each convert four values (in upper and | |
288 | * lower halves of two 32-bit words) into five bytes. The | |
289 | * ROM boot loader uses this same packing scheme. | |
290 | */ | |
291 | nand_davinci_readecc_4bit(info, raw_ecc); | |
292 | for (i = 0, p = raw_ecc; i < 2; i++, p += 2) { | |
293 | *ecc_code++ = p[0] & 0xff; | |
294 | *ecc_code++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc); | |
295 | *ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0); | |
296 | *ecc_code++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0); | |
297 | *ecc_code++ = (p[1] >> 18) & 0xff; | |
298 | } | |
299 | ||
300 | return 0; | |
301 | } | |
302 | ||
303 | /* Correct up to 4 bits in data we just read, using state left in the | |
304 | * hardware plus the ecc_code computed when it was first written. | |
305 | */ | |
306 | static int nand_davinci_correct_4bit(struct mtd_info *mtd, | |
307 | u_char *data, u_char *ecc_code, u_char *null) | |
308 | { | |
309 | int i; | |
310 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
311 | unsigned short ecc10[8]; | |
312 | unsigned short *ecc16; | |
313 | u32 syndrome[4]; | |
314 | unsigned num_errors, corrected; | |
315 | ||
316 | /* All bytes 0xff? It's an erased page; ignore its ECC. */ | |
317 | for (i = 0; i < 10; i++) { | |
318 | if (ecc_code[i] != 0xff) | |
319 | goto compare; | |
320 | } | |
321 | return 0; | |
322 | ||
323 | compare: | |
324 | /* Unpack ten bytes into eight 10 bit values. We know we're | |
325 | * little-endian, and use type punning for less shifting/masking. | |
326 | */ | |
327 | if (WARN_ON(0x01 & (unsigned) ecc_code)) | |
328 | return -EINVAL; | |
329 | ecc16 = (unsigned short *)ecc_code; | |
330 | ||
331 | ecc10[0] = (ecc16[0] >> 0) & 0x3ff; | |
332 | ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0); | |
333 | ecc10[2] = (ecc16[1] >> 4) & 0x3ff; | |
334 | ecc10[3] = ((ecc16[1] >> 14) & 0x3) | ((ecc16[2] << 2) & 0x3fc); | |
335 | ecc10[4] = (ecc16[2] >> 8) | ((ecc16[3] << 8) & 0x300); | |
336 | ecc10[5] = (ecc16[3] >> 2) & 0x3ff; | |
337 | ecc10[6] = ((ecc16[3] >> 12) & 0xf) | ((ecc16[4] << 4) & 0x3f0); | |
338 | ecc10[7] = (ecc16[4] >> 6) & 0x3ff; | |
339 | ||
340 | /* Tell ECC controller about the expected ECC codes. */ | |
341 | for (i = 7; i >= 0; i--) | |
342 | davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]); | |
343 | ||
344 | /* Allow time for syndrome calculation ... then read it. | |
345 | * A syndrome of all zeroes 0 means no detected errors. | |
346 | */ | |
347 | davinci_nand_readl(info, NANDFSR_OFFSET); | |
348 | nand_davinci_readecc_4bit(info, syndrome); | |
349 | if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3])) | |
350 | return 0; | |
351 | ||
f12a9473 SN |
352 | /* |
353 | * Clear any previous address calculation by doing a dummy read of an | |
354 | * error address register. | |
355 | */ | |
356 | davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET); | |
357 | ||
6a4123e5 DB |
358 | /* Start address calculation, and wait for it to complete. |
359 | * We _could_ start reading more data while this is working, | |
360 | * to speed up the overall page read. | |
361 | */ | |
362 | davinci_nand_writel(info, NANDFCR_OFFSET, | |
363 | davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13)); | |
364 | for (;;) { | |
365 | u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET); | |
366 | ||
367 | switch ((fsr >> 8) & 0x0f) { | |
368 | case 0: /* no error, should not happen */ | |
f12a9473 | 369 | davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET); |
6a4123e5 DB |
370 | return 0; |
371 | case 1: /* five or more errors detected */ | |
f12a9473 | 372 | davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET); |
6a4123e5 DB |
373 | return -EIO; |
374 | case 2: /* error addresses computed */ | |
375 | case 3: | |
376 | num_errors = 1 + ((fsr >> 16) & 0x03); | |
377 | goto correct; | |
378 | default: /* still working on it */ | |
379 | cpu_relax(); | |
380 | continue; | |
381 | } | |
382 | } | |
383 | ||
384 | correct: | |
385 | /* correct each error */ | |
386 | for (i = 0, corrected = 0; i < num_errors; i++) { | |
387 | int error_address, error_value; | |
388 | ||
389 | if (i > 1) { | |
390 | error_address = davinci_nand_readl(info, | |
391 | NAND_ERR_ADD2_OFFSET); | |
392 | error_value = davinci_nand_readl(info, | |
393 | NAND_ERR_ERRVAL2_OFFSET); | |
394 | } else { | |
395 | error_address = davinci_nand_readl(info, | |
396 | NAND_ERR_ADD1_OFFSET); | |
397 | error_value = davinci_nand_readl(info, | |
398 | NAND_ERR_ERRVAL1_OFFSET); | |
399 | } | |
400 | ||
401 | if (i & 1) { | |
402 | error_address >>= 16; | |
403 | error_value >>= 16; | |
404 | } | |
405 | error_address &= 0x3ff; | |
406 | error_address = (512 + 7) - error_address; | |
407 | ||
408 | if (error_address < 512) { | |
409 | data[error_address] ^= error_value; | |
410 | corrected++; | |
411 | } | |
412 | } | |
413 | ||
414 | return corrected; | |
415 | } | |
416 | ||
417 | /*----------------------------------------------------------------------*/ | |
418 | ||
ff4569c7 DB |
419 | /* |
420 | * NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's | |
421 | * how these chips are normally wired. This translates to both 8 and 16 | |
422 | * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4). | |
423 | * | |
424 | * For now we assume that configuration, or any other one which ignores | |
425 | * the two LSBs for NAND access ... so we can issue 32-bit reads/writes | |
426 | * and have that transparently morphed into multiple NAND operations. | |
427 | */ | |
428 | static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
429 | { | |
430 | struct nand_chip *chip = mtd->priv; | |
431 | ||
432 | if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0) | |
433 | ioread32_rep(chip->IO_ADDR_R, buf, len >> 2); | |
434 | else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0) | |
435 | ioread16_rep(chip->IO_ADDR_R, buf, len >> 1); | |
436 | else | |
437 | ioread8_rep(chip->IO_ADDR_R, buf, len); | |
438 | } | |
439 | ||
440 | static void nand_davinci_write_buf(struct mtd_info *mtd, | |
441 | const uint8_t *buf, int len) | |
442 | { | |
443 | struct nand_chip *chip = mtd->priv; | |
444 | ||
445 | if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0) | |
446 | iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2); | |
447 | else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0) | |
448 | iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1); | |
449 | else | |
450 | iowrite8_rep(chip->IO_ADDR_R, buf, len); | |
451 | } | |
452 | ||
453 | /* | |
454 | * Check hardware register for wait status. Returns 1 if device is ready, | |
455 | * 0 if it is still busy. | |
456 | */ | |
457 | static int nand_davinci_dev_ready(struct mtd_info *mtd) | |
458 | { | |
459 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
460 | ||
461 | return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0); | |
462 | } | |
463 | ||
464 | static void __init nand_dm6446evm_flash_init(struct davinci_nand_info *info) | |
465 | { | |
466 | uint32_t regval, a1cr; | |
467 | ||
468 | /* | |
469 | * NAND FLASH timings @ PLL1 == 459 MHz | |
470 | * - AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz | |
471 | * - AEMIF.CLK period = 1/76.5 MHz = 13.1 ns | |
472 | */ | |
473 | regval = 0 | |
474 | | (0 << 31) /* selectStrobe */ | |
475 | | (0 << 30) /* extWait (never with NAND) */ | |
476 | | (1 << 26) /* writeSetup 10 ns */ | |
477 | | (3 << 20) /* writeStrobe 40 ns */ | |
478 | | (1 << 17) /* writeHold 10 ns */ | |
479 | | (0 << 13) /* readSetup 10 ns */ | |
480 | | (3 << 7) /* readStrobe 60 ns */ | |
481 | | (0 << 4) /* readHold 10 ns */ | |
482 | | (3 << 2) /* turnAround ?? ns */ | |
483 | | (0 << 0) /* asyncSize 8-bit bus */ | |
484 | ; | |
485 | a1cr = davinci_nand_readl(info, A1CR_OFFSET); | |
486 | if (a1cr != regval) { | |
487 | dev_dbg(info->dev, "Warning: NAND config: Set A1CR " \ | |
488 | "reg to 0x%08x, was 0x%08x, should be done by " \ | |
489 | "bootloader.\n", regval, a1cr); | |
490 | davinci_nand_writel(info, A1CR_OFFSET, regval); | |
491 | } | |
492 | } | |
493 | ||
494 | /*----------------------------------------------------------------------*/ | |
495 | ||
6a4123e5 DB |
496 | /* An ECC layout for using 4-bit ECC with small-page flash, storing |
497 | * ten ECC bytes plus the manufacturer's bad block marker byte, and | |
498 | * and not overlapping the default BBT markers. | |
499 | */ | |
500 | static struct nand_ecclayout hwecc4_small __initconst = { | |
501 | .eccbytes = 10, | |
502 | .eccpos = { 0, 1, 2, 3, 4, | |
503 | /* offset 5 holds the badblock marker */ | |
504 | 6, 7, | |
505 | 13, 14, 15, }, | |
506 | .oobfree = { | |
507 | {.offset = 8, .length = 5, }, | |
508 | {.offset = 16, }, | |
509 | }, | |
510 | }; | |
511 | ||
f12a9473 SN |
512 | /* An ECC layout for using 4-bit ECC with large-page (2048bytes) flash, |
513 | * storing ten ECC bytes plus the manufacturer's bad block marker byte, | |
514 | * and not overlapping the default BBT markers. | |
515 | */ | |
516 | static struct nand_ecclayout hwecc4_2048 __initconst = { | |
517 | .eccbytes = 40, | |
518 | .eccpos = { | |
519 | /* at the end of spare sector */ | |
520 | 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, | |
521 | 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, | |
522 | 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, | |
523 | 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, | |
524 | }, | |
525 | .oobfree = { | |
526 | /* 2 bytes at offset 0 hold manufacturer badblock markers */ | |
527 | {.offset = 2, .length = 22, }, | |
528 | /* 5 bytes at offset 8 hold BBT markers */ | |
529 | /* 8 bytes at offset 16 hold JFFS2 clean markers */ | |
530 | }, | |
531 | }; | |
6a4123e5 | 532 | |
ff4569c7 DB |
533 | static int __init nand_davinci_probe(struct platform_device *pdev) |
534 | { | |
535 | struct davinci_nand_pdata *pdata = pdev->dev.platform_data; | |
536 | struct davinci_nand_info *info; | |
537 | struct resource *res1; | |
538 | struct resource *res2; | |
539 | void __iomem *vaddr; | |
540 | void __iomem *base; | |
541 | int ret; | |
542 | uint32_t val; | |
543 | nand_ecc_modes_t ecc_mode; | |
544 | ||
533a0149 DB |
545 | /* insist on board-specific configuration */ |
546 | if (!pdata) | |
547 | return -ENODEV; | |
548 | ||
ff4569c7 DB |
549 | /* which external chipselect will we be managing? */ |
550 | if (pdev->id < 0 || pdev->id > 3) | |
551 | return -ENODEV; | |
552 | ||
553 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
554 | if (!info) { | |
555 | dev_err(&pdev->dev, "unable to allocate memory\n"); | |
556 | ret = -ENOMEM; | |
557 | goto err_nomem; | |
558 | } | |
559 | ||
560 | platform_set_drvdata(pdev, info); | |
561 | ||
562 | res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
563 | res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
564 | if (!res1 || !res2) { | |
565 | dev_err(&pdev->dev, "resource missing\n"); | |
566 | ret = -EINVAL; | |
567 | goto err_nomem; | |
568 | } | |
569 | ||
570 | vaddr = ioremap(res1->start, res1->end - res1->start); | |
571 | base = ioremap(res2->start, res2->end - res2->start); | |
572 | if (!vaddr || !base) { | |
573 | dev_err(&pdev->dev, "ioremap failed\n"); | |
574 | ret = -EINVAL; | |
575 | goto err_ioremap; | |
576 | } | |
577 | ||
578 | info->dev = &pdev->dev; | |
579 | info->base = base; | |
580 | info->vaddr = vaddr; | |
581 | ||
582 | info->mtd.priv = &info->chip; | |
583 | info->mtd.name = dev_name(&pdev->dev); | |
584 | info->mtd.owner = THIS_MODULE; | |
585 | ||
87f39f04 DB |
586 | info->mtd.dev.parent = &pdev->dev; |
587 | ||
ff4569c7 DB |
588 | info->chip.IO_ADDR_R = vaddr; |
589 | info->chip.IO_ADDR_W = vaddr; | |
590 | info->chip.chip_delay = 0; | |
591 | info->chip.select_chip = nand_davinci_select_chip; | |
592 | ||
593 | /* options such as NAND_USE_FLASH_BBT or 16-bit widths */ | |
533a0149 | 594 | info->chip.options = pdata->options; |
f611a79f MG |
595 | info->chip.bbt_td = pdata->bbt_td; |
596 | info->chip.bbt_md = pdata->bbt_md; | |
ff4569c7 DB |
597 | |
598 | info->ioaddr = (uint32_t __force) vaddr; | |
599 | ||
600 | info->current_cs = info->ioaddr; | |
601 | info->core_chipsel = pdev->id; | |
602 | info->mask_chipsel = pdata->mask_chipsel; | |
603 | ||
604 | /* use nandboot-capable ALE/CLE masks by default */ | |
5cd0be8e | 605 | info->mask_ale = pdata->mask_ale ? : MASK_ALE; |
533a0149 | 606 | info->mask_cle = pdata->mask_cle ? : MASK_CLE; |
ff4569c7 DB |
607 | |
608 | /* Set address of hardware control function */ | |
609 | info->chip.cmd_ctrl = nand_davinci_hwcontrol; | |
610 | info->chip.dev_ready = nand_davinci_dev_ready; | |
611 | ||
612 | /* Speed up buffer I/O */ | |
613 | info->chip.read_buf = nand_davinci_read_buf; | |
614 | info->chip.write_buf = nand_davinci_write_buf; | |
615 | ||
533a0149 DB |
616 | /* Use board-specific ECC config */ |
617 | ecc_mode = pdata->ecc_mode; | |
ff4569c7 | 618 | |
6a4123e5 | 619 | ret = -EINVAL; |
ff4569c7 DB |
620 | switch (ecc_mode) { |
621 | case NAND_ECC_NONE: | |
622 | case NAND_ECC_SOFT: | |
6a4123e5 | 623 | pdata->ecc_bits = 0; |
ff4569c7 DB |
624 | break; |
625 | case NAND_ECC_HW: | |
6a4123e5 DB |
626 | if (pdata->ecc_bits == 4) { |
627 | /* No sanity checks: CPUs must support this, | |
628 | * and the chips may not use NAND_BUSWIDTH_16. | |
629 | */ | |
630 | ||
631 | /* No sharing 4-bit hardware between chipselects yet */ | |
632 | spin_lock_irq(&davinci_nand_lock); | |
633 | if (ecc4_busy) | |
634 | ret = -EBUSY; | |
635 | else | |
636 | ecc4_busy = true; | |
637 | spin_unlock_irq(&davinci_nand_lock); | |
638 | ||
639 | if (ret == -EBUSY) | |
640 | goto err_ecc; | |
641 | ||
642 | info->chip.ecc.calculate = nand_davinci_calculate_4bit; | |
643 | info->chip.ecc.correct = nand_davinci_correct_4bit; | |
644 | info->chip.ecc.hwctl = nand_davinci_hwctl_4bit; | |
645 | info->chip.ecc.bytes = 10; | |
646 | } else { | |
647 | info->chip.ecc.calculate = nand_davinci_calculate_1bit; | |
648 | info->chip.ecc.correct = nand_davinci_correct_1bit; | |
649 | info->chip.ecc.hwctl = nand_davinci_hwctl_1bit; | |
650 | info->chip.ecc.bytes = 3; | |
651 | } | |
ff4569c7 | 652 | info->chip.ecc.size = 512; |
ff4569c7 | 653 | break; |
ff4569c7 DB |
654 | default: |
655 | ret = -EINVAL; | |
656 | goto err_ecc; | |
657 | } | |
658 | info->chip.ecc.mode = ecc_mode; | |
659 | ||
cd24f8c1 | 660 | info->clk = clk_get(&pdev->dev, "aemif"); |
ff4569c7 DB |
661 | if (IS_ERR(info->clk)) { |
662 | ret = PTR_ERR(info->clk); | |
cd24f8c1 | 663 | dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret); |
ff4569c7 DB |
664 | goto err_clk; |
665 | } | |
666 | ||
667 | ret = clk_enable(info->clk); | |
668 | if (ret < 0) { | |
cd24f8c1 KH |
669 | dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n", |
670 | ret); | |
ff4569c7 DB |
671 | goto err_clk_enable; |
672 | } | |
673 | ||
674 | /* EMIF timings should normally be set by the boot loader, | |
675 | * especially after boot-from-NAND. The *only* reason to | |
676 | * have this special casing for the DM6446 EVM is to work | |
677 | * with boot-from-NOR ... with CS0 manually re-jumpered | |
678 | * (after startup) so it addresses the NAND flash, not NOR. | |
679 | * Even for dev boards, that's unusually rude... | |
680 | */ | |
681 | if (machine_is_davinci_evm()) | |
682 | nand_dm6446evm_flash_init(info); | |
683 | ||
684 | spin_lock_irq(&davinci_nand_lock); | |
685 | ||
686 | /* put CSxNAND into NAND mode */ | |
687 | val = davinci_nand_readl(info, NANDFCR_OFFSET); | |
688 | val |= BIT(info->core_chipsel); | |
689 | davinci_nand_writel(info, NANDFCR_OFFSET, val); | |
690 | ||
691 | spin_unlock_irq(&davinci_nand_lock); | |
692 | ||
693 | /* Scan to find existence of the device(s) */ | |
6a4123e5 | 694 | ret = nand_scan_ident(&info->mtd, pdata->mask_chipsel ? 2 : 1); |
ff4569c7 DB |
695 | if (ret < 0) { |
696 | dev_dbg(&pdev->dev, "no NAND chip(s) found\n"); | |
697 | goto err_scan; | |
698 | } | |
699 | ||
6a4123e5 DB |
700 | /* Update ECC layout if needed ... for 1-bit HW ECC, the default |
701 | * is OK, but it allocates 6 bytes when only 3 are needed (for | |
702 | * each 512 bytes). For the 4-bit HW ECC, that default is not | |
703 | * usable: 10 bytes are needed, not 6. | |
704 | */ | |
705 | if (pdata->ecc_bits == 4) { | |
706 | int chunks = info->mtd.writesize / 512; | |
707 | ||
708 | if (!chunks || info->mtd.oobsize < 16) { | |
709 | dev_dbg(&pdev->dev, "too small\n"); | |
710 | ret = -EINVAL; | |
711 | goto err_scan; | |
712 | } | |
713 | ||
714 | /* For small page chips, preserve the manufacturer's | |
715 | * badblock marking data ... and make sure a flash BBT | |
716 | * table marker fits in the free bytes. | |
717 | */ | |
718 | if (chunks == 1) { | |
719 | info->ecclayout = hwecc4_small; | |
720 | info->ecclayout.oobfree[1].length = | |
721 | info->mtd.oobsize - 16; | |
722 | goto syndrome_done; | |
723 | } | |
f12a9473 SN |
724 | if (chunks == 4) { |
725 | info->ecclayout = hwecc4_2048; | |
726 | info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST; | |
727 | goto syndrome_done; | |
728 | } | |
6a4123e5 | 729 | |
f12a9473 SN |
730 | /* 4KiB page chips are not yet supported. The eccpos from |
731 | * nand_ecclayout cannot hold 80 bytes and change to eccpos[] | |
732 | * breaks userspace ioctl interface with mtd-utils. Once we | |
733 | * resolve this issue, NAND_ECC_HW_OOB_FIRST mode can be used | |
734 | * for the 4KiB page chips. | |
6a4123e5 DB |
735 | */ |
736 | dev_warn(&pdev->dev, "no 4-bit ECC support yet " | |
f12a9473 | 737 | "for 4KiB-page NAND\n"); |
6a4123e5 DB |
738 | ret = -EIO; |
739 | goto err_scan; | |
740 | ||
741 | syndrome_done: | |
742 | info->chip.ecc.layout = &info->ecclayout; | |
743 | } | |
744 | ||
745 | ret = nand_scan_tail(&info->mtd); | |
746 | if (ret < 0) | |
747 | goto err_scan; | |
748 | ||
ff4569c7 DB |
749 | if (mtd_has_partitions()) { |
750 | struct mtd_partition *mtd_parts = NULL; | |
751 | int mtd_parts_nb = 0; | |
752 | ||
753 | if (mtd_has_cmdlinepart()) { | |
754 | static const char *probes[] __initconst = | |
755 | { "cmdlinepart", NULL }; | |
756 | ||
ff4569c7 DB |
757 | mtd_parts_nb = parse_mtd_partitions(&info->mtd, probes, |
758 | &mtd_parts, 0); | |
ff4569c7 DB |
759 | } |
760 | ||
533a0149 | 761 | if (mtd_parts_nb <= 0) { |
ff4569c7 DB |
762 | mtd_parts = pdata->parts; |
763 | mtd_parts_nb = pdata->nr_parts; | |
764 | } | |
765 | ||
766 | /* Register any partitions */ | |
767 | if (mtd_parts_nb > 0) { | |
768 | ret = add_mtd_partitions(&info->mtd, | |
769 | mtd_parts, mtd_parts_nb); | |
770 | if (ret == 0) | |
771 | info->partitioned = true; | |
772 | } | |
773 | ||
533a0149 | 774 | } else if (pdata->nr_parts) { |
ff4569c7 DB |
775 | dev_warn(&pdev->dev, "ignoring %d default partitions on %s\n", |
776 | pdata->nr_parts, info->mtd.name); | |
777 | } | |
778 | ||
779 | /* If there's no partition info, just package the whole chip | |
780 | * as a single MTD device. | |
781 | */ | |
782 | if (!info->partitioned) | |
783 | ret = add_mtd_device(&info->mtd) ? -ENODEV : 0; | |
784 | ||
785 | if (ret < 0) | |
786 | goto err_scan; | |
787 | ||
788 | val = davinci_nand_readl(info, NRCSR_OFFSET); | |
789 | dev_info(&pdev->dev, "controller rev. %d.%d\n", | |
790 | (val >> 8) & 0xff, val & 0xff); | |
791 | ||
792 | return 0; | |
793 | ||
794 | err_scan: | |
795 | clk_disable(info->clk); | |
796 | ||
797 | err_clk_enable: | |
798 | clk_put(info->clk); | |
799 | ||
6a4123e5 DB |
800 | spin_lock_irq(&davinci_nand_lock); |
801 | if (ecc_mode == NAND_ECC_HW_SYNDROME) | |
802 | ecc4_busy = false; | |
803 | spin_unlock_irq(&davinci_nand_lock); | |
804 | ||
ff4569c7 DB |
805 | err_ecc: |
806 | err_clk: | |
807 | err_ioremap: | |
808 | if (base) | |
809 | iounmap(base); | |
810 | if (vaddr) | |
811 | iounmap(vaddr); | |
812 | ||
813 | err_nomem: | |
814 | kfree(info); | |
815 | return ret; | |
816 | } | |
817 | ||
818 | static int __exit nand_davinci_remove(struct platform_device *pdev) | |
819 | { | |
820 | struct davinci_nand_info *info = platform_get_drvdata(pdev); | |
821 | int status; | |
822 | ||
823 | if (mtd_has_partitions() && info->partitioned) | |
824 | status = del_mtd_partitions(&info->mtd); | |
825 | else | |
826 | status = del_mtd_device(&info->mtd); | |
827 | ||
6a4123e5 DB |
828 | spin_lock_irq(&davinci_nand_lock); |
829 | if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME) | |
830 | ecc4_busy = false; | |
831 | spin_unlock_irq(&davinci_nand_lock); | |
832 | ||
ff4569c7 DB |
833 | iounmap(info->base); |
834 | iounmap(info->vaddr); | |
835 | ||
836 | nand_release(&info->mtd); | |
837 | ||
838 | clk_disable(info->clk); | |
839 | clk_put(info->clk); | |
840 | ||
841 | kfree(info); | |
842 | ||
843 | return 0; | |
844 | } | |
845 | ||
846 | static struct platform_driver nand_davinci_driver = { | |
847 | .remove = __exit_p(nand_davinci_remove), | |
848 | .driver = { | |
849 | .name = "davinci_nand", | |
850 | }, | |
851 | }; | |
852 | MODULE_ALIAS("platform:davinci_nand"); | |
853 | ||
854 | static int __init nand_davinci_init(void) | |
855 | { | |
856 | return platform_driver_probe(&nand_davinci_driver, nand_davinci_probe); | |
857 | } | |
858 | module_init(nand_davinci_init); | |
859 | ||
860 | static void __exit nand_davinci_exit(void) | |
861 | { | |
862 | platform_driver_unregister(&nand_davinci_driver); | |
863 | } | |
864 | module_exit(nand_davinci_exit); | |
865 | ||
866 | MODULE_LICENSE("GPL"); | |
867 | MODULE_AUTHOR("Texas Instruments"); | |
868 | MODULE_DESCRIPTION("Davinci NAND flash driver"); | |
869 |