[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mtd / nand / davinci_nand.c

/*
 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
 *
 * Copyright © 2006 Texas Instruments.
 *
 * Port to 2.6.23 Copyright © 2008 by:
 *   Sander Huijsen <Shuijsen@optelecom-nkf.com>
 *   Troy Kisky <troy.kisky@boundarydevices.com>
 *   Dirk Behme <Dirk.Behme@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>

#include <mach/nand.h>

#include <asm/mach-types.h>


/*
 * This is a device driver for the NAND flash controller found on the
 * various DaVinci family chips.  It handles up to four SoC chipselects,
 * and some flavors of secondary chipselect (e.g. based on A12) as used
 * with multichip packages.
 *
 * The 1-bit ECC hardware is supported, but not yet the newer 4-bit ECC
 * available on chips like the DM355 and OMAP-L137 and needed with the
 * more error-prone MLC NAND chips.
 *
 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
 * outputs in a "wire-AND" configuration, with no per-chip signals.
 */
struct davinci_nand_info {
	struct mtd_info		mtd;
	struct nand_chip	chip;

	struct device		*dev;
	struct clk		*clk;
	bool			partitioned;

	void __iomem		*base;
	void __iomem		*vaddr;

	uint32_t		ioaddr;
	uint32_t		current_cs;

	uint32_t		mask_chipsel;
	uint32_t		mask_ale;
	uint32_t		mask_cle;

	uint32_t		core_chipsel;
};

static DEFINE_SPINLOCK(davinci_nand_lock);

#define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd)


static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
		int offset)
{
	return __raw_readl(info->base + offset);
}

static inline void davinci_nand_writel(struct davinci_nand_info *info,
		int offset, unsigned long value)
{
	__raw_writel(value, info->base + offset);
}

/*----------------------------------------------------------------------*/

/*
 * Access to hardware control lines:  ALE, CLE, secondary chipselect.
 */

static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
				   unsigned int ctrl)
{
	struct davinci_nand_info	*info = to_davinci_nand(mtd);
	uint32_t			addr = info->current_cs;
	struct nand_chip		*nand = mtd->priv;

	/* Did the control lines change? */
	if (ctrl & NAND_CTRL_CHANGE) {
		if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE)
			addr |= info->mask_cle;
		else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
			addr |= info->mask_ale;

		nand->IO_ADDR_W = (void __iomem __force *)addr;
	}

	if (cmd != NAND_CMD_NONE)
		iowrite8(cmd, nand->IO_ADDR_W);
}

static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
{
	struct davinci_nand_info	*info = to_davinci_nand(mtd);
	uint32_t			addr = info->ioaddr;

	/* maybe kick in a second chipselect */
	if (chip > 0)
		addr |= info->mask_chipsel;
	info->current_cs = addr;

	info->chip.IO_ADDR_W = (void __iomem __force *)addr;
	info->chip.IO_ADDR_R = info->chip.IO_ADDR_W;
}

/*----------------------------------------------------------------------*/

/*
 * 1-bit hardware ECC ... context maintained for each core chipselect
 */

static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
{
	struct davinci_nand_info *info = to_davinci_nand(mtd);

	return davinci_nand_readl(info, NANDF1ECC_OFFSET
			+ 4 * info->core_chipsel);
}

static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode)
{
	struct davinci_nand_info *info;
	uint32_t nandcfr;
	unsigned long flags;

	info = to_davinci_nand(mtd);

	/* Reset ECC hardware */
	nand_davinci_readecc_1bit(mtd);

	spin_lock_irqsave(&davinci_nand_lock, flags);

	/* Restart ECC hardware */
	nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
	nandcfr |= BIT(8 + info->core_chipsel);
	davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);

	spin_unlock_irqrestore(&davinci_nand_lock, flags);
}

/*
 * Read hardware ECC value and pack into three bytes
 */
static int nand_davinci_calculate_1bit(struct mtd_info *mtd,
				      const u_char *dat, u_char *ecc_code)
{
	unsigned int ecc_val = nand_davinci_readecc_1bit(mtd);
	unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);

	/* invert so that erased block ecc is correct */
	ecc24 = ~ecc24;
	ecc_code[0] = (u_char)(ecc24);
	ecc_code[1] = (u_char)(ecc24 >> 8);
	ecc_code[2] = (u_char)(ecc24 >> 16);

	return 0;
}

static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat,
				     u_char *read_ecc, u_char *calc_ecc)
{
	struct nand_chip *chip = mtd->priv;
	uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
					  (read_ecc[2] << 16);
	uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
					  (calc_ecc[2] << 16);
	uint32_t diff = eccCalc ^ eccNand;

	if (diff) {
		if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
			/* Correctable error */
			if ((diff >> (12 + 3)) < chip->ecc.size) {
				dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7);
				return 1;
			} else {
				return -1;
			}
		} else if (!(diff & (diff - 1))) {
			/* Single bit ECC error in the ECC itself,
			 * nothing to fix */
			return 1;
		} else {
			/* Uncorrectable error */
			return -1;
		}

	}
	return 0;
}

/*----------------------------------------------------------------------*/

/*
 * NOTE:  NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
 * how these chips are normally wired.  This translates to both 8 and 16
 * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
 *
 * For now we assume that configuration, or any other one which ignores
 * the two LSBs for NAND access ... so we can issue 32-bit reads/writes
 * and have that transparently morphed into multiple NAND operations.
 */
static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
	struct nand_chip *chip = mtd->priv;

	if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
		ioread32_rep(chip->IO_ADDR_R, buf, len >> 2);
	else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
		ioread16_rep(chip->IO_ADDR_R, buf, len >> 1);
	else
		ioread8_rep(chip->IO_ADDR_R, buf, len);
}

static void nand_davinci_write_buf(struct mtd_info *mtd,
		const uint8_t *buf, int len)
{
	struct nand_chip *chip = mtd->priv;

	if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
		iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2);
	else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
		iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1);
	else
		iowrite8_rep(chip->IO_ADDR_R, buf, len);
}

/*
 * Check hardware register for wait status. Returns 1 if device is ready,
 * 0 if it is still busy.
 */
static int nand_davinci_dev_ready(struct mtd_info *mtd)
{
	struct davinci_nand_info *info = to_davinci_nand(mtd);

	return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
}

static void __init nand_dm6446evm_flash_init(struct davinci_nand_info *info)
{
	uint32_t regval, a1cr;

	/*
	 * NAND FLASH timings @ PLL1 == 459 MHz
	 *  - AEMIF.CLK freq   = PLL1/6 = 459/6 = 76.5 MHz
	 *  - AEMIF.CLK period = 1/76.5 MHz = 13.1 ns
	 */
	regval = 0
		| (0 << 31)           /* selectStrobe */
		| (0 << 30)           /* extWait (never with NAND) */
		| (1 << 26)           /* writeSetup      10 ns */
		| (3 << 20)           /* writeStrobe     40 ns */
		| (1 << 17)           /* writeHold       10 ns */
		| (0 << 13)           /* readSetup       10 ns */
		| (3 << 7)            /* readStrobe      60 ns */
		| (0 << 4)            /* readHold        10 ns */
		| (3 << 2)            /* turnAround      ?? ns */
		| (0 << 0)            /* asyncSize       8-bit bus */
		;
	a1cr = davinci_nand_readl(info, A1CR_OFFSET);
	if (a1cr != regval) {
		dev_dbg(info->dev, "Warning: NAND config: Set A1CR " \
		       "reg to 0x%08x, was 0x%08x, should be done by " \
		       "bootloader.\n", regval, a1cr);
		davinci_nand_writel(info, A1CR_OFFSET, regval);
	}
}

/*----------------------------------------------------------------------*/

static int __init nand_davinci_probe(struct platform_device *pdev)
{
	struct davinci_nand_pdata	*pdata = pdev->dev.platform_data;
	struct davinci_nand_info	*info;
	struct resource			*res1;
	struct resource			*res2;
	void __iomem			*vaddr;
	void __iomem			*base;
	int				ret;
	uint32_t			val;
	nand_ecc_modes_t		ecc_mode;

	/* which external chipselect will we be managing? */
	if (pdev->id < 0 || pdev->id > 3)
		return -ENODEV;

	info = kzalloc(sizeof(*info), GFP_KERNEL);
	if (!info) {
		dev_err(&pdev->dev, "unable to allocate memory\n");
		ret = -ENOMEM;
		goto err_nomem;
	}

	platform_set_drvdata(pdev, info);

	res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res1 || !res2) {
		dev_err(&pdev->dev, "resource missing\n");
		ret = -EINVAL;
		goto err_nomem;
	}

	vaddr = ioremap(res1->start, res1->end - res1->start);
	base = ioremap(res2->start, res2->end - res2->start);
	if (!vaddr || !base) {
		dev_err(&pdev->dev, "ioremap failed\n");
		ret = -EINVAL;
		goto err_ioremap;
	}

	info->dev		= &pdev->dev;
	info->base		= base;
	info->vaddr		= vaddr;

	info->mtd.priv		= &info->chip;
	info->mtd.name		= dev_name(&pdev->dev);
	info->mtd.owner		= THIS_MODULE;

	info->mtd.dev.parent	= &pdev->dev;

	info->chip.IO_ADDR_R	= vaddr;
	info->chip.IO_ADDR_W	= vaddr;
	info->chip.chip_delay	= 0;
	info->chip.select_chip	= nand_davinci_select_chip;

	/* options such as NAND_USE_FLASH_BBT or 16-bit widths */
	info->chip.options	= pdata ? pdata->options : 0;

	info->ioaddr		= (uint32_t __force) vaddr;

	info->current_cs	= info->ioaddr;
	info->core_chipsel	= pdev->id;
	info->mask_chipsel	= pdata->mask_chipsel;

	/* use nandboot-capable ALE/CLE masks by default */
	if (pdata && pdata->mask_ale)
		info->mask_ale	= pdata->mask_cle;
	else
		info->mask_ale	= MASK_ALE;
	if (pdata && pdata->mask_cle)
		info->mask_cle	= pdata->mask_cle;
	else
		info->mask_cle	= MASK_CLE;

	/* Set address of hardware control function */
	info->chip.cmd_ctrl	= nand_davinci_hwcontrol;
	info->chip.dev_ready	= nand_davinci_dev_ready;

	/* Speed up buffer I/O */
	info->chip.read_buf     = nand_davinci_read_buf;
	info->chip.write_buf    = nand_davinci_write_buf;

	/* use board-specific ECC config; else, the best available */
	if (pdata)
		ecc_mode = pdata->ecc_mode;
	else
		ecc_mode = NAND_ECC_HW;

	switch (ecc_mode) {
	case NAND_ECC_NONE:
	case NAND_ECC_SOFT:
		break;
	case NAND_ECC_HW:
		info->chip.ecc.calculate = nand_davinci_calculate_1bit;
		info->chip.ecc.correct = nand_davinci_correct_1bit;
		info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
		info->chip.ecc.size = 512;
		info->chip.ecc.bytes = 3;
		break;
	case NAND_ECC_HW_SYNDROME:
		/* FIXME implement */
		info->chip.ecc.size = 512;
		info->chip.ecc.bytes = 10;

		dev_warn(&pdev->dev, "4-bit ECC nyet supported\n");
		/* FALL THROUGH */
	default:
		ret = -EINVAL;
		goto err_ecc;
	}
	info->chip.ecc.mode = ecc_mode;

	info->clk = clk_get(&pdev->dev, "AEMIFCLK");
	if (IS_ERR(info->clk)) {
		ret = PTR_ERR(info->clk);
		dev_dbg(&pdev->dev, "unable to get AEMIFCLK, err %d\n", ret);
		goto err_clk;
	}

	ret = clk_enable(info->clk);
	if (ret < 0) {
		dev_dbg(&pdev->dev, "unable to enable AEMIFCLK, err %d\n", ret);
		goto err_clk_enable;
	}

	/* EMIF timings should normally be set by the boot loader,
	 * especially after boot-from-NAND.  The *only* reason to
	 * have this special casing for the DM6446 EVM is to work
	 * with boot-from-NOR ... with CS0 manually re-jumpered
	 * (after startup) so it addresses the NAND flash, not NOR.
	 * Even for dev boards, that's unusually rude...
	 */
	if (machine_is_davinci_evm())
		nand_dm6446evm_flash_init(info);

	spin_lock_irq(&davinci_nand_lock);

	/* put CSxNAND into NAND mode */
	val = davinci_nand_readl(info, NANDFCR_OFFSET);
	val |= BIT(info->core_chipsel);
	davinci_nand_writel(info, NANDFCR_OFFSET, val);

	spin_unlock_irq(&davinci_nand_lock);

	/* Scan to find existence of the device(s) */
	ret = nand_scan(&info->mtd, pdata->mask_chipsel ? 2 : 1);
	if (ret < 0) {
		dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
		goto err_scan;
	}

	if (mtd_has_partitions()) {
		struct mtd_partition	*mtd_parts = NULL;
		int			mtd_parts_nb = 0;

		if (mtd_has_cmdlinepart()) {
			static const char *probes[] __initconst =
				{ "cmdlinepart", NULL };

			const char		*master_name;

			/* Set info->mtd.name = 0 temporarily */
			master_name		= info->mtd.name;
			info->mtd.name		= (char *)0;

			/* info->mtd.name == 0, means: don't bother checking
			   <mtd-id> */
			mtd_parts_nb = parse_mtd_partitions(&info->mtd, probes,
							    &mtd_parts, 0);

			/* Restore info->mtd.name */
			info->mtd.name = master_name;
		}

		if (mtd_parts_nb <= 0 && pdata) {
			mtd_parts = pdata->parts;
			mtd_parts_nb = pdata->nr_parts;
		}

		/* Register any partitions */
		if (mtd_parts_nb > 0) {
			ret = add_mtd_partitions(&info->mtd,
					mtd_parts, mtd_parts_nb);
			if (ret == 0)
				info->partitioned = true;
		}

	} else if (pdata && pdata->nr_parts) {
		dev_warn(&pdev->dev, "ignoring %d default partitions on %s\n",
				pdata->nr_parts, info->mtd.name);
	}

	/* If there's no partition info, just package the whole chip
	 * as a single MTD device.
	 */
	if (!info->partitioned)
		ret = add_mtd_device(&info->mtd) ? -ENODEV : 0;

	if (ret < 0)
		goto err_scan;

	val = davinci_nand_readl(info, NRCSR_OFFSET);
	dev_info(&pdev->dev, "controller rev. %d.%d\n",
	       (val >> 8) & 0xff, val & 0xff);

	return 0;

err_scan:
	clk_disable(info->clk);

err_clk_enable:
	clk_put(info->clk);

err_ecc:
err_clk:
err_ioremap:
	if (base)
		iounmap(base);
	if (vaddr)
		iounmap(vaddr);

err_nomem:
	kfree(info);
	return ret;
}

static int __exit nand_davinci_remove(struct platform_device *pdev)
{
	struct davinci_nand_info *info = platform_get_drvdata(pdev);
	int status;

	if (mtd_has_partitions() && info->partitioned)
		status = del_mtd_partitions(&info->mtd);
	else
		status = del_mtd_device(&info->mtd);

	iounmap(info->base);
	iounmap(info->vaddr);

	nand_release(&info->mtd);

	clk_disable(info->clk);
	clk_put(info->clk);

	kfree(info);

	return 0;
}

static struct platform_driver nand_davinci_driver = {
	.remove		= __exit_p(nand_davinci_remove),
	.driver		= {
		.name	= "davinci_nand",
	},
};
MODULE_ALIAS("platform:davinci_nand");

static int __init nand_davinci_init(void)
{
	return platform_driver_probe(&nand_davinci_driver, nand_davinci_probe);
}
module_init(nand_davinci_init);

static void __exit nand_davinci_exit(void)
{
	platform_driver_unregister(&nand_davinci_driver);
}
module_exit(nand_davinci_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Texas Instruments");
MODULE_DESCRIPTION("Davinci NAND flash driver");
Commit	Line	Data
ff4569c7 DB	1	/*
	2	* davinci_nand.c - NAND Flash Driver for DaVinci family chips
	3	*
	4	* Copyright © 2006 Texas Instruments.
	5	*
	6	* Port to 2.6.23 Copyright © 2008 by:
	7	* Sander Huijsen <Shuijsen@optelecom-nkf.com>
	8	* Troy Kisky <troy.kisky@boundarydevices.com>
	9	* Dirk Behme <Dirk.Behme@gmail.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	24	*/
	25
	26	#include <linux/kernel.h>
	27	#include <linux/init.h>
	28	#include <linux/module.h>
	29	#include <linux/platform_device.h>
	30	#include <linux/err.h>
	31	#include <linux/clk.h>
	32	#include <linux/io.h>
	33	#include <linux/mtd/nand.h>
	34	#include <linux/mtd/partitions.h>
	35
ff4569c7 DB	36	#include <mach/nand.h>
	37
	38	#include <asm/mach-types.h>
	39
	40
ff4569c7 DB	41	/*
	42	* This is a device driver for the NAND flash controller found on the
	43	* various DaVinci family chips. It handles up to four SoC chipselects,
	44	* and some flavors of secondary chipselect (e.g. based on A12) as used
	45	* with multichip packages.
	46	*
	47	* The 1-bit ECC hardware is supported, but not yet the newer 4-bit ECC
	48	* available on chips like the DM355 and OMAP-L137 and needed with the
	49	* more error-prone MLC NAND chips.
	50	*
	51	* This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
	52	* outputs in a "wire-AND" configuration, with no per-chip signals.
	53	*/
	54	struct davinci_nand_info {
	55	struct mtd_info mtd;
	56	struct nand_chip chip;
	57
	58	struct device *dev;
	59	struct clk *clk;
	60	bool partitioned;
	61
	62	void __iomem *base;
	63	void __iomem *vaddr;
	64
	65	uint32_t ioaddr;
	66	uint32_t current_cs;
	67
	68	uint32_t mask_chipsel;
	69	uint32_t mask_ale;
	70	uint32_t mask_cle;
	71
	72	uint32_t core_chipsel;
	73	};
	74
	75	static DEFINE_SPINLOCK(davinci_nand_lock);
	76
	77	#define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd)
	78
	79
	80	static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
	81	int offset)
	82	{
	83	return __raw_readl(info->base + offset);
	84	}
	85
	86	static inline void davinci_nand_writel(struct davinci_nand_info *info,
	87	int offset, unsigned long value)
	88	{
	89	__raw_writel(value, info->base + offset);
	90	}
	91
	92	/----------------------------------------------------------------------/
	93
	94	/*
	95	* Access to hardware control lines: ALE, CLE, secondary chipselect.
	96	*/
	97
	98	static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
	99	unsigned int ctrl)
	100	{
	101	struct davinci_nand_info *info = to_davinci_nand(mtd);
	102	uint32_t addr = info->current_cs;
	103	struct nand_chip *nand = mtd->priv;
	104
105	/* Did the control lines change? */
106	if (ctrl & NAND_CTRL_CHANGE) {
107	if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE)
108	addr \|= info->mask_cle;
109	else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
110	addr \|= info->mask_ale;
111
112	nand->IO_ADDR_W = (void __iomem __force *)addr;
113	}
114
115	if (cmd != NAND_CMD_NONE)
116	iowrite8(cmd, nand->IO_ADDR_W);
117	}
118
119	static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
120	{
121	struct davinci_nand_info *info = to_davinci_nand(mtd);
122	uint32_t addr = info->ioaddr;
123
124	/* maybe kick in a second chipselect */
125	if (chip > 0)
126	addr \|= info->mask_chipsel;
127	info->current_cs = addr;
128
129	info->chip.IO_ADDR_W = (void __iomem __force *)addr;
130	info->chip.IO_ADDR_R = info->chip.IO_ADDR_W;
131	}
132
133	/----------------------------------------------------------------------/
134
135	/*
136	* 1-bit hardware ECC ... context maintained for each core chipselect
137	*/
138
139	static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
140	{
141	struct davinci_nand_info *info = to_davinci_nand(mtd);
142
143	return davinci_nand_readl(info, NANDF1ECC_OFFSET
144	+ 4 * info->core_chipsel);
145	}
146
147	static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode)
148	{
149	struct davinci_nand_info *info;
150	uint32_t nandcfr;
151	unsigned long flags;
152
153	info = to_davinci_nand(mtd);
154
155	/* Reset ECC hardware */
156	nand_davinci_readecc_1bit(mtd);
157
158	spin_lock_irqsave(&davinci_nand_lock, flags);
159
160	/* Restart ECC hardware */
161	nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
162	nandcfr \|= BIT(8 + info->core_chipsel);
163	davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);
164
165	spin_unlock_irqrestore(&davinci_nand_lock, flags);
166	}
167
168	/*
169	* Read hardware ECC value and pack into three bytes
170	*/
171	static int nand_davinci_calculate_1bit(struct mtd_info *mtd,
172	const u_char dat, u_char ecc_code)
173	{
174	unsigned int ecc_val = nand_davinci_readecc_1bit(mtd);
175	unsigned int ecc24 = (ecc_val & 0x0fff) \| ((ecc_val & 0x0fff0000) >> 4);
176
177	/* invert so that erased block ecc is correct */
178	ecc24 = ~ecc24;
179	ecc_code[0] = (u_char)(ecc24);
180	ecc_code[1] = (u_char)(ecc24 >> 8);
181	ecc_code[2] = (u_char)(ecc24 >> 16);
182
183	return 0;
184	}
185
186	static int nand_davinci_correct_1bit(struct mtd_info mtd, u_char dat,
187	u_char read_ecc, u_char calc_ecc)
188	{
189	struct nand_chip *chip = mtd->priv;
190	uint32_t eccNand = read_ecc[0] \| (read_ecc[1] << 8) \|
191	(read_ecc[2] << 16);
192	uint32_t eccCalc = calc_ecc[0] \| (calc_ecc[1] << 8) \|
193	(calc_ecc[2] << 16);
194	uint32_t diff = eccCalc ^ eccNand;
195
196	if (diff) {
197	if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
198	/* Correctable error */
199	if ((diff >> (12 + 3)) < chip->ecc.size) {
200	dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7);
201	return 1;
202	} else {
203	return -1;
204	}
205	} else if (!(diff & (diff - 1))) {
206	/* Single bit ECC error in the ECC itself,
207	* nothing to fix */
208	return 1;
209	} else {
210	/* Uncorrectable error */
211	return -1;
212	}
213
214	}
215	return 0;
216	}
217
218	/----------------------------------------------------------------------/
219
220	/*
221	* NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
222	* how these chips are normally wired. This translates to both 8 and 16
223	* bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
224	*
225	* For now we assume that configuration, or any other one which ignores
226	* the two LSBs for NAND access ... so we can issue 32-bit reads/writes
227	* and have that transparently morphed into multiple NAND operations.
228	*/
229	static void nand_davinci_read_buf(struct mtd_info mtd, uint8_t buf, int len)
230	{
231	struct nand_chip *chip = mtd->priv;
232
233	if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
234	ioread32_rep(chip->IO_ADDR_R, buf, len >> 2);
235	else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
236	ioread16_rep(chip->IO_ADDR_R, buf, len >> 1);
237	else
238	ioread8_rep(chip->IO_ADDR_R, buf, len);
239	}
240
241	static void nand_davinci_write_buf(struct mtd_info *mtd,
242	const uint8_t *buf, int len)
243	{
244	struct nand_chip *chip = mtd->priv;
245
246	if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
247	iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2);
248	else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
249	iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1);
250	else
251	iowrite8_rep(chip->IO_ADDR_R, buf, len);
252	}
253
254	/*
255	* Check hardware register for wait status. Returns 1 if device is ready,
256	* 0 if it is still busy.
257	*/
258	static int nand_davinci_dev_ready(struct mtd_info *mtd)
259	{
260	struct davinci_nand_info *info = to_davinci_nand(mtd);
261
262	return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
263	}
264
265	static void __init nand_dm6446evm_flash_init(struct davinci_nand_info *info)
266	{
267	uint32_t regval, a1cr;
268
269	/*
270	* NAND FLASH timings @ PLL1 == 459 MHz
271	* - AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz
272	* - AEMIF.CLK period = 1/76.5 MHz = 13.1 ns
273	*/
274	regval = 0
275	\| (0 << 31) /* selectStrobe */
276	\| (0 << 30) /* extWait (never with NAND) */
277	\| (1 << 26) /* writeSetup 10 ns */
278	\| (3 << 20) /* writeStrobe 40 ns */
279	\| (1 << 17) /* writeHold 10 ns */
280	\| (0 << 13) /* readSetup 10 ns */
281	\| (3 << 7) /* readStrobe 60 ns */
282	\| (0 << 4) /* readHold 10 ns */
283	\| (3 << 2) /* turnAround ?? ns */
284	\| (0 << 0) /* asyncSize 8-bit bus */
285	;
286	a1cr = davinci_nand_readl(info, A1CR_OFFSET);
287	if (a1cr != regval) {
288	dev_dbg(info->dev, "Warning: NAND config: Set A1CR " \
289	"reg to 0x%08x, was 0x%08x, should be done by " \
290	"bootloader.\n", regval, a1cr);
291	davinci_nand_writel(info, A1CR_OFFSET, regval);
292	}
293	}
294
295	/----------------------------------------------------------------------/
296
297	static int __init nand_davinci_probe(struct platform_device *pdev)
298	{
299	struct davinci_nand_pdata *pdata = pdev->dev.platform_data;
300	struct davinci_nand_info *info;
301	struct resource *res1;
302	struct resource *res2;
303	void __iomem *vaddr;
304	void __iomem *base;
305	int ret;
306	uint32_t val;
307	nand_ecc_modes_t ecc_mode;
308
309	/* which external chipselect will we be managing? */
310	if (pdev->id < 0 \|\| pdev->id > 3)
311	return -ENODEV;
312
313	info = kzalloc(sizeof(*info), GFP_KERNEL);
314	if (!info) {
315	dev_err(&pdev->dev, "unable to allocate memory\n");
316	ret = -ENOMEM;
317	goto err_nomem;
318	}
319
320	platform_set_drvdata(pdev, info);
321
322	res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
323	res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
324	if (!res1 \|\| !res2) {
325	dev_err(&pdev->dev, "resource missing\n");
326	ret = -EINVAL;
327	goto err_nomem;
328	}
329
330	vaddr = ioremap(res1->start, res1->end - res1->start);
331	base = ioremap(res2->start, res2->end - res2->start);
332	if (!vaddr \|\| !base) {
333	dev_err(&pdev->dev, "ioremap failed\n");
334	ret = -EINVAL;
335	goto err_ioremap;
336	}
337
338	info->dev = &pdev->dev;
339	info->base = base;
340	info->vaddr = vaddr;
341
342	info->mtd.priv = &info->chip;
343	info->mtd.name = dev_name(&pdev->dev);
344	info->mtd.owner = THIS_MODULE;
345
87f39f04 DB	346	info->mtd.dev.parent = &pdev->dev;
87f39f04 DB	347
ff4569c7 DB	348	info->chip.IO_ADDR_R = vaddr;
	349	info->chip.IO_ADDR_W = vaddr;
	350	info->chip.chip_delay = 0;
	351	info->chip.select_chip = nand_davinci_select_chip;
	352
	353	/* options such as NAND_USE_FLASH_BBT or 16-bit widths */
	354	info->chip.options = pdata ? pdata->options : 0;
	355
	356	info->ioaddr = (uint32_t __force) vaddr;
	357
	358	info->current_cs = info->ioaddr;
	359	info->core_chipsel = pdev->id;
	360	info->mask_chipsel = pdata->mask_chipsel;
	361
	362	/* use nandboot-capable ALE/CLE masks by default */
	363	if (pdata && pdata->mask_ale)
	364	info->mask_ale = pdata->mask_cle;
	365	else
	366	info->mask_ale = MASK_ALE;
	367	if (pdata && pdata->mask_cle)
	368	info->mask_cle = pdata->mask_cle;
	369	else
	370	info->mask_cle = MASK_CLE;
	371
	372	/* Set address of hardware control function */
	373	info->chip.cmd_ctrl = nand_davinci_hwcontrol;
	374	info->chip.dev_ready = nand_davinci_dev_ready;
	375
	376	/* Speed up buffer I/O */
	377	info->chip.read_buf = nand_davinci_read_buf;
	378	info->chip.write_buf = nand_davinci_write_buf;
	379
	380	/* use board-specific ECC config; else, the best available */
	381	if (pdata)
	382	ecc_mode = pdata->ecc_mode;
ff4569c7 DB	383	else
	384	ecc_mode = NAND_ECC_HW;
	385
	386	switch (ecc_mode) {
	387	case NAND_ECC_NONE:
	388	case NAND_ECC_SOFT:
	389	break;
	390	case NAND_ECC_HW:
	391	info->chip.ecc.calculate = nand_davinci_calculate_1bit;
	392	info->chip.ecc.correct = nand_davinci_correct_1bit;
	393	info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
	394	info->chip.ecc.size = 512;
	395	info->chip.ecc.bytes = 3;
	396	break;
	397	case NAND_ECC_HW_SYNDROME:
	398	/* FIXME implement */
	399	info->chip.ecc.size = 512;
	400	info->chip.ecc.bytes = 10;
	401
	402	dev_warn(&pdev->dev, "4-bit ECC nyet supported\n");
	403	/* FALL THROUGH */
	404	default:
	405	ret = -EINVAL;
	406	goto err_ecc;
	407	}
	408	info->chip.ecc.mode = ecc_mode;
	409
	410	info->clk = clk_get(&pdev->dev, "AEMIFCLK");
	411	if (IS_ERR(info->clk)) {
	412	ret = PTR_ERR(info->clk);
	413	dev_dbg(&pdev->dev, "unable to get AEMIFCLK, err %d\n", ret);
	414	goto err_clk;
	415	}
	416
	417	ret = clk_enable(info->clk);
	418	if (ret < 0) {
	419	dev_dbg(&pdev->dev, "unable to enable AEMIFCLK, err %d\n", ret);
	420	goto err_clk_enable;
	421	}
	422
	423	/* EMIF timings should normally be set by the boot loader,
	424	* especially after boot-from-NAND. The only reason to
	425	* have this special casing for the DM6446 EVM is to work
	426	* with boot-from-NOR ... with CS0 manually re-jumpered
	427	* (after startup) so it addresses the NAND flash, not NOR.
	428	* Even for dev boards, that's unusually rude...
	429	*/
	430	if (machine_is_davinci_evm())
	431	nand_dm6446evm_flash_init(info);
	432
	433	spin_lock_irq(&davinci_nand_lock);
	434
	435	/* put CSxNAND into NAND mode */
	436	val = davinci_nand_readl(info, NANDFCR_OFFSET);
	437	val \|= BIT(info->core_chipsel);
	438	davinci_nand_writel(info, NANDFCR_OFFSET, val);
	439
	440	spin_unlock_irq(&davinci_nand_lock);
	441
	442	/* Scan to find existence of the device(s) */
	443	ret = nand_scan(&info->mtd, pdata->mask_chipsel ? 2 : 1);
	444	if (ret < 0) {
	445	dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
	446	goto err_scan;
447	}
448
449	if (mtd_has_partitions()) {
450	struct mtd_partition *mtd_parts = NULL;
451	int mtd_parts_nb = 0;
452
453	if (mtd_has_cmdlinepart()) {
454	static const char *probes[] __initconst =
455	{ "cmdlinepart", NULL };
456
457	const char *master_name;
458
459	/* Set info->mtd.name = 0 temporarily */
460	master_name = info->mtd.name;
461	info->mtd.name = (char *)0;
462
463	/* info->mtd.name == 0, means: don't bother checking
464	<mtd-id> */
465	mtd_parts_nb = parse_mtd_partitions(&info->mtd, probes,
466	&mtd_parts, 0);
467
468	/* Restore info->mtd.name */
469	info->mtd.name = master_name;
470	}
471
472	if (mtd_parts_nb <= 0 && pdata) {
473	mtd_parts = pdata->parts;
474	mtd_parts_nb = pdata->nr_parts;
475	}
476
477	/* Register any partitions */
478	if (mtd_parts_nb > 0) {
479	ret = add_mtd_partitions(&info->mtd,
480	mtd_parts, mtd_parts_nb);
481	if (ret == 0)
482	info->partitioned = true;
483	}
484
485	} else if (pdata && pdata->nr_parts) {
486	dev_warn(&pdev->dev, "ignoring %d default partitions on %s\n",
487	pdata->nr_parts, info->mtd.name);
488	}
489
490	/* If there's no partition info, just package the whole chip
491	* as a single MTD device.
492	*/
493	if (!info->partitioned)
494	ret = add_mtd_device(&info->mtd) ? -ENODEV : 0;
495
496	if (ret < 0)
497	goto err_scan;
498
499	val = davinci_nand_readl(info, NRCSR_OFFSET);
500	dev_info(&pdev->dev, "controller rev. %d.%d\n",
501	(val >> 8) & 0xff, val & 0xff);
502
503	return 0;
504
505	err_scan:
506	clk_disable(info->clk);
507
508	err_clk_enable:
509	clk_put(info->clk);
510
511	err_ecc:
512	err_clk:
513	err_ioremap:
514	if (base)
515	iounmap(base);
516	if (vaddr)
517	iounmap(vaddr);
518
519	err_nomem:
520	kfree(info);
521	return ret;
522	}
523
524	static int __exit nand_davinci_remove(struct platform_device *pdev)
525	{
526	struct davinci_nand_info *info = platform_get_drvdata(pdev);
527	int status;
528
529	if (mtd_has_partitions() && info->partitioned)
530	status = del_mtd_partitions(&info->mtd);
531	else
532	status = del_mtd_device(&info->mtd);
533
534	iounmap(info->base);
535	iounmap(info->vaddr);
536
537	nand_release(&info->mtd);
538
539	clk_disable(info->clk);
540	clk_put(info->clk);
541
542	kfree(info);
543
544	return 0;
545	}
546
547	static struct platform_driver nand_davinci_driver = {
548	.remove = __exit_p(nand_davinci_remove),
549	.driver = {
550	.name = "davinci_nand",
551	},
552	};
553	MODULE_ALIAS("platform:davinci_nand");
554
555	static int __init nand_davinci_init(void)
556	{
557	return platform_driver_probe(&nand_davinci_driver, nand_davinci_probe);
558	}
559	module_init(nand_davinci_init);
560
561	static void __exit nand_davinci_exit(void)
562	{
563	platform_driver_unregister(&nand_davinci_driver);
564	}
565	module_exit(nand_davinci_exit);
566
567	MODULE_LICENSE("GPL");
568	MODULE_AUTHOR("Texas Instruments");
569	MODULE_DESCRIPTION("Davinci NAND flash driver");
570