[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mfd / omap-usb-tll.c

/**
 * omap-usb-tll.c - The USB TLL driver for OMAP EHCI & OHCI
 *
 * Copyright (C) 2012-2013 Texas Instruments Incorporated - http://www.ti.com
 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
 * Author: Roger Quadros <rogerq@ti.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2  of
 * the License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/pm_runtime.h>
#include <linux/platform_data/usb-omap.h>
#include <linux/of.h>

#define USBTLL_DRIVER_NAME	"usbhs_tll"

/* TLL Register Set */
#define	OMAP_USBTLL_REVISION				(0x00)
#define	OMAP_USBTLL_SYSCONFIG				(0x10)
#define	OMAP_USBTLL_SYSCONFIG_CACTIVITY			(1 << 8)
#define	OMAP_USBTLL_SYSCONFIG_SIDLEMODE			(1 << 3)
#define	OMAP_USBTLL_SYSCONFIG_ENAWAKEUP			(1 << 2)
#define	OMAP_USBTLL_SYSCONFIG_SOFTRESET			(1 << 1)
#define	OMAP_USBTLL_SYSCONFIG_AUTOIDLE			(1 << 0)

#define	OMAP_USBTLL_SYSSTATUS				(0x14)
#define	OMAP_USBTLL_SYSSTATUS_RESETDONE			(1 << 0)

#define	OMAP_USBTLL_IRQSTATUS				(0x18)
#define	OMAP_USBTLL_IRQENABLE				(0x1C)

#define	OMAP_TLL_SHARED_CONF				(0x30)
#define	OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN		(1 << 6)
#define	OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN		(1 << 5)
#define	OMAP_TLL_SHARED_CONF_USB_DIVRATION		(1 << 2)
#define	OMAP_TLL_SHARED_CONF_FCLK_REQ			(1 << 1)
#define	OMAP_TLL_SHARED_CONF_FCLK_IS_ON			(1 << 0)

#define	OMAP_TLL_CHANNEL_CONF(num)			(0x040 + 0x004 * num)
#define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT		24
#define OMAP_TLL_CHANNEL_CONF_DRVVBUS			(1 << 16)
#define OMAP_TLL_CHANNEL_CONF_CHRGVBUS			(1 << 15)
#define	OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF		(1 << 11)
#define	OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE		(1 << 10)
#define	OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE		(1 << 9)
#define	OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE		(1 << 8)
#define OMAP_TLL_CHANNEL_CONF_MODE_TRANSPARENT_UTMI	(2 << 1)
#define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS		(1 << 1)
#define	OMAP_TLL_CHANNEL_CONF_CHANEN			(1 << 0)

#define OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0		0x0
#define OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM		0x1
#define OMAP_TLL_FSLSMODE_3PIN_PHY			0x2
#define OMAP_TLL_FSLSMODE_4PIN_PHY			0x3
#define OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0		0x4
#define OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM		0x5
#define OMAP_TLL_FSLSMODE_3PIN_TLL			0x6
#define OMAP_TLL_FSLSMODE_4PIN_TLL			0x7
#define OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0		0xA
#define OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM		0xB

#define	OMAP_TLL_ULPI_FUNCTION_CTRL(num)		(0x804 + 0x100 * num)
#define	OMAP_TLL_ULPI_INTERFACE_CTRL(num)		(0x807 + 0x100 * num)
#define	OMAP_TLL_ULPI_OTG_CTRL(num)			(0x80A + 0x100 * num)
#define	OMAP_TLL_ULPI_INT_EN_RISE(num)			(0x80D + 0x100 * num)
#define	OMAP_TLL_ULPI_INT_EN_FALL(num)			(0x810 + 0x100 * num)
#define	OMAP_TLL_ULPI_INT_STATUS(num)			(0x813 + 0x100 * num)
#define	OMAP_TLL_ULPI_INT_LATCH(num)			(0x814 + 0x100 * num)
#define	OMAP_TLL_ULPI_DEBUG(num)			(0x815 + 0x100 * num)
#define	OMAP_TLL_ULPI_SCRATCH_REGISTER(num)		(0x816 + 0x100 * num)

#define OMAP_REV2_TLL_CHANNEL_COUNT			2
#define OMAP_TLL_CHANNEL_COUNT				3
#define OMAP_TLL_CHANNEL_1_EN_MASK			(1 << 0)
#define OMAP_TLL_CHANNEL_2_EN_MASK			(1 << 1)
#define OMAP_TLL_CHANNEL_3_EN_MASK			(1 << 2)

/* Values of USBTLL_REVISION - Note: these are not given in the TRM */
#define OMAP_USBTLL_REV1		0x00000015	/* OMAP3 */
#define OMAP_USBTLL_REV2		0x00000018	/* OMAP 3630 */
#define OMAP_USBTLL_REV3		0x00000004	/* OMAP4 */
#define OMAP_USBTLL_REV4		0x00000006	/* OMAP5 */

#define is_ehci_tll_mode(x)	(x == OMAP_EHCI_PORT_MODE_TLL)

/* only PHY and UNUSED modes don't need TLL */
#define omap_usb_mode_needs_tll(x)	((x) != OMAP_USBHS_PORT_MODE_UNUSED &&\
					 (x) != OMAP_EHCI_PORT_MODE_PHY)

struct usbtll_omap {
	int					nch;	/* num. of channels */
	struct clk				**ch_clk;
	void __iomem				*base;
};

/*-------------------------------------------------------------------------*/

static const char usbtll_driver_name[] = USBTLL_DRIVER_NAME;
static struct device	*tll_dev;
static DEFINE_SPINLOCK(tll_lock);	/* serialize access to tll_dev */

/*-------------------------------------------------------------------------*/

static inline void usbtll_write(void __iomem *base, u32 reg, u32 val)
{
	__raw_writel(val, base + reg);
}

static inline u32 usbtll_read(void __iomem *base, u32 reg)
{
	return __raw_readl(base + reg);
}

static inline void usbtll_writeb(void __iomem *base, u8 reg, u8 val)
{
	__raw_writeb(val, base + reg);
}

static inline u8 usbtll_readb(void __iomem *base, u8 reg)
{
	return __raw_readb(base + reg);
}

/*-------------------------------------------------------------------------*/

static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
{
	switch (pmode) {
	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
	case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
	case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
	case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
	case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
		return true;

	default:
		return false;
	}
}

/*
 * convert the port-mode enum to a value we can use in the FSLSMODE
 * field of USBTLL_CHANNEL_CONF
 */
static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode)
{
	switch (mode) {
	case OMAP_USBHS_PORT_MODE_UNUSED:
	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
		return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;

	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
		return OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM;

	case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
		return OMAP_TLL_FSLSMODE_3PIN_PHY;

	case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
		return OMAP_TLL_FSLSMODE_4PIN_PHY;

	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
		return OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0;

	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
		return OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM;

	case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
		return OMAP_TLL_FSLSMODE_3PIN_TLL;

	case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
		return OMAP_TLL_FSLSMODE_4PIN_TLL;

	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
		return OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0;

	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
		return OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM;
	default:
		pr_warn("Invalid port mode, using default\n");
		return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
	}
}

/**
 * usbtll_omap_probe - initialize TI-based HCDs
 *
 * Allocates basic resources for this USB host controller.
 */
static int usbtll_omap_probe(struct platform_device *pdev)
{
	struct device				*dev =  &pdev->dev;
	struct resource				*res;
	struct usbtll_omap			*tll;
	int					ret = 0;
	int					i, ver;

	dev_dbg(dev, "starting TI HSUSB TLL Controller\n");

	tll = devm_kzalloc(dev, sizeof(struct usbtll_omap), GFP_KERNEL);
	if (!tll) {
		dev_err(dev, "Memory allocation failed\n");
		return -ENOMEM;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	tll->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(tll->base))
		return PTR_ERR(tll->base);

	platform_set_drvdata(pdev, tll);
	pm_runtime_enable(dev);
	pm_runtime_get_sync(dev);

	ver =  usbtll_read(tll->base, OMAP_USBTLL_REVISION);
	switch (ver) {
	case OMAP_USBTLL_REV1:
	case OMAP_USBTLL_REV4:
		tll->nch = OMAP_TLL_CHANNEL_COUNT;
		break;
	case OMAP_USBTLL_REV2:
	case OMAP_USBTLL_REV3:
		tll->nch = OMAP_REV2_TLL_CHANNEL_COUNT;
		break;
	default:
		tll->nch = OMAP_TLL_CHANNEL_COUNT;
		dev_dbg(dev,
		 "USB TLL Rev : 0x%x not recognized, assuming %d channels\n",
			ver, tll->nch);
		break;
	}

	tll->ch_clk = devm_kzalloc(dev, sizeof(struct clk * [tll->nch]),
						GFP_KERNEL);
	if (!tll->ch_clk) {
		ret = -ENOMEM;
		dev_err(dev, "Couldn't allocate memory for channel clocks\n");
		goto err_clk_alloc;
	}

	for (i = 0; i < tll->nch; i++) {
		char clkname[] = "usb_tll_hs_usb_chx_clk";

		snprintf(clkname, sizeof(clkname),
					"usb_tll_hs_usb_ch%d_clk", i);
		tll->ch_clk[i] = clk_get(dev, clkname);

		if (IS_ERR(tll->ch_clk[i]))
			dev_dbg(dev, "can't get clock : %s\n", clkname);
		else
			clk_prepare(tll->ch_clk[i]);
	}

	pm_runtime_put_sync(dev);
	/* only after this can omap_tll_enable/disable work */
	spin_lock(&tll_lock);
	tll_dev = dev;
	spin_unlock(&tll_lock);

	return 0;

err_clk_alloc:
	pm_runtime_put_sync(dev);
	pm_runtime_disable(dev);

	return ret;
}

/**
 * usbtll_omap_remove - shutdown processing for UHH & TLL HCDs
 * @pdev: USB Host Controller being removed
 *
 * Reverses the effect of usbtll_omap_probe().
 */
static int usbtll_omap_remove(struct platform_device *pdev)
{
	struct usbtll_omap *tll = platform_get_drvdata(pdev);
	int i;

	spin_lock(&tll_lock);
	tll_dev = NULL;
	spin_unlock(&tll_lock);

	for (i = 0; i < tll->nch; i++) {
		if (!IS_ERR(tll->ch_clk[i])) {
			clk_unprepare(tll->ch_clk[i]);
			clk_put(tll->ch_clk[i]);
		}
	}

	pm_runtime_disable(&pdev->dev);
	return 0;
}

static const struct of_device_id usbtll_omap_dt_ids[] = {
	{ .compatible = "ti,usbhs-tll" },
	{ }
};

MODULE_DEVICE_TABLE(of, usbtll_omap_dt_ids);

static struct platform_driver usbtll_omap_driver = {
	.driver = {
		.name		= (char *)usbtll_driver_name,
		.owner		= THIS_MODULE,
		.of_match_table = of_match_ptr(usbtll_omap_dt_ids),
	},
	.probe		= usbtll_omap_probe,
	.remove		= usbtll_omap_remove,
};

int omap_tll_init(struct usbhs_omap_platform_data *pdata)
{
	int i;
	bool needs_tll;
	unsigned reg;
	struct usbtll_omap *tll;

	spin_lock(&tll_lock);

	if (!tll_dev) {
		spin_unlock(&tll_lock);
		return -ENODEV;
	}

	tll = dev_get_drvdata(tll_dev);

	needs_tll = false;
	for (i = 0; i < tll->nch; i++)
		needs_tll |= omap_usb_mode_needs_tll(pdata->port_mode[i]);

	pm_runtime_get_sync(tll_dev);

	if (needs_tll) {
		void __iomem *base = tll->base;

		/* Program Common TLL register */
		reg = usbtll_read(base, OMAP_TLL_SHARED_CONF);
		reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
			| OMAP_TLL_SHARED_CONF_USB_DIVRATION);
		reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
		reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN;

		usbtll_write(base, OMAP_TLL_SHARED_CONF, reg);

		/* Enable channels now */
		for (i = 0; i < tll->nch; i++) {
			reg = usbtll_read(base,	OMAP_TLL_CHANNEL_CONF(i));

			if (is_ohci_port(pdata->port_mode[i])) {
				reg |= ohci_omap3_fslsmode(pdata->port_mode[i])
				<< OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT;
				reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS;
			} else if (pdata->port_mode[i] ==
					OMAP_EHCI_PORT_MODE_TLL) {
				/*
				 * Disable AutoIdle, BitStuffing
				 * and use SDR Mode
				 */
				reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
					| OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
				reg |= OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF;
			} else if (pdata->port_mode[i] ==
					OMAP_EHCI_PORT_MODE_HSIC) {
				/*
				 * HSIC Mode requires UTMI port configurations
				 */
				reg |= OMAP_TLL_CHANNEL_CONF_DRVVBUS
				 | OMAP_TLL_CHANNEL_CONF_CHRGVBUS
				 | OMAP_TLL_CHANNEL_CONF_MODE_TRANSPARENT_UTMI
				 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF;
			} else {
				continue;
			}
			reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
			usbtll_write(base, OMAP_TLL_CHANNEL_CONF(i), reg);

			usbtll_writeb(base,
				      OMAP_TLL_ULPI_SCRATCH_REGISTER(i),
				      0xbe);
		}
	}

	pm_runtime_put_sync(tll_dev);

	spin_unlock(&tll_lock);

	return 0;
}
EXPORT_SYMBOL_GPL(omap_tll_init);

int omap_tll_enable(struct usbhs_omap_platform_data *pdata)
{
	int i;
	struct usbtll_omap *tll;

	spin_lock(&tll_lock);

	if (!tll_dev) {
		spin_unlock(&tll_lock);
		return -ENODEV;
	}

	tll = dev_get_drvdata(tll_dev);

	pm_runtime_get_sync(tll_dev);

	for (i = 0; i < tll->nch; i++) {
		if (omap_usb_mode_needs_tll(pdata->port_mode[i])) {
			int r;

			if (IS_ERR(tll->ch_clk[i]))
				continue;

			r = clk_enable(tll->ch_clk[i]);
			if (r) {
				dev_err(tll_dev,
				 "Error enabling ch %d clock: %d\n", i, r);
			}
		}
	}

	spin_unlock(&tll_lock);

	return 0;
}
EXPORT_SYMBOL_GPL(omap_tll_enable);

int omap_tll_disable(struct usbhs_omap_platform_data *pdata)
{
	int i;
	struct usbtll_omap *tll;

	spin_lock(&tll_lock);

	if (!tll_dev) {
		spin_unlock(&tll_lock);
		return -ENODEV;
	}

	tll = dev_get_drvdata(tll_dev);

	for (i = 0; i < tll->nch; i++) {
		if (omap_usb_mode_needs_tll(pdata->port_mode[i])) {
			if (!IS_ERR(tll->ch_clk[i]))
				clk_disable(tll->ch_clk[i]);
		}
	}

	pm_runtime_put_sync(tll_dev);

	spin_unlock(&tll_lock);

	return 0;
}
EXPORT_SYMBOL_GPL(omap_tll_disable);

MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>");
MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("usb tll driver for TI OMAP EHCI and OHCI controllers");

static int __init omap_usbtll_drvinit(void)
{
	return platform_driver_register(&usbtll_omap_driver);
}

/*
 * init before usbhs core driver;
 * The usbtll driver should be initialized before
 * the usbhs core driver probe function is called.
 */
fs_initcall(omap_usbtll_drvinit);

static void __exit omap_usbtll_drvexit(void)
{
	platform_driver_unregister(&usbtll_omap_driver);
}
module_exit(omap_usbtll_drvexit);
Commit	Line	Data
16fa3dc7 KM	1	/**
	2	* omap-usb-tll.c - The USB TLL driver for OMAP EHCI & OHCI
	3	*
9f4a3ece	4	* Copyright (C) 2012-2013 Texas Instruments Incorporated - http://www.ti.com
16fa3dc7	5	* Author: Keshava Munegowda <keshava_mgowda@ti.com>
9f4a3ece	6	* Author: Roger Quadros <rogerq@ti.com>
16fa3dc7 KM	7	*
	8	* This program is free software: you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 of
	10	* the License as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/types.h>
	23	#include <linux/slab.h>
	24	#include <linux/spinlock.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/clk.h>
	27	#include <linux/io.h>
	28	#include <linux/err.h>
16fa3dc7	29	#include <linux/pm_runtime.h>
e8c4a7ac	30	#include <linux/platform_data/usb-omap.h>
48130b8f	31	#include <linux/of.h>
16fa3dc7 KM	32
	33	#define USBTLL_DRIVER_NAME "usbhs_tll"
	34
	35	/* TLL Register Set */
	36	#define OMAP_USBTLL_REVISION (0x00)
	37	#define OMAP_USBTLL_SYSCONFIG (0x10)
	38	#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
	39	#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
	40	#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
	41	#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
	42	#define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0)
	43
	44	#define OMAP_USBTLL_SYSSTATUS (0x14)
	45	#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0)
	46
	47	#define OMAP_USBTLL_IRQSTATUS (0x18)
	48	#define OMAP_USBTLL_IRQENABLE (0x1C)
	49
	50	#define OMAP_TLL_SHARED_CONF (0x30)
	51	#define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6)
	52	#define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5)
	53	#define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2)
	54	#define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1)
	55	#define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0)
	56
	57	#define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num)
	58	#define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24
300c2f8f RQ	59	#define OMAP_TLL_CHANNEL_CONF_DRVVBUS (1 << 16)
300c2f8f RQ	60	#define OMAP_TLL_CHANNEL_CONF_CHRGVBUS (1 << 15)
16fa3dc7 KM	61	#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11)
	62	#define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10)
	63	#define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9)
	64	#define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8)
300c2f8f	65	#define OMAP_TLL_CHANNEL_CONF_MODE_TRANSPARENT_UTMI (2 << 1)
16fa3dc7 KM	66	#define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS (1 << 1)
	67	#define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0)
	68
	69	#define OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0 0x0
	70	#define OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM 0x1
	71	#define OMAP_TLL_FSLSMODE_3PIN_PHY 0x2
	72	#define OMAP_TLL_FSLSMODE_4PIN_PHY 0x3
	73	#define OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0 0x4
	74	#define OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM 0x5
	75	#define OMAP_TLL_FSLSMODE_3PIN_TLL 0x6
	76	#define OMAP_TLL_FSLSMODE_4PIN_TLL 0x7
	77	#define OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0 0xA
	78	#define OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM 0xB
	79
	80	#define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num)
	81	#define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num)
	82	#define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num)
	83	#define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num)
	84	#define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num)
	85	#define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num)
	86	#define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num)
	87	#define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num)
	88	#define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num)
	89
	90	#define OMAP_REV2_TLL_CHANNEL_COUNT 2
	91	#define OMAP_TLL_CHANNEL_COUNT 3
	92	#define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 0)
	93	#define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 1)
	94	#define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 2)
	95
	96	/* Values of USBTLL_REVISION - Note: these are not given in the TRM */
	97	#define OMAP_USBTLL_REV1 0x00000015 /* OMAP3 */
	98	#define OMAP_USBTLL_REV2 0x00000018 /* OMAP 3630 */
	99	#define OMAP_USBTLL_REV3 0x00000004 /* OMAP4 */
300c2f8f	100	#define OMAP_USBTLL_REV4 0x00000006 /* OMAP5 */
16fa3dc7 KM	101
	102	#define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
	103
32a51f2a RQ	104	/* only PHY and UNUSED modes don't need TLL */
	105	#define omap_usb_mode_needs_tll(x) ((x) != OMAP_USBHS_PORT_MODE_UNUSED &&\
	106	(x) != OMAP_EHCI_PORT_MODE_PHY)
	107
16fa3dc7	108	struct usbtll_omap {
7e0ff103	109	int nch; /* num. of channels */
0bde3e9f	110	struct clk **ch_clk;
9f4a3ece	111	void __iomem *base;
16fa3dc7 KM	112	};
	113
	114	/-------------------------------------------------------------------------/
	115
7ed86191 RQ	116	static const char usbtll_driver_name[] = USBTLL_DRIVER_NAME;
7ed86191 RQ	117	static struct device *tll_dev;
66751446	118	static DEFINE_SPINLOCK(tll_lock); /* serialize access to tll_dev */
16fa3dc7 KM	119
	120	/-------------------------------------------------------------------------/
	121
	122	static inline void usbtll_write(void __iomem *base, u32 reg, u32 val)
	123	{
	124	__raw_writel(val, base + reg);
	125	}
	126
	127	static inline u32 usbtll_read(void __iomem *base, u32 reg)
	128	{
	129	return __raw_readl(base + reg);
	130	}
	131
	132	static inline void usbtll_writeb(void __iomem *base, u8 reg, u8 val)
	133	{
	134	__raw_writeb(val, base + reg);
	135	}
	136
	137	static inline u8 usbtll_readb(void __iomem *base, u8 reg)
	138	{
	139	return __raw_readb(base + reg);
	140	}
	141
	142	/-------------------------------------------------------------------------/
	143
	144	static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
	145	{
	146	switch (pmode) {
	147	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
	148	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
	149	case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
	150	case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
	151	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
	152	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
	153	case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
	154	case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
	155	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
	156	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
	157	return true;
	158
	159	default:
	160	return false;
	161	}
	162	}
	163
	164	/*
	165	* convert the port-mode enum to a value we can use in the FSLSMODE
	166	* field of USBTLL_CHANNEL_CONF
	167	*/
	168	static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode)
	169	{
	170	switch (mode) {
	171	case OMAP_USBHS_PORT_MODE_UNUSED:
	172	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
	173	return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
	174
	175	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
	176	return OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM;
	177
	178	case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
	179	return OMAP_TLL_FSLSMODE_3PIN_PHY;
	180
	181	case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
	182	return OMAP_TLL_FSLSMODE_4PIN_PHY;
183
184	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
185	return OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0;
186
187	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
188	return OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM;
189
190	case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
191	return OMAP_TLL_FSLSMODE_3PIN_TLL;
192
193	case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
194	return OMAP_TLL_FSLSMODE_4PIN_TLL;
195
196	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
197	return OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0;
198
199	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
200	return OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM;
201	default:
202	pr_warn("Invalid port mode, using default\n");
203	return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
204	}
205	}
206
207	/**
208	* usbtll_omap_probe - initialize TI-based HCDs
209	*
210	* Allocates basic resources for this USB host controller.
211	*/
f791be49	212	static int usbtll_omap_probe(struct platform_device *pdev)
16fa3dc7 KM	213	{
16fa3dc7 KM	214	struct device *dev = &pdev->dev;
16fa3dc7 KM	215	struct resource *res;
16fa3dc7 KM	216	struct usbtll_omap *tll;
16fa3dc7	217	int ret = 0;
7e0ff103	218	int i, ver;
16fa3dc7 KM	219
	220	dev_dbg(dev, "starting TI HSUSB TLL Controller\n");
	221
1a7a8d70	222	tll = devm_kzalloc(dev, sizeof(struct usbtll_omap), GFP_KERNEL);
16fa3dc7 KM	223	if (!tll) {
16fa3dc7 KM	224	dev_err(dev, "Memory allocation failed\n");
1a7a8d70	225	return -ENOMEM;
16fa3dc7 KM	226	}
16fa3dc7 KM	227
16fa3dc7	228	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
651da3d4 SK	229	tll->base = devm_ioremap_resource(dev, res);
	230	if (IS_ERR(tll->base))
	231	return PTR_ERR(tll->base);
16fa3dc7 KM	232
	233	platform_set_drvdata(pdev, tll);
	234	pm_runtime_enable(dev);
	235	pm_runtime_get_sync(dev);
	236
9f4a3ece	237	ver = usbtll_read(tll->base, OMAP_USBTLL_REVISION);
16fa3dc7 KM	238	switch (ver) {
16fa3dc7 KM	239	case OMAP_USBTLL_REV1:
300c2f8f	240	case OMAP_USBTLL_REV4:
7e0ff103	241	tll->nch = OMAP_TLL_CHANNEL_COUNT;
16fa3dc7	242	break;
7e0ff103	243	case OMAP_USBTLL_REV2:
16fa3dc7	244	case OMAP_USBTLL_REV3:
7e0ff103	245	tll->nch = OMAP_REV2_TLL_CHANNEL_COUNT;
16fa3dc7 KM	246	break;
16fa3dc7 KM	247	default:
7e0ff103 RQ	248	tll->nch = OMAP_TLL_CHANNEL_COUNT;
	249	dev_dbg(dev,
	250	"USB TLL Rev : 0x%x not recognized, assuming %d channels\n",
	251	ver, tll->nch);
	252	break;
16fa3dc7 KM	253	}
16fa3dc7 KM	254
0bde3e9f RQ	255	tll->ch_clk = devm_kzalloc(dev, sizeof(struct clk * [tll->nch]),
	256	GFP_KERNEL);
	257	if (!tll->ch_clk) {
	258	ret = -ENOMEM;
	259	dev_err(dev, "Couldn't allocate memory for channel clocks\n");
	260	goto err_clk_alloc;
	261	}
	262
	263	for (i = 0; i < tll->nch; i++) {
	264	char clkname[] = "usb_tll_hs_usb_chx_clk";
	265
	266	snprintf(clkname, sizeof(clkname),
	267	"usb_tll_hs_usb_ch%d_clk", i);
	268	tll->ch_clk[i] = clk_get(dev, clkname);
	269
	270	if (IS_ERR(tll->ch_clk[i]))
	271	dev_dbg(dev, "can't get clock : %s\n", clkname);
0cf26616 RQ	272	else
0cf26616 RQ	273	clk_prepare(tll->ch_clk[i]);
0bde3e9f RQ	274	}
0bde3e9f RQ	275
9f4a3ece RQ	276	pm_runtime_put_sync(dev);
	277	/* only after this can omap_tll_enable/disable work */
	278	spin_lock(&tll_lock);
	279	tll_dev = dev;
	280	spin_unlock(&tll_lock);
	281
	282	return 0;
	283
	284	err_clk_alloc:
	285	pm_runtime_put_sync(dev);
	286	pm_runtime_disable(dev);
	287
	288	return ret;
	289	}
	290
	291	/**
	292	* usbtll_omap_remove - shutdown processing for UHH & TLL HCDs
	293	* @pdev: USB Host Controller being removed
	294	*
	295	* Reverses the effect of usbtll_omap_probe().
	296	*/
	297	static int usbtll_omap_remove(struct platform_device *pdev)
	298	{
	299	struct usbtll_omap *tll = platform_get_drvdata(pdev);
	300	int i;
	301
	302	spin_lock(&tll_lock);
	303	tll_dev = NULL;
	304	spin_unlock(&tll_lock);
	305
0cf26616 RQ	306	for (i = 0; i < tll->nch; i++) {
	307	if (!IS_ERR(tll->ch_clk[i])) {
	308	clk_unprepare(tll->ch_clk[i]);
9f4a3ece	309	clk_put(tll->ch_clk[i]);
0cf26616 RQ	310	}
0cf26616 RQ	311	}
9f4a3ece RQ	312
	313	pm_runtime_disable(&pdev->dev);
	314	return 0;
	315	}
	316
48130b8f RQ	317	static const struct of_device_id usbtll_omap_dt_ids[] = {
	318	{ .compatible = "ti,usbhs-tll" },
	319	{ }
	320	};
	321
	322	MODULE_DEVICE_TABLE(of, usbtll_omap_dt_ids);
	323
9f4a3ece RQ	324	static struct platform_driver usbtll_omap_driver = {
	325	.driver = {
	326	.name = (char *)usbtll_driver_name,
	327	.owner = THIS_MODULE,
48130b8f	328	.of_match_table = of_match_ptr(usbtll_omap_dt_ids),
9f4a3ece RQ	329	},
	330	.probe = usbtll_omap_probe,
	331	.remove = usbtll_omap_remove,
	332	};
	333
	334	int omap_tll_init(struct usbhs_omap_platform_data *pdata)
	335	{
	336	int i;
	337	bool needs_tll;
	338	unsigned reg;
	339	struct usbtll_omap *tll;
	340
	341	spin_lock(&tll_lock);
	342
	343	if (!tll_dev) {
	344	spin_unlock(&tll_lock);
	345	return -ENODEV;
	346	}
	347
	348	tll = dev_get_drvdata(tll_dev);
	349
32a51f2a RQ	350	needs_tll = false;
	351	for (i = 0; i < tll->nch; i++)
	352	needs_tll \|= omap_usb_mode_needs_tll(pdata->port_mode[i]);
	353
9f4a3ece RQ	354	pm_runtime_get_sync(tll_dev);
9f4a3ece RQ	355
32a51f2a	356	if (needs_tll) {
9f4a3ece	357	void __iomem *base = tll->base;
16fa3dc7 KM	358
	359	/* Program Common TLL register */
	360	reg = usbtll_read(base, OMAP_TLL_SHARED_CONF);
	361	reg \|= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
	362	\| OMAP_TLL_SHARED_CONF_USB_DIVRATION);
	363	reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
	364	reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN;
	365
	366	usbtll_write(base, OMAP_TLL_SHARED_CONF, reg);
	367
	368	/* Enable channels now */
7e0ff103	369	for (i = 0; i < tll->nch; i++) {
16fa3dc7 KM	370	reg = usbtll_read(base, OMAP_TLL_CHANNEL_CONF(i));
	371
	372	if (is_ohci_port(pdata->port_mode[i])) {
	373	reg \|= ohci_omap3_fslsmode(pdata->port_mode[i])
	374	<< OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT;
	375	reg \|= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS;
	376	} else if (pdata->port_mode[i] ==
	377	OMAP_EHCI_PORT_MODE_TLL) {
	378	/*
	379	* Disable AutoIdle, BitStuffing
	380	* and use SDR Mode
	381	*/
	382	reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
16fa3dc7	383	\| OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
1e7ae919	384	reg \|= OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF;
300c2f8f RQ	385	} else if (pdata->port_mode[i] ==
	386	OMAP_EHCI_PORT_MODE_HSIC) {
	387	/*
	388	* HSIC Mode requires UTMI port configurations
	389	*/
	390	reg \|= OMAP_TLL_CHANNEL_CONF_DRVVBUS
	391	\| OMAP_TLL_CHANNEL_CONF_CHRGVBUS
	392	\| OMAP_TLL_CHANNEL_CONF_MODE_TRANSPARENT_UTMI
	393	\| OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF;
16fa3dc7 KM	394	} else {
	395	continue;
	396	}
	397	reg \|= OMAP_TLL_CHANNEL_CONF_CHANEN;
	398	usbtll_write(base, OMAP_TLL_CHANNEL_CONF(i), reg);
	399
	400	usbtll_writeb(base,
	401	OMAP_TLL_ULPI_SCRATCH_REGISTER(i),
	402	0xbe);
	403	}
	404	}
	405
9f4a3ece RQ	406	pm_runtime_put_sync(tll_dev);
9f4a3ece RQ	407
66751446	408	spin_unlock(&tll_lock);
16fa3dc7	409
1a7a8d70	410	return 0;
16fa3dc7	411	}
9f4a3ece	412	EXPORT_SYMBOL_GPL(omap_tll_init);
16fa3dc7	413
9f4a3ece	414	int omap_tll_enable(struct usbhs_omap_platform_data *pdata)
16fa3dc7	415	{
0bde3e9f	416	int i;
9f4a3ece	417	struct usbtll_omap *tll;
0bde3e9f	418
66751446	419	spin_lock(&tll_lock);
16fa3dc7	420
9f4a3ece RQ	421	if (!tll_dev) {
	422	spin_unlock(&tll_lock);
	423	return -ENODEV;
	424	}
16fa3dc7	425
9f4a3ece	426	tll = dev_get_drvdata(tll_dev);
16fa3dc7	427
9f4a3ece	428	pm_runtime_get_sync(tll_dev);
16fa3dc7	429
0bde3e9f	430	for (i = 0; i < tll->nch; i++) {
32a51f2a	431	if (omap_usb_mode_needs_tll(pdata->port_mode[i])) {
0bde3e9f	432	int r;
16fa3dc7	433
0bde3e9f RQ	434	if (IS_ERR(tll->ch_clk[i]))
	435	continue;
	436
	437	r = clk_enable(tll->ch_clk[i]);
	438	if (r) {
9f4a3ece	439	dev_err(tll_dev,
0bde3e9f RQ	440	"Error enabling ch %d clock: %d\n", i, r);
	441	}
	442	}
	443	}
16fa3dc7	444
9f4a3ece RQ	445	spin_unlock(&tll_lock);
9f4a3ece RQ	446
16fa3dc7 KM	447	return 0;
16fa3dc7 KM	448	}
9f4a3ece	449	EXPORT_SYMBOL_GPL(omap_tll_enable);
16fa3dc7	450
9f4a3ece	451	int omap_tll_disable(struct usbhs_omap_platform_data *pdata)
16fa3dc7	452	{
0bde3e9f	453	int i;
9f4a3ece RQ	454	struct usbtll_omap *tll;
	455
	456	spin_lock(&tll_lock);
	457
	458	if (!tll_dev) {
	459	spin_unlock(&tll_lock);
	460	return -ENODEV;
	461	}
16fa3dc7	462
9f4a3ece	463	tll = dev_get_drvdata(tll_dev);
16fa3dc7	464
0bde3e9f	465	for (i = 0; i < tll->nch; i++) {
32a51f2a	466	if (omap_usb_mode_needs_tll(pdata->port_mode[i])) {
0bde3e9f RQ	467	if (!IS_ERR(tll->ch_clk[i]))
	468	clk_disable(tll->ch_clk[i]);
	469	}
	470	}
16fa3dc7	471
9f4a3ece	472	pm_runtime_put_sync(tll_dev);
66751446 RQ	473
	474	spin_unlock(&tll_lock);
	475
9f4a3ece	476	return 0;
16fa3dc7 KM	477	}
	478	EXPORT_SYMBOL_GPL(omap_tll_disable);
	479
	480	MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
48130b8f	481	MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>");
16fa3dc7 KM	482	MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
	483	MODULE_LICENSE("GPL v2");
	484	MODULE_DESCRIPTION("usb tll driver for TI OMAP EHCI and OHCI controllers");
	485
	486	static int __init omap_usbtll_drvinit(void)
	487	{
	488	return platform_driver_register(&usbtll_omap_driver);
	489	}
	490
	491	/*
	492	* init before usbhs core driver;
	493	* The usbtll driver should be initialized before
	494	* the usbhs core driver probe function is called.
	495	*/
	496	fs_initcall(omap_usbtll_drvinit);
	497
	498	static void __exit omap_usbtll_drvexit(void)
	499	{
	500	platform_driver_unregister(&usbtll_omap_driver);
	501	}
	502	module_exit(omap_usbtll_drvexit);