[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / irqchip / exynos-combiner.c

/*
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Combiner irqchip for EXYNOS
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/err.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <asm/mach/irq.h>

#ifdef CONFIG_EXYNOS_ATAGS
#include <plat/cpu.h>
#endif

#include "irqchip.h"

#define COMBINER_ENABLE_SET	0x0
#define COMBINER_ENABLE_CLEAR	0x4
#define COMBINER_INT_STATUS	0xC

#define IRQ_IN_COMBINER		8

static DEFINE_SPINLOCK(irq_controller_lock);

struct combiner_chip_data {
	unsigned int hwirq_offset;
	unsigned int irq_mask;
	void __iomem *base;
	unsigned int parent_irq;
};

static struct irq_domain *combiner_irq_domain;

static inline void __iomem *combiner_base(struct irq_data *data)
{
	struct combiner_chip_data *combiner_data =
		irq_data_get_irq_chip_data(data);

	return combiner_data->base;
}

static void combiner_mask_irq(struct irq_data *data)
{
	u32 mask = 1 << (data->hwirq % 32);

	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
}

static void combiner_unmask_irq(struct irq_data *data)
{
	u32 mask = 1 << (data->hwirq % 32);

	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
}

static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{
	struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
	struct irq_chip *chip = irq_get_chip(irq);
	unsigned int cascade_irq, combiner_irq;
	unsigned long status;

	chained_irq_enter(chip, desc);

	spin_lock(&irq_controller_lock);
	status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
	spin_unlock(&irq_controller_lock);
	status &= chip_data->irq_mask;

	if (status == 0)
		goto out;

	combiner_irq = chip_data->hwirq_offset + __ffs(status);
	cascade_irq = irq_find_mapping(combiner_irq_domain, combiner_irq);

	if (unlikely(!cascade_irq))
		do_bad_IRQ(irq, desc);
	else
		generic_handle_irq(cascade_irq);

 out:
	chained_irq_exit(chip, desc);
}

#ifdef CONFIG_SMP
static int combiner_set_affinity(struct irq_data *d,
				 const struct cpumask *mask_val, bool force)
{
	struct combiner_chip_data *chip_data = irq_data_get_irq_chip_data(d);
	struct irq_chip *chip = irq_get_chip(chip_data->parent_irq);
	struct irq_data *data = irq_get_irq_data(chip_data->parent_irq);

	if (chip && chip->irq_set_affinity)
		return chip->irq_set_affinity(data, mask_val, force);
	else
		return -EINVAL;
}
#endif

static struct irq_chip combiner_chip = {
	.name			= "COMBINER",
	.irq_mask		= combiner_mask_irq,
	.irq_unmask		= combiner_unmask_irq,
#ifdef CONFIG_SMP
	.irq_set_affinity	= combiner_set_affinity,
#endif
};

static void __init combiner_cascade_irq(struct combiner_chip_data *combiner_data,
					unsigned int irq)
{
	if (irq_set_handler_data(irq, combiner_data) != 0)
		BUG();
	irq_set_chained_handler(irq, combiner_handle_cascade_irq);
}

static void __init combiner_init_one(struct combiner_chip_data *combiner_data,
				     unsigned int combiner_nr,
				     void __iomem *base, unsigned int irq)
{
	combiner_data->base = base;
	combiner_data->hwirq_offset = (combiner_nr & ~3) * IRQ_IN_COMBINER;
	combiner_data->irq_mask = 0xff << ((combiner_nr % 4) << 3);
	combiner_data->parent_irq = irq;

	/* Disable all interrupts */
	__raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
}

#ifdef CONFIG_OF
static int combiner_irq_domain_xlate(struct irq_domain *d,
				     struct device_node *controller,
				     const u32 *intspec, unsigned int intsize,
				     unsigned long *out_hwirq,
				     unsigned int *out_type)
{
	if (d->of_node != controller)
		return -EINVAL;

	if (intsize < 2)
		return -EINVAL;

	*out_hwirq = intspec[0] * IRQ_IN_COMBINER + intspec[1];
	*out_type = 0;

	return 0;
}
#else
static int combiner_irq_domain_xlate(struct irq_domain *d,
				     struct device_node *controller,
				     const u32 *intspec, unsigned int intsize,
				     unsigned long *out_hwirq,
				     unsigned int *out_type)
{
	return -EINVAL;
}
#endif

static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
				   irq_hw_number_t hw)
{
	struct combiner_chip_data *combiner_data = d->host_data;

	irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
	irq_set_chip_data(irq, &combiner_data[hw >> 3]);
	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);

	return 0;
}

static struct irq_domain_ops combiner_irq_domain_ops = {
	.xlate	= combiner_irq_domain_xlate,
	.map	= combiner_irq_domain_map,
};

static unsigned int combiner_lookup_irq(int group)
{
#ifdef CONFIG_EXYNOS_ATAGS
	if (group < EXYNOS4210_MAX_COMBINER_NR || soc_is_exynos5250())
		return IRQ_SPI(group);

	switch (group) {
	case 16:
		return IRQ_SPI(107);
	case 17:
		return IRQ_SPI(108);
	case 18:
		return IRQ_SPI(48);
	case 19:
		return IRQ_SPI(42);
	}
#endif
	return 0;
}

void __init combiner_init(void __iomem *combiner_base,
			  struct device_node *np,
			  unsigned int max_nr,
			  int irq_base)
{
	int i, irq;
	unsigned int nr_irq;
	struct combiner_chip_data *combiner_data;

	nr_irq = max_nr * IRQ_IN_COMBINER;

	combiner_data = kcalloc(max_nr, sizeof (*combiner_data), GFP_KERNEL);
	if (!combiner_data) {
		pr_warning("%s: could not allocate combiner data\n", __func__);
		return;
	}

	combiner_irq_domain = irq_domain_add_simple(np, nr_irq, irq_base,
				&combiner_irq_domain_ops, combiner_data);
	if (WARN_ON(!combiner_irq_domain)) {
		pr_warning("%s: irq domain init failed\n", __func__);
		return;
	}

	for (i = 0; i < max_nr; i++) {
#ifdef CONFIG_OF
		if (np)
			irq = irq_of_parse_and_map(np, i);
		else
#endif
			irq = combiner_lookup_irq(i);

		combiner_init_one(&combiner_data[i], i,
				  combiner_base + (i >> 2) * 0x10, irq);
		combiner_cascade_irq(&combiner_data[i], irq);
	}
}

#ifdef CONFIG_OF
static int __init combiner_of_init(struct device_node *np,
				   struct device_node *parent)
{
	void __iomem *combiner_base;
	unsigned int max_nr = 20;
	int irq_base = -1;

	combiner_base = of_iomap(np, 0);
	if (!combiner_base) {
		pr_err("%s: failed to map combiner registers\n", __func__);
		return -ENXIO;
	}

	if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
		pr_info("%s: number of combiners not specified, "
			"setting default as %d.\n",
			__func__, max_nr);
	}

	/* 
	 * FIXME: This is a hardwired COMBINER_IRQ(0,0). Once all devices
	 * get their IRQ from DT, remove this in order to get dynamic
	 * allocation.
	 */
	irq_base = 160;

	combiner_init(combiner_base, np, max_nr, irq_base);

	return 0;
}
IRQCHIP_DECLARE(exynos4210_combiner, "samsung,exynos4210-combiner",
		combiner_of_init);
#endif
Commit	Line	Data
a900e5d9 RH	1	/*
	2	* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com
	4	*
	5	* Combiner irqchip for EXYNOS
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#include <linux/err.h>
	12	#include <linux/export.h>
	13	#include <linux/init.h>
	14	#include <linux/io.h>
d34f03d4	15	#include <linux/slab.h>
a900e5d9	16	#include <linux/irqdomain.h>
de88cbb7	17	#include <linux/irqchip/chained_irq.h>
a900e5d9 RH	18	#include <linux/of_address.h>
	19	#include <linux/of_irq.h>
	20	#include <asm/mach/irq.h>
	21
92c8e496	22	#ifdef CONFIG_EXYNOS_ATAGS
a900e5d9	23	#include <plat/cpu.h>
92c8e496	24	#endif
a900e5d9 RH	25
	26	#include "irqchip.h"
	27
	28	#define COMBINER_ENABLE_SET 0x0
	29	#define COMBINER_ENABLE_CLEAR 0x4
	30	#define COMBINER_INT_STATUS 0xC
	31
6761dcfe AB	32	#define IRQ_IN_COMBINER 8
6761dcfe AB	33
a900e5d9 RH	34	static DEFINE_SPINLOCK(irq_controller_lock);
	35
	36	struct combiner_chip_data {
20adee8f	37	unsigned int hwirq_offset;
a900e5d9 RH	38	unsigned int irq_mask;
a900e5d9 RH	39	void __iomem *base;
df7ef462	40	unsigned int parent_irq;
a900e5d9 RH	41	};
	42
	43	static struct irq_domain *combiner_irq_domain;
a900e5d9 RH	44
	45	static inline void __iomem combiner_base(struct irq_data data)
	46	{
	47	struct combiner_chip_data *combiner_data =
	48	irq_data_get_irq_chip_data(data);
	49
	50	return combiner_data->base;
	51	}
	52
	53	static void combiner_mask_irq(struct irq_data *data)
	54	{
	55	u32 mask = 1 << (data->hwirq % 32);
	56
	57	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
	58	}
	59
	60	static void combiner_unmask_irq(struct irq_data *data)
	61	{
	62	u32 mask = 1 << (data->hwirq % 32);
	63
	64	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
	65	}
	66
	67	static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
	68	{
	69	struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
	70	struct irq_chip *chip = irq_get_chip(irq);
	71	unsigned int cascade_irq, combiner_irq;
	72	unsigned long status;
	73
	74	chained_irq_enter(chip, desc);
	75
	76	spin_lock(&irq_controller_lock);
	77	status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
	78	spin_unlock(&irq_controller_lock);
	79	status &= chip_data->irq_mask;
	80
	81	if (status == 0)
	82	goto out;
	83
20adee8f AB	84	combiner_irq = chip_data->hwirq_offset + __ffs(status);
20adee8f AB	85	cascade_irq = irq_find_mapping(combiner_irq_domain, combiner_irq);
a900e5d9	86
20adee8f AB	87	if (unlikely(!cascade_irq))
20adee8f AB	88	do_bad_IRQ(irq, desc);
a900e5d9 RH	89	else
	90	generic_handle_irq(cascade_irq);
	91
	92	out:
	93	chained_irq_exit(chip, desc);
	94	}
	95
df7ef462 CP	96	#ifdef CONFIG_SMP
	97	static int combiner_set_affinity(struct irq_data *d,
	98	const struct cpumask *mask_val, bool force)
	99	{
	100	struct combiner_chip_data *chip_data = irq_data_get_irq_chip_data(d);
	101	struct irq_chip *chip = irq_get_chip(chip_data->parent_irq);
	102	struct irq_data *data = irq_get_irq_data(chip_data->parent_irq);
	103
	104	if (chip && chip->irq_set_affinity)
	105	return chip->irq_set_affinity(data, mask_val, force);
	106	else
	107	return -EINVAL;
	108	}
	109	#endif
	110
a900e5d9	111	static struct irq_chip combiner_chip = {
df7ef462 CP	112	.name = "COMBINER",
	113	.irq_mask = combiner_mask_irq,
	114	.irq_unmask = combiner_unmask_irq,
	115	#ifdef CONFIG_SMP
	116	.irq_set_affinity = combiner_set_affinity,
	117	#endif
a900e5d9 RH	118	};
a900e5d9 RH	119
d34f03d4	120	static void __init combiner_cascade_irq(struct combiner_chip_data *combiner_data,
4e164dc5 CP	121	unsigned int irq)
4e164dc5 CP	122	{
d34f03d4	123	if (irq_set_handler_data(irq, combiner_data) != 0)
a900e5d9 RH	124	BUG();
	125	irq_set_chained_handler(irq, combiner_handle_cascade_irq);
	126	}
	127
d34f03d4 AB	128	static void __init combiner_init_one(struct combiner_chip_data *combiner_data,
d34f03d4 AB	129	unsigned int combiner_nr,
df7ef462	130	void __iomem *base, unsigned int irq)
a900e5d9	131	{
d34f03d4	132	combiner_data->base = base;
20adee8f	133	combiner_data->hwirq_offset = (combiner_nr & ~3) * IRQ_IN_COMBINER;
d34f03d4 AB	134	combiner_data->irq_mask = 0xff << ((combiner_nr % 4) << 3);
d34f03d4 AB	135	combiner_data->parent_irq = irq;
a900e5d9 RH	136
a900e5d9 RH	137	/* Disable all interrupts */
d34f03d4	138	__raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
a900e5d9 RH	139	}
	140
	141	#ifdef CONFIG_OF
	142	static int combiner_irq_domain_xlate(struct irq_domain *d,
	143	struct device_node *controller,
	144	const u32 *intspec, unsigned int intsize,
	145	unsigned long *out_hwirq,
	146	unsigned int *out_type)
	147	{
	148	if (d->of_node != controller)
	149	return -EINVAL;
	150
	151	if (intsize < 2)
	152	return -EINVAL;
	153
6761dcfe	154	out_hwirq = intspec[0] IRQ_IN_COMBINER + intspec[1];
a900e5d9 RH	155	*out_type = 0;
	156
	157	return 0;
	158	}
	159	#else
	160	static int combiner_irq_domain_xlate(struct irq_domain *d,
	161	struct device_node *controller,
	162	const u32 *intspec, unsigned int intsize,
	163	unsigned long *out_hwirq,
	164	unsigned int *out_type)
	165	{
	166	return -EINVAL;
	167	}
	168	#endif
	169
	170	static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
	171	irq_hw_number_t hw)
	172	{
d34f03d4 AB	173	struct combiner_chip_data *combiner_data = d->host_data;
d34f03d4 AB	174
a900e5d9 RH	175	irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
	176	irq_set_chip_data(irq, &combiner_data[hw >> 3]);
	177	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	178
	179	return 0;
	180	}
	181
	182	static struct irq_domain_ops combiner_irq_domain_ops = {
	183	.xlate = combiner_irq_domain_xlate,
	184	.map = combiner_irq_domain_map,
	185	};
	186
92c8e496	187	static unsigned int combiner_lookup_irq(int group)
4e164dc5	188	{
92c8e496 AB	189	#ifdef CONFIG_EXYNOS_ATAGS
	190	if (group < EXYNOS4210_MAX_COMBINER_NR \|\| soc_is_exynos5250())
	191	return IRQ_SPI(group);
	192
4e164dc5 CP	193	switch (group) {
	194	case 16:
	195	return IRQ_SPI(107);
	196	case 17:
	197	return IRQ_SPI(108);
	198	case 18:
	199	return IRQ_SPI(48);
	200	case 19:
	201	return IRQ_SPI(42);
4e164dc5	202	}
92c8e496 AB	203	#endif
92c8e496 AB	204	return 0;
4e164dc5 CP	205	}
4e164dc5 CP	206
a900e5d9	207	void __init combiner_init(void __iomem *combiner_base,
6761dcfe	208	struct device_node *np,
863a08dc AB	209	unsigned int max_nr,
863a08dc AB	210	int irq_base)
a900e5d9	211	{
863a08dc	212	int i, irq;
6761dcfe	213	unsigned int nr_irq;
d34f03d4	214	struct combiner_chip_data *combiner_data;
a900e5d9	215
6761dcfe	216	nr_irq = max_nr * IRQ_IN_COMBINER;
4e164dc5	217
d34f03d4 AB	218	combiner_data = kcalloc(max_nr, sizeof (*combiner_data), GFP_KERNEL);
	219	if (!combiner_data) {
	220	pr_warning("%s: could not allocate combiner data\n", __func__);
	221	return;
a900e5d9 RH	222	}
a900e5d9 RH	223
863a08dc	224	combiner_irq_domain = irq_domain_add_simple(np, nr_irq, irq_base,
d34f03d4	225	&combiner_irq_domain_ops, combiner_data);
a900e5d9 RH	226	if (WARN_ON(!combiner_irq_domain)) {
	227	pr_warning("%s: irq domain init failed\n", __func__);
	228	return;
	229	}
	230
	231	for (i = 0; i < max_nr; i++) {
a900e5d9 RH	232	#ifdef CONFIG_OF
	233	if (np)
	234	irq = irq_of_parse_and_map(np, i);
92c8e496	235	else
a900e5d9	236	#endif
92c8e496 AB	237	irq = combiner_lookup_irq(i);
92c8e496 AB	238
d34f03d4 AB	239	combiner_init_one(&combiner_data[i], i,
	240	combiner_base + (i >> 2) * 0x10, irq);
	241	combiner_cascade_irq(&combiner_data[i], irq);
a900e5d9 RH	242	}
	243	}
	244
	245	#ifdef CONFIG_OF
	246	static int __init combiner_of_init(struct device_node *np,
	247	struct device_node *parent)
	248	{
	249	void __iomem *combiner_base;
6761dcfe	250	unsigned int max_nr = 20;
863a08dc	251	int irq_base = -1;
a900e5d9 RH	252
	253	combiner_base = of_iomap(np, 0);
	254	if (!combiner_base) {
	255	pr_err("%s: failed to map combiner registers\n", __func__);
	256	return -ENXIO;
	257	}
	258
6761dcfe AB	259	if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
	260	pr_info("%s: number of combiners not specified, "
	261	"setting default as %d.\n",
	262	__func__, max_nr);
	263	}
	264
863a08dc AB	265	/*
	266	* FIXME: This is a hardwired COMBINER_IRQ(0,0). Once all devices
	267	* get their IRQ from DT, remove this in order to get dynamic
	268	* allocation.
	269	*/
	270	irq_base = 160;
	271
	272	combiner_init(combiner_base, np, max_nr, irq_base);
a900e5d9 RH	273
	274	return 0;
	275	}
	276	IRQCHIP_DECLARE(exynos4210_combiner, "samsung,exynos4210-combiner",
	277	combiner_of_init);
	278	#endif