[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / serverworks.c

/*
 * Copyright (C) 1998-2000 Michel Aubry
 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
 * Portions copyright (c) 2001 Sun Microsystems
 *
 *
 * RCC/ServerWorks IDE driver for Linux
 *
 *   OSB4: `Open South Bridge' IDE Interface (fn 1)
 *         supports UDMA mode 2 (33 MB/s)
 *
 *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
 *         all revisions support UDMA mode 4 (66 MB/s)
 *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
 *
 *         *** The CSB5 does not provide ANY register ***
 *         *** to detect 80-conductor cable presence. ***
 *
 *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
 *
 *   HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
 *   controller same as the CSB6. Single channel ATA100 only.
 *
 * Documentation:
 *	Available under NDA only. Errata info very hard to get.
 *
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#define DRV_NAME "serverworks"

#define SVWKS_CSB5_REVISION_NEW	0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
#define SVWKS_CSB6_REVISION	0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */

/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
 * can overrun their FIFOs when used with the CSB5 */
static const char *svwks_bad_ata100[] = {
	"ST320011A",
	"ST340016A",
	"ST360021A",
	"ST380021A",
	NULL
};

static int check_in_drive_lists (ide_drive_t *drive, const char **list)
{
	char *m = (char *)&drive->id[ATA_ID_PROD];

	while (*list)
		if (!strcmp(*list++, m))
			return 1;
	return 0;
}

static u8 svwks_udma_filter(ide_drive_t *drive)
{
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);

	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
		return 0x1f;
	} else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
		return 0x07;
	} else {
		u8 btr = 0, mode, mask;

		pci_read_config_byte(dev, 0x5A, &btr);
		mode = btr & 0x3;

		/* If someone decides to do UDMA133 on CSB5 the same
		   issue will bite so be inclusive */
		if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
			mode = 2;

		switch(mode) {
		case 3:	 mask = 0x3f; break;
		case 2:	 mask = 0x1f; break;
		case 1:	 mask = 0x07; break;
		default: mask = 0x00; break;
		}

		return mask;
	}
}

static u8 svwks_csb_check (struct pci_dev *dev)
{
	switch (dev->device) {
		case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
		case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
			return 1;
		default:
			break;
	}
	return 0;
}

static void svwks_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
	static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };

	struct pci_dev *dev = to_pci_dev(hwif->dev);
	const u8 pio = drive->pio_mode - XFER_PIO_0;

	pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);

	if (svwks_csb_check(dev)) {
		u16 csb_pio = 0;

		pci_read_config_word(dev, 0x4a, &csb_pio);

		csb_pio &= ~(0x0f << (4 * drive->dn));
		csb_pio |= (pio << (4 * drive->dn));

		pci_write_config_word(dev, 0x4a, csb_pio);
	}
}

static void svwks_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	static const u8 udma_modes[]		= { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
	static const u8 dma_modes[]		= { 0x77, 0x21, 0x20 };
	static const u8 drive_pci2[]		= { 0x45, 0x44, 0x47, 0x46 };

	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	const u8 speed		= drive->dma_mode;
	u8 unit			= drive->dn & 1;

	u8 ultra_enable	 = 0, ultra_timing = 0, dma_timing = 0;

	pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
	pci_read_config_byte(dev, 0x54, &ultra_enable);

	ultra_timing	&= ~(0x0F << (4*unit));
	ultra_enable	&= ~(0x01 << drive->dn);

	if (speed >= XFER_UDMA_0) {
		dma_timing   |= dma_modes[2];
		ultra_timing |= (udma_modes[speed - XFER_UDMA_0] << (4 * unit));
		ultra_enable |= (0x01 << drive->dn);
	} else if (speed >= XFER_MW_DMA_0)
		dma_timing   |= dma_modes[speed - XFER_MW_DMA_0];

	pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
	pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
	pci_write_config_byte(dev, 0x54, ultra_enable);
}

static int init_chipset_svwks(struct pci_dev *dev)
{
	unsigned int reg;
	u8 btr;

	/* force Master Latency Timer value to 64 PCICLKs */
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);

	/* OSB4 : South Bridge and IDE */
	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
		struct pci_dev *isa_dev =
			pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
					PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
		if (isa_dev) {
			pci_read_config_dword(isa_dev, 0x64, &reg);
			reg &= ~0x00002000; /* disable 600ns interrupt mask */
			if(!(reg & 0x00004000))
				printk(KERN_DEBUG DRV_NAME " %s: UDMA not BIOS "
					"enabled.\n", pci_name(dev));
			reg |=  0x00004000; /* enable UDMA/33 support */
			pci_write_config_dword(isa_dev, 0x64, reg);
			pci_dev_put(isa_dev);
		}
	}

	/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
	else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
		 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
		 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {

		/* Third Channel Test */
		if (!(PCI_FUNC(dev->devfn) & 1)) {
			struct pci_dev * findev = NULL;
			u32 reg4c = 0;
			findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
				PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
			if (findev) {
				pci_read_config_dword(findev, 0x4C, &reg4c);
				reg4c &= ~0x000007FF;
				reg4c |=  0x00000040;
				reg4c |=  0x00000020;
				pci_write_config_dword(findev, 0x4C, reg4c);
				pci_dev_put(findev);
			}
			outb_p(0x06, 0x0c00);
			dev->irq = inb_p(0x0c01);
		} else {
			struct pci_dev * findev = NULL;
			u8 reg41 = 0;

			findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
					PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
			if (findev) {
				pci_read_config_byte(findev, 0x41, &reg41);
				reg41 &= ~0x40;
				pci_write_config_byte(findev, 0x41, reg41);
				pci_dev_put(findev);
			}
			/*
			 * This is a device pin issue on CSB6.
			 * Since there will be a future raid mode,
			 * early versions of the chipset require the
			 * interrupt pin to be set, and it is a compatibility
			 * mode issue.
			 */
			if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
				dev->irq = 0;
		}
//		pci_read_config_dword(dev, 0x40, &pioreg)
//		pci_write_config_dword(dev, 0x40, 0x99999999);
//		pci_read_config_dword(dev, 0x44, &dmareg);
//		pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
		/* setup the UDMA Control register
		 *
		 * 1. clear bit 6 to enable DMA
		 * 2. enable DMA modes with bits 0-1
		 * 	00 : legacy
		 * 	01 : udma2
		 * 	10 : udma2/udma4
		 * 	11 : udma2/udma4/udma5
		 */
		pci_read_config_byte(dev, 0x5A, &btr);
		btr &= ~0x40;
		if (!(PCI_FUNC(dev->devfn) & 1))
			btr |= 0x2;
		else
			btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
		pci_write_config_byte(dev, 0x5A, btr);
	}
	/* Setup HT1000 SouthBridge Controller - Single Channel Only */
	else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
		pci_read_config_byte(dev, 0x5A, &btr);
		btr &= ~0x40;
		btr |= 0x3;
		pci_write_config_byte(dev, 0x5A, btr);
	}

	return 0;
}

static u8 ata66_svwks_svwks(ide_hwif_t *hwif)
{
	return ATA_CBL_PATA80;
}

/* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
 * of the subsystem device ID indicate presence of an 80-pin cable.
 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
 * Bit 15 set   = secondary IDE channel has 80-pin cable.
 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
 * Bit 14 set   = primary IDE channel has 80-pin cable.
 */
static u8 ata66_svwks_dell(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
	    dev->vendor	== PCI_VENDOR_ID_SERVERWORKS &&
	    (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
	     dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
		return ((1 << (hwif->channel + 14)) &
			dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
	return ATA_CBL_PATA40;
}

/* Sun Cobalt Alpine hardware avoids the 80-pin cable
 * detect issue by attaching the drives directly to the board.
 * This check follows the Dell precedent (how scary is that?!)
 *
 * WARNING: this only works on Alpine hardware!
 */
static u8 ata66_svwks_cobalt(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
	    dev->vendor	== PCI_VENDOR_ID_SERVERWORKS &&
	    dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
		return ((1 << (hwif->channel + 14)) &
			dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
	return ATA_CBL_PATA40;
}

static u8 svwks_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	/* Server Works */
	if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
		return ata66_svwks_svwks (hwif);
	
	/* Dell PowerEdge */
	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
		return ata66_svwks_dell (hwif);

	/* Cobalt Alpine */
	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
		return ata66_svwks_cobalt (hwif);

	/* Per Specified Design by OEM, and ASIC Architect */
	if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
	    (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
		return ATA_CBL_PATA80;

	return ATA_CBL_PATA40;
}

static const struct ide_port_ops osb4_port_ops = {
	.set_pio_mode		= svwks_set_pio_mode,
	.set_dma_mode		= svwks_set_dma_mode,
};

static const struct ide_port_ops svwks_port_ops = {
	.set_pio_mode		= svwks_set_pio_mode,
	.set_dma_mode		= svwks_set_dma_mode,
	.udma_filter		= svwks_udma_filter,
	.cable_detect		= svwks_cable_detect,
};

static const struct ide_port_info serverworks_chipsets[] = {
	{	/* 0: OSB4 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_svwks,
		.port_ops	= &osb4_port_ops,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= 0x00, /* UDMA is problematic on OSB4 */
	},
	{	/* 1: CSB5 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_svwks,
		.port_ops	= &svwks_port_ops,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	},
	{	/* 2: CSB6 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_svwks,
		.port_ops	= &svwks_port_ops,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	},
	{	/* 3: CSB6-2 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_svwks,
		.port_ops	= &svwks_port_ops,
		.host_flags	= IDE_HFLAG_SINGLE,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	},
	{	/* 4: HT1000 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_svwks,
		.port_ops	= &svwks_port_ops,
		.host_flags	= IDE_HFLAG_SINGLE,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	}
};

/**
 *	svwks_init_one	-	called when a OSB/CSB is found
 *	@dev: the svwks device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct ide_port_info d;
	u8 idx = id->driver_data;

	d = serverworks_chipsets[idx];

	if (idx == 1)
		d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
	else if (idx == 2 || idx == 3) {
		if ((PCI_FUNC(dev->devfn) & 1) == 0) {
			if (pci_resource_start(dev, 0) != 0x01f1)
				d.host_flags |= IDE_HFLAG_NON_BOOTABLE;
			d.host_flags |= IDE_HFLAG_SINGLE;
		} else
			d.host_flags &= ~IDE_HFLAG_SINGLE;
	}

	return ide_pci_init_one(dev, &d, NULL);
}

static const struct pci_device_id svwks_pci_tbl[] = {
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE),   0 },
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE),   1 },
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE),   2 },
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2),  3 },
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);

static struct pci_driver svwks_pci_driver = {
	.name		= "Serverworks_IDE",
	.id_table	= svwks_pci_tbl,
	.probe		= svwks_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init svwks_ide_init(void)
{
	return ide_pci_register_driver(&svwks_pci_driver);
}

static void __exit svwks_ide_exit(void)
{
	pci_unregister_driver(&svwks_pci_driver);
}

module_init(svwks_ide_init);
module_exit(svwks_ide_exit);

MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick, Bartlomiej Zolnierkiewicz");
MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1998-2000 Michel Aubry
	3	* Copyright (C) 1998-2000 Andrzej Krzysztofowicz
	4	* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
e7593af6	5	* Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
1da177e4 LT	6	* Portions copyright (c) 2001 Sun Microsystems
	7	*
	8	*
	9	* RCC/ServerWorks IDE driver for Linux
	10	*
	11	* OSB4: `Open South Bridge' IDE Interface (fn 1)
	12	* supports UDMA mode 2 (33 MB/s)
	13	*
	14	* CSB5: `Champion South Bridge' IDE Interface (fn 1)
	15	* all revisions support UDMA mode 4 (66 MB/s)
	16	* revision A2.0 and up support UDMA mode 5 (100 MB/s)
	17	*
	18	* * The CSB5 does not provide ANY register *
	19	* * to detect 80-conductor cable presence. *
	20	*
	21	* CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
	22	*
84f57fbc NS	23	* HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
	24	* controller same as the CSB6. Single channel ATA100 only.
	25	*
1da177e4 LT	26	* Documentation:
	27	* Available under NDA only. Errata info very hard to get.
	28	*
	29	*/
	30
1da177e4 LT	31	#include <linux/types.h>
	32	#include <linux/module.h>
	33	#include <linux/kernel.h>
1da177e4	34	#include <linux/pci.h>
1da177e4 LT	35	#include <linux/ide.h>
1da177e4 LT	36	#include <linux/init.h>
1da177e4 LT	37
	38	#include <asm/io.h>
	39
ced3ec8a BZ	40	#define DRV_NAME "serverworks"
ced3ec8a BZ	41
1da177e4 LT	42	#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
	43	#define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
	44
	45	/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
	46	* can overrun their FIFOs when used with the CSB5 */
	47	static const char *svwks_bad_ata100[] = {
	48	"ST320011A",
	49	"ST340016A",
	50	"ST360021A",
	51	"ST380021A",
	52	NULL
	53	};
	54
1da177e4 LT	55	static int check_in_drive_lists (ide_drive_t drive, const char *list)
1da177e4 LT	56	{
4dde4492 BZ	57	char m = (char )&drive->id[ATA_ID_PROD];
4dde4492 BZ	58
1da177e4	59	while (*list)
4dde4492	60	if (!strcmp(*list++, m))
1da177e4 LT	61	return 1;
	62	return 0;
	63	}
	64
2d5eaa6d	65	static u8 svwks_udma_filter(ide_drive_t *drive)
1da177e4	66	{
36501650	67	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
1da177e4	68
e7593af6	69	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
2d5eaa6d	70	return 0x1f;
44c10138	71	} else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
2d5eaa6d	72	return 0x07;
e7593af6 BZ	73	} else {
	74	u8 btr = 0, mode, mask;
	75
1da177e4 LT	76	pci_read_config_byte(dev, 0x5A, &btr);
1da177e4 LT	77	mode = btr & 0x3;
2d5eaa6d	78
1da177e4 LT	79	/* If someone decides to do UDMA133 on CSB5 the same
	80	issue will bite so be inclusive */
	81	if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
	82	mode = 2;
2d5eaa6d BZ	83
2d5eaa6d BZ	84	switch(mode) {
0c824b51	85	case 3: mask = 0x3f; break;
2d5eaa6d BZ	86	case 2: mask = 0x1f; break;
	87	case 1: mask = 0x07; break;
	88	default: mask = 0x00; break;
	89	}
2d5eaa6d	90
e7593af6 BZ	91	return mask;
e7593af6 BZ	92	}
1da177e4 LT	93	}
	94
	95	static u8 svwks_csb_check (struct pci_dev *dev)
	96	{
	97	switch (dev->device) {
	98	case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
	99	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
	100	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
84f57fbc	101	case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
1da177e4 LT	102	return 1;
	103	default:
	104	break;
	105	}
	106	return 0;
	107	}
1880a8d7	108
e085b3ca	109	static void svwks_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
1880a8d7 BZ	110	{
	111	static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
	112	static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
	113
e085b3ca BZ	114	struct pci_dev *dev = to_pci_dev(hwif->dev);
e085b3ca BZ	115	const u8 pio = drive->pio_mode - XFER_PIO_0;
1880a8d7 BZ	116
	117	pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
	118
	119	if (svwks_csb_check(dev)) {
	120	u16 csb_pio = 0;
	121
	122	pci_read_config_word(dev, 0x4a, &csb_pio);
	123
	124	csb_pio &= ~(0x0f << (4 * drive->dn));
	125	csb_pio \|= (pio << (4 * drive->dn));
	126
	127	pci_write_config_word(dev, 0x4a, csb_pio);
	128	}
	129	}
	130
8776168c	131	static void svwks_set_dma_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	132	{
f201f504 AC	133	static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
f201f504 AC	134	static const u8 dma_modes[] = { 0x77, 0x21, 0x20 };
f201f504	135	static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
1da177e4	136
36501650	137	struct pci_dev *dev = to_pci_dev(hwif->dev);
8776168c	138	const u8 speed = drive->dma_mode;
123995b9	139	u8 unit = drive->dn & 1;
1880a8d7 BZ	140
	141	u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0;
	142
1da177e4	143	pci_read_config_byte(dev, (0x56\|hwif->channel), &ultra_timing);
1da177e4 LT	144	pci_read_config_byte(dev, 0x54, &ultra_enable);
1da177e4 LT	145
1da177e4 LT	146	ultra_timing &= ~(0x0F << (4*unit));
1da177e4 LT	147	ultra_enable &= ~(0x01 << drive->dn);
1da177e4	148
7b971df1 BZ	149	if (speed >= XFER_UDMA_0) {
	150	dma_timing \|= dma_modes[2];
	151	ultra_timing \|= (udma_modes[speed - XFER_UDMA_0] << (4 * unit));
	152	ultra_enable \|= (0x01 << drive->dn);
	153	} else if (speed >= XFER_MW_DMA_0)
	154	dma_timing \|= dma_modes[speed - XFER_MW_DMA_0];
1da177e4	155
1da177e4 LT	156	pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
	157	pci_write_config_byte(dev, (0x56\|hwif->channel), ultra_timing);
	158	pci_write_config_byte(dev, 0x54, ultra_enable);
1da177e4 LT	159	}
1da177e4 LT	160
2ed0ef54	161	static int init_chipset_svwks(struct pci_dev *dev)
1da177e4 LT	162	{
	163	unsigned int reg;
	164	u8 btr;
	165
1da177e4 LT	166	/* force Master Latency Timer value to 64 PCICLKs */
	167	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
	168
	169	/* OSB4 : South Bridge and IDE */
	170	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
e7593af6 BZ	171	struct pci_dev *isa_dev =
	172	pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
	173	PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
1da177e4 LT	174	if (isa_dev) {
	175	pci_read_config_dword(isa_dev, 0x64, &reg);
	176	reg &= ~0x00002000; /* disable 600ns interrupt mask */
	177	if(!(reg & 0x00004000))
a326b02b BZ	178	printk(KERN_DEBUG DRV_NAME " %s: UDMA not BIOS "
a326b02b BZ	179	"enabled.\n", pci_name(dev));
1da177e4 LT	180	reg \|= 0x00004000; /* enable UDMA/33 support */
1da177e4 LT	181	pci_write_config_dword(isa_dev, 0x64, reg);
cb06fc3f	182	pci_dev_put(isa_dev);
1da177e4 LT	183	}
	184	}
	185
	186	/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
	187	else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) \|\|
	188	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) \|\|
	189	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
	190
	191	/* Third Channel Test */
	192	if (!(PCI_FUNC(dev->devfn) & 1)) {
	193	struct pci_dev * findev = NULL;
	194	u32 reg4c = 0;
970a6136	195	findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
1da177e4 LT	196	PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
	197	if (findev) {
	198	pci_read_config_dword(findev, 0x4C, &reg4c);
	199	reg4c &= ~0x000007FF;
	200	reg4c \|= 0x00000040;
	201	reg4c \|= 0x00000020;
	202	pci_write_config_dword(findev, 0x4C, reg4c);
970a6136	203	pci_dev_put(findev);
1da177e4 LT	204	}
	205	outb_p(0x06, 0x0c00);
	206	dev->irq = inb_p(0x0c01);
1da177e4 LT	207	} else {
	208	struct pci_dev * findev = NULL;
	209	u8 reg41 = 0;
	210
970a6136	211	findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
1da177e4 LT	212	PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
	213	if (findev) {
	214	pci_read_config_byte(findev, 0x41, &reg41);
	215	reg41 &= ~0x40;
	216	pci_write_config_byte(findev, 0x41, reg41);
970a6136	217	pci_dev_put(findev);
1da177e4 LT	218	}
	219	/*
	220	* This is a device pin issue on CSB6.
	221	* Since there will be a future raid mode,
	222	* early versions of the chipset require the
	223	* interrupt pin to be set, and it is a compatibility
	224	* mode issue.
	225	*/
	226	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
	227	dev->irq = 0;
	228	}
	229	// pci_read_config_dword(dev, 0x40, &pioreg)
	230	// pci_write_config_dword(dev, 0x40, 0x99999999);
	231	// pci_read_config_dword(dev, 0x44, &dmareg);
	232	// pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
	233	/* setup the UDMA Control register
	234	*
	235	* 1. clear bit 6 to enable DMA
	236	* 2. enable DMA modes with bits 0-1
	237	* 00 : legacy
	238	* 01 : udma2
	239	* 10 : udma2/udma4
	240	* 11 : udma2/udma4/udma5
	241	*/
	242	pci_read_config_byte(dev, 0x5A, &btr);
	243	btr &= ~0x40;
	244	if (!(PCI_FUNC(dev->devfn) & 1))
	245	btr \|= 0x2;
	246	else
44c10138	247	btr \|= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
1da177e4 LT	248	pci_write_config_byte(dev, 0x5A, btr);
1da177e4 LT	249	}
84f57fbc NS	250	/* Setup HT1000 SouthBridge Controller - Single Channel Only */
	251	else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
	252	pci_read_config_byte(dev, 0x5A, &btr);
	253	btr &= ~0x40;
	254	btr \|= 0x3;
	255	pci_write_config_byte(dev, 0x5A, btr);
	256	}
1da177e4	257
2ed0ef54	258	return 0;
1da177e4 LT	259	}
1da177e4 LT	260
f454cbe8	261	static u8 ata66_svwks_svwks(ide_hwif_t *hwif)
1da177e4	262	{
49521f97	263	return ATA_CBL_PATA80;
1da177e4 LT	264	}
	265
	266	/* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
	267	* of the subsystem device ID indicate presence of an 80-pin cable.
	268	* Bit 15 clear = secondary IDE channel does not have 80-pin cable.
	269	* Bit 15 set = secondary IDE channel has 80-pin cable.
	270	* Bit 14 clear = primary IDE channel does not have 80-pin cable.
	271	* Bit 14 set = primary IDE channel has 80-pin cable.
	272	*/
f454cbe8	273	static u8 ata66_svwks_dell(ide_hwif_t *hwif)
1da177e4	274	{
36501650 BZ	275	struct pci_dev *dev = to_pci_dev(hwif->dev);
36501650 BZ	276
1da177e4 LT	277	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
	278	dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
	279	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE \|\|
	280	dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
	281	return ((1 << (hwif->channel + 14)) &
49521f97 BZ	282	dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
49521f97 BZ	283	return ATA_CBL_PATA40;
1da177e4 LT	284	}
	285
	286	/* Sun Cobalt Alpine hardware avoids the 80-pin cable
	287	* detect issue by attaching the drives directly to the board.
	288	* This check follows the Dell precedent (how scary is that?!)
	289	*
	290	* WARNING: this only works on Alpine hardware!
	291	*/
f454cbe8	292	static u8 ata66_svwks_cobalt(ide_hwif_t *hwif)
1da177e4	293	{
36501650 BZ	294	struct pci_dev *dev = to_pci_dev(hwif->dev);
36501650 BZ	295
1da177e4 LT	296	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
	297	dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
	298	dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
	299	return ((1 << (hwif->channel + 14)) &
49521f97 BZ	300	dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
49521f97 BZ	301	return ATA_CBL_PATA40;
1da177e4 LT	302	}
1da177e4 LT	303
f454cbe8	304	static u8 svwks_cable_detect(ide_hwif_t *hwif)
1da177e4	305	{
36501650	306	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	307
1da177e4 LT	308	/* Server Works */
	309	if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
	310	return ata66_svwks_svwks (hwif);
	311
	312	/* Dell PowerEdge */
	313	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
	314	return ata66_svwks_dell (hwif);
	315
	316	/* Cobalt Alpine */
	317	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
	318	return ata66_svwks_cobalt (hwif);
	319
f201f504 AC	320	/* Per Specified Design by OEM, and ASIC Architect */
	321	if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) \|\|
	322	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
49521f97	323	return ATA_CBL_PATA80;
f201f504	324
49521f97	325	return ATA_CBL_PATA40;
1da177e4 LT	326	}
1da177e4 LT	327
ac95beed BZ	328	static const struct ide_port_ops osb4_port_ops = {
	329	.set_pio_mode = svwks_set_pio_mode,
	330	.set_dma_mode = svwks_set_dma_mode,
ac95beed	331	};
1da177e4	332
ac95beed BZ	333	static const struct ide_port_ops svwks_port_ops = {
	334	.set_pio_mode = svwks_set_pio_mode,
	335	.set_dma_mode = svwks_set_dma_mode,
	336	.udma_filter = svwks_udma_filter,
	337	.cable_detect = svwks_cable_detect,
	338	};
1da177e4	339
fe31edc8	340	static const struct ide_port_info serverworks_chipsets[] = {
ced3ec8a BZ	341	{ /* 0: OSB4 */
ced3ec8a BZ	342	.name = DRV_NAME,
1da177e4	343	.init_chipset = init_chipset_svwks,
ac95beed	344	.port_ops = &osb4_port_ops,
4099d143	345	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	346	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	347	.udma_mask = 0x00, /* UDMA is problematic on OSB4 */
ced3ec8a BZ	348	},
	349	{ /* 1: CSB5 */
	350	.name = DRV_NAME,
1da177e4	351	.init_chipset = init_chipset_svwks,
ac95beed	352	.port_ops = &svwks_port_ops,
4099d143	353	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	354	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	355	.udma_mask = ATA_UDMA5,
ced3ec8a BZ	356	},
	357	{ /* 2: CSB6 */
	358	.name = DRV_NAME,
1da177e4	359	.init_chipset = init_chipset_svwks,
ac95beed	360	.port_ops = &svwks_port_ops,
4099d143	361	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	362	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	363	.udma_mask = ATA_UDMA5,
ced3ec8a BZ	364	},
	365	{ /* 3: CSB6-2 */
	366	.name = DRV_NAME,
1da177e4	367	.init_chipset = init_chipset_svwks,
ac95beed	368	.port_ops = &svwks_port_ops,
2467922a	369	.host_flags = IDE_HFLAG_SINGLE,
4099d143	370	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	371	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	372	.udma_mask = ATA_UDMA5,
ced3ec8a BZ	373	},
	374	{ /* 4: HT1000 */
	375	.name = DRV_NAME,
84f57fbc	376	.init_chipset = init_chipset_svwks,
ac95beed	377	.port_ops = &svwks_port_ops,
2467922a	378	.host_flags = IDE_HFLAG_SINGLE,
4099d143	379	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	380	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	381	.udma_mask = ATA_UDMA5,
1da177e4 LT	382	}
	383	};
	384
	385	/**
	386	* svwks_init_one - called when a OSB/CSB is found
	387	* @dev: the svwks device
	388	* @id: the matching pci id
	389	*
	390	* Called when the PCI registration layer (or the IDE initialization)
	391	* finds a device matching our IDE device tables.
	392	*/
	393
fe31edc8	394	static int svwks_init_one(struct pci_dev dev, const struct pci_device_id id)
1da177e4	395	{
039788e1	396	struct ide_port_info d;
7ed58297 BZ	397	u8 idx = id->driver_data;
	398
	399	d = serverworks_chipsets[idx];
	400
8ac2b42a BZ	401	if (idx == 1)
	402	d.host_flags \|= IDE_HFLAG_CLEAR_SIMPLEX;
	403	else if (idx == 2 \|\| idx == 3) {
7ed58297 BZ	404	if ((PCI_FUNC(dev->devfn) & 1) == 0) {
7ed58297 BZ	405	if (pci_resource_start(dev, 0) != 0x01f1)
5e71d9c5	406	d.host_flags \|= IDE_HFLAG_NON_BOOTABLE;
7ed58297 BZ	407	d.host_flags \|= IDE_HFLAG_SINGLE;
	408	} else
	409	d.host_flags &= ~IDE_HFLAG_SINGLE;
	410	}
1da177e4	411
6cdf6eb3	412	return ide_pci_init_one(dev, &d, NULL);
1da177e4 LT	413	}
1da177e4 LT	414
9cbcc5e3 BZ	415	static const struct pci_device_id svwks_pci_tbl[] = {
	416	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0 },
	417	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 1 },
	418	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2 },
	419	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 3 },
	420	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 },
1da177e4 LT	421	{ 0, },
	422	};
	423	MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
	424
a9ab09e2	425	static struct pci_driver svwks_pci_driver = {
1da177e4 LT	426	.name = "Serverworks_IDE",
	427	.id_table = svwks_pci_tbl,
	428	.probe = svwks_init_one,
bc2c9a80	429	.remove = ide_pci_remove,
feb22b7f BZ	430	.suspend = ide_pci_suspend,
feb22b7f BZ	431	.resume = ide_pci_resume,
1da177e4 LT	432	};
1da177e4 LT	433
82ab1eec	434	static int __init svwks_ide_init(void)
1da177e4	435	{
a9ab09e2	436	return ide_pci_register_driver(&svwks_pci_driver);
1da177e4 LT	437	}
1da177e4 LT	438
bc2c9a80 BZ	439	static void __exit svwks_ide_exit(void)
bc2c9a80 BZ	440	{
a9ab09e2	441	pci_unregister_driver(&svwks_pci_driver);
bc2c9a80 BZ	442	}
bc2c9a80 BZ	443
1da177e4	444	module_init(svwks_ide_init);
bc2c9a80	445	module_exit(svwks_ide_exit);
1da177e4	446
e7593af6	447	MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick, Bartlomiej Zolnierkiewicz");
1da177e4 LT	448	MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
1da177e4 LT	449	MODULE_LICENSE("GPL");