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ia64: add pci_get_legacy_ide_irq()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / serverworks.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/ide/pci/serverworks.c Version 0.8 25 Ebr 2003
3 *
4 * Copyright (C) 1998-2000 Michel Aubry
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
6 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
7 * Portions copyright (c) 2001 Sun Microsystems
8 *
9 *
10 * RCC/ServerWorks IDE driver for Linux
11 *
12 * OSB4: `Open South Bridge' IDE Interface (fn 1)
13 * supports UDMA mode 2 (33 MB/s)
14 *
15 * CSB5: `Champion South Bridge' IDE Interface (fn 1)
16 * all revisions support UDMA mode 4 (66 MB/s)
17 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
18 *
19 * *** The CSB5 does not provide ANY register ***
20 * *** to detect 80-conductor cable presence. ***
21 *
22 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
23 *
84f57fbc
NS		 24 * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
25 * controller same as the CSB6. Single channel ATA100 only.
26 *
1da177e4
LT		 27 * Documentation:
28 * Available under NDA only. Errata info very hard to get.
29 *
30 */
31
1da177e4
LT		 32#include <linux/types.h>
33#include <linux/module.h>
34#include <linux/kernel.h>
35#include <linux/ioport.h>
36#include <linux/pci.h>
37#include <linux/hdreg.h>
38#include <linux/ide.h>
39#include <linux/init.h>
40#include <linux/delay.h>
41
42#include <asm/io.h>
43
44#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
45#define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
46
47/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
48 * can overrun their FIFOs when used with the CSB5 */
49static const char *svwks_bad_ata100[] = {
50 "ST320011A",
51 "ST340016A",
52 "ST360021A",
53 "ST380021A",
54 NULL
55};
56
57static u8 svwks_revision = 0;
58static struct pci_dev *isa_dev;
59
60static int check_in_drive_lists (ide_drive_t *drive, const char **list)
61{
62 while (*list)
63 if (!strcmp(*list++, drive->id->model))
64 return 1;
65 return 0;
66}
67
68static u8 svwks_ratemask (ide_drive_t *drive)
69{
70 struct pci_dev *dev = HWIF(drive)->pci_dev;
6d524aed 71 u8 mode = 0;
1da177e4
LT		 72
73 if (!svwks_revision)
74 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
75
84f57fbc
NS		 76 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
77 return 2;
1da177e4
LT		 78 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
79 u32 reg = 0;
80 if (isa_dev)
81 pci_read_config_dword(isa_dev, 0x64, &reg);
82
83 /*
84 * Don't enable UDMA on disk devices for the moment
85 */
86 if(drive->media == ide_disk)
87 return 0;
88 /* Check the OSB4 DMA33 enable bit */
89 return ((reg & 0x00004000) == 0x00004000) ? 1 : 0;
90 } else if (svwks_revision < SVWKS_CSB5_REVISION_NEW) {
91 return 1;
92 } else if (svwks_revision >= SVWKS_CSB5_REVISION_NEW) {
93 u8 btr = 0;
94 pci_read_config_byte(dev, 0x5A, &btr);
95 mode = btr & 0x3;
96 if (!eighty_ninty_three(drive))
97 mode = min(mode, (u8)1);
98 /* If someone decides to do UDMA133 on CSB5 the same
99 issue will bite so be inclusive */
100 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
101 mode = 2;
102 }
103 if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
104 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
105 (!(PCI_FUNC(dev->devfn) & 1)))
106 mode = 2;
107 return mode;
108}
109
110static u8 svwks_csb_check (struct pci_dev *dev)
111{
112 switch (dev->device) {
113 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
114 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
115 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
84f57fbc 116 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
1da177e4
LT		 117 return 1;
118 default:
119 break;
120 }
121 return 0;
122}
123static int svwks_tune_chipset (ide_drive_t *drive, u8 xferspeed)
124{
f201f504
AC		 125 static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
126 static const u8 dma_modes[] = { 0x77, 0x21, 0x20 };
127 static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
128 static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
129 static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
1da177e4
LT		 130
131 ide_hwif_t *hwif = HWIF(drive);
132 struct pci_dev *dev = hwif->pci_dev;
133 u8 speed;
134 u8 pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
135 u8 unit = (drive->select.b.unit & 0x01);
136 u8 csb5 = svwks_csb_check(dev);
137 u8 ultra_enable = 0, ultra_timing = 0;
138 u8 dma_timing = 0, pio_timing = 0;
139 u16 csb5_pio = 0;
140
141 if (xferspeed == 255) /* PIO auto-tuning */
142 speed = XFER_PIO_0 + pio;
143 else
144 speed = ide_rate_filter(svwks_ratemask(drive), xferspeed);
145
146 /* If we are about to put a disk into UDMA mode we screwed up.
147 Our code assumes we never _ever_ do this on an OSB4 */
148
149 if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
150 drive->media == ide_disk && speed >= XFER_UDMA_0)
151 BUG();
152
153 pci_read_config_byte(dev, drive_pci[drive->dn], &pio_timing);
154 pci_read_config_byte(dev, drive_pci2[drive->dn], &dma_timing);
155 pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
156 pci_read_config_word(dev, 0x4A, &csb5_pio);
157 pci_read_config_byte(dev, 0x54, &ultra_enable);
158
159 /* Per Specified Design by OEM, and ASIC Architect */
160 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
161 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
162 if (!drive->init_speed) {
163 u8 dma_stat = hwif->INB(hwif->dma_status);
164
165dma_pio:
166 if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) &&
167 ((dma_stat & (1<<(5+unit))) == (1<<(5+unit)))) {
168 drive->current_speed = drive->init_speed = XFER_UDMA_0 + udma_modes[(ultra_timing >> (4*unit)) & ~(0xF0)];
169 return 0;
170 } else if ((dma_timing) &&
171 ((dma_stat&(1<<(5+unit)))==(1<<(5+unit)))) {
172 u8 dmaspeed = dma_timing;
173
174 dma_timing &= ~0xFF;
175 if ((dmaspeed & 0x20) == 0x20)
176 dmaspeed = XFER_MW_DMA_2;
177 else if ((dmaspeed & 0x21) == 0x21)
178 dmaspeed = XFER_MW_DMA_1;
179 else if ((dmaspeed & 0x77) == 0x77)
180 dmaspeed = XFER_MW_DMA_0;
181 else
182 goto dma_pio;
183 drive->current_speed = drive->init_speed = dmaspeed;
184 return 0;
185 } else if (pio_timing) {
186 u8 piospeed = pio_timing;
187
188 pio_timing &= ~0xFF;
189 if ((piospeed & 0x20) == 0x20)
190 piospeed = XFER_PIO_4;
191 else if ((piospeed & 0x22) == 0x22)
192 piospeed = XFER_PIO_3;
193 else if ((piospeed & 0x34) == 0x34)
194 piospeed = XFER_PIO_2;
195 else if ((piospeed & 0x47) == 0x47)
196 piospeed = XFER_PIO_1;
197 else if ((piospeed & 0x5d) == 0x5d)
198 piospeed = XFER_PIO_0;
199 else
200 goto oem_setup_failed;
201 drive->current_speed = drive->init_speed = piospeed;
202 return 0;
203 }
204 }
205 }
206
207oem_setup_failed:
208
209 pio_timing &= ~0xFF;
210 dma_timing &= ~0xFF;
211 ultra_timing &= ~(0x0F << (4*unit));
212 ultra_enable &= ~(0x01 << drive->dn);
213 csb5_pio &= ~(0x0F << (4*drive->dn));
214
215 switch(speed) {
216 case XFER_PIO_4:
217 case XFER_PIO_3:
218 case XFER_PIO_2:
219 case XFER_PIO_1:
220 case XFER_PIO_0:
221 pio_timing |= pio_modes[speed - XFER_PIO_0];
222 csb5_pio |= ((speed - XFER_PIO_0) << (4*drive->dn));
223 break;
224
225 case XFER_MW_DMA_2:
226 case XFER_MW_DMA_1:
227 case XFER_MW_DMA_0:
228 pio_timing |= pio_modes[pio];
229 csb5_pio |= (pio << (4*drive->dn));
230 dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
231 break;
232
233 case XFER_UDMA_5:
234 case XFER_UDMA_4:
235 case XFER_UDMA_3:
236 case XFER_UDMA_2:
237 case XFER_UDMA_1:
238 case XFER_UDMA_0:
239 pio_timing |= pio_modes[pio];
240 csb5_pio |= (pio << (4*drive->dn));
241 dma_timing |= dma_modes[2];
242 ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
243 ultra_enable |= (0x01 << drive->dn);
244 default:
245 break;
246 }
247
248 pci_write_config_byte(dev, drive_pci[drive->dn], pio_timing);
249 if (csb5)
250 pci_write_config_word(dev, 0x4A, csb5_pio);
251
252 pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
253 pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
254 pci_write_config_byte(dev, 0x54, ultra_enable);
255
256 return (ide_config_drive_speed(drive, speed));
257}
258
259static void config_chipset_for_pio (ide_drive_t *drive)
260{
261 u16 eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
262 u16 xfer_pio = drive->id->eide_pio_modes;
263 u8 timing, speed, pio;
264
265 pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
266
267 if (xfer_pio > 4)
268 xfer_pio = 0;
269
270 if (drive->id->eide_pio_iordy > 0)
271 for (xfer_pio = 5;
272 xfer_pio>0 &&
273 drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
274 xfer_pio--);
275 else
276 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
277 (drive->id->eide_pio_modes & 2) ? 0x04 :
278 (drive->id->eide_pio_modes & 1) ? 0x03 :
279 (drive->id->tPIO & 2) ? 0x02 :
280 (drive->id->tPIO & 1) ? 0x01 : xfer_pio;
281
282 timing = (xfer_pio >= pio) ? xfer_pio : pio;
283
284 switch(timing) {
285 case 4: speed = XFER_PIO_4;break;
286 case 3: speed = XFER_PIO_3;break;
287 case 2: speed = XFER_PIO_2;break;
288 case 1: speed = XFER_PIO_1;break;
289 default:
290 speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
291 break;
292 }
293 (void) svwks_tune_chipset(drive, speed);
294 drive->current_speed = speed;
295}
296
297static void svwks_tune_drive (ide_drive_t *drive, u8 pio)
298{
299 if(pio == 255)
300 (void) svwks_tune_chipset(drive, 255);
301 else
302 (void) svwks_tune_chipset(drive, (XFER_PIO_0 + pio));
303}
304
305static int config_chipset_for_dma (ide_drive_t *drive)
306{
307 u8 speed = ide_dma_speed(drive, svwks_ratemask(drive));
308
309 if (!(speed))
310 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
311
312 (void) svwks_tune_chipset(drive, speed);
313 return ide_dma_enable(drive);
314}
315
316static int svwks_config_drive_xfer_rate (ide_drive_t *drive)
317{
318 ide_hwif_t *hwif = HWIF(drive);
319 struct hd_driveid *id = drive->id;
320
321 drive->init_speed = 0;
322
323 if ((id->capability & 1) && drive->autodma) {
324
325 if (ide_use_dma(drive)) {
326 if (config_chipset_for_dma(drive))
327 return hwif->ide_dma_on(drive);
328 }
329
330 goto fast_ata_pio;
331
332 } else if ((id->capability & 8) || (id->field_valid & 2)) {
333fast_ata_pio:
334 config_chipset_for_pio(drive);
335 // hwif->tuneproc(drive, 5);
336 return hwif->ide_dma_off_quietly(drive);
337 }
338 /* IORDY not supported */
339 return 0;
340}
341
342/* This can go soon */
343
344static int svwks_ide_dma_end (ide_drive_t *drive)
345{
346 return __ide_dma_end(drive);
347}
348
349static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
350{
351 unsigned int reg;
352 u8 btr;
353
354 /* save revision id to determine DMA capability */
355 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
356
357 /* force Master Latency Timer value to 64 PCICLKs */
358 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
359
360 /* OSB4 : South Bridge and IDE */
361 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
970a6136 362 isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
1da177e4
LT		 363 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
364 if (isa_dev) {
365 pci_read_config_dword(isa_dev, 0x64, &reg);
366 reg &= ~0x00002000; /* disable 600ns interrupt mask */
367 if(!(reg & 0x00004000))
368 printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
369 reg |= 0x00004000; /* enable UDMA/33 support */
370 pci_write_config_dword(isa_dev, 0x64, reg);
371 }
372 }
373
374 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
375 else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
376 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
377 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
378
379 /* Third Channel Test */
380 if (!(PCI_FUNC(dev->devfn) & 1)) {
381 struct pci_dev * findev = NULL;
382 u32 reg4c = 0;
970a6136 383 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
1da177e4
LT		 384 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
385 if (findev) {
386 pci_read_config_dword(findev, 0x4C, &reg4c);
387 reg4c &= ~0x000007FF;
388 reg4c |= 0x00000040;
389 reg4c |= 0x00000020;
390 pci_write_config_dword(findev, 0x4C, reg4c);
970a6136 391 pci_dev_put(findev);
1da177e4
LT		 392 }
393 outb_p(0x06, 0x0c00);
394 dev->irq = inb_p(0x0c01);
1da177e4
LT		 395 } else {
396 struct pci_dev * findev = NULL;
397 u8 reg41 = 0;
398
970a6136 399 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
1da177e4
LT		 400 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
401 if (findev) {
402 pci_read_config_byte(findev, 0x41, &reg41);
403 reg41 &= ~0x40;
404 pci_write_config_byte(findev, 0x41, reg41);
970a6136 405 pci_dev_put(findev);
1da177e4
LT		 406 }
407 /*
408 * This is a device pin issue on CSB6.
409 * Since there will be a future raid mode,
410 * early versions of the chipset require the
411 * interrupt pin to be set, and it is a compatibility
412 * mode issue.
413 */
414 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
415 dev->irq = 0;
416 }
417// pci_read_config_dword(dev, 0x40, &pioreg)
418// pci_write_config_dword(dev, 0x40, 0x99999999);
419// pci_read_config_dword(dev, 0x44, &dmareg);
420// pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
421 /* setup the UDMA Control register
422 *
423 * 1. clear bit 6 to enable DMA
424 * 2. enable DMA modes with bits 0-1
425 * 00 : legacy
426 * 01 : udma2
427 * 10 : udma2/udma4
428 * 11 : udma2/udma4/udma5
429 */
430 pci_read_config_byte(dev, 0x5A, &btr);
431 btr &= ~0x40;
432 if (!(PCI_FUNC(dev->devfn) & 1))
433 btr |= 0x2;
434 else
435 btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
436 pci_write_config_byte(dev, 0x5A, btr);
437 }
84f57fbc
NS		 438 /* Setup HT1000 SouthBridge Controller - Single Channel Only */
439 else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
440 pci_read_config_byte(dev, 0x5A, &btr);
441 btr &= ~0x40;
442 btr |= 0x3;
443 pci_write_config_byte(dev, 0x5A, btr);
444 }
1da177e4 445
f201f504 446 return dev->irq;
1da177e4
LT		 447}
448
bb732d7b 449static unsigned int __devinit ata66_svwks_svwks (ide_hwif_t *hwif)
1da177e4
LT		 450{
451 return 1;
452}
453
454/* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
455 * of the subsystem device ID indicate presence of an 80-pin cable.
456 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
457 * Bit 15 set = secondary IDE channel has 80-pin cable.
458 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
459 * Bit 14 set = primary IDE channel has 80-pin cable.
460 */
bb732d7b 461static unsigned int __devinit ata66_svwks_dell (ide_hwif_t *hwif)
1da177e4
LT		 462{
463 struct pci_dev *dev = hwif->pci_dev;
464 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
465 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
466 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
467 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
468 return ((1 << (hwif->channel + 14)) &
469 dev->subsystem_device) ? 1 : 0;
470 return 0;
471}
472
473/* Sun Cobalt Alpine hardware avoids the 80-pin cable
474 * detect issue by attaching the drives directly to the board.
475 * This check follows the Dell precedent (how scary is that?!)
476 *
477 * WARNING: this only works on Alpine hardware!
478 */
bb732d7b 479static unsigned int __devinit ata66_svwks_cobalt (ide_hwif_t *hwif)
1da177e4
LT		 480{
481 struct pci_dev *dev = hwif->pci_dev;
482 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
483 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
484 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
485 return ((1 << (hwif->channel + 14)) &
486 dev->subsystem_device) ? 1 : 0;
487 return 0;
488}
489
bb732d7b 490static unsigned int __devinit ata66_svwks (ide_hwif_t *hwif)
1da177e4
LT		 491{
492 struct pci_dev *dev = hwif->pci_dev;
493
1da177e4
LT		 494 /* Server Works */
495 if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
496 return ata66_svwks_svwks (hwif);
497
498 /* Dell PowerEdge */
499 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
500 return ata66_svwks_dell (hwif);
501
502 /* Cobalt Alpine */
503 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
504 return ata66_svwks_cobalt (hwif);
505
f201f504
AC		 506 /* Per Specified Design by OEM, and ASIC Architect */
507 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
508 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
509 return 1;
510
1da177e4
LT		 511 return 0;
512}
513
1da177e4
LT		 514static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
515{
516 u8 dma_stat = 0;
517
518 if (!hwif->irq)
519 hwif->irq = hwif->channel ? 15 : 14;
520
521 hwif->tuneproc = &svwks_tune_drive;
522 hwif->speedproc = &svwks_tune_chipset;
523
524 hwif->atapi_dma = 1;
525
526 if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
527 hwif->ultra_mask = 0x3f;
528
529 hwif->mwdma_mask = 0x07;
1da177e4
LT		 530
531 hwif->autodma = 0;
532
533 if (!hwif->dma_base) {
534 hwif->drives[0].autotune = 1;
535 hwif->drives[1].autotune = 1;
536 return;
537 }
538
539 hwif->ide_dma_check = &svwks_config_drive_xfer_rate;
540 if (hwif->pci_dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
541 hwif->ide_dma_end = &svwks_ide_dma_end;
542 else if (!(hwif->udma_four))
543 hwif->udma_four = ata66_svwks(hwif);
544 if (!noautodma)
545 hwif->autodma = 1;
546
547 dma_stat = hwif->INB(hwif->dma_status);
548 hwif->drives[0].autodma = (dma_stat & 0x20);
549 hwif->drives[1].autodma = (dma_stat & 0x40);
550 hwif->drives[0].autotune = (!(dma_stat & 0x20));
551 hwif->drives[1].autotune = (!(dma_stat & 0x40));
1da177e4
LT		 552}
553
554/*
555 * We allow the BM-DMA driver to only work on enabled interfaces.
556 */
557static void __devinit init_dma_svwks (ide_hwif_t *hwif, unsigned long dmabase)
558{
559 struct pci_dev *dev = hwif->pci_dev;
560
561 if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
562 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
563 (!(PCI_FUNC(dev->devfn) & 1)) && (hwif->channel))
564 return;
565
566 ide_setup_dma(hwif, dmabase, 8);
567}
568
569static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d)
570{
571 return ide_setup_pci_device(dev, d);
572}
573
bb732d7b 574static int __devinit init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d)
1da177e4
LT		 575{
576 if (!(PCI_FUNC(dev->devfn) & 1)) {
577 d->bootable = NEVER_BOARD;
578 if (dev->resource[0].start == 0x01f1)
579 d->bootable = ON_BOARD;
580 }
1da177e4
LT		 581
582 d->channels = ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE ||
583 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) &&
584 (!(PCI_FUNC(dev->devfn) & 1))) ? 1 : 2;
585
586 return ide_setup_pci_device(dev, d);
587}
588
589static ide_pci_device_t serverworks_chipsets[] __devinitdata = {
590 { /* 0 */
591 .name = "SvrWks OSB4",
592 .init_setup = init_setup_svwks,
593 .init_chipset = init_chipset_svwks,
594 .init_hwif = init_hwif_svwks,
595 .channels = 2,
596 .autodma = AUTODMA,
597 .bootable = ON_BOARD,
598 },{ /* 1 */
599 .name = "SvrWks CSB5",
600 .init_setup = init_setup_svwks,
601 .init_chipset = init_chipset_svwks,
602 .init_hwif = init_hwif_svwks,
603 .init_dma = init_dma_svwks,
604 .channels = 2,
605 .autodma = AUTODMA,
606 .bootable = ON_BOARD,
607 },{ /* 2 */
608 .name = "SvrWks CSB6",
609 .init_setup = init_setup_csb6,
610 .init_chipset = init_chipset_svwks,
611 .init_hwif = init_hwif_svwks,
612 .init_dma = init_dma_svwks,
613 .channels = 2,
614 .autodma = AUTODMA,
615 .bootable = ON_BOARD,
616 },{ /* 3 */
617 .name = "SvrWks CSB6",
618 .init_setup = init_setup_csb6,
619 .init_chipset = init_chipset_svwks,
620 .init_hwif = init_hwif_svwks,
621 .init_dma = init_dma_svwks,
622 .channels = 1, /* 2 */
623 .autodma = AUTODMA,
624 .bootable = ON_BOARD,
84f57fbc
NS		 625 },{ /* 4 */
626 .name = "SvrWks HT1000",
627 .init_setup = init_setup_svwks,
628 .init_chipset = init_chipset_svwks,
629 .init_hwif = init_hwif_svwks,
630 .init_dma = init_dma_svwks,
631 .channels = 1, /* 2 */
632 .autodma = AUTODMA,
633 .bootable = ON_BOARD,
1da177e4
LT		 634 }
635};
636
637/**
638 * svwks_init_one - called when a OSB/CSB is found
639 * @dev: the svwks device
640 * @id: the matching pci id
641 *
642 * Called when the PCI registration layer (or the IDE initialization)
643 * finds a device matching our IDE device tables.
644 */
645
646static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
647{
648 ide_pci_device_t *d = &serverworks_chipsets[id->driver_data];
649
650 return d->init_setup(dev, d);
651}
652
653static struct pci_device_id svwks_pci_tbl[] = {
28a2a3f5
AC		 654 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
655 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
656 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
657 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
658 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1da177e4
LT		 659 { 0, },
660};
661MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
662
663static struct pci_driver driver = {
664 .name = "Serverworks_IDE",
665 .id_table = svwks_pci_tbl,
666 .probe = svwks_init_one,
667};
668
669static int svwks_ide_init(void)
670{
671 return ide_pci_register_driver(&driver);
672}
673
674module_init(svwks_ide_init);
675
676MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
677MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
678MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)