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Merge tag 'v3.10.90' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon_combios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
760285e7
DH		 27#include <drm/drmP.h>
28#include <drm/radeon_drm.h>
771fe6b9
JG		 29#include "radeon.h"
30#include "atom.h"
31
32#ifdef CONFIG_PPC_PMAC
33/* not sure which of these are needed */
34#include <asm/machdep.h>
35#include <asm/pmac_feature.h>
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#endif /* CONFIG_PPC_PMAC */
39
40/* from radeon_encoder.c */
41extern uint32_t
5137ee94
AD		 42radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
771fe6b9
JG		 44extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46/* from radeon_connector.c */
47extern void
48radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
b75fad06 52 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
771fe6b9
JG		 55
56/* from radeon_legacy_encoder.c */
57extern void
5137ee94 58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
771fe6b9
JG		 59 uint32_t supported_device);
60
61/* old legacy ATI BIOS routines */
62
63/* COMBIOS table offsets */
64enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
112};
113
114enum radeon_combios_ddc {
115 DDC_NONE_DETECTED,
116 DDC_MONID,
117 DDC_DVI,
118 DDC_VGA,
119 DDC_CRT2,
120 DDC_LCD,
121 DDC_GPIO,
122};
123
124enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
133};
134
135const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
144};
145
146static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
148{
149 struct radeon_device *rdev = dev->dev_private;
405a7cca 150 int rev, size;
771fe6b9
JG		 151 uint16_t offset = 0, check_offset;
152
03047cdf
MD		 153 if (!rdev->bios)
154 return 0;
155
771fe6b9
JG		 156 switch (table) {
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE:
405a7cca 159 check_offset = 0xc;
771fe6b9
JG		 160 break;
161 case COMBIOS_BIOS_SUPPORT_TABLE:
405a7cca 162 check_offset = 0x14;
771fe6b9
JG		 163 break;
164 case COMBIOS_DAC_PROGRAMMING_TABLE:
405a7cca 165 check_offset = 0x2a;
771fe6b9
JG		 166 break;
167 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
405a7cca 168 check_offset = 0x2c;
771fe6b9
JG		 169 break;
170 case COMBIOS_CRTC_INFO_TABLE:
405a7cca 171 check_offset = 0x2e;
771fe6b9
JG		 172 break;
173 case COMBIOS_PLL_INFO_TABLE:
405a7cca 174 check_offset = 0x30;
771fe6b9
JG		 175 break;
176 case COMBIOS_TV_INFO_TABLE:
405a7cca 177 check_offset = 0x32;
771fe6b9
JG		 178 break;
179 case COMBIOS_DFP_INFO_TABLE:
405a7cca 180 check_offset = 0x34;
771fe6b9
JG		 181 break;
182 case COMBIOS_HW_CONFIG_INFO_TABLE:
405a7cca 183 check_offset = 0x36;
771fe6b9
JG		 184 break;
185 case COMBIOS_MULTIMEDIA_INFO_TABLE:
405a7cca 186 check_offset = 0x38;
771fe6b9
JG		 187 break;
188 case COMBIOS_TV_STD_PATCH_TABLE:
405a7cca 189 check_offset = 0x3e;
771fe6b9
JG		 190 break;
191 case COMBIOS_LCD_INFO_TABLE:
405a7cca 192 check_offset = 0x40;
771fe6b9
JG		 193 break;
194 case COMBIOS_MOBILE_INFO_TABLE:
405a7cca 195 check_offset = 0x42;
771fe6b9
JG		 196 break;
197 case COMBIOS_PLL_INIT_TABLE:
405a7cca 198 check_offset = 0x46;
771fe6b9
JG		 199 break;
200 case COMBIOS_MEM_CONFIG_TABLE:
405a7cca 201 check_offset = 0x48;
771fe6b9
JG		 202 break;
203 case COMBIOS_SAVE_MASK_TABLE:
405a7cca 204 check_offset = 0x4a;
771fe6b9
JG		 205 break;
206 case COMBIOS_HARDCODED_EDID_TABLE:
405a7cca 207 check_offset = 0x4c;
771fe6b9
JG		 208 break;
209 case COMBIOS_ASIC_INIT_2_TABLE:
405a7cca 210 check_offset = 0x4e;
771fe6b9
JG		 211 break;
212 case COMBIOS_CONNECTOR_INFO_TABLE:
405a7cca 213 check_offset = 0x50;
771fe6b9
JG		 214 break;
215 case COMBIOS_DYN_CLK_1_TABLE:
405a7cca 216 check_offset = 0x52;
771fe6b9
JG		 217 break;
218 case COMBIOS_RESERVED_MEM_TABLE:
405a7cca 219 check_offset = 0x54;
771fe6b9
JG		 220 break;
221 case COMBIOS_EXT_TMDS_INFO_TABLE:
405a7cca 222 check_offset = 0x58;
771fe6b9
JG		 223 break;
224 case COMBIOS_MEM_CLK_INFO_TABLE:
405a7cca 225 check_offset = 0x5a;
771fe6b9
JG		 226 break;
227 case COMBIOS_EXT_DAC_INFO_TABLE:
405a7cca 228 check_offset = 0x5c;
771fe6b9
JG		 229 break;
230 case COMBIOS_MISC_INFO_TABLE:
405a7cca 231 check_offset = 0x5e;
771fe6b9
JG		 232 break;
233 case COMBIOS_CRT_INFO_TABLE:
405a7cca 234 check_offset = 0x60;
771fe6b9
JG		 235 break;
236 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
405a7cca 237 check_offset = 0x62;
771fe6b9
JG		 238 break;
239 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
405a7cca 240 check_offset = 0x64;
771fe6b9
JG		 241 break;
242 case COMBIOS_FAN_SPEED_INFO_TABLE:
405a7cca 243 check_offset = 0x66;
771fe6b9
JG		 244 break;
245 case COMBIOS_OVERDRIVE_INFO_TABLE:
405a7cca 246 check_offset = 0x68;
771fe6b9
JG		 247 break;
248 case COMBIOS_OEM_INFO_TABLE:
405a7cca 249 check_offset = 0x6a;
771fe6b9
JG		 250 break;
251 case COMBIOS_DYN_CLK_2_TABLE:
405a7cca 252 check_offset = 0x6c;
771fe6b9
JG		 253 break;
254 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
405a7cca 255 check_offset = 0x6e;
771fe6b9
JG		 256 break;
257 case COMBIOS_I2C_INFO_TABLE:
405a7cca 258 check_offset = 0x70;
771fe6b9
JG		 259 break;
260 /* relative offset tables */
261 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
262 check_offset =
263 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
264 if (check_offset) {
265 rev = RBIOS8(check_offset);
266 if (rev > 0) {
267 check_offset = RBIOS16(check_offset + 0x3);
268 if (check_offset)
269 offset = check_offset;
270 }
271 }
272 break;
273 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
274 check_offset =
275 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
276 if (check_offset) {
277 rev = RBIOS8(check_offset);
278 if (rev > 0) {
279 check_offset = RBIOS16(check_offset + 0x5);
280 if (check_offset)
281 offset = check_offset;
282 }
283 }
284 break;
285 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
286 check_offset =
287 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
288 if (check_offset) {
289 rev = RBIOS8(check_offset);
290 if (rev > 0) {
291 check_offset = RBIOS16(check_offset + 0x7);
292 if (check_offset)
293 offset = check_offset;
294 }
295 }
296 break;
297 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
298 check_offset =
299 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
300 if (check_offset) {
301 rev = RBIOS8(check_offset);
302 if (rev == 2) {
303 check_offset = RBIOS16(check_offset + 0x9);
304 if (check_offset)
305 offset = check_offset;
306 }
307 }
308 break;
309 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
310 check_offset =
311 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
312 if (check_offset) {
313 while (RBIOS8(check_offset++));
314 check_offset += 2;
315 if (check_offset)
316 offset = check_offset;
317 }
318 break;
319 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
320 check_offset =
321 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
322 if (check_offset) {
323 check_offset = RBIOS16(check_offset + 0x11);
324 if (check_offset)
325 offset = check_offset;
326 }
327 break;
328 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
329 check_offset =
330 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
331 if (check_offset) {
332 check_offset = RBIOS16(check_offset + 0x13);
333 if (check_offset)
334 offset = check_offset;
335 }
336 break;
337 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
338 check_offset =
339 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
340 if (check_offset) {
341 check_offset = RBIOS16(check_offset + 0x15);
342 if (check_offset)
343 offset = check_offset;
344 }
345 break;
346 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
347 check_offset =
348 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
349 if (check_offset) {
350 check_offset = RBIOS16(check_offset + 0x17);
351 if (check_offset)
352 offset = check_offset;
353 }
354 break;
355 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
356 check_offset =
357 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
358 if (check_offset) {
359 check_offset = RBIOS16(check_offset + 0x2);
360 if (check_offset)
361 offset = check_offset;
362 }
363 break;
364 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
365 check_offset =
366 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
367 if (check_offset) {
368 check_offset = RBIOS16(check_offset + 0x4);
369 if (check_offset)
370 offset = check_offset;
371 }
372 break;
373 default:
405a7cca 374 check_offset = 0;
771fe6b9
JG		 375 break;
376 }
377
405a7cca
MK		 378 size = RBIOS8(rdev->bios_header_start + 0x6);
379 /* check absolute offset tables */
380 if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size)
381 offset = RBIOS16(rdev->bios_header_start + check_offset);
771fe6b9 382
405a7cca 383 return offset;
771fe6b9
JG		 384}
385
3c537889
AD		 386bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
387{
fafcf94e 388 int edid_info, size;
3c537889 389 struct edid *edid;
7466f4cc 390 unsigned char *raw;
3c537889
AD		 391 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
392 if (!edid_info)
393 return false;
394
7466f4cc 395 raw = rdev->bios + edid_info;
fafcf94e
AD		 396 size = EDID_LENGTH * (raw[0x7e] + 1);
397 edid = kmalloc(size, GFP_KERNEL);
3c537889
AD		 398 if (edid == NULL)
399 return false;
400
fafcf94e 401 memcpy((unsigned char *)edid, raw, size);
3c537889
AD		 402
403 if (!drm_edid_is_valid(edid)) {
404 kfree(edid);
405 return false;
406 }
407
408 rdev->mode_info.bios_hardcoded_edid = edid;
fafcf94e 409 rdev->mode_info.bios_hardcoded_edid_size = size;
3c537889
AD		 410 return true;
411}
412
c324acd5 413/* this is used for atom LCDs as well */
3c537889 414struct edid *
c324acd5 415radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
3c537889 416{
fafcf94e
AD		 417 struct edid *edid;
418
419 if (rdev->mode_info.bios_hardcoded_edid) {
420 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
421 if (edid) {
422 memcpy((unsigned char *)edid,
423 (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
424 rdev->mode_info.bios_hardcoded_edid_size);
425 return edid;
426 }
427 }
3c537889
AD		 428 return NULL;
429}
430
6a93cb25 431static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
179e8078
AD		 432 enum radeon_combios_ddc ddc,
433 u32 clk_mask,
434 u32 data_mask)
771fe6b9
JG		 435{
436 struct radeon_i2c_bus_rec i2c;
179e8078
AD		 437 int ddc_line = 0;
438
439 /* ddc id = mask reg
440 * DDC_NONE_DETECTED = none
441 * DDC_DVI = RADEON_GPIO_DVI_DDC
442 * DDC_VGA = RADEON_GPIO_VGA_DDC
443 * DDC_LCD = RADEON_GPIOPAD_MASK
444 * DDC_GPIO = RADEON_MDGPIO_MASK
508c8d60 445 * r1xx
179e8078
AD		 446 * DDC_MONID = RADEON_GPIO_MONID
447 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
508c8d60 448 * r200
179e8078
AD		 449 * DDC_MONID = RADEON_GPIO_MONID
450 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
508c8d60
AD		 451 * r300/r350
452 * DDC_MONID = RADEON_GPIO_DVI_DDC
453 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
454 * rv2xx/rv3xx
455 * DDC_MONID = RADEON_GPIO_MONID
456 * DDC_CRT2 = RADEON_GPIO_MONID
179e8078
AD		 457 * rs3xx/rs4xx
458 * DDC_MONID = RADEON_GPIOPAD_MASK
459 * DDC_CRT2 = RADEON_GPIO_MONID
460 */
461 switch (ddc) {
462 case DDC_NONE_DETECTED:
463 default:
464 ddc_line = 0;
465 break;
466 case DDC_DVI:
467 ddc_line = RADEON_GPIO_DVI_DDC;
468 break;
469 case DDC_VGA:
470 ddc_line = RADEON_GPIO_VGA_DDC;
471 break;
472 case DDC_LCD:
473 ddc_line = RADEON_GPIOPAD_MASK;
474 break;
475 case DDC_GPIO:
476 ddc_line = RADEON_MDGPIO_MASK;
477 break;
478 case DDC_MONID:
479 if (rdev->family == CHIP_RS300 ||
480 rdev->family == CHIP_RS400 ||
481 rdev->family == CHIP_RS480)
482 ddc_line = RADEON_GPIOPAD_MASK;
508c8d60 483 else if (rdev->family == CHIP_R300 ||
776f2b7c 484 rdev->family == CHIP_R350) {
508c8d60 485 ddc_line = RADEON_GPIO_DVI_DDC;
776f2b7c
AD		 486 ddc = DDC_DVI;
487 } else
179e8078
AD		 488 ddc_line = RADEON_GPIO_MONID;
489 break;
490 case DDC_CRT2:
508c8d60
AD		 491 if (rdev->family == CHIP_R200 ||
492 rdev->family == CHIP_R300 ||
776f2b7c 493 rdev->family == CHIP_R350) {
179e8078 494 ddc_line = RADEON_GPIO_DVI_DDC;
776f2b7c
AD		 495 ddc = DDC_DVI;
496 } else if (rdev->family == CHIP_RS300 ||
497 rdev->family == CHIP_RS400 ||
498 rdev->family == CHIP_RS480)
508c8d60 499 ddc_line = RADEON_GPIO_MONID;
776f2b7c
AD		 500 else if (rdev->family >= CHIP_RV350) {
501 ddc_line = RADEON_GPIO_MONID;
502 ddc = DDC_MONID;
503 } else
179e8078
AD		 504 ddc_line = RADEON_GPIO_CRT2_DDC;
505 break;
506 }
771fe6b9 507
6a93cb25
AD		 508 if (ddc_line == RADEON_GPIOPAD_MASK) {
509 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
510 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
511 i2c.a_clk_reg = RADEON_GPIOPAD_A;
512 i2c.a_data_reg = RADEON_GPIOPAD_A;
513 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
514 i2c.en_data_reg = RADEON_GPIOPAD_EN;
515 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
516 i2c.y_data_reg = RADEON_GPIOPAD_Y;
517 } else if (ddc_line == RADEON_MDGPIO_MASK) {
518 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
519 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
520 i2c.a_clk_reg = RADEON_MDGPIO_A;
521 i2c.a_data_reg = RADEON_MDGPIO_A;
522 i2c.en_clk_reg = RADEON_MDGPIO_EN;
523 i2c.en_data_reg = RADEON_MDGPIO_EN;
524 i2c.y_clk_reg = RADEON_MDGPIO_Y;
525 i2c.y_data_reg = RADEON_MDGPIO_Y;
771fe6b9
JG		 526 } else {
527 i2c.mask_clk_reg = ddc_line;
528 i2c.mask_data_reg = ddc_line;
529 i2c.a_clk_reg = ddc_line;
530 i2c.a_data_reg = ddc_line;
9b9fe724
AD		 531 i2c.en_clk_reg = ddc_line;
532 i2c.en_data_reg = ddc_line;
533 i2c.y_clk_reg = ddc_line;
534 i2c.y_data_reg = ddc_line;
771fe6b9
JG		 535 }
536
179e8078 537 if (clk_mask && data_mask) {
be663057 538 /* system specific masks */
179e8078
AD		 539 i2c.mask_clk_mask = clk_mask;
540 i2c.mask_data_mask = data_mask;
541 i2c.a_clk_mask = clk_mask;
542 i2c.a_data_mask = data_mask;
543 i2c.en_clk_mask = clk_mask;
544 i2c.en_data_mask = data_mask;
545 i2c.y_clk_mask = clk_mask;
546 i2c.y_data_mask = data_mask;
be663057
AD		 547 } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
548 (ddc_line == RADEON_MDGPIO_MASK)) {
549 /* default gpiopad masks */
550 i2c.mask_clk_mask = (0x20 << 8);
551 i2c.mask_data_mask = 0x80;
552 i2c.a_clk_mask = (0x20 << 8);
553 i2c.a_data_mask = 0x80;
554 i2c.en_clk_mask = (0x20 << 8);
555 i2c.en_data_mask = 0x80;
556 i2c.y_clk_mask = (0x20 << 8);
557 i2c.y_data_mask = 0x80;
179e8078 558 } else {
be663057 559 /* default masks for ddc pads */
286e0c94
JD		 560 i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
561 i2c.mask_data_mask = RADEON_GPIO_MASK_0;
179e8078
AD		 562 i2c.a_clk_mask = RADEON_GPIO_A_1;
563 i2c.a_data_mask = RADEON_GPIO_A_0;
564 i2c.en_clk_mask = RADEON_GPIO_EN_1;
565 i2c.en_data_mask = RADEON_GPIO_EN_0;
566 i2c.y_clk_mask = RADEON_GPIO_Y_1;
567 i2c.y_data_mask = RADEON_GPIO_Y_0;
568 }
569
40bacf16
AD		 570 switch (rdev->family) {
571 case CHIP_R100:
572 case CHIP_RV100:
573 case CHIP_RS100:
574 case CHIP_RV200:
575 case CHIP_RS200:
576 case CHIP_RS300:
577 switch (ddc_line) {
578 case RADEON_GPIO_DVI_DDC:
b28ea411 579 i2c.hw_capable = true;
40bacf16
AD		 580 break;
581 default:
582 i2c.hw_capable = false;
583 break;
584 }
585 break;
586 case CHIP_R200:
587 switch (ddc_line) {
588 case RADEON_GPIO_DVI_DDC:
589 case RADEON_GPIO_MONID:
590 i2c.hw_capable = true;
591 break;
592 default:
593 i2c.hw_capable = false;
594 break;
595 }
596 break;
597 case CHIP_RV250:
598 case CHIP_RV280:
599 switch (ddc_line) {
600 case RADEON_GPIO_VGA_DDC:
601 case RADEON_GPIO_DVI_DDC:
602 case RADEON_GPIO_CRT2_DDC:
603 i2c.hw_capable = true;
604 break;
605 default:
606 i2c.hw_capable = false;
607 break;
608 }
609 break;
610 case CHIP_R300:
611 case CHIP_R350:
612 switch (ddc_line) {
613 case RADEON_GPIO_VGA_DDC:
614 case RADEON_GPIO_DVI_DDC:
615 i2c.hw_capable = true;
616 break;
617 default:
618 i2c.hw_capable = false;
619 break;
620 }
621 break;
622 case CHIP_RV350:
623 case CHIP_RV380:
624 case CHIP_RS400:
625 case CHIP_RS480:
6a93cb25
AD		 626 switch (ddc_line) {
627 case RADEON_GPIO_VGA_DDC:
628 case RADEON_GPIO_DVI_DDC:
629 i2c.hw_capable = true;
630 break;
631 case RADEON_GPIO_MONID:
632 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
633 * reliably on some pre-r4xx hardware; not sure why.
634 */
635 i2c.hw_capable = false;
636 break;
637 default:
638 i2c.hw_capable = false;
639 break;
640 }
40bacf16
AD		 641 break;
642 default:
643 i2c.hw_capable = false;
644 break;
6a93cb25
AD		 645 }
646 i2c.mm_i2c = false;
f376b94f 647
179e8078 648 i2c.i2c_id = ddc;
8e36ed00 649 i2c.hpd = RADEON_HPD_NONE;
6a93cb25 650
771fe6b9
JG		 651 if (ddc_line)
652 i2c.valid = true;
653 else
654 i2c.valid = false;
655
656 return i2c;
657}
658
3d61bd42
AD		 659static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
660{
661 struct drm_device *dev = rdev->ddev;
662 struct radeon_i2c_bus_rec i2c;
663 u16 offset;
664 u8 id, blocks, clk, data;
665 int i;
666
667 i2c.valid = false;
668
669 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
670 if (offset) {
671 blocks = RBIOS8(offset + 2);
672 for (i = 0; i < blocks; i++) {
673 id = RBIOS8(offset + 3 + (i * 5) + 0);
674 if (id == 136) {
675 clk = RBIOS8(offset + 3 + (i * 5) + 3);
676 data = RBIOS8(offset + 3 + (i * 5) + 4);
677 /* gpiopad */
678 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
679 (1 << clk), (1 << data));
680 break;
681 }
682 }
683 }
684 return i2c;
685}
686
f376b94f
AD		 687void radeon_combios_i2c_init(struct radeon_device *rdev)
688{
689 struct drm_device *dev = rdev->ddev;
690 struct radeon_i2c_bus_rec i2c;
691
508c8d60
AD		 692 /* actual hw pads
693 * r1xx/rs2xx/rs3xx
694 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
695 * r200
696 * 0x60, 0x64, 0x68, mm
697 * r300/r350
698 * 0x60, 0x64, mm
699 * rv2xx/rv3xx/rs4xx
700 * 0x60, 0x64, 0x68, gpiopads, mm
701 */
f376b94f 702
508c8d60 703 /* 0x60 */
179e8078
AD		 704 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
705 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
508c8d60 706 /* 0x64 */
179e8078
AD		 707 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
708 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
f376b94f 709
508c8d60 710 /* mm i2c */
f376b94f
AD		 711 i2c.valid = true;
712 i2c.hw_capable = true;
713 i2c.mm_i2c = true;
179e8078
AD		 714 i2c.i2c_id = 0xa0;
715 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
716
508c8d60
AD		 717 if (rdev->family == CHIP_R300 ||
718 rdev->family == CHIP_R350) {
719 /* only 2 sw i2c pads */
720 } else if (rdev->family == CHIP_RS300 ||
721 rdev->family == CHIP_RS400 ||
722 rdev->family == CHIP_RS480) {
508c8d60 723 /* 0x68 */
179e8078
AD		 724 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
725 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
726
3d61bd42
AD		 727 /* gpiopad */
728 i2c = radeon_combios_get_i2c_info_from_table(rdev);
729 if (i2c.valid)
730 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
6dd66633
AD		 731 } else if ((rdev->family == CHIP_R200) ||
732 (rdev->family >= CHIP_R300)) {
508c8d60 733 /* 0x68 */
179e8078
AD		 734 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
735 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
736 } else {
508c8d60 737 /* 0x68 */
179e8078
AD		 738 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
739 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
508c8d60 740 /* 0x6c */
179e8078
AD		 741 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
742 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
743 }
f376b94f
AD		 744}
745
771fe6b9
JG		 746bool radeon_combios_get_clock_info(struct drm_device *dev)
747{
748 struct radeon_device *rdev = dev->dev_private;
749 uint16_t pll_info;
750 struct radeon_pll *p1pll = &rdev->clock.p1pll;
751 struct radeon_pll *p2pll = &rdev->clock.p2pll;
752 struct radeon_pll *spll = &rdev->clock.spll;
753 struct radeon_pll *mpll = &rdev->clock.mpll;
754 int8_t rev;
755 uint16_t sclk, mclk;
756
771fe6b9
JG		 757 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
758 if (pll_info) {
759 rev = RBIOS8(pll_info);
760
761 /* pixel clocks */
762 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
763 p1pll->reference_div = RBIOS16(pll_info + 0x10);
764 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
765 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
86cb2bbf
AD		 766 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
767 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
771fe6b9
JG		 768
769 if (rev > 9) {
770 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
771 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
772 } else {
773 p1pll->pll_in_min = 40;
774 p1pll->pll_in_max = 500;
775 }
776 *p2pll = *p1pll;
777
778 /* system clock */
779 spll->reference_freq = RBIOS16(pll_info + 0x1a);
780 spll->reference_div = RBIOS16(pll_info + 0x1c);
781 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
782 spll->pll_out_max = RBIOS32(pll_info + 0x22);
783
784 if (rev > 10) {
785 spll->pll_in_min = RBIOS32(pll_info + 0x48);
786 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
787 } else {
788 /* ??? */
789 spll->pll_in_min = 40;
790 spll->pll_in_max = 500;
791 }
792
793 /* memory clock */
794 mpll->reference_freq = RBIOS16(pll_info + 0x26);
795 mpll->reference_div = RBIOS16(pll_info + 0x28);
796 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
797 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
798
799 if (rev > 10) {
800 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
801 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
802 } else {
803 /* ??? */
804 mpll->pll_in_min = 40;
805 mpll->pll_in_max = 500;
806 }
807
808 /* default sclk/mclk */
809 sclk = RBIOS16(pll_info + 0xa);
810 mclk = RBIOS16(pll_info + 0x8);
811 if (sclk == 0)
812 sclk = 200 * 100;
813 if (mclk == 0)
814 mclk = 200 * 100;
815
816 rdev->clock.default_sclk = sclk;
817 rdev->clock.default_mclk = mclk;
818
b20f9bef
AD		 819 if (RBIOS32(pll_info + 0x16))
820 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
821 else
822 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
823
771fe6b9
JG		 824 return true;
825 }
826 return false;
827}
828
06b6476d
AD		 829bool radeon_combios_sideport_present(struct radeon_device *rdev)
830{
831 struct drm_device *dev = rdev->ddev;
832 u16 igp_info;
833
4c70b2ea
AD		 834 /* sideport is AMD only */
835 if (rdev->family == CHIP_RS400)
836 return false;
837
06b6476d
AD		 838 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
839
840 if (igp_info) {
841 if (RBIOS16(igp_info + 0x4))
842 return true;
843 }
844 return false;
845}
846
246263cc
AD		 847static const uint32_t default_primarydac_adj[CHIP_LAST] = {
848 0x00000808, /* r100 */
849 0x00000808, /* rv100 */
850 0x00000808, /* rs100 */
851 0x00000808, /* rv200 */
852 0x00000808, /* rs200 */
853 0x00000808, /* r200 */
854 0x00000808, /* rv250 */
855 0x00000000, /* rs300 */
856 0x00000808, /* rv280 */
857 0x00000808, /* r300 */
858 0x00000808, /* r350 */
859 0x00000808, /* rv350 */
860 0x00000808, /* rv380 */
861 0x00000808, /* r420 */
862 0x00000808, /* r423 */
863 0x00000808, /* rv410 */
864 0x00000000, /* rs400 */
865 0x00000000, /* rs480 */
866};
867
868static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
869 struct radeon_encoder_primary_dac *p_dac)
870{
871 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
872 return;
873}
874
771fe6b9
JG		 875struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
876 radeon_encoder
877 *encoder)
878{
879 struct drm_device *dev = encoder->base.dev;
880 struct radeon_device *rdev = dev->dev_private;
881 uint16_t dac_info;
882 uint8_t rev, bg, dac;
883 struct radeon_encoder_primary_dac *p_dac = NULL;
246263cc 884 int found = 0;
771fe6b9 885
246263cc
AD		 886 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
887 GFP_KERNEL);
888
889 if (!p_dac)
771fe6b9
JG		 890 return NULL;
891
892 /* check CRT table */
893 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
894 if (dac_info) {
771fe6b9
JG		 895 rev = RBIOS8(dac_info) & 0x3;
896 if (rev < 2) {
897 bg = RBIOS8(dac_info + 0x2) & 0xf;
898 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
899 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
900 } else {
901 bg = RBIOS8(dac_info + 0x2) & 0xf;
902 dac = RBIOS8(dac_info + 0x3) & 0xf;
903 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
904 }
d54b22e5
AD		 905 /* if the values are zeros, use the table */
906 if ((dac == 0) || (bg == 0))
907 found = 0;
908 else
3a89b4a9 909 found = 1;
771fe6b9
JG		 910 }
911
e8fc4137 912 /* quirks */
d19ccc40
OZ		 913 /* Radeon 7000 (RV100) */
914 if (((dev->pdev->device == 0x5159) &&
915 (dev->pdev->subsystem_vendor == 0x174B) &&
916 (dev->pdev->subsystem_device == 0x7c28)) ||
e8fc4137 917 /* Radeon 9100 (R200) */
d19ccc40 918 ((dev->pdev->device == 0x514D) &&
e8fc4137 919 (dev->pdev->subsystem_vendor == 0x174B) &&
d19ccc40 920 (dev->pdev->subsystem_device == 0x7149))) {
e8fc4137
AD		 921 /* vbios value is bad, use the default */
922 found = 0;
923 }
924
246263cc
AD		 925 if (!found) /* fallback to defaults */
926 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
927
771fe6b9
JG		 928 return p_dac;
929}
930
d79766fa
AD		 931enum radeon_tv_std
932radeon_combios_get_tv_info(struct radeon_device *rdev)
771fe6b9 933{
d79766fa 934 struct drm_device *dev = rdev->ddev;
771fe6b9
JG		 935 uint16_t tv_info;
936 enum radeon_tv_std tv_std = TV_STD_NTSC;
937
938 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
939 if (tv_info) {
940 if (RBIOS8(tv_info + 6) == 'T') {
941 switch (RBIOS8(tv_info + 7) & 0xf) {
942 case 1:
943 tv_std = TV_STD_NTSC;
40f76d81 944 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
771fe6b9
JG		 945 break;
946 case 2:
947 tv_std = TV_STD_PAL;
40f76d81 948 DRM_DEBUG_KMS("Default TV standard: PAL\n");
771fe6b9
JG		 949 break;
950 case 3:
951 tv_std = TV_STD_PAL_M;
40f76d81 952 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
771fe6b9
JG		 953 break;
954 case 4:
955 tv_std = TV_STD_PAL_60;
40f76d81 956 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
771fe6b9
JG		 957 break;
958 case 5:
959 tv_std = TV_STD_NTSC_J;
40f76d81 960 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
771fe6b9
JG		 961 break;
962 case 6:
963 tv_std = TV_STD_SCART_PAL;
40f76d81 964 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
771fe6b9
JG		 965 break;
966 default:
967 tv_std = TV_STD_NTSC;
40f76d81 968 DRM_DEBUG_KMS
771fe6b9
JG		 969 ("Unknown TV standard; defaulting to NTSC\n");
970 break;
971 }
972
973 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
974 case 0:
40f76d81 975 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
771fe6b9
JG		 976 break;
977 case 1:
40f76d81 978 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
771fe6b9
JG		 979 break;
980 case 2:
40f76d81 981 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
771fe6b9
JG		 982 break;
983 case 3:
40f76d81 984 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
771fe6b9
JG		 985 break;
986 default:
987 break;
988 }
989 }
990 }
991 return tv_std;
992}
993
994static const uint32_t default_tvdac_adj[CHIP_LAST] = {
995 0x00000000, /* r100 */
996 0x00280000, /* rv100 */
997 0x00000000, /* rs100 */
998 0x00880000, /* rv200 */
999 0x00000000, /* rs200 */
1000 0x00000000, /* r200 */
1001 0x00770000, /* rv250 */
1002 0x00290000, /* rs300 */
1003 0x00560000, /* rv280 */
1004 0x00780000, /* r300 */
1005 0x00770000, /* r350 */
1006 0x00780000, /* rv350 */
1007 0x00780000, /* rv380 */
1008 0x01080000, /* r420 */
1009 0x01080000, /* r423 */
1010 0x01080000, /* rv410 */
1011 0x00780000, /* rs400 */
1012 0x00780000, /* rs480 */
1013};
1014
6a719e05
DA		 1015static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1016 struct radeon_encoder_tv_dac *tv_dac)
771fe6b9 1017{
771fe6b9
JG		 1018 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1019 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1020 tv_dac->ps2_tvdac_adj = 0x00880000;
1021 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1022 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 1023 return;
771fe6b9
JG		 1024}
1025
1026struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1027 radeon_encoder
1028 *encoder)
1029{
1030 struct drm_device *dev = encoder->base.dev;
1031 struct radeon_device *rdev = dev->dev_private;
1032 uint16_t dac_info;
1033 uint8_t rev, bg, dac;
1034 struct radeon_encoder_tv_dac *tv_dac = NULL;
6a719e05
DA		 1035 int found = 0;
1036
1037 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1038 if (!tv_dac)
1039 return NULL;
771fe6b9 1040
771fe6b9
JG		 1041 /* first check TV table */
1042 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1043 if (dac_info) {
771fe6b9
JG		 1044 rev = RBIOS8(dac_info + 0x3);
1045 if (rev > 4) {
1046 bg = RBIOS8(dac_info + 0xc) & 0xf;
1047 dac = RBIOS8(dac_info + 0xd) & 0xf;
1048 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1049
1050 bg = RBIOS8(dac_info + 0xe) & 0xf;
1051 dac = RBIOS8(dac_info + 0xf) & 0xf;
1052 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1053
1054 bg = RBIOS8(dac_info + 0x10) & 0xf;
1055 dac = RBIOS8(dac_info + 0x11) & 0xf;
1056 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
3a89b4a9
AD		 1057 /* if the values are all zeros, use the table */
1058 if (tv_dac->ps2_tvdac_adj)
1059 found = 1;
771fe6b9
JG		 1060 } else if (rev > 1) {
1061 bg = RBIOS8(dac_info + 0xc) & 0xf;
1062 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1063 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1064
1065 bg = RBIOS8(dac_info + 0xd) & 0xf;
1066 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1067 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1068
1069 bg = RBIOS8(dac_info + 0xe) & 0xf;
1070 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1071 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
3a89b4a9
AD		 1072 /* if the values are all zeros, use the table */
1073 if (tv_dac->ps2_tvdac_adj)
1074 found = 1;
771fe6b9 1075 }
d79766fa 1076 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
6a719e05
DA		 1077 }
1078 if (!found) {
771fe6b9
JG		 1079 /* then check CRT table */
1080 dac_info =
1081 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1082 if (dac_info) {
771fe6b9
JG		 1083 rev = RBIOS8(dac_info) & 0x3;
1084 if (rev < 2) {
1085 bg = RBIOS8(dac_info + 0x3) & 0xf;
1086 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1087 tv_dac->ps2_tvdac_adj =
1088 (bg << 16) | (dac << 20);
1089 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1090 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
3a89b4a9
AD		 1091 /* if the values are all zeros, use the table */
1092 if (tv_dac->ps2_tvdac_adj)
1093 found = 1;
771fe6b9
JG		 1094 } else {
1095 bg = RBIOS8(dac_info + 0x4) & 0xf;
1096 dac = RBIOS8(dac_info + 0x5) & 0xf;
1097 tv_dac->ps2_tvdac_adj =
1098 (bg << 16) | (dac << 20);
1099 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1100 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
3a89b4a9
AD		 1101 /* if the values are all zeros, use the table */
1102 if (tv_dac->ps2_tvdac_adj)
1103 found = 1;
771fe6b9 1104 }
6fe7ac3f
AD		 1105 } else {
1106 DRM_INFO("No TV DAC info found in BIOS\n");
771fe6b9
JG		 1107 }
1108 }
1109
6a719e05
DA		 1110 if (!found) /* fallback to defaults */
1111 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1112
771fe6b9
JG		 1113 return tv_dac;
1114}
1115
1116static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1117 radeon_device
1118 *rdev)
1119{
1120 struct radeon_encoder_lvds *lvds = NULL;
1121 uint32_t fp_vert_stretch, fp_horz_stretch;
1122 uint32_t ppll_div_sel, ppll_val;
8b5c7444 1123 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
771fe6b9
JG		 1124
1125 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1126
1127 if (!lvds)
1128 return NULL;
1129
1130 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1131 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1132
8b5c7444
MD		 1133 /* These should be fail-safe defaults, fingers crossed */
1134 lvds->panel_pwr_delay = 200;
1135 lvds->panel_vcc_delay = 2000;
1136
1137 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1138 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1139 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1140
771fe6b9 1141 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
de2103e4 1142 lvds->native_mode.vdisplay =
771fe6b9
JG		 1143 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1144 RADEON_VERT_PANEL_SHIFT) + 1;
1145 else
de2103e4 1146 lvds->native_mode.vdisplay =
771fe6b9
JG		 1147 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1148
1149 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
de2103e4 1150 lvds->native_mode.hdisplay =
771fe6b9
JG		 1151 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1152 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1153 else
de2103e4 1154 lvds->native_mode.hdisplay =
771fe6b9
JG		 1155 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1156
de2103e4
AD		 1157 if ((lvds->native_mode.hdisplay < 640) ||
1158 (lvds->native_mode.vdisplay < 480)) {
1159 lvds->native_mode.hdisplay = 640;
1160 lvds->native_mode.vdisplay = 480;
771fe6b9
JG		 1161 }
1162
1163 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1164 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1165 if ((ppll_val & 0x000707ff) == 0x1bb)
1166 lvds->use_bios_dividers = false;
1167 else {
1168 lvds->panel_ref_divider =
1169 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1170 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1171 lvds->panel_fb_divider = ppll_val & 0x7ff;
1172
1173 if ((lvds->panel_ref_divider != 0) &&
1174 (lvds->panel_fb_divider > 3))
1175 lvds->use_bios_dividers = true;
1176 }
1177 lvds->panel_vcc_delay = 200;
1178
1179 DRM_INFO("Panel info derived from registers\n");
de2103e4
AD		 1180 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1181 lvds->native_mode.vdisplay);
771fe6b9
JG		 1182
1183 return lvds;
1184}
1185
1186struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1187 *encoder)
1188{
1189 struct drm_device *dev = encoder->base.dev;
1190 struct radeon_device *rdev = dev->dev_private;
1191 uint16_t lcd_info;
1192 uint32_t panel_setup;
1193 char stmp[30];
1194 int tmp, i;
1195 struct radeon_encoder_lvds *lvds = NULL;
1196
771fe6b9
JG		 1197 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1198
1199 if (lcd_info) {
1200 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1201
1202 if (!lvds)
1203 return NULL;
1204
1205 for (i = 0; i < 24; i++)
1206 stmp[i] = RBIOS8(lcd_info + i + 1);
1207 stmp[24] = 0;
1208
1209 DRM_INFO("Panel ID String: %s\n", stmp);
1210
de2103e4
AD		 1211 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1212 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
771fe6b9 1213
de2103e4
AD		 1214 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1215 lvds->native_mode.vdisplay);
771fe6b9
JG		 1216
1217 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
94cf6434 1218 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
771fe6b9
JG		 1219
1220 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1221 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1222 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1223
1224 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1225 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1226 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1227 if ((lvds->panel_ref_divider != 0) &&
1228 (lvds->panel_fb_divider > 3))
1229 lvds->use_bios_dividers = true;
1230
1231 panel_setup = RBIOS32(lcd_info + 0x39);
1232 lvds->lvds_gen_cntl = 0xff00;
1233 if (panel_setup & 0x1)
1234 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1235
1236 if ((panel_setup >> 4) & 0x1)
1237 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1238
1239 switch ((panel_setup >> 8) & 0x7) {
1240 case 0:
1241 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1242 break;
1243 case 1:
1244 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1245 break;
1246 case 2:
1247 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1248 break;
1249 default:
1250 break;
1251 }
1252
1253 if ((panel_setup >> 16) & 0x1)
1254 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1255
1256 if ((panel_setup >> 17) & 0x1)
1257 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1258
1259 if ((panel_setup >> 18) & 0x1)
1260 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1261
1262 if ((panel_setup >> 23) & 0x1)
1263 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1264
1265 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1266
1267 for (i = 0; i < 32; i++) {
1268 tmp = RBIOS16(lcd_info + 64 + i * 2);
1269 if (tmp == 0)
1270 break;
1271
de2103e4 1272 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
68b61a7f 1273 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
2f1a904e
AD		 1274 u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1275
1276 if (hss > lvds->native_mode.hdisplay)
1277 hss = (10 - 1) * 8;
1278
68b61a7f
AD		 1279 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1280 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1281 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
2f1a904e 1282 hss;
68b61a7f
AD		 1283 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1284 (RBIOS8(tmp + 23) * 8);
1285
1286 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1287 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1288 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1289 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1290 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1291 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
de2103e4
AD		 1292
1293 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
771fe6b9 1294 lvds->native_mode.flags = 0;
de2103e4
AD		 1295 /* set crtc values */
1296 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1297
771fe6b9
JG		 1298 }
1299 }
6fe7ac3f 1300 } else {
771fe6b9 1301 DRM_INFO("No panel info found in BIOS\n");
8dfaa8a7 1302 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
6fe7ac3f 1303 }
03047cdf 1304
8dfaa8a7
MD		 1305 if (lvds)
1306 encoder->native_mode = lvds->native_mode;
771fe6b9
JG		 1307 return lvds;
1308}
1309
1310static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1311 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1312 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1313 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1314 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1315 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1316 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1317 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1318 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1319 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1320 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1321 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1322 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1323 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1324 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1325 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1326 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
fcec570b
AD		 1327 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1328 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
771fe6b9
JG		 1329};
1330
445282db
DA		 1331bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1332 struct radeon_encoder_int_tmds *tmds)
771fe6b9 1333{
445282db
DA		 1334 struct drm_device *dev = encoder->base.dev;
1335 struct radeon_device *rdev = dev->dev_private;
771fe6b9 1336 int i;
771fe6b9
JG		 1337
1338 for (i = 0; i < 4; i++) {
1339 tmds->tmds_pll[i].value =
445282db 1340 default_tmds_pll[rdev->family][i].value;
771fe6b9
JG		 1341 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1342 }
1343
445282db 1344 return true;
771fe6b9
JG		 1345}
1346
445282db
DA		 1347bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1348 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1349{
1350 struct drm_device *dev = encoder->base.dev;
1351 struct radeon_device *rdev = dev->dev_private;
1352 uint16_t tmds_info;
1353 int i, n;
1354 uint8_t ver;
771fe6b9 1355
771fe6b9
JG		 1356 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1357
1358 if (tmds_info) {
771fe6b9 1359 ver = RBIOS8(tmds_info);
40f76d81 1360 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
771fe6b9
JG		 1361 if (ver == 3) {
1362 n = RBIOS8(tmds_info + 5) + 1;
1363 if (n > 4)
1364 n = 4;
1365 for (i = 0; i < n; i++) {
1366 tmds->tmds_pll[i].value =
1367 RBIOS32(tmds_info + i * 10 + 0x08);
1368 tmds->tmds_pll[i].freq =
1369 RBIOS16(tmds_info + i * 10 + 0x10);
d9fdaafb 1370 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
771fe6b9
JG		 1371 tmds->tmds_pll[i].freq,
1372 tmds->tmds_pll[i].value);
1373 }
1374 } else if (ver == 4) {
1375 int stride = 0;
1376 n = RBIOS8(tmds_info + 5) + 1;
1377 if (n > 4)
1378 n = 4;
1379 for (i = 0; i < n; i++) {
1380 tmds->tmds_pll[i].value =
1381 RBIOS32(tmds_info + stride + 0x08);
1382 tmds->tmds_pll[i].freq =
1383 RBIOS16(tmds_info + stride + 0x10);
1384 if (i == 0)
1385 stride += 10;
1386 else
1387 stride += 6;
d9fdaafb 1388 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
771fe6b9
JG		 1389 tmds->tmds_pll[i].freq,
1390 tmds->tmds_pll[i].value);
1391 }
1392 }
fcec570b 1393 } else {
771fe6b9 1394 DRM_INFO("No TMDS info found in BIOS\n");
fcec570b
AD		 1395 return false;
1396 }
445282db
DA		 1397 return true;
1398}
1399
fcec570b
AD		 1400bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1401 struct radeon_encoder_ext_tmds *tmds)
445282db 1402{
fcec570b
AD		 1403 struct drm_device *dev = encoder->base.dev;
1404 struct radeon_device *rdev = dev->dev_private;
1405 struct radeon_i2c_bus_rec i2c_bus;
445282db 1406
fcec570b 1407 /* default for macs */
179e8078 1408 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
f376b94f 1409 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
445282db 1410
fcec570b
AD		 1411 /* XXX some macs have duallink chips */
1412 switch (rdev->mode_info.connector_table) {
1413 case CT_POWERBOOK_EXTERNAL:
1414 case CT_MINI_EXTERNAL:
1415 default:
1416 tmds->dvo_chip = DVO_SIL164;
1417 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1418 break;
1419 }
445282db 1420
fcec570b 1421 return true;
771fe6b9
JG		 1422}
1423
fcec570b
AD		 1424bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1425 struct radeon_encoder_ext_tmds *tmds)
771fe6b9
JG		 1426{
1427 struct drm_device *dev = encoder->base.dev;
1428 struct radeon_device *rdev = dev->dev_private;
fcec570b 1429 uint16_t offset;
179e8078 1430 uint8_t ver;
fcec570b
AD		 1431 enum radeon_combios_ddc gpio;
1432 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9 1433
fcec570b
AD		 1434 tmds->i2c_bus = NULL;
1435 if (rdev->flags & RADEON_IS_IGP) {
179e8078
AD		 1436 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1437 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1438 tmds->dvo_chip = DVO_SIL164;
1439 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
fcec570b
AD		 1440 } else {
1441 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1442 if (offset) {
1443 ver = RBIOS8(offset);
40f76d81 1444 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
fcec570b
AD		 1445 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1446 tmds->slave_addr >>= 1; /* 7 bit addressing */
1447 gpio = RBIOS8(offset + 4 + 3);
179e8078
AD		 1448 if (gpio == DDC_LCD) {
1449 /* MM i2c */
40bacf16
AD		 1450 i2c_bus.valid = true;
1451 i2c_bus.hw_capable = true;
1452 i2c_bus.mm_i2c = true;
179e8078
AD		 1453 i2c_bus.i2c_id = 0xa0;
1454 } else
1455 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1456 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
fcec570b 1457 }
771fe6b9 1458 }
fcec570b
AD		 1459
1460 if (!tmds->i2c_bus) {
1461 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1462 return false;
1463 }
1464
1465 return true;
771fe6b9
JG		 1466}
1467
1468bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1469{
1470 struct radeon_device *rdev = dev->dev_private;
1471 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 1472 struct radeon_hpd hpd;
771fe6b9
JG		 1473
1474 rdev->mode_info.connector_table = radeon_connector_table;
1475 if (rdev->mode_info.connector_table == CT_NONE) {
1476#ifdef CONFIG_PPC_PMAC
71a157e8 1477 if (of_machine_is_compatible("PowerBook3,3")) {
771fe6b9
JG		 1478 /* powerbook with VGA */
1479 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
71a157e8
GL		 1480 } else if (of_machine_is_compatible("PowerBook3,4") ||
1481 of_machine_is_compatible("PowerBook3,5")) {
771fe6b9
JG		 1482 /* powerbook with internal tmds */
1483 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
71a157e8
GL		 1484 } else if (of_machine_is_compatible("PowerBook5,1") ||
1485 of_machine_is_compatible("PowerBook5,2") ||
1486 of_machine_is_compatible("PowerBook5,3") ||
1487 of_machine_is_compatible("PowerBook5,4") ||
1488 of_machine_is_compatible("PowerBook5,5")) {
771fe6b9
JG		 1489 /* powerbook with external single link tmds (sil164) */
1490 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8 1491 } else if (of_machine_is_compatible("PowerBook5,6")) {
771fe6b9
JG		 1492 /* powerbook with external dual or single link tmds */
1493 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8
GL		 1494 } else if (of_machine_is_compatible("PowerBook5,7") ||
1495 of_machine_is_compatible("PowerBook5,8") ||
1496 of_machine_is_compatible("PowerBook5,9")) {
771fe6b9
JG		 1497 /* PowerBook6,2 ? */
1498 /* powerbook with external dual link tmds (sil1178?) */
1499 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8
GL		 1500 } else if (of_machine_is_compatible("PowerBook4,1") ||
1501 of_machine_is_compatible("PowerBook4,2") ||
1502 of_machine_is_compatible("PowerBook4,3") ||
1503 of_machine_is_compatible("PowerBook6,3") ||
1504 of_machine_is_compatible("PowerBook6,5") ||
1505 of_machine_is_compatible("PowerBook6,7")) {
771fe6b9
JG		 1506 /* ibook */
1507 rdev->mode_info.connector_table = CT_IBOOK;
cafa59b9
AD		 1508 } else if (of_machine_is_compatible("PowerMac3,5")) {
1509 /* PowerMac G4 Silver radeon 7500 */
1510 rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
71a157e8 1511 } else if (of_machine_is_compatible("PowerMac4,4")) {
771fe6b9
JG		 1512 /* emac */
1513 rdev->mode_info.connector_table = CT_EMAC;
71a157e8 1514 } else if (of_machine_is_compatible("PowerMac10,1")) {
771fe6b9
JG		 1515 /* mini with internal tmds */
1516 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
71a157e8 1517 } else if (of_machine_is_compatible("PowerMac10,2")) {
771fe6b9
JG		 1518 /* mini with external tmds */
1519 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
71a157e8 1520 } else if (of_machine_is_compatible("PowerMac12,1")) {
771fe6b9
JG		 1521 /* PowerMac8,1 ? */
1522 /* imac g5 isight */
1523 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
aa74fbb4
AD		 1524 } else if ((rdev->pdev->device == 0x4a48) &&
1525 (rdev->pdev->subsystem_vendor == 0x1002) &&
1526 (rdev->pdev->subsystem_device == 0x4a48)) {
1527 /* Mac X800 */
1528 rdev->mode_info.connector_table = CT_MAC_X800;
7c88d2b8
AD		 1529 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1530 of_machine_is_compatible("PowerMac7,3")) &&
1531 (rdev->pdev->device == 0x4150) &&
1532 (rdev->pdev->subsystem_vendor == 0x1002) &&
1533 (rdev->pdev->subsystem_device == 0x4150)) {
1534 /* Mac G5 tower 9600 */
9fad321a 1535 rdev->mode_info.connector_table = CT_MAC_G5_9600;
6a556039
AD		 1536 } else if ((rdev->pdev->device == 0x4c66) &&
1537 (rdev->pdev->subsystem_vendor == 0x1002) &&
1538 (rdev->pdev->subsystem_device == 0x4c66)) {
1539 /* SAM440ep RV250 embedded board */
1540 rdev->mode_info.connector_table = CT_SAM440EP;
771fe6b9
JG		 1541 } else
1542#endif /* CONFIG_PPC_PMAC */
76a7142a
DA		 1543#ifdef CONFIG_PPC64
1544 if (ASIC_IS_RN50(rdev))
1545 rdev->mode_info.connector_table = CT_RN50_POWER;
1546 else
1547#endif
771fe6b9
JG		 1548 rdev->mode_info.connector_table = CT_GENERIC;
1549 }
1550
1551 switch (rdev->mode_info.connector_table) {
1552 case CT_GENERIC:
1553 DRM_INFO("Connector Table: %d (generic)\n",
1554 rdev->mode_info.connector_table);
1555 /* these are the most common settings */
1556 if (rdev->flags & RADEON_SINGLE_CRTC) {
1557 /* VGA - primary dac */
179e8078 1558 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1559 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1560 radeon_add_legacy_encoder(dev,
5137ee94 1561 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1562 ATOM_DEVICE_CRT1_SUPPORT,
1563 1),
1564 ATOM_DEVICE_CRT1_SUPPORT);
1565 radeon_add_legacy_connector(dev, 0,
1566 ATOM_DEVICE_CRT1_SUPPORT,
1567 DRM_MODE_CONNECTOR_VGA,
b75fad06 1568 &ddc_i2c,
eed45b30
AD		 1569 CONNECTOR_OBJECT_ID_VGA,
1570 &hpd);
771fe6b9
JG		 1571 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1572 /* LVDS */
179e8078 1573 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
eed45b30 1574 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1575 radeon_add_legacy_encoder(dev,
5137ee94 1576 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1577 ATOM_DEVICE_LCD1_SUPPORT,
1578 0),
1579 ATOM_DEVICE_LCD1_SUPPORT);
1580 radeon_add_legacy_connector(dev, 0,
1581 ATOM_DEVICE_LCD1_SUPPORT,
1582 DRM_MODE_CONNECTOR_LVDS,
b75fad06 1583 &ddc_i2c,
eed45b30
AD		 1584 CONNECTOR_OBJECT_ID_LVDS,
1585 &hpd);
771fe6b9
JG		 1586
1587 /* VGA - primary dac */
179e8078 1588 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1589 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1590 radeon_add_legacy_encoder(dev,
5137ee94 1591 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1592 ATOM_DEVICE_CRT1_SUPPORT,
1593 1),
1594 ATOM_DEVICE_CRT1_SUPPORT);
1595 radeon_add_legacy_connector(dev, 1,
1596 ATOM_DEVICE_CRT1_SUPPORT,
1597 DRM_MODE_CONNECTOR_VGA,
b75fad06 1598 &ddc_i2c,
eed45b30
AD		 1599 CONNECTOR_OBJECT_ID_VGA,
1600 &hpd);
771fe6b9
JG		 1601 } else {
1602 /* DVI-I - tv dac, int tmds */
179e8078 1603 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1604 hpd.hpd = RADEON_HPD_1;
771fe6b9 1605 radeon_add_legacy_encoder(dev,
5137ee94 1606 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1607 ATOM_DEVICE_DFP1_SUPPORT,
1608 0),
1609 ATOM_DEVICE_DFP1_SUPPORT);
1610 radeon_add_legacy_encoder(dev,
5137ee94 1611 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1612 ATOM_DEVICE_CRT2_SUPPORT,
1613 2),
1614 ATOM_DEVICE_CRT2_SUPPORT);
1615 radeon_add_legacy_connector(dev, 0,
1616 ATOM_DEVICE_DFP1_SUPPORT |
1617 ATOM_DEVICE_CRT2_SUPPORT,
1618 DRM_MODE_CONNECTOR_DVII,
b75fad06 1619 &ddc_i2c,
eed45b30
AD		 1620 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1621 &hpd);
771fe6b9
JG		 1622
1623 /* VGA - primary dac */
179e8078 1624 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1625 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1626 radeon_add_legacy_encoder(dev,
5137ee94 1627 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1628 ATOM_DEVICE_CRT1_SUPPORT,
1629 1),
1630 ATOM_DEVICE_CRT1_SUPPORT);
1631 radeon_add_legacy_connector(dev, 1,
1632 ATOM_DEVICE_CRT1_SUPPORT,
1633 DRM_MODE_CONNECTOR_VGA,
b75fad06 1634 &ddc_i2c,
eed45b30
AD		 1635 CONNECTOR_OBJECT_ID_VGA,
1636 &hpd);
771fe6b9
JG		 1637 }
1638
1639 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1640 /* TV - tv dac */
eed45b30
AD		 1641 ddc_i2c.valid = false;
1642 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1643 radeon_add_legacy_encoder(dev,
5137ee94 1644 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1645 ATOM_DEVICE_TV1_SUPPORT,
1646 2),
1647 ATOM_DEVICE_TV1_SUPPORT);
1648 radeon_add_legacy_connector(dev, 2,
1649 ATOM_DEVICE_TV1_SUPPORT,
1650 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1651 &ddc_i2c,
eed45b30
AD		 1652 CONNECTOR_OBJECT_ID_SVIDEO,
1653 &hpd);
771fe6b9
JG		 1654 }
1655 break;
1656 case CT_IBOOK:
1657 DRM_INFO("Connector Table: %d (ibook)\n",
1658 rdev->mode_info.connector_table);
1659 /* LVDS */
179e8078 1660 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1661 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1662 radeon_add_legacy_encoder(dev,
5137ee94 1663 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1664 ATOM_DEVICE_LCD1_SUPPORT,
1665 0),
1666 ATOM_DEVICE_LCD1_SUPPORT);
1667 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1668 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1669 CONNECTOR_OBJECT_ID_LVDS,
1670 &hpd);
771fe6b9 1671 /* VGA - TV DAC */
179e8078 1672 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1673 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1674 radeon_add_legacy_encoder(dev,
5137ee94 1675 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1676 ATOM_DEVICE_CRT2_SUPPORT,
1677 2),
1678 ATOM_DEVICE_CRT2_SUPPORT);
1679 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1680 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1681 CONNECTOR_OBJECT_ID_VGA,
1682 &hpd);
771fe6b9 1683 /* TV - TV DAC */
eed45b30
AD		 1684 ddc_i2c.valid = false;
1685 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1686 radeon_add_legacy_encoder(dev,
5137ee94 1687 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1688 ATOM_DEVICE_TV1_SUPPORT,
1689 2),
1690 ATOM_DEVICE_TV1_SUPPORT);
1691 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1692 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1693 &ddc_i2c,
eed45b30
AD		 1694 CONNECTOR_OBJECT_ID_SVIDEO,
1695 &hpd);
771fe6b9
JG		 1696 break;
1697 case CT_POWERBOOK_EXTERNAL:
1698 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1699 rdev->mode_info.connector_table);
1700 /* LVDS */
179e8078 1701 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1702 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1703 radeon_add_legacy_encoder(dev,
5137ee94 1704 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1705 ATOM_DEVICE_LCD1_SUPPORT,
1706 0),
1707 ATOM_DEVICE_LCD1_SUPPORT);
1708 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1709 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1710 CONNECTOR_OBJECT_ID_LVDS,
1711 &hpd);
771fe6b9 1712 /* DVI-I - primary dac, ext tmds */
179e8078 1713 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1714 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9 1715 radeon_add_legacy_encoder(dev,
5137ee94 1716 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1717 ATOM_DEVICE_DFP2_SUPPORT,
1718 0),
1719 ATOM_DEVICE_DFP2_SUPPORT);
1720 radeon_add_legacy_encoder(dev,
5137ee94 1721 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1722 ATOM_DEVICE_CRT1_SUPPORT,
1723 1),
1724 ATOM_DEVICE_CRT1_SUPPORT);
b75fad06 1725 /* XXX some are SL */
771fe6b9
JG		 1726 radeon_add_legacy_connector(dev, 1,
1727 ATOM_DEVICE_DFP2_SUPPORT |
1728 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1729 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1730 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1731 &hpd);
771fe6b9 1732 /* TV - TV DAC */
eed45b30
AD		 1733 ddc_i2c.valid = false;
1734 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1735 radeon_add_legacy_encoder(dev,
5137ee94 1736 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1737 ATOM_DEVICE_TV1_SUPPORT,
1738 2),
1739 ATOM_DEVICE_TV1_SUPPORT);
1740 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1741 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1742 &ddc_i2c,
eed45b30
AD		 1743 CONNECTOR_OBJECT_ID_SVIDEO,
1744 &hpd);
771fe6b9
JG		 1745 break;
1746 case CT_POWERBOOK_INTERNAL:
1747 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1748 rdev->mode_info.connector_table);
1749 /* LVDS */
179e8078 1750 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1751 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1752 radeon_add_legacy_encoder(dev,
5137ee94 1753 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1754 ATOM_DEVICE_LCD1_SUPPORT,
1755 0),
1756 ATOM_DEVICE_LCD1_SUPPORT);
1757 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1758 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1759 CONNECTOR_OBJECT_ID_LVDS,
1760 &hpd);
771fe6b9 1761 /* DVI-I - primary dac, int tmds */
179e8078 1762 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1763 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9 1764 radeon_add_legacy_encoder(dev,
5137ee94 1765 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1766 ATOM_DEVICE_DFP1_SUPPORT,
1767 0),
1768 ATOM_DEVICE_DFP1_SUPPORT);
1769 radeon_add_legacy_encoder(dev,
5137ee94 1770 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1771 ATOM_DEVICE_CRT1_SUPPORT,
1772 1),
1773 ATOM_DEVICE_CRT1_SUPPORT);
1774 radeon_add_legacy_connector(dev, 1,
1775 ATOM_DEVICE_DFP1_SUPPORT |
1776 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1777 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1778 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1779 &hpd);
771fe6b9 1780 /* TV - TV DAC */
eed45b30
AD		 1781 ddc_i2c.valid = false;
1782 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1783 radeon_add_legacy_encoder(dev,
5137ee94 1784 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1785 ATOM_DEVICE_TV1_SUPPORT,
1786 2),
1787 ATOM_DEVICE_TV1_SUPPORT);
1788 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1789 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1790 &ddc_i2c,
eed45b30
AD		 1791 CONNECTOR_OBJECT_ID_SVIDEO,
1792 &hpd);
771fe6b9
JG		 1793 break;
1794 case CT_POWERBOOK_VGA:
1795 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1796 rdev->mode_info.connector_table);
1797 /* LVDS */
179e8078 1798 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1799 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1800 radeon_add_legacy_encoder(dev,
5137ee94 1801 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1802 ATOM_DEVICE_LCD1_SUPPORT,
1803 0),
1804 ATOM_DEVICE_LCD1_SUPPORT);
1805 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1806 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1807 CONNECTOR_OBJECT_ID_LVDS,
1808 &hpd);
771fe6b9 1809 /* VGA - primary dac */
179e8078 1810 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1811 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1812 radeon_add_legacy_encoder(dev,
5137ee94 1813 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1814 ATOM_DEVICE_CRT1_SUPPORT,
1815 1),
1816 ATOM_DEVICE_CRT1_SUPPORT);
1817 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1818 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1819 CONNECTOR_OBJECT_ID_VGA,
1820 &hpd);
771fe6b9 1821 /* TV - TV DAC */
eed45b30
AD		 1822 ddc_i2c.valid = false;
1823 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1824 radeon_add_legacy_encoder(dev,
5137ee94 1825 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1826 ATOM_DEVICE_TV1_SUPPORT,
1827 2),
1828 ATOM_DEVICE_TV1_SUPPORT);
1829 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1830 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1831 &ddc_i2c,
eed45b30
AD		 1832 CONNECTOR_OBJECT_ID_SVIDEO,
1833 &hpd);
771fe6b9
JG		 1834 break;
1835 case CT_MINI_EXTERNAL:
1836 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1837 rdev->mode_info.connector_table);
1838 /* DVI-I - tv dac, ext tmds */
179e8078 1839 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
eed45b30 1840 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9 1841 radeon_add_legacy_encoder(dev,
5137ee94 1842 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1843 ATOM_DEVICE_DFP2_SUPPORT,
1844 0),
1845 ATOM_DEVICE_DFP2_SUPPORT);
1846 radeon_add_legacy_encoder(dev,
5137ee94 1847 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1848 ATOM_DEVICE_CRT2_SUPPORT,
1849 2),
1850 ATOM_DEVICE_CRT2_SUPPORT);
b75fad06 1851 /* XXX are any DL? */
771fe6b9
JG		 1852 radeon_add_legacy_connector(dev, 0,
1853 ATOM_DEVICE_DFP2_SUPPORT |
1854 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1855 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1856 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1857 &hpd);
771fe6b9 1858 /* TV - TV DAC */
eed45b30
AD		 1859 ddc_i2c.valid = false;
1860 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1861 radeon_add_legacy_encoder(dev,
5137ee94 1862 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1863 ATOM_DEVICE_TV1_SUPPORT,
1864 2),
1865 ATOM_DEVICE_TV1_SUPPORT);
1866 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1867 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1868 &ddc_i2c,
eed45b30
AD		 1869 CONNECTOR_OBJECT_ID_SVIDEO,
1870 &hpd);
771fe6b9
JG		 1871 break;
1872 case CT_MINI_INTERNAL:
1873 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1874 rdev->mode_info.connector_table);
1875 /* DVI-I - tv dac, int tmds */
179e8078 1876 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
eed45b30 1877 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9 1878 radeon_add_legacy_encoder(dev,
5137ee94 1879 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1880 ATOM_DEVICE_DFP1_SUPPORT,
1881 0),
1882 ATOM_DEVICE_DFP1_SUPPORT);
1883 radeon_add_legacy_encoder(dev,
5137ee94 1884 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1885 ATOM_DEVICE_CRT2_SUPPORT,
1886 2),
1887 ATOM_DEVICE_CRT2_SUPPORT);
1888 radeon_add_legacy_connector(dev, 0,
1889 ATOM_DEVICE_DFP1_SUPPORT |
1890 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1891 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1892 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1893 &hpd);
771fe6b9 1894 /* TV - TV DAC */
eed45b30
AD		 1895 ddc_i2c.valid = false;
1896 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1897 radeon_add_legacy_encoder(dev,
5137ee94 1898 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1899 ATOM_DEVICE_TV1_SUPPORT,
1900 2),
1901 ATOM_DEVICE_TV1_SUPPORT);
1902 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1903 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1904 &ddc_i2c,
eed45b30
AD		 1905 CONNECTOR_OBJECT_ID_SVIDEO,
1906 &hpd);
771fe6b9
JG		 1907 break;
1908 case CT_IMAC_G5_ISIGHT:
1909 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1910 rdev->mode_info.connector_table);
1911 /* DVI-D - int tmds */
179e8078 1912 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
eed45b30 1913 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9 1914 radeon_add_legacy_encoder(dev,
5137ee94 1915 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1916 ATOM_DEVICE_DFP1_SUPPORT,
1917 0),
1918 ATOM_DEVICE_DFP1_SUPPORT);
1919 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
b75fad06 1920 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
eed45b30
AD		 1921 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1922 &hpd);
771fe6b9 1923 /* VGA - tv dac */
179e8078 1924 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1925 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1926 radeon_add_legacy_encoder(dev,
5137ee94 1927 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1928 ATOM_DEVICE_CRT2_SUPPORT,
1929 2),
1930 ATOM_DEVICE_CRT2_SUPPORT);
1931 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1932 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1933 CONNECTOR_OBJECT_ID_VGA,
1934 &hpd);
771fe6b9 1935 /* TV - TV DAC */
eed45b30
AD		 1936 ddc_i2c.valid = false;
1937 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1938 radeon_add_legacy_encoder(dev,
5137ee94 1939 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1940 ATOM_DEVICE_TV1_SUPPORT,
1941 2),
1942 ATOM_DEVICE_TV1_SUPPORT);
1943 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1944 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1945 &ddc_i2c,
eed45b30
AD		 1946 CONNECTOR_OBJECT_ID_SVIDEO,
1947 &hpd);
771fe6b9
JG		 1948 break;
1949 case CT_EMAC:
1950 DRM_INFO("Connector Table: %d (emac)\n",
1951 rdev->mode_info.connector_table);
1952 /* VGA - primary dac */
179e8078 1953 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1954 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1955 radeon_add_legacy_encoder(dev,
5137ee94 1956 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1957 ATOM_DEVICE_CRT1_SUPPORT,
1958 1),
1959 ATOM_DEVICE_CRT1_SUPPORT);
1960 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1961 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1962 CONNECTOR_OBJECT_ID_VGA,
1963 &hpd);
771fe6b9 1964 /* VGA - tv dac */
179e8078 1965 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
eed45b30 1966 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1967 radeon_add_legacy_encoder(dev,
5137ee94 1968 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1969 ATOM_DEVICE_CRT2_SUPPORT,
1970 2),
1971 ATOM_DEVICE_CRT2_SUPPORT);
1972 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1973 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1974 CONNECTOR_OBJECT_ID_VGA,
1975 &hpd);
771fe6b9 1976 /* TV - TV DAC */
eed45b30
AD		 1977 ddc_i2c.valid = false;
1978 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1979 radeon_add_legacy_encoder(dev,
5137ee94 1980 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1981 ATOM_DEVICE_TV1_SUPPORT,
1982 2),
1983 ATOM_DEVICE_TV1_SUPPORT);
1984 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1985 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1986 &ddc_i2c,
eed45b30
AD		 1987 CONNECTOR_OBJECT_ID_SVIDEO,
1988 &hpd);
771fe6b9 1989 break;
76a7142a
DA		 1990 case CT_RN50_POWER:
1991 DRM_INFO("Connector Table: %d (rn50-power)\n",
1992 rdev->mode_info.connector_table);
1993 /* VGA - primary dac */
179e8078 1994 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
76a7142a
DA		 1995 hpd.hpd = RADEON_HPD_NONE;
1996 radeon_add_legacy_encoder(dev,
5137ee94 1997 radeon_get_encoder_enum(dev,
76a7142a
DA		 1998 ATOM_DEVICE_CRT1_SUPPORT,
1999 1),
2000 ATOM_DEVICE_CRT1_SUPPORT);
2001 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
2002 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2003 CONNECTOR_OBJECT_ID_VGA,
2004 &hpd);
179e8078 2005 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
76a7142a
DA		 2006 hpd.hpd = RADEON_HPD_NONE;
2007 radeon_add_legacy_encoder(dev,
5137ee94 2008 radeon_get_encoder_enum(dev,
76a7142a
DA		 2009 ATOM_DEVICE_CRT2_SUPPORT,
2010 2),
2011 ATOM_DEVICE_CRT2_SUPPORT);
2012 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2013 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2014 CONNECTOR_OBJECT_ID_VGA,
2015 &hpd);
2016 break;
aa74fbb4
AD		 2017 case CT_MAC_X800:
2018 DRM_INFO("Connector Table: %d (mac x800)\n",
2019 rdev->mode_info.connector_table);
2020 /* DVI - primary dac, internal tmds */
2021 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2022 hpd.hpd = RADEON_HPD_1; /* ??? */
2023 radeon_add_legacy_encoder(dev,
2024 radeon_get_encoder_enum(dev,
2025 ATOM_DEVICE_DFP1_SUPPORT,
2026 0),
2027 ATOM_DEVICE_DFP1_SUPPORT);
2028 radeon_add_legacy_encoder(dev,
2029 radeon_get_encoder_enum(dev,
2030 ATOM_DEVICE_CRT1_SUPPORT,
2031 1),
2032 ATOM_DEVICE_CRT1_SUPPORT);
2033 radeon_add_legacy_connector(dev, 0,
2034 ATOM_DEVICE_DFP1_SUPPORT |
2035 ATOM_DEVICE_CRT1_SUPPORT,
2036 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2037 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2038 &hpd);
2039 /* DVI - tv dac, dvo */
2040 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2041 hpd.hpd = RADEON_HPD_2; /* ??? */
2042 radeon_add_legacy_encoder(dev,
2043 radeon_get_encoder_enum(dev,
2044 ATOM_DEVICE_DFP2_SUPPORT,
2045 0),
2046 ATOM_DEVICE_DFP2_SUPPORT);
2047 radeon_add_legacy_encoder(dev,
2048 radeon_get_encoder_enum(dev,
2049 ATOM_DEVICE_CRT2_SUPPORT,
2050 2),
2051 ATOM_DEVICE_CRT2_SUPPORT);
2052 radeon_add_legacy_connector(dev, 1,
2053 ATOM_DEVICE_DFP2_SUPPORT |
2054 ATOM_DEVICE_CRT2_SUPPORT,
2055 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2056 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2057 &hpd);
2058 break;
9fad321a
AD		 2059 case CT_MAC_G5_9600:
2060 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2061 rdev->mode_info.connector_table);
2062 /* DVI - tv dac, dvo */
2063 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2064 hpd.hpd = RADEON_HPD_1; /* ??? */
2065 radeon_add_legacy_encoder(dev,
2066 radeon_get_encoder_enum(dev,
2067 ATOM_DEVICE_DFP2_SUPPORT,
2068 0),
2069 ATOM_DEVICE_DFP2_SUPPORT);
2070 radeon_add_legacy_encoder(dev,
2071 radeon_get_encoder_enum(dev,
2072 ATOM_DEVICE_CRT2_SUPPORT,
2073 2),
2074 ATOM_DEVICE_CRT2_SUPPORT);
2075 radeon_add_legacy_connector(dev, 0,
2076 ATOM_DEVICE_DFP2_SUPPORT |
2077 ATOM_DEVICE_CRT2_SUPPORT,
2078 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2079 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2080 &hpd);
2081 /* ADC - primary dac, internal tmds */
2082 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2083 hpd.hpd = RADEON_HPD_2; /* ??? */
2084 radeon_add_legacy_encoder(dev,
2085 radeon_get_encoder_enum(dev,
2086 ATOM_DEVICE_DFP1_SUPPORT,
2087 0),
2088 ATOM_DEVICE_DFP1_SUPPORT);
2089 radeon_add_legacy_encoder(dev,
2090 radeon_get_encoder_enum(dev,
2091 ATOM_DEVICE_CRT1_SUPPORT,
2092 1),
2093 ATOM_DEVICE_CRT1_SUPPORT);
2094 radeon_add_legacy_connector(dev, 1,
2095 ATOM_DEVICE_DFP1_SUPPORT |
2096 ATOM_DEVICE_CRT1_SUPPORT,
2097 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2098 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2099 &hpd);
beb47274
AD		 2100 /* TV - TV DAC */
2101 ddc_i2c.valid = false;
2102 hpd.hpd = RADEON_HPD_NONE;
2103 radeon_add_legacy_encoder(dev,
2104 radeon_get_encoder_enum(dev,
2105 ATOM_DEVICE_TV1_SUPPORT,
2106 2),
2107 ATOM_DEVICE_TV1_SUPPORT);
2108 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2109 DRM_MODE_CONNECTOR_SVIDEO,
2110 &ddc_i2c,
2111 CONNECTOR_OBJECT_ID_SVIDEO,
2112 &hpd);
9fad321a 2113 break;
6a556039
AD		 2114 case CT_SAM440EP:
2115 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
2116 rdev->mode_info.connector_table);
2117 /* LVDS */
2118 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
2119 hpd.hpd = RADEON_HPD_NONE;
2120 radeon_add_legacy_encoder(dev,
2121 radeon_get_encoder_enum(dev,
2122 ATOM_DEVICE_LCD1_SUPPORT,
2123 0),
2124 ATOM_DEVICE_LCD1_SUPPORT);
2125 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
2126 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
2127 CONNECTOR_OBJECT_ID_LVDS,
2128 &hpd);
2129 /* DVI-I - secondary dac, int tmds */
2130 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2131 hpd.hpd = RADEON_HPD_1; /* ??? */
2132 radeon_add_legacy_encoder(dev,
2133 radeon_get_encoder_enum(dev,
2134 ATOM_DEVICE_DFP1_SUPPORT,
2135 0),
2136 ATOM_DEVICE_DFP1_SUPPORT);
2137 radeon_add_legacy_encoder(dev,
2138 radeon_get_encoder_enum(dev,
2139 ATOM_DEVICE_CRT2_SUPPORT,
2140 2),
2141 ATOM_DEVICE_CRT2_SUPPORT);
2142 radeon_add_legacy_connector(dev, 1,
2143 ATOM_DEVICE_DFP1_SUPPORT |
2144 ATOM_DEVICE_CRT2_SUPPORT,
2145 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2146 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2147 &hpd);
2148 /* VGA - primary dac */
2149 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2150 hpd.hpd = RADEON_HPD_NONE;
2151 radeon_add_legacy_encoder(dev,
2152 radeon_get_encoder_enum(dev,
2153 ATOM_DEVICE_CRT1_SUPPORT,
2154 1),
2155 ATOM_DEVICE_CRT1_SUPPORT);
2156 radeon_add_legacy_connector(dev, 2,
2157 ATOM_DEVICE_CRT1_SUPPORT,
2158 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2159 CONNECTOR_OBJECT_ID_VGA,
2160 &hpd);
2161 /* TV - TV DAC */
2162 ddc_i2c.valid = false;
2163 hpd.hpd = RADEON_HPD_NONE;
2164 radeon_add_legacy_encoder(dev,
2165 radeon_get_encoder_enum(dev,
2166 ATOM_DEVICE_TV1_SUPPORT,
2167 2),
2168 ATOM_DEVICE_TV1_SUPPORT);
2169 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
2170 DRM_MODE_CONNECTOR_SVIDEO,
2171 &ddc_i2c,
2172 CONNECTOR_OBJECT_ID_SVIDEO,
2173 &hpd);
2174 break;
cafa59b9
AD		 2175 case CT_MAC_G4_SILVER:
2176 DRM_INFO("Connector Table: %d (mac g4 silver)\n",
2177 rdev->mode_info.connector_table);
2178 /* DVI-I - tv dac, int tmds */
2179 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2180 hpd.hpd = RADEON_HPD_1; /* ??? */
2181 radeon_add_legacy_encoder(dev,
2182 radeon_get_encoder_enum(dev,
2183 ATOM_DEVICE_DFP1_SUPPORT,
2184 0),
2185 ATOM_DEVICE_DFP1_SUPPORT);
2186 radeon_add_legacy_encoder(dev,
2187 radeon_get_encoder_enum(dev,
2188 ATOM_DEVICE_CRT2_SUPPORT,
2189 2),
2190 ATOM_DEVICE_CRT2_SUPPORT);
2191 radeon_add_legacy_connector(dev, 0,
2192 ATOM_DEVICE_DFP1_SUPPORT |
2193 ATOM_DEVICE_CRT2_SUPPORT,
2194 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2195 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2196 &hpd);
2197 /* VGA - primary dac */
2198 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2199 hpd.hpd = RADEON_HPD_NONE;
2200 radeon_add_legacy_encoder(dev,
2201 radeon_get_encoder_enum(dev,
2202 ATOM_DEVICE_CRT1_SUPPORT,
2203 1),
2204 ATOM_DEVICE_CRT1_SUPPORT);
2205 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
2206 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2207 CONNECTOR_OBJECT_ID_VGA,
2208 &hpd);
2209 /* TV - TV DAC */
2210 ddc_i2c.valid = false;
2211 hpd.hpd = RADEON_HPD_NONE;
2212 radeon_add_legacy_encoder(dev,
2213 radeon_get_encoder_enum(dev,
2214 ATOM_DEVICE_TV1_SUPPORT,
2215 2),
2216 ATOM_DEVICE_TV1_SUPPORT);
2217 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2218 DRM_MODE_CONNECTOR_SVIDEO,
2219 &ddc_i2c,
2220 CONNECTOR_OBJECT_ID_SVIDEO,
2221 &hpd);
2222 break;
771fe6b9
JG		 2223 default:
2224 DRM_INFO("Connector table: %d (invalid)\n",
2225 rdev->mode_info.connector_table);
2226 return false;
2227 }
2228
2229 radeon_link_encoder_connector(dev);
2230
2231 return true;
2232}
2233
2234static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2235 int bios_index,
2236 enum radeon_combios_connector
2237 *legacy_connector,
eed45b30
AD		 2238 struct radeon_i2c_bus_rec *ddc_i2c,
2239 struct radeon_hpd *hpd)
771fe6b9 2240{
fcec570b 2241
771fe6b9
JG		 2242 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2243 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2244 if (dev->pdev->device == 0x515e &&
2245 dev->pdev->subsystem_vendor == 0x1014) {
2246 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2247 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2248 return false;
2249 }
2250
771fe6b9
JG		 2251 /* X300 card with extra non-existent DVI port */
2252 if (dev->pdev->device == 0x5B60 &&
2253 dev->pdev->subsystem_vendor == 0x17af &&
2254 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2255 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2256 return false;
2257 }
2258
2259 return true;
2260}
2261
790cfb34
AD		 2262static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2263{
2264 /* Acer 5102 has non-existent TV port */
2265 if (dev->pdev->device == 0x5975 &&
2266 dev->pdev->subsystem_vendor == 0x1025 &&
2267 dev->pdev->subsystem_device == 0x009f)
2268 return false;
2269
fc7f7119
AD		 2270 /* HP dc5750 has non-existent TV port */
2271 if (dev->pdev->device == 0x5974 &&
2272 dev->pdev->subsystem_vendor == 0x103c &&
2273 dev->pdev->subsystem_device == 0x280a)
2274 return false;
2275
fd874ad0
AD		 2276 /* MSI S270 has non-existent TV port */
2277 if (dev->pdev->device == 0x5955 &&
2278 dev->pdev->subsystem_vendor == 0x1462 &&
2279 dev->pdev->subsystem_device == 0x0131)
2280 return false;
2281
790cfb34
AD		 2282 return true;
2283}
2284
b75fad06
AD		 2285static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2286{
2287 struct radeon_device *rdev = dev->dev_private;
2288 uint32_t ext_tmds_info;
2289
2290 if (rdev->flags & RADEON_IS_IGP) {
2291 if (is_dvi_d)
2292 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2293 else
2294 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2295 }
2296 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2297 if (ext_tmds_info) {
2298 uint8_t rev = RBIOS8(ext_tmds_info);
2299 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2300 if (rev >= 3) {
2301 if (is_dvi_d)
2302 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2303 else
2304 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2305 } else {
2306 if (flags & 1) {
2307 if (is_dvi_d)
2308 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2309 else
2310 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2311 }
2312 }
2313 }
2314 if (is_dvi_d)
2315 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2316 else
2317 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2318}
2319
771fe6b9
JG		 2320bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2321{
2322 struct radeon_device *rdev = dev->dev_private;
2323 uint32_t conn_info, entry, devices;
b75fad06 2324 uint16_t tmp, connector_object_id;
771fe6b9
JG		 2325 enum radeon_combios_ddc ddc_type;
2326 enum radeon_combios_connector connector;
2327 int i = 0;
2328 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 2329 struct radeon_hpd hpd;
771fe6b9 2330
771fe6b9
JG		 2331 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2332 if (conn_info) {
2333 for (i = 0; i < 4; i++) {
2334 entry = conn_info + 2 + i * 2;
2335
2336 if (!RBIOS16(entry))
2337 break;
2338
2339 tmp = RBIOS16(entry);
2340
2341 connector = (tmp >> 12) & 0xf;
2342
2343 ddc_type = (tmp >> 8) & 0xf;
3d61bd42
AD		 2344 if (ddc_type == 5)
2345 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
2346 else
2347 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
771fe6b9 2348
eed45b30
AD		 2349 switch (connector) {
2350 case CONNECTOR_PROPRIETARY_LEGACY:
2351 case CONNECTOR_DVI_I_LEGACY:
2352 case CONNECTOR_DVI_D_LEGACY:
2353 if ((tmp >> 4) & 0x1)
2354 hpd.hpd = RADEON_HPD_2;
2355 else
2356 hpd.hpd = RADEON_HPD_1;
2357 break;
2358 default:
2359 hpd.hpd = RADEON_HPD_NONE;
2360 break;
2361 }
2362
2d152c6b 2363 if (!radeon_apply_legacy_quirks(dev, i, &connector,
eed45b30 2364 &ddc_i2c, &hpd))
2d152c6b 2365 continue;
771fe6b9
JG		 2366
2367 switch (connector) {
2368 case CONNECTOR_PROPRIETARY_LEGACY:
2369 if ((tmp >> 4) & 0x1)
2370 devices = ATOM_DEVICE_DFP2_SUPPORT;
2371 else
2372 devices = ATOM_DEVICE_DFP1_SUPPORT;
2373 radeon_add_legacy_encoder(dev,
5137ee94 2374 radeon_get_encoder_enum
771fe6b9
JG		 2375 (dev, devices, 0),
2376 devices);
2377 radeon_add_legacy_connector(dev, i, devices,
2378 legacy_connector_convert
2379 [connector],
b75fad06 2380 &ddc_i2c,
eed45b30
AD		 2381 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2382 &hpd);
771fe6b9
JG		 2383 break;
2384 case CONNECTOR_CRT_LEGACY:
2385 if (tmp & 0x1) {
2386 devices = ATOM_DEVICE_CRT2_SUPPORT;
2387 radeon_add_legacy_encoder(dev,
5137ee94 2388 radeon_get_encoder_enum
771fe6b9
JG		 2389 (dev,
2390 ATOM_DEVICE_CRT2_SUPPORT,
2391 2),
2392 ATOM_DEVICE_CRT2_SUPPORT);
2393 } else {
2394 devices = ATOM_DEVICE_CRT1_SUPPORT;
2395 radeon_add_legacy_encoder(dev,
5137ee94 2396 radeon_get_encoder_enum
771fe6b9
JG		 2397 (dev,
2398 ATOM_DEVICE_CRT1_SUPPORT,
2399 1),
2400 ATOM_DEVICE_CRT1_SUPPORT);
2401 }
2402 radeon_add_legacy_connector(dev,
2403 i,
2404 devices,
2405 legacy_connector_convert
2406 [connector],
b75fad06 2407 &ddc_i2c,
eed45b30
AD		 2408 CONNECTOR_OBJECT_ID_VGA,
2409 &hpd);
771fe6b9
JG		 2410 break;
2411 case CONNECTOR_DVI_I_LEGACY:
2412 devices = 0;
2413 if (tmp & 0x1) {
2414 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2415 radeon_add_legacy_encoder(dev,
5137ee94 2416 radeon_get_encoder_enum
771fe6b9
JG		 2417 (dev,
2418 ATOM_DEVICE_CRT2_SUPPORT,
2419 2),
2420 ATOM_DEVICE_CRT2_SUPPORT);
2421 } else {
2422 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2423 radeon_add_legacy_encoder(dev,
5137ee94 2424 radeon_get_encoder_enum
771fe6b9
JG		 2425 (dev,
2426 ATOM_DEVICE_CRT1_SUPPORT,
2427 1),
2428 ATOM_DEVICE_CRT1_SUPPORT);
2429 }
9200ee49
AD		 2430 /* RV100 board with external TDMS bit mis-set.
2431 * Actually uses internal TMDS, clear the bit.
2432 */
2433 if (dev->pdev->device == 0x5159 &&
2434 dev->pdev->subsystem_vendor == 0x1014 &&
2435 dev->pdev->subsystem_device == 0x029A) {
2436 tmp &= ~(1 << 4);
2437 }
771fe6b9
JG		 2438 if ((tmp >> 4) & 0x1) {
2439 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2440 radeon_add_legacy_encoder(dev,
5137ee94 2441 radeon_get_encoder_enum
771fe6b9
JG		 2442 (dev,
2443 ATOM_DEVICE_DFP2_SUPPORT,
2444 0),
2445 ATOM_DEVICE_DFP2_SUPPORT);
b75fad06 2446 connector_object_id = combios_check_dl_dvi(dev, 0);
771fe6b9
JG		 2447 } else {
2448 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2449 radeon_add_legacy_encoder(dev,
5137ee94 2450 radeon_get_encoder_enum
771fe6b9
JG		 2451 (dev,
2452 ATOM_DEVICE_DFP1_SUPPORT,
2453 0),
2454 ATOM_DEVICE_DFP1_SUPPORT);
b75fad06 2455 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
771fe6b9
JG		 2456 }
2457 radeon_add_legacy_connector(dev,
2458 i,
2459 devices,
2460 legacy_connector_convert
2461 [connector],
b75fad06 2462 &ddc_i2c,
eed45b30
AD		 2463 connector_object_id,
2464 &hpd);
771fe6b9
JG		 2465 break;
2466 case CONNECTOR_DVI_D_LEGACY:
b75fad06 2467 if ((tmp >> 4) & 0x1) {
771fe6b9 2468 devices = ATOM_DEVICE_DFP2_SUPPORT;
b75fad06
AD		 2469 connector_object_id = combios_check_dl_dvi(dev, 1);
2470 } else {
771fe6b9 2471 devices = ATOM_DEVICE_DFP1_SUPPORT;
b75fad06
AD		 2472 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2473 }
771fe6b9 2474 radeon_add_legacy_encoder(dev,
5137ee94 2475 radeon_get_encoder_enum
771fe6b9
JG		 2476 (dev, devices, 0),
2477 devices);
2478 radeon_add_legacy_connector(dev, i, devices,
2479 legacy_connector_convert
2480 [connector],
b75fad06 2481 &ddc_i2c,
eed45b30
AD		 2482 connector_object_id,
2483 &hpd);
771fe6b9
JG		 2484 break;
2485 case CONNECTOR_CTV_LEGACY:
2486 case CONNECTOR_STV_LEGACY:
2487 radeon_add_legacy_encoder(dev,
5137ee94 2488 radeon_get_encoder_enum
771fe6b9
JG		 2489 (dev,
2490 ATOM_DEVICE_TV1_SUPPORT,
2491 2),
2492 ATOM_DEVICE_TV1_SUPPORT);
2493 radeon_add_legacy_connector(dev, i,
2494 ATOM_DEVICE_TV1_SUPPORT,
2495 legacy_connector_convert
2496 [connector],
b75fad06 2497 &ddc_i2c,
eed45b30
AD		 2498 CONNECTOR_OBJECT_ID_SVIDEO,
2499 &hpd);
771fe6b9
JG		 2500 break;
2501 default:
2502 DRM_ERROR("Unknown connector type: %d\n",
2503 connector);
2504 continue;
2505 }
2506
2507 }
2508 } else {
2509 uint16_t tmds_info =
2510 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2511 if (tmds_info) {
d9fdaafb 2512 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
771fe6b9
JG		 2513
2514 radeon_add_legacy_encoder(dev,
5137ee94 2515 radeon_get_encoder_enum(dev,
771fe6b9
JG		 2516 ATOM_DEVICE_CRT1_SUPPORT,
2517 1),
2518 ATOM_DEVICE_CRT1_SUPPORT);
2519 radeon_add_legacy_encoder(dev,
5137ee94 2520 radeon_get_encoder_enum(dev,
771fe6b9
JG		 2521 ATOM_DEVICE_DFP1_SUPPORT,
2522 0),
2523 ATOM_DEVICE_DFP1_SUPPORT);
2524
179e8078 2525 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
8e36ed00 2526 hpd.hpd = RADEON_HPD_1;
771fe6b9
JG		 2527 radeon_add_legacy_connector(dev,
2528 0,
2529 ATOM_DEVICE_CRT1_SUPPORT |
2530 ATOM_DEVICE_DFP1_SUPPORT,
2531 DRM_MODE_CONNECTOR_DVII,
b75fad06 2532 &ddc_i2c,
eed45b30
AD		 2533 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2534 &hpd);
771fe6b9 2535 } else {
d0c403e9
AD		 2536 uint16_t crt_info =
2537 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
d9fdaafb 2538 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
d0c403e9
AD		 2539 if (crt_info) {
2540 radeon_add_legacy_encoder(dev,
5137ee94 2541 radeon_get_encoder_enum(dev,
d0c403e9
AD		 2542 ATOM_DEVICE_CRT1_SUPPORT,
2543 1),
2544 ATOM_DEVICE_CRT1_SUPPORT);
179e8078 2545 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 2546 hpd.hpd = RADEON_HPD_NONE;
d0c403e9
AD		 2547 radeon_add_legacy_connector(dev,
2548 0,
2549 ATOM_DEVICE_CRT1_SUPPORT,
2550 DRM_MODE_CONNECTOR_VGA,
b75fad06 2551 &ddc_i2c,
eed45b30
AD		 2552 CONNECTOR_OBJECT_ID_VGA,
2553 &hpd);
d0c403e9 2554 } else {
d9fdaafb 2555 DRM_DEBUG_KMS("No connector info found\n");
d0c403e9
AD		 2556 return false;
2557 }
771fe6b9
JG		 2558 }
2559 }
2560
2561 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2562 uint16_t lcd_info =
2563 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2564 if (lcd_info) {
2565 uint16_t lcd_ddc_info =
2566 combios_get_table_offset(dev,
2567 COMBIOS_LCD_DDC_INFO_TABLE);
2568
2569 radeon_add_legacy_encoder(dev,
5137ee94 2570 radeon_get_encoder_enum(dev,
771fe6b9
JG		 2571 ATOM_DEVICE_LCD1_SUPPORT,
2572 0),
2573 ATOM_DEVICE_LCD1_SUPPORT);
2574
2575 if (lcd_ddc_info) {
2576 ddc_type = RBIOS8(lcd_ddc_info + 2);
2577 switch (ddc_type) {
771fe6b9
JG		 2578 case DDC_LCD:
2579 ddc_i2c =
179e8078
AD		 2580 combios_setup_i2c_bus(rdev,
2581 DDC_LCD,
2582 RBIOS32(lcd_ddc_info + 3),
2583 RBIOS32(lcd_ddc_info + 7));
f376b94f 2584 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
771fe6b9
JG		 2585 break;
2586 case DDC_GPIO:
2587 ddc_i2c =
179e8078
AD		 2588 combios_setup_i2c_bus(rdev,
2589 DDC_GPIO,
2590 RBIOS32(lcd_ddc_info + 3),
2591 RBIOS32(lcd_ddc_info + 7));
f376b94f 2592 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
771fe6b9
JG		 2593 break;
2594 default:
179e8078
AD		 2595 ddc_i2c =
2596 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
771fe6b9
JG		 2597 break;
2598 }
d9fdaafb 2599 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
771fe6b9
JG		 2600 } else
2601 ddc_i2c.valid = false;
2602
eed45b30 2603 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 2604 radeon_add_legacy_connector(dev,
2605 5,
2606 ATOM_DEVICE_LCD1_SUPPORT,
2607 DRM_MODE_CONNECTOR_LVDS,
b75fad06 2608 &ddc_i2c,
eed45b30
AD		 2609 CONNECTOR_OBJECT_ID_LVDS,
2610 &hpd);
771fe6b9
JG		 2611 }
2612 }
2613
2614 /* check TV table */
2615 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2616 uint32_t tv_info =
2617 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2618 if (tv_info) {
2619 if (RBIOS8(tv_info + 6) == 'T') {
790cfb34 2620 if (radeon_apply_legacy_tv_quirks(dev)) {
eed45b30 2621 hpd.hpd = RADEON_HPD_NONE;
d294ed69 2622 ddc_i2c.valid = false;
790cfb34 2623 radeon_add_legacy_encoder(dev,
5137ee94 2624 radeon_get_encoder_enum
790cfb34
AD		 2625 (dev,
2626 ATOM_DEVICE_TV1_SUPPORT,
2627 2),
2628 ATOM_DEVICE_TV1_SUPPORT);
2629 radeon_add_legacy_connector(dev, 6,
2630 ATOM_DEVICE_TV1_SUPPORT,
2631 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 2632 &ddc_i2c,
eed45b30
AD		 2633 CONNECTOR_OBJECT_ID_SVIDEO,
2634 &hpd);
790cfb34 2635 }
771fe6b9
JG		 2636 }
2637 }
2638 }
2639
2640 radeon_link_encoder_connector(dev);
2641
2642 return true;
2643}
2644
63f7d982
AD		 2645static const char *thermal_controller_names[] = {
2646 "NONE",
2647 "lm63",
2648 "adm1032",
2649};
2650
56278a8e
AD		 2651void radeon_combios_get_power_modes(struct radeon_device *rdev)
2652{
2653 struct drm_device *dev = rdev->ddev;
2654 u16 offset, misc, misc2 = 0;
2655 u8 rev, blocks, tmp;
2656 int state_index = 0;
c41b9ee9 2657 struct radeon_i2c_bus_rec i2c_bus;
56278a8e 2658
a48b9b4e 2659 rdev->pm.default_power_state_index = -1;
56278a8e 2660
0975b162
AD		 2661 /* allocate 2 power states */
2662 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
a7c36fd8
AD		 2663 if (rdev->pm.power_state) {
2664 /* allocate 1 clock mode per state */
2665 rdev->pm.power_state[0].clock_info =
2666 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2667 rdev->pm.power_state[1].clock_info =
2668 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2669 if (!rdev->pm.power_state[0].clock_info ||
2670 !rdev->pm.power_state[1].clock_info)
2671 goto pm_failed;
2672 } else
2673 goto pm_failed;
0975b162 2674
63f7d982
AD		 2675 /* check for a thermal chip */
2676 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2677 if (offset) {
2678 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
63f7d982
AD		 2679
2680 rev = RBIOS8(offset);
2681
2682 if (rev == 0) {
2683 thermal_controller = RBIOS8(offset + 3);
2684 gpio = RBIOS8(offset + 4) & 0x3f;
2685 i2c_addr = RBIOS8(offset + 5);
2686 } else if (rev == 1) {
2687 thermal_controller = RBIOS8(offset + 4);
2688 gpio = RBIOS8(offset + 5) & 0x3f;
2689 i2c_addr = RBIOS8(offset + 6);
2690 } else if (rev == 2) {
2691 thermal_controller = RBIOS8(offset + 4);
2692 gpio = RBIOS8(offset + 5) & 0x3f;
2693 i2c_addr = RBIOS8(offset + 6);
2694 clk_bit = RBIOS8(offset + 0xa);
2695 data_bit = RBIOS8(offset + 0xb);
2696 }
2697 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2698 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2699 thermal_controller_names[thermal_controller],
2700 i2c_addr >> 1);
2701 if (gpio == DDC_LCD) {
2702 /* MM i2c */
2703 i2c_bus.valid = true;
2704 i2c_bus.hw_capable = true;
2705 i2c_bus.mm_i2c = true;
2706 i2c_bus.i2c_id = 0xa0;
2707 } else if (gpio == DDC_GPIO)
2708 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2709 else
2710 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2711 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2712 if (rdev->pm.i2c_bus) {
2713 struct i2c_board_info info = { };
2714 const char *name = thermal_controller_names[thermal_controller];
2715 info.addr = i2c_addr >> 1;
2716 strlcpy(info.type, name, sizeof(info.type));
2717 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2718 }
2719 }
c41b9ee9
AD		 2720 } else {
2721 /* boards with a thermal chip, but no overdrive table */
2722
2723 /* Asus 9600xt has an f75375 on the monid bus */
2724 if ((dev->pdev->device == 0x4152) &&
2725 (dev->pdev->subsystem_vendor == 0x1043) &&
2726 (dev->pdev->subsystem_device == 0xc002)) {
2727 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2728 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2729 if (rdev->pm.i2c_bus) {
2730 struct i2c_board_info info = { };
2731 const char *name = "f75375";
2732 info.addr = 0x28;
2733 strlcpy(info.type, name, sizeof(info.type));
2734 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2735 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2736 name, info.addr);
2737 }
2738 }
63f7d982
AD		 2739 }
2740
56278a8e
AD		 2741 if (rdev->flags & RADEON_IS_MOBILITY) {
2742 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2743 if (offset) {
2744 rev = RBIOS8(offset);
2745 blocks = RBIOS8(offset + 0x2);
2746 /* power mode 0 tends to be the only valid one */
2747 rdev->pm.power_state[state_index].num_clock_modes = 1;
2748 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2749 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2750 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2751 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2752 goto default_mode;
0ec0e74f
AD		 2753 rdev->pm.power_state[state_index].type =
2754 POWER_STATE_TYPE_BATTERY;
56278a8e
AD		 2755 misc = RBIOS16(offset + 0x5 + 0x0);
2756 if (rev > 4)
2757 misc2 = RBIOS16(offset + 0x5 + 0xe);
79daedc9
AD		 2758 rdev->pm.power_state[state_index].misc = misc;
2759 rdev->pm.power_state[state_index].misc2 = misc2;
56278a8e
AD		 2760 if (misc & 0x4) {
2761 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2762 if (misc & 0x8)
2763 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2764 true;
2765 else
2766 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2767 false;
2768 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2769 if (rev < 6) {
2770 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2771 RBIOS16(offset + 0x5 + 0xb) * 4;
2772 tmp = RBIOS8(offset + 0x5 + 0xd);
2773 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2774 } else {
2775 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2776 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2777 if (entries && voltage_table_offset) {
2778 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2779 RBIOS16(voltage_table_offset) * 4;
2780 tmp = RBIOS8(voltage_table_offset + 0x2);
2781 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2782 } else
2783 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2784 }
2785 switch ((misc2 & 0x700) >> 8) {
2786 case 0:
2787 default:
2788 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2789 break;
2790 case 1:
2791 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2792 break;
2793 case 2:
2794 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2795 break;
2796 case 3:
2797 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2798 break;
2799 case 4:
2800 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2801 break;
2802 }
2803 } else
2804 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2805 if (rev > 6)
79daedc9 2806 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e 2807 RBIOS8(offset + 0x5 + 0x10);
d7311171 2808 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e
AD		 2809 state_index++;
2810 } else {
2811 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2812 }
2813 } else {
2814 /* XXX figure out some good default low power mode for desktop cards */
2815 }
2816
2817default_mode:
2818 /* add the default mode */
0ec0e74f
AD		 2819 rdev->pm.power_state[state_index].type =
2820 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 2821 rdev->pm.power_state[state_index].num_clock_modes = 1;
2822 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2823 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2824 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
84d88f4c 2825 if ((state_index > 0) &&
8de016e2 2826 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
84d88f4c
AD		 2827 rdev->pm.power_state[state_index].clock_info[0].voltage =
2828 rdev->pm.power_state[0].clock_info[0].voltage;
2829 else
2830 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
79daedc9 2831 rdev->pm.power_state[state_index].pcie_lanes = 16;
a48b9b4e
AD		 2832 rdev->pm.power_state[state_index].flags = 0;
2833 rdev->pm.default_power_state_index = state_index;
56278a8e 2834 rdev->pm.num_power_states = state_index + 1;
9038dfdf 2835
a7c36fd8
AD		 2836 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2837 rdev->pm.current_clock_mode_index = 0;
2838 return;
2839
2840pm_failed:
2841 rdev->pm.default_power_state_index = state_index;
2842 rdev->pm.num_power_states = 0;
2843
a48b9b4e
AD		 2844 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2845 rdev->pm.current_clock_mode_index = 0;
56278a8e
AD		 2846}
2847
fcec570b
AD		 2848void radeon_external_tmds_setup(struct drm_encoder *encoder)
2849{
2850 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2851 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2852
2853 if (!tmds)
2854 return;
2855
2856 switch (tmds->dvo_chip) {
2857 case DVO_SIL164:
2858 /* sil 164 */
5a6f98f5
AD		 2859 radeon_i2c_put_byte(tmds->i2c_bus,
2860 tmds->slave_addr,
2861 0x08, 0x30);
2862 radeon_i2c_put_byte(tmds->i2c_bus,
fcec570b
AD		 2863 tmds->slave_addr,
2864 0x09, 0x00);
5a6f98f5
AD		 2865 radeon_i2c_put_byte(tmds->i2c_bus,
2866 tmds->slave_addr,
2867 0x0a, 0x90);
2868 radeon_i2c_put_byte(tmds->i2c_bus,
2869 tmds->slave_addr,
2870 0x0c, 0x89);
2871 radeon_i2c_put_byte(tmds->i2c_bus,
fcec570b
AD		 2872 tmds->slave_addr,
2873 0x08, 0x3b);
fcec570b
AD		 2874 break;
2875 case DVO_SIL1178:
2876 /* sil 1178 - untested */
2877 /*
2878 * 0x0f, 0x44
2879 * 0x0f, 0x4c
2880 * 0x0e, 0x01
2881 * 0x0a, 0x80
2882 * 0x09, 0x30
2883 * 0x0c, 0xc9
2884 * 0x0d, 0x70
2885 * 0x08, 0x32
2886 * 0x08, 0x33
2887 */
2888 break;
2889 default:
2890 break;
2891 }
2892
2893}
2894
2895bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2896{
2897 struct drm_device *dev = encoder->dev;
2898 struct radeon_device *rdev = dev->dev_private;
2899 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2900 uint16_t offset;
2901 uint8_t blocks, slave_addr, rev;
2902 uint32_t index, id;
2903 uint32_t reg, val, and_mask, or_mask;
2904 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2905
fcec570b
AD		 2906 if (!tmds)
2907 return false;
2908
2909 if (rdev->flags & RADEON_IS_IGP) {
2910 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2911 rev = RBIOS8(offset);
2912 if (offset) {
2913 rev = RBIOS8(offset);
2914 if (rev > 1) {
2915 blocks = RBIOS8(offset + 3);
2916 index = offset + 4;
2917 while (blocks > 0) {
2918 id = RBIOS16(index);
2919 index += 2;
2920 switch (id >> 13) {
2921 case 0:
2922 reg = (id & 0x1fff) * 4;
2923 val = RBIOS32(index);
2924 index += 4;
2925 WREG32(reg, val);
2926 break;
2927 case 2:
2928 reg = (id & 0x1fff) * 4;
2929 and_mask = RBIOS32(index);
2930 index += 4;
2931 or_mask = RBIOS32(index);
2932 index += 4;
2933 val = RREG32(reg);
2934 val = (val & and_mask) | or_mask;
2935 WREG32(reg, val);
2936 break;
2937 case 3:
2938 val = RBIOS16(index);
2939 index += 2;
2940 udelay(val);
2941 break;
2942 case 4:
2943 val = RBIOS16(index);
2944 index += 2;
4de833c3 2945 mdelay(val);
fcec570b
AD		 2946 break;
2947 case 6:
2948 slave_addr = id & 0xff;
2949 slave_addr >>= 1; /* 7 bit addressing */
2950 index++;
2951 reg = RBIOS8(index);
2952 index++;
2953 val = RBIOS8(index);
2954 index++;
5a6f98f5
AD		 2955 radeon_i2c_put_byte(tmds->i2c_bus,
2956 slave_addr,
2957 reg, val);
fcec570b
AD		 2958 break;
2959 default:
2960 DRM_ERROR("Unknown id %d\n", id >> 13);
2961 break;
2962 }
2963 blocks--;
2964 }
2965 return true;
2966 }
2967 }
2968 } else {
2969 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2970 if (offset) {
2971 index = offset + 10;
2972 id = RBIOS16(index);
2973 while (id != 0xffff) {
2974 index += 2;
2975 switch (id >> 13) {
2976 case 0:
2977 reg = (id & 0x1fff) * 4;
2978 val = RBIOS32(index);
2979 WREG32(reg, val);
2980 break;
2981 case 2:
2982 reg = (id & 0x1fff) * 4;
2983 and_mask = RBIOS32(index);
2984 index += 4;
2985 or_mask = RBIOS32(index);
2986 index += 4;
2987 val = RREG32(reg);
2988 val = (val & and_mask) | or_mask;
2989 WREG32(reg, val);
2990 break;
2991 case 4:
2992 val = RBIOS16(index);
2993 index += 2;
2994 udelay(val);
2995 break;
2996 case 5:
2997 reg = id & 0x1fff;
2998 and_mask = RBIOS32(index);
2999 index += 4;
3000 or_mask = RBIOS32(index);
3001 index += 4;
3002 val = RREG32_PLL(reg);
3003 val = (val & and_mask) | or_mask;
3004 WREG32_PLL(reg, val);
3005 break;
3006 case 6:
3007 reg = id & 0x1fff;
3008 val = RBIOS8(index);
3009 index += 1;
5a6f98f5
AD		 3010 radeon_i2c_put_byte(tmds->i2c_bus,
3011 tmds->slave_addr,
3012 reg, val);
fcec570b
AD		 3013 break;
3014 default:
3015 DRM_ERROR("Unknown id %d\n", id >> 13);
3016 break;
3017 }
3018 id = RBIOS16(index);
3019 }
3020 return true;
3021 }
3022 }
3023 return false;
3024}
3025
771fe6b9
JG		 3026static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
3027{
3028 struct radeon_device *rdev = dev->dev_private;
3029
3030 if (offset) {
3031 while (RBIOS16(offset)) {
3032 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
3033 uint32_t addr = (RBIOS16(offset) & 0x1fff);
3034 uint32_t val, and_mask, or_mask;
3035 uint32_t tmp;
3036
3037 offset += 2;
3038 switch (cmd) {
3039 case 0:
3040 val = RBIOS32(offset);
3041 offset += 4;
3042 WREG32(addr, val);
3043 break;
3044 case 1:
3045 val = RBIOS32(offset);
3046 offset += 4;
3047 WREG32(addr, val);
3048 break;
3049 case 2:
3050 and_mask = RBIOS32(offset);
3051 offset += 4;
3052 or_mask = RBIOS32(offset);
3053 offset += 4;
3054 tmp = RREG32(addr);
3055 tmp &= and_mask;
3056 tmp |= or_mask;
3057 WREG32(addr, tmp);
3058 break;
3059 case 3:
3060 and_mask = RBIOS32(offset);
3061 offset += 4;
3062 or_mask = RBIOS32(offset);
3063 offset += 4;
3064 tmp = RREG32(addr);
3065 tmp &= and_mask;
3066 tmp |= or_mask;
3067 WREG32(addr, tmp);
3068 break;
3069 case 4:
3070 val = RBIOS16(offset);
3071 offset += 2;
3072 udelay(val);
3073 break;
3074 case 5:
3075 val = RBIOS16(offset);
3076 offset += 2;
3077 switch (addr) {
3078 case 8:
3079 while (val--) {
3080 if (!
3081 (RREG32_PLL
3082 (RADEON_CLK_PWRMGT_CNTL) &
3083 RADEON_MC_BUSY))
3084 break;
3085 }
3086 break;
3087 case 9:
3088 while (val--) {
3089 if ((RREG32(RADEON_MC_STATUS) &
3090 RADEON_MC_IDLE))
3091 break;
3092 }
3093 break;
3094 default:
3095 break;
3096 }
3097 break;
3098 default:
3099 break;
3100 }
3101 }
3102 }
3103}
3104
3105static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3106{
3107 struct radeon_device *rdev = dev->dev_private;
3108
3109 if (offset) {
3110 while (RBIOS8(offset)) {
3111 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
3112 uint8_t addr = (RBIOS8(offset) & 0x3f);
3113 uint32_t val, shift, tmp;
3114 uint32_t and_mask, or_mask;
3115
3116 offset++;
3117 switch (cmd) {
3118 case 0:
3119 val = RBIOS32(offset);
3120 offset += 4;
3121 WREG32_PLL(addr, val);
3122 break;
3123 case 1:
3124 shift = RBIOS8(offset) * 8;
3125 offset++;
3126 and_mask = RBIOS8(offset) << shift;
3127 and_mask |= ~(0xff << shift);
3128 offset++;
3129 or_mask = RBIOS8(offset) << shift;
3130 offset++;
3131 tmp = RREG32_PLL(addr);
3132 tmp &= and_mask;
3133 tmp |= or_mask;
3134 WREG32_PLL(addr, tmp);
3135 break;
3136 case 2:
3137 case 3:
3138 tmp = 1000;
3139 switch (addr) {
3140 case 1:
3141 udelay(150);
3142 break;
3143 case 2:
4de833c3 3144 mdelay(1);
771fe6b9
JG		 3145 break;
3146 case 3:
3147 while (tmp--) {
3148 if (!
3149 (RREG32_PLL
3150 (RADEON_CLK_PWRMGT_CNTL) &
3151 RADEON_MC_BUSY))
3152 break;
3153 }
3154 break;
3155 case 4:
3156 while (tmp--) {
3157 if (RREG32_PLL
3158 (RADEON_CLK_PWRMGT_CNTL) &
3159 RADEON_DLL_READY)
3160 break;
3161 }
3162 break;
3163 case 5:
3164 tmp =
3165 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3166 if (tmp & RADEON_CG_NO1_DEBUG_0) {
3167#if 0
3168 uint32_t mclk_cntl =
3169 RREG32_PLL
3170 (RADEON_MCLK_CNTL);
3171 mclk_cntl &= 0xffff0000;
3172 /*mclk_cntl |= 0x00001111;*//* ??? */
3173 WREG32_PLL(RADEON_MCLK_CNTL,
3174 mclk_cntl);
4de833c3 3175 mdelay(10);
771fe6b9
JG		 3176#endif
3177 WREG32_PLL
3178 (RADEON_CLK_PWRMGT_CNTL,
3179 tmp &
3180 ~RADEON_CG_NO1_DEBUG_0);
4de833c3 3181 mdelay(10);
771fe6b9
JG		 3182 }
3183 break;
3184 default:
3185 break;
3186 }
3187 break;
3188 default:
3189 break;
3190 }
3191 }
3192 }
3193}
3194
3195static void combios_parse_ram_reset_table(struct drm_device *dev,
3196 uint16_t offset)
3197{
3198 struct radeon_device *rdev = dev->dev_private;
3199 uint32_t tmp;
3200
3201 if (offset) {
3202 uint8_t val = RBIOS8(offset);
3203 while (val != 0xff) {
3204 offset++;
3205
3206 if (val == 0x0f) {
3207 uint32_t channel_complete_mask;
3208
3209 if (ASIC_IS_R300(rdev))
3210 channel_complete_mask =
3211 R300_MEM_PWRUP_COMPLETE;
3212 else
3213 channel_complete_mask =
3214 RADEON_MEM_PWRUP_COMPLETE;
3215 tmp = 20000;
3216 while (tmp--) {
3217 if ((RREG32(RADEON_MEM_STR_CNTL) &
3218 channel_complete_mask) ==
3219 channel_complete_mask)
3220 break;
3221 }
3222 } else {
3223 uint32_t or_mask = RBIOS16(offset);
3224 offset += 2;
3225
3226 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3227 tmp &= RADEON_SDRAM_MODE_MASK;
3228 tmp |= or_mask;
3229 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3230
3231 or_mask = val << 24;
3232 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3233 tmp &= RADEON_B3MEM_RESET_MASK;
3234 tmp |= or_mask;
3235 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3236 }
3237 val = RBIOS8(offset);
3238 }
3239 }
3240}
3241
3242static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3243 int mem_addr_mapping)
3244{
3245 struct radeon_device *rdev = dev->dev_private;
3246 uint32_t mem_cntl;
3247 uint32_t mem_size;
3248 uint32_t addr = 0;
3249
3250 mem_cntl = RREG32(RADEON_MEM_CNTL);
3251 if (mem_cntl & RV100_HALF_MODE)
3252 ram /= 2;
3253 mem_size = ram;
3254 mem_cntl &= ~(0xff << 8);
3255 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3256 WREG32(RADEON_MEM_CNTL, mem_cntl);
3257 RREG32(RADEON_MEM_CNTL);
3258
3259 /* sdram reset ? */
3260
3261 /* something like this???? */
3262 while (ram--) {
3263 addr = ram * 1024 * 1024;
3264 /* write to each page */
2ef9bdfe 3265 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef);
771fe6b9 3266 /* read back and verify */
2ef9bdfe 3267 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef)
771fe6b9
JG		 3268 return 0;
3269 }
3270
3271 return mem_size;
3272}
3273
3274static void combios_write_ram_size(struct drm_device *dev)
3275{
3276 struct radeon_device *rdev = dev->dev_private;
3277 uint8_t rev;
3278 uint16_t offset;
3279 uint32_t mem_size = 0;
3280 uint32_t mem_cntl = 0;
3281
3282 /* should do something smarter here I guess... */
3283 if (rdev->flags & RADEON_IS_IGP)
3284 return;
3285
3286 /* first check detected mem table */
3287 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3288 if (offset) {
3289 rev = RBIOS8(offset);
3290 if (rev < 3) {
3291 mem_cntl = RBIOS32(offset + 1);
3292 mem_size = RBIOS16(offset + 5);
4ce9198e
AD		 3293 if ((rdev->family < CHIP_R200) &&
3294 !ASIC_IS_RN50(rdev))
771fe6b9
JG		 3295 WREG32(RADEON_MEM_CNTL, mem_cntl);
3296 }
3297 }
3298
3299 if (!mem_size) {
3300 offset =
3301 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3302 if (offset) {
3303 rev = RBIOS8(offset - 1);
3304 if (rev < 1) {
4ce9198e
AD		 3305 if ((rdev->family < CHIP_R200)
3306 && !ASIC_IS_RN50(rdev)) {
771fe6b9
JG		 3307 int ram = 0;
3308 int mem_addr_mapping = 0;
3309
3310 while (RBIOS8(offset)) {
3311 ram = RBIOS8(offset);
3312 mem_addr_mapping =
3313 RBIOS8(offset + 1);
3314 if (mem_addr_mapping != 0x25)
3315 ram *= 2;
3316 mem_size =
3317 combios_detect_ram(dev, ram,
3318 mem_addr_mapping);
3319 if (mem_size)
3320 break;
3321 offset += 2;
3322 }
3323 } else
3324 mem_size = RBIOS8(offset);
3325 } else {
3326 mem_size = RBIOS8(offset);
3327 mem_size *= 2; /* convert to MB */
3328 }
3329 }
3330 }
3331
3332 mem_size *= (1024 * 1024); /* convert to bytes */
3333 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3334}
3335
771fe6b9
JG		 3336void radeon_combios_asic_init(struct drm_device *dev)
3337{
3338 struct radeon_device *rdev = dev->dev_private;
3339 uint16_t table;
3340
3341 /* port hardcoded mac stuff from radeonfb */
3342 if (rdev->bios == NULL)
3343 return;
3344
3345 /* ASIC INIT 1 */
3346 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3347 if (table)
3348 combios_parse_mmio_table(dev, table);
3349
3350 /* PLL INIT */
3351 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3352 if (table)
3353 combios_parse_pll_table(dev, table);
3354
3355 /* ASIC INIT 2 */
3356 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3357 if (table)
3358 combios_parse_mmio_table(dev, table);
3359
3360 if (!(rdev->flags & RADEON_IS_IGP)) {
3361 /* ASIC INIT 4 */
3362 table =
3363 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3364 if (table)
3365 combios_parse_mmio_table(dev, table);
3366
3367 /* RAM RESET */
3368 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3369 if (table)
3370 combios_parse_ram_reset_table(dev, table);
3371
3372 /* ASIC INIT 3 */
3373 table =
3374 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3375 if (table)
3376 combios_parse_mmio_table(dev, table);
3377
3378 /* write CONFIG_MEMSIZE */
3379 combios_write_ram_size(dev);
3380 }
3381
580b4fff
DA		 3382 /* quirk for rs4xx HP nx6125 laptop to make it resume
3383 * - it hangs on resume inside the dynclk 1 table.
3384 */
3385 if (rdev->family == CHIP_RS480 &&
3386 rdev->pdev->subsystem_vendor == 0x103c &&
3387 rdev->pdev->subsystem_device == 0x308b)
3388 return;
3389
52fa2bbc
AD		 3390 /* quirk for rs4xx HP dv5000 laptop to make it resume
3391 * - it hangs on resume inside the dynclk 1 table.
3392 */
3393 if (rdev->family == CHIP_RS480 &&
3394 rdev->pdev->subsystem_vendor == 0x103c &&
3395 rdev->pdev->subsystem_device == 0x30a4)
3396 return;
3397
302a8e8b
AD		 3398 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3399 * - it hangs on resume inside the dynclk 1 table.
3400 */
3401 if (rdev->family == CHIP_RS480 &&
3402 rdev->pdev->subsystem_vendor == 0x103c &&
3403 rdev->pdev->subsystem_device == 0x30ae)
3404 return;
3405
1d6c4573
JM		 3406 /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume
3407 * - it hangs on resume inside the dynclk 1 table.
3408 */
3409 if (rdev->family == CHIP_RS480 &&
3410 rdev->pdev->subsystem_vendor == 0x103c &&
3411 rdev->pdev->subsystem_device == 0x280a)
3412 return;
3413
771fe6b9
JG		 3414 /* DYN CLK 1 */
3415 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3416 if (table)
3417 combios_parse_pll_table(dev, table);
3418
3419}
3420
3421void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3422{
3423 struct radeon_device *rdev = dev->dev_private;
3424 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3425
3426 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3427 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3428 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3429
3430 /* let the bios control the backlight */
3431 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3432
3433 /* tell the bios not to handle mode switching */
3434 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3435 RADEON_ACC_MODE_CHANGE);
3436
3437 /* tell the bios a driver is loaded */
3438 bios_7_scratch |= RADEON_DRV_LOADED;
3439
3440 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3441 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3442 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3443}
3444
3445void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3446{
3447 struct drm_device *dev = encoder->dev;
3448 struct radeon_device *rdev = dev->dev_private;
3449 uint32_t bios_6_scratch;
3450
3451 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3452
3453 if (lock)
3454 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3455 else
3456 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3457
3458 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3459}
3460
3461void
3462radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3463 struct drm_encoder *encoder,
3464 bool connected)
3465{
3466 struct drm_device *dev = connector->dev;
3467 struct radeon_device *rdev = dev->dev_private;
3468 struct radeon_connector *radeon_connector =
3469 to_radeon_connector(connector);
3470 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3471 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3472 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3473
3474 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3475 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3476 if (connected) {
d9fdaafb 3477 DRM_DEBUG_KMS("TV1 connected\n");
771fe6b9
JG		 3478 /* fix me */
3479 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3480 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3481 bios_5_scratch |= RADEON_TV1_ON;
3482 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3483 } else {
d9fdaafb 3484 DRM_DEBUG_KMS("TV1 disconnected\n");
771fe6b9
JG		 3485 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3486 bios_5_scratch &= ~RADEON_TV1_ON;
3487 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3488 }
3489 }
3490 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3491 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3492 if (connected) {
d9fdaafb 3493 DRM_DEBUG_KMS("LCD1 connected\n");
771fe6b9
JG		 3494 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3495 bios_5_scratch |= RADEON_LCD1_ON;
3496 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3497 } else {
d9fdaafb 3498 DRM_DEBUG_KMS("LCD1 disconnected\n");
771fe6b9
JG		 3499 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3500 bios_5_scratch &= ~RADEON_LCD1_ON;
3501 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3502 }
3503 }
3504 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3505 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3506 if (connected) {
d9fdaafb 3507 DRM_DEBUG_KMS("CRT1 connected\n");
771fe6b9
JG		 3508 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3509 bios_5_scratch |= RADEON_CRT1_ON;
3510 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3511 } else {
d9fdaafb 3512 DRM_DEBUG_KMS("CRT1 disconnected\n");
771fe6b9
JG		 3513 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3514 bios_5_scratch &= ~RADEON_CRT1_ON;
3515 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3516 }
3517 }
3518 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3519 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3520 if (connected) {
d9fdaafb 3521 DRM_DEBUG_KMS("CRT2 connected\n");
771fe6b9
JG		 3522 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3523 bios_5_scratch |= RADEON_CRT2_ON;
3524 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3525 } else {
d9fdaafb 3526 DRM_DEBUG_KMS("CRT2 disconnected\n");
771fe6b9
JG		 3527 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3528 bios_5_scratch &= ~RADEON_CRT2_ON;
3529 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3530 }
3531 }
3532 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3533 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3534 if (connected) {
d9fdaafb 3535 DRM_DEBUG_KMS("DFP1 connected\n");
771fe6b9
JG		 3536 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3537 bios_5_scratch |= RADEON_DFP1_ON;
3538 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3539 } else {
d9fdaafb 3540 DRM_DEBUG_KMS("DFP1 disconnected\n");
771fe6b9
JG		 3541 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3542 bios_5_scratch &= ~RADEON_DFP1_ON;
3543 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3544 }
3545 }
3546 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3547 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3548 if (connected) {
d9fdaafb 3549 DRM_DEBUG_KMS("DFP2 connected\n");
771fe6b9
JG		 3550 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3551 bios_5_scratch |= RADEON_DFP2_ON;
3552 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3553 } else {
d9fdaafb 3554 DRM_DEBUG_KMS("DFP2 disconnected\n");
771fe6b9
JG		 3555 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3556 bios_5_scratch &= ~RADEON_DFP2_ON;
3557 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3558 }
3559 }
3560 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3561 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3562}
3563
3564void
3565radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3566{
3567 struct drm_device *dev = encoder->dev;
3568 struct radeon_device *rdev = dev->dev_private;
3569 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3570 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3571
3572 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3573 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3574 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3575 }
3576 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3577 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3578 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3579 }
3580 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3581 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3582 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3583 }
3584 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3585 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3586 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3587 }
3588 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3589 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3590 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3591 }
3592 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3593 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3594 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3595 }
3596 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3597}
3598
3599void
3600radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3601{
3602 struct drm_device *dev = encoder->dev;
3603 struct radeon_device *rdev = dev->dev_private;
3604 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3605 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3606
3607 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3608 if (on)
3609 bios_6_scratch |= RADEON_TV_DPMS_ON;
3610 else
3611 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3612 }
3613 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3614 if (on)
3615 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3616 else
3617 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3618 }
3619 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3620 if (on)
3621 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3622 else
3623 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3624 }
3625 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3626 if (on)
3627 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3628 else
3629 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3630 }
3631 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3632}
kernel source for telekom puls (alcatel/mediatek)