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drm/radeon: fix a couple of array index errors
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon_combios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27#include "drmP.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32#ifdef CONFIG_PPC_PMAC
33/* not sure which of these are needed */
34#include <asm/machdep.h>
35#include <asm/pmac_feature.h>
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#endif /* CONFIG_PPC_PMAC */
39
40/* from radeon_encoder.c */
41extern uint32_t
42radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
44extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46/* from radeon_connector.c */
47extern void
48radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
b75fad06 52 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
771fe6b9
JG		 55
56/* from radeon_legacy_encoder.c */
57extern void
58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
59 uint32_t supported_device);
60
61/* old legacy ATI BIOS routines */
62
63/* COMBIOS table offsets */
64enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
112};
113
114enum radeon_combios_ddc {
115 DDC_NONE_DETECTED,
116 DDC_MONID,
117 DDC_DVI,
118 DDC_VGA,
119 DDC_CRT2,
120 DDC_LCD,
121 DDC_GPIO,
122};
123
124enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
133};
134
135const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
144};
145
146static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
148{
149 struct radeon_device *rdev = dev->dev_private;
150 int rev;
151 uint16_t offset = 0, check_offset;
152
153 switch (table) {
154 /* absolute offset tables */
155 case COMBIOS_ASIC_INIT_1_TABLE:
156 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
157 if (check_offset)
158 offset = check_offset;
159 break;
160 case COMBIOS_BIOS_SUPPORT_TABLE:
161 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
162 if (check_offset)
163 offset = check_offset;
164 break;
165 case COMBIOS_DAC_PROGRAMMING_TABLE:
166 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
167 if (check_offset)
168 offset = check_offset;
169 break;
170 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
171 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
172 if (check_offset)
173 offset = check_offset;
174 break;
175 case COMBIOS_CRTC_INFO_TABLE:
176 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
177 if (check_offset)
178 offset = check_offset;
179 break;
180 case COMBIOS_PLL_INFO_TABLE:
181 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
182 if (check_offset)
183 offset = check_offset;
184 break;
185 case COMBIOS_TV_INFO_TABLE:
186 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
187 if (check_offset)
188 offset = check_offset;
189 break;
190 case COMBIOS_DFP_INFO_TABLE:
191 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
192 if (check_offset)
193 offset = check_offset;
194 break;
195 case COMBIOS_HW_CONFIG_INFO_TABLE:
196 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
197 if (check_offset)
198 offset = check_offset;
199 break;
200 case COMBIOS_MULTIMEDIA_INFO_TABLE:
201 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
202 if (check_offset)
203 offset = check_offset;
204 break;
205 case COMBIOS_TV_STD_PATCH_TABLE:
206 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
207 if (check_offset)
208 offset = check_offset;
209 break;
210 case COMBIOS_LCD_INFO_TABLE:
211 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
212 if (check_offset)
213 offset = check_offset;
214 break;
215 case COMBIOS_MOBILE_INFO_TABLE:
216 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
217 if (check_offset)
218 offset = check_offset;
219 break;
220 case COMBIOS_PLL_INIT_TABLE:
221 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
222 if (check_offset)
223 offset = check_offset;
224 break;
225 case COMBIOS_MEM_CONFIG_TABLE:
226 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
227 if (check_offset)
228 offset = check_offset;
229 break;
230 case COMBIOS_SAVE_MASK_TABLE:
231 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
232 if (check_offset)
233 offset = check_offset;
234 break;
235 case COMBIOS_HARDCODED_EDID_TABLE:
236 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
237 if (check_offset)
238 offset = check_offset;
239 break;
240 case COMBIOS_ASIC_INIT_2_TABLE:
241 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
242 if (check_offset)
243 offset = check_offset;
244 break;
245 case COMBIOS_CONNECTOR_INFO_TABLE:
246 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
247 if (check_offset)
248 offset = check_offset;
249 break;
250 case COMBIOS_DYN_CLK_1_TABLE:
251 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
252 if (check_offset)
253 offset = check_offset;
254 break;
255 case COMBIOS_RESERVED_MEM_TABLE:
256 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
257 if (check_offset)
258 offset = check_offset;
259 break;
260 case COMBIOS_EXT_TMDS_INFO_TABLE:
261 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
262 if (check_offset)
263 offset = check_offset;
264 break;
265 case COMBIOS_MEM_CLK_INFO_TABLE:
266 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
267 if (check_offset)
268 offset = check_offset;
269 break;
270 case COMBIOS_EXT_DAC_INFO_TABLE:
271 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
272 if (check_offset)
273 offset = check_offset;
274 break;
275 case COMBIOS_MISC_INFO_TABLE:
276 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
277 if (check_offset)
278 offset = check_offset;
279 break;
280 case COMBIOS_CRT_INFO_TABLE:
281 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
282 if (check_offset)
283 offset = check_offset;
284 break;
285 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
286 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
287 if (check_offset)
288 offset = check_offset;
289 break;
290 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
291 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
292 if (check_offset)
293 offset = check_offset;
294 break;
295 case COMBIOS_FAN_SPEED_INFO_TABLE:
296 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
297 if (check_offset)
298 offset = check_offset;
299 break;
300 case COMBIOS_OVERDRIVE_INFO_TABLE:
301 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
302 if (check_offset)
303 offset = check_offset;
304 break;
305 case COMBIOS_OEM_INFO_TABLE:
306 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
307 if (check_offset)
308 offset = check_offset;
309 break;
310 case COMBIOS_DYN_CLK_2_TABLE:
311 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
312 if (check_offset)
313 offset = check_offset;
314 break;
315 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
316 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
317 if (check_offset)
318 offset = check_offset;
319 break;
320 case COMBIOS_I2C_INFO_TABLE:
321 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
322 if (check_offset)
323 offset = check_offset;
324 break;
325 /* relative offset tables */
326 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
327 check_offset =
328 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
329 if (check_offset) {
330 rev = RBIOS8(check_offset);
331 if (rev > 0) {
332 check_offset = RBIOS16(check_offset + 0x3);
333 if (check_offset)
334 offset = check_offset;
335 }
336 }
337 break;
338 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
339 check_offset =
340 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
341 if (check_offset) {
342 rev = RBIOS8(check_offset);
343 if (rev > 0) {
344 check_offset = RBIOS16(check_offset + 0x5);
345 if (check_offset)
346 offset = check_offset;
347 }
348 }
349 break;
350 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
351 check_offset =
352 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
353 if (check_offset) {
354 rev = RBIOS8(check_offset);
355 if (rev > 0) {
356 check_offset = RBIOS16(check_offset + 0x7);
357 if (check_offset)
358 offset = check_offset;
359 }
360 }
361 break;
362 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
363 check_offset =
364 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
365 if (check_offset) {
366 rev = RBIOS8(check_offset);
367 if (rev == 2) {
368 check_offset = RBIOS16(check_offset + 0x9);
369 if (check_offset)
370 offset = check_offset;
371 }
372 }
373 break;
374 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
375 check_offset =
376 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
377 if (check_offset) {
378 while (RBIOS8(check_offset++));
379 check_offset += 2;
380 if (check_offset)
381 offset = check_offset;
382 }
383 break;
384 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
385 check_offset =
386 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
387 if (check_offset) {
388 check_offset = RBIOS16(check_offset + 0x11);
389 if (check_offset)
390 offset = check_offset;
391 }
392 break;
393 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
394 check_offset =
395 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
396 if (check_offset) {
397 check_offset = RBIOS16(check_offset + 0x13);
398 if (check_offset)
399 offset = check_offset;
400 }
401 break;
402 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
403 check_offset =
404 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
405 if (check_offset) {
406 check_offset = RBIOS16(check_offset + 0x15);
407 if (check_offset)
408 offset = check_offset;
409 }
410 break;
411 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
412 check_offset =
413 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
414 if (check_offset) {
415 check_offset = RBIOS16(check_offset + 0x17);
416 if (check_offset)
417 offset = check_offset;
418 }
419 break;
420 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
421 check_offset =
422 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
423 if (check_offset) {
424 check_offset = RBIOS16(check_offset + 0x2);
425 if (check_offset)
426 offset = check_offset;
427 }
428 break;
429 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
430 check_offset =
431 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
432 if (check_offset) {
433 check_offset = RBIOS16(check_offset + 0x4);
434 if (check_offset)
435 offset = check_offset;
436 }
437 break;
438 default:
439 break;
440 }
441
442 return offset;
443
444}
445
6a93cb25
AD		 446static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
447 int ddc_line)
771fe6b9
JG		 448{
449 struct radeon_i2c_bus_rec i2c;
450
6a93cb25
AD		 451 if (ddc_line == RADEON_GPIOPAD_MASK) {
452 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
453 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
454 i2c.a_clk_reg = RADEON_GPIOPAD_A;
455 i2c.a_data_reg = RADEON_GPIOPAD_A;
456 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
457 i2c.en_data_reg = RADEON_GPIOPAD_EN;
458 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
459 i2c.y_data_reg = RADEON_GPIOPAD_Y;
460 } else if (ddc_line == RADEON_MDGPIO_MASK) {
461 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
462 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
463 i2c.a_clk_reg = RADEON_MDGPIO_A;
464 i2c.a_data_reg = RADEON_MDGPIO_A;
465 i2c.en_clk_reg = RADEON_MDGPIO_EN;
466 i2c.en_data_reg = RADEON_MDGPIO_EN;
467 i2c.y_clk_reg = RADEON_MDGPIO_Y;
468 i2c.y_data_reg = RADEON_MDGPIO_Y;
771fe6b9 469 } else {
6a93cb25
AD		 470 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
471 i2c.mask_data_mask = RADEON_GPIO_EN_0;
472 i2c.a_clk_mask = RADEON_GPIO_A_1;
473 i2c.a_data_mask = RADEON_GPIO_A_0;
474 i2c.en_clk_mask = RADEON_GPIO_EN_1;
475 i2c.en_data_mask = RADEON_GPIO_EN_0;
476 i2c.y_clk_mask = RADEON_GPIO_Y_1;
477 i2c.y_data_mask = RADEON_GPIO_Y_0;
478
771fe6b9
JG		 479 i2c.mask_clk_reg = ddc_line;
480 i2c.mask_data_reg = ddc_line;
481 i2c.a_clk_reg = ddc_line;
482 i2c.a_data_reg = ddc_line;
9b9fe724
AD		 483 i2c.en_clk_reg = ddc_line;
484 i2c.en_data_reg = ddc_line;
485 i2c.y_clk_reg = ddc_line;
486 i2c.y_data_reg = ddc_line;
771fe6b9
JG		 487 }
488
6a93cb25
AD		 489 if (rdev->family < CHIP_R200)
490 i2c.hw_capable = false;
491 else {
492 switch (ddc_line) {
493 case RADEON_GPIO_VGA_DDC:
494 case RADEON_GPIO_DVI_DDC:
495 i2c.hw_capable = true;
496 break;
497 case RADEON_GPIO_MONID:
498 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
499 * reliably on some pre-r4xx hardware; not sure why.
500 */
501 i2c.hw_capable = false;
502 break;
503 default:
504 i2c.hw_capable = false;
505 break;
506 }
507 }
508 i2c.mm_i2c = false;
509 i2c.i2c_id = 0;
510
771fe6b9
JG		 511 if (ddc_line)
512 i2c.valid = true;
513 else
514 i2c.valid = false;
515
516 return i2c;
517}
518
519bool radeon_combios_get_clock_info(struct drm_device *dev)
520{
521 struct radeon_device *rdev = dev->dev_private;
522 uint16_t pll_info;
523 struct radeon_pll *p1pll = &rdev->clock.p1pll;
524 struct radeon_pll *p2pll = &rdev->clock.p2pll;
525 struct radeon_pll *spll = &rdev->clock.spll;
526 struct radeon_pll *mpll = &rdev->clock.mpll;
527 int8_t rev;
528 uint16_t sclk, mclk;
529
530 if (rdev->bios == NULL)
4b30b870 531 return false;
771fe6b9
JG		 532
533 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
534 if (pll_info) {
535 rev = RBIOS8(pll_info);
536
537 /* pixel clocks */
538 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
539 p1pll->reference_div = RBIOS16(pll_info + 0x10);
540 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
541 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
542
543 if (rev > 9) {
544 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
545 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
546 } else {
547 p1pll->pll_in_min = 40;
548 p1pll->pll_in_max = 500;
549 }
550 *p2pll = *p1pll;
551
552 /* system clock */
553 spll->reference_freq = RBIOS16(pll_info + 0x1a);
554 spll->reference_div = RBIOS16(pll_info + 0x1c);
555 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
556 spll->pll_out_max = RBIOS32(pll_info + 0x22);
557
558 if (rev > 10) {
559 spll->pll_in_min = RBIOS32(pll_info + 0x48);
560 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
561 } else {
562 /* ??? */
563 spll->pll_in_min = 40;
564 spll->pll_in_max = 500;
565 }
566
567 /* memory clock */
568 mpll->reference_freq = RBIOS16(pll_info + 0x26);
569 mpll->reference_div = RBIOS16(pll_info + 0x28);
570 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
571 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
572
573 if (rev > 10) {
574 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
575 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
576 } else {
577 /* ??? */
578 mpll->pll_in_min = 40;
579 mpll->pll_in_max = 500;
580 }
581
582 /* default sclk/mclk */
583 sclk = RBIOS16(pll_info + 0xa);
584 mclk = RBIOS16(pll_info + 0x8);
585 if (sclk == 0)
586 sclk = 200 * 100;
587 if (mclk == 0)
588 mclk = 200 * 100;
589
590 rdev->clock.default_sclk = sclk;
591 rdev->clock.default_mclk = mclk;
592
593 return true;
594 }
595 return false;
596}
597
246263cc
AD		 598static const uint32_t default_primarydac_adj[CHIP_LAST] = {
599 0x00000808, /* r100 */
600 0x00000808, /* rv100 */
601 0x00000808, /* rs100 */
602 0x00000808, /* rv200 */
603 0x00000808, /* rs200 */
604 0x00000808, /* r200 */
605 0x00000808, /* rv250 */
606 0x00000000, /* rs300 */
607 0x00000808, /* rv280 */
608 0x00000808, /* r300 */
609 0x00000808, /* r350 */
610 0x00000808, /* rv350 */
611 0x00000808, /* rv380 */
612 0x00000808, /* r420 */
613 0x00000808, /* r423 */
614 0x00000808, /* rv410 */
615 0x00000000, /* rs400 */
616 0x00000000, /* rs480 */
617};
618
619static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
620 struct radeon_encoder_primary_dac *p_dac)
621{
622 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
623 return;
624}
625
771fe6b9
JG		 626struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
627 radeon_encoder
628 *encoder)
629{
630 struct drm_device *dev = encoder->base.dev;
631 struct radeon_device *rdev = dev->dev_private;
632 uint16_t dac_info;
633 uint8_t rev, bg, dac;
634 struct radeon_encoder_primary_dac *p_dac = NULL;
246263cc 635 int found = 0;
771fe6b9 636
246263cc
AD		 637 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
638 GFP_KERNEL);
639
640 if (!p_dac)
771fe6b9
JG		 641 return NULL;
642
246263cc
AD		 643 if (rdev->bios == NULL)
644 goto out;
645
771fe6b9
JG		 646 /* check CRT table */
647 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
648 if (dac_info) {
771fe6b9
JG		 649 rev = RBIOS8(dac_info) & 0x3;
650 if (rev < 2) {
651 bg = RBIOS8(dac_info + 0x2) & 0xf;
652 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
653 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
654 } else {
655 bg = RBIOS8(dac_info + 0x2) & 0xf;
656 dac = RBIOS8(dac_info + 0x3) & 0xf;
657 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
658 }
246263cc 659 found = 1;
771fe6b9
JG		 660 }
661
246263cc
AD		 662out:
663 if (!found) /* fallback to defaults */
664 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
665
771fe6b9
JG		 666 return p_dac;
667}
668
d79766fa
AD		 669enum radeon_tv_std
670radeon_combios_get_tv_info(struct radeon_device *rdev)
771fe6b9 671{
d79766fa 672 struct drm_device *dev = rdev->ddev;
771fe6b9
JG		 673 uint16_t tv_info;
674 enum radeon_tv_std tv_std = TV_STD_NTSC;
675
676 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
677 if (tv_info) {
678 if (RBIOS8(tv_info + 6) == 'T') {
679 switch (RBIOS8(tv_info + 7) & 0xf) {
680 case 1:
681 tv_std = TV_STD_NTSC;
682 DRM_INFO("Default TV standard: NTSC\n");
683 break;
684 case 2:
685 tv_std = TV_STD_PAL;
686 DRM_INFO("Default TV standard: PAL\n");
687 break;
688 case 3:
689 tv_std = TV_STD_PAL_M;
690 DRM_INFO("Default TV standard: PAL-M\n");
691 break;
692 case 4:
693 tv_std = TV_STD_PAL_60;
694 DRM_INFO("Default TV standard: PAL-60\n");
695 break;
696 case 5:
697 tv_std = TV_STD_NTSC_J;
698 DRM_INFO("Default TV standard: NTSC-J\n");
699 break;
700 case 6:
701 tv_std = TV_STD_SCART_PAL;
702 DRM_INFO("Default TV standard: SCART-PAL\n");
703 break;
704 default:
705 tv_std = TV_STD_NTSC;
706 DRM_INFO
707 ("Unknown TV standard; defaulting to NTSC\n");
708 break;
709 }
710
711 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
712 case 0:
713 DRM_INFO("29.498928713 MHz TV ref clk\n");
714 break;
715 case 1:
716 DRM_INFO("28.636360000 MHz TV ref clk\n");
717 break;
718 case 2:
719 DRM_INFO("14.318180000 MHz TV ref clk\n");
720 break;
721 case 3:
722 DRM_INFO("27.000000000 MHz TV ref clk\n");
723 break;
724 default:
725 break;
726 }
727 }
728 }
729 return tv_std;
730}
731
732static const uint32_t default_tvdac_adj[CHIP_LAST] = {
733 0x00000000, /* r100 */
734 0x00280000, /* rv100 */
735 0x00000000, /* rs100 */
736 0x00880000, /* rv200 */
737 0x00000000, /* rs200 */
738 0x00000000, /* r200 */
739 0x00770000, /* rv250 */
740 0x00290000, /* rs300 */
741 0x00560000, /* rv280 */
742 0x00780000, /* r300 */
743 0x00770000, /* r350 */
744 0x00780000, /* rv350 */
745 0x00780000, /* rv380 */
746 0x01080000, /* r420 */
747 0x01080000, /* r423 */
748 0x01080000, /* rv410 */
749 0x00780000, /* rs400 */
750 0x00780000, /* rs480 */
751};
752
6a719e05
DA		 753static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
754 struct radeon_encoder_tv_dac *tv_dac)
771fe6b9 755{
771fe6b9
JG		 756 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
757 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
758 tv_dac->ps2_tvdac_adj = 0x00880000;
759 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
760 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 761 return;
771fe6b9
JG		 762}
763
764struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
765 radeon_encoder
766 *encoder)
767{
768 struct drm_device *dev = encoder->base.dev;
769 struct radeon_device *rdev = dev->dev_private;
770 uint16_t dac_info;
771 uint8_t rev, bg, dac;
772 struct radeon_encoder_tv_dac *tv_dac = NULL;
6a719e05
DA		 773 int found = 0;
774
775 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
776 if (!tv_dac)
777 return NULL;
771fe6b9
JG		 778
779 if (rdev->bios == NULL)
6a719e05 780 goto out;
771fe6b9
JG		 781
782 /* first check TV table */
783 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
784 if (dac_info) {
771fe6b9
JG		 785 rev = RBIOS8(dac_info + 0x3);
786 if (rev > 4) {
787 bg = RBIOS8(dac_info + 0xc) & 0xf;
788 dac = RBIOS8(dac_info + 0xd) & 0xf;
789 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
790
791 bg = RBIOS8(dac_info + 0xe) & 0xf;
792 dac = RBIOS8(dac_info + 0xf) & 0xf;
793 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
794
795 bg = RBIOS8(dac_info + 0x10) & 0xf;
796 dac = RBIOS8(dac_info + 0x11) & 0xf;
797 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
6a719e05 798 found = 1;
771fe6b9
JG		 799 } else if (rev > 1) {
800 bg = RBIOS8(dac_info + 0xc) & 0xf;
801 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
802 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
803
804 bg = RBIOS8(dac_info + 0xd) & 0xf;
805 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
806 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
807
808 bg = RBIOS8(dac_info + 0xe) & 0xf;
809 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
810 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
6a719e05 811 found = 1;
771fe6b9 812 }
d79766fa 813 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
6a719e05
DA		 814 }
815 if (!found) {
771fe6b9
JG		 816 /* then check CRT table */
817 dac_info =
818 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
819 if (dac_info) {
771fe6b9
JG		 820 rev = RBIOS8(dac_info) & 0x3;
821 if (rev < 2) {
822 bg = RBIOS8(dac_info + 0x3) & 0xf;
823 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
824 tv_dac->ps2_tvdac_adj =
825 (bg << 16) | (dac << 20);
826 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
827 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 828 found = 1;
771fe6b9
JG		 829 } else {
830 bg = RBIOS8(dac_info + 0x4) & 0xf;
831 dac = RBIOS8(dac_info + 0x5) & 0xf;
832 tv_dac->ps2_tvdac_adj =
833 (bg << 16) | (dac << 20);
834 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
835 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 836 found = 1;
771fe6b9 837 }
6fe7ac3f
AD		 838 } else {
839 DRM_INFO("No TV DAC info found in BIOS\n");
771fe6b9
JG		 840 }
841 }
842
6a719e05
DA		 843out:
844 if (!found) /* fallback to defaults */
845 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
846
771fe6b9
JG		 847 return tv_dac;
848}
849
850static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
851 radeon_device
852 *rdev)
853{
854 struct radeon_encoder_lvds *lvds = NULL;
855 uint32_t fp_vert_stretch, fp_horz_stretch;
856 uint32_t ppll_div_sel, ppll_val;
8b5c7444 857 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
771fe6b9
JG		 858
859 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
860
861 if (!lvds)
862 return NULL;
863
864 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
865 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
866
8b5c7444
MD		 867 /* These should be fail-safe defaults, fingers crossed */
868 lvds->panel_pwr_delay = 200;
869 lvds->panel_vcc_delay = 2000;
870
871 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
872 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
873 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
874
771fe6b9 875 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
de2103e4 876 lvds->native_mode.vdisplay =
771fe6b9
JG		 877 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
878 RADEON_VERT_PANEL_SHIFT) + 1;
879 else
de2103e4 880 lvds->native_mode.vdisplay =
771fe6b9
JG		 881 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
882
883 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
de2103e4 884 lvds->native_mode.hdisplay =
771fe6b9
JG		 885 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
886 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
887 else
de2103e4 888 lvds->native_mode.hdisplay =
771fe6b9
JG		 889 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
890
de2103e4
AD		 891 if ((lvds->native_mode.hdisplay < 640) ||
892 (lvds->native_mode.vdisplay < 480)) {
893 lvds->native_mode.hdisplay = 640;
894 lvds->native_mode.vdisplay = 480;
771fe6b9
JG		 895 }
896
897 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
898 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
899 if ((ppll_val & 0x000707ff) == 0x1bb)
900 lvds->use_bios_dividers = false;
901 else {
902 lvds->panel_ref_divider =
903 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
904 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
905 lvds->panel_fb_divider = ppll_val & 0x7ff;
906
907 if ((lvds->panel_ref_divider != 0) &&
908 (lvds->panel_fb_divider > 3))
909 lvds->use_bios_dividers = true;
910 }
911 lvds->panel_vcc_delay = 200;
912
913 DRM_INFO("Panel info derived from registers\n");
de2103e4
AD		 914 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
915 lvds->native_mode.vdisplay);
771fe6b9
JG		 916
917 return lvds;
918}
919
920struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
921 *encoder)
922{
923 struct drm_device *dev = encoder->base.dev;
924 struct radeon_device *rdev = dev->dev_private;
925 uint16_t lcd_info;
926 uint32_t panel_setup;
927 char stmp[30];
928 int tmp, i;
929 struct radeon_encoder_lvds *lvds = NULL;
930
8dfaa8a7
MD		 931 if (rdev->bios == NULL) {
932 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
933 goto out;
934 }
771fe6b9
JG		 935
936 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
937
938 if (lcd_info) {
939 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
940
941 if (!lvds)
942 return NULL;
943
944 for (i = 0; i < 24; i++)
945 stmp[i] = RBIOS8(lcd_info + i + 1);
946 stmp[24] = 0;
947
948 DRM_INFO("Panel ID String: %s\n", stmp);
949
de2103e4
AD		 950 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
951 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
771fe6b9 952
de2103e4
AD		 953 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
954 lvds->native_mode.vdisplay);
771fe6b9
JG		 955
956 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
957 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0)
958 lvds->panel_vcc_delay = 2000;
959
960 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
961 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
962 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
963
964 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
965 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
966 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
967 if ((lvds->panel_ref_divider != 0) &&
968 (lvds->panel_fb_divider > 3))
969 lvds->use_bios_dividers = true;
970
971 panel_setup = RBIOS32(lcd_info + 0x39);
972 lvds->lvds_gen_cntl = 0xff00;
973 if (panel_setup & 0x1)
974 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
975
976 if ((panel_setup >> 4) & 0x1)
977 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
978
979 switch ((panel_setup >> 8) & 0x7) {
980 case 0:
981 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
982 break;
983 case 1:
984 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
985 break;
986 case 2:
987 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
988 break;
989 default:
990 break;
991 }
992
993 if ((panel_setup >> 16) & 0x1)
994 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
995
996 if ((panel_setup >> 17) & 0x1)
997 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
998
999 if ((panel_setup >> 18) & 0x1)
1000 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1001
1002 if ((panel_setup >> 23) & 0x1)
1003 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1004
1005 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1006
1007 for (i = 0; i < 32; i++) {
1008 tmp = RBIOS16(lcd_info + 64 + i * 2);
1009 if (tmp == 0)
1010 break;
1011
de2103e4 1012 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
771fe6b9 1013 (RBIOS16(tmp + 2) ==
de2103e4
AD		 1014 lvds->native_mode.vdisplay)) {
1015 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
1016 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
1017 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
1018 RBIOS16(tmp + 21)) * 8;
1019
1020 lvds->native_mode.vtotal = RBIOS16(tmp + 24);
1021 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
1022 lvds->native_mode.vsync_end =
1023 ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
1024 (RBIOS16(tmp + 28) & 0x7ff);
1025
1026 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
771fe6b9 1027 lvds->native_mode.flags = 0;
de2103e4
AD		 1028 /* set crtc values */
1029 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1030
771fe6b9
JG		 1031 }
1032 }
6fe7ac3f 1033 } else {
771fe6b9 1034 DRM_INFO("No panel info found in BIOS\n");
8dfaa8a7 1035 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
6fe7ac3f 1036 }
8dfaa8a7
MD		 1037out:
1038 if (lvds)
1039 encoder->native_mode = lvds->native_mode;
771fe6b9
JG		 1040 return lvds;
1041}
1042
1043static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1044 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1045 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1046 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1047 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1048 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1049 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1050 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1051 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1052 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1053 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1054 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1055 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1056 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1057 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1058 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1059 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
fcec570b
AD		 1060 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1061 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
771fe6b9
JG		 1062};
1063
445282db
DA		 1064bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1065 struct radeon_encoder_int_tmds *tmds)
771fe6b9 1066{
445282db
DA		 1067 struct drm_device *dev = encoder->base.dev;
1068 struct radeon_device *rdev = dev->dev_private;
771fe6b9 1069 int i;
771fe6b9
JG		 1070
1071 for (i = 0; i < 4; i++) {
1072 tmds->tmds_pll[i].value =
445282db 1073 default_tmds_pll[rdev->family][i].value;
771fe6b9
JG		 1074 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1075 }
1076
445282db 1077 return true;
771fe6b9
JG		 1078}
1079
445282db
DA		 1080bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1081 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1082{
1083 struct drm_device *dev = encoder->base.dev;
1084 struct radeon_device *rdev = dev->dev_private;
1085 uint16_t tmds_info;
1086 int i, n;
1087 uint8_t ver;
771fe6b9
JG		 1088
1089 if (rdev->bios == NULL)
445282db 1090 return false;
771fe6b9
JG		 1091
1092 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1093
1094 if (tmds_info) {
771fe6b9
JG		 1095 ver = RBIOS8(tmds_info);
1096 DRM_INFO("DFP table revision: %d\n", ver);
1097 if (ver == 3) {
1098 n = RBIOS8(tmds_info + 5) + 1;
1099 if (n > 4)
1100 n = 4;
1101 for (i = 0; i < n; i++) {
1102 tmds->tmds_pll[i].value =
1103 RBIOS32(tmds_info + i * 10 + 0x08);
1104 tmds->tmds_pll[i].freq =
1105 RBIOS16(tmds_info + i * 10 + 0x10);
1106 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1107 tmds->tmds_pll[i].freq,
1108 tmds->tmds_pll[i].value);
1109 }
1110 } else if (ver == 4) {
1111 int stride = 0;
1112 n = RBIOS8(tmds_info + 5) + 1;
1113 if (n > 4)
1114 n = 4;
1115 for (i = 0; i < n; i++) {
1116 tmds->tmds_pll[i].value =
1117 RBIOS32(tmds_info + stride + 0x08);
1118 tmds->tmds_pll[i].freq =
1119 RBIOS16(tmds_info + stride + 0x10);
1120 if (i == 0)
1121 stride += 10;
1122 else
1123 stride += 6;
1124 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1125 tmds->tmds_pll[i].freq,
1126 tmds->tmds_pll[i].value);
1127 }
1128 }
fcec570b 1129 } else {
771fe6b9 1130 DRM_INFO("No TMDS info found in BIOS\n");
fcec570b
AD		 1131 return false;
1132 }
445282db
DA		 1133 return true;
1134}
1135
fcec570b
AD		 1136bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1137 struct radeon_encoder_ext_tmds *tmds)
445282db 1138{
fcec570b
AD		 1139 struct drm_device *dev = encoder->base.dev;
1140 struct radeon_device *rdev = dev->dev_private;
1141 struct radeon_i2c_bus_rec i2c_bus;
445282db 1142
fcec570b 1143 /* default for macs */
6a93cb25 1144 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b 1145 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
445282db 1146
fcec570b
AD		 1147 /* XXX some macs have duallink chips */
1148 switch (rdev->mode_info.connector_table) {
1149 case CT_POWERBOOK_EXTERNAL:
1150 case CT_MINI_EXTERNAL:
1151 default:
1152 tmds->dvo_chip = DVO_SIL164;
1153 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1154 break;
1155 }
445282db 1156
fcec570b 1157 return true;
771fe6b9
JG		 1158}
1159
fcec570b
AD		 1160bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1161 struct radeon_encoder_ext_tmds *tmds)
771fe6b9
JG		 1162{
1163 struct drm_device *dev = encoder->base.dev;
1164 struct radeon_device *rdev = dev->dev_private;
fcec570b
AD		 1165 uint16_t offset;
1166 uint8_t ver, id, blocks, clk, data;
1167 int i;
1168 enum radeon_combios_ddc gpio;
1169 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9
JG		 1170
1171 if (rdev->bios == NULL)
fcec570b 1172 return false;
771fe6b9 1173
fcec570b
AD		 1174 tmds->i2c_bus = NULL;
1175 if (rdev->flags & RADEON_IS_IGP) {
1176 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1177 if (offset) {
1178 ver = RBIOS8(offset);
1179 DRM_INFO("GPIO Table revision: %d\n", ver);
1180 blocks = RBIOS8(offset + 2);
1181 for (i = 0; i < blocks; i++) {
1182 id = RBIOS8(offset + 3 + (i * 5) + 0);
1183 if (id == 136) {
1184 clk = RBIOS8(offset + 3 + (i * 5) + 3);
1185 data = RBIOS8(offset + 3 + (i * 5) + 4);
1186 i2c_bus.valid = true;
1187 i2c_bus.mask_clk_mask = (1 << clk);
1188 i2c_bus.mask_data_mask = (1 << data);
1189 i2c_bus.a_clk_mask = (1 << clk);
1190 i2c_bus.a_data_mask = (1 << data);
1191 i2c_bus.en_clk_mask = (1 << clk);
1192 i2c_bus.en_data_mask = (1 << data);
1193 i2c_bus.y_clk_mask = (1 << clk);
1194 i2c_bus.y_data_mask = (1 << data);
1195 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1196 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1197 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1198 i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1199 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1200 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1201 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1202 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1203 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1204 tmds->dvo_chip = DVO_SIL164;
1205 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1206 break;
1207 }
1208 }
1209 }
1210 } else {
1211 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1212 if (offset) {
1213 ver = RBIOS8(offset);
1214 DRM_INFO("External TMDS Table revision: %d\n", ver);
1215 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1216 tmds->slave_addr >>= 1; /* 7 bit addressing */
1217 gpio = RBIOS8(offset + 4 + 3);
1218 switch (gpio) {
1219 case DDC_MONID:
6a93cb25 1220 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b
AD		 1221 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1222 break;
1223 case DDC_DVI:
6a93cb25 1224 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
fcec570b
AD		 1225 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1226 break;
1227 case DDC_VGA:
6a93cb25 1228 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
fcec570b
AD		 1229 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1230 break;
1231 case DDC_CRT2:
1232 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1233 if (rdev->family >= CHIP_R300)
6a93cb25 1234 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b 1235 else
6a93cb25 1236 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
fcec570b
AD		 1237 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1238 break;
1239 case DDC_LCD: /* MM i2c */
1240 DRM_ERROR("MM i2c requires hw i2c engine\n");
1241 break;
1242 default:
1243 DRM_ERROR("Unsupported gpio %d\n", gpio);
1244 break;
1245 }
1246 }
771fe6b9 1247 }
fcec570b
AD		 1248
1249 if (!tmds->i2c_bus) {
1250 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1251 return false;
1252 }
1253
1254 return true;
771fe6b9
JG		 1255}
1256
1257bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1258{
1259 struct radeon_device *rdev = dev->dev_private;
1260 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 1261 struct radeon_hpd hpd;
771fe6b9
JG		 1262
1263 rdev->mode_info.connector_table = radeon_connector_table;
1264 if (rdev->mode_info.connector_table == CT_NONE) {
1265#ifdef CONFIG_PPC_PMAC
1266 if (machine_is_compatible("PowerBook3,3")) {
1267 /* powerbook with VGA */
1268 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1269 } else if (machine_is_compatible("PowerBook3,4") ||
1270 machine_is_compatible("PowerBook3,5")) {
1271 /* powerbook with internal tmds */
1272 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1273 } else if (machine_is_compatible("PowerBook5,1") ||
1274 machine_is_compatible("PowerBook5,2") ||
1275 machine_is_compatible("PowerBook5,3") ||
1276 machine_is_compatible("PowerBook5,4") ||
1277 machine_is_compatible("PowerBook5,5")) {
1278 /* powerbook with external single link tmds (sil164) */
1279 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1280 } else if (machine_is_compatible("PowerBook5,6")) {
1281 /* powerbook with external dual or single link tmds */
1282 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1283 } else if (machine_is_compatible("PowerBook5,7") ||
1284 machine_is_compatible("PowerBook5,8") ||
1285 machine_is_compatible("PowerBook5,9")) {
1286 /* PowerBook6,2 ? */
1287 /* powerbook with external dual link tmds (sil1178?) */
1288 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1289 } else if (machine_is_compatible("PowerBook4,1") ||
1290 machine_is_compatible("PowerBook4,2") ||
1291 machine_is_compatible("PowerBook4,3") ||
1292 machine_is_compatible("PowerBook6,3") ||
1293 machine_is_compatible("PowerBook6,5") ||
1294 machine_is_compatible("PowerBook6,7")) {
1295 /* ibook */
1296 rdev->mode_info.connector_table = CT_IBOOK;
1297 } else if (machine_is_compatible("PowerMac4,4")) {
1298 /* emac */
1299 rdev->mode_info.connector_table = CT_EMAC;
1300 } else if (machine_is_compatible("PowerMac10,1")) {
1301 /* mini with internal tmds */
1302 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1303 } else if (machine_is_compatible("PowerMac10,2")) {
1304 /* mini with external tmds */
1305 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1306 } else if (machine_is_compatible("PowerMac12,1")) {
1307 /* PowerMac8,1 ? */
1308 /* imac g5 isight */
1309 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1310 } else
1311#endif /* CONFIG_PPC_PMAC */
1312 rdev->mode_info.connector_table = CT_GENERIC;
1313 }
1314
1315 switch (rdev->mode_info.connector_table) {
1316 case CT_GENERIC:
1317 DRM_INFO("Connector Table: %d (generic)\n",
1318 rdev->mode_info.connector_table);
1319 /* these are the most common settings */
1320 if (rdev->flags & RADEON_SINGLE_CRTC) {
1321 /* VGA - primary dac */
6a93cb25 1322 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1323 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1324 radeon_add_legacy_encoder(dev,
1325 radeon_get_encoder_id(dev,
1326 ATOM_DEVICE_CRT1_SUPPORT,
1327 1),
1328 ATOM_DEVICE_CRT1_SUPPORT);
1329 radeon_add_legacy_connector(dev, 0,
1330 ATOM_DEVICE_CRT1_SUPPORT,
1331 DRM_MODE_CONNECTOR_VGA,
b75fad06 1332 &ddc_i2c,
eed45b30
AD		 1333 CONNECTOR_OBJECT_ID_VGA,
1334 &hpd);
771fe6b9
JG		 1335 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1336 /* LVDS */
6a93cb25 1337 ddc_i2c = combios_setup_i2c_bus(rdev, 0);
eed45b30 1338 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1339 radeon_add_legacy_encoder(dev,
1340 radeon_get_encoder_id(dev,
1341 ATOM_DEVICE_LCD1_SUPPORT,
1342 0),
1343 ATOM_DEVICE_LCD1_SUPPORT);
1344 radeon_add_legacy_connector(dev, 0,
1345 ATOM_DEVICE_LCD1_SUPPORT,
1346 DRM_MODE_CONNECTOR_LVDS,
b75fad06 1347 &ddc_i2c,
eed45b30
AD		 1348 CONNECTOR_OBJECT_ID_LVDS,
1349 &hpd);
771fe6b9
JG		 1350
1351 /* VGA - primary dac */
6a93cb25 1352 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1353 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1354 radeon_add_legacy_encoder(dev,
1355 radeon_get_encoder_id(dev,
1356 ATOM_DEVICE_CRT1_SUPPORT,
1357 1),
1358 ATOM_DEVICE_CRT1_SUPPORT);
1359 radeon_add_legacy_connector(dev, 1,
1360 ATOM_DEVICE_CRT1_SUPPORT,
1361 DRM_MODE_CONNECTOR_VGA,
b75fad06 1362 &ddc_i2c,
eed45b30
AD		 1363 CONNECTOR_OBJECT_ID_VGA,
1364 &hpd);
771fe6b9
JG		 1365 } else {
1366 /* DVI-I - tv dac, int tmds */
6a93cb25 1367 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1368 hpd.hpd = RADEON_HPD_1;
771fe6b9
JG		 1369 radeon_add_legacy_encoder(dev,
1370 radeon_get_encoder_id(dev,
1371 ATOM_DEVICE_DFP1_SUPPORT,
1372 0),
1373 ATOM_DEVICE_DFP1_SUPPORT);
1374 radeon_add_legacy_encoder(dev,
1375 radeon_get_encoder_id(dev,
1376 ATOM_DEVICE_CRT2_SUPPORT,
1377 2),
1378 ATOM_DEVICE_CRT2_SUPPORT);
1379 radeon_add_legacy_connector(dev, 0,
1380 ATOM_DEVICE_DFP1_SUPPORT |
1381 ATOM_DEVICE_CRT2_SUPPORT,
1382 DRM_MODE_CONNECTOR_DVII,
b75fad06 1383 &ddc_i2c,
eed45b30
AD		 1384 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1385 &hpd);
771fe6b9
JG		 1386
1387 /* VGA - primary dac */
6a93cb25 1388 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1389 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1390 radeon_add_legacy_encoder(dev,
1391 radeon_get_encoder_id(dev,
1392 ATOM_DEVICE_CRT1_SUPPORT,
1393 1),
1394 ATOM_DEVICE_CRT1_SUPPORT);
1395 radeon_add_legacy_connector(dev, 1,
1396 ATOM_DEVICE_CRT1_SUPPORT,
1397 DRM_MODE_CONNECTOR_VGA,
b75fad06 1398 &ddc_i2c,
eed45b30
AD		 1399 CONNECTOR_OBJECT_ID_VGA,
1400 &hpd);
771fe6b9
JG		 1401 }
1402
1403 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1404 /* TV - tv dac */
eed45b30
AD		 1405 ddc_i2c.valid = false;
1406 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1407 radeon_add_legacy_encoder(dev,
1408 radeon_get_encoder_id(dev,
1409 ATOM_DEVICE_TV1_SUPPORT,
1410 2),
1411 ATOM_DEVICE_TV1_SUPPORT);
1412 radeon_add_legacy_connector(dev, 2,
1413 ATOM_DEVICE_TV1_SUPPORT,
1414 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1415 &ddc_i2c,
eed45b30
AD		 1416 CONNECTOR_OBJECT_ID_SVIDEO,
1417 &hpd);
771fe6b9
JG		 1418 }
1419 break;
1420 case CT_IBOOK:
1421 DRM_INFO("Connector Table: %d (ibook)\n",
1422 rdev->mode_info.connector_table);
1423 /* LVDS */
6a93cb25 1424 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1425 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1426 radeon_add_legacy_encoder(dev,
1427 radeon_get_encoder_id(dev,
1428 ATOM_DEVICE_LCD1_SUPPORT,
1429 0),
1430 ATOM_DEVICE_LCD1_SUPPORT);
1431 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1432 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1433 CONNECTOR_OBJECT_ID_LVDS,
1434 &hpd);
771fe6b9 1435 /* VGA - TV DAC */
6a93cb25 1436 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1437 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1438 radeon_add_legacy_encoder(dev,
1439 radeon_get_encoder_id(dev,
1440 ATOM_DEVICE_CRT2_SUPPORT,
1441 2),
1442 ATOM_DEVICE_CRT2_SUPPORT);
1443 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1444 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1445 CONNECTOR_OBJECT_ID_VGA,
1446 &hpd);
771fe6b9 1447 /* TV - TV DAC */
eed45b30
AD		 1448 ddc_i2c.valid = false;
1449 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1450 radeon_add_legacy_encoder(dev,
1451 radeon_get_encoder_id(dev,
1452 ATOM_DEVICE_TV1_SUPPORT,
1453 2),
1454 ATOM_DEVICE_TV1_SUPPORT);
1455 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1456 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1457 &ddc_i2c,
eed45b30
AD		 1458 CONNECTOR_OBJECT_ID_SVIDEO,
1459 &hpd);
771fe6b9
JG		 1460 break;
1461 case CT_POWERBOOK_EXTERNAL:
1462 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1463 rdev->mode_info.connector_table);
1464 /* LVDS */
6a93cb25 1465 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1466 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1467 radeon_add_legacy_encoder(dev,
1468 radeon_get_encoder_id(dev,
1469 ATOM_DEVICE_LCD1_SUPPORT,
1470 0),
1471 ATOM_DEVICE_LCD1_SUPPORT);
1472 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1473 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1474 CONNECTOR_OBJECT_ID_LVDS,
1475 &hpd);
771fe6b9 1476 /* DVI-I - primary dac, ext tmds */
6a93cb25 1477 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1478 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9
JG		 1479 radeon_add_legacy_encoder(dev,
1480 radeon_get_encoder_id(dev,
1481 ATOM_DEVICE_DFP2_SUPPORT,
1482 0),
1483 ATOM_DEVICE_DFP2_SUPPORT);
1484 radeon_add_legacy_encoder(dev,
1485 radeon_get_encoder_id(dev,
1486 ATOM_DEVICE_CRT1_SUPPORT,
1487 1),
1488 ATOM_DEVICE_CRT1_SUPPORT);
b75fad06 1489 /* XXX some are SL */
771fe6b9
JG		 1490 radeon_add_legacy_connector(dev, 1,
1491 ATOM_DEVICE_DFP2_SUPPORT |
1492 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1493 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1494 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1495 &hpd);
771fe6b9 1496 /* TV - TV DAC */
eed45b30
AD		 1497 ddc_i2c.valid = false;
1498 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1499 radeon_add_legacy_encoder(dev,
1500 radeon_get_encoder_id(dev,
1501 ATOM_DEVICE_TV1_SUPPORT,
1502 2),
1503 ATOM_DEVICE_TV1_SUPPORT);
1504 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1505 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1506 &ddc_i2c,
eed45b30
AD		 1507 CONNECTOR_OBJECT_ID_SVIDEO,
1508 &hpd);
771fe6b9
JG		 1509 break;
1510 case CT_POWERBOOK_INTERNAL:
1511 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1512 rdev->mode_info.connector_table);
1513 /* LVDS */
6a93cb25 1514 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1515 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1516 radeon_add_legacy_encoder(dev,
1517 radeon_get_encoder_id(dev,
1518 ATOM_DEVICE_LCD1_SUPPORT,
1519 0),
1520 ATOM_DEVICE_LCD1_SUPPORT);
1521 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1522 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1523 CONNECTOR_OBJECT_ID_LVDS,
1524 &hpd);
771fe6b9 1525 /* DVI-I - primary dac, int tmds */
6a93cb25 1526 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1527 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1528 radeon_add_legacy_encoder(dev,
1529 radeon_get_encoder_id(dev,
1530 ATOM_DEVICE_DFP1_SUPPORT,
1531 0),
1532 ATOM_DEVICE_DFP1_SUPPORT);
1533 radeon_add_legacy_encoder(dev,
1534 radeon_get_encoder_id(dev,
1535 ATOM_DEVICE_CRT1_SUPPORT,
1536 1),
1537 ATOM_DEVICE_CRT1_SUPPORT);
1538 radeon_add_legacy_connector(dev, 1,
1539 ATOM_DEVICE_DFP1_SUPPORT |
1540 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1541 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1542 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1543 &hpd);
771fe6b9 1544 /* TV - TV DAC */
eed45b30
AD		 1545 ddc_i2c.valid = false;
1546 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1547 radeon_add_legacy_encoder(dev,
1548 radeon_get_encoder_id(dev,
1549 ATOM_DEVICE_TV1_SUPPORT,
1550 2),
1551 ATOM_DEVICE_TV1_SUPPORT);
1552 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1553 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1554 &ddc_i2c,
eed45b30
AD		 1555 CONNECTOR_OBJECT_ID_SVIDEO,
1556 &hpd);
771fe6b9
JG		 1557 break;
1558 case CT_POWERBOOK_VGA:
1559 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1560 rdev->mode_info.connector_table);
1561 /* LVDS */
6a93cb25 1562 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1563 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1564 radeon_add_legacy_encoder(dev,
1565 radeon_get_encoder_id(dev,
1566 ATOM_DEVICE_LCD1_SUPPORT,
1567 0),
1568 ATOM_DEVICE_LCD1_SUPPORT);
1569 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1570 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1571 CONNECTOR_OBJECT_ID_LVDS,
1572 &hpd);
771fe6b9 1573 /* VGA - primary dac */
6a93cb25 1574 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1575 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1576 radeon_add_legacy_encoder(dev,
1577 radeon_get_encoder_id(dev,
1578 ATOM_DEVICE_CRT1_SUPPORT,
1579 1),
1580 ATOM_DEVICE_CRT1_SUPPORT);
1581 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1582 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1583 CONNECTOR_OBJECT_ID_VGA,
1584 &hpd);
771fe6b9 1585 /* TV - TV DAC */
eed45b30
AD		 1586 ddc_i2c.valid = false;
1587 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1588 radeon_add_legacy_encoder(dev,
1589 radeon_get_encoder_id(dev,
1590 ATOM_DEVICE_TV1_SUPPORT,
1591 2),
1592 ATOM_DEVICE_TV1_SUPPORT);
1593 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1594 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1595 &ddc_i2c,
eed45b30
AD		 1596 CONNECTOR_OBJECT_ID_SVIDEO,
1597 &hpd);
771fe6b9
JG		 1598 break;
1599 case CT_MINI_EXTERNAL:
1600 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1601 rdev->mode_info.connector_table);
1602 /* DVI-I - tv dac, ext tmds */
6a93cb25 1603 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1604 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9
JG		 1605 radeon_add_legacy_encoder(dev,
1606 radeon_get_encoder_id(dev,
1607 ATOM_DEVICE_DFP2_SUPPORT,
1608 0),
1609 ATOM_DEVICE_DFP2_SUPPORT);
1610 radeon_add_legacy_encoder(dev,
1611 radeon_get_encoder_id(dev,
1612 ATOM_DEVICE_CRT2_SUPPORT,
1613 2),
1614 ATOM_DEVICE_CRT2_SUPPORT);
b75fad06 1615 /* XXX are any DL? */
771fe6b9
JG		 1616 radeon_add_legacy_connector(dev, 0,
1617 ATOM_DEVICE_DFP2_SUPPORT |
1618 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1619 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1620 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1621 &hpd);
771fe6b9 1622 /* TV - TV DAC */
eed45b30
AD		 1623 ddc_i2c.valid = false;
1624 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1625 radeon_add_legacy_encoder(dev,
1626 radeon_get_encoder_id(dev,
1627 ATOM_DEVICE_TV1_SUPPORT,
1628 2),
1629 ATOM_DEVICE_TV1_SUPPORT);
1630 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1631 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1632 &ddc_i2c,
eed45b30
AD		 1633 CONNECTOR_OBJECT_ID_SVIDEO,
1634 &hpd);
771fe6b9
JG		 1635 break;
1636 case CT_MINI_INTERNAL:
1637 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1638 rdev->mode_info.connector_table);
1639 /* DVI-I - tv dac, int tmds */
6a93cb25 1640 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1641 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1642 radeon_add_legacy_encoder(dev,
1643 radeon_get_encoder_id(dev,
1644 ATOM_DEVICE_DFP1_SUPPORT,
1645 0),
1646 ATOM_DEVICE_DFP1_SUPPORT);
1647 radeon_add_legacy_encoder(dev,
1648 radeon_get_encoder_id(dev,
1649 ATOM_DEVICE_CRT2_SUPPORT,
1650 2),
1651 ATOM_DEVICE_CRT2_SUPPORT);
1652 radeon_add_legacy_connector(dev, 0,
1653 ATOM_DEVICE_DFP1_SUPPORT |
1654 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1655 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1656 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1657 &hpd);
771fe6b9 1658 /* TV - TV DAC */
eed45b30
AD		 1659 ddc_i2c.valid = false;
1660 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1661 radeon_add_legacy_encoder(dev,
1662 radeon_get_encoder_id(dev,
1663 ATOM_DEVICE_TV1_SUPPORT,
1664 2),
1665 ATOM_DEVICE_TV1_SUPPORT);
1666 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1667 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1668 &ddc_i2c,
eed45b30
AD		 1669 CONNECTOR_OBJECT_ID_SVIDEO,
1670 &hpd);
771fe6b9
JG		 1671 break;
1672 case CT_IMAC_G5_ISIGHT:
1673 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1674 rdev->mode_info.connector_table);
1675 /* DVI-D - int tmds */
6a93cb25 1676 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
eed45b30 1677 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1678 radeon_add_legacy_encoder(dev,
1679 radeon_get_encoder_id(dev,
1680 ATOM_DEVICE_DFP1_SUPPORT,
1681 0),
1682 ATOM_DEVICE_DFP1_SUPPORT);
1683 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
b75fad06 1684 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
eed45b30
AD		 1685 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1686 &hpd);
771fe6b9 1687 /* VGA - tv dac */
6a93cb25 1688 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1689 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1690 radeon_add_legacy_encoder(dev,
1691 radeon_get_encoder_id(dev,
1692 ATOM_DEVICE_CRT2_SUPPORT,
1693 2),
1694 ATOM_DEVICE_CRT2_SUPPORT);
1695 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1696 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1697 CONNECTOR_OBJECT_ID_VGA,
1698 &hpd);
771fe6b9 1699 /* TV - TV DAC */
eed45b30
AD		 1700 ddc_i2c.valid = false;
1701 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1702 radeon_add_legacy_encoder(dev,
1703 radeon_get_encoder_id(dev,
1704 ATOM_DEVICE_TV1_SUPPORT,
1705 2),
1706 ATOM_DEVICE_TV1_SUPPORT);
1707 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1708 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1709 &ddc_i2c,
eed45b30
AD		 1710 CONNECTOR_OBJECT_ID_SVIDEO,
1711 &hpd);
771fe6b9
JG		 1712 break;
1713 case CT_EMAC:
1714 DRM_INFO("Connector Table: %d (emac)\n",
1715 rdev->mode_info.connector_table);
1716 /* VGA - primary dac */
6a93cb25 1717 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1718 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1719 radeon_add_legacy_encoder(dev,
1720 radeon_get_encoder_id(dev,
1721 ATOM_DEVICE_CRT1_SUPPORT,
1722 1),
1723 ATOM_DEVICE_CRT1_SUPPORT);
1724 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1725 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1726 CONNECTOR_OBJECT_ID_VGA,
1727 &hpd);
771fe6b9 1728 /* VGA - tv dac */
6a93cb25 1729 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1730 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1731 radeon_add_legacy_encoder(dev,
1732 radeon_get_encoder_id(dev,
1733 ATOM_DEVICE_CRT2_SUPPORT,
1734 2),
1735 ATOM_DEVICE_CRT2_SUPPORT);
1736 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1737 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1738 CONNECTOR_OBJECT_ID_VGA,
1739 &hpd);
771fe6b9 1740 /* TV - TV DAC */
eed45b30
AD		 1741 ddc_i2c.valid = false;
1742 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1743 radeon_add_legacy_encoder(dev,
1744 radeon_get_encoder_id(dev,
1745 ATOM_DEVICE_TV1_SUPPORT,
1746 2),
1747 ATOM_DEVICE_TV1_SUPPORT);
1748 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1749 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1750 &ddc_i2c,
eed45b30
AD		 1751 CONNECTOR_OBJECT_ID_SVIDEO,
1752 &hpd);
771fe6b9
JG		 1753 break;
1754 default:
1755 DRM_INFO("Connector table: %d (invalid)\n",
1756 rdev->mode_info.connector_table);
1757 return false;
1758 }
1759
1760 radeon_link_encoder_connector(dev);
1761
1762 return true;
1763}
1764
1765static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1766 int bios_index,
1767 enum radeon_combios_connector
1768 *legacy_connector,
eed45b30
AD		 1769 struct radeon_i2c_bus_rec *ddc_i2c,
1770 struct radeon_hpd *hpd)
771fe6b9
JG		 1771{
1772 struct radeon_device *rdev = dev->dev_private;
1773
1774 /* XPRESS DDC quirks */
1775 if ((rdev->family == CHIP_RS400 ||
1776 rdev->family == CHIP_RS480) &&
1777 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
6a93cb25 1778 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 1779 else if ((rdev->family == CHIP_RS400 ||
1780 rdev->family == CHIP_RS480) &&
1781 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
6a93cb25 1782 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
771fe6b9
JG		 1783 ddc_i2c->mask_clk_mask = (0x20 << 8);
1784 ddc_i2c->mask_data_mask = 0x80;
1785 ddc_i2c->a_clk_mask = (0x20 << 8);
1786 ddc_i2c->a_data_mask = 0x80;
9b9fe724
AD		 1787 ddc_i2c->en_clk_mask = (0x20 << 8);
1788 ddc_i2c->en_data_mask = 0x80;
1789 ddc_i2c->y_clk_mask = (0x20 << 8);
1790 ddc_i2c->y_data_mask = 0x80;
771fe6b9
JG		 1791 }
1792
fcec570b
AD		 1793 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1794 if ((rdev->family >= CHIP_R300) &&
1795 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
6a93cb25 1796 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
fcec570b 1797
771fe6b9
JG		 1798 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1799 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1800 if (dev->pdev->device == 0x515e &&
1801 dev->pdev->subsystem_vendor == 0x1014) {
1802 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1803 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1804 return false;
1805 }
1806
1807 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1808 if (dev->pdev->device == 0x5159 &&
1809 dev->pdev->subsystem_vendor == 0x1002 &&
1810 dev->pdev->subsystem_device == 0x013a) {
1811 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1812 *legacy_connector = CONNECTOR_CRT_LEGACY;
1813
1814 }
1815
1816 /* X300 card with extra non-existent DVI port */
1817 if (dev->pdev->device == 0x5B60 &&
1818 dev->pdev->subsystem_vendor == 0x17af &&
1819 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1820 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1821 return false;
1822 }
1823
1824 return true;
1825}
1826
790cfb34
AD		 1827static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1828{
1829 /* Acer 5102 has non-existent TV port */
1830 if (dev->pdev->device == 0x5975 &&
1831 dev->pdev->subsystem_vendor == 0x1025 &&
1832 dev->pdev->subsystem_device == 0x009f)
1833 return false;
1834
fc7f7119
AD		 1835 /* HP dc5750 has non-existent TV port */
1836 if (dev->pdev->device == 0x5974 &&
1837 dev->pdev->subsystem_vendor == 0x103c &&
1838 dev->pdev->subsystem_device == 0x280a)
1839 return false;
1840
fd874ad0
AD		 1841 /* MSI S270 has non-existent TV port */
1842 if (dev->pdev->device == 0x5955 &&
1843 dev->pdev->subsystem_vendor == 0x1462 &&
1844 dev->pdev->subsystem_device == 0x0131)
1845 return false;
1846
790cfb34
AD		 1847 return true;
1848}
1849
b75fad06
AD		 1850static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1851{
1852 struct radeon_device *rdev = dev->dev_private;
1853 uint32_t ext_tmds_info;
1854
1855 if (rdev->flags & RADEON_IS_IGP) {
1856 if (is_dvi_d)
1857 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1858 else
1859 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1860 }
1861 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1862 if (ext_tmds_info) {
1863 uint8_t rev = RBIOS8(ext_tmds_info);
1864 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1865 if (rev >= 3) {
1866 if (is_dvi_d)
1867 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1868 else
1869 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1870 } else {
1871 if (flags & 1) {
1872 if (is_dvi_d)
1873 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1874 else
1875 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1876 }
1877 }
1878 }
1879 if (is_dvi_d)
1880 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1881 else
1882 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1883}
1884
771fe6b9
JG		 1885bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1886{
1887 struct radeon_device *rdev = dev->dev_private;
1888 uint32_t conn_info, entry, devices;
b75fad06 1889 uint16_t tmp, connector_object_id;
771fe6b9
JG		 1890 enum radeon_combios_ddc ddc_type;
1891 enum radeon_combios_connector connector;
1892 int i = 0;
1893 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 1894 struct radeon_hpd hpd;
771fe6b9
JG		 1895
1896 if (rdev->bios == NULL)
1897 return false;
1898
1899 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1900 if (conn_info) {
1901 for (i = 0; i < 4; i++) {
1902 entry = conn_info + 2 + i * 2;
1903
1904 if (!RBIOS16(entry))
1905 break;
1906
1907 tmp = RBIOS16(entry);
1908
1909 connector = (tmp >> 12) & 0xf;
1910
1911 ddc_type = (tmp >> 8) & 0xf;
1912 switch (ddc_type) {
1913 case DDC_MONID:
1914 ddc_i2c =
6a93cb25 1915 combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 1916 break;
1917 case DDC_DVI:
1918 ddc_i2c =
6a93cb25 1919 combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
771fe6b9
JG		 1920 break;
1921 case DDC_VGA:
1922 ddc_i2c =
6a93cb25 1923 combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
771fe6b9
JG		 1924 break;
1925 case DDC_CRT2:
1926 ddc_i2c =
6a93cb25 1927 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
771fe6b9
JG		 1928 break;
1929 default:
1930 break;
1931 }
1932
eed45b30
AD		 1933 switch (connector) {
1934 case CONNECTOR_PROPRIETARY_LEGACY:
1935 case CONNECTOR_DVI_I_LEGACY:
1936 case CONNECTOR_DVI_D_LEGACY:
1937 if ((tmp >> 4) & 0x1)
1938 hpd.hpd = RADEON_HPD_2;
1939 else
1940 hpd.hpd = RADEON_HPD_1;
1941 break;
1942 default:
1943 hpd.hpd = RADEON_HPD_NONE;
1944 break;
1945 }
1946
2d152c6b 1947 if (!radeon_apply_legacy_quirks(dev, i, &connector,
eed45b30 1948 &ddc_i2c, &hpd))
2d152c6b 1949 continue;
771fe6b9
JG		 1950
1951 switch (connector) {
1952 case CONNECTOR_PROPRIETARY_LEGACY:
1953 if ((tmp >> 4) & 0x1)
1954 devices = ATOM_DEVICE_DFP2_SUPPORT;
1955 else
1956 devices = ATOM_DEVICE_DFP1_SUPPORT;
1957 radeon_add_legacy_encoder(dev,
1958 radeon_get_encoder_id
1959 (dev, devices, 0),
1960 devices);
1961 radeon_add_legacy_connector(dev, i, devices,
1962 legacy_connector_convert
1963 [connector],
b75fad06 1964 &ddc_i2c,
eed45b30
AD		 1965 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1966 &hpd);
771fe6b9
JG		 1967 break;
1968 case CONNECTOR_CRT_LEGACY:
1969 if (tmp & 0x1) {
1970 devices = ATOM_DEVICE_CRT2_SUPPORT;
1971 radeon_add_legacy_encoder(dev,
1972 radeon_get_encoder_id
1973 (dev,
1974 ATOM_DEVICE_CRT2_SUPPORT,
1975 2),
1976 ATOM_DEVICE_CRT2_SUPPORT);
1977 } else {
1978 devices = ATOM_DEVICE_CRT1_SUPPORT;
1979 radeon_add_legacy_encoder(dev,
1980 radeon_get_encoder_id
1981 (dev,
1982 ATOM_DEVICE_CRT1_SUPPORT,
1983 1),
1984 ATOM_DEVICE_CRT1_SUPPORT);
1985 }
1986 radeon_add_legacy_connector(dev,
1987 i,
1988 devices,
1989 legacy_connector_convert
1990 [connector],
b75fad06 1991 &ddc_i2c,
eed45b30
AD		 1992 CONNECTOR_OBJECT_ID_VGA,
1993 &hpd);
771fe6b9
JG		 1994 break;
1995 case CONNECTOR_DVI_I_LEGACY:
1996 devices = 0;
1997 if (tmp & 0x1) {
1998 devices |= ATOM_DEVICE_CRT2_SUPPORT;
1999 radeon_add_legacy_encoder(dev,
2000 radeon_get_encoder_id
2001 (dev,
2002 ATOM_DEVICE_CRT2_SUPPORT,
2003 2),
2004 ATOM_DEVICE_CRT2_SUPPORT);
2005 } else {
2006 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2007 radeon_add_legacy_encoder(dev,
2008 radeon_get_encoder_id
2009 (dev,
2010 ATOM_DEVICE_CRT1_SUPPORT,
2011 1),
2012 ATOM_DEVICE_CRT1_SUPPORT);
2013 }
2014 if ((tmp >> 4) & 0x1) {
2015 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2016 radeon_add_legacy_encoder(dev,
2017 radeon_get_encoder_id
2018 (dev,
2019 ATOM_DEVICE_DFP2_SUPPORT,
2020 0),
2021 ATOM_DEVICE_DFP2_SUPPORT);
b75fad06 2022 connector_object_id = combios_check_dl_dvi(dev, 0);
771fe6b9
JG		 2023 } else {
2024 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2025 radeon_add_legacy_encoder(dev,
2026 radeon_get_encoder_id
2027 (dev,
2028 ATOM_DEVICE_DFP1_SUPPORT,
2029 0),
2030 ATOM_DEVICE_DFP1_SUPPORT);
b75fad06 2031 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
771fe6b9
JG		 2032 }
2033 radeon_add_legacy_connector(dev,
2034 i,
2035 devices,
2036 legacy_connector_convert
2037 [connector],
b75fad06 2038 &ddc_i2c,
eed45b30
AD		 2039 connector_object_id,
2040 &hpd);
771fe6b9
JG		 2041 break;
2042 case CONNECTOR_DVI_D_LEGACY:
b75fad06 2043 if ((tmp >> 4) & 0x1) {
771fe6b9 2044 devices = ATOM_DEVICE_DFP2_SUPPORT;
b75fad06
AD		 2045 connector_object_id = combios_check_dl_dvi(dev, 1);
2046 } else {
771fe6b9 2047 devices = ATOM_DEVICE_DFP1_SUPPORT;
b75fad06
AD		 2048 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2049 }
771fe6b9
JG		 2050 radeon_add_legacy_encoder(dev,
2051 radeon_get_encoder_id
2052 (dev, devices, 0),
2053 devices);
2054 radeon_add_legacy_connector(dev, i, devices,
2055 legacy_connector_convert
2056 [connector],
b75fad06 2057 &ddc_i2c,
eed45b30
AD		 2058 connector_object_id,
2059 &hpd);
771fe6b9
JG		 2060 break;
2061 case CONNECTOR_CTV_LEGACY:
2062 case CONNECTOR_STV_LEGACY:
2063 radeon_add_legacy_encoder(dev,
2064 radeon_get_encoder_id
2065 (dev,
2066 ATOM_DEVICE_TV1_SUPPORT,
2067 2),
2068 ATOM_DEVICE_TV1_SUPPORT);
2069 radeon_add_legacy_connector(dev, i,
2070 ATOM_DEVICE_TV1_SUPPORT,
2071 legacy_connector_convert
2072 [connector],
b75fad06 2073 &ddc_i2c,
eed45b30
AD		 2074 CONNECTOR_OBJECT_ID_SVIDEO,
2075 &hpd);
771fe6b9
JG		 2076 break;
2077 default:
2078 DRM_ERROR("Unknown connector type: %d\n",
2079 connector);
2080 continue;
2081 }
2082
2083 }
2084 } else {
2085 uint16_t tmds_info =
2086 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2087 if (tmds_info) {
2088 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
2089
2090 radeon_add_legacy_encoder(dev,
2091 radeon_get_encoder_id(dev,
2092 ATOM_DEVICE_CRT1_SUPPORT,
2093 1),
2094 ATOM_DEVICE_CRT1_SUPPORT);
2095 radeon_add_legacy_encoder(dev,
2096 radeon_get_encoder_id(dev,
2097 ATOM_DEVICE_DFP1_SUPPORT,
2098 0),
2099 ATOM_DEVICE_DFP1_SUPPORT);
2100
6a93cb25 2101 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 2102 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 2103 radeon_add_legacy_connector(dev,
2104 0,
2105 ATOM_DEVICE_CRT1_SUPPORT |
2106 ATOM_DEVICE_DFP1_SUPPORT,
2107 DRM_MODE_CONNECTOR_DVII,
b75fad06 2108 &ddc_i2c,
eed45b30
AD		 2109 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2110 &hpd);
771fe6b9 2111 } else {
d0c403e9
AD		 2112 uint16_t crt_info =
2113 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2114 DRM_DEBUG("Found CRT table, assuming VGA connector\n");
2115 if (crt_info) {
2116 radeon_add_legacy_encoder(dev,
2117 radeon_get_encoder_id(dev,
2118 ATOM_DEVICE_CRT1_SUPPORT,
2119 1),
2120 ATOM_DEVICE_CRT1_SUPPORT);
6a93cb25 2121 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 2122 hpd.hpd = RADEON_HPD_NONE;
d0c403e9
AD		 2123 radeon_add_legacy_connector(dev,
2124 0,
2125 ATOM_DEVICE_CRT1_SUPPORT,
2126 DRM_MODE_CONNECTOR_VGA,
b75fad06 2127 &ddc_i2c,
eed45b30
AD		 2128 CONNECTOR_OBJECT_ID_VGA,
2129 &hpd);
d0c403e9
AD		 2130 } else {
2131 DRM_DEBUG("No connector info found\n");
2132 return false;
2133 }
771fe6b9
JG		 2134 }
2135 }
2136
2137 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2138 uint16_t lcd_info =
2139 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2140 if (lcd_info) {
2141 uint16_t lcd_ddc_info =
2142 combios_get_table_offset(dev,
2143 COMBIOS_LCD_DDC_INFO_TABLE);
2144
2145 radeon_add_legacy_encoder(dev,
2146 radeon_get_encoder_id(dev,
2147 ATOM_DEVICE_LCD1_SUPPORT,
2148 0),
2149 ATOM_DEVICE_LCD1_SUPPORT);
2150
2151 if (lcd_ddc_info) {
2152 ddc_type = RBIOS8(lcd_ddc_info + 2);
2153 switch (ddc_type) {
2154 case DDC_MONID:
2155 ddc_i2c =
2156 combios_setup_i2c_bus
6a93cb25 2157 (rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 2158 break;
2159 case DDC_DVI:
2160 ddc_i2c =
2161 combios_setup_i2c_bus
6a93cb25 2162 (rdev, RADEON_GPIO_DVI_DDC);
771fe6b9
JG		 2163 break;
2164 case DDC_VGA:
2165 ddc_i2c =
2166 combios_setup_i2c_bus
6a93cb25 2167 (rdev, RADEON_GPIO_VGA_DDC);
771fe6b9
JG		 2168 break;
2169 case DDC_CRT2:
2170 ddc_i2c =
2171 combios_setup_i2c_bus
6a93cb25 2172 (rdev, RADEON_GPIO_CRT2_DDC);
771fe6b9
JG		 2173 break;
2174 case DDC_LCD:
2175 ddc_i2c =
2176 combios_setup_i2c_bus
6a93cb25 2177 (rdev, RADEON_GPIOPAD_MASK);
771fe6b9
JG		 2178 ddc_i2c.mask_clk_mask =
2179 RBIOS32(lcd_ddc_info + 3);
2180 ddc_i2c.mask_data_mask =
2181 RBIOS32(lcd_ddc_info + 7);
2182 ddc_i2c.a_clk_mask =
2183 RBIOS32(lcd_ddc_info + 3);
2184 ddc_i2c.a_data_mask =
2185 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2186 ddc_i2c.en_clk_mask =
771fe6b9 2187 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2188 ddc_i2c.en_data_mask =
771fe6b9 2189 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2190 ddc_i2c.y_clk_mask =
771fe6b9 2191 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2192 ddc_i2c.y_data_mask =
771fe6b9
JG		 2193 RBIOS32(lcd_ddc_info + 7);
2194 break;
2195 case DDC_GPIO:
2196 ddc_i2c =
2197 combios_setup_i2c_bus
6a93cb25 2198 (rdev, RADEON_MDGPIO_MASK);
771fe6b9
JG		 2199 ddc_i2c.mask_clk_mask =
2200 RBIOS32(lcd_ddc_info + 3);
2201 ddc_i2c.mask_data_mask =
2202 RBIOS32(lcd_ddc_info + 7);
2203 ddc_i2c.a_clk_mask =
2204 RBIOS32(lcd_ddc_info + 3);
2205 ddc_i2c.a_data_mask =
2206 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2207 ddc_i2c.en_clk_mask =
771fe6b9 2208 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2209 ddc_i2c.en_data_mask =
771fe6b9 2210 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2211 ddc_i2c.y_clk_mask =
771fe6b9 2212 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2213 ddc_i2c.y_data_mask =
771fe6b9
JG		 2214 RBIOS32(lcd_ddc_info + 7);
2215 break;
2216 default:
2217 ddc_i2c.valid = false;
2218 break;
2219 }
2220 DRM_DEBUG("LCD DDC Info Table found!\n");
2221 } else
2222 ddc_i2c.valid = false;
2223
eed45b30 2224 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 2225 radeon_add_legacy_connector(dev,
2226 5,
2227 ATOM_DEVICE_LCD1_SUPPORT,
2228 DRM_MODE_CONNECTOR_LVDS,
b75fad06 2229 &ddc_i2c,
eed45b30
AD		 2230 CONNECTOR_OBJECT_ID_LVDS,
2231 &hpd);
771fe6b9
JG		 2232 }
2233 }
2234
2235 /* check TV table */
2236 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2237 uint32_t tv_info =
2238 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2239 if (tv_info) {
2240 if (RBIOS8(tv_info + 6) == 'T') {
790cfb34 2241 if (radeon_apply_legacy_tv_quirks(dev)) {
eed45b30 2242 hpd.hpd = RADEON_HPD_NONE;
790cfb34
AD		 2243 radeon_add_legacy_encoder(dev,
2244 radeon_get_encoder_id
2245 (dev,
2246 ATOM_DEVICE_TV1_SUPPORT,
2247 2),
2248 ATOM_DEVICE_TV1_SUPPORT);
2249 radeon_add_legacy_connector(dev, 6,
2250 ATOM_DEVICE_TV1_SUPPORT,
2251 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 2252 &ddc_i2c,
eed45b30
AD		 2253 CONNECTOR_OBJECT_ID_SVIDEO,
2254 &hpd);
790cfb34 2255 }
771fe6b9
JG		 2256 }
2257 }
2258 }
2259
2260 radeon_link_encoder_connector(dev);
2261
2262 return true;
2263}
2264
fcec570b
AD		 2265void radeon_external_tmds_setup(struct drm_encoder *encoder)
2266{
2267 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2268 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2269
2270 if (!tmds)
2271 return;
2272
2273 switch (tmds->dvo_chip) {
2274 case DVO_SIL164:
2275 /* sil 164 */
2276 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2277 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2278 tmds->slave_addr,
2279 0x08, 0x30);
2280 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2281 tmds->slave_addr,
2282 0x09, 0x00);
2283 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2284 tmds->slave_addr,
2285 0x0a, 0x90);
2286 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2287 tmds->slave_addr,
2288 0x0c, 0x89);
2289 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2290 tmds->slave_addr,
2291 0x08, 0x3b);
2292 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2293 break;
2294 case DVO_SIL1178:
2295 /* sil 1178 - untested */
2296 /*
2297 * 0x0f, 0x44
2298 * 0x0f, 0x4c
2299 * 0x0e, 0x01
2300 * 0x0a, 0x80
2301 * 0x09, 0x30
2302 * 0x0c, 0xc9
2303 * 0x0d, 0x70
2304 * 0x08, 0x32
2305 * 0x08, 0x33
2306 */
2307 break;
2308 default:
2309 break;
2310 }
2311
2312}
2313
2314bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2315{
2316 struct drm_device *dev = encoder->dev;
2317 struct radeon_device *rdev = dev->dev_private;
2318 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2319 uint16_t offset;
2320 uint8_t blocks, slave_addr, rev;
2321 uint32_t index, id;
2322 uint32_t reg, val, and_mask, or_mask;
2323 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2324
2325 if (rdev->bios == NULL)
2326 return false;
2327
2328 if (!tmds)
2329 return false;
2330
2331 if (rdev->flags & RADEON_IS_IGP) {
2332 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2333 rev = RBIOS8(offset);
2334 if (offset) {
2335 rev = RBIOS8(offset);
2336 if (rev > 1) {
2337 blocks = RBIOS8(offset + 3);
2338 index = offset + 4;
2339 while (blocks > 0) {
2340 id = RBIOS16(index);
2341 index += 2;
2342 switch (id >> 13) {
2343 case 0:
2344 reg = (id & 0x1fff) * 4;
2345 val = RBIOS32(index);
2346 index += 4;
2347 WREG32(reg, val);
2348 break;
2349 case 2:
2350 reg = (id & 0x1fff) * 4;
2351 and_mask = RBIOS32(index);
2352 index += 4;
2353 or_mask = RBIOS32(index);
2354 index += 4;
2355 val = RREG32(reg);
2356 val = (val & and_mask) | or_mask;
2357 WREG32(reg, val);
2358 break;
2359 case 3:
2360 val = RBIOS16(index);
2361 index += 2;
2362 udelay(val);
2363 break;
2364 case 4:
2365 val = RBIOS16(index);
2366 index += 2;
2367 udelay(val * 1000);
2368 break;
2369 case 6:
2370 slave_addr = id & 0xff;
2371 slave_addr >>= 1; /* 7 bit addressing */
2372 index++;
2373 reg = RBIOS8(index);
2374 index++;
2375 val = RBIOS8(index);
2376 index++;
2377 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2378 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2379 slave_addr,
2380 reg, val);
2381 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2382 break;
2383 default:
2384 DRM_ERROR("Unknown id %d\n", id >> 13);
2385 break;
2386 }
2387 blocks--;
2388 }
2389 return true;
2390 }
2391 }
2392 } else {
2393 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2394 if (offset) {
2395 index = offset + 10;
2396 id = RBIOS16(index);
2397 while (id != 0xffff) {
2398 index += 2;
2399 switch (id >> 13) {
2400 case 0:
2401 reg = (id & 0x1fff) * 4;
2402 val = RBIOS32(index);
2403 WREG32(reg, val);
2404 break;
2405 case 2:
2406 reg = (id & 0x1fff) * 4;
2407 and_mask = RBIOS32(index);
2408 index += 4;
2409 or_mask = RBIOS32(index);
2410 index += 4;
2411 val = RREG32(reg);
2412 val = (val & and_mask) | or_mask;
2413 WREG32(reg, val);
2414 break;
2415 case 4:
2416 val = RBIOS16(index);
2417 index += 2;
2418 udelay(val);
2419 break;
2420 case 5:
2421 reg = id & 0x1fff;
2422 and_mask = RBIOS32(index);
2423 index += 4;
2424 or_mask = RBIOS32(index);
2425 index += 4;
2426 val = RREG32_PLL(reg);
2427 val = (val & and_mask) | or_mask;
2428 WREG32_PLL(reg, val);
2429 break;
2430 case 6:
2431 reg = id & 0x1fff;
2432 val = RBIOS8(index);
2433 index += 1;
2434 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2435 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2436 tmds->slave_addr,
2437 reg, val);
2438 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2439 break;
2440 default:
2441 DRM_ERROR("Unknown id %d\n", id >> 13);
2442 break;
2443 }
2444 id = RBIOS16(index);
2445 }
2446 return true;
2447 }
2448 }
2449 return false;
2450}
2451
771fe6b9
JG		 2452static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2453{
2454 struct radeon_device *rdev = dev->dev_private;
2455
2456 if (offset) {
2457 while (RBIOS16(offset)) {
2458 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2459 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2460 uint32_t val, and_mask, or_mask;
2461 uint32_t tmp;
2462
2463 offset += 2;
2464 switch (cmd) {
2465 case 0:
2466 val = RBIOS32(offset);
2467 offset += 4;
2468 WREG32(addr, val);
2469 break;
2470 case 1:
2471 val = RBIOS32(offset);
2472 offset += 4;
2473 WREG32(addr, val);
2474 break;
2475 case 2:
2476 and_mask = RBIOS32(offset);
2477 offset += 4;
2478 or_mask = RBIOS32(offset);
2479 offset += 4;
2480 tmp = RREG32(addr);
2481 tmp &= and_mask;
2482 tmp |= or_mask;
2483 WREG32(addr, tmp);
2484 break;
2485 case 3:
2486 and_mask = RBIOS32(offset);
2487 offset += 4;
2488 or_mask = RBIOS32(offset);
2489 offset += 4;
2490 tmp = RREG32(addr);
2491 tmp &= and_mask;
2492 tmp |= or_mask;
2493 WREG32(addr, tmp);
2494 break;
2495 case 4:
2496 val = RBIOS16(offset);
2497 offset += 2;
2498 udelay(val);
2499 break;
2500 case 5:
2501 val = RBIOS16(offset);
2502 offset += 2;
2503 switch (addr) {
2504 case 8:
2505 while (val--) {
2506 if (!
2507 (RREG32_PLL
2508 (RADEON_CLK_PWRMGT_CNTL) &
2509 RADEON_MC_BUSY))
2510 break;
2511 }
2512 break;
2513 case 9:
2514 while (val--) {
2515 if ((RREG32(RADEON_MC_STATUS) &
2516 RADEON_MC_IDLE))
2517 break;
2518 }
2519 break;
2520 default:
2521 break;
2522 }
2523 break;
2524 default:
2525 break;
2526 }
2527 }
2528 }
2529}
2530
2531static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2532{
2533 struct radeon_device *rdev = dev->dev_private;
2534
2535 if (offset) {
2536 while (RBIOS8(offset)) {
2537 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2538 uint8_t addr = (RBIOS8(offset) & 0x3f);
2539 uint32_t val, shift, tmp;
2540 uint32_t and_mask, or_mask;
2541
2542 offset++;
2543 switch (cmd) {
2544 case 0:
2545 val = RBIOS32(offset);
2546 offset += 4;
2547 WREG32_PLL(addr, val);
2548 break;
2549 case 1:
2550 shift = RBIOS8(offset) * 8;
2551 offset++;
2552 and_mask = RBIOS8(offset) << shift;
2553 and_mask |= ~(0xff << shift);
2554 offset++;
2555 or_mask = RBIOS8(offset) << shift;
2556 offset++;
2557 tmp = RREG32_PLL(addr);
2558 tmp &= and_mask;
2559 tmp |= or_mask;
2560 WREG32_PLL(addr, tmp);
2561 break;
2562 case 2:
2563 case 3:
2564 tmp = 1000;
2565 switch (addr) {
2566 case 1:
2567 udelay(150);
2568 break;
2569 case 2:
2570 udelay(1000);
2571 break;
2572 case 3:
2573 while (tmp--) {
2574 if (!
2575 (RREG32_PLL
2576 (RADEON_CLK_PWRMGT_CNTL) &
2577 RADEON_MC_BUSY))
2578 break;
2579 }
2580 break;
2581 case 4:
2582 while (tmp--) {
2583 if (RREG32_PLL
2584 (RADEON_CLK_PWRMGT_CNTL) &
2585 RADEON_DLL_READY)
2586 break;
2587 }
2588 break;
2589 case 5:
2590 tmp =
2591 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2592 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2593#if 0
2594 uint32_t mclk_cntl =
2595 RREG32_PLL
2596 (RADEON_MCLK_CNTL);
2597 mclk_cntl &= 0xffff0000;
2598 /*mclk_cntl |= 0x00001111;*//* ??? */
2599 WREG32_PLL(RADEON_MCLK_CNTL,
2600 mclk_cntl);
2601 udelay(10000);
2602#endif
2603 WREG32_PLL
2604 (RADEON_CLK_PWRMGT_CNTL,
2605 tmp &
2606 ~RADEON_CG_NO1_DEBUG_0);
2607 udelay(10000);
2608 }
2609 break;
2610 default:
2611 break;
2612 }
2613 break;
2614 default:
2615 break;
2616 }
2617 }
2618 }
2619}
2620
2621static void combios_parse_ram_reset_table(struct drm_device *dev,
2622 uint16_t offset)
2623{
2624 struct radeon_device *rdev = dev->dev_private;
2625 uint32_t tmp;
2626
2627 if (offset) {
2628 uint8_t val = RBIOS8(offset);
2629 while (val != 0xff) {
2630 offset++;
2631
2632 if (val == 0x0f) {
2633 uint32_t channel_complete_mask;
2634
2635 if (ASIC_IS_R300(rdev))
2636 channel_complete_mask =
2637 R300_MEM_PWRUP_COMPLETE;
2638 else
2639 channel_complete_mask =
2640 RADEON_MEM_PWRUP_COMPLETE;
2641 tmp = 20000;
2642 while (tmp--) {
2643 if ((RREG32(RADEON_MEM_STR_CNTL) &
2644 channel_complete_mask) ==
2645 channel_complete_mask)
2646 break;
2647 }
2648 } else {
2649 uint32_t or_mask = RBIOS16(offset);
2650 offset += 2;
2651
2652 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2653 tmp &= RADEON_SDRAM_MODE_MASK;
2654 tmp |= or_mask;
2655 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2656
2657 or_mask = val << 24;
2658 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2659 tmp &= RADEON_B3MEM_RESET_MASK;
2660 tmp |= or_mask;
2661 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2662 }
2663 val = RBIOS8(offset);
2664 }
2665 }
2666}
2667
2668static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2669 int mem_addr_mapping)
2670{
2671 struct radeon_device *rdev = dev->dev_private;
2672 uint32_t mem_cntl;
2673 uint32_t mem_size;
2674 uint32_t addr = 0;
2675
2676 mem_cntl = RREG32(RADEON_MEM_CNTL);
2677 if (mem_cntl & RV100_HALF_MODE)
2678 ram /= 2;
2679 mem_size = ram;
2680 mem_cntl &= ~(0xff << 8);
2681 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2682 WREG32(RADEON_MEM_CNTL, mem_cntl);
2683 RREG32(RADEON_MEM_CNTL);
2684
2685 /* sdram reset ? */
2686
2687 /* something like this???? */
2688 while (ram--) {
2689 addr = ram * 1024 * 1024;
2690 /* write to each page */
2691 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2692 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2693 /* read back and verify */
2694 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2695 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2696 return 0;
2697 }
2698
2699 return mem_size;
2700}
2701
2702static void combios_write_ram_size(struct drm_device *dev)
2703{
2704 struct radeon_device *rdev = dev->dev_private;
2705 uint8_t rev;
2706 uint16_t offset;
2707 uint32_t mem_size = 0;
2708 uint32_t mem_cntl = 0;
2709
2710 /* should do something smarter here I guess... */
2711 if (rdev->flags & RADEON_IS_IGP)
2712 return;
2713
2714 /* first check detected mem table */
2715 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2716 if (offset) {
2717 rev = RBIOS8(offset);
2718 if (rev < 3) {
2719 mem_cntl = RBIOS32(offset + 1);
2720 mem_size = RBIOS16(offset + 5);
2721 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2722 ((dev->pdev->device != 0x515e)
2723 && (dev->pdev->device != 0x5969)))
2724 WREG32(RADEON_MEM_CNTL, mem_cntl);
2725 }
2726 }
2727
2728 if (!mem_size) {
2729 offset =
2730 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2731 if (offset) {
2732 rev = RBIOS8(offset - 1);
2733 if (rev < 1) {
2734 if (((rdev->flags & RADEON_FAMILY_MASK) <
2735 CHIP_R200)
2736 && ((dev->pdev->device != 0x515e)
2737 && (dev->pdev->device != 0x5969))) {
2738 int ram = 0;
2739 int mem_addr_mapping = 0;
2740
2741 while (RBIOS8(offset)) {
2742 ram = RBIOS8(offset);
2743 mem_addr_mapping =
2744 RBIOS8(offset + 1);
2745 if (mem_addr_mapping != 0x25)
2746 ram *= 2;
2747 mem_size =
2748 combios_detect_ram(dev, ram,
2749 mem_addr_mapping);
2750 if (mem_size)
2751 break;
2752 offset += 2;
2753 }
2754 } else
2755 mem_size = RBIOS8(offset);
2756 } else {
2757 mem_size = RBIOS8(offset);
2758 mem_size *= 2; /* convert to MB */
2759 }
2760 }
2761 }
2762
2763 mem_size *= (1024 * 1024); /* convert to bytes */
2764 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2765}
2766
2767void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2768{
2769 uint16_t dyn_clk_info =
2770 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2771
2772 if (dyn_clk_info)
2773 combios_parse_pll_table(dev, dyn_clk_info);
2774}
2775
2776void radeon_combios_asic_init(struct drm_device *dev)
2777{
2778 struct radeon_device *rdev = dev->dev_private;
2779 uint16_t table;
2780
2781 /* port hardcoded mac stuff from radeonfb */
2782 if (rdev->bios == NULL)
2783 return;
2784
2785 /* ASIC INIT 1 */
2786 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2787 if (table)
2788 combios_parse_mmio_table(dev, table);
2789
2790 /* PLL INIT */
2791 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2792 if (table)
2793 combios_parse_pll_table(dev, table);
2794
2795 /* ASIC INIT 2 */
2796 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2797 if (table)
2798 combios_parse_mmio_table(dev, table);
2799
2800 if (!(rdev->flags & RADEON_IS_IGP)) {
2801 /* ASIC INIT 4 */
2802 table =
2803 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
2804 if (table)
2805 combios_parse_mmio_table(dev, table);
2806
2807 /* RAM RESET */
2808 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
2809 if (table)
2810 combios_parse_ram_reset_table(dev, table);
2811
2812 /* ASIC INIT 3 */
2813 table =
2814 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
2815 if (table)
2816 combios_parse_mmio_table(dev, table);
2817
2818 /* write CONFIG_MEMSIZE */
2819 combios_write_ram_size(dev);
2820 }
2821
2822 /* DYN CLK 1 */
2823 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2824 if (table)
2825 combios_parse_pll_table(dev, table);
2826
2827}
2828
2829void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
2830{
2831 struct radeon_device *rdev = dev->dev_private;
2832 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
2833
2834 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2835 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2836 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
2837
2838 /* let the bios control the backlight */
2839 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
2840
2841 /* tell the bios not to handle mode switching */
2842 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
2843 RADEON_ACC_MODE_CHANGE);
2844
2845 /* tell the bios a driver is loaded */
2846 bios_7_scratch |= RADEON_DRV_LOADED;
2847
2848 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2849 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2850 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
2851}
2852
2853void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
2854{
2855 struct drm_device *dev = encoder->dev;
2856 struct radeon_device *rdev = dev->dev_private;
2857 uint32_t bios_6_scratch;
2858
2859 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2860
2861 if (lock)
2862 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
2863 else
2864 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
2865
2866 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2867}
2868
2869void
2870radeon_combios_connected_scratch_regs(struct drm_connector *connector,
2871 struct drm_encoder *encoder,
2872 bool connected)
2873{
2874 struct drm_device *dev = connector->dev;
2875 struct radeon_device *rdev = dev->dev_private;
2876 struct radeon_connector *radeon_connector =
2877 to_radeon_connector(connector);
2878 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2879 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
2880 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2881
2882 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2883 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2884 if (connected) {
2885 DRM_DEBUG("TV1 connected\n");
2886 /* fix me */
2887 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
2888 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
2889 bios_5_scratch |= RADEON_TV1_ON;
2890 bios_5_scratch |= RADEON_ACC_REQ_TV1;
2891 } else {
2892 DRM_DEBUG("TV1 disconnected\n");
2893 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
2894 bios_5_scratch &= ~RADEON_TV1_ON;
2895 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
2896 }
2897 }
2898 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2899 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2900 if (connected) {
2901 DRM_DEBUG("LCD1 connected\n");
2902 bios_4_scratch |= RADEON_LCD1_ATTACHED;
2903 bios_5_scratch |= RADEON_LCD1_ON;
2904 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
2905 } else {
2906 DRM_DEBUG("LCD1 disconnected\n");
2907 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
2908 bios_5_scratch &= ~RADEON_LCD1_ON;
2909 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
2910 }
2911 }
2912 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2913 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2914 if (connected) {
2915 DRM_DEBUG("CRT1 connected\n");
2916 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
2917 bios_5_scratch |= RADEON_CRT1_ON;
2918 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
2919 } else {
2920 DRM_DEBUG("CRT1 disconnected\n");
2921 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
2922 bios_5_scratch &= ~RADEON_CRT1_ON;
2923 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
2924 }
2925 }
2926 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2927 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2928 if (connected) {
2929 DRM_DEBUG("CRT2 connected\n");
2930 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
2931 bios_5_scratch |= RADEON_CRT2_ON;
2932 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
2933 } else {
2934 DRM_DEBUG("CRT2 disconnected\n");
2935 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
2936 bios_5_scratch &= ~RADEON_CRT2_ON;
2937 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
2938 }
2939 }
2940 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2941 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2942 if (connected) {
2943 DRM_DEBUG("DFP1 connected\n");
2944 bios_4_scratch |= RADEON_DFP1_ATTACHED;
2945 bios_5_scratch |= RADEON_DFP1_ON;
2946 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
2947 } else {
2948 DRM_DEBUG("DFP1 disconnected\n");
2949 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
2950 bios_5_scratch &= ~RADEON_DFP1_ON;
2951 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
2952 }
2953 }
2954 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2955 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2956 if (connected) {
2957 DRM_DEBUG("DFP2 connected\n");
2958 bios_4_scratch |= RADEON_DFP2_ATTACHED;
2959 bios_5_scratch |= RADEON_DFP2_ON;
2960 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
2961 } else {
2962 DRM_DEBUG("DFP2 disconnected\n");
2963 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
2964 bios_5_scratch &= ~RADEON_DFP2_ON;
2965 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
2966 }
2967 }
2968 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
2969 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2970}
2971
2972void
2973radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2974{
2975 struct drm_device *dev = encoder->dev;
2976 struct radeon_device *rdev = dev->dev_private;
2977 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2978 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2979
2980 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2981 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
2982 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
2983 }
2984 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2985 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
2986 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
2987 }
2988 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2989 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
2990 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
2991 }
2992 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2993 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
2994 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
2995 }
2996 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2997 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
2998 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
2999 }
3000 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3001 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3002 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3003 }
3004 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3005}
3006
3007void
3008radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3009{
3010 struct drm_device *dev = encoder->dev;
3011 struct radeon_device *rdev = dev->dev_private;
3012 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3013 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3014
3015 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3016 if (on)
3017 bios_6_scratch |= RADEON_TV_DPMS_ON;
3018 else
3019 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3020 }
3021 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3022 if (on)
3023 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3024 else
3025 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3026 }
3027 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3028 if (on)
3029 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3030 else
3031 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3032 }
3033 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3034 if (on)
3035 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3036 else
3037 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3038 }
3039 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3040}
kernel source for telekom puls (alcatel/mediatek)