[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpio / gpio-msm-v2.c

/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
 * 02110-1301, USA.
 *
 */
#define pr_fmt(fmt) "%s: " fmt, __func__

#include <linux/bitmap.h>
#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>

#include <mach/msm_gpiomux.h>
#include <mach/msm_iomap.h>

/* Bits of interest in the GPIO_IN_OUT register.
 */
enum {
	GPIO_IN  = 0,
	GPIO_OUT = 1
};

/* Bits of interest in the GPIO_INTR_STATUS register.
 */
enum {
	INTR_STATUS = 0,
};

/* Bits of interest in the GPIO_CFG register.
 */
enum {
	GPIO_OE = 9,
};

/* Bits of interest in the GPIO_INTR_CFG register.
 * When a GPIO triggers, two separate decisions are made, controlled
 * by two separate flags.
 *
 * - First, INTR_RAW_STATUS_EN controls whether or not the GPIO_INTR_STATUS
 * register for that GPIO will be updated to reflect the triggering of that
 * gpio.  If this bit is 0, this register will not be updated.
 * - Second, INTR_ENABLE controls whether an interrupt is triggered.
 *
 * If INTR_ENABLE is set and INTR_RAW_STATUS_EN is NOT set, an interrupt
 * can be triggered but the status register will not reflect it.
 */
enum {
	INTR_ENABLE        = 0,
	INTR_POL_CTL       = 1,
	INTR_DECT_CTL      = 2,
	INTR_RAW_STATUS_EN = 3,
};

/* Codes of interest in GPIO_INTR_CFG_SU.
 */
enum {
	TARGET_PROC_SCORPION = 4,
	TARGET_PROC_NONE     = 7,
};


#define GPIO_INTR_CFG_SU(gpio)    (MSM_TLMM_BASE + 0x0400 + (0x04 * (gpio)))
#define GPIO_CONFIG(gpio)         (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio)))
#define GPIO_IN_OUT(gpio)         (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio)))
#define GPIO_INTR_CFG(gpio)       (MSM_TLMM_BASE + 0x1008 + (0x10 * (gpio)))
#define GPIO_INTR_STATUS(gpio)    (MSM_TLMM_BASE + 0x100c + (0x10 * (gpio)))

/**
 * struct msm_gpio_dev: the MSM8660 SoC GPIO device structure
 *
 * @enabled_irqs: a bitmap used to optimize the summary-irq handler.  By
 * keeping track of which gpios are unmasked as irq sources, we avoid
 * having to do readl calls on hundreds of iomapped registers each time
 * the summary interrupt fires in order to locate the active interrupts.
 *
 * @wake_irqs: a bitmap for tracking which interrupt lines are enabled
 * as wakeup sources.  When the device is suspended, interrupts which are
 * not wakeup sources are disabled.
 *
 * @dual_edge_irqs: a bitmap used to track which irqs are configured
 * as dual-edge, as this is not supported by the hardware and requires
 * some special handling in the driver.
 */
struct msm_gpio_dev {
	struct gpio_chip gpio_chip;
	DECLARE_BITMAP(enabled_irqs, NR_GPIO_IRQS);
	DECLARE_BITMAP(wake_irqs, NR_GPIO_IRQS);
	DECLARE_BITMAP(dual_edge_irqs, NR_GPIO_IRQS);
};

static DEFINE_SPINLOCK(tlmm_lock);

static inline struct msm_gpio_dev *to_msm_gpio_dev(struct gpio_chip *chip)
{
	return container_of(chip, struct msm_gpio_dev, gpio_chip);
}

static inline void set_gpio_bits(unsigned n, void __iomem *reg)
{
	writel(readl(reg) | n, reg);
}

static inline void clear_gpio_bits(unsigned n, void __iomem *reg)
{
	writel(readl(reg) & ~n, reg);
}

static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN);
}

static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	writel(val ? BIT(GPIO_OUT) : 0, GPIO_IN_OUT(offset));
}

static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	unsigned long irq_flags;

	spin_lock_irqsave(&tlmm_lock, irq_flags);
	clear_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset));
	spin_unlock_irqrestore(&tlmm_lock, irq_flags);
	return 0;
}

static int msm_gpio_direction_output(struct gpio_chip *chip,
				unsigned offset,
				int val)
{
	unsigned long irq_flags;

	spin_lock_irqsave(&tlmm_lock, irq_flags);
	msm_gpio_set(chip, offset, val);
	set_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset));
	spin_unlock_irqrestore(&tlmm_lock, irq_flags);
	return 0;
}

static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	return msm_gpiomux_get(chip->base + offset);
}

static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	msm_gpiomux_put(chip->base + offset);
}

static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	return MSM_GPIO_TO_INT(chip->base + offset);
}

static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq)
{
	return irq - MSM_GPIO_TO_INT(chip->base);
}

static struct msm_gpio_dev msm_gpio = {
	.gpio_chip = {
		.base             = 0,
		.ngpio            = NR_GPIO_IRQS,
		.direction_input  = msm_gpio_direction_input,
		.direction_output = msm_gpio_direction_output,
		.get              = msm_gpio_get,
		.set              = msm_gpio_set,
		.to_irq           = msm_gpio_to_irq,
		.request          = msm_gpio_request,
		.free             = msm_gpio_free,
	},
};

/* For dual-edge interrupts in software, since the hardware has no
 * such support:
 *
 * At appropriate moments, this function may be called to flip the polarity
 * settings of both-edge irq lines to try and catch the next edge.
 *
 * The attempt is considered successful if:
 * - the status bit goes high, indicating that an edge was caught, or
 * - the input value of the gpio doesn't change during the attempt.
 * If the value changes twice during the process, that would cause the first
 * test to fail but would force the second, as two opposite
 * transitions would cause a detection no matter the polarity setting.
 *
 * The do-loop tries to sledge-hammer closed the timing hole between
 * the initial value-read and the polarity-write - if the line value changes
 * during that window, an interrupt is lost, the new polarity setting is
 * incorrect, and the first success test will fail, causing a retry.
 *
 * Algorithm comes from Google's msmgpio driver, see mach-msm/gpio.c.
 */
static void msm_gpio_update_dual_edge_pos(unsigned gpio)
{
	int loop_limit = 100;
	unsigned val, val2, intstat;

	do {
		val = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN);
		if (val)
			clear_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio));
		else
			set_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio));
		val2 = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN);
		intstat = readl(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS);
		if (intstat || val == val2)
			return;
	} while (loop_limit-- > 0);
	pr_err("dual-edge irq failed to stabilize, "
	       "interrupts dropped. %#08x != %#08x\n",
	       val, val2);
}

static void msm_gpio_irq_ack(struct irq_data *d)
{
	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);

	writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio));
	if (test_bit(gpio, msm_gpio.dual_edge_irqs))
		msm_gpio_update_dual_edge_pos(gpio);
}

static void msm_gpio_irq_mask(struct irq_data *d)
{
	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
	unsigned long irq_flags;

	spin_lock_irqsave(&tlmm_lock, irq_flags);
	writel(TARGET_PROC_NONE, GPIO_INTR_CFG_SU(gpio));
	clear_gpio_bits(BIT(INTR_RAW_STATUS_EN) | BIT(INTR_ENABLE), GPIO_INTR_CFG(gpio));
	__clear_bit(gpio, msm_gpio.enabled_irqs);
	spin_unlock_irqrestore(&tlmm_lock, irq_flags);
}

static void msm_gpio_irq_unmask(struct irq_data *d)
{
	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
	unsigned long irq_flags;

	spin_lock_irqsave(&tlmm_lock, irq_flags);
	__set_bit(gpio, msm_gpio.enabled_irqs);
	set_gpio_bits(BIT(INTR_RAW_STATUS_EN) | BIT(INTR_ENABLE), GPIO_INTR_CFG(gpio));
	writel(TARGET_PROC_SCORPION, GPIO_INTR_CFG_SU(gpio));
	spin_unlock_irqrestore(&tlmm_lock, irq_flags);
}

static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
	unsigned long irq_flags;
	uint32_t bits;

	spin_lock_irqsave(&tlmm_lock, irq_flags);

	bits = readl(GPIO_INTR_CFG(gpio));

	if (flow_type & IRQ_TYPE_EDGE_BOTH) {
		bits |= BIT(INTR_DECT_CTL);
		__irq_set_handler_locked(d->irq, handle_edge_irq);
		if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
			__set_bit(gpio, msm_gpio.dual_edge_irqs);
		else
			__clear_bit(gpio, msm_gpio.dual_edge_irqs);
	} else {
		bits &= ~BIT(INTR_DECT_CTL);
		__irq_set_handler_locked(d->irq, handle_level_irq);
		__clear_bit(gpio, msm_gpio.dual_edge_irqs);
	}

	if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
		bits |= BIT(INTR_POL_CTL);
	else
		bits &= ~BIT(INTR_POL_CTL);

	writel(bits, GPIO_INTR_CFG(gpio));

	if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
		msm_gpio_update_dual_edge_pos(gpio);

	spin_unlock_irqrestore(&tlmm_lock, irq_flags);

	return 0;
}

/*
 * When the summary IRQ is raised, any number of GPIO lines may be high.
 * It is the job of the summary handler to find all those GPIO lines
 * which have been set as summary IRQ lines and which are triggered,
 * and to call their interrupt handlers.
 */
static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	unsigned long i;
	struct irq_chip *chip = irq_desc_get_chip(desc);

	chained_irq_enter(chip, desc);

	for_each_set_bit(i, msm_gpio.enabled_irqs, NR_GPIO_IRQS) {
		if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS))
			generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
							   i));
	}

	chained_irq_exit(chip, desc);
}

static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
{
	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);

	if (on) {
		if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
			irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
		set_bit(gpio, msm_gpio.wake_irqs);
	} else {
		clear_bit(gpio, msm_gpio.wake_irqs);
		if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
			irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
	}

	return 0;
}

static struct irq_chip msm_gpio_irq_chip = {
	.name		= "msmgpio",
	.irq_mask	= msm_gpio_irq_mask,
	.irq_unmask	= msm_gpio_irq_unmask,
	.irq_ack	= msm_gpio_irq_ack,
	.irq_set_type	= msm_gpio_irq_set_type,
	.irq_set_wake	= msm_gpio_irq_set_wake,
};

static int msm_gpio_probe(struct platform_device *dev)
{
	int i, irq, ret;

	bitmap_zero(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
	bitmap_zero(msm_gpio.wake_irqs, NR_GPIO_IRQS);
	bitmap_zero(msm_gpio.dual_edge_irqs, NR_GPIO_IRQS);
	msm_gpio.gpio_chip.label = dev->name;
	ret = gpiochip_add(&msm_gpio.gpio_chip);
	if (ret < 0)
		return ret;

	for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) {
		irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i);
		irq_set_chip_and_handler(irq, &msm_gpio_irq_chip,
					 handle_level_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	irq_set_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
				msm_summary_irq_handler);
	return 0;
}

static int msm_gpio_remove(struct platform_device *dev)
{
	int ret = gpiochip_remove(&msm_gpio.gpio_chip);

	if (ret < 0)
		return ret;

	irq_set_handler(TLMM_SCSS_SUMMARY_IRQ, NULL);

	return 0;
}

static struct platform_driver msm_gpio_driver = {
	.probe = msm_gpio_probe,
	.remove = msm_gpio_remove,
	.driver = {
		.name = "msmgpio",
		.owner = THIS_MODULE,
	},
};

static struct platform_device msm_device_gpio = {
	.name = "msmgpio",
	.id   = -1,
};

static int __init msm_gpio_init(void)
{
	int rc;

	rc = platform_driver_register(&msm_gpio_driver);
	if (!rc) {
		rc = platform_device_register(&msm_device_gpio);
		if (rc)
			platform_driver_unregister(&msm_gpio_driver);
	}

	return rc;
}

static void __exit msm_gpio_exit(void)
{
	platform_device_unregister(&msm_device_gpio);
	platform_driver_unregister(&msm_gpio_driver);
}

postcore_initcall(msm_gpio_init);
module_exit(msm_gpio_exit);

MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>");
MODULE_DESCRIPTION("Driver for Qualcomm MSM TLMMv2 SoC GPIOs");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:msmgpio");
Commit	Line	Data
1a5ab4b3	1	/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
0cc2fc1f GB	2	*
	3	* This program is free software; you can redistribute it and/or modify
	4	* it under the terms of the GNU General Public License version 2 and
	5	* only version 2 as published by the Free Software Foundation.
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*
	12	* You should have received a copy of the GNU General Public License
	13	* along with this program; if not, write to the Free Software
	14	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
	15	* 02110-1301, USA.
	16	*
	17	*/
70cc2c00 GB	18	#define pr_fmt(fmt) "%s: " fmt, __func__
	19
	20	#include <linux/bitmap.h>
	21	#include <linux/bitops.h>
0cc2fc1f	22	#include <linux/gpio.h>
70cc2c00 GB	23	#include <linux/init.h>
70cc2c00 GB	24	#include <linux/interrupt.h>
0cc2fc1f	25	#include <linux/io.h>
de88cbb7	26	#include <linux/irqchip/chained_irq.h>
0cc2fc1f GB	27	#include <linux/irq.h>
	28	#include <linux/module.h>
	29	#include <linux/platform_device.h>
	30	#include <linux/spinlock.h>
03dd765f	31
1a5ab4b3	32	#include <mach/msm_gpiomux.h>
0cc2fc1f	33	#include <mach/msm_iomap.h>
0cc2fc1f GB	34
	35	/* Bits of interest in the GPIO_IN_OUT register.
	36	*/
	37	enum {
70cc2c00 GB	38	GPIO_IN = 0,
	39	GPIO_OUT = 1
	40	};
	41
	42	/* Bits of interest in the GPIO_INTR_STATUS register.
	43	*/
	44	enum {
	45	INTR_STATUS = 0,
0cc2fc1f GB	46	};
	47
	48	/* Bits of interest in the GPIO_CFG register.
	49	*/
	50	enum {
70cc2c00 GB	51	GPIO_OE = 9,
	52	};
	53
	54	/* Bits of interest in the GPIO_INTR_CFG register.
	55	* When a GPIO triggers, two separate decisions are made, controlled
	56	* by two separate flags.
	57	*
	58	* - First, INTR_RAW_STATUS_EN controls whether or not the GPIO_INTR_STATUS
	59	* register for that GPIO will be updated to reflect the triggering of that
	60	* gpio. If this bit is 0, this register will not be updated.
	61	* - Second, INTR_ENABLE controls whether an interrupt is triggered.
	62	*
	63	* If INTR_ENABLE is set and INTR_RAW_STATUS_EN is NOT set, an interrupt
	64	* can be triggered but the status register will not reflect it.
	65	*/
	66	enum {
	67	INTR_ENABLE = 0,
	68	INTR_POL_CTL = 1,
	69	INTR_DECT_CTL = 2,
	70	INTR_RAW_STATUS_EN = 3,
	71	};
	72
	73	/* Codes of interest in GPIO_INTR_CFG_SU.
	74	*/
	75	enum {
	76	TARGET_PROC_SCORPION = 4,
	77	TARGET_PROC_NONE = 7,
0cc2fc1f GB	78	};
0cc2fc1f GB	79
70cc2c00 GB	80
70cc2c00 GB	81	#define GPIO_INTR_CFG_SU(gpio) (MSM_TLMM_BASE + 0x0400 + (0x04 * (gpio)))
0cc2fc1f GB	82	#define GPIO_CONFIG(gpio) (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio)))
0cc2fc1f GB	83	#define GPIO_IN_OUT(gpio) (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio)))
70cc2c00 GB	84	#define GPIO_INTR_CFG(gpio) (MSM_TLMM_BASE + 0x1008 + (0x10 * (gpio)))
	85	#define GPIO_INTR_STATUS(gpio) (MSM_TLMM_BASE + 0x100c + (0x10 * (gpio)))
	86
	87	/**
	88	* struct msm_gpio_dev: the MSM8660 SoC GPIO device structure
	89	*
	90	* @enabled_irqs: a bitmap used to optimize the summary-irq handler. By
	91	* keeping track of which gpios are unmasked as irq sources, we avoid
	92	* having to do readl calls on hundreds of iomapped registers each time
	93	* the summary interrupt fires in order to locate the active interrupts.
	94	*
	95	* @wake_irqs: a bitmap for tracking which interrupt lines are enabled
	96	* as wakeup sources. When the device is suspended, interrupts which are
	97	* not wakeup sources are disabled.
	98	*
	99	* @dual_edge_irqs: a bitmap used to track which irqs are configured
	100	* as dual-edge, as this is not supported by the hardware and requires
	101	* some special handling in the driver.
	102	*/
	103	struct msm_gpio_dev {
	104	struct gpio_chip gpio_chip;
	105	DECLARE_BITMAP(enabled_irqs, NR_GPIO_IRQS);
	106	DECLARE_BITMAP(wake_irqs, NR_GPIO_IRQS);
	107	DECLARE_BITMAP(dual_edge_irqs, NR_GPIO_IRQS);
	108	};
0cc2fc1f GB	109
	110	static DEFINE_SPINLOCK(tlmm_lock);
	111
70cc2c00 GB	112	static inline struct msm_gpio_dev to_msm_gpio_dev(struct gpio_chip chip)
	113	{
	114	return container_of(chip, struct msm_gpio_dev, gpio_chip);
	115	}
	116
	117	static inline void set_gpio_bits(unsigned n, void __iomem *reg)
	118	{
	119	writel(readl(reg) \| n, reg);
	120	}
	121
	122	static inline void clear_gpio_bits(unsigned n, void __iomem *reg)
	123	{
	124	writel(readl(reg) & ~n, reg);
	125	}
	126
0cc2fc1f GB	127	static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
0cc2fc1f GB	128	{
70cc2c00	129	return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN);
0cc2fc1f GB	130	}
	131
	132	static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
	133	{
70cc2c00	134	writel(val ? BIT(GPIO_OUT) : 0, GPIO_IN_OUT(offset));
0cc2fc1f GB	135	}
	136
	137	static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	138	{
	139	unsigned long irq_flags;
	140
	141	spin_lock_irqsave(&tlmm_lock, irq_flags);
70cc2c00	142	clear_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset));
0cc2fc1f GB	143	spin_unlock_irqrestore(&tlmm_lock, irq_flags);
	144	return 0;
	145	}
	146
	147	static int msm_gpio_direction_output(struct gpio_chip *chip,
	148	unsigned offset,
	149	int val)
	150	{
	151	unsigned long irq_flags;
	152
	153	spin_lock_irqsave(&tlmm_lock, irq_flags);
	154	msm_gpio_set(chip, offset, val);
70cc2c00	155	set_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset));
0cc2fc1f GB	156	spin_unlock_irqrestore(&tlmm_lock, irq_flags);
	157	return 0;
	158	}
	159
	160	static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
	161	{
	162	return msm_gpiomux_get(chip->base + offset);
	163	}
	164
	165	static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
	166	{
	167	msm_gpiomux_put(chip->base + offset);
	168	}
	169
70cc2c00 GB	170	static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	171	{
	172	return MSM_GPIO_TO_INT(chip->base + offset);
	173	}
	174
	175	static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq)
	176	{
	177	return irq - MSM_GPIO_TO_INT(chip->base);
	178	}
	179
	180	static struct msm_gpio_dev msm_gpio = {
	181	.gpio_chip = {
	182	.base = 0,
	183	.ngpio = NR_GPIO_IRQS,
	184	.direction_input = msm_gpio_direction_input,
	185	.direction_output = msm_gpio_direction_output,
	186	.get = msm_gpio_get,
	187	.set = msm_gpio_set,
	188	.to_irq = msm_gpio_to_irq,
	189	.request = msm_gpio_request,
	190	.free = msm_gpio_free,
	191	},
	192	};
	193
	194	/* For dual-edge interrupts in software, since the hardware has no
	195	* such support:
	196	*
	197	* At appropriate moments, this function may be called to flip the polarity
	198	* settings of both-edge irq lines to try and catch the next edge.
	199	*
	200	* The attempt is considered successful if:
	201	* - the status bit goes high, indicating that an edge was caught, or
	202	* - the input value of the gpio doesn't change during the attempt.
	203	* If the value changes twice during the process, that would cause the first
	204	* test to fail but would force the second, as two opposite
	205	* transitions would cause a detection no matter the polarity setting.
	206	*
	207	* The do-loop tries to sledge-hammer closed the timing hole between
	208	* the initial value-read and the polarity-write - if the line value changes
	209	* during that window, an interrupt is lost, the new polarity setting is
	210	* incorrect, and the first success test will fail, causing a retry.
	211	*
	212	* Algorithm comes from Google's msmgpio driver, see mach-msm/gpio.c.
	213	*/
	214	static void msm_gpio_update_dual_edge_pos(unsigned gpio)
	215	{
	216	int loop_limit = 100;
	217	unsigned val, val2, intstat;
	218
	219	do {
	220	val = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN);
	221	if (val)
	222	clear_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio));
	223	else
	224	set_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio));
	225	val2 = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN);
	226	intstat = readl(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS);
	227	if (intstat \|\| val == val2)
	228	return;
	229	} while (loop_limit-- > 0);
	230	pr_err("dual-edge irq failed to stabilize, "
	231	"interrupts dropped. %#08x != %#08x\n",
	232	val, val2);
	233	}
234
cf8d1581	235	static void msm_gpio_irq_ack(struct irq_data *d)
70cc2c00	236	{
cf8d1581	237	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
70cc2c00 GB	238
	239	writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio));
	240	if (test_bit(gpio, msm_gpio.dual_edge_irqs))
	241	msm_gpio_update_dual_edge_pos(gpio);
	242	}
	243
cf8d1581	244	static void msm_gpio_irq_mask(struct irq_data *d)
70cc2c00	245	{
cf8d1581	246	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
70cc2c00 GB	247	unsigned long irq_flags;
	248
	249	spin_lock_irqsave(&tlmm_lock, irq_flags);
	250	writel(TARGET_PROC_NONE, GPIO_INTR_CFG_SU(gpio));
db74f022	251	clear_gpio_bits(BIT(INTR_RAW_STATUS_EN) \| BIT(INTR_ENABLE), GPIO_INTR_CFG(gpio));
70cc2c00 GB	252	__clear_bit(gpio, msm_gpio.enabled_irqs);
	253	spin_unlock_irqrestore(&tlmm_lock, irq_flags);
	254	}
	255
cf8d1581	256	static void msm_gpio_irq_unmask(struct irq_data *d)
70cc2c00	257	{
cf8d1581	258	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
70cc2c00 GB	259	unsigned long irq_flags;
	260
	261	spin_lock_irqsave(&tlmm_lock, irq_flags);
	262	__set_bit(gpio, msm_gpio.enabled_irqs);
db74f022	263	set_gpio_bits(BIT(INTR_RAW_STATUS_EN) \| BIT(INTR_ENABLE), GPIO_INTR_CFG(gpio));
70cc2c00 GB	264	writel(TARGET_PROC_SCORPION, GPIO_INTR_CFG_SU(gpio));
	265	spin_unlock_irqrestore(&tlmm_lock, irq_flags);
	266	}
	267
cf8d1581	268	static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
70cc2c00	269	{
cf8d1581	270	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
70cc2c00 GB	271	unsigned long irq_flags;
	272	uint32_t bits;
	273
	274	spin_lock_irqsave(&tlmm_lock, irq_flags);
	275
	276	bits = readl(GPIO_INTR_CFG(gpio));
	277
	278	if (flow_type & IRQ_TYPE_EDGE_BOTH) {
	279	bits \|= BIT(INTR_DECT_CTL);
70c4fa22	280	__irq_set_handler_locked(d->irq, handle_edge_irq);
70cc2c00 GB	281	if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
	282	__set_bit(gpio, msm_gpio.dual_edge_irqs);
	283	else
	284	__clear_bit(gpio, msm_gpio.dual_edge_irqs);
	285	} else {
	286	bits &= ~BIT(INTR_DECT_CTL);
70c4fa22	287	__irq_set_handler_locked(d->irq, handle_level_irq);
70cc2c00 GB	288	__clear_bit(gpio, msm_gpio.dual_edge_irqs);
	289	}
	290
	291	if (flow_type & (IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_LEVEL_HIGH))
	292	bits \|= BIT(INTR_POL_CTL);
	293	else
	294	bits &= ~BIT(INTR_POL_CTL);
	295
	296	writel(bits, GPIO_INTR_CFG(gpio));
	297
	298	if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
	299	msm_gpio_update_dual_edge_pos(gpio);
	300
	301	spin_unlock_irqrestore(&tlmm_lock, irq_flags);
	302
	303	return 0;
	304	}
	305
	306	/*
	307	* When the summary IRQ is raised, any number of GPIO lines may be high.
	308	* It is the job of the summary handler to find all those GPIO lines
	309	* which have been set as summary IRQ lines and which are triggered,
	310	* and to call their interrupt handlers.
	311	*/
	312	static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
	313	{
	314	unsigned long i;
03dd765f WD	315	struct irq_chip *chip = irq_desc_get_chip(desc);
	316
	317	chained_irq_enter(chip, desc);
70cc2c00	318
939d902d	319	for_each_set_bit(i, msm_gpio.enabled_irqs, NR_GPIO_IRQS) {
70cc2c00 GB	320	if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS))
	321	generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
	322	i));
	323	}
03dd765f WD	324
03dd765f WD	325	chained_irq_exit(chip, desc);
70cc2c00 GB	326	}
70cc2c00 GB	327
cf8d1581	328	static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
70cc2c00	329	{
cf8d1581	330	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
70cc2c00 GB	331
	332	if (on) {
	333	if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
6845664a	334	irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
70cc2c00 GB	335	set_bit(gpio, msm_gpio.wake_irqs);
	336	} else {
	337	clear_bit(gpio, msm_gpio.wake_irqs);
	338	if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
6845664a	339	irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
70cc2c00 GB	340	}
	341
	342	return 0;
	343	}
	344
	345	static struct irq_chip msm_gpio_irq_chip = {
	346	.name = "msmgpio",
cf8d1581 TG	347	.irq_mask = msm_gpio_irq_mask,
	348	.irq_unmask = msm_gpio_irq_unmask,
	349	.irq_ack = msm_gpio_irq_ack,
	350	.irq_set_type = msm_gpio_irq_set_type,
	351	.irq_set_wake = msm_gpio_irq_set_wake,
0cc2fc1f GB	352	};
0cc2fc1f GB	353
3836309d	354	static int msm_gpio_probe(struct platform_device *dev)
0cc2fc1f	355	{
70cc2c00 GB	356	int i, irq, ret;
	357
	358	bitmap_zero(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
	359	bitmap_zero(msm_gpio.wake_irqs, NR_GPIO_IRQS);
	360	bitmap_zero(msm_gpio.dual_edge_irqs, NR_GPIO_IRQS);
	361	msm_gpio.gpio_chip.label = dev->name;
	362	ret = gpiochip_add(&msm_gpio.gpio_chip);
	363	if (ret < 0)
	364	return ret;
0cc2fc1f	365
70cc2c00 GB	366	for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) {
70cc2c00 GB	367	irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i);
f38c02f3 TG	368	irq_set_chip_and_handler(irq, &msm_gpio_irq_chip,
f38c02f3 TG	369	handle_level_irq);
70cc2c00 GB	370	set_irq_flags(irq, IRQF_VALID);
70cc2c00 GB	371	}
0cc2fc1f	372
6845664a	373	irq_set_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
70cc2c00 GB	374	msm_summary_irq_handler);
70cc2c00 GB	375	return 0;
0cc2fc1f GB	376	}
0cc2fc1f GB	377
206210ce	378	static int msm_gpio_remove(struct platform_device *dev)
0cc2fc1f	379	{
70cc2c00	380	int ret = gpiochip_remove(&msm_gpio.gpio_chip);
0cc2fc1f GB	381
	382	if (ret < 0)
	383	return ret;
	384
6845664a	385	irq_set_handler(TLMM_SCSS_SUMMARY_IRQ, NULL);
0cc2fc1f GB	386
	387	return 0;
	388	}
	389
	390	static struct platform_driver msm_gpio_driver = {
	391	.probe = msm_gpio_probe,
8283c4ff	392	.remove = msm_gpio_remove,
0cc2fc1f GB	393	.driver = {
	394	.name = "msmgpio",
	395	.owner = THIS_MODULE,
	396	},
	397	};
	398
	399	static struct platform_device msm_device_gpio = {
	400	.name = "msmgpio",
	401	.id = -1,
	402	};
	403
	404	static int __init msm_gpio_init(void)
	405	{
	406	int rc;
	407
	408	rc = platform_driver_register(&msm_gpio_driver);
	409	if (!rc) {
	410	rc = platform_device_register(&msm_device_gpio);
	411	if (rc)
	412	platform_driver_unregister(&msm_gpio_driver);
	413	}
	414
	415	return rc;
	416	}
	417
	418	static void __exit msm_gpio_exit(void)
	419	{
	420	platform_device_unregister(&msm_device_gpio);
	421	platform_driver_unregister(&msm_gpio_driver);
	422	}
	423
	424	postcore_initcall(msm_gpio_init);
	425	module_exit(msm_gpio_exit);
	426
	427	MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>");
	428	MODULE_DESCRIPTION("Driver for Qualcomm MSM TLMMv2 SoC GPIOs");
	429	MODULE_LICENSE("GPL v2");
	430	MODULE_ALIAS("platform:msmgpio");