dmatest: move dmatest_channels and nr_channels to dmatest_info
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / dma / dmatest.c
CommitLineData
4a776f0a
HS
1/*
2 * DMA Engine test module
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/delay.h>
b7f080cf 11#include <linux/dma-mapping.h>
4a776f0a 12#include <linux/dmaengine.h>
981ed70d 13#include <linux/freezer.h>
4a776f0a
HS
14#include <linux/init.h>
15#include <linux/kthread.h>
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/random.h>
5a0e3ad6 19#include <linux/slab.h>
4a776f0a
HS
20#include <linux/wait.h>
21
22static unsigned int test_buf_size = 16384;
23module_param(test_buf_size, uint, S_IRUGO);
24MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
25
06190d84 26static char test_channel[20];
4a776f0a
HS
27module_param_string(channel, test_channel, sizeof(test_channel), S_IRUGO);
28MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
29
06190d84 30static char test_device[20];
4a776f0a
HS
31module_param_string(device, test_device, sizeof(test_device), S_IRUGO);
32MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
33
34static unsigned int threads_per_chan = 1;
35module_param(threads_per_chan, uint, S_IRUGO);
36MODULE_PARM_DESC(threads_per_chan,
37 "Number of threads to start per channel (default: 1)");
38
39static unsigned int max_channels;
40module_param(max_channels, uint, S_IRUGO);
33df8ca0 41MODULE_PARM_DESC(max_channels,
4a776f0a
HS
42 "Maximum number of channels to use (default: all)");
43
0a2ff57d
NF
44static unsigned int iterations;
45module_param(iterations, uint, S_IRUGO);
46MODULE_PARM_DESC(iterations,
47 "Iterations before stopping test (default: infinite)");
48
b54d5cb9
DW
49static unsigned int xor_sources = 3;
50module_param(xor_sources, uint, S_IRUGO);
51MODULE_PARM_DESC(xor_sources,
52 "Number of xor source buffers (default: 3)");
53
58691d64
DW
54static unsigned int pq_sources = 3;
55module_param(pq_sources, uint, S_IRUGO);
56MODULE_PARM_DESC(pq_sources,
57 "Number of p+q source buffers (default: 3)");
58
d42efe6b
VK
59static int timeout = 3000;
60module_param(timeout, uint, S_IRUGO);
85ee7a1d
JP
61MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
62 "Pass -1 for infinite timeout");
d42efe6b 63
4a776f0a
HS
64/*
65 * Initialization patterns. All bytes in the source buffer has bit 7
66 * set, all bytes in the destination buffer has bit 7 cleared.
67 *
68 * Bit 6 is set for all bytes which are to be copied by the DMA
69 * engine. Bit 5 is set for all bytes which are to be overwritten by
70 * the DMA engine.
71 *
72 * The remaining bits are the inverse of a counter which increments by
73 * one for each byte address.
74 */
75#define PATTERN_SRC 0x80
76#define PATTERN_DST 0x00
77#define PATTERN_COPY 0x40
78#define PATTERN_OVERWRITE 0x20
79#define PATTERN_COUNT_MASK 0x1f
80
e03e93a9
AS
81struct dmatest_info;
82
4a776f0a
HS
83struct dmatest_thread {
84 struct list_head node;
e03e93a9 85 struct dmatest_info *info;
4a776f0a
HS
86 struct task_struct *task;
87 struct dma_chan *chan;
b54d5cb9
DW
88 u8 **srcs;
89 u8 **dsts;
90 enum dma_transaction_type type;
4a776f0a
HS
91};
92
93struct dmatest_chan {
94 struct list_head node;
95 struct dma_chan *chan;
96 struct list_head threads;
97};
98
e03e93a9
AS
99/**
100 * struct dmatest_info - test information.
101 * @buf_size: size of the memcpy test buffer
102 * @channel: bus ID of the channel to test
103 * @device: bus ID of the DMA Engine to test
104 * @threads_per_chan: number of threads to start per channel
105 * @max_channels: maximum number of channels to use
106 * @iterations: iterations before stopping test
107 * @xor_sources: number of xor source buffers
108 * @pq_sources: number of p+q source buffers
109 * @timeout: transfer timeout in msec, -1 for infinite timeout
110 */
111struct dmatest_info {
838cc704 112 /* Test parameters */
e03e93a9
AS
113 unsigned int buf_size;
114 char channel[20];
115 char device[20];
116 unsigned int threads_per_chan;
117 unsigned int max_channels;
118 unsigned int iterations;
119 unsigned int xor_sources;
120 unsigned int pq_sources;
121 int timeout;
838cc704
AS
122
123 /* Internal state */
124 struct list_head channels;
125 unsigned int nr_channels;
e03e93a9
AS
126};
127
128static struct dmatest_info test_info;
129
e03e93a9
AS
130static bool dmatest_match_channel(struct dmatest_info *info,
131 struct dma_chan *chan)
4a776f0a 132{
e03e93a9 133 if (info->channel[0] == '\0')
4a776f0a 134 return true;
e03e93a9 135 return strcmp(dma_chan_name(chan), info->channel) == 0;
4a776f0a
HS
136}
137
e03e93a9
AS
138static bool dmatest_match_device(struct dmatest_info *info,
139 struct dma_device *device)
4a776f0a 140{
e03e93a9 141 if (info->device[0] == '\0')
4a776f0a 142 return true;
e03e93a9 143 return strcmp(dev_name(device->dev), info->device) == 0;
4a776f0a
HS
144}
145
146static unsigned long dmatest_random(void)
147{
148 unsigned long buf;
149
150 get_random_bytes(&buf, sizeof(buf));
151 return buf;
152}
153
e03e93a9
AS
154static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len,
155 unsigned int buf_size)
4a776f0a
HS
156{
157 unsigned int i;
b54d5cb9
DW
158 u8 *buf;
159
160 for (; (buf = *bufs); bufs++) {
161 for (i = 0; i < start; i++)
162 buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
163 for ( ; i < start + len; i++)
164 buf[i] = PATTERN_SRC | PATTERN_COPY
c019894e 165 | (~i & PATTERN_COUNT_MASK);
e03e93a9 166 for ( ; i < buf_size; i++)
b54d5cb9
DW
167 buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
168 buf++;
169 }
4a776f0a
HS
170}
171
e03e93a9
AS
172static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len,
173 unsigned int buf_size)
4a776f0a
HS
174{
175 unsigned int i;
b54d5cb9
DW
176 u8 *buf;
177
178 for (; (buf = *bufs); bufs++) {
179 for (i = 0; i < start; i++)
180 buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
181 for ( ; i < start + len; i++)
182 buf[i] = PATTERN_DST | PATTERN_OVERWRITE
183 | (~i & PATTERN_COUNT_MASK);
e03e93a9 184 for ( ; i < buf_size; i++)
b54d5cb9
DW
185 buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
186 }
4a776f0a
HS
187}
188
189static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
190 unsigned int counter, bool is_srcbuf)
191{
192 u8 diff = actual ^ pattern;
193 u8 expected = pattern | (~counter & PATTERN_COUNT_MASK);
194 const char *thread_name = current->comm;
195
196 if (is_srcbuf)
197 pr_warning("%s: srcbuf[0x%x] overwritten!"
198 " Expected %02x, got %02x\n",
199 thread_name, index, expected, actual);
200 else if ((pattern & PATTERN_COPY)
201 && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
202 pr_warning("%s: dstbuf[0x%x] not copied!"
203 " Expected %02x, got %02x\n",
204 thread_name, index, expected, actual);
205 else if (diff & PATTERN_SRC)
206 pr_warning("%s: dstbuf[0x%x] was copied!"
207 " Expected %02x, got %02x\n",
208 thread_name, index, expected, actual);
209 else
210 pr_warning("%s: dstbuf[0x%x] mismatch!"
211 " Expected %02x, got %02x\n",
212 thread_name, index, expected, actual);
213}
214
b54d5cb9 215static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
4a776f0a
HS
216 unsigned int end, unsigned int counter, u8 pattern,
217 bool is_srcbuf)
218{
219 unsigned int i;
220 unsigned int error_count = 0;
221 u8 actual;
b54d5cb9
DW
222 u8 expected;
223 u8 *buf;
224 unsigned int counter_orig = counter;
225
226 for (; (buf = *bufs); bufs++) {
227 counter = counter_orig;
228 for (i = start; i < end; i++) {
229 actual = buf[i];
230 expected = pattern | (~counter & PATTERN_COUNT_MASK);
231 if (actual != expected) {
232 if (error_count < 32)
233 dmatest_mismatch(actual, pattern, i,
234 counter, is_srcbuf);
235 error_count++;
236 }
237 counter++;
4a776f0a 238 }
4a776f0a
HS
239 }
240
241 if (error_count > 32)
242 pr_warning("%s: %u errors suppressed\n",
243 current->comm, error_count - 32);
244
245 return error_count;
246}
247
adfa543e
TH
248/* poor man's completion - we want to use wait_event_freezable() on it */
249struct dmatest_done {
250 bool done;
251 wait_queue_head_t *wait;
252};
253
254static void dmatest_callback(void *arg)
e44e0aa3 255{
adfa543e
TH
256 struct dmatest_done *done = arg;
257
258 done->done = true;
259 wake_up_all(done->wait);
e44e0aa3
DW
260}
261
632fd283
AS
262static inline void unmap_src(struct device *dev, dma_addr_t *addr, size_t len,
263 unsigned int count)
264{
265 while (count--)
266 dma_unmap_single(dev, addr[count], len, DMA_TO_DEVICE);
267}
268
269static inline void unmap_dst(struct device *dev, dma_addr_t *addr, size_t len,
270 unsigned int count)
271{
272 while (count--)
273 dma_unmap_single(dev, addr[count], len, DMA_BIDIRECTIONAL);
274}
275
8be9e32b
AM
276static unsigned int min_odd(unsigned int x, unsigned int y)
277{
278 unsigned int val = min(x, y);
279
280 return val % 2 ? val : val - 1;
281}
282
4a776f0a
HS
283/*
284 * This function repeatedly tests DMA transfers of various lengths and
b54d5cb9
DW
285 * offsets for a given operation type until it is told to exit by
286 * kthread_stop(). There may be multiple threads running this function
287 * in parallel for a single channel, and there may be multiple channels
288 * being tested in parallel.
4a776f0a
HS
289 *
290 * Before each test, the source and destination buffer is initialized
291 * with a known pattern. This pattern is different depending on
292 * whether it's in an area which is supposed to be copied or
293 * overwritten, and different in the source and destination buffers.
294 * So if the DMA engine doesn't copy exactly what we tell it to copy,
295 * we'll notice.
296 */
297static int dmatest_func(void *data)
298{
adfa543e 299 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_wait);
4a776f0a 300 struct dmatest_thread *thread = data;
adfa543e 301 struct dmatest_done done = { .wait = &done_wait };
e03e93a9 302 struct dmatest_info *info;
4a776f0a 303 struct dma_chan *chan;
8be9e32b 304 struct dma_device *dev;
4a776f0a
HS
305 const char *thread_name;
306 unsigned int src_off, dst_off, len;
307 unsigned int error_count;
308 unsigned int failed_tests = 0;
309 unsigned int total_tests = 0;
310 dma_cookie_t cookie;
311 enum dma_status status;
b54d5cb9 312 enum dma_ctrl_flags flags;
945b5af3 313 u8 *pq_coefs = NULL;
4a776f0a 314 int ret;
b54d5cb9
DW
315 int src_cnt;
316 int dst_cnt;
317 int i;
4a776f0a
HS
318
319 thread_name = current->comm;
adfa543e 320 set_freezable();
4a776f0a
HS
321
322 ret = -ENOMEM;
4a776f0a
HS
323
324 smp_rmb();
e03e93a9 325 info = thread->info;
4a776f0a 326 chan = thread->chan;
8be9e32b 327 dev = chan->device;
b54d5cb9
DW
328 if (thread->type == DMA_MEMCPY)
329 src_cnt = dst_cnt = 1;
330 else if (thread->type == DMA_XOR) {
8be9e32b 331 /* force odd to ensure dst = src */
e03e93a9 332 src_cnt = min_odd(info->xor_sources | 1, dev->max_xor);
b54d5cb9 333 dst_cnt = 1;
58691d64 334 } else if (thread->type == DMA_PQ) {
8be9e32b 335 /* force odd to ensure dst = src */
e03e93a9 336 src_cnt = min_odd(info->pq_sources | 1, dma_maxpq(dev, 0));
58691d64 337 dst_cnt = 2;
945b5af3 338
e03e93a9 339 pq_coefs = kmalloc(info->pq_sources+1, GFP_KERNEL);
945b5af3
AS
340 if (!pq_coefs)
341 goto err_thread_type;
342
94de648d 343 for (i = 0; i < src_cnt; i++)
58691d64 344 pq_coefs[i] = 1;
b54d5cb9 345 } else
945b5af3 346 goto err_thread_type;
b54d5cb9
DW
347
348 thread->srcs = kcalloc(src_cnt+1, sizeof(u8 *), GFP_KERNEL);
349 if (!thread->srcs)
350 goto err_srcs;
351 for (i = 0; i < src_cnt; i++) {
e03e93a9 352 thread->srcs[i] = kmalloc(info->buf_size, GFP_KERNEL);
b54d5cb9
DW
353 if (!thread->srcs[i])
354 goto err_srcbuf;
355 }
356 thread->srcs[i] = NULL;
357
358 thread->dsts = kcalloc(dst_cnt+1, sizeof(u8 *), GFP_KERNEL);
359 if (!thread->dsts)
360 goto err_dsts;
361 for (i = 0; i < dst_cnt; i++) {
e03e93a9 362 thread->dsts[i] = kmalloc(info->buf_size, GFP_KERNEL);
b54d5cb9
DW
363 if (!thread->dsts[i])
364 goto err_dstbuf;
365 }
366 thread->dsts[i] = NULL;
367
e44e0aa3
DW
368 set_user_nice(current, 10);
369
b203bd3f
IS
370 /*
371 * src buffers are freed by the DMAEngine code with dma_unmap_single()
372 * dst buffers are freed by ourselves below
373 */
374 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT
375 | DMA_COMPL_SKIP_DEST_UNMAP | DMA_COMPL_SRC_UNMAP_SINGLE;
4a776f0a 376
0a2ff57d 377 while (!kthread_should_stop()
e03e93a9 378 && !(info->iterations && total_tests >= info->iterations)) {
b54d5cb9
DW
379 struct dma_async_tx_descriptor *tx = NULL;
380 dma_addr_t dma_srcs[src_cnt];
381 dma_addr_t dma_dsts[dst_cnt];
83544ae9 382 u8 align = 0;
d86be86e 383
4a776f0a
HS
384 total_tests++;
385
83544ae9
DW
386 /* honor alignment restrictions */
387 if (thread->type == DMA_MEMCPY)
388 align = dev->copy_align;
389 else if (thread->type == DMA_XOR)
390 align = dev->xor_align;
391 else if (thread->type == DMA_PQ)
392 align = dev->pq_align;
393
e03e93a9 394 if (1 << align > info->buf_size) {
cfe4f275 395 pr_err("%u-byte buffer too small for %d-byte alignment\n",
e03e93a9 396 info->buf_size, 1 << align);
cfe4f275
GL
397 break;
398 }
399
e03e93a9 400 len = dmatest_random() % info->buf_size + 1;
83544ae9 401 len = (len >> align) << align;
cfe4f275
GL
402 if (!len)
403 len = 1 << align;
e03e93a9
AS
404 src_off = dmatest_random() % (info->buf_size - len + 1);
405 dst_off = dmatest_random() % (info->buf_size - len + 1);
cfe4f275 406
83544ae9
DW
407 src_off = (src_off >> align) << align;
408 dst_off = (dst_off >> align) << align;
409
e03e93a9
AS
410 dmatest_init_srcs(thread->srcs, src_off, len, info->buf_size);
411 dmatest_init_dsts(thread->dsts, dst_off, len, info->buf_size);
4a776f0a 412
b54d5cb9
DW
413 for (i = 0; i < src_cnt; i++) {
414 u8 *buf = thread->srcs[i] + src_off;
415
416 dma_srcs[i] = dma_map_single(dev->dev, buf, len,
417 DMA_TO_DEVICE);
afde3be1
AS
418 ret = dma_mapping_error(dev->dev, dma_srcs[i]);
419 if (ret) {
420 unmap_src(dev->dev, dma_srcs, len, i);
421 pr_warn("%s: #%u: mapping error %d with "
422 "src_off=0x%x len=0x%x\n",
423 thread_name, total_tests - 1, ret,
424 src_off, len);
425 failed_tests++;
426 continue;
427 }
b54d5cb9 428 }
d86be86e 429 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
b54d5cb9
DW
430 for (i = 0; i < dst_cnt; i++) {
431 dma_dsts[i] = dma_map_single(dev->dev, thread->dsts[i],
e03e93a9 432 info->buf_size,
b54d5cb9 433 DMA_BIDIRECTIONAL);
afde3be1
AS
434 ret = dma_mapping_error(dev->dev, dma_dsts[i]);
435 if (ret) {
436 unmap_src(dev->dev, dma_srcs, len, src_cnt);
e03e93a9 437 unmap_dst(dev->dev, dma_dsts, info->buf_size, i);
afde3be1
AS
438 pr_warn("%s: #%u: mapping error %d with "
439 "dst_off=0x%x len=0x%x\n",
440 thread_name, total_tests - 1, ret,
e03e93a9 441 dst_off, info->buf_size);
afde3be1
AS
442 failed_tests++;
443 continue;
444 }
b54d5cb9
DW
445 }
446
447 if (thread->type == DMA_MEMCPY)
448 tx = dev->device_prep_dma_memcpy(chan,
449 dma_dsts[0] + dst_off,
450 dma_srcs[0], len,
451 flags);
452 else if (thread->type == DMA_XOR)
453 tx = dev->device_prep_dma_xor(chan,
454 dma_dsts[0] + dst_off,
67b9124f 455 dma_srcs, src_cnt,
b54d5cb9 456 len, flags);
58691d64
DW
457 else if (thread->type == DMA_PQ) {
458 dma_addr_t dma_pq[dst_cnt];
459
460 for (i = 0; i < dst_cnt; i++)
461 dma_pq[i] = dma_dsts[i] + dst_off;
462 tx = dev->device_prep_dma_pq(chan, dma_pq, dma_srcs,
94de648d 463 src_cnt, pq_coefs,
58691d64
DW
464 len, flags);
465 }
d86be86e 466
d86be86e 467 if (!tx) {
632fd283 468 unmap_src(dev->dev, dma_srcs, len, src_cnt);
e03e93a9 469 unmap_dst(dev->dev, dma_dsts, info->buf_size, dst_cnt);
d86be86e
AN
470 pr_warning("%s: #%u: prep error with src_off=0x%x "
471 "dst_off=0x%x len=0x%x\n",
472 thread_name, total_tests - 1,
473 src_off, dst_off, len);
474 msleep(100);
475 failed_tests++;
476 continue;
477 }
e44e0aa3 478
adfa543e 479 done.done = false;
e44e0aa3 480 tx->callback = dmatest_callback;
adfa543e 481 tx->callback_param = &done;
d86be86e
AN
482 cookie = tx->tx_submit(tx);
483
4a776f0a
HS
484 if (dma_submit_error(cookie)) {
485 pr_warning("%s: #%u: submit error %d with src_off=0x%x "
486 "dst_off=0x%x len=0x%x\n",
487 thread_name, total_tests - 1, cookie,
488 src_off, dst_off, len);
489 msleep(100);
490 failed_tests++;
491 continue;
492 }
b54d5cb9 493 dma_async_issue_pending(chan);
4a776f0a 494
77101ce5
AS
495 wait_event_freezable_timeout(done_wait,
496 done.done || kthread_should_stop(),
e03e93a9 497 msecs_to_jiffies(info->timeout));
981ed70d 498
e44e0aa3 499 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
4a776f0a 500
adfa543e
TH
501 if (!done.done) {
502 /*
503 * We're leaving the timed out dma operation with
504 * dangling pointer to done_wait. To make this
505 * correct, we'll need to allocate wait_done for
506 * each test iteration and perform "who's gonna
507 * free it this time?" dancing. For now, just
508 * leave it dangling.
509 */
e44e0aa3
DW
510 pr_warning("%s: #%u: test timed out\n",
511 thread_name, total_tests - 1);
512 failed_tests++;
513 continue;
514 } else if (status != DMA_SUCCESS) {
515 pr_warning("%s: #%u: got completion callback,"
516 " but status is \'%s\'\n",
517 thread_name, total_tests - 1,
518 status == DMA_ERROR ? "error" : "in progress");
4a776f0a
HS
519 failed_tests++;
520 continue;
521 }
e44e0aa3 522
d86be86e 523 /* Unmap by myself (see DMA_COMPL_SKIP_DEST_UNMAP above) */
e03e93a9 524 unmap_dst(dev->dev, dma_dsts, info->buf_size, dst_cnt);
4a776f0a
HS
525
526 error_count = 0;
527
528 pr_debug("%s: verifying source buffer...\n", thread_name);
b54d5cb9 529 error_count += dmatest_verify(thread->srcs, 0, src_off,
4a776f0a 530 0, PATTERN_SRC, true);
b54d5cb9 531 error_count += dmatest_verify(thread->srcs, src_off,
4a776f0a
HS
532 src_off + len, src_off,
533 PATTERN_SRC | PATTERN_COPY, true);
b54d5cb9 534 error_count += dmatest_verify(thread->srcs, src_off + len,
e03e93a9 535 info->buf_size, src_off + len,
4a776f0a
HS
536 PATTERN_SRC, true);
537
538 pr_debug("%s: verifying dest buffer...\n",
539 thread->task->comm);
b54d5cb9 540 error_count += dmatest_verify(thread->dsts, 0, dst_off,
4a776f0a 541 0, PATTERN_DST, false);
b54d5cb9 542 error_count += dmatest_verify(thread->dsts, dst_off,
4a776f0a
HS
543 dst_off + len, src_off,
544 PATTERN_SRC | PATTERN_COPY, false);
b54d5cb9 545 error_count += dmatest_verify(thread->dsts, dst_off + len,
e03e93a9 546 info->buf_size, dst_off + len,
4a776f0a
HS
547 PATTERN_DST, false);
548
549 if (error_count) {
550 pr_warning("%s: #%u: %u errors with "
551 "src_off=0x%x dst_off=0x%x len=0x%x\n",
552 thread_name, total_tests - 1, error_count,
553 src_off, dst_off, len);
554 failed_tests++;
555 } else {
556 pr_debug("%s: #%u: No errors with "
557 "src_off=0x%x dst_off=0x%x len=0x%x\n",
558 thread_name, total_tests - 1,
559 src_off, dst_off, len);
560 }
561 }
562
563 ret = 0;
b54d5cb9
DW
564 for (i = 0; thread->dsts[i]; i++)
565 kfree(thread->dsts[i]);
4a776f0a 566err_dstbuf:
b54d5cb9
DW
567 kfree(thread->dsts);
568err_dsts:
569 for (i = 0; thread->srcs[i]; i++)
570 kfree(thread->srcs[i]);
4a776f0a 571err_srcbuf:
b54d5cb9
DW
572 kfree(thread->srcs);
573err_srcs:
945b5af3
AS
574 kfree(pq_coefs);
575err_thread_type:
4a776f0a
HS
576 pr_notice("%s: terminating after %u tests, %u failures (status %d)\n",
577 thread_name, total_tests, failed_tests, ret);
0a2ff57d 578
9704efaa 579 /* terminate all transfers on specified channels */
5e034f7b
SH
580 if (ret)
581 dmaengine_terminate_all(chan);
582
e03e93a9 583 if (info->iterations > 0)
0a2ff57d 584 while (!kthread_should_stop()) {
b953df7c 585 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wait_dmatest_exit);
0a2ff57d
NF
586 interruptible_sleep_on(&wait_dmatest_exit);
587 }
588
4a776f0a
HS
589 return ret;
590}
591
592static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
593{
594 struct dmatest_thread *thread;
595 struct dmatest_thread *_thread;
596 int ret;
597
598 list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
599 ret = kthread_stop(thread->task);
600 pr_debug("dmatest: thread %s exited with status %d\n",
601 thread->task->comm, ret);
602 list_del(&thread->node);
603 kfree(thread);
604 }
9704efaa
VK
605
606 /* terminate all transfers on specified channels */
944ea4dd 607 dmaengine_terminate_all(dtc->chan);
9704efaa 608
4a776f0a
HS
609 kfree(dtc);
610}
611
e03e93a9
AS
612static int dmatest_add_threads(struct dmatest_info *info,
613 struct dmatest_chan *dtc, enum dma_transaction_type type)
4a776f0a 614{
b54d5cb9
DW
615 struct dmatest_thread *thread;
616 struct dma_chan *chan = dtc->chan;
617 char *op;
618 unsigned int i;
4a776f0a 619
b54d5cb9
DW
620 if (type == DMA_MEMCPY)
621 op = "copy";
622 else if (type == DMA_XOR)
623 op = "xor";
58691d64
DW
624 else if (type == DMA_PQ)
625 op = "pq";
b54d5cb9
DW
626 else
627 return -EINVAL;
4a776f0a 628
e03e93a9 629 for (i = 0; i < info->threads_per_chan; i++) {
4a776f0a
HS
630 thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
631 if (!thread) {
b54d5cb9
DW
632 pr_warning("dmatest: No memory for %s-%s%u\n",
633 dma_chan_name(chan), op, i);
634
4a776f0a
HS
635 break;
636 }
e03e93a9 637 thread->info = info;
4a776f0a 638 thread->chan = dtc->chan;
b54d5cb9 639 thread->type = type;
4a776f0a 640 smp_wmb();
b54d5cb9
DW
641 thread->task = kthread_run(dmatest_func, thread, "%s-%s%u",
642 dma_chan_name(chan), op, i);
4a776f0a 643 if (IS_ERR(thread->task)) {
b54d5cb9
DW
644 pr_warning("dmatest: Failed to run thread %s-%s%u\n",
645 dma_chan_name(chan), op, i);
4a776f0a
HS
646 kfree(thread);
647 break;
648 }
649
650 /* srcbuf and dstbuf are allocated by the thread itself */
651
652 list_add_tail(&thread->node, &dtc->threads);
653 }
654
b54d5cb9
DW
655 return i;
656}
657
e03e93a9
AS
658static int dmatest_add_channel(struct dmatest_info *info,
659 struct dma_chan *chan)
b54d5cb9
DW
660{
661 struct dmatest_chan *dtc;
662 struct dma_device *dma_dev = chan->device;
663 unsigned int thread_count = 0;
b9033e68 664 int cnt;
b54d5cb9
DW
665
666 dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
667 if (!dtc) {
668 pr_warning("dmatest: No memory for %s\n", dma_chan_name(chan));
669 return -ENOMEM;
670 }
671
672 dtc->chan = chan;
673 INIT_LIST_HEAD(&dtc->threads);
674
675 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
e03e93a9 676 cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
f1aef8b6 677 thread_count += cnt > 0 ? cnt : 0;
b54d5cb9
DW
678 }
679 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
e03e93a9 680 cnt = dmatest_add_threads(info, dtc, DMA_XOR);
f1aef8b6 681 thread_count += cnt > 0 ? cnt : 0;
b54d5cb9 682 }
58691d64 683 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
e03e93a9 684 cnt = dmatest_add_threads(info, dtc, DMA_PQ);
d07a74a5 685 thread_count += cnt > 0 ? cnt : 0;
58691d64 686 }
b54d5cb9
DW
687
688 pr_info("dmatest: Started %u threads using %s\n",
689 thread_count, dma_chan_name(chan));
4a776f0a 690
838cc704
AS
691 list_add_tail(&dtc->node, &info->channels);
692 info->nr_channels++;
4a776f0a 693
33df8ca0 694 return 0;
4a776f0a
HS
695}
696
7dd60251 697static bool filter(struct dma_chan *chan, void *param)
4a776f0a 698{
e03e93a9
AS
699 struct dmatest_info *info = param;
700
701 if (!dmatest_match_channel(info, chan) ||
702 !dmatest_match_device(info, chan->device))
7dd60251 703 return false;
33df8ca0 704 else
7dd60251 705 return true;
4a776f0a
HS
706}
707
e03e93a9 708static int run_threaded_test(struct dmatest_info *info)
4a776f0a 709{
33df8ca0
DW
710 dma_cap_mask_t mask;
711 struct dma_chan *chan;
712 int err = 0;
713
714 dma_cap_zero(mask);
715 dma_cap_set(DMA_MEMCPY, mask);
716 for (;;) {
e03e93a9 717 chan = dma_request_channel(mask, filter, info);
33df8ca0 718 if (chan) {
e03e93a9 719 err = dmatest_add_channel(info, chan);
c56c81ab 720 if (err) {
33df8ca0
DW
721 dma_release_channel(chan);
722 break; /* add_channel failed, punt */
723 }
724 } else
725 break; /* no more channels available */
838cc704
AS
726 if (info->max_channels &&
727 info->nr_channels >= info->max_channels)
33df8ca0
DW
728 break; /* we have all we need */
729 }
33df8ca0 730 return err;
4a776f0a 731}
4a776f0a 732
e03e93a9 733static void stop_threaded_test(struct dmatest_info *info)
4a776f0a 734{
33df8ca0 735 struct dmatest_chan *dtc, *_dtc;
7cbd4877 736 struct dma_chan *chan;
33df8ca0 737
838cc704 738 list_for_each_entry_safe(dtc, _dtc, &info->channels, node) {
33df8ca0 739 list_del(&dtc->node);
7cbd4877 740 chan = dtc->chan;
33df8ca0 741 dmatest_cleanup_channel(dtc);
838cc704 742 pr_debug("dmatest: dropped channel %s\n", dma_chan_name(chan));
7cbd4877 743 dma_release_channel(chan);
33df8ca0 744 }
838cc704
AS
745
746 info->nr_channels = 0;
4a776f0a 747}
e03e93a9
AS
748
749static int __init dmatest_init(void)
750{
751 struct dmatest_info *info = &test_info;
752
753 memset(info, 0, sizeof(*info));
754
838cc704
AS
755 INIT_LIST_HEAD(&info->channels);
756
757 /* Set default parameters */
e03e93a9
AS
758 info->buf_size = test_buf_size;
759 strlcpy(info->channel, test_channel, sizeof(info->channel));
760 strlcpy(info->device, test_device, sizeof(info->device));
761 info->threads_per_chan = threads_per_chan;
762 info->max_channels = max_channels;
763 info->iterations = iterations;
764 info->xor_sources = xor_sources;
765 info->pq_sources = pq_sources;
766 info->timeout = timeout;
767
768 return run_threaded_test(info);
769}
770/* when compiled-in wait for drivers to load first */
771late_initcall(dmatest_init);
772
773static void __exit dmatest_exit(void)
774{
775 struct dmatest_info *info = &test_info;
776
777 stop_threaded_test(info);
778}
4a776f0a
HS
779module_exit(dmatest_exit);
780
e05503ef 781MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
4a776f0a 782MODULE_LICENSE("GPL v2");