fsldma: Fix cookie issues
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / dma / dmatest.c
CommitLineData
4a776f0a
HS
1/*
2 * DMA Engine test module
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/delay.h>
11#include <linux/dmaengine.h>
12#include <linux/init.h>
13#include <linux/kthread.h>
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/random.h>
17#include <linux/wait.h>
18
19static unsigned int test_buf_size = 16384;
20module_param(test_buf_size, uint, S_IRUGO);
21MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
22
06190d84 23static char test_channel[20];
4a776f0a
HS
24module_param_string(channel, test_channel, sizeof(test_channel), S_IRUGO);
25MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
26
06190d84 27static char test_device[20];
4a776f0a
HS
28module_param_string(device, test_device, sizeof(test_device), S_IRUGO);
29MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
30
31static unsigned int threads_per_chan = 1;
32module_param(threads_per_chan, uint, S_IRUGO);
33MODULE_PARM_DESC(threads_per_chan,
34 "Number of threads to start per channel (default: 1)");
35
36static unsigned int max_channels;
37module_param(max_channels, uint, S_IRUGO);
33df8ca0 38MODULE_PARM_DESC(max_channels,
4a776f0a
HS
39 "Maximum number of channels to use (default: all)");
40
0a2ff57d
NF
41static unsigned int iterations;
42module_param(iterations, uint, S_IRUGO);
43MODULE_PARM_DESC(iterations,
44 "Iterations before stopping test (default: infinite)");
45
b54d5cb9
DW
46static unsigned int xor_sources = 3;
47module_param(xor_sources, uint, S_IRUGO);
48MODULE_PARM_DESC(xor_sources,
49 "Number of xor source buffers (default: 3)");
50
58691d64
DW
51static unsigned int pq_sources = 3;
52module_param(pq_sources, uint, S_IRUGO);
53MODULE_PARM_DESC(pq_sources,
54 "Number of p+q source buffers (default: 3)");
55
4a776f0a
HS
56/*
57 * Initialization patterns. All bytes in the source buffer has bit 7
58 * set, all bytes in the destination buffer has bit 7 cleared.
59 *
60 * Bit 6 is set for all bytes which are to be copied by the DMA
61 * engine. Bit 5 is set for all bytes which are to be overwritten by
62 * the DMA engine.
63 *
64 * The remaining bits are the inverse of a counter which increments by
65 * one for each byte address.
66 */
67#define PATTERN_SRC 0x80
68#define PATTERN_DST 0x00
69#define PATTERN_COPY 0x40
70#define PATTERN_OVERWRITE 0x20
71#define PATTERN_COUNT_MASK 0x1f
72
73struct dmatest_thread {
74 struct list_head node;
75 struct task_struct *task;
76 struct dma_chan *chan;
b54d5cb9
DW
77 u8 **srcs;
78 u8 **dsts;
79 enum dma_transaction_type type;
4a776f0a
HS
80};
81
82struct dmatest_chan {
83 struct list_head node;
84 struct dma_chan *chan;
85 struct list_head threads;
86};
87
88/*
89 * These are protected by dma_list_mutex since they're only used by
33df8ca0 90 * the DMA filter function callback
4a776f0a
HS
91 */
92static LIST_HEAD(dmatest_channels);
93static unsigned int nr_channels;
94
95static bool dmatest_match_channel(struct dma_chan *chan)
96{
97 if (test_channel[0] == '\0')
98 return true;
41d5e59c 99 return strcmp(dma_chan_name(chan), test_channel) == 0;
4a776f0a
HS
100}
101
102static bool dmatest_match_device(struct dma_device *device)
103{
104 if (test_device[0] == '\0')
105 return true;
06190d84 106 return strcmp(dev_name(device->dev), test_device) == 0;
4a776f0a
HS
107}
108
109static unsigned long dmatest_random(void)
110{
111 unsigned long buf;
112
113 get_random_bytes(&buf, sizeof(buf));
114 return buf;
115}
116
b54d5cb9 117static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len)
4a776f0a
HS
118{
119 unsigned int i;
b54d5cb9
DW
120 u8 *buf;
121
122 for (; (buf = *bufs); bufs++) {
123 for (i = 0; i < start; i++)
124 buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
125 for ( ; i < start + len; i++)
126 buf[i] = PATTERN_SRC | PATTERN_COPY
c019894e 127 | (~i & PATTERN_COUNT_MASK);
b54d5cb9
DW
128 for ( ; i < test_buf_size; i++)
129 buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
130 buf++;
131 }
4a776f0a
HS
132}
133
b54d5cb9 134static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len)
4a776f0a
HS
135{
136 unsigned int i;
b54d5cb9
DW
137 u8 *buf;
138
139 for (; (buf = *bufs); bufs++) {
140 for (i = 0; i < start; i++)
141 buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
142 for ( ; i < start + len; i++)
143 buf[i] = PATTERN_DST | PATTERN_OVERWRITE
144 | (~i & PATTERN_COUNT_MASK);
145 for ( ; i < test_buf_size; i++)
146 buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
147 }
4a776f0a
HS
148}
149
150static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
151 unsigned int counter, bool is_srcbuf)
152{
153 u8 diff = actual ^ pattern;
154 u8 expected = pattern | (~counter & PATTERN_COUNT_MASK);
155 const char *thread_name = current->comm;
156
157 if (is_srcbuf)
158 pr_warning("%s: srcbuf[0x%x] overwritten!"
159 " Expected %02x, got %02x\n",
160 thread_name, index, expected, actual);
161 else if ((pattern & PATTERN_COPY)
162 && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
163 pr_warning("%s: dstbuf[0x%x] not copied!"
164 " Expected %02x, got %02x\n",
165 thread_name, index, expected, actual);
166 else if (diff & PATTERN_SRC)
167 pr_warning("%s: dstbuf[0x%x] was copied!"
168 " Expected %02x, got %02x\n",
169 thread_name, index, expected, actual);
170 else
171 pr_warning("%s: dstbuf[0x%x] mismatch!"
172 " Expected %02x, got %02x\n",
173 thread_name, index, expected, actual);
174}
175
b54d5cb9 176static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
4a776f0a
HS
177 unsigned int end, unsigned int counter, u8 pattern,
178 bool is_srcbuf)
179{
180 unsigned int i;
181 unsigned int error_count = 0;
182 u8 actual;
b54d5cb9
DW
183 u8 expected;
184 u8 *buf;
185 unsigned int counter_orig = counter;
186
187 for (; (buf = *bufs); bufs++) {
188 counter = counter_orig;
189 for (i = start; i < end; i++) {
190 actual = buf[i];
191 expected = pattern | (~counter & PATTERN_COUNT_MASK);
192 if (actual != expected) {
193 if (error_count < 32)
194 dmatest_mismatch(actual, pattern, i,
195 counter, is_srcbuf);
196 error_count++;
197 }
198 counter++;
4a776f0a 199 }
4a776f0a
HS
200 }
201
202 if (error_count > 32)
203 pr_warning("%s: %u errors suppressed\n",
204 current->comm, error_count - 32);
205
206 return error_count;
207}
208
e44e0aa3
DW
209static void dmatest_callback(void *completion)
210{
211 complete(completion);
212}
213
4a776f0a
HS
214/*
215 * This function repeatedly tests DMA transfers of various lengths and
b54d5cb9
DW
216 * offsets for a given operation type until it is told to exit by
217 * kthread_stop(). There may be multiple threads running this function
218 * in parallel for a single channel, and there may be multiple channels
219 * being tested in parallel.
4a776f0a
HS
220 *
221 * Before each test, the source and destination buffer is initialized
222 * with a known pattern. This pattern is different depending on
223 * whether it's in an area which is supposed to be copied or
224 * overwritten, and different in the source and destination buffers.
225 * So if the DMA engine doesn't copy exactly what we tell it to copy,
226 * we'll notice.
227 */
228static int dmatest_func(void *data)
229{
230 struct dmatest_thread *thread = data;
231 struct dma_chan *chan;
232 const char *thread_name;
233 unsigned int src_off, dst_off, len;
234 unsigned int error_count;
235 unsigned int failed_tests = 0;
236 unsigned int total_tests = 0;
237 dma_cookie_t cookie;
238 enum dma_status status;
b54d5cb9 239 enum dma_ctrl_flags flags;
58691d64 240 u8 pq_coefs[pq_sources];
4a776f0a 241 int ret;
b54d5cb9
DW
242 int src_cnt;
243 int dst_cnt;
244 int i;
4a776f0a
HS
245
246 thread_name = current->comm;
247
248 ret = -ENOMEM;
4a776f0a
HS
249
250 smp_rmb();
251 chan = thread->chan;
b54d5cb9
DW
252 if (thread->type == DMA_MEMCPY)
253 src_cnt = dst_cnt = 1;
254 else if (thread->type == DMA_XOR) {
255 src_cnt = xor_sources | 1; /* force odd to ensure dst = src */
256 dst_cnt = 1;
58691d64
DW
257 } else if (thread->type == DMA_PQ) {
258 src_cnt = pq_sources | 1; /* force odd to ensure dst = src */
259 dst_cnt = 2;
260 for (i = 0; i < pq_sources; i++)
261 pq_coefs[i] = 1;
b54d5cb9
DW
262 } else
263 goto err_srcs;
264
265 thread->srcs = kcalloc(src_cnt+1, sizeof(u8 *), GFP_KERNEL);
266 if (!thread->srcs)
267 goto err_srcs;
268 for (i = 0; i < src_cnt; i++) {
269 thread->srcs[i] = kmalloc(test_buf_size, GFP_KERNEL);
270 if (!thread->srcs[i])
271 goto err_srcbuf;
272 }
273 thread->srcs[i] = NULL;
274
275 thread->dsts = kcalloc(dst_cnt+1, sizeof(u8 *), GFP_KERNEL);
276 if (!thread->dsts)
277 goto err_dsts;
278 for (i = 0; i < dst_cnt; i++) {
279 thread->dsts[i] = kmalloc(test_buf_size, GFP_KERNEL);
280 if (!thread->dsts[i])
281 goto err_dstbuf;
282 }
283 thread->dsts[i] = NULL;
284
e44e0aa3
DW
285 set_user_nice(current, 10);
286
287 flags = DMA_CTRL_ACK | DMA_COMPL_SKIP_DEST_UNMAP | DMA_PREP_INTERRUPT;
4a776f0a 288
0a2ff57d
NF
289 while (!kthread_should_stop()
290 && !(iterations && total_tests >= iterations)) {
d86be86e 291 struct dma_device *dev = chan->device;
b54d5cb9
DW
292 struct dma_async_tx_descriptor *tx = NULL;
293 dma_addr_t dma_srcs[src_cnt];
294 dma_addr_t dma_dsts[dst_cnt];
e44e0aa3
DW
295 struct completion cmp;
296 unsigned long tmo = msecs_to_jiffies(3000);
83544ae9 297 u8 align = 0;
d86be86e 298
4a776f0a
HS
299 total_tests++;
300
83544ae9
DW
301 /* honor alignment restrictions */
302 if (thread->type == DMA_MEMCPY)
303 align = dev->copy_align;
304 else if (thread->type == DMA_XOR)
305 align = dev->xor_align;
306 else if (thread->type == DMA_PQ)
307 align = dev->pq_align;
308
cfe4f275
GL
309 if (1 << align > test_buf_size) {
310 pr_err("%u-byte buffer too small for %d-byte alignment\n",
311 test_buf_size, 1 << align);
312 break;
313 }
314
315 len = dmatest_random() % test_buf_size + 1;
83544ae9 316 len = (len >> align) << align;
cfe4f275
GL
317 if (!len)
318 len = 1 << align;
319 src_off = dmatest_random() % (test_buf_size - len + 1);
320 dst_off = dmatest_random() % (test_buf_size - len + 1);
321
83544ae9
DW
322 src_off = (src_off >> align) << align;
323 dst_off = (dst_off >> align) << align;
324
b54d5cb9
DW
325 dmatest_init_srcs(thread->srcs, src_off, len);
326 dmatest_init_dsts(thread->dsts, dst_off, len);
4a776f0a 327
b54d5cb9
DW
328 for (i = 0; i < src_cnt; i++) {
329 u8 *buf = thread->srcs[i] + src_off;
330
331 dma_srcs[i] = dma_map_single(dev->dev, buf, len,
332 DMA_TO_DEVICE);
333 }
d86be86e 334 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
b54d5cb9
DW
335 for (i = 0; i < dst_cnt; i++) {
336 dma_dsts[i] = dma_map_single(dev->dev, thread->dsts[i],
337 test_buf_size,
338 DMA_BIDIRECTIONAL);
339 }
340
83544ae9 341
b54d5cb9
DW
342 if (thread->type == DMA_MEMCPY)
343 tx = dev->device_prep_dma_memcpy(chan,
344 dma_dsts[0] + dst_off,
345 dma_srcs[0], len,
346 flags);
347 else if (thread->type == DMA_XOR)
348 tx = dev->device_prep_dma_xor(chan,
349 dma_dsts[0] + dst_off,
350 dma_srcs, xor_sources,
351 len, flags);
58691d64
DW
352 else if (thread->type == DMA_PQ) {
353 dma_addr_t dma_pq[dst_cnt];
354
355 for (i = 0; i < dst_cnt; i++)
356 dma_pq[i] = dma_dsts[i] + dst_off;
357 tx = dev->device_prep_dma_pq(chan, dma_pq, dma_srcs,
358 pq_sources, pq_coefs,
359 len, flags);
360 }
d86be86e 361
d86be86e 362 if (!tx) {
b54d5cb9
DW
363 for (i = 0; i < src_cnt; i++)
364 dma_unmap_single(dev->dev, dma_srcs[i], len,
365 DMA_TO_DEVICE);
366 for (i = 0; i < dst_cnt; i++)
367 dma_unmap_single(dev->dev, dma_dsts[i],
368 test_buf_size,
369 DMA_BIDIRECTIONAL);
d86be86e
AN
370 pr_warning("%s: #%u: prep error with src_off=0x%x "
371 "dst_off=0x%x len=0x%x\n",
372 thread_name, total_tests - 1,
373 src_off, dst_off, len);
374 msleep(100);
375 failed_tests++;
376 continue;
377 }
e44e0aa3
DW
378
379 init_completion(&cmp);
380 tx->callback = dmatest_callback;
381 tx->callback_param = &cmp;
d86be86e
AN
382 cookie = tx->tx_submit(tx);
383
4a776f0a
HS
384 if (dma_submit_error(cookie)) {
385 pr_warning("%s: #%u: submit error %d with src_off=0x%x "
386 "dst_off=0x%x len=0x%x\n",
387 thread_name, total_tests - 1, cookie,
388 src_off, dst_off, len);
389 msleep(100);
390 failed_tests++;
391 continue;
392 }
b54d5cb9 393 dma_async_issue_pending(chan);
4a776f0a 394
e44e0aa3
DW
395 tmo = wait_for_completion_timeout(&cmp, tmo);
396 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
4a776f0a 397
e44e0aa3
DW
398 if (tmo == 0) {
399 pr_warning("%s: #%u: test timed out\n",
400 thread_name, total_tests - 1);
401 failed_tests++;
402 continue;
403 } else if (status != DMA_SUCCESS) {
404 pr_warning("%s: #%u: got completion callback,"
405 " but status is \'%s\'\n",
406 thread_name, total_tests - 1,
407 status == DMA_ERROR ? "error" : "in progress");
4a776f0a
HS
408 failed_tests++;
409 continue;
410 }
e44e0aa3 411
d86be86e 412 /* Unmap by myself (see DMA_COMPL_SKIP_DEST_UNMAP above) */
b54d5cb9
DW
413 for (i = 0; i < dst_cnt; i++)
414 dma_unmap_single(dev->dev, dma_dsts[i], test_buf_size,
415 DMA_BIDIRECTIONAL);
4a776f0a
HS
416
417 error_count = 0;
418
419 pr_debug("%s: verifying source buffer...\n", thread_name);
b54d5cb9 420 error_count += dmatest_verify(thread->srcs, 0, src_off,
4a776f0a 421 0, PATTERN_SRC, true);
b54d5cb9 422 error_count += dmatest_verify(thread->srcs, src_off,
4a776f0a
HS
423 src_off + len, src_off,
424 PATTERN_SRC | PATTERN_COPY, true);
b54d5cb9 425 error_count += dmatest_verify(thread->srcs, src_off + len,
4a776f0a
HS
426 test_buf_size, src_off + len,
427 PATTERN_SRC, true);
428
429 pr_debug("%s: verifying dest buffer...\n",
430 thread->task->comm);
b54d5cb9 431 error_count += dmatest_verify(thread->dsts, 0, dst_off,
4a776f0a 432 0, PATTERN_DST, false);
b54d5cb9 433 error_count += dmatest_verify(thread->dsts, dst_off,
4a776f0a
HS
434 dst_off + len, src_off,
435 PATTERN_SRC | PATTERN_COPY, false);
b54d5cb9 436 error_count += dmatest_verify(thread->dsts, dst_off + len,
4a776f0a
HS
437 test_buf_size, dst_off + len,
438 PATTERN_DST, false);
439
440 if (error_count) {
441 pr_warning("%s: #%u: %u errors with "
442 "src_off=0x%x dst_off=0x%x len=0x%x\n",
443 thread_name, total_tests - 1, error_count,
444 src_off, dst_off, len);
445 failed_tests++;
446 } else {
447 pr_debug("%s: #%u: No errors with "
448 "src_off=0x%x dst_off=0x%x len=0x%x\n",
449 thread_name, total_tests - 1,
450 src_off, dst_off, len);
451 }
452 }
453
454 ret = 0;
b54d5cb9
DW
455 for (i = 0; thread->dsts[i]; i++)
456 kfree(thread->dsts[i]);
4a776f0a 457err_dstbuf:
b54d5cb9
DW
458 kfree(thread->dsts);
459err_dsts:
460 for (i = 0; thread->srcs[i]; i++)
461 kfree(thread->srcs[i]);
4a776f0a 462err_srcbuf:
b54d5cb9
DW
463 kfree(thread->srcs);
464err_srcs:
4a776f0a
HS
465 pr_notice("%s: terminating after %u tests, %u failures (status %d)\n",
466 thread_name, total_tests, failed_tests, ret);
0a2ff57d
NF
467
468 if (iterations > 0)
469 while (!kthread_should_stop()) {
470 DECLARE_WAIT_QUEUE_HEAD(wait_dmatest_exit);
471 interruptible_sleep_on(&wait_dmatest_exit);
472 }
473
4a776f0a
HS
474 return ret;
475}
476
477static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
478{
479 struct dmatest_thread *thread;
480 struct dmatest_thread *_thread;
481 int ret;
482
483 list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
484 ret = kthread_stop(thread->task);
485 pr_debug("dmatest: thread %s exited with status %d\n",
486 thread->task->comm, ret);
487 list_del(&thread->node);
488 kfree(thread);
489 }
490 kfree(dtc);
491}
492
b54d5cb9 493static int dmatest_add_threads(struct dmatest_chan *dtc, enum dma_transaction_type type)
4a776f0a 494{
b54d5cb9
DW
495 struct dmatest_thread *thread;
496 struct dma_chan *chan = dtc->chan;
497 char *op;
498 unsigned int i;
4a776f0a 499
b54d5cb9
DW
500 if (type == DMA_MEMCPY)
501 op = "copy";
502 else if (type == DMA_XOR)
503 op = "xor";
58691d64
DW
504 else if (type == DMA_PQ)
505 op = "pq";
b54d5cb9
DW
506 else
507 return -EINVAL;
4a776f0a
HS
508
509 for (i = 0; i < threads_per_chan; i++) {
510 thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
511 if (!thread) {
b54d5cb9
DW
512 pr_warning("dmatest: No memory for %s-%s%u\n",
513 dma_chan_name(chan), op, i);
514
4a776f0a
HS
515 break;
516 }
517 thread->chan = dtc->chan;
b54d5cb9 518 thread->type = type;
4a776f0a 519 smp_wmb();
b54d5cb9
DW
520 thread->task = kthread_run(dmatest_func, thread, "%s-%s%u",
521 dma_chan_name(chan), op, i);
4a776f0a 522 if (IS_ERR(thread->task)) {
b54d5cb9
DW
523 pr_warning("dmatest: Failed to run thread %s-%s%u\n",
524 dma_chan_name(chan), op, i);
4a776f0a
HS
525 kfree(thread);
526 break;
527 }
528
529 /* srcbuf and dstbuf are allocated by the thread itself */
530
531 list_add_tail(&thread->node, &dtc->threads);
532 }
533
b54d5cb9
DW
534 return i;
535}
536
537static int dmatest_add_channel(struct dma_chan *chan)
538{
539 struct dmatest_chan *dtc;
540 struct dma_device *dma_dev = chan->device;
541 unsigned int thread_count = 0;
542 unsigned int cnt;
543
544 dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
545 if (!dtc) {
546 pr_warning("dmatest: No memory for %s\n", dma_chan_name(chan));
547 return -ENOMEM;
548 }
549
550 dtc->chan = chan;
551 INIT_LIST_HEAD(&dtc->threads);
552
553 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
554 cnt = dmatest_add_threads(dtc, DMA_MEMCPY);
f1aef8b6 555 thread_count += cnt > 0 ? cnt : 0;
b54d5cb9
DW
556 }
557 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
558 cnt = dmatest_add_threads(dtc, DMA_XOR);
f1aef8b6 559 thread_count += cnt > 0 ? cnt : 0;
b54d5cb9 560 }
58691d64
DW
561 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
562 cnt = dmatest_add_threads(dtc, DMA_PQ);
563 thread_count += cnt > 0 ?: 0;
564 }
b54d5cb9
DW
565
566 pr_info("dmatest: Started %u threads using %s\n",
567 thread_count, dma_chan_name(chan));
4a776f0a
HS
568
569 list_add_tail(&dtc->node, &dmatest_channels);
570 nr_channels++;
571
33df8ca0 572 return 0;
4a776f0a
HS
573}
574
7dd60251 575static bool filter(struct dma_chan *chan, void *param)
4a776f0a 576{
33df8ca0 577 if (!dmatest_match_channel(chan) || !dmatest_match_device(chan->device))
7dd60251 578 return false;
33df8ca0 579 else
7dd60251 580 return true;
4a776f0a
HS
581}
582
4a776f0a
HS
583static int __init dmatest_init(void)
584{
33df8ca0
DW
585 dma_cap_mask_t mask;
586 struct dma_chan *chan;
587 int err = 0;
588
589 dma_cap_zero(mask);
590 dma_cap_set(DMA_MEMCPY, mask);
591 for (;;) {
592 chan = dma_request_channel(mask, filter, NULL);
593 if (chan) {
594 err = dmatest_add_channel(chan);
c56c81ab 595 if (err) {
33df8ca0
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596 dma_release_channel(chan);
597 break; /* add_channel failed, punt */
598 }
599 } else
600 break; /* no more channels available */
601 if (max_channels && nr_channels >= max_channels)
602 break; /* we have all we need */
603 }
4a776f0a 604
33df8ca0 605 return err;
4a776f0a 606}
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607/* when compiled-in wait for drivers to load first */
608late_initcall(dmatest_init);
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609
610static void __exit dmatest_exit(void)
611{
33df8ca0 612 struct dmatest_chan *dtc, *_dtc;
7cbd4877 613 struct dma_chan *chan;
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614
615 list_for_each_entry_safe(dtc, _dtc, &dmatest_channels, node) {
616 list_del(&dtc->node);
7cbd4877 617 chan = dtc->chan;
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618 dmatest_cleanup_channel(dtc);
619 pr_debug("dmatest: dropped channel %s\n",
7cbd4877
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620 dma_chan_name(chan));
621 dma_release_channel(chan);
33df8ca0 622 }
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623}
624module_exit(dmatest_exit);
625
626MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
627MODULE_LICENSE("GPL v2");