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scsi: zfcp: fix payload with full FCP_RSP IU in SCSI trace records
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
40f21b11 4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
8b260248 5 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 6 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7 7 *
40f21b11
ML		 8 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
10 *
20f733e7
BR		 11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
4a05e209 28/*
85afb934
ML		 29 * sata_mv TODO list:
30 *
85afb934
ML		 31 * --> Develop a low-power-consumption strategy, and implement it.
32 *
2b748a0a 33 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
85afb934
ML		 34 *
35 * --> [Experiment, Marvell value added] Is it possible to use target
36 * mode to cross-connect two Linux boxes with Marvell cards? If so,
37 * creating LibATA target mode support would be very interesting.
38 *
39 * Target mode, for those without docs, is the ability to directly
40 * connect two SATA ports.
41 */
4a05e209 42
65ad7fef
ML		 43/*
44 * 80x1-B2 errata PCI#11:
45 *
46 * Users of the 6041/6081 Rev.B2 chips (current is C0)
47 * should be careful to insert those cards only onto PCI-X bus #0,
48 * and only in device slots 0..7, not higher. The chips may not
49 * work correctly otherwise (note: this is a pretty rare condition).
50 */
51
20f733e7
BR		 52#include <linux/kernel.h>
53#include <linux/module.h>
54#include <linux/pci.h>
55#include <linux/init.h>
56#include <linux/blkdev.h>
57#include <linux/delay.h>
58#include <linux/interrupt.h>
8d8b6004 59#include <linux/dmapool.h>
20f733e7 60#include <linux/dma-mapping.h>
a9524a76 61#include <linux/device.h>
c77a2f4e 62#include <linux/clk.h>
f351b2d6
SB		 63#include <linux/platform_device.h>
64#include <linux/ata_platform.h>
15a32632 65#include <linux/mbus.h>
c46938cc 66#include <linux/bitops.h>
5a0e3ad6 67#include <linux/gfp.h>
97b414e1
AL		 68#include <linux/of.h>
69#include <linux/of_irq.h>
20f733e7 70#include <scsi/scsi_host.h>
193515d5 71#include <scsi/scsi_cmnd.h>
6c08772e 72#include <scsi/scsi_device.h>
20f733e7 73#include <linux/libata.h>
20f733e7
BR		 74
75#define DRV_NAME "sata_mv"
cae5a29d 76#define DRV_VERSION "1.28"
20f733e7 77
40f21b11
ML		 78/*
79 * module options
80 */
81
40f21b11 82#ifdef CONFIG_PCI
13b74085 83static int msi;
40f21b11
ML		 84module_param(msi, int, S_IRUGO);
85MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
86#endif
87
2b748a0a
ML		 88static int irq_coalescing_io_count;
89module_param(irq_coalescing_io_count, int, S_IRUGO);
90MODULE_PARM_DESC(irq_coalescing_io_count,
91 "IRQ coalescing I/O count threshold (0..255)");
92
93static int irq_coalescing_usecs;
94module_param(irq_coalescing_usecs, int, S_IRUGO);
95MODULE_PARM_DESC(irq_coalescing_usecs,
96 "IRQ coalescing time threshold in usecs");
97
20f733e7
BR		 98enum {
99 /* BAR's are enumerated in terms of pci_resource_start() terms */
100 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
101 MV_IO_BAR = 2, /* offset 0x18: IO space */
102 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
103
104 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
105 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
106
2b748a0a
ML		 107 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
108 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
109 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
110 MAX_COAL_IO_COUNT = 255, /* completed I/O count */
111
20f733e7 112 MV_PCI_REG_BASE = 0,
615ab953 113
2b748a0a
ML		 114 /*
115 * Per-chip ("all ports") interrupt coalescing feature.
116 * This is only for GEN_II / GEN_IIE hardware.
117 *
118 * Coalescing defers the interrupt until either the IO_THRESHOLD
119 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
120 */
cae5a29d
ML		 121 COAL_REG_BASE = 0x18000,
122 IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
2b748a0a
ML		 123 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
124
cae5a29d
ML		 125 IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
126 IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
2b748a0a
ML		 127
128 /*
129 * Registers for the (unused here) transaction coalescing feature:
130 */
cae5a29d
ML		 131 TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
132 TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
2b748a0a 133
cae5a29d
ML		 134 SATAHC0_REG_BASE = 0x20000,
135 FLASH_CTL = 0x1046c,
136 GPIO_PORT_CTL = 0x104f0,
137 RESET_CFG = 0x180d8,
20f733e7
BR		 138
139 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
140 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
141 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
142 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
143
31961943
BR		 144 MV_MAX_Q_DEPTH = 32,
145 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
146
147 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
148 * CRPB needs alignment on a 256B boundary. Size == 256B
31961943
BR		 149 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
150 */
151 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
152 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
da2fa9ba 153 MV_MAX_SG_CT = 256,
31961943 154 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
31961943 155
352fab70 156 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
20f733e7 157 MV_PORT_HC_SHIFT = 2,
352fab70
ML		 158 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
159 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
160 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
20f733e7
BR		 161
162 /* Host Flags */
163 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
7bb3c529 164
9cbe056f 165 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING,
ad3aef51 166
91b1a84c 167 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
20f733e7 168
40f21b11
ML		 169 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
170 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
91b1a84c
ML		 171
172 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
ad3aef51 173
31961943
BR		 174 CRQB_FLAG_READ = (1 << 0),
175 CRQB_TAG_SHIFT = 1,
c5d3e45a 176 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
e12bef50 177 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
c5d3e45a 178 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 179 CRQB_CMD_ADDR_SHIFT = 8,
180 CRQB_CMD_CS = (0x2 << 11),
181 CRQB_CMD_LAST = (1 << 15),
182
183 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 184 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
185 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 186
187 EPRD_FLAG_END_OF_TBL = (1 << 31),
188
20f733e7
BR		 189 /* PCI interface registers */
190
cae5a29d
ML		 191 MV_PCI_COMMAND = 0xc00,
192 MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
193 MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
31961943 194
cae5a29d 195 PCI_MAIN_CMD_STS = 0xd30,
20f733e7
BR		 196 STOP_PCI_MASTER = (1 << 2),
197 PCI_MASTER_EMPTY = (1 << 3),
198 GLOB_SFT_RST = (1 << 4),
199
cae5a29d 200 MV_PCI_MODE = 0xd00,
8e7decdb
ML		 201 MV_PCI_MODE_MASK = 0x30,
202
522479fb
JG		 203 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
204 MV_PCI_DISC_TIMER = 0xd04,
205 MV_PCI_MSI_TRIGGER = 0xc38,
206 MV_PCI_SERR_MASK = 0xc28,
cae5a29d 207 MV_PCI_XBAR_TMOUT = 0x1d04,
522479fb
JG		 208 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
209 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
210 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
211 MV_PCI_ERR_COMMAND = 0x1d50,
212
cae5a29d
ML		 213 PCI_IRQ_CAUSE = 0x1d58,
214 PCI_IRQ_MASK = 0x1d5c,
20f733e7
BR		 215 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
216
cae5a29d
ML		 217 PCIE_IRQ_CAUSE = 0x1900,
218 PCIE_IRQ_MASK = 0x1910,
646a4da5 219 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 220
7368f919 221 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
cae5a29d
ML		 222 PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
223 PCI_HC_MAIN_IRQ_MASK = 0x1d64,
224 SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
225 SOC_HC_MAIN_IRQ_MASK = 0x20024,
40f21b11
ML		 226 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
227 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
20f733e7
BR		 228 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
229 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
2b748a0a
ML		 230 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
231 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
20f733e7 232 PCI_ERR = (1 << 18),
40f21b11
ML		 233 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
234 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
235 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
236 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
237 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
20f733e7
BR		 238 GPIO_INT = (1 << 22),
239 SELF_INT = (1 << 23),
240 TWSI_INT = (1 << 24),
241 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 242 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
e12bef50 243 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
20f733e7
BR		 244
245 /* SATAHC registers */
cae5a29d 246 HC_CFG = 0x00,
20f733e7 247
cae5a29d 248 HC_IRQ_CAUSE = 0x14,
352fab70
ML		 249 DMA_IRQ = (1 << 0), /* shift by port # */
250 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
20f733e7
BR		 251 DEV_IRQ = (1 << 8), /* shift by port # */
252
2b748a0a
ML		 253 /*
254 * Per-HC (Host-Controller) interrupt coalescing feature.
255 * This is present on all chip generations.
256 *
257 * Coalescing defers the interrupt until either the IO_THRESHOLD
258 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
259 */
cae5a29d
ML		 260 HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
261 HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
2b748a0a 262
cae5a29d 263 SOC_LED_CTRL = 0x2c,
000b344f
ML		 264 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
265 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
266 /* with dev activity LED */
267
20f733e7 268 /* Shadow block registers */
cae5a29d
ML		 269 SHD_BLK = 0x100,
270 SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */
20f733e7
BR		 271
272 /* SATA registers */
cae5a29d
ML		 273 SATA_STATUS = 0x300, /* ctrl, err regs follow status */
274 SATA_ACTIVE = 0x350,
275 FIS_IRQ_CAUSE = 0x364,
276 FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */
17c5aab5 277
cae5a29d 278 LTMODE = 0x30c, /* requires read-after-write */
17c5aab5
ML		 279 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
280
cae5a29d 281 PHY_MODE2 = 0x330,
47c2b677 282 PHY_MODE3 = 0x310,
cae5a29d
ML		 283
284 PHY_MODE4 = 0x314, /* requires read-after-write */
ba069e37
ML		 285 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
286 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
287 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
288 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
289
cae5a29d
ML		 290 SATA_IFCTL = 0x344,
291 SATA_TESTCTL = 0x348,
292 SATA_IFSTAT = 0x34c,
293 VENDOR_UNIQUE_FIS = 0x35c,
17c5aab5 294
cae5a29d 295 FISCFG = 0x360,
8e7decdb
ML		 296 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
297 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
17c5aab5 298
29b7e43c
MM		 299 PHY_MODE9_GEN2 = 0x398,
300 PHY_MODE9_GEN1 = 0x39c,
301 PHYCFG_OFS = 0x3a0, /* only in 65n devices */
302
c9d39130 303 MV5_PHY_MODE = 0x74,
cae5a29d
ML		 304 MV5_LTMODE = 0x30,
305 MV5_PHY_CTL = 0x0C,
306 SATA_IFCFG = 0x050,
6314611a 307 LP_PHY_CTL = 0x058,
bca1c4eb
JG		 308
309 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 310
311 /* Port registers */
cae5a29d 312 EDMA_CFG = 0,
0c58912e
ML		 313 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
314 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
315 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
316 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
317 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
e12bef50
ML		 318 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
319 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
20f733e7 320
cae5a29d
ML		 321 EDMA_ERR_IRQ_CAUSE = 0x8,
322 EDMA_ERR_IRQ_MASK = 0xc,
6c1153e0
JG		 323 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
324 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
325 EDMA_ERR_DEV = (1 << 2), /* device error */
326 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
327 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
328 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 329 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
330 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 331 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 332 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 333 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
334 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
335 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
336 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 337
6c1153e0 338 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 339 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
340 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
341 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
342 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
343
6c1153e0 344 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 345
6c1153e0 346 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 347 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
348 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
349 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
350 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
351 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
352
6c1153e0 353 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 354
6c1153e0 355 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 356 EDMA_ERR_OVERRUN_5 = (1 << 5),
357 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 358
359 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
360 EDMA_ERR_LNK_CTRL_RX_1 |
361 EDMA_ERR_LNK_CTRL_RX_3 |
85afb934 362 EDMA_ERR_LNK_CTRL_TX,
646a4da5 363
bdd4ddde
JG		 364 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
365 EDMA_ERR_PRD_PAR |
366 EDMA_ERR_DEV_DCON |
367 EDMA_ERR_DEV_CON |
368 EDMA_ERR_SERR |
369 EDMA_ERR_SELF_DIS |
6c1153e0 370 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 371 EDMA_ERR_CRPB_PAR |
372 EDMA_ERR_INTRL_PAR |
373 EDMA_ERR_IORDY |
374 EDMA_ERR_LNK_CTRL_RX_2 |
375 EDMA_ERR_LNK_DATA_RX |
376 EDMA_ERR_LNK_DATA_TX |
377 EDMA_ERR_TRANS_PROTO,
e12bef50 378
bdd4ddde
JG		 379 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
380 EDMA_ERR_PRD_PAR |
381 EDMA_ERR_DEV_DCON |
382 EDMA_ERR_DEV_CON |
383 EDMA_ERR_OVERRUN_5 |
384 EDMA_ERR_UNDERRUN_5 |
385 EDMA_ERR_SELF_DIS_5 |
6c1153e0 386 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 387 EDMA_ERR_CRPB_PAR |
388 EDMA_ERR_INTRL_PAR |
389 EDMA_ERR_IORDY,
20f733e7 390
cae5a29d
ML		 391 EDMA_REQ_Q_BASE_HI = 0x10,
392 EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */
31961943 393
cae5a29d 394 EDMA_REQ_Q_OUT_PTR = 0x18,
31961943
BR		 395 EDMA_REQ_Q_PTR_SHIFT = 5,
396
cae5a29d
ML		 397 EDMA_RSP_Q_BASE_HI = 0x1c,
398 EDMA_RSP_Q_IN_PTR = 0x20,
399 EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */
31961943
BR		 400 EDMA_RSP_Q_PTR_SHIFT = 3,
401
cae5a29d 402 EDMA_CMD = 0x28, /* EDMA command register */
0ea9e179
JG		 403 EDMA_EN = (1 << 0), /* enable EDMA */
404 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
8e7decdb
ML		 405 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
406
cae5a29d 407 EDMA_STATUS = 0x30, /* EDMA engine status */
8e7decdb
ML		 408 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
409 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
20f733e7 410
cae5a29d
ML		 411 EDMA_IORDY_TMOUT = 0x34,
412 EDMA_ARB_CFG = 0x38,
8e7decdb 413
cae5a29d
ML		 414 EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */
415 EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */
da14265e 416
cae5a29d
ML		 417 BMDMA_CMD = 0x224, /* bmdma command register */
418 BMDMA_STATUS = 0x228, /* bmdma status register */
419 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
420 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
da14265e 421
31961943
BR		 422 /* Host private flags (hp_flags) */
423 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 424 MV_HP_ERRATA_50XXB0 = (1 << 1),
425 MV_HP_ERRATA_50XXB2 = (1 << 2),
426 MV_HP_ERRATA_60X1B2 = (1 << 3),
427 MV_HP_ERRATA_60X1C0 = (1 << 4),
0ea9e179
JG		 428 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
429 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
430 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 431 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
616d4a98 432 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
1f398472 433 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
000b344f 434 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
6314611a 435 MV_HP_FIX_LP_PHY_CTL = (1 << 13), /* fix speed in LP_PHY_CTL ? */
20f733e7 436
31961943 437 /* Port private flags (pp_flags) */
0ea9e179 438 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 439 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
00f42eab 440 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
29d187bb 441 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
d16ab3f6 442 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
20f733e7
BR		 443};
444
ee9ccdf7
JG		 445#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
446#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 447#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
8e7decdb 448#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
1f398472 449#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
bca1c4eb 450
15a32632
LB		 451#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
452#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
453
095fec88 454enum {
baf14aa1
JG		 455 /* DMA boundary 0xffff is required by the s/g splitting
456 * we need on /length/ in mv_fill-sg().
457 */
458 MV_DMA_BOUNDARY = 0xffffU,
095fec88 459
0ea9e179
JG		 460 /* mask of register bits containing lower 32 bits
461 * of EDMA request queue DMA address
462 */
095fec88
JG		 463 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
464
0ea9e179 465 /* ditto, for response queue */
095fec88
JG		 466 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
467};
468
522479fb
JG		 469enum chip_type {
470 chip_504x,
471 chip_508x,
472 chip_5080,
473 chip_604x,
474 chip_608x,
e4e7b892
JG		 475 chip_6042,
476 chip_7042,
f351b2d6 477 chip_soc,
522479fb
JG		 478};
479
31961943
BR		 480/* Command ReQuest Block: 32B */
481struct mv_crqb {
e1469874
ML		 482 __le32 sg_addr;
483 __le32 sg_addr_hi;
484 __le16 ctrl_flags;
485 __le16 ata_cmd[11];
31961943 486};
20f733e7 487
e4e7b892 488struct mv_crqb_iie {
e1469874
ML		 489 __le32 addr;
490 __le32 addr_hi;
491 __le32 flags;
492 __le32 len;
493 __le32 ata_cmd[4];
e4e7b892
JG		 494};
495
31961943
BR		 496/* Command ResPonse Block: 8B */
497struct mv_crpb {
e1469874
ML		 498 __le16 id;
499 __le16 flags;
500 __le32 tmstmp;
20f733e7
BR		 501};
502
31961943
BR		 503/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
504struct mv_sg {
e1469874
ML		 505 __le32 addr;
506 __le32 flags_size;
507 __le32 addr_hi;
508 __le32 reserved;
31961943 509};
20f733e7 510
08da1759
ML		 511/*
512 * We keep a local cache of a few frequently accessed port
513 * registers here, to avoid having to read them (very slow)
514 * when switching between EDMA and non-EDMA modes.
515 */
516struct mv_cached_regs {
517 u32 fiscfg;
518 u32 ltmode;
519 u32 haltcond;
c01e8a23 520 u32 unknown_rsvd;
08da1759
ML		 521};
522
31961943
BR		 523struct mv_port_priv {
524 struct mv_crqb *crqb;
525 dma_addr_t crqb_dma;
526 struct mv_crpb *crpb;
527 dma_addr_t crpb_dma;
eb73d558
ML		 528 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
529 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
bdd4ddde
JG		 530
531 unsigned int req_idx;
532 unsigned int resp_idx;
533
31961943 534 u32 pp_flags;
08da1759 535 struct mv_cached_regs cached;
29d187bb 536 unsigned int delayed_eh_pmp_map;
31961943
BR		 537};
538
bca1c4eb
JG		 539struct mv_port_signal {
540 u32 amps;
541 u32 pre;
542};
543
02a121da
ML		 544struct mv_host_priv {
545 u32 hp_flags;
1bfeff03 546 unsigned int board_idx;
96e2c487 547 u32 main_irq_mask;
02a121da
ML		 548 struct mv_port_signal signal[8];
549 const struct mv_hw_ops *ops;
f351b2d6
SB		 550 int n_ports;
551 void __iomem *base;
7368f919
ML		 552 void __iomem *main_irq_cause_addr;
553 void __iomem *main_irq_mask_addr;
cae5a29d
ML		 554 u32 irq_cause_offset;
555 u32 irq_mask_offset;
02a121da 556 u32 unmask_all_irqs;
c77a2f4e
SB		 557
558#if defined(CONFIG_HAVE_CLK)
559 struct clk *clk;
eee98990 560 struct clk **port_clks;
c77a2f4e 561#endif
da2fa9ba
ML		 562 /*
563 * These consistent DMA memory pools give us guaranteed
564 * alignment for hardware-accessed data structures,
565 * and less memory waste in accomplishing the alignment.
566 */
567 struct dma_pool *crqb_pool;
568 struct dma_pool *crpb_pool;
569 struct dma_pool *sg_tbl_pool;
02a121da
ML		 570};
571
47c2b677 572struct mv_hw_ops {
2a47ce06
JG		 573 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
574 unsigned int port);
47c2b677
JG		 575 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
576 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
577 void __iomem *mmio);
c9d39130
JG		 578 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
579 unsigned int n_hc);
522479fb 580 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 581 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
47c2b677
JG		 582};
583
82ef04fb
TH		 584static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
585static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
586static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
587static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
31961943
BR		 588static int mv_port_start(struct ata_port *ap);
589static void mv_port_stop(struct ata_port *ap);
3e4a1391 590static int mv_qc_defer(struct ata_queued_cmd *qc);
31961943 591static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 592static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 593static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
a1efdaba
TH		 594static int mv_hardreset(struct ata_link *link, unsigned int *class,
595 unsigned long deadline);
bdd4ddde
JG		 596static void mv_eh_freeze(struct ata_port *ap);
597static void mv_eh_thaw(struct ata_port *ap);
f273827e 598static void mv6_dev_config(struct ata_device *dev);
20f733e7 599
2a47ce06
JG		 600static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
601 unsigned int port);
47c2b677
JG		 602static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
603static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
604 void __iomem *mmio);
c9d39130
JG		 605static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
606 unsigned int n_hc);
522479fb 607static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 608static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
47c2b677 609
2a47ce06
JG		 610static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
611 unsigned int port);
47c2b677
JG		 612static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
613static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
614 void __iomem *mmio);
c9d39130
JG		 615static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
616 unsigned int n_hc);
522479fb 617static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
f351b2d6
SB		 618static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
619 void __iomem *mmio);
620static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
621 void __iomem *mmio);
622static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
623 void __iomem *mmio, unsigned int n_hc);
624static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
625 void __iomem *mmio);
626static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
29b7e43c
MM		 627static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
628 void __iomem *mmio, unsigned int port);
7bb3c529 629static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
e12bef50 630static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130 631 unsigned int port_no);
e12bef50 632static int mv_stop_edma(struct ata_port *ap);
b562468c 633static int mv_stop_edma_engine(void __iomem *port_mmio);
00b81235 634static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
47c2b677 635
e49856d8
ML		 636static void mv_pmp_select(struct ata_port *ap, int pmp);
637static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
638 unsigned long deadline);
639static int mv_softreset(struct ata_link *link, unsigned int *class,
640 unsigned long deadline);
29d187bb 641static void mv_pmp_error_handler(struct ata_port *ap);
4c299ca3
ML		 642static void mv_process_crpb_entries(struct ata_port *ap,
643 struct mv_port_priv *pp);
47c2b677 644
da14265e
ML		 645static void mv_sff_irq_clear(struct ata_port *ap);
646static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
647static void mv_bmdma_setup(struct ata_queued_cmd *qc);
648static void mv_bmdma_start(struct ata_queued_cmd *qc);
649static void mv_bmdma_stop(struct ata_queued_cmd *qc);
650static u8 mv_bmdma_status(struct ata_port *ap);
d16ab3f6 651static u8 mv_sff_check_status(struct ata_port *ap);
da14265e 652
eb73d558
ML		 653/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
654 * because we have to allow room for worst case splitting of
655 * PRDs for 64K boundaries in mv_fill_sg().
656 */
13b74085 657#ifdef CONFIG_PCI
c5d3e45a 658static struct scsi_host_template mv5_sht = {
68d1d07b 659 ATA_BASE_SHT(DRV_NAME),
baf14aa1 660 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a 661 .dma_boundary = MV_DMA_BOUNDARY,
c5d3e45a 662};
13b74085 663#endif
c5d3e45a 664static struct scsi_host_template mv6_sht = {
68d1d07b 665 ATA_NCQ_SHT(DRV_NAME),
138bfdd0 666 .can_queue = MV_MAX_Q_DEPTH - 1,
baf14aa1 667 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7 668 .dma_boundary = MV_DMA_BOUNDARY,
20f733e7
BR		 669};
670
029cfd6b
TH		 671static struct ata_port_operations mv5_ops = {
672 .inherits = &ata_sff_port_ops,
c9d39130 673
c96f1732
AC		 674 .lost_interrupt = ATA_OP_NULL,
675
3e4a1391 676 .qc_defer = mv_qc_defer,
c9d39130
JG		 677 .qc_prep = mv_qc_prep,
678 .qc_issue = mv_qc_issue,
c9d39130 679
bdd4ddde
JG		 680 .freeze = mv_eh_freeze,
681 .thaw = mv_eh_thaw,
a1efdaba 682 .hardreset = mv_hardreset,
bdd4ddde 683
c9d39130
JG		 684 .scr_read = mv5_scr_read,
685 .scr_write = mv5_scr_write,
686
687 .port_start = mv_port_start,
688 .port_stop = mv_port_stop,
c9d39130
JG		 689};
690
029cfd6b 691static struct ata_port_operations mv6_ops = {
8930ff25
TH		 692 .inherits = &ata_bmdma_port_ops,
693
694 .lost_interrupt = ATA_OP_NULL,
695
696 .qc_defer = mv_qc_defer,
697 .qc_prep = mv_qc_prep,
698 .qc_issue = mv_qc_issue,
699
f273827e 700 .dev_config = mv6_dev_config,
20f733e7 701
8930ff25
TH		 702 .freeze = mv_eh_freeze,
703 .thaw = mv_eh_thaw,
704 .hardreset = mv_hardreset,
705 .softreset = mv_softreset,
e49856d8
ML		 706 .pmp_hardreset = mv_pmp_hardreset,
707 .pmp_softreset = mv_softreset,
29d187bb 708 .error_handler = mv_pmp_error_handler,
da14265e 709
8930ff25
TH		 710 .scr_read = mv_scr_read,
711 .scr_write = mv_scr_write,
712
40f21b11 713 .sff_check_status = mv_sff_check_status,
da14265e
ML		 714 .sff_irq_clear = mv_sff_irq_clear,
715 .check_atapi_dma = mv_check_atapi_dma,
716 .bmdma_setup = mv_bmdma_setup,
717 .bmdma_start = mv_bmdma_start,
718 .bmdma_stop = mv_bmdma_stop,
719 .bmdma_status = mv_bmdma_status,
8930ff25
TH		 720
721 .port_start = mv_port_start,
722 .port_stop = mv_port_stop,
20f733e7
BR		 723};
724
029cfd6b
TH		 725static struct ata_port_operations mv_iie_ops = {
726 .inherits = &mv6_ops,
727 .dev_config = ATA_OP_NULL,
e4e7b892 728 .qc_prep = mv_qc_prep_iie,
e4e7b892
JG		 729};
730
98ac62de 731static const struct ata_port_info mv_port_info[] = {
20f733e7 732 { /* chip_504x */
91b1a84c 733 .flags = MV_GEN_I_FLAGS,
c361acbc 734 .pio_mask = ATA_PIO4,
bf6263a8 735 .udma_mask = ATA_UDMA6,
c9d39130 736 .port_ops = &mv5_ops,
20f733e7
BR		 737 },
738 { /* chip_508x */
91b1a84c 739 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
c361acbc 740 .pio_mask = ATA_PIO4,
bf6263a8 741 .udma_mask = ATA_UDMA6,
c9d39130 742 .port_ops = &mv5_ops,
20f733e7 743 },
47c2b677 744 { /* chip_5080 */
91b1a84c 745 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
c361acbc 746 .pio_mask = ATA_PIO4,
bf6263a8 747 .udma_mask = ATA_UDMA6,
c9d39130 748 .port_ops = &mv5_ops,
47c2b677 749 },
20f733e7 750 { /* chip_604x */
91b1a84c 751 .flags = MV_GEN_II_FLAGS,
c361acbc 752 .pio_mask = ATA_PIO4,
bf6263a8 753 .udma_mask = ATA_UDMA6,
c9d39130 754 .port_ops = &mv6_ops,
20f733e7
BR		 755 },
756 { /* chip_608x */
91b1a84c 757 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
c361acbc 758 .pio_mask = ATA_PIO4,
bf6263a8 759 .udma_mask = ATA_UDMA6,
c9d39130 760 .port_ops = &mv6_ops,
20f733e7 761 },
e4e7b892 762 { /* chip_6042 */
91b1a84c 763 .flags = MV_GEN_IIE_FLAGS,
c361acbc 764 .pio_mask = ATA_PIO4,
bf6263a8 765 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 766 .port_ops = &mv_iie_ops,
767 },
768 { /* chip_7042 */
91b1a84c 769 .flags = MV_GEN_IIE_FLAGS,
c361acbc 770 .pio_mask = ATA_PIO4,
bf6263a8 771 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 772 .port_ops = &mv_iie_ops,
773 },
f351b2d6 774 { /* chip_soc */
91b1a84c 775 .flags = MV_GEN_IIE_FLAGS,
c361acbc 776 .pio_mask = ATA_PIO4,
17c5aab5
ML		 777 .udma_mask = ATA_UDMA6,
778 .port_ops = &mv_iie_ops,
f351b2d6 779 },
20f733e7
BR		 780};
781
3b7d697d 782static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 783 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
784 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
785 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
786 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
46c5784c
ML		 787 /* RocketRAID 1720/174x have different identifiers */
788 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
4462254a
ML		 789 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
790 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
2d2744fc
JG		 791
792 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
793 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
794 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
795 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
796 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
797
798 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
799
d9f9c6bc
FA		 800 /* Adaptec 1430SA */
801 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
802
02a121da 803 /* Marvell 7042 support */
6a3d586d
MT		 804 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
805
02a121da
ML		 806 /* Highpoint RocketRAID PCIe series */
807 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
808 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
809
2d2744fc 810 { } /* terminate list */
20f733e7
BR		 811};
812
47c2b677
JG		 813static const struct mv_hw_ops mv5xxx_ops = {
814 .phy_errata = mv5_phy_errata,
815 .enable_leds = mv5_enable_leds,
816 .read_preamp = mv5_read_preamp,
817 .reset_hc = mv5_reset_hc,
522479fb
JG		 818 .reset_flash = mv5_reset_flash,
819 .reset_bus = mv5_reset_bus,
47c2b677
JG		 820};
821
822static const struct mv_hw_ops mv6xxx_ops = {
823 .phy_errata = mv6_phy_errata,
824 .enable_leds = mv6_enable_leds,
825 .read_preamp = mv6_read_preamp,
826 .reset_hc = mv6_reset_hc,
522479fb
JG		 827 .reset_flash = mv6_reset_flash,
828 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 829};
830
f351b2d6
SB		 831static const struct mv_hw_ops mv_soc_ops = {
832 .phy_errata = mv6_phy_errata,
833 .enable_leds = mv_soc_enable_leds,
834 .read_preamp = mv_soc_read_preamp,
835 .reset_hc = mv_soc_reset_hc,
836 .reset_flash = mv_soc_reset_flash,
837 .reset_bus = mv_soc_reset_bus,
838};
839
29b7e43c
MM		 840static const struct mv_hw_ops mv_soc_65n_ops = {
841 .phy_errata = mv_soc_65n_phy_errata,
842 .enable_leds = mv_soc_enable_leds,
843 .reset_hc = mv_soc_reset_hc,
844 .reset_flash = mv_soc_reset_flash,
845 .reset_bus = mv_soc_reset_bus,
846};
847
20f733e7
BR		 848/*
849 * Functions
850 */
851
852static inline void writelfl(unsigned long data, void __iomem *addr)
853{
854 writel(data, addr);
855 (void) readl(addr); /* flush to avoid PCI posted write */
856}
857
c9d39130
JG		 858static inline unsigned int mv_hc_from_port(unsigned int port)
859{
860 return port >> MV_PORT_HC_SHIFT;
861}
862
863static inline unsigned int mv_hardport_from_port(unsigned int port)
864{
865 return port & MV_PORT_MASK;
866}
867
1cfd19ae
ML		 868/*
869 * Consolidate some rather tricky bit shift calculations.
870 * This is hot-path stuff, so not a function.
871 * Simple code, with two return values, so macro rather than inline.
872 *
873 * port is the sole input, in range 0..7.
7368f919
ML		 874 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
875 * hardport is the other output, in range 0..3.
1cfd19ae
ML		 876 *
877 * Note that port and hardport may be the same variable in some cases.
878 */
879#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
880{ \
881 shift = mv_hc_from_port(port) * HC_SHIFT; \
882 hardport = mv_hardport_from_port(port); \
883 shift += hardport * 2; \
884}
885
352fab70
ML		 886static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
887{
cae5a29d 888 return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
352fab70
ML		 889}
890
c9d39130
JG		 891static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
892 unsigned int port)
893{
894 return mv_hc_base(base, mv_hc_from_port(port));
895}
896
20f733e7
BR		 897static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
898{
c9d39130 899 return mv_hc_base_from_port(base, port) +
8b260248 900 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 901 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 902}
903
e12bef50
ML		 904static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
905{
906 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
907 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
908
909 return hc_mmio + ofs;
910}
911
f351b2d6
SB		 912static inline void __iomem *mv_host_base(struct ata_host *host)
913{
914 struct mv_host_priv *hpriv = host->private_data;
915 return hpriv->base;
916}
917
20f733e7
BR		 918static inline void __iomem *mv_ap_base(struct ata_port *ap)
919{
f351b2d6 920 return mv_port_base(mv_host_base(ap->host), ap->port_no);
20f733e7
BR		 921}
922
cca3974e 923static inline int mv_get_hc_count(unsigned long port_flags)
31961943 924{
cca3974e 925 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 926}
927
08da1759
ML		 928/**
929 * mv_save_cached_regs - (re-)initialize cached port registers
930 * @ap: the port whose registers we are caching
931 *
932 * Initialize the local cache of port registers,
933 * so that reading them over and over again can
934 * be avoided on the hotter paths of this driver.
935 * This saves a few microseconds each time we switch
936 * to/from EDMA mode to perform (eg.) a drive cache flush.
937 */
938static void mv_save_cached_regs(struct ata_port *ap)
939{
940 void __iomem *port_mmio = mv_ap_base(ap);
941 struct mv_port_priv *pp = ap->private_data;
942
cae5a29d
ML		 943 pp->cached.fiscfg = readl(port_mmio + FISCFG);
944 pp->cached.ltmode = readl(port_mmio + LTMODE);
945 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
946 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
08da1759
ML		 947}
948
949/**
950 * mv_write_cached_reg - write to a cached port register
951 * @addr: hardware address of the register
952 * @old: pointer to cached value of the register
953 * @new: new value for the register
954 *
955 * Write a new value to a cached register,
956 * but only if the value is different from before.
957 */
958static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
959{
960 if (new != *old) {
12f3b6d7 961 unsigned long laddr;
08da1759 962 *old = new;
12f3b6d7
ML		 963 /*
964 * Workaround for 88SX60x1-B2 FEr SATA#13:
965 * Read-after-write is needed to prevent generating 64-bit
966 * write cycles on the PCI bus for SATA interface registers
967 * at offsets ending in 0x4 or 0xc.
968 *
969 * Looks like a lot of fuss, but it avoids an unnecessary
970 * +1 usec read-after-write delay for unaffected registers.
971 */
972 laddr = (long)addr & 0xffff;
973 if (laddr >= 0x300 && laddr <= 0x33c) {
974 laddr &= 0x000f;
975 if (laddr == 0x4 || laddr == 0xc) {
976 writelfl(new, addr); /* read after write */
977 return;
978 }
979 }
980 writel(new, addr); /* unaffected by the errata */
08da1759
ML		 981 }
982}
983
c5d3e45a
JG		 984static void mv_set_edma_ptrs(void __iomem *port_mmio,
985 struct mv_host_priv *hpriv,
986 struct mv_port_priv *pp)
987{
bdd4ddde
JG		 988 u32 index;
989
c5d3e45a
JG		 990 /*
991 * initialize request queue
992 */
fcfb1f77
ML		 993 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
994 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
bdd4ddde 995
c5d3e45a 996 WARN_ON(pp->crqb_dma & 0x3ff);
cae5a29d 997 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
bdd4ddde 998 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
cae5a29d
ML		 999 port_mmio + EDMA_REQ_Q_IN_PTR);
1000 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
c5d3e45a
JG		 1001
1002 /*
1003 * initialize response queue
1004 */
fcfb1f77
ML		 1005 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
1006 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
bdd4ddde 1007
c5d3e45a 1008 WARN_ON(pp->crpb_dma & 0xff);
cae5a29d
ML		 1009 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
1010 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
bdd4ddde 1011 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
cae5a29d 1012 port_mmio + EDMA_RSP_Q_OUT_PTR);
c5d3e45a
JG		 1013}
1014
2b748a0a
ML		 1015static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
1016{
1017 /*
1018 * When writing to the main_irq_mask in hardware,
1019 * we must ensure exclusivity between the interrupt coalescing bits
1020 * and the corresponding individual port DONE_IRQ bits.
1021 *
1022 * Note that this register is really an "IRQ enable" register,
1023 * not an "IRQ mask" register as Marvell's naming might suggest.
1024 */
1025 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
1026 mask &= ~DONE_IRQ_0_3;
1027 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
1028 mask &= ~DONE_IRQ_4_7;
1029 writelfl(mask, hpriv->main_irq_mask_addr);
1030}
1031
c4de573b
ML		 1032static void mv_set_main_irq_mask(struct ata_host *host,
1033 u32 disable_bits, u32 enable_bits)
1034{
1035 struct mv_host_priv *hpriv = host->private_data;
1036 u32 old_mask, new_mask;
1037
96e2c487 1038 old_mask = hpriv->main_irq_mask;
c4de573b 1039 new_mask = (old_mask & ~disable_bits) | enable_bits;
96e2c487
ML		 1040 if (new_mask != old_mask) {
1041 hpriv->main_irq_mask = new_mask;
2b748a0a 1042 mv_write_main_irq_mask(new_mask, hpriv);
96e2c487 1043 }
c4de573b
ML		 1044}
1045
1046static void mv_enable_port_irqs(struct ata_port *ap,
1047 unsigned int port_bits)
1048{
1049 unsigned int shift, hardport, port = ap->port_no;
1050 u32 disable_bits, enable_bits;
1051
1052 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1053
1054 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
1055 enable_bits = port_bits << shift;
1056 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
1057}
1058
00b81235
ML		 1059static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
1060 void __iomem *port_mmio,
1061 unsigned int port_irqs)
1062{
1063 struct mv_host_priv *hpriv = ap->host->private_data;
1064 int hardport = mv_hardport_from_port(ap->port_no);
1065 void __iomem *hc_mmio = mv_hc_base_from_port(
1066 mv_host_base(ap->host), ap->port_no);
1067 u32 hc_irq_cause;
1068
1069 /* clear EDMA event indicators, if any */
cae5a29d 1070 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
00b81235
ML		 1071
1072 /* clear pending irq events */
1073 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
cae5a29d 1074 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
00b81235
ML		 1075
1076 /* clear FIS IRQ Cause */
1077 if (IS_GEN_IIE(hpriv))
cae5a29d 1078 writelfl(0, port_mmio + FIS_IRQ_CAUSE);
00b81235
ML		 1079
1080 mv_enable_port_irqs(ap, port_irqs);
1081}
1082
2b748a0a
ML		 1083static void mv_set_irq_coalescing(struct ata_host *host,
1084 unsigned int count, unsigned int usecs)
1085{
1086 struct mv_host_priv *hpriv = host->private_data;
1087 void __iomem *mmio = hpriv->base, *hc_mmio;
1088 u32 coal_enable = 0;
1089 unsigned long flags;
6abf4678 1090 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
2b748a0a
ML		 1091 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1092 ALL_PORTS_COAL_DONE;
1093
1094 /* Disable IRQ coalescing if either threshold is zero */
1095 if (!usecs || !count) {
1096 clks = count = 0;
1097 } else {
1098 /* Respect maximum limits of the hardware */
1099 clks = usecs * COAL_CLOCKS_PER_USEC;
1100 if (clks > MAX_COAL_TIME_THRESHOLD)
1101 clks = MAX_COAL_TIME_THRESHOLD;
1102 if (count > MAX_COAL_IO_COUNT)
1103 count = MAX_COAL_IO_COUNT;
1104 }
1105
1106 spin_lock_irqsave(&host->lock, flags);
6abf4678 1107 mv_set_main_irq_mask(host, coal_disable, 0);
2b748a0a 1108
6abf4678 1109 if (is_dual_hc && !IS_GEN_I(hpriv)) {
2b748a0a 1110 /*
6abf4678
ML		 1111 * GEN_II/GEN_IIE with dual host controllers:
1112 * one set of global thresholds for the entire chip.
2b748a0a 1113 */
cae5a29d
ML		 1114 writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
1115 writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
2b748a0a 1116 /* clear leftover coal IRQ bit */
cae5a29d 1117 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
6abf4678
ML		 1118 if (count)
1119 coal_enable = ALL_PORTS_COAL_DONE;
1120 clks = count = 0; /* force clearing of regular regs below */
2b748a0a 1121 }
6abf4678 1122
2b748a0a
ML		 1123 /*
1124 * All chips: independent thresholds for each HC on the chip.
1125 */
1126 hc_mmio = mv_hc_base_from_port(mmio, 0);
cae5a29d
ML		 1127 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1128 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1129 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
6abf4678
ML		 1130 if (count)
1131 coal_enable |= PORTS_0_3_COAL_DONE;
1132 if (is_dual_hc) {
2b748a0a 1133 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
cae5a29d
ML		 1134 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1135 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1136 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
6abf4678
ML		 1137 if (count)
1138 coal_enable |= PORTS_4_7_COAL_DONE;
2b748a0a 1139 }
2b748a0a 1140
6abf4678 1141 mv_set_main_irq_mask(host, 0, coal_enable);
2b748a0a
ML		 1142 spin_unlock_irqrestore(&host->lock, flags);
1143}
1144
05b308e1 1145/**
00b81235 1146 * mv_start_edma - Enable eDMA engine
05b308e1
BR		 1147 * @base: port base address
1148 * @pp: port private data
1149 *
beec7dbc
TH		 1150 * Verify the local cache of the eDMA state is accurate with a
1151 * WARN_ON.
05b308e1
BR		 1152 *
1153 * LOCKING:
1154 * Inherited from caller.
1155 */
00b81235 1156static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
72109168 1157 struct mv_port_priv *pp, u8 protocol)
20f733e7 1158{
72109168
ML		 1159 int want_ncq = (protocol == ATA_PROT_NCQ);
1160
1161 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1162 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1163 if (want_ncq != using_ncq)
b562468c 1164 mv_stop_edma(ap);
72109168 1165 }
c5d3e45a 1166 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e 1167 struct mv_host_priv *hpriv = ap->host->private_data;
0c58912e 1168
00b81235 1169 mv_edma_cfg(ap, want_ncq, 1);
0c58912e 1170
f630d562 1171 mv_set_edma_ptrs(port_mmio, hpriv, pp);
00b81235 1172 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
bdd4ddde 1173
cae5a29d 1174 writelfl(EDMA_EN, port_mmio + EDMA_CMD);
afb0edd9
BR		 1175 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1176 }
20f733e7
BR		 1177}
1178
9b2c4e0b
ML		 1179static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1180{
1181 void __iomem *port_mmio = mv_ap_base(ap);
1182 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1183 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1184 int i;
1185
1186 /*
1187 * Wait for the EDMA engine to finish transactions in progress.
c46938cc
ML		 1188 * No idea what a good "timeout" value might be, but measurements
1189 * indicate that it often requires hundreds of microseconds
1190 * with two drives in-use. So we use the 15msec value above
1191 * as a rough guess at what even more drives might require.
9b2c4e0b
ML		 1192 */
1193 for (i = 0; i < timeout; ++i) {
cae5a29d 1194 u32 edma_stat = readl(port_mmio + EDMA_STATUS);
9b2c4e0b
ML		 1195 if ((edma_stat & empty_idle) == empty_idle)
1196 break;
1197 udelay(per_loop);
1198 }
a9a79dfe 1199 /* ata_port_info(ap, "%s: %u+ usecs\n", __func__, i); */
9b2c4e0b
ML		 1200}
1201
05b308e1 1202/**
e12bef50 1203 * mv_stop_edma_engine - Disable eDMA engine
b562468c 1204 * @port_mmio: io base address
05b308e1
BR		 1205 *
1206 * LOCKING:
1207 * Inherited from caller.
1208 */
b562468c 1209static int mv_stop_edma_engine(void __iomem *port_mmio)
20f733e7 1210{
b562468c 1211 int i;
31961943 1212
b562468c 1213 /* Disable eDMA. The disable bit auto clears. */
cae5a29d 1214 writelfl(EDMA_DS, port_mmio + EDMA_CMD);
8b260248 1215
b562468c
ML		 1216 /* Wait for the chip to confirm eDMA is off. */
1217 for (i = 10000; i > 0; i--) {
cae5a29d 1218 u32 reg = readl(port_mmio + EDMA_CMD);
4537deb5 1219 if (!(reg & EDMA_EN))
b562468c
ML		 1220 return 0;
1221 udelay(10);
31961943 1222 }
b562468c 1223 return -EIO;
20f733e7
BR		 1224}
1225
e12bef50 1226static int mv_stop_edma(struct ata_port *ap)
0ea9e179 1227{
b562468c
ML		 1228 void __iomem *port_mmio = mv_ap_base(ap);
1229 struct mv_port_priv *pp = ap->private_data;
66e57a2c 1230 int err = 0;
0ea9e179 1231
b562468c
ML		 1232 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1233 return 0;
1234 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
9b2c4e0b 1235 mv_wait_for_edma_empty_idle(ap);
b562468c 1236 if (mv_stop_edma_engine(port_mmio)) {
a9a79dfe 1237 ata_port_err(ap, "Unable to stop eDMA\n");
66e57a2c 1238 err = -EIO;
b562468c 1239 }
66e57a2c
ML		 1240 mv_edma_cfg(ap, 0, 0);
1241 return err;
0ea9e179
JG		 1242}
1243
8a70f8dc 1244#ifdef ATA_DEBUG
31961943 1245static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 1246{
31961943
BR		 1247 int b, w;
1248 for (b = 0; b < bytes; ) {
1249 DPRINTK("%p: ", start + b);
1250 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 1251 printk("%08x ", readl(start + b));
31961943
BR		 1252 b += sizeof(u32);
1253 }
1254 printk("\n");
1255 }
31961943 1256}
8a70f8dc 1257#endif
13b74085 1258#if defined(ATA_DEBUG) || defined(CONFIG_PCI)
31961943
BR		 1259static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1260{
1261#ifdef ATA_DEBUG
1262 int b, w;
1263 u32 dw;
1264 for (b = 0; b < bytes; ) {
1265 DPRINTK("%02x: ", b);
1266 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 1267 (void) pci_read_config_dword(pdev, b, &dw);
1268 printk("%08x ", dw);
31961943
BR		 1269 b += sizeof(u32);
1270 }
1271 printk("\n");
1272 }
1273#endif
1274}
13b74085 1275#endif
31961943
BR		 1276static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1277 struct pci_dev *pdev)
1278{
1279#ifdef ATA_DEBUG
8b260248 1280 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 1281 port >> MV_PORT_HC_SHIFT);
1282 void __iomem *port_base;
1283 int start_port, num_ports, p, start_hc, num_hcs, hc;
1284
1285 if (0 > port) {
1286 start_hc = start_port = 0;
1287 num_ports = 8; /* shld be benign for 4 port devs */
1288 num_hcs = 2;
1289 } else {
1290 start_hc = port >> MV_PORT_HC_SHIFT;
1291 start_port = port;
1292 num_ports = num_hcs = 1;
1293 }
8b260248 1294 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 1295 num_ports > 1 ? num_ports - 1 : start_port);
1296
1297 if (NULL != pdev) {
1298 DPRINTK("PCI config space regs:\n");
1299 mv_dump_pci_cfg(pdev, 0x68);
1300 }
1301 DPRINTK("PCI regs:\n");
1302 mv_dump_mem(mmio_base+0xc00, 0x3c);
1303 mv_dump_mem(mmio_base+0xd00, 0x34);
1304 mv_dump_mem(mmio_base+0xf00, 0x4);
1305 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1306 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 1307 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 1308 DPRINTK("HC regs (HC %i):\n", hc);
1309 mv_dump_mem(hc_base, 0x1c);
1310 }
1311 for (p = start_port; p < start_port + num_ports; p++) {
1312 port_base = mv_port_base(mmio_base, p);
2dcb407e 1313 DPRINTK("EDMA regs (port %i):\n", p);
31961943 1314 mv_dump_mem(port_base, 0x54);
2dcb407e 1315 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 1316 mv_dump_mem(port_base+0x300, 0x60);
1317 }
1318#endif
20f733e7
BR		 1319}
1320
1321static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1322{
1323 unsigned int ofs;
1324
1325 switch (sc_reg_in) {
1326 case SCR_STATUS:
1327 case SCR_CONTROL:
1328 case SCR_ERROR:
cae5a29d 1329 ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
20f733e7
BR		 1330 break;
1331 case SCR_ACTIVE:
cae5a29d 1332 ofs = SATA_ACTIVE; /* active is not with the others */
20f733e7
BR		 1333 break;
1334 default:
1335 ofs = 0xffffffffU;
1336 break;
1337 }
1338 return ofs;
1339}
1340
82ef04fb 1341static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1342{
1343 unsigned int ofs = mv_scr_offset(sc_reg_in);
1344
da3dbb17 1345 if (ofs != 0xffffffffU) {
82ef04fb 1346 *val = readl(mv_ap_base(link->ap) + ofs);
da3dbb17
TH		 1347 return 0;
1348 } else
1349 return -EINVAL;
20f733e7
BR		 1350}
1351
82ef04fb 1352static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1353{
1354 unsigned int ofs = mv_scr_offset(sc_reg_in);
1355
da3dbb17 1356 if (ofs != 0xffffffffU) {
20091773 1357 void __iomem *addr = mv_ap_base(link->ap) + ofs;
6314611a 1358 struct mv_host_priv *hpriv = link->ap->host->private_data;
20091773
ML		 1359 if (sc_reg_in == SCR_CONTROL) {
1360 /*
1361 * Workaround for 88SX60x1 FEr SATA#26:
1362 *
25985edc 1363 * COMRESETs have to take care not to accidentally
20091773
ML		 1364 * put the drive to sleep when writing SCR_CONTROL.
1365 * Setting bits 12..15 prevents this problem.
1366 *
1367 * So if we see an outbound COMMRESET, set those bits.
1368 * Ditto for the followup write that clears the reset.
1369 *
1370 * The proprietary driver does this for
1371 * all chip versions, and so do we.
1372 */
1373 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
1374 val |= 0xf000;
6314611a
LA		 1375
1376 if (hpriv->hp_flags & MV_HP_FIX_LP_PHY_CTL) {
1377 void __iomem *lp_phy_addr =
1378 mv_ap_base(link->ap) + LP_PHY_CTL;
1379 /*
1380 * Set PHY speed according to SControl speed.
1381 */
1382 if ((val & 0xf0) == 0x10)
1383 writelfl(0x7, lp_phy_addr);
1384 else
1385 writelfl(0x227, lp_phy_addr);
1386 }
20091773
ML		 1387 }
1388 writelfl(val, addr);
da3dbb17
TH		 1389 return 0;
1390 } else
1391 return -EINVAL;
20f733e7
BR		 1392}
1393
f273827e
ML		 1394static void mv6_dev_config(struct ata_device *adev)
1395{
1396 /*
e49856d8
ML		 1397 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1398 *
1399 * Gen-II does not support NCQ over a port multiplier
1400 * (no FIS-based switching).
f273827e 1401 */
e49856d8 1402 if (adev->flags & ATA_DFLAG_NCQ) {
352fab70 1403 if (sata_pmp_attached(adev->link->ap)) {
e49856d8 1404 adev->flags &= ~ATA_DFLAG_NCQ;
a9a79dfe 1405 ata_dev_info(adev,
352fab70 1406 "NCQ disabled for command-based switching\n");
352fab70 1407 }
e49856d8 1408 }
f273827e
ML		 1409}
1410
3e4a1391
ML		 1411static int mv_qc_defer(struct ata_queued_cmd *qc)
1412{
1413 struct ata_link *link = qc->dev->link;
1414 struct ata_port *ap = link->ap;
1415 struct mv_port_priv *pp = ap->private_data;
1416
29d187bb
ML		 1417 /*
1418 * Don't allow new commands if we're in a delayed EH state
1419 * for NCQ and/or FIS-based switching.
1420 */
1421 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1422 return ATA_DEFER_PORT;
159a7ff7
GG		 1423
1424 /* PIO commands need exclusive link: no other commands [DMA or PIO]
1425 * can run concurrently.
1426 * set excl_link when we want to send a PIO command in DMA mode
1427 * or a non-NCQ command in NCQ mode.
1428 * When we receive a command from that link, and there are no
1429 * outstanding commands, mark a flag to clear excl_link and let
1430 * the command go through.
1431 */
1432 if (unlikely(ap->excl_link)) {
1433 if (link == ap->excl_link) {
1434 if (ap->nr_active_links)
1435 return ATA_DEFER_PORT;
1436 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
1437 return 0;
1438 } else
1439 return ATA_DEFER_PORT;
1440 }
1441
3e4a1391
ML		 1442 /*
1443 * If the port is completely idle, then allow the new qc.
1444 */
1445 if (ap->nr_active_links == 0)
1446 return 0;
1447
4bdee6c5
TH		 1448 /*
1449 * The port is operating in host queuing mode (EDMA) with NCQ
1450 * enabled, allow multiple NCQ commands. EDMA also allows
1451 * queueing multiple DMA commands but libata core currently
1452 * doesn't allow it.
1453 */
1454 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
159a7ff7
GG		 1455 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
1456 if (ata_is_ncq(qc->tf.protocol))
1457 return 0;
1458 else {
1459 ap->excl_link = link;
1460 return ATA_DEFER_PORT;
1461 }
1462 }
4bdee6c5 1463
3e4a1391
ML		 1464 return ATA_DEFER_PORT;
1465}
1466
08da1759 1467static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
e49856d8 1468{
08da1759
ML		 1469 struct mv_port_priv *pp = ap->private_data;
1470 void __iomem *port_mmio;
00f42eab 1471
08da1759
ML		 1472 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1473 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1474 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
00f42eab 1475
08da1759
ML		 1476 ltmode = *old_ltmode & ~LTMODE_BIT8;
1477 haltcond = *old_haltcond | EDMA_ERR_DEV;
00f42eab
ML		 1478
1479 if (want_fbs) {
08da1759
ML		 1480 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1481 ltmode = *old_ltmode | LTMODE_BIT8;
4c299ca3 1482 if (want_ncq)
08da1759 1483 haltcond &= ~EDMA_ERR_DEV;
4c299ca3 1484 else
08da1759
ML		 1485 fiscfg |= FISCFG_WAIT_DEV_ERR;
1486 } else {
1487 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
e49856d8 1488 }
00f42eab 1489
08da1759 1490 port_mmio = mv_ap_base(ap);
cae5a29d
ML		 1491 mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
1492 mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
1493 mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
f273827e
ML		 1494}
1495
dd2890f6
ML		 1496static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1497{
1498 struct mv_host_priv *hpriv = ap->host->private_data;
1499 u32 old, new;
1500
1501 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
cae5a29d 1502 old = readl(hpriv->base + GPIO_PORT_CTL);
dd2890f6
ML		 1503 if (want_ncq)
1504 new = old | (1 << 22);
1505 else
1506 new = old & ~(1 << 22);
1507 if (new != old)
cae5a29d 1508 writel(new, hpriv->base + GPIO_PORT_CTL);
dd2890f6
ML		 1509}
1510
c01e8a23 1511/**
40f21b11
ML		 1512 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1513 * @ap: Port being initialized
c01e8a23
ML		 1514 *
1515 * There are two DMA modes on these chips: basic DMA, and EDMA.
1516 *
1517 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1518 * of basic DMA on the GEN_IIE versions of the chips.
1519 *
1520 * This bit survives EDMA resets, and must be set for basic DMA
1521 * to function, and should be cleared when EDMA is active.
1522 */
1523static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1524{
1525 struct mv_port_priv *pp = ap->private_data;
1526 u32 new, *old = &pp->cached.unknown_rsvd;
1527
1528 if (enable_bmdma)
1529 new = *old | 1;
1530 else
1531 new = *old & ~1;
cae5a29d 1532 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
c01e8a23
ML		 1533}
1534
000b344f
ML		 1535/*
1536 * SOC chips have an issue whereby the HDD LEDs don't always blink
1537 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1538 * of the SOC takes care of it, generating a steady blink rate when
1539 * any drive on the chip is active.
1540 *
1541 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1542 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1543 *
1544 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1545 * LED operation works then, and provides better (more accurate) feedback.
1546 *
1547 * Note that this code assumes that an SOC never has more than one HC onboard.
1548 */
1549static void mv_soc_led_blink_enable(struct ata_port *ap)
1550{
1551 struct ata_host *host = ap->host;
1552 struct mv_host_priv *hpriv = host->private_data;
1553 void __iomem *hc_mmio;
1554 u32 led_ctrl;
1555
1556 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1557 return;
1558 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1559 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
cae5a29d
ML		 1560 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1561 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
000b344f
ML		 1562}
1563
1564static void mv_soc_led_blink_disable(struct ata_port *ap)
1565{
1566 struct ata_host *host = ap->host;
1567 struct mv_host_priv *hpriv = host->private_data;
1568 void __iomem *hc_mmio;
1569 u32 led_ctrl;
1570 unsigned int port;
1571
1572 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1573 return;
1574
1575 /* disable led-blink only if no ports are using NCQ */
1576 for (port = 0; port < hpriv->n_ports; port++) {
1577 struct ata_port *this_ap = host->ports[port];
1578 struct mv_port_priv *pp = this_ap->private_data;
1579
1580 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1581 return;
1582 }
1583
1584 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1585 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
cae5a29d
ML		 1586 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1587 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
000b344f
ML		 1588}
1589
00b81235 1590static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
e4e7b892 1591{
0c58912e 1592 u32 cfg;
e12bef50
ML		 1593 struct mv_port_priv *pp = ap->private_data;
1594 struct mv_host_priv *hpriv = ap->host->private_data;
1595 void __iomem *port_mmio = mv_ap_base(ap);
e4e7b892
JG		 1596
1597 /* set up non-NCQ EDMA configuration */
0c58912e 1598 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
d16ab3f6
ML		 1599 pp->pp_flags &=
1600 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
e4e7b892 1601
0c58912e 1602 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1603 cfg |= (1 << 8); /* enab config burst size mask */
1604
dd2890f6 1605 else if (IS_GEN_II(hpriv)) {
e4e7b892 1606 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
dd2890f6 1607 mv_60x1_errata_sata25(ap, want_ncq);
e4e7b892 1608
dd2890f6 1609 } else if (IS_GEN_IIE(hpriv)) {
00f42eab
ML		 1610 int want_fbs = sata_pmp_attached(ap);
1611 /*
1612 * Possible future enhancement:
1613 *
1614 * The chip can use FBS with non-NCQ, if we allow it,
1615 * But first we need to have the error handling in place
1616 * for this mode (datasheet section 7.3.15.4.2.3).
1617 * So disallow non-NCQ FBS for now.
1618 */
1619 want_fbs &= want_ncq;
1620
08da1759 1621 mv_config_fbs(ap, want_ncq, want_fbs);
00f42eab
ML		 1622
1623 if (want_fbs) {
1624 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1625 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1626 }
1627
e728eabe 1628 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
00b81235
ML		 1629 if (want_edma) {
1630 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1631 if (!IS_SOC(hpriv))
1632 cfg |= (1 << 18); /* enab early completion */
1633 }
616d4a98
ML		 1634 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1635 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
c01e8a23 1636 mv_bmdma_enable_iie(ap, !want_edma);
000b344f
ML		 1637
1638 if (IS_SOC(hpriv)) {
1639 if (want_ncq)
1640 mv_soc_led_blink_enable(ap);
1641 else
1642 mv_soc_led_blink_disable(ap);
1643 }
e4e7b892
JG		 1644 }
1645
72109168
ML		 1646 if (want_ncq) {
1647 cfg |= EDMA_CFG_NCQ;
1648 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
00b81235 1649 }
72109168 1650
cae5a29d 1651 writelfl(cfg, port_mmio + EDMA_CFG);
e4e7b892
JG		 1652}
1653
da2fa9ba
ML		 1654static void mv_port_free_dma_mem(struct ata_port *ap)
1655{
1656 struct mv_host_priv *hpriv = ap->host->private_data;
1657 struct mv_port_priv *pp = ap->private_data;
eb73d558 1658 int tag;
da2fa9ba
ML		 1659
1660 if (pp->crqb) {
1661 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1662 pp->crqb = NULL;
1663 }
1664 if (pp->crpb) {
1665 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1666 pp->crpb = NULL;
1667 }
eb73d558
ML		 1668 /*
1669 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1670 * For later hardware, we have one unique sg_tbl per NCQ tag.
1671 */
1672 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1673 if (pp->sg_tbl[tag]) {
1674 if (tag == 0 || !IS_GEN_I(hpriv))
1675 dma_pool_free(hpriv->sg_tbl_pool,
1676 pp->sg_tbl[tag],
1677 pp->sg_tbl_dma[tag]);
1678 pp->sg_tbl[tag] = NULL;
1679 }
da2fa9ba
ML		 1680 }
1681}
1682
05b308e1
BR		 1683/**
1684 * mv_port_start - Port specific init/start routine.
1685 * @ap: ATA channel to manipulate
1686 *
1687 * Allocate and point to DMA memory, init port private memory,
1688 * zero indices.
1689 *
1690 * LOCKING:
1691 * Inherited from caller.
1692 */
31961943
BR		 1693static int mv_port_start(struct ata_port *ap)
1694{
cca3974e
JG		 1695 struct device *dev = ap->host->dev;
1696 struct mv_host_priv *hpriv = ap->host->private_data;
31961943 1697 struct mv_port_priv *pp;
933cb8e5 1698 unsigned long flags;
dde20207 1699 int tag;
31961943 1700
24dc5f33 1701 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1702 if (!pp)
24dc5f33 1703 return -ENOMEM;
da2fa9ba 1704 ap->private_data = pp;
31961943 1705
da2fa9ba
ML		 1706 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1707 if (!pp->crqb)
1708 return -ENOMEM;
1709 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
31961943 1710
da2fa9ba
ML		 1711 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1712 if (!pp->crpb)
1713 goto out_port_free_dma_mem;
1714 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
31961943 1715
3bd0a70e
ML		 1716 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1717 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1718 ap->flags |= ATA_FLAG_AN;
eb73d558
ML		 1719 /*
1720 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1721 * For later hardware, we need one unique sg_tbl per NCQ tag.
1722 */
1723 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1724 if (tag == 0 || !IS_GEN_I(hpriv)) {
1725 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1726 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1727 if (!pp->sg_tbl[tag])
1728 goto out_port_free_dma_mem;
1729 } else {
1730 pp->sg_tbl[tag] = pp->sg_tbl[0];
1731 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1732 }
1733 }
933cb8e5
ML		 1734
1735 spin_lock_irqsave(ap->lock, flags);
08da1759 1736 mv_save_cached_regs(ap);
66e57a2c 1737 mv_edma_cfg(ap, 0, 0);
933cb8e5
ML		 1738 spin_unlock_irqrestore(ap->lock, flags);
1739
31961943 1740 return 0;
da2fa9ba
ML		 1741
1742out_port_free_dma_mem:
1743 mv_port_free_dma_mem(ap);
1744 return -ENOMEM;
31961943
BR		 1745}
1746
05b308e1
BR		 1747/**
1748 * mv_port_stop - Port specific cleanup/stop routine.
1749 * @ap: ATA channel to manipulate
1750 *
1751 * Stop DMA, cleanup port memory.
1752 *
1753 * LOCKING:
cca3974e 1754 * This routine uses the host lock to protect the DMA stop.
05b308e1 1755 */
31961943
BR		 1756static void mv_port_stop(struct ata_port *ap)
1757{
933cb8e5
ML		 1758 unsigned long flags;
1759
1760 spin_lock_irqsave(ap->lock, flags);
e12bef50 1761 mv_stop_edma(ap);
88e675e1 1762 mv_enable_port_irqs(ap, 0);
933cb8e5 1763 spin_unlock_irqrestore(ap->lock, flags);
da2fa9ba 1764 mv_port_free_dma_mem(ap);
31961943
BR		 1765}
1766
05b308e1
BR		 1767/**
1768 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1769 * @qc: queued command whose SG list to source from
1770 *
1771 * Populate the SG list and mark the last entry.
1772 *
1773 * LOCKING:
1774 * Inherited from caller.
1775 */
6c08772e 1776static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1777{
1778 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1779 struct scatterlist *sg;
3be6cbd7 1780 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1781 unsigned int si;
31961943 1782
eb73d558 1783 mv_sg = pp->sg_tbl[qc->tag];
ff2aeb1e 1784 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1785 dma_addr_t addr = sg_dma_address(sg);
1786 u32 sg_len = sg_dma_len(sg);
22374677 1787
4007b493
OJ		 1788 while (sg_len) {
1789 u32 offset = addr & 0xffff;
1790 u32 len = sg_len;
22374677 1791
32cd11a6 1792 if (offset + len > 0x10000)
4007b493
OJ		 1793 len = 0x10000 - offset;
1794
1795 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1796 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1797 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
32cd11a6 1798 mv_sg->reserved = 0;
4007b493
OJ		 1799
1800 sg_len -= len;
1801 addr += len;
1802
3be6cbd7 1803 last_sg = mv_sg;
4007b493 1804 mv_sg++;
4007b493 1805 }
31961943 1806 }
3be6cbd7
JG		 1807
1808 if (likely(last_sg))
1809 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
32cd11a6 1810 mb(); /* ensure data structure is visible to the chipset */
31961943
BR		 1811}
1812
5796d1c4 1813static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1814{
559eedad 1815 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1816 (last ? CRQB_CMD_LAST : 0);
559eedad 1817 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1818}
1819
da14265e
ML		 1820/**
1821 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1822 * @ap: Port associated with this ATA transaction.
1823 *
1824 * We need this only for ATAPI bmdma transactions,
1825 * as otherwise we experience spurious interrupts
1826 * after libata-sff handles the bmdma interrupts.
1827 */
1828static void mv_sff_irq_clear(struct ata_port *ap)
1829{
1830 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1831}
1832
1833/**
1834 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1835 * @qc: queued command to check for chipset/DMA compatibility.
1836 *
1837 * The bmdma engines cannot handle speculative data sizes
1838 * (bytecount under/over flow). So only allow DMA for
1839 * data transfer commands with known data sizes.
1840 *
1841 * LOCKING:
1842 * Inherited from caller.
1843 */
1844static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1845{
1846 struct scsi_cmnd *scmd = qc->scsicmd;
1847
1848 if (scmd) {
1849 switch (scmd->cmnd[0]) {
1850 case READ_6:
1851 case READ_10:
1852 case READ_12:
1853 case WRITE_6:
1854 case WRITE_10:
1855 case WRITE_12:
1856 case GPCMD_READ_CD:
1857 case GPCMD_SEND_DVD_STRUCTURE:
1858 case GPCMD_SEND_CUE_SHEET:
1859 return 0; /* DMA is safe */
1860 }
1861 }
1862 return -EOPNOTSUPP; /* use PIO instead */
1863}
1864
1865/**
1866 * mv_bmdma_setup - Set up BMDMA transaction
1867 * @qc: queued command to prepare DMA for.
1868 *
1869 * LOCKING:
1870 * Inherited from caller.
1871 */
1872static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1873{
1874 struct ata_port *ap = qc->ap;
1875 void __iomem *port_mmio = mv_ap_base(ap);
1876 struct mv_port_priv *pp = ap->private_data;
1877
1878 mv_fill_sg(qc);
1879
1880 /* clear all DMA cmd bits */
cae5a29d 1881 writel(0, port_mmio + BMDMA_CMD);
da14265e
ML		 1882
1883 /* load PRD table addr. */
1884 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
cae5a29d 1885 port_mmio + BMDMA_PRD_HIGH);
da14265e 1886 writelfl(pp->sg_tbl_dma[qc->tag],
cae5a29d 1887 port_mmio + BMDMA_PRD_LOW);
da14265e
ML		 1888
1889 /* issue r/w command */
1890 ap->ops->sff_exec_command(ap, &qc->tf);
1891}
1892
1893/**
1894 * mv_bmdma_start - Start a BMDMA transaction
1895 * @qc: queued command to start DMA on.
1896 *
1897 * LOCKING:
1898 * Inherited from caller.
1899 */
1900static void mv_bmdma_start(struct ata_queued_cmd *qc)
1901{
1902 struct ata_port *ap = qc->ap;
1903 void __iomem *port_mmio = mv_ap_base(ap);
1904 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1905 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1906
1907 /* start host DMA transaction */
cae5a29d 1908 writelfl(cmd, port_mmio + BMDMA_CMD);
da14265e
ML		 1909}
1910
1911/**
1912 * mv_bmdma_stop - Stop BMDMA transfer
1913 * @qc: queued command to stop DMA on.
1914 *
1915 * Clears the ATA_DMA_START flag in the bmdma control register
1916 *
1917 * LOCKING:
1918 * Inherited from caller.
1919 */
44b73380 1920static void mv_bmdma_stop_ap(struct ata_port *ap)
da14265e 1921{
da14265e
ML		 1922 void __iomem *port_mmio = mv_ap_base(ap);
1923 u32 cmd;
1924
1925 /* clear start/stop bit */
cae5a29d 1926 cmd = readl(port_mmio + BMDMA_CMD);
44b73380
ML		 1927 if (cmd & ATA_DMA_START) {
1928 cmd &= ~ATA_DMA_START;
1929 writelfl(cmd, port_mmio + BMDMA_CMD);
1930
1931 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1932 ata_sff_dma_pause(ap);
1933 }
1934}
da14265e 1935
44b73380
ML		 1936static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1937{
1938 mv_bmdma_stop_ap(qc->ap);
da14265e
ML		 1939}
1940
1941/**
1942 * mv_bmdma_status - Read BMDMA status
1943 * @ap: port for which to retrieve DMA status.
1944 *
1945 * Read and return equivalent of the sff BMDMA status register.
1946 *
1947 * LOCKING:
1948 * Inherited from caller.
1949 */
1950static u8 mv_bmdma_status(struct ata_port *ap)
1951{
1952 void __iomem *port_mmio = mv_ap_base(ap);
1953 u32 reg, status;
1954
1955 /*
1956 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1957 * and the ATA_DMA_INTR bit doesn't exist.
1958 */
cae5a29d 1959 reg = readl(port_mmio + BMDMA_STATUS);
da14265e
ML		 1960 if (reg & ATA_DMA_ACTIVE)
1961 status = ATA_DMA_ACTIVE;
44b73380 1962 else if (reg & ATA_DMA_ERR)
da14265e 1963 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
44b73380
ML		 1964 else {
1965 /*
1966 * Just because DMA_ACTIVE is 0 (DMA completed),
1967 * this does _not_ mean the device is "done".
1968 * So we should not yet be signalling ATA_DMA_INTR
1969 * in some cases. Eg. DSM/TRIM, and perhaps others.
1970 */
1971 mv_bmdma_stop_ap(ap);
1972 if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY)
1973 status = 0;
1974 else
1975 status = ATA_DMA_INTR;
1976 }
da14265e
ML		 1977 return status;
1978}
1979
299b3f8d
ML		 1980static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
1981{
1982 struct ata_taskfile *tf = &qc->tf;
1983 /*
1984 * Workaround for 88SX60x1 FEr SATA#24.
1985 *
1986 * Chip may corrupt WRITEs if multi_count >= 4kB.
1987 * Note that READs are unaffected.
1988 *
1989 * It's not clear if this errata really means "4K bytes",
1990 * or if it always happens for multi_count > 7
1991 * regardless of device sector_size.
1992 *
1993 * So, for safety, any write with multi_count > 7
1994 * gets converted here into a regular PIO write instead:
1995 */
1996 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {
1997 if (qc->dev->multi_count > 7) {
1998 switch (tf->command) {
1999 case ATA_CMD_WRITE_MULTI:
2000 tf->command = ATA_CMD_PIO_WRITE;
2001 break;
2002 case ATA_CMD_WRITE_MULTI_FUA_EXT:
2003 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
2004 /* fall through */
2005 case ATA_CMD_WRITE_MULTI_EXT:
2006 tf->command = ATA_CMD_PIO_WRITE_EXT;
2007 break;
2008 }
2009 }
2010 }
2011}
2012
05b308e1
BR		 2013/**
2014 * mv_qc_prep - Host specific command preparation.
2015 * @qc: queued command to prepare
2016 *
2017 * This routine simply redirects to the general purpose routine
2018 * if command is not DMA. Else, it handles prep of the CRQB
2019 * (command request block), does some sanity checking, and calls
2020 * the SG load routine.
2021 *
2022 * LOCKING:
2023 * Inherited from caller.
2024 */
31961943
BR		 2025static void mv_qc_prep(struct ata_queued_cmd *qc)
2026{
2027 struct ata_port *ap = qc->ap;
2028 struct mv_port_priv *pp = ap->private_data;
e1469874 2029 __le16 *cw;
8d2b450d 2030 struct ata_taskfile *tf = &qc->tf;
31961943 2031 u16 flags = 0;
a6432436 2032 unsigned in_index;
31961943 2033
299b3f8d
ML		 2034 switch (tf->protocol) {
2035 case ATA_PROT_DMA:
44b73380
ML		 2036 if (tf->command == ATA_CMD_DSM)
2037 return;
2038 /* fall-thru */
299b3f8d
ML		 2039 case ATA_PROT_NCQ:
2040 break; /* continue below */
2041 case ATA_PROT_PIO:
2042 mv_rw_multi_errata_sata24(qc);
31961943 2043 return;
299b3f8d
ML		 2044 default:
2045 return;
2046 }
20f733e7 2047
31961943
BR		 2048 /* Fill in command request block
2049 */
8d2b450d 2050 if (!(tf->flags & ATA_TFLAG_WRITE))
31961943 2051 flags |= CRQB_FLAG_READ;
beec7dbc 2052 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943 2053 flags |= qc->tag << CRQB_TAG_SHIFT;
e49856d8 2054 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
31961943 2055
bdd4ddde 2056 /* get current queue index from software */
fcfb1f77 2057 in_index = pp->req_idx;
a6432436
ML		 2058
2059 pp->crqb[in_index].sg_addr =
eb73d558 2060 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
a6432436 2061 pp->crqb[in_index].sg_addr_hi =
eb73d558 2062 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
a6432436 2063 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 2064
a6432436 2065 cw = &pp->crqb[in_index].ata_cmd[0];
31961943 2066
25985edc 2067 /* Sadly, the CRQB cannot accommodate all registers--there are
31961943
BR		 2068 * only 11 bytes...so we must pick and choose required
2069 * registers based on the command. So, we drop feature and
2070 * hob_feature for [RW] DMA commands, but they are needed for
cd12e1f7
ML		 2071 * NCQ. NCQ will drop hob_nsect, which is not needed there
2072 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
20f733e7 2073 */
31961943
BR		 2074 switch (tf->command) {
2075 case ATA_CMD_READ:
2076 case ATA_CMD_READ_EXT:
2077 case ATA_CMD_WRITE:
2078 case ATA_CMD_WRITE_EXT:
c15d85c8 2079 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 2080 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
2081 break;
31961943
BR		 2082 case ATA_CMD_FPDMA_READ:
2083 case ATA_CMD_FPDMA_WRITE:
8b260248 2084 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 2085 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
2086 break;
31961943
BR		 2087 default:
2088 /* The only other commands EDMA supports in non-queued and
2089 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
2090 * of which are defined/used by Linux. If we get here, this
2091 * driver needs work.
2092 *
2093 * FIXME: modify libata to give qc_prep a return value and
2094 * return error here.
2095 */
2096 BUG_ON(tf->command);
2097 break;
2098 }
2099 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
2100 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
2101 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
2102 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
2103 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
2104 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
2105 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
2106 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
2107 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
2108
e4e7b892
JG		 2109 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2110 return;
2111 mv_fill_sg(qc);
2112}
2113
2114/**
2115 * mv_qc_prep_iie - Host specific command preparation.
2116 * @qc: queued command to prepare
2117 *
2118 * This routine simply redirects to the general purpose routine
2119 * if command is not DMA. Else, it handles prep of the CRQB
2120 * (command request block), does some sanity checking, and calls
2121 * the SG load routine.
2122 *
2123 * LOCKING:
2124 * Inherited from caller.
2125 */
2126static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
2127{
2128 struct ata_port *ap = qc->ap;
2129 struct mv_port_priv *pp = ap->private_data;
2130 struct mv_crqb_iie *crqb;
8d2b450d 2131 struct ata_taskfile *tf = &qc->tf;
a6432436 2132 unsigned in_index;
e4e7b892
JG		 2133 u32 flags = 0;
2134
8d2b450d
ML		 2135 if ((tf->protocol != ATA_PROT_DMA) &&
2136 (tf->protocol != ATA_PROT_NCQ))
e4e7b892 2137 return;
44b73380
ML		 2138 if (tf->command == ATA_CMD_DSM)
2139 return; /* use bmdma for this */
e4e7b892 2140
e12bef50 2141 /* Fill in Gen IIE command request block */
8d2b450d 2142 if (!(tf->flags & ATA_TFLAG_WRITE))
e4e7b892
JG		 2143 flags |= CRQB_FLAG_READ;
2144
beec7dbc 2145 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 2146 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 2147 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e49856d8 2148 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
e4e7b892 2149
bdd4ddde 2150 /* get current queue index from software */
fcfb1f77 2151 in_index = pp->req_idx;
a6432436
ML		 2152
2153 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
eb73d558
ML		 2154 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2155 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
e4e7b892
JG		 2156 crqb->flags = cpu_to_le32(flags);
2157
e4e7b892
JG		 2158 crqb->ata_cmd[0] = cpu_to_le32(
2159 (tf->command << 16) |
2160 (tf->feature << 24)
2161 );
2162 crqb->ata_cmd[1] = cpu_to_le32(
2163 (tf->lbal << 0) |
2164 (tf->lbam << 8) |
2165 (tf->lbah << 16) |
2166 (tf->device << 24)
2167 );
2168 crqb->ata_cmd[2] = cpu_to_le32(
2169 (tf->hob_lbal << 0) |
2170 (tf->hob_lbam << 8) |
2171 (tf->hob_lbah << 16) |
2172 (tf->hob_feature << 24)
2173 );
2174 crqb->ata_cmd[3] = cpu_to_le32(
2175 (tf->nsect << 0) |
2176 (tf->hob_nsect << 8)
2177 );
2178
2179 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 2180 return;
31961943
BR		 2181 mv_fill_sg(qc);
2182}
2183
d16ab3f6
ML		 2184/**
2185 * mv_sff_check_status - fetch device status, if valid
2186 * @ap: ATA port to fetch status from
2187 *
2188 * When using command issue via mv_qc_issue_fis(),
2189 * the initial ATA_BUSY state does not show up in the
2190 * ATA status (shadow) register. This can confuse libata!
2191 *
2192 * So we have a hook here to fake ATA_BUSY for that situation,
2193 * until the first time a BUSY, DRQ, or ERR bit is seen.
2194 *
2195 * The rest of the time, it simply returns the ATA status register.
2196 */
2197static u8 mv_sff_check_status(struct ata_port *ap)
2198{
2199 u8 stat = ioread8(ap->ioaddr.status_addr);
2200 struct mv_port_priv *pp = ap->private_data;
2201
2202 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2203 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2204 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2205 else
2206 stat = ATA_BUSY;
2207 }
2208 return stat;
2209}
2210
70f8b79c
ML		 2211/**
2212 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2213 * @fis: fis to be sent
2214 * @nwords: number of 32-bit words in the fis
2215 */
2216static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2217{
2218 void __iomem *port_mmio = mv_ap_base(ap);
2219 u32 ifctl, old_ifctl, ifstat;
2220 int i, timeout = 200, final_word = nwords - 1;
2221
2222 /* Initiate FIS transmission mode */
cae5a29d 2223 old_ifctl = readl(port_mmio + SATA_IFCTL);
70f8b79c 2224 ifctl = 0x100 | (old_ifctl & 0xf);
cae5a29d 2225 writelfl(ifctl, port_mmio + SATA_IFCTL);
70f8b79c
ML		 2226
2227 /* Send all words of the FIS except for the final word */
2228 for (i = 0; i < final_word; ++i)
cae5a29d 2229 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
70f8b79c
ML		 2230
2231 /* Flag end-of-transmission, and then send the final word */
cae5a29d
ML		 2232 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
2233 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
70f8b79c
ML		 2234
2235 /*
2236 * Wait for FIS transmission to complete.
2237 * This typically takes just a single iteration.
2238 */
2239 do {
cae5a29d 2240 ifstat = readl(port_mmio + SATA_IFSTAT);
70f8b79c
ML		 2241 } while (!(ifstat & 0x1000) && --timeout);
2242
2243 /* Restore original port configuration */
cae5a29d 2244 writelfl(old_ifctl, port_mmio + SATA_IFCTL);
70f8b79c
ML		 2245
2246 /* See if it worked */
2247 if ((ifstat & 0x3000) != 0x1000) {
a9a79dfe
JP		 2248 ata_port_warn(ap, "%s transmission error, ifstat=%08x\n",
2249 __func__, ifstat);
70f8b79c
ML		 2250 return AC_ERR_OTHER;
2251 }
2252 return 0;
2253}
2254
2255/**
2256 * mv_qc_issue_fis - Issue a command directly as a FIS
2257 * @qc: queued command to start
2258 *
2259 * Note that the ATA shadow registers are not updated
2260 * after command issue, so the device will appear "READY"
2261 * if polled, even while it is BUSY processing the command.
2262 *
2263 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2264 *
2265 * Note: we don't get updated shadow regs on *completion*
2266 * of non-data commands. So avoid sending them via this function,
2267 * as they will appear to have completed immediately.
2268 *
2269 * GEN_IIE has special registers that we could get the result tf from,
2270 * but earlier chipsets do not. For now, we ignore those registers.
2271 */
2272static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2273{
2274 struct ata_port *ap = qc->ap;
2275 struct mv_port_priv *pp = ap->private_data;
2276 struct ata_link *link = qc->dev->link;
2277 u32 fis[5];
2278 int err = 0;
2279
2280 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
4c4a90fd 2281 err = mv_send_fis(ap, fis, ARRAY_SIZE(fis));
70f8b79c
ML		 2282 if (err)
2283 return err;
2284
2285 switch (qc->tf.protocol) {
2286 case ATAPI_PROT_PIO:
2287 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2288 /* fall through */
2289 case ATAPI_PROT_NODATA:
2290 ap->hsm_task_state = HSM_ST_FIRST;
2291 break;
2292 case ATA_PROT_PIO:
2293 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2294 if (qc->tf.flags & ATA_TFLAG_WRITE)
2295 ap->hsm_task_state = HSM_ST_FIRST;
2296 else
2297 ap->hsm_task_state = HSM_ST;
2298 break;
2299 default:
2300 ap->hsm_task_state = HSM_ST_LAST;
2301 break;
2302 }
2303
2304 if (qc->tf.flags & ATA_TFLAG_POLLING)
ea3c6450 2305 ata_sff_queue_pio_task(link, 0);
70f8b79c
ML		 2306 return 0;
2307}
2308
05b308e1
BR		 2309/**
2310 * mv_qc_issue - Initiate a command to the host
2311 * @qc: queued command to start
2312 *
2313 * This routine simply redirects to the general purpose routine
2314 * if command is not DMA. Else, it sanity checks our local
2315 * caches of the request producer/consumer indices then enables
2316 * DMA and bumps the request producer index.
2317 *
2318 * LOCKING:
2319 * Inherited from caller.
2320 */
9a3d9eb0 2321static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 2322{
f48765cc 2323 static int limit_warnings = 10;
c5d3e45a
JG		 2324 struct ata_port *ap = qc->ap;
2325 void __iomem *port_mmio = mv_ap_base(ap);
2326 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 2327 u32 in_index;
42ed893d 2328 unsigned int port_irqs;
f48765cc 2329
d16ab3f6
ML		 2330 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2331
f48765cc
ML		 2332 switch (qc->tf.protocol) {
2333 case ATA_PROT_DMA:
44b73380
ML		 2334 if (qc->tf.command == ATA_CMD_DSM) {
2335 if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */
2336 return AC_ERR_OTHER;
2337 break; /* use bmdma for this */
2338 }
2339 /* fall thru */
f48765cc
ML		 2340 case ATA_PROT_NCQ:
2341 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2342 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2343 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2344
2345 /* Write the request in pointer to kick the EDMA to life */
2346 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
cae5a29d 2347 port_mmio + EDMA_REQ_Q_IN_PTR);
f48765cc 2348 return 0;
31961943 2349
f48765cc 2350 case ATA_PROT_PIO:
c6112bd8
ML		 2351 /*
2352 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2353 *
2354 * Someday, we might implement special polling workarounds
2355 * for these, but it all seems rather unnecessary since we
2356 * normally use only DMA for commands which transfer more
2357 * than a single block of data.
2358 *
2359 * Much of the time, this could just work regardless.
2360 * So for now, just log the incident, and allow the attempt.
2361 */
c7843e8f 2362 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
c6112bd8 2363 --limit_warnings;
a9a79dfe
JP		 2364 ata_link_warn(qc->dev->link, DRV_NAME
2365 ": attempting PIO w/multiple DRQ: "
2366 "this may fail due to h/w errata\n");
c6112bd8 2367 }
f48765cc 2368 /* drop through */
42ed893d 2369 case ATA_PROT_NODATA:
f48765cc 2370 case ATAPI_PROT_PIO:
42ed893d
ML		 2371 case ATAPI_PROT_NODATA:
2372 if (ap->flags & ATA_FLAG_PIO_POLLING)
2373 qc->tf.flags |= ATA_TFLAG_POLLING;
2374 break;
31961943 2375 }
42ed893d
ML		 2376
2377 if (qc->tf.flags & ATA_TFLAG_POLLING)
2378 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2379 else
2380 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2381
2382 /*
2383 * We're about to send a non-EDMA capable command to the
2384 * port. Turn off EDMA so there won't be problems accessing
2385 * shadow block, etc registers.
2386 */
2387 mv_stop_edma(ap);
2388 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2389 mv_pmp_select(ap, qc->dev->link->pmp);
70f8b79c
ML		 2390
2391 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2392 struct mv_host_priv *hpriv = ap->host->private_data;
2393 /*
2394 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
40f21b11 2395 *
70f8b79c
ML		 2396 * After any NCQ error, the READ_LOG_EXT command
2397 * from libata-eh *must* use mv_qc_issue_fis().
2398 * Otherwise it might fail, due to chip errata.
2399 *
2400 * Rather than special-case it, we'll just *always*
2401 * use this method here for READ_LOG_EXT, making for
2402 * easier testing.
2403 */
2404 if (IS_GEN_II(hpriv))
2405 return mv_qc_issue_fis(qc);
2406 }
360ff783 2407 return ata_bmdma_qc_issue(qc);
31961943
BR		 2408}
2409
8f767f8a
ML		 2410static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2411{
2412 struct mv_port_priv *pp = ap->private_data;
2413 struct ata_queued_cmd *qc;
2414
2415 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2416 return NULL;
2417 qc = ata_qc_from_tag(ap, ap->link.active_tag);
3e4ec344
TH		 2418 if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING))
2419 return qc;
2420 return NULL;
8f767f8a
ML		 2421}
2422
29d187bb
ML		 2423static void mv_pmp_error_handler(struct ata_port *ap)
2424{
2425 unsigned int pmp, pmp_map;
2426 struct mv_port_priv *pp = ap->private_data;
2427
2428 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2429 /*
2430 * Perform NCQ error analysis on failed PMPs
2431 * before we freeze the port entirely.
2432 *
2433 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2434 */
2435 pmp_map = pp->delayed_eh_pmp_map;
2436 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2437 for (pmp = 0; pmp_map != 0; pmp++) {
2438 unsigned int this_pmp = (1 << pmp);
2439 if (pmp_map & this_pmp) {
2440 struct ata_link *link = &ap->pmp_link[pmp];
2441 pmp_map &= ~this_pmp;
2442 ata_eh_analyze_ncq_error(link);
2443 }
2444 }
2445 ata_port_freeze(ap);
2446 }
2447 sata_pmp_error_handler(ap);
2448}
2449
4c299ca3
ML		 2450static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2451{
2452 void __iomem *port_mmio = mv_ap_base(ap);
2453
cae5a29d 2454 return readl(port_mmio + SATA_TESTCTL) >> 16;
4c299ca3
ML		 2455}
2456
4c299ca3
ML		 2457static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2458{
2459 struct ata_eh_info *ehi;
2460 unsigned int pmp;
2461
2462 /*
2463 * Initialize EH info for PMPs which saw device errors
2464 */
2465 ehi = &ap->link.eh_info;
2466 for (pmp = 0; pmp_map != 0; pmp++) {
2467 unsigned int this_pmp = (1 << pmp);
2468 if (pmp_map & this_pmp) {
2469 struct ata_link *link = &ap->pmp_link[pmp];
2470
2471 pmp_map &= ~this_pmp;
2472 ehi = &link->eh_info;
2473 ata_ehi_clear_desc(ehi);
2474 ata_ehi_push_desc(ehi, "dev err");
2475 ehi->err_mask |= AC_ERR_DEV;
2476 ehi->action |= ATA_EH_RESET;
2477 ata_link_abort(link);
2478 }
2479 }
2480}
2481
06aaca3f
ML		 2482static int mv_req_q_empty(struct ata_port *ap)
2483{
2484 void __iomem *port_mmio = mv_ap_base(ap);
2485 u32 in_ptr, out_ptr;
2486
cae5a29d 2487 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
06aaca3f 2488 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
cae5a29d 2489 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
06aaca3f
ML		 2490 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2491 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2492}
2493
4c299ca3
ML		 2494static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2495{
2496 struct mv_port_priv *pp = ap->private_data;
2497 int failed_links;
2498 unsigned int old_map, new_map;
2499
2500 /*
2501 * Device error during FBS+NCQ operation:
2502 *
2503 * Set a port flag to prevent further I/O being enqueued.
2504 * Leave the EDMA running to drain outstanding commands from this port.
2505 * Perform the post-mortem/EH only when all responses are complete.
2506 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2507 */
2508 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2509 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2510 pp->delayed_eh_pmp_map = 0;
2511 }
2512 old_map = pp->delayed_eh_pmp_map;
2513 new_map = old_map | mv_get_err_pmp_map(ap);
2514
2515 if (old_map != new_map) {
2516 pp->delayed_eh_pmp_map = new_map;
2517 mv_pmp_eh_prep(ap, new_map & ~old_map);
2518 }
c46938cc 2519 failed_links = hweight16(new_map);
4c299ca3 2520
a9a79dfe
JP		 2521 ata_port_info(ap,
2522 "%s: pmp_map=%04x qc_map=%04x failed_links=%d nr_active_links=%d\n",
2523 __func__, pp->delayed_eh_pmp_map,
2524 ap->qc_active, failed_links,
2525 ap->nr_active_links);
4c299ca3 2526
06aaca3f 2527 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
4c299ca3
ML		 2528 mv_process_crpb_entries(ap, pp);
2529 mv_stop_edma(ap);
2530 mv_eh_freeze(ap);
a9a79dfe 2531 ata_port_info(ap, "%s: done\n", __func__);
4c299ca3
ML		 2532 return 1; /* handled */
2533 }
a9a79dfe 2534 ata_port_info(ap, "%s: waiting\n", __func__);
4c299ca3
ML		 2535 return 1; /* handled */
2536}
2537
2538static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2539{
2540 /*
2541 * Possible future enhancement:
2542 *
2543 * FBS+non-NCQ operation is not yet implemented.
2544 * See related notes in mv_edma_cfg().
2545 *
2546 * Device error during FBS+non-NCQ operation:
2547 *
2548 * We need to snapshot the shadow registers for each failed command.
2549 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2550 */
2551 return 0; /* not handled */
2552}
2553
2554static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2555{
2556 struct mv_port_priv *pp = ap->private_data;
2557
2558 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2559 return 0; /* EDMA was not active: not handled */
2560 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2561 return 0; /* FBS was not active: not handled */
2562
2563 if (!(edma_err_cause & EDMA_ERR_DEV))
2564 return 0; /* non DEV error: not handled */
2565 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2566 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2567 return 0; /* other problems: not handled */
2568
2569 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2570 /*
2571 * EDMA should NOT have self-disabled for this case.
2572 * If it did, then something is wrong elsewhere,
2573 * and we cannot handle it here.
2574 */
2575 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
a9a79dfe
JP		 2576 ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n",
2577 __func__, edma_err_cause, pp->pp_flags);
4c299ca3
ML		 2578 return 0; /* not handled */
2579 }
2580 return mv_handle_fbs_ncq_dev_err(ap);
2581 } else {
2582 /*
2583 * EDMA should have self-disabled for this case.
2584 * If it did not, then something is wrong elsewhere,
2585 * and we cannot handle it here.
2586 */
2587 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
a9a79dfe
JP		 2588 ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n",
2589 __func__, edma_err_cause, pp->pp_flags);
4c299ca3
ML		 2590 return 0; /* not handled */
2591 }
2592 return mv_handle_fbs_non_ncq_dev_err(ap);
2593 }
2594 return 0; /* not handled */
2595}
2596
a9010329 2597static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
8f767f8a 2598{
8f767f8a 2599 struct ata_eh_info *ehi = &ap->link.eh_info;
a9010329 2600 char *when = "idle";
8f767f8a 2601
8f767f8a 2602 ata_ehi_clear_desc(ehi);
3e4ec344 2603 if (edma_was_enabled) {
a9010329 2604 when = "EDMA enabled";
8f767f8a
ML		 2605 } else {
2606 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2607 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
a9010329 2608 when = "polling";
8f767f8a 2609 }
a9010329 2610 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
8f767f8a
ML		 2611 ehi->err_mask |= AC_ERR_OTHER;
2612 ehi->action |= ATA_EH_RESET;
2613 ata_port_freeze(ap);
2614}
2615
05b308e1
BR		 2616/**
2617 * mv_err_intr - Handle error interrupts on the port
2618 * @ap: ATA channel to manipulate
2619 *
8d07379d
ML		 2620 * Most cases require a full reset of the chip's state machine,
2621 * which also performs a COMRESET.
2622 * Also, if the port disabled DMA, update our cached copy to match.
05b308e1
BR		 2623 *
2624 * LOCKING:
2625 * Inherited from caller.
2626 */
37b9046a 2627static void mv_err_intr(struct ata_port *ap)
31961943
BR		 2628{
2629 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde 2630 u32 edma_err_cause, eh_freeze_mask, serr = 0;
e4006077 2631 u32 fis_cause = 0;
bdd4ddde
JG		 2632 struct mv_port_priv *pp = ap->private_data;
2633 struct mv_host_priv *hpriv = ap->host->private_data;
bdd4ddde 2634 unsigned int action = 0, err_mask = 0;
9af5c9c9 2635 struct ata_eh_info *ehi = &ap->link.eh_info;
37b9046a
ML		 2636 struct ata_queued_cmd *qc;
2637 int abort = 0;
20f733e7 2638
8d07379d 2639 /*
37b9046a 2640 * Read and clear the SError and err_cause bits.
e4006077
ML		 2641 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2642 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
8d07379d 2643 */
37b9046a
ML		 2644 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2645 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2646
cae5a29d 2647 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
e4006077 2648 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
cae5a29d
ML		 2649 fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
2650 writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
e4006077 2651 }
cae5a29d 2652 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
bdd4ddde 2653
4c299ca3
ML		 2654 if (edma_err_cause & EDMA_ERR_DEV) {
2655 /*
2656 * Device errors during FIS-based switching operation
2657 * require special handling.
2658 */
2659 if (mv_handle_dev_err(ap, edma_err_cause))
2660 return;
2661 }
2662
37b9046a
ML		 2663 qc = mv_get_active_qc(ap);
2664 ata_ehi_clear_desc(ehi);
2665 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2666 edma_err_cause, pp->pp_flags);
e4006077 2667
c443c500 2668 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
e4006077 2669 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
cae5a29d 2670 if (fis_cause & FIS_IRQ_CAUSE_AN) {
c443c500
ML		 2671 u32 ec = edma_err_cause &
2672 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2673 sata_async_notification(ap);
2674 if (!ec)
2675 return; /* Just an AN; no need for the nukes */
2676 ata_ehi_push_desc(ehi, "SDB notify");
2677 }
2678 }
bdd4ddde 2679 /*
352fab70 2680 * All generations share these EDMA error cause bits:
bdd4ddde 2681 */
37b9046a 2682 if (edma_err_cause & EDMA_ERR_DEV) {
bdd4ddde 2683 err_mask |= AC_ERR_DEV;
37b9046a
ML		 2684 action |= ATA_EH_RESET;
2685 ata_ehi_push_desc(ehi, "dev error");
2686 }
bdd4ddde 2687 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 2688 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 2689 EDMA_ERR_INTRL_PAR)) {
2690 err_mask |= AC_ERR_ATA_BUS;
cf480626 2691 action |= ATA_EH_RESET;
b64bbc39 2692 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 2693 }
2694 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2695 ata_ehi_hotplugged(ehi);
2696 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 2697 "dev disconnect" : "dev connect");
cf480626 2698 action |= ATA_EH_RESET;
bdd4ddde
JG		 2699 }
2700
352fab70
ML		 2701 /*
2702 * Gen-I has a different SELF_DIS bit,
2703 * different FREEZE bits, and no SERR bit:
2704 */
ee9ccdf7 2705 if (IS_GEN_I(hpriv)) {
bdd4ddde 2706 eh_freeze_mask = EDMA_EH_FREEZE_5;
bdd4ddde 2707 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
bdd4ddde 2708 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 2709 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 2710 }
2711 } else {
2712 eh_freeze_mask = EDMA_EH_FREEZE;
bdd4ddde 2713 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
bdd4ddde 2714 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 2715 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde 2716 }
bdd4ddde 2717 if (edma_err_cause & EDMA_ERR_SERR) {
8d07379d
ML		 2718 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2719 err_mask |= AC_ERR_ATA_BUS;
cf480626 2720 action |= ATA_EH_RESET;
bdd4ddde 2721 }
afb0edd9 2722 }
20f733e7 2723
bdd4ddde
JG		 2724 if (!err_mask) {
2725 err_mask = AC_ERR_OTHER;
cf480626 2726 action |= ATA_EH_RESET;
bdd4ddde
JG		 2727 }
2728
2729 ehi->serror |= serr;
2730 ehi->action |= action;
2731
2732 if (qc)
2733 qc->err_mask |= err_mask;
2734 else
2735 ehi->err_mask |= err_mask;
2736
37b9046a
ML		 2737 if (err_mask == AC_ERR_DEV) {
2738 /*
2739 * Cannot do ata_port_freeze() here,
2740 * because it would kill PIO access,
2741 * which is needed for further diagnosis.
2742 */
2743 mv_eh_freeze(ap);
2744 abort = 1;
2745 } else if (edma_err_cause & eh_freeze_mask) {
2746 /*
2747 * Note to self: ata_port_freeze() calls ata_port_abort()
2748 */
bdd4ddde 2749 ata_port_freeze(ap);
37b9046a
ML		 2750 } else {
2751 abort = 1;
2752 }
2753
2754 if (abort) {
2755 if (qc)
2756 ata_link_abort(qc->dev->link);
2757 else
2758 ata_port_abort(ap);
2759 }
bdd4ddde
JG		 2760}
2761
1aadf5c3 2762static bool mv_process_crpb_response(struct ata_port *ap,
fcfb1f77
ML		 2763 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2764{
752e386c
TH		 2765 u8 ata_status;
2766 u16 edma_status = le16_to_cpu(response->flags);
752e386c
TH		 2767
2768 /*
2769 * edma_status from a response queue entry:
2770 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
2771 * MSB is saved ATA status from command completion.
2772 */
2773 if (!ncq_enabled) {
2774 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2775 if (err_cause) {
2776 /*
2777 * Error will be seen/handled by
2778 * mv_err_intr(). So do nothing at all here.
2779 */
1aadf5c3 2780 return false;
752e386c 2781 }
fcfb1f77 2782 }
752e386c
TH		 2783 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2784 if (!ac_err_mask(ata_status))
1aadf5c3 2785 return true;
752e386c 2786 /* else: leave it for mv_err_intr() */
1aadf5c3 2787 return false;
fcfb1f77
ML		 2788}
2789
2790static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
bdd4ddde
JG		 2791{
2792 void __iomem *port_mmio = mv_ap_base(ap);
2793 struct mv_host_priv *hpriv = ap->host->private_data;
fcfb1f77 2794 u32 in_index;
bdd4ddde 2795 bool work_done = false;
1aadf5c3 2796 u32 done_mask = 0;
fcfb1f77 2797 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
bdd4ddde 2798
fcfb1f77 2799 /* Get the hardware queue position index */
cae5a29d 2800 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
bdd4ddde
JG		 2801 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2802
fcfb1f77
ML		 2803 /* Process new responses from since the last time we looked */
2804 while (in_index != pp->resp_idx) {
6c1153e0 2805 unsigned int tag;
fcfb1f77 2806 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
bdd4ddde 2807
fcfb1f77 2808 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
bdd4ddde 2809
fcfb1f77
ML		 2810 if (IS_GEN_I(hpriv)) {
2811 /* 50xx: no NCQ, only one command active at a time */
9af5c9c9 2812 tag = ap->link.active_tag;
fcfb1f77
ML		 2813 } else {
2814 /* Gen II/IIE: get command tag from CRPB entry */
2815 tag = le16_to_cpu(response->id) & 0x1f;
bdd4ddde 2816 }
1aadf5c3
TH		 2817 if (mv_process_crpb_response(ap, response, tag, ncq_enabled))
2818 done_mask |= 1 << tag;
bdd4ddde 2819 work_done = true;
bdd4ddde
JG		 2820 }
2821
1aadf5c3
TH		 2822 if (work_done) {
2823 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
2824
2825 /* Update the software queue position index in hardware */
bdd4ddde 2826 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
fcfb1f77 2827 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
cae5a29d 2828 port_mmio + EDMA_RSP_Q_OUT_PTR);
1aadf5c3 2829 }
20f733e7
BR		 2830}
2831
a9010329
ML		 2832static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2833{
2834 struct mv_port_priv *pp;
2835 int edma_was_enabled;
2836
a9010329
ML		 2837 /*
2838 * Grab a snapshot of the EDMA_EN flag setting,
2839 * so that we have a consistent view for this port,
2840 * even if something we call of our routines changes it.
2841 */
2842 pp = ap->private_data;
2843 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2844 /*
2845 * Process completed CRPB response(s) before other events.
2846 */
2847 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2848 mv_process_crpb_entries(ap, pp);
4c299ca3
ML		 2849 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2850 mv_handle_fbs_ncq_dev_err(ap);
a9010329
ML		 2851 }
2852 /*
2853 * Handle chip-reported errors, or continue on to handle PIO.
2854 */
2855 if (unlikely(port_cause & ERR_IRQ)) {
2856 mv_err_intr(ap);
2857 } else if (!edma_was_enabled) {
2858 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2859 if (qc)
c3b28894 2860 ata_bmdma_port_intr(ap, qc);
a9010329
ML		 2861 else
2862 mv_unexpected_intr(ap, edma_was_enabled);
2863 }
2864}
2865
05b308e1
BR		 2866/**
2867 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 2868 * @host: host specific structure
7368f919 2869 * @main_irq_cause: Main interrupt cause register for the chip.
05b308e1
BR		 2870 *
2871 * LOCKING:
2872 * Inherited from caller.
2873 */
7368f919 2874static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
20f733e7 2875{
f351b2d6 2876 struct mv_host_priv *hpriv = host->private_data;
eabd5eb1 2877 void __iomem *mmio = hpriv->base, *hc_mmio;
a3718c1f 2878 unsigned int handled = 0, port;
20f733e7 2879
2b748a0a
ML		 2880 /* If asserted, clear the "all ports" IRQ coalescing bit */
2881 if (main_irq_cause & ALL_PORTS_COAL_DONE)
cae5a29d 2882 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
2b748a0a 2883
a3718c1f 2884 for (port = 0; port < hpriv->n_ports; port++) {
cca3974e 2885 struct ata_port *ap = host->ports[port];
eabd5eb1
ML		 2886 unsigned int p, shift, hardport, port_cause;
2887
a3718c1f 2888 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
a3718c1f 2889 /*
eabd5eb1
ML		 2890 * Each hc within the host has its own hc_irq_cause register,
2891 * where the interrupting ports bits get ack'd.
a3718c1f 2892 */
eabd5eb1
ML		 2893 if (hardport == 0) { /* first port on this hc ? */
2894 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2895 u32 port_mask, ack_irqs;
2896 /*
2897 * Skip this entire hc if nothing pending for any ports
2898 */
2899 if (!hc_cause) {
2900 port += MV_PORTS_PER_HC - 1;
2901 continue;
2902 }
2903 /*
2904 * We don't need/want to read the hc_irq_cause register,
2905 * because doing so hurts performance, and
2906 * main_irq_cause already gives us everything we need.
2907 *
2908 * But we do have to *write* to the hc_irq_cause to ack
2909 * the ports that we are handling this time through.
2910 *
2911 * This requires that we create a bitmap for those
2912 * ports which interrupted us, and use that bitmap
2913 * to ack (only) those ports via hc_irq_cause.
2914 */
2915 ack_irqs = 0;
2b748a0a
ML		 2916 if (hc_cause & PORTS_0_3_COAL_DONE)
2917 ack_irqs = HC_COAL_IRQ;
eabd5eb1
ML		 2918 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2919 if ((port + p) >= hpriv->n_ports)
2920 break;
2921 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2922 if (hc_cause & port_mask)
2923 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2924 }
a3718c1f 2925 hc_mmio = mv_hc_base_from_port(mmio, port);
cae5a29d 2926 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
a3718c1f
ML		 2927 handled = 1;
2928 }
8f767f8a 2929 /*
a9010329 2930 * Handle interrupts signalled for this port:
8f767f8a 2931 */
a9010329
ML		 2932 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2933 if (port_cause)
2934 mv_port_intr(ap, port_cause);
20f733e7 2935 }
a3718c1f 2936 return handled;
20f733e7
BR		 2937}
2938
a3718c1f 2939static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
bdd4ddde 2940{
02a121da 2941 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 2942 struct ata_port *ap;
2943 struct ata_queued_cmd *qc;
2944 struct ata_eh_info *ehi;
2945 unsigned int i, err_mask, printed = 0;
2946 u32 err_cause;
2947
cae5a29d 2948 err_cause = readl(mmio + hpriv->irq_cause_offset);
bdd4ddde 2949
a44fec1f 2950 dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause);
bdd4ddde
JG		 2951
2952 DPRINTK("All regs @ PCI error\n");
2953 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2954
cae5a29d 2955 writelfl(0, mmio + hpriv->irq_cause_offset);
bdd4ddde
JG		 2956
2957 for (i = 0; i < host->n_ports; i++) {
2958 ap = host->ports[i];
936fd732 2959 if (!ata_link_offline(&ap->link)) {
9af5c9c9 2960 ehi = &ap->link.eh_info;
bdd4ddde
JG		 2961 ata_ehi_clear_desc(ehi);
2962 if (!printed++)
2963 ata_ehi_push_desc(ehi,
2964 "PCI err cause 0x%08x", err_cause);
2965 err_mask = AC_ERR_HOST_BUS;
cf480626 2966 ehi->action = ATA_EH_RESET;
9af5c9c9 2967 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 2968 if (qc)
2969 qc->err_mask |= err_mask;
2970 else
2971 ehi->err_mask |= err_mask;
2972
2973 ata_port_freeze(ap);
2974 }
2975 }
a3718c1f 2976 return 1; /* handled */
bdd4ddde
JG		 2977}
2978
05b308e1 2979/**
c5d3e45a 2980 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 2981 * @irq: unused
2982 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 2983 *
2984 * Read the read only register to determine if any host
2985 * controllers have pending interrupts. If so, call lower level
2986 * routine to handle. Also check for PCI errors which are only
2987 * reported here.
2988 *
8b260248 2989 * LOCKING:
cca3974e 2990 * This routine holds the host lock while processing pending
05b308e1
BR		 2991 * interrupts.
2992 */
7d12e780 2993static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 2994{
cca3974e 2995 struct ata_host *host = dev_instance;
f351b2d6 2996 struct mv_host_priv *hpriv = host->private_data;
a3718c1f 2997 unsigned int handled = 0;
6d3c30ef 2998 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
96e2c487 2999 u32 main_irq_cause, pending_irqs;
20f733e7 3000
646a4da5 3001 spin_lock(&host->lock);
6d3c30ef
ML		 3002
3003 /* for MSI: block new interrupts while in here */
3004 if (using_msi)
2b748a0a 3005 mv_write_main_irq_mask(0, hpriv);
6d3c30ef 3006
7368f919 3007 main_irq_cause = readl(hpriv->main_irq_cause_addr);
96e2c487 3008 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
352fab70
ML		 3009 /*
3010 * Deal with cases where we either have nothing pending, or have read
3011 * a bogus register value which can indicate HW removal or PCI fault.
20f733e7 3012 */
a44253d2 3013 if (pending_irqs && main_irq_cause != 0xffffffffU) {
1f398472 3014 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
a3718c1f
ML		 3015 handled = mv_pci_error(host, hpriv->base);
3016 else
a44253d2 3017 handled = mv_host_intr(host, pending_irqs);
bdd4ddde 3018 }
6d3c30ef
ML		 3019
3020 /* for MSI: unmask; interrupt cause bits will retrigger now */
3021 if (using_msi)
2b748a0a 3022 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
6d3c30ef 3023
9d51af7b
ML		 3024 spin_unlock(&host->lock);
3025
20f733e7
BR		 3026 return IRQ_RETVAL(handled);
3027}
3028
c9d39130
JG		 3029static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
3030{
3031 unsigned int ofs;
3032
3033 switch (sc_reg_in) {
3034 case SCR_STATUS:
3035 case SCR_ERROR:
3036 case SCR_CONTROL:
3037 ofs = sc_reg_in * sizeof(u32);
3038 break;
3039 default:
3040 ofs = 0xffffffffU;
3041 break;
3042 }
3043 return ofs;
3044}
3045
82ef04fb 3046static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
c9d39130 3047{
82ef04fb 3048 struct mv_host_priv *hpriv = link->ap->host->private_data;
f351b2d6 3049 void __iomem *mmio = hpriv->base;
82ef04fb 3050 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
c9d39130
JG		 3051 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3052
da3dbb17
TH		 3053 if (ofs != 0xffffffffU) {
3054 *val = readl(addr + ofs);
3055 return 0;
3056 } else
3057 return -EINVAL;
c9d39130
JG		 3058}
3059
82ef04fb 3060static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
c9d39130 3061{
82ef04fb 3062 struct mv_host_priv *hpriv = link->ap->host->private_data;
f351b2d6 3063 void __iomem *mmio = hpriv->base;
82ef04fb 3064 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
c9d39130
JG		 3065 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3066
da3dbb17 3067 if (ofs != 0xffffffffU) {
0d5ff566 3068 writelfl(val, addr + ofs);
da3dbb17
TH		 3069 return 0;
3070 } else
3071 return -EINVAL;
c9d39130
JG		 3072}
3073
7bb3c529 3074static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
522479fb 3075{
7bb3c529 3076 struct pci_dev *pdev = to_pci_dev(host->dev);
522479fb
JG		 3077 int early_5080;
3078
44c10138 3079 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 3080
3081 if (!early_5080) {
3082 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3083 tmp |= (1 << 0);
3084 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3085 }
3086
7bb3c529 3087 mv_reset_pci_bus(host, mmio);
522479fb
JG		 3088}
3089
3090static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3091{
cae5a29d 3092 writel(0x0fcfffff, mmio + FLASH_CTL);
522479fb
JG		 3093}
3094
47c2b677 3095static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 3096 void __iomem *mmio)
3097{
c9d39130
JG		 3098 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
3099 u32 tmp;
3100
3101 tmp = readl(phy_mmio + MV5_PHY_MODE);
3102
3103 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
3104 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 3105}
3106
47c2b677 3107static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 3108{
522479fb
JG		 3109 u32 tmp;
3110
cae5a29d 3111 writel(0, mmio + GPIO_PORT_CTL);
522479fb
JG		 3112
3113 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
3114
3115 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3116 tmp |= ~(1 << 0);
3117 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 3118}
3119
2a47ce06
JG		 3120static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3121 unsigned int port)
bca1c4eb 3122{
c9d39130
JG		 3123 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
3124 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
3125 u32 tmp;
3126 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
3127
3128 if (fix_apm_sq) {
cae5a29d 3129 tmp = readl(phy_mmio + MV5_LTMODE);
c9d39130 3130 tmp |= (1 << 19);
cae5a29d 3131 writel(tmp, phy_mmio + MV5_LTMODE);
c9d39130 3132
cae5a29d 3133 tmp = readl(phy_mmio + MV5_PHY_CTL);
c9d39130
JG		 3134 tmp &= ~0x3;
3135 tmp |= 0x1;
cae5a29d 3136 writel(tmp, phy_mmio + MV5_PHY_CTL);
c9d39130
JG		 3137 }
3138
3139 tmp = readl(phy_mmio + MV5_PHY_MODE);
3140 tmp &= ~mask;
3141 tmp |= hpriv->signal[port].pre;
3142 tmp |= hpriv->signal[port].amps;
3143 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 3144}
3145
c9d39130
JG		 3146
3147#undef ZERO
3148#define ZERO(reg) writel(0, port_mmio + (reg))
3149static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
3150 unsigned int port)
3151{
3152 void __iomem *port_mmio = mv_port_base(mmio, port);
3153
e12bef50 3154 mv_reset_channel(hpriv, mmio, port);
c9d39130
JG		 3155
3156 ZERO(0x028); /* command */
cae5a29d 3157 writel(0x11f, port_mmio + EDMA_CFG);
c9d39130
JG		 3158 ZERO(0x004); /* timer */
3159 ZERO(0x008); /* irq err cause */
3160 ZERO(0x00c); /* irq err mask */
3161 ZERO(0x010); /* rq bah */
3162 ZERO(0x014); /* rq inp */
3163 ZERO(0x018); /* rq outp */
3164 ZERO(0x01c); /* respq bah */
3165 ZERO(0x024); /* respq outp */
3166 ZERO(0x020); /* respq inp */
3167 ZERO(0x02c); /* test control */
cae5a29d 3168 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
c9d39130
JG		 3169}
3170#undef ZERO
3171
3172#define ZERO(reg) writel(0, hc_mmio + (reg))
3173static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3174 unsigned int hc)
47c2b677 3175{
c9d39130
JG		 3176 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3177 u32 tmp;
3178
3179 ZERO(0x00c);
3180 ZERO(0x010);
3181 ZERO(0x014);
3182 ZERO(0x018);
3183
3184 tmp = readl(hc_mmio + 0x20);
3185 tmp &= 0x1c1c1c1c;
3186 tmp |= 0x03030303;
3187 writel(tmp, hc_mmio + 0x20);
3188}
3189#undef ZERO
3190
3191static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3192 unsigned int n_hc)
3193{
3194 unsigned int hc, port;
3195
3196 for (hc = 0; hc < n_hc; hc++) {
3197 for (port = 0; port < MV_PORTS_PER_HC; port++)
3198 mv5_reset_hc_port(hpriv, mmio,
3199 (hc * MV_PORTS_PER_HC) + port);
3200
3201 mv5_reset_one_hc(hpriv, mmio, hc);
3202 }
3203
3204 return 0;
47c2b677
JG		 3205}
3206
101ffae2
JG		 3207#undef ZERO
3208#define ZERO(reg) writel(0, mmio + (reg))
7bb3c529 3209static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
101ffae2 3210{
02a121da 3211 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 3212 u32 tmp;
3213
cae5a29d 3214 tmp = readl(mmio + MV_PCI_MODE);
101ffae2 3215 tmp &= 0xff00ffff;
cae5a29d 3216 writel(tmp, mmio + MV_PCI_MODE);
101ffae2
JG		 3217
3218 ZERO(MV_PCI_DISC_TIMER);
3219 ZERO(MV_PCI_MSI_TRIGGER);
cae5a29d 3220 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
101ffae2 3221 ZERO(MV_PCI_SERR_MASK);
cae5a29d
ML		 3222 ZERO(hpriv->irq_cause_offset);
3223 ZERO(hpriv->irq_mask_offset);
101ffae2
JG		 3224 ZERO(MV_PCI_ERR_LOW_ADDRESS);
3225 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3226 ZERO(MV_PCI_ERR_ATTRIBUTE);
3227 ZERO(MV_PCI_ERR_COMMAND);
3228}
3229#undef ZERO
3230
3231static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3232{
3233 u32 tmp;
3234
3235 mv5_reset_flash(hpriv, mmio);
3236
cae5a29d 3237 tmp = readl(mmio + GPIO_PORT_CTL);
101ffae2
JG		 3238 tmp &= 0x3;
3239 tmp |= (1 << 5) | (1 << 6);
cae5a29d 3240 writel(tmp, mmio + GPIO_PORT_CTL);
101ffae2
JG		 3241}
3242
3243/**
3244 * mv6_reset_hc - Perform the 6xxx global soft reset
3245 * @mmio: base address of the HBA
3246 *
3247 * This routine only applies to 6xxx parts.
3248 *
3249 * LOCKING:
3250 * Inherited from caller.
3251 */
c9d39130
JG		 3252static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3253 unsigned int n_hc)
101ffae2 3254{
cae5a29d 3255 void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
101ffae2
JG		 3256 int i, rc = 0;
3257 u32 t;
3258
3259 /* Following procedure defined in PCI "main command and status
3260 * register" table.
3261 */
3262 t = readl(reg);
3263 writel(t | STOP_PCI_MASTER, reg);
3264
3265 for (i = 0; i < 1000; i++) {
3266 udelay(1);
3267 t = readl(reg);
2dcb407e 3268 if (PCI_MASTER_EMPTY & t)
101ffae2 3269 break;
101ffae2
JG		 3270 }
3271 if (!(PCI_MASTER_EMPTY & t)) {
3272 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3273 rc = 1;
3274 goto done;
3275 }
3276
3277 /* set reset */
3278 i = 5;
3279 do {
3280 writel(t | GLOB_SFT_RST, reg);
3281 t = readl(reg);
3282 udelay(1);
3283 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3284
3285 if (!(GLOB_SFT_RST & t)) {
3286 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3287 rc = 1;
3288 goto done;
3289 }
3290
3291 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3292 i = 5;
3293 do {
3294 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3295 t = readl(reg);
3296 udelay(1);
3297 } while ((GLOB_SFT_RST & t) && (i-- > 0));
3298
3299 if (GLOB_SFT_RST & t) {
3300 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3301 rc = 1;
3302 }
3303done:
3304 return rc;
3305}
3306
47c2b677 3307static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 3308 void __iomem *mmio)
3309{
3310 void __iomem *port_mmio;
3311 u32 tmp;
3312
cae5a29d 3313 tmp = readl(mmio + RESET_CFG);
ba3fe8fb 3314 if ((tmp & (1 << 0)) == 0) {
47c2b677 3315 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 3316 hpriv->signal[idx].pre = 0x1 << 5;
3317 return;
3318 }
3319
3320 port_mmio = mv_port_base(mmio, idx);
3321 tmp = readl(port_mmio + PHY_MODE2);
3322
3323 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3324 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3325}
3326
47c2b677 3327static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 3328{
cae5a29d 3329 writel(0x00000060, mmio + GPIO_PORT_CTL);
ba3fe8fb
JG		 3330}
3331
c9d39130 3332static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 3333 unsigned int port)
bca1c4eb 3334{
c9d39130
JG		 3335 void __iomem *port_mmio = mv_port_base(mmio, port);
3336
bca1c4eb 3337 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 3338 int fix_phy_mode2 =
3339 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 3340 int fix_phy_mode4 =
47c2b677 3341 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
8c30a8b9 3342 u32 m2, m3;
47c2b677
JG		 3343
3344 if (fix_phy_mode2) {
3345 m2 = readl(port_mmio + PHY_MODE2);
3346 m2 &= ~(1 << 16);
3347 m2 |= (1 << 31);
3348 writel(m2, port_mmio + PHY_MODE2);
3349
3350 udelay(200);
3351
3352 m2 = readl(port_mmio + PHY_MODE2);
3353 m2 &= ~((1 << 16) | (1 << 31));
3354 writel(m2, port_mmio + PHY_MODE2);
3355
3356 udelay(200);
3357 }
3358
8c30a8b9
ML		 3359 /*
3360 * Gen-II/IIe PHY_MODE3 errata RM#2:
3361 * Achieves better receiver noise performance than the h/w default:
3362 */
3363 m3 = readl(port_mmio + PHY_MODE3);
3364 m3 = (m3 & 0x1f) | (0x5555601 << 5);
bca1c4eb 3365
0388a8c0
ML		 3366 /* Guideline 88F5182 (GL# SATA-S11) */
3367 if (IS_SOC(hpriv))
3368 m3 &= ~0x1c;
3369
bca1c4eb 3370 if (fix_phy_mode4) {
ba069e37
ML		 3371 u32 m4 = readl(port_mmio + PHY_MODE4);
3372 /*
3373 * Enforce reserved-bit restrictions on GenIIe devices only.
3374 * For earlier chipsets, force only the internal config field
3375 * (workaround for errata FEr SATA#10 part 1).
3376 */
8c30a8b9 3377 if (IS_GEN_IIE(hpriv))
ba069e37
ML		 3378 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3379 else
3380 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
8c30a8b9 3381 writel(m4, port_mmio + PHY_MODE4);
bca1c4eb 3382 }
b406c7a6
ML		 3383 /*
3384 * Workaround for 60x1-B2 errata SATA#13:
3385 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3386 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
ba68460b 3387 * Or ensure we use writelfl() when writing PHY_MODE4.
b406c7a6
ML		 3388 */
3389 writel(m3, port_mmio + PHY_MODE3);
bca1c4eb
JG		 3390
3391 /* Revert values of pre-emphasis and signal amps to the saved ones */
3392 m2 = readl(port_mmio + PHY_MODE2);
3393
3394 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 3395 m2 |= hpriv->signal[port].amps;
3396 m2 |= hpriv->signal[port].pre;
47c2b677 3397 m2 &= ~(1 << 16);
bca1c4eb 3398
e4e7b892
JG		 3399 /* according to mvSata 3.6.1, some IIE values are fixed */
3400 if (IS_GEN_IIE(hpriv)) {
3401 m2 &= ~0xC30FF01F;
3402 m2 |= 0x0000900F;
3403 }
3404
bca1c4eb
JG		 3405 writel(m2, port_mmio + PHY_MODE2);
3406}
3407
f351b2d6
SB		 3408/* TODO: use the generic LED interface to configure the SATA Presence */
3409/* & Acitivy LEDs on the board */
3410static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3411 void __iomem *mmio)
3412{
3413 return;
3414}
3415
3416static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3417 void __iomem *mmio)
3418{
3419 void __iomem *port_mmio;
3420 u32 tmp;
3421
3422 port_mmio = mv_port_base(mmio, idx);
3423 tmp = readl(port_mmio + PHY_MODE2);
3424
3425 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3426 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3427}
3428
3429#undef ZERO
3430#define ZERO(reg) writel(0, port_mmio + (reg))
3431static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3432 void __iomem *mmio, unsigned int port)
3433{
3434 void __iomem *port_mmio = mv_port_base(mmio, port);
3435
e12bef50 3436 mv_reset_channel(hpriv, mmio, port);
f351b2d6
SB		 3437
3438 ZERO(0x028); /* command */
cae5a29d 3439 writel(0x101f, port_mmio + EDMA_CFG);
f351b2d6
SB		 3440 ZERO(0x004); /* timer */
3441 ZERO(0x008); /* irq err cause */
3442 ZERO(0x00c); /* irq err mask */
3443 ZERO(0x010); /* rq bah */
3444 ZERO(0x014); /* rq inp */
3445 ZERO(0x018); /* rq outp */
3446 ZERO(0x01c); /* respq bah */
3447 ZERO(0x024); /* respq outp */
3448 ZERO(0x020); /* respq inp */
3449 ZERO(0x02c); /* test control */
d7b0c143 3450 writel(0x800, port_mmio + EDMA_IORDY_TMOUT);
f351b2d6
SB		 3451}
3452
3453#undef ZERO
3454
3455#define ZERO(reg) writel(0, hc_mmio + (reg))
3456static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3457 void __iomem *mmio)
3458{
3459 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3460
3461 ZERO(0x00c);
3462 ZERO(0x010);
3463 ZERO(0x014);
3464
3465}
3466
3467#undef ZERO
3468
3469static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3470 void __iomem *mmio, unsigned int n_hc)
3471{
3472 unsigned int port;
3473
3474 for (port = 0; port < hpriv->n_ports; port++)
3475 mv_soc_reset_hc_port(hpriv, mmio, port);
3476
3477 mv_soc_reset_one_hc(hpriv, mmio);
3478
3479 return 0;
3480}
3481
3482static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3483 void __iomem *mmio)
3484{
3485 return;
3486}
3487
3488static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3489{
3490 return;
3491}
3492
29b7e43c
MM		 3493static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
3494 void __iomem *mmio, unsigned int port)
3495{
3496 void __iomem *port_mmio = mv_port_base(mmio, port);
3497 u32 reg;
3498
3499 reg = readl(port_mmio + PHY_MODE3);
3500 reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
3501 reg |= (0x1 << 27);
3502 reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
3503 reg |= (0x1 << 29);
3504 writel(reg, port_mmio + PHY_MODE3);
3505
3506 reg = readl(port_mmio + PHY_MODE4);
3507 reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
3508 reg |= (0x1 << 16);
3509 writel(reg, port_mmio + PHY_MODE4);
3510
3511 reg = readl(port_mmio + PHY_MODE9_GEN2);
3512 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3513 reg |= 0x8;
3514 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3515 writel(reg, port_mmio + PHY_MODE9_GEN2);
3516
3517 reg = readl(port_mmio + PHY_MODE9_GEN1);
3518 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3519 reg |= 0x8;
3520 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3521 writel(reg, port_mmio + PHY_MODE9_GEN1);
3522}
3523
3524/**
3525 * soc_is_65 - check if the soc is 65 nano device
3526 *
3527 * Detect the type of the SoC, this is done by reading the PHYCFG_OFS
3528 * register, this register should contain non-zero value and it exists only
3529 * in the 65 nano devices, when reading it from older devices we get 0.
3530 */
3531static bool soc_is_65n(struct mv_host_priv *hpriv)
3532{
3533 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
3534
3535 if (readl(port0_mmio + PHYCFG_OFS))
3536 return true;
3537 return false;
3538}
3539
8e7decdb 3540static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
b67a1064 3541{
cae5a29d 3542 u32 ifcfg = readl(port_mmio + SATA_IFCFG);
b67a1064 3543
8e7decdb 3544 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
b67a1064 3545 if (want_gen2i)
8e7decdb 3546 ifcfg |= (1 << 7); /* enable gen2i speed */
cae5a29d 3547 writelfl(ifcfg, port_mmio + SATA_IFCFG);
b67a1064
ML		 3548}
3549
e12bef50 3550static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130
JG		 3551 unsigned int port_no)
3552{
3553 void __iomem *port_mmio = mv_port_base(mmio, port_no);
3554
8e7decdb
ML		 3555 /*
3556 * The datasheet warns against setting EDMA_RESET when EDMA is active
3557 * (but doesn't say what the problem might be). So we first try
3558 * to disable the EDMA engine before doing the EDMA_RESET operation.
3559 */
0d8be5cb 3560 mv_stop_edma_engine(port_mmio);
cae5a29d 3561 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
c9d39130 3562
b67a1064 3563 if (!IS_GEN_I(hpriv)) {
8e7decdb
ML		 3564 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3565 mv_setup_ifcfg(port_mmio, 1);
c9d39130 3566 }
b67a1064 3567 /*
8e7decdb 3568 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
b67a1064 3569 * link, and physical layers. It resets all SATA interface registers
cae5a29d 3570 * (except for SATA_IFCFG), and issues a COMRESET to the dev.
c9d39130 3571 */
cae5a29d 3572 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
b67a1064 3573 udelay(25); /* allow reset propagation */
cae5a29d 3574 writelfl(0, port_mmio + EDMA_CMD);
c9d39130
JG		 3575
3576 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3577
ee9ccdf7 3578 if (IS_GEN_I(hpriv))
c9d39130
JG		 3579 mdelay(1);
3580}
3581
e49856d8 3582static void mv_pmp_select(struct ata_port *ap, int pmp)
20f733e7 3583{
e49856d8
ML		 3584 if (sata_pmp_supported(ap)) {
3585 void __iomem *port_mmio = mv_ap_base(ap);
cae5a29d 3586 u32 reg = readl(port_mmio + SATA_IFCTL);
e49856d8 3587 int old = reg & 0xf;
22374677 3588
e49856d8
ML		 3589 if (old != pmp) {
3590 reg = (reg & ~0xf) | pmp;
cae5a29d 3591 writelfl(reg, port_mmio + SATA_IFCTL);
e49856d8 3592 }
22374677 3593 }
20f733e7
BR		 3594}
3595
e49856d8
ML		 3596static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3597 unsigned long deadline)
22374677 3598{
e49856d8
ML		 3599 mv_pmp_select(link->ap, sata_srst_pmp(link));
3600 return sata_std_hardreset(link, class, deadline);
3601}
bdd4ddde 3602
e49856d8
ML		 3603static int mv_softreset(struct ata_link *link, unsigned int *class,
3604 unsigned long deadline)
3605{
3606 mv_pmp_select(link->ap, sata_srst_pmp(link));
3607 return ata_sff_softreset(link, class, deadline);
22374677
JG		 3608}
3609
cc0680a5 3610static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 3611 unsigned long deadline)
31961943 3612{
cc0680a5 3613 struct ata_port *ap = link->ap;
bdd4ddde 3614 struct mv_host_priv *hpriv = ap->host->private_data;
b562468c 3615 struct mv_port_priv *pp = ap->private_data;
f351b2d6 3616 void __iomem *mmio = hpriv->base;
0d8be5cb
ML		 3617 int rc, attempts = 0, extra = 0;
3618 u32 sstatus;
3619 bool online;
31961943 3620
e12bef50 3621 mv_reset_channel(hpriv, mmio, ap->port_no);
b562468c 3622 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
d16ab3f6
ML		 3623 pp->pp_flags &=
3624 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
bdd4ddde 3625
0d8be5cb
ML		 3626 /* Workaround for errata FEr SATA#10 (part 2) */
3627 do {
17c5aab5
ML		 3628 const unsigned long *timing =
3629 sata_ehc_deb_timing(&link->eh_context);
bdd4ddde 3630
17c5aab5
ML		 3631 rc = sata_link_hardreset(link, timing, deadline + extra,
3632 &online, NULL);
9dcffd99 3633 rc = online ? -EAGAIN : rc;
17c5aab5 3634 if (rc)
0d8be5cb 3635 return rc;
0d8be5cb
ML		 3636 sata_scr_read(link, SCR_STATUS, &sstatus);
3637 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3638 /* Force 1.5gb/s link speed and try again */
8e7decdb 3639 mv_setup_ifcfg(mv_ap_base(ap), 0);
0d8be5cb
ML		 3640 if (time_after(jiffies + HZ, deadline))
3641 extra = HZ; /* only extend it once, max */
3642 }
3643 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
08da1759 3644 mv_save_cached_regs(ap);
66e57a2c 3645 mv_edma_cfg(ap, 0, 0);
bdd4ddde 3646
17c5aab5 3647 return rc;
bdd4ddde
JG		 3648}
3649
bdd4ddde
JG		 3650static void mv_eh_freeze(struct ata_port *ap)
3651{
1cfd19ae 3652 mv_stop_edma(ap);
c4de573b 3653 mv_enable_port_irqs(ap, 0);
bdd4ddde
JG		 3654}
3655
3656static void mv_eh_thaw(struct ata_port *ap)
3657{
f351b2d6 3658 struct mv_host_priv *hpriv = ap->host->private_data;
c4de573b
ML		 3659 unsigned int port = ap->port_no;
3660 unsigned int hardport = mv_hardport_from_port(port);
1cfd19ae 3661 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
bdd4ddde 3662 void __iomem *port_mmio = mv_ap_base(ap);
c4de573b 3663 u32 hc_irq_cause;
bdd4ddde 3664
bdd4ddde 3665 /* clear EDMA errors on this port */
cae5a29d 3666 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
bdd4ddde
JG		 3667
3668 /* clear pending irq events */
cae6edc3 3669 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
cae5a29d 3670 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
bdd4ddde 3671
88e675e1 3672 mv_enable_port_irqs(ap, ERR_IRQ);
31961943
BR		 3673}
3674
05b308e1
BR		 3675/**
3676 * mv_port_init - Perform some early initialization on a single port.
3677 * @port: libata data structure storing shadow register addresses
3678 * @port_mmio: base address of the port
3679 *
3680 * Initialize shadow register mmio addresses, clear outstanding
3681 * interrupts on the port, and unmask interrupts for the future
3682 * start of the port.
3683 *
3684 * LOCKING:
3685 * Inherited from caller.
3686 */
31961943 3687static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 3688{
cae5a29d 3689 void __iomem *serr, *shd_base = port_mmio + SHD_BLK;
31961943 3690
8b260248 3691 /* PIO related setup
31961943
BR		 3692 */
3693 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 3694 port->error_addr =
31961943
BR		 3695 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3696 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3697 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3698 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3699 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3700 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 3701 port->status_addr =
31961943
BR		 3702 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3703 /* special case: control/altstatus doesn't have ATA_REG_ address */
cae5a29d 3704 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
31961943 3705
31961943 3706 /* Clear any currently outstanding port interrupt conditions */
cae5a29d
ML		 3707 serr = port_mmio + mv_scr_offset(SCR_ERROR);
3708 writelfl(readl(serr), serr);
3709 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
31961943 3710
646a4da5 3711 /* unmask all non-transient EDMA error interrupts */
cae5a29d 3712 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
20f733e7 3713
8b260248 3714 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
cae5a29d
ML		 3715 readl(port_mmio + EDMA_CFG),
3716 readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
3717 readl(port_mmio + EDMA_ERR_IRQ_MASK));
20f733e7
BR		 3718}
3719
616d4a98
ML		 3720static unsigned int mv_in_pcix_mode(struct ata_host *host)
3721{
3722 struct mv_host_priv *hpriv = host->private_data;
3723 void __iomem *mmio = hpriv->base;
3724 u32 reg;
3725
1f398472 3726 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
616d4a98 3727 return 0; /* not PCI-X capable */
cae5a29d 3728 reg = readl(mmio + MV_PCI_MODE);
616d4a98
ML		 3729 if ((reg & MV_PCI_MODE_MASK) == 0)
3730 return 0; /* conventional PCI mode */
3731 return 1; /* chip is in PCI-X mode */
3732}
3733
3734static int mv_pci_cut_through_okay(struct ata_host *host)
3735{
3736 struct mv_host_priv *hpriv = host->private_data;
3737 void __iomem *mmio = hpriv->base;
3738 u32 reg;
3739
3740 if (!mv_in_pcix_mode(host)) {
cae5a29d
ML		 3741 reg = readl(mmio + MV_PCI_COMMAND);
3742 if (reg & MV_PCI_COMMAND_MRDTRIG)
616d4a98
ML		 3743 return 0; /* not okay */
3744 }
3745 return 1; /* okay */
3746}
3747
65ad7fef
ML		 3748static void mv_60x1b2_errata_pci7(struct ata_host *host)
3749{
3750 struct mv_host_priv *hpriv = host->private_data;
3751 void __iomem *mmio = hpriv->base;
3752
3753 /* workaround for 60x1-B2 errata PCI#7 */
3754 if (mv_in_pcix_mode(host)) {
cae5a29d
ML		 3755 u32 reg = readl(mmio + MV_PCI_COMMAND);
3756 writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
65ad7fef
ML		 3757 }
3758}
3759
4447d351 3760static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 3761{
4447d351
TH		 3762 struct pci_dev *pdev = to_pci_dev(host->dev);
3763 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 3764 u32 hp_flags = hpriv->hp_flags;
3765
5796d1c4 3766 switch (board_idx) {
47c2b677
JG		 3767 case chip_5080:
3768 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 3769 hp_flags |= MV_HP_GEN_I;
47c2b677 3770
44c10138 3771 switch (pdev->revision) {
47c2b677
JG		 3772 case 0x1:
3773 hp_flags |= MV_HP_ERRATA_50XXB0;
3774 break;
3775 case 0x3:
3776 hp_flags |= MV_HP_ERRATA_50XXB2;
3777 break;
3778 default:
a44fec1f
JP		 3779 dev_warn(&pdev->dev,
3780 "Applying 50XXB2 workarounds to unknown rev\n");
47c2b677
JG		 3781 hp_flags |= MV_HP_ERRATA_50XXB2;
3782 break;
3783 }
3784 break;
3785
bca1c4eb
JG		 3786 case chip_504x:
3787 case chip_508x:
47c2b677 3788 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 3789 hp_flags |= MV_HP_GEN_I;
bca1c4eb 3790
44c10138 3791 switch (pdev->revision) {
47c2b677
JG		 3792 case 0x0:
3793 hp_flags |= MV_HP_ERRATA_50XXB0;
3794 break;
3795 case 0x3:
3796 hp_flags |= MV_HP_ERRATA_50XXB2;
3797 break;
3798 default:
a44fec1f
JP		 3799 dev_warn(&pdev->dev,
3800 "Applying B2 workarounds to unknown rev\n");
47c2b677
JG		 3801 hp_flags |= MV_HP_ERRATA_50XXB2;
3802 break;
bca1c4eb
JG		 3803 }
3804 break;
3805
3806 case chip_604x:
3807 case chip_608x:
47c2b677 3808 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 3809 hp_flags |= MV_HP_GEN_II;
47c2b677 3810
44c10138 3811 switch (pdev->revision) {
47c2b677 3812 case 0x7:
65ad7fef 3813 mv_60x1b2_errata_pci7(host);
47c2b677
JG		 3814 hp_flags |= MV_HP_ERRATA_60X1B2;
3815 break;
3816 case 0x9:
3817 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 3818 break;
3819 default:
a44fec1f
JP		 3820 dev_warn(&pdev->dev,
3821 "Applying B2 workarounds to unknown rev\n");
47c2b677 3822 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 3823 break;
3824 }
3825 break;
3826
e4e7b892 3827 case chip_7042:
616d4a98 3828 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
306b30f7
ML		 3829 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3830 (pdev->device == 0x2300 || pdev->device == 0x2310))
3831 {
4e520033
ML		 3832 /*
3833 * Highpoint RocketRAID PCIe 23xx series cards:
3834 *
3835 * Unconfigured drives are treated as "Legacy"
3836 * by the BIOS, and it overwrites sector 8 with
3837 * a "Lgcy" metadata block prior to Linux boot.
3838 *
3839 * Configured drives (RAID or JBOD) leave sector 8
3840 * alone, but instead overwrite a high numbered
3841 * sector for the RAID metadata. This sector can
3842 * be determined exactly, by truncating the physical
3843 * drive capacity to a nice even GB value.
3844 *
3845 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3846 *
3847 * Warn the user, lest they think we're just buggy.
3848 */
3849 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3850 " BIOS CORRUPTS DATA on all attached drives,"
3851 " regardless of if/how they are configured."
3852 " BEWARE!\n");
3853 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3854 " use sectors 8-9 on \"Legacy\" drives,"
3855 " and avoid the final two gigabytes on"
3856 " all RocketRAID BIOS initialized drives.\n");
306b30f7 3857 }
8e7decdb 3858 /* drop through */
e4e7b892
JG		 3859 case chip_6042:
3860 hpriv->ops = &mv6xxx_ops;
e4e7b892 3861 hp_flags |= MV_HP_GEN_IIE;
616d4a98
ML		 3862 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3863 hp_flags |= MV_HP_CUT_THROUGH;
e4e7b892 3864
44c10138 3865 switch (pdev->revision) {
5cf73bfb 3866 case 0x2: /* Rev.B0: the first/only public release */
e4e7b892
JG		 3867 hp_flags |= MV_HP_ERRATA_60X1C0;
3868 break;
3869 default:
a44fec1f
JP		 3870 dev_warn(&pdev->dev,
3871 "Applying 60X1C0 workarounds to unknown rev\n");
e4e7b892
JG		 3872 hp_flags |= MV_HP_ERRATA_60X1C0;
3873 break;
3874 }
3875 break;
f351b2d6 3876 case chip_soc:
29b7e43c
MM		 3877 if (soc_is_65n(hpriv))
3878 hpriv->ops = &mv_soc_65n_ops;
3879 else
3880 hpriv->ops = &mv_soc_ops;
eb3a55a9
SB		 3881 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3882 MV_HP_ERRATA_60X1C0;
f351b2d6 3883 break;
e4e7b892 3884
bca1c4eb 3885 default:
a44fec1f 3886 dev_err(host->dev, "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 3887 return 1;
3888 }
3889
3890 hpriv->hp_flags = hp_flags;
02a121da 3891 if (hp_flags & MV_HP_PCIE) {
cae5a29d
ML		 3892 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
3893 hpriv->irq_mask_offset = PCIE_IRQ_MASK;
02a121da
ML		 3894 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3895 } else {
cae5a29d
ML		 3896 hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
3897 hpriv->irq_mask_offset = PCI_IRQ_MASK;
02a121da
ML		 3898 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3899 }
bca1c4eb
JG		 3900
3901 return 0;
3902}
3903
05b308e1 3904/**
47c2b677 3905 * mv_init_host - Perform some early initialization of the host.
4447d351 3906 * @host: ATA host to initialize
05b308e1
BR		 3907 *
3908 * If possible, do an early global reset of the host. Then do
3909 * our port init and clear/unmask all/relevant host interrupts.
3910 *
3911 * LOCKING:
3912 * Inherited from caller.
3913 */
1bfeff03 3914static int mv_init_host(struct ata_host *host)
20f733e7
BR		 3915{
3916 int rc = 0, n_hc, port, hc;
4447d351 3917 struct mv_host_priv *hpriv = host->private_data;
f351b2d6 3918 void __iomem *mmio = hpriv->base;
47c2b677 3919
1bfeff03 3920 rc = mv_chip_id(host, hpriv->board_idx);
bca1c4eb 3921 if (rc)
352fab70 3922 goto done;
f351b2d6 3923
1f398472 3924 if (IS_SOC(hpriv)) {
cae5a29d
ML		 3925 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
3926 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
1f398472 3927 } else {
cae5a29d
ML		 3928 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
3929 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
f351b2d6 3930 }
352fab70 3931
5d0fb2e7
TR		 3932 /* initialize shadow irq mask with register's value */
3933 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3934
352fab70 3935 /* global interrupt mask: 0 == mask everything */
c4de573b 3936 mv_set_main_irq_mask(host, ~0, 0);
bca1c4eb 3937
4447d351 3938 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 3939
4447d351 3940 for (port = 0; port < host->n_ports; port++)
29b7e43c
MM		 3941 if (hpriv->ops->read_preamp)
3942 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 3943
c9d39130 3944 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 3945 if (rc)
20f733e7 3946 goto done;
20f733e7 3947
522479fb 3948 hpriv->ops->reset_flash(hpriv, mmio);
7bb3c529 3949 hpriv->ops->reset_bus(host, mmio);
47c2b677 3950 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 3951
4447d351 3952 for (port = 0; port < host->n_ports; port++) {
cbcdd875 3953 struct ata_port *ap = host->ports[port];
2a47ce06 3954 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 3955
3956 mv_port_init(&ap->ioaddr, port_mmio);
20f733e7
BR		 3957 }
3958
3959 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 3960 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3961
3962 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3963 "(before clear)=0x%08x\n", hc,
cae5a29d
ML		 3964 readl(hc_mmio + HC_CFG),
3965 readl(hc_mmio + HC_IRQ_CAUSE));
31961943
BR		 3966
3967 /* Clear any currently outstanding hc interrupt conditions */
cae5a29d 3968 writelfl(0, hc_mmio + HC_IRQ_CAUSE);
20f733e7
BR		 3969 }
3970
44c65d16
ML		 3971 if (!IS_SOC(hpriv)) {
3972 /* Clear any currently outstanding host interrupt conditions */
cae5a29d 3973 writelfl(0, mmio + hpriv->irq_cause_offset);
31961943 3974
44c65d16 3975 /* and unmask interrupt generation for host regs */
cae5a29d 3976 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
44c65d16 3977 }
51de32d2 3978
6be96ac1
ML		 3979 /*
3980 * enable only global host interrupts for now.
3981 * The per-port interrupts get done later as ports are set up.
3982 */
3983 mv_set_main_irq_mask(host, 0, PCI_ERR);
2b748a0a
ML		 3984 mv_set_irq_coalescing(host, irq_coalescing_io_count,
3985 irq_coalescing_usecs);
f351b2d6
SB		 3986done:
3987 return rc;
3988}
fb621e2f 3989
fbf14e2f
BB		 3990static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3991{
3992 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3993 MV_CRQB_Q_SZ, 0);
3994 if (!hpriv->crqb_pool)
3995 return -ENOMEM;
3996
3997 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3998 MV_CRPB_Q_SZ, 0);
3999 if (!hpriv->crpb_pool)
4000 return -ENOMEM;
4001
4002 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
4003 MV_SG_TBL_SZ, 0);
4004 if (!hpriv->sg_tbl_pool)
4005 return -ENOMEM;
4006
4007 return 0;
4008}
4009
15a32632 4010static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
63a9332b 4011 const struct mbus_dram_target_info *dram)
15a32632
LB		 4012{
4013 int i;
4014
4015 for (i = 0; i < 4; i++) {
4016 writel(0, hpriv->base + WINDOW_CTRL(i));
4017 writel(0, hpriv->base + WINDOW_BASE(i));
4018 }
4019
4020 for (i = 0; i < dram->num_cs; i++) {
63a9332b 4021 const struct mbus_dram_window *cs = dram->cs + i;
15a32632
LB		 4022
4023 writel(((cs->size - 1) & 0xffff0000) |
4024 (cs->mbus_attr << 8) |
4025 (dram->mbus_dram_target_id << 4) | 1,
4026 hpriv->base + WINDOW_CTRL(i));
4027 writel(cs->base, hpriv->base + WINDOW_BASE(i));
4028 }
4029}
4030
f351b2d6
SB		 4031/**
4032 * mv_platform_probe - handle a positive probe of an soc Marvell
4033 * host
4034 * @pdev: platform device found
4035 *
4036 * LOCKING:
4037 * Inherited from caller.
4038 */
4039static int mv_platform_probe(struct platform_device *pdev)
4040{
f351b2d6 4041 const struct mv_sata_platform_data *mv_platform_data;
63a9332b 4042 const struct mbus_dram_target_info *dram;
f351b2d6
SB		 4043 const struct ata_port_info *ppi[] =
4044 { &mv_port_info[chip_soc], NULL };
4045 struct ata_host *host;
4046 struct mv_host_priv *hpriv;
4047 struct resource *res;
97b414e1 4048 int n_ports = 0, irq = 0;
99b80e97 4049 int rc;
eee98990
AL		 4050#if defined(CONFIG_HAVE_CLK)
4051 int port;
4052#endif
20f733e7 4053
06296a1e 4054 ata_print_version_once(&pdev->dev, DRV_VERSION);
bca1c4eb 4055
f351b2d6
SB		 4056 /*
4057 * Simple resource validation ..
4058 */
4059 if (unlikely(pdev->num_resources != 2)) {
4060 dev_err(&pdev->dev, "invalid number of resources\n");
4061 return -EINVAL;
4062 }
4063
4064 /*
4065 * Get the register base first
4066 */
4067 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4068 if (res == NULL)
4069 return -EINVAL;
4070
4071 /* allocate host */
97b414e1
AL		 4072 if (pdev->dev.of_node) {
4073 of_property_read_u32(pdev->dev.of_node, "nr-ports", &n_ports);
4074 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
4075 } else {
4076 mv_platform_data = pdev->dev.platform_data;
4077 n_ports = mv_platform_data->n_ports;
4078 irq = platform_get_irq(pdev, 0);
4079 }
f351b2d6
SB		 4080
4081 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4082 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4083
4084 if (!host || !hpriv)
4085 return -ENOMEM;
eee98990
AL		 4086#if defined(CONFIG_HAVE_CLK)
4087 hpriv->port_clks = devm_kzalloc(&pdev->dev,
4088 sizeof(struct clk *) * n_ports,
4089 GFP_KERNEL);
4090 if (!hpriv->port_clks)
4091 return -ENOMEM;
4092#endif
f351b2d6
SB		 4093 host->private_data = hpriv;
4094 hpriv->n_ports = n_ports;
1bfeff03 4095 hpriv->board_idx = chip_soc;
f351b2d6
SB		 4096
4097 host->iomap = NULL;
f1cb0ea1 4098 hpriv->base = devm_ioremap(&pdev->dev, res->start,
041b5eac 4099 resource_size(res));
bb3d39c7
AY		 4100 if (!hpriv->base)
4101 return -ENOMEM;
4102
cae5a29d 4103 hpriv->base -= SATAHC0_REG_BASE;
f351b2d6 4104
c77a2f4e
SB		 4105#if defined(CONFIG_HAVE_CLK)
4106 hpriv->clk = clk_get(&pdev->dev, NULL);
4107 if (IS_ERR(hpriv->clk))
eee98990 4108 dev_notice(&pdev->dev, "cannot get optional clkdev\n");
c77a2f4e 4109 else
eee98990
AL		 4110 clk_prepare_enable(hpriv->clk);
4111
4112 for (port = 0; port < n_ports; port++) {
4113 char port_number[16];
4114 sprintf(port_number, "%d", port);
4115 hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);
4116 if (!IS_ERR(hpriv->port_clks[port]))
4117 clk_prepare_enable(hpriv->port_clks[port]);
4118 }
c77a2f4e
SB		 4119#endif
4120
15a32632
LB		 4121 /*
4122 * (Re-)program MBUS remapping windows if we are asked to.
4123 */
63a9332b
AL		 4124 dram = mv_mbus_dram_info();
4125 if (dram)
4126 mv_conf_mbus_windows(hpriv, dram);
15a32632 4127
fbf14e2f
BB		 4128 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4129 if (rc)
c77a2f4e 4130 goto err;
fbf14e2f 4131
6314611a
LA		 4132 /*
4133 * To allow disk hotplug on Armada 370/XP SoCs, the PHY speed must be
4134 * updated in the LP_PHY_CTL register.
4135 */
4136 if (pdev->dev.of_node &&
4137 of_device_is_compatible(pdev->dev.of_node,
4138 "marvell,armada-370-sata"))
4139 hpriv->hp_flags |= MV_HP_FIX_LP_PHY_CTL;
4140
f351b2d6 4141 /* initialize adapter */
1bfeff03 4142 rc = mv_init_host(host);
f351b2d6 4143 if (rc)
c77a2f4e 4144 goto err;
f351b2d6 4145
a44fec1f
JP		 4146 dev_info(&pdev->dev, "slots %u ports %d\n",
4147 (unsigned)MV_MAX_Q_DEPTH, host->n_ports);
f351b2d6 4148
97b414e1 4149 rc = ata_host_activate(host, irq, mv_interrupt, IRQF_SHARED, &mv6_sht);
c00a4c9d
SS		 4150 if (!rc)
4151 return 0;
4152
c77a2f4e
SB		 4153err:
4154#if defined(CONFIG_HAVE_CLK)
4155 if (!IS_ERR(hpriv->clk)) {
eee98990 4156 clk_disable_unprepare(hpriv->clk);
c77a2f4e
SB		 4157 clk_put(hpriv->clk);
4158 }
eee98990
AL		 4159 for (port = 0; port < n_ports; port++) {
4160 if (!IS_ERR(hpriv->port_clks[port])) {
4161 clk_disable_unprepare(hpriv->port_clks[port]);
4162 clk_put(hpriv->port_clks[port]);
4163 }
4164 }
c77a2f4e
SB		 4165#endif
4166
4167 return rc;
f351b2d6
SB		 4168}
4169
4170/*
4171 *
4172 * mv_platform_remove - unplug a platform interface
4173 * @pdev: platform device
4174 *
4175 * A platform bus SATA device has been unplugged. Perform the needed
4176 * cleanup. Also called on module unload for any active devices.
4177 */
0ec24914 4178static int mv_platform_remove(struct platform_device *pdev)
f351b2d6 4179{
d8661921 4180 struct ata_host *host = platform_get_drvdata(pdev);
c77a2f4e
SB		 4181#if defined(CONFIG_HAVE_CLK)
4182 struct mv_host_priv *hpriv = host->private_data;
eee98990 4183 int port;
c77a2f4e 4184#endif
f351b2d6 4185 ata_host_detach(host);
c77a2f4e
SB		 4186
4187#if defined(CONFIG_HAVE_CLK)
4188 if (!IS_ERR(hpriv->clk)) {
eee98990 4189 clk_disable_unprepare(hpriv->clk);
c77a2f4e
SB		 4190 clk_put(hpriv->clk);
4191 }
eee98990
AL		 4192 for (port = 0; port < host->n_ports; port++) {
4193 if (!IS_ERR(hpriv->port_clks[port])) {
4194 clk_disable_unprepare(hpriv->port_clks[port]);
4195 clk_put(hpriv->port_clks[port]);
4196 }
4197 }
c77a2f4e 4198#endif
f351b2d6 4199 return 0;
20f733e7
BR		 4200}
4201
6481f2b5
SB		 4202#ifdef CONFIG_PM
4203static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state)
4204{
d8661921 4205 struct ata_host *host = platform_get_drvdata(pdev);
6481f2b5
SB		 4206 if (host)
4207 return ata_host_suspend(host, state);
4208 else
4209 return 0;
4210}
4211
4212static int mv_platform_resume(struct platform_device *pdev)
4213{
d8661921 4214 struct ata_host *host = platform_get_drvdata(pdev);
63a9332b 4215 const struct mbus_dram_target_info *dram;
6481f2b5
SB		 4216 int ret;
4217
4218 if (host) {
4219 struct mv_host_priv *hpriv = host->private_data;
63a9332b 4220
6481f2b5
SB		 4221 /*
4222 * (Re-)program MBUS remapping windows if we are asked to.
4223 */
63a9332b
AL		 4224 dram = mv_mbus_dram_info();
4225 if (dram)
4226 mv_conf_mbus_windows(hpriv, dram);
6481f2b5
SB		 4227
4228 /* initialize adapter */
1bfeff03 4229 ret = mv_init_host(host);
6481f2b5
SB		 4230 if (ret) {
4231 printk(KERN_ERR DRV_NAME ": Error during HW init\n");
4232 return ret;
4233 }
4234 ata_host_resume(host);
4235 }
4236
4237 return 0;
4238}
4239#else
4240#define mv_platform_suspend NULL
4241#define mv_platform_resume NULL
4242#endif
4243
97b414e1 4244#ifdef CONFIG_OF
0ec24914 4245static struct of_device_id mv_sata_dt_ids[] = {
509e5695 4246 { .compatible = "marvell,armada-370-sata", },
97b414e1
AL		 4247 { .compatible = "marvell,orion-sata", },
4248 {},
4249};
4250MODULE_DEVICE_TABLE(of, mv_sata_dt_ids);
4251#endif
4252
f351b2d6 4253static struct platform_driver mv_platform_driver = {
97b414e1 4254 .probe = mv_platform_probe,
0ec24914 4255 .remove = mv_platform_remove,
97b414e1
AL		 4256 .suspend = mv_platform_suspend,
4257 .resume = mv_platform_resume,
4258 .driver = {
4259 .name = DRV_NAME,
4260 .owner = THIS_MODULE,
4261 .of_match_table = of_match_ptr(mv_sata_dt_ids),
4262 },
f351b2d6
SB		 4263};
4264
4265
7bb3c529 4266#ifdef CONFIG_PCI
f351b2d6
SB		 4267static int mv_pci_init_one(struct pci_dev *pdev,
4268 const struct pci_device_id *ent);
b2dec48c
SB		 4269#ifdef CONFIG_PM
4270static int mv_pci_device_resume(struct pci_dev *pdev);
4271#endif
f351b2d6 4272
7bb3c529
SB		 4273
4274static struct pci_driver mv_pci_driver = {
4275 .name = DRV_NAME,
4276 .id_table = mv_pci_tbl,
f351b2d6 4277 .probe = mv_pci_init_one,
7bb3c529 4278 .remove = ata_pci_remove_one,
b2dec48c
SB		 4279#ifdef CONFIG_PM
4280 .suspend = ata_pci_device_suspend,
4281 .resume = mv_pci_device_resume,
4282#endif
4283
7bb3c529
SB		 4284};
4285
7bb3c529
SB		 4286/* move to PCI layer or libata core? */
4287static int pci_go_64(struct pci_dev *pdev)
4288{
4289 int rc;
4290
6a35528a
YH		 4291 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4292 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
7bb3c529 4293 if (rc) {
284901a9 4294 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
7bb3c529 4295 if (rc) {
a44fec1f
JP		 4296 dev_err(&pdev->dev,
4297 "64-bit DMA enable failed\n");
7bb3c529
SB		 4298 return rc;
4299 }
4300 }
4301 } else {
284901a9 4302 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7bb3c529 4303 if (rc) {
a44fec1f 4304 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
7bb3c529
SB		 4305 return rc;
4306 }
284901a9 4307 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
7bb3c529 4308 if (rc) {
a44fec1f
JP		 4309 dev_err(&pdev->dev,
4310 "32-bit consistent DMA enable failed\n");
7bb3c529
SB		 4311 return rc;
4312 }
4313 }
4314
4315 return rc;
4316}
4317
05b308e1
BR		 4318/**
4319 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 4320 * @host: ATA host to print info about
05b308e1
BR		 4321 *
4322 * FIXME: complete this.
4323 *
4324 * LOCKING:
4325 * Inherited from caller.
4326 */
4447d351 4327static void mv_print_info(struct ata_host *host)
31961943 4328{
4447d351
TH		 4329 struct pci_dev *pdev = to_pci_dev(host->dev);
4330 struct mv_host_priv *hpriv = host->private_data;
44c10138 4331 u8 scc;
c1e4fe71 4332 const char *scc_s, *gen;
31961943
BR		 4333
4334 /* Use this to determine the HW stepping of the chip so we know
4335 * what errata to workaround
4336 */
31961943
BR		 4337 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
4338 if (scc == 0)
4339 scc_s = "SCSI";
4340 else if (scc == 0x01)
4341 scc_s = "RAID";
4342 else
c1e4fe71
JG		 4343 scc_s = "?";
4344
4345 if (IS_GEN_I(hpriv))
4346 gen = "I";
4347 else if (IS_GEN_II(hpriv))
4348 gen = "II";
4349 else if (IS_GEN_IIE(hpriv))
4350 gen = "IIE";
4351 else
4352 gen = "?";
31961943 4353
a44fec1f
JP		 4354 dev_info(&pdev->dev, "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
4355 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
4356 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
31961943
BR		 4357}
4358
05b308e1 4359/**
f351b2d6 4360 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
05b308e1
BR		 4361 * @pdev: PCI device found
4362 * @ent: PCI device ID entry for the matched host
4363 *
4364 * LOCKING:
4365 * Inherited from caller.
4366 */
f351b2d6
SB		 4367static int mv_pci_init_one(struct pci_dev *pdev,
4368 const struct pci_device_id *ent)
20f733e7 4369{
20f733e7 4370 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 4371 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
4372 struct ata_host *host;
4373 struct mv_host_priv *hpriv;
c4bc7d73 4374 int n_ports, port, rc;
20f733e7 4375
06296a1e 4376 ata_print_version_once(&pdev->dev, DRV_VERSION);
20f733e7 4377
4447d351
TH		 4378 /* allocate host */
4379 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4380
4381 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4382 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4383 if (!host || !hpriv)
4384 return -ENOMEM;
4385 host->private_data = hpriv;
f351b2d6 4386 hpriv->n_ports = n_ports;
1bfeff03 4387 hpriv->board_idx = board_idx;
4447d351
TH		 4388
4389 /* acquire resources */
24dc5f33
TH		 4390 rc = pcim_enable_device(pdev);
4391 if (rc)
20f733e7 4392 return rc;
20f733e7 4393
0d5ff566
TH		 4394 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4395 if (rc == -EBUSY)
24dc5f33 4396 pcim_pin_device(pdev);
0d5ff566 4397 if (rc)
24dc5f33 4398 return rc;
4447d351 4399 host->iomap = pcim_iomap_table(pdev);
f351b2d6 4400 hpriv->base = host->iomap[MV_PRIMARY_BAR];
20f733e7 4401
d88184fb
JG		 4402 rc = pci_go_64(pdev);
4403 if (rc)
4404 return rc;
4405
da2fa9ba
ML		 4406 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4407 if (rc)
4408 return rc;
4409
c4bc7d73
SB		 4410 for (port = 0; port < host->n_ports; port++) {
4411 struct ata_port *ap = host->ports[port];
4412 void __iomem *port_mmio = mv_port_base(hpriv->base, port);
4413 unsigned int offset = port_mmio - hpriv->base;
4414
4415 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
4416 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
4417 }
4418
20f733e7 4419 /* initialize adapter */
1bfeff03 4420 rc = mv_init_host(host);
24dc5f33
TH		 4421 if (rc)
4422 return rc;
20f733e7 4423
6d3c30ef
ML		 4424 /* Enable message-switched interrupts, if requested */
4425 if (msi && pci_enable_msi(pdev) == 0)
4426 hpriv->hp_flags |= MV_HP_FLAG_MSI;
20f733e7 4427
31961943 4428 mv_dump_pci_cfg(pdev, 0x68);
4447d351 4429 mv_print_info(host);
20f733e7 4430
4447d351 4431 pci_set_master(pdev);
ea8b4db9 4432 pci_try_set_mwi(pdev);
4447d351 4433 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 4434 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7 4435}
b2dec48c
SB		 4436
4437#ifdef CONFIG_PM
4438static int mv_pci_device_resume(struct pci_dev *pdev)
4439{
d8661921 4440 struct ata_host *host = pci_get_drvdata(pdev);
b2dec48c
SB		 4441 int rc;
4442
4443 rc = ata_pci_device_do_resume(pdev);
4444 if (rc)
4445 return rc;
4446
4447 /* initialize adapter */
4448 rc = mv_init_host(host);
4449 if (rc)
4450 return rc;
4451
4452 ata_host_resume(host);
4453
4454 return 0;
4455}
4456#endif
7bb3c529 4457#endif
20f733e7 4458
f351b2d6 4459static int mv_platform_probe(struct platform_device *pdev);
0ec24914 4460static int mv_platform_remove(struct platform_device *pdev);
f351b2d6 4461
20f733e7
BR		 4462static int __init mv_init(void)
4463{
7bb3c529
SB		 4464 int rc = -ENODEV;
4465#ifdef CONFIG_PCI
4466 rc = pci_register_driver(&mv_pci_driver);
f351b2d6
SB		 4467 if (rc < 0)
4468 return rc;
4469#endif
4470 rc = platform_driver_register(&mv_platform_driver);
4471
4472#ifdef CONFIG_PCI
4473 if (rc < 0)
4474 pci_unregister_driver(&mv_pci_driver);
7bb3c529
SB		 4475#endif
4476 return rc;
20f733e7
BR		 4477}
4478
4479static void __exit mv_exit(void)
4480{
7bb3c529 4481#ifdef CONFIG_PCI
20f733e7 4482 pci_unregister_driver(&mv_pci_driver);
7bb3c529 4483#endif
f351b2d6 4484 platform_driver_unregister(&mv_platform_driver);
20f733e7
BR		 4485}
4486
4487MODULE_AUTHOR("Brett Russ");
4488MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4489MODULE_LICENSE("GPL");
4490MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4491MODULE_VERSION(DRV_VERSION);
17c5aab5 4492MODULE_ALIAS("platform:" DRV_NAME);
20f733e7
BR		 4493
4494module_init(mv_init);
4495module_exit(mv_exit);
kernel source for telekom puls (alcatel/mediatek)