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[libata] Drain data on errors
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
40f21b11 4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
8b260248 5 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 6 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7 7 *
40f21b11
ML		 8 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
10 *
20f733e7
BR		 11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
4a05e209 28/*
85afb934
ML		 29 * sata_mv TODO list:
30 *
85afb934
ML		 31 * --> More errata workarounds for PCI-X.
32 *
33 * --> Complete a full errata audit for all chipsets to identify others.
34 *
85afb934
ML		 35 * --> Develop a low-power-consumption strategy, and implement it.
36 *
2b748a0a 37 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
85afb934
ML		 38 *
39 * --> [Experiment, Marvell value added] Is it possible to use target
40 * mode to cross-connect two Linux boxes with Marvell cards? If so,
41 * creating LibATA target mode support would be very interesting.
42 *
43 * Target mode, for those without docs, is the ability to directly
44 * connect two SATA ports.
45 */
4a05e209 46
20f733e7
BR		 47#include <linux/kernel.h>
48#include <linux/module.h>
49#include <linux/pci.h>
50#include <linux/init.h>
51#include <linux/blkdev.h>
52#include <linux/delay.h>
53#include <linux/interrupt.h>
8d8b6004 54#include <linux/dmapool.h>
20f733e7 55#include <linux/dma-mapping.h>
a9524a76 56#include <linux/device.h>
f351b2d6
SB		 57#include <linux/platform_device.h>
58#include <linux/ata_platform.h>
15a32632 59#include <linux/mbus.h>
c46938cc 60#include <linux/bitops.h>
20f733e7 61#include <scsi/scsi_host.h>
193515d5 62#include <scsi/scsi_cmnd.h>
6c08772e 63#include <scsi/scsi_device.h>
20f733e7 64#include <linux/libata.h>
20f733e7
BR		 65
66#define DRV_NAME "sata_mv"
2b748a0a 67#define DRV_VERSION "1.27"
20f733e7 68
40f21b11
ML		 69/*
70 * module options
71 */
72
73static int msi;
74#ifdef CONFIG_PCI
75module_param(msi, int, S_IRUGO);
76MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
77#endif
78
2b748a0a
ML		 79static int irq_coalescing_io_count;
80module_param(irq_coalescing_io_count, int, S_IRUGO);
81MODULE_PARM_DESC(irq_coalescing_io_count,
82 "IRQ coalescing I/O count threshold (0..255)");
83
84static int irq_coalescing_usecs;
85module_param(irq_coalescing_usecs, int, S_IRUGO);
86MODULE_PARM_DESC(irq_coalescing_usecs,
87 "IRQ coalescing time threshold in usecs");
88
20f733e7
BR		 89enum {
90 /* BAR's are enumerated in terms of pci_resource_start() terms */
91 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
92 MV_IO_BAR = 2, /* offset 0x18: IO space */
93 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
94
95 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
96 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
97
2b748a0a
ML		 98 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
99 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
100 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
101 MAX_COAL_IO_COUNT = 255, /* completed I/O count */
102
20f733e7 103 MV_PCI_REG_BASE = 0,
615ab953 104
2b748a0a
ML		 105 /*
106 * Per-chip ("all ports") interrupt coalescing feature.
107 * This is only for GEN_II / GEN_IIE hardware.
108 *
109 * Coalescing defers the interrupt until either the IO_THRESHOLD
110 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
111 */
112 MV_COAL_REG_BASE = 0x18000,
113 MV_IRQ_COAL_CAUSE = (MV_COAL_REG_BASE + 0x08),
114 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
115
116 MV_IRQ_COAL_IO_THRESHOLD = (MV_COAL_REG_BASE + 0xcc),
117 MV_IRQ_COAL_TIME_THRESHOLD = (MV_COAL_REG_BASE + 0xd0),
118
119 /*
120 * Registers for the (unused here) transaction coalescing feature:
121 */
122 MV_TRAN_COAL_CAUSE_LO = (MV_COAL_REG_BASE + 0x88),
123 MV_TRAN_COAL_CAUSE_HI = (MV_COAL_REG_BASE + 0x8c),
124
20f733e7 125 MV_SATAHC0_REG_BASE = 0x20000,
8e7decdb
ML		 126 MV_FLASH_CTL_OFS = 0x1046c,
127 MV_GPIO_PORT_CTL_OFS = 0x104f0,
128 MV_RESET_CFG_OFS = 0x180d8,
20f733e7
BR		 129
130 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
131 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
132 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
133 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
134
31961943
BR		 135 MV_MAX_Q_DEPTH = 32,
136 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
137
138 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
139 * CRPB needs alignment on a 256B boundary. Size == 256B
31961943
BR		 140 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
141 */
142 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
143 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
da2fa9ba 144 MV_MAX_SG_CT = 256,
31961943 145 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
31961943 146
352fab70 147 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
20f733e7 148 MV_PORT_HC_SHIFT = 2,
352fab70
ML		 149 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
150 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
151 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
20f733e7
BR		 152
153 /* Host Flags */
154 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
7bb3c529 155
c5d3e45a 156 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
91b1a84c 157 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
ad3aef51 158
91b1a84c 159 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
20f733e7 160
40f21b11
ML		 161 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
162 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
91b1a84c
ML		 163
164 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
ad3aef51 165
31961943
BR		 166 CRQB_FLAG_READ = (1 << 0),
167 CRQB_TAG_SHIFT = 1,
c5d3e45a 168 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
e12bef50 169 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
c5d3e45a 170 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 171 CRQB_CMD_ADDR_SHIFT = 8,
172 CRQB_CMD_CS = (0x2 << 11),
173 CRQB_CMD_LAST = (1 << 15),
174
175 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 176 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
177 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 178
179 EPRD_FLAG_END_OF_TBL = (1 << 31),
180
20f733e7
BR		 181 /* PCI interface registers */
182
31961943 183 PCI_COMMAND_OFS = 0xc00,
8e7decdb 184 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
31961943 185
20f733e7
BR		 186 PCI_MAIN_CMD_STS_OFS = 0xd30,
187 STOP_PCI_MASTER = (1 << 2),
188 PCI_MASTER_EMPTY = (1 << 3),
189 GLOB_SFT_RST = (1 << 4),
190
8e7decdb
ML		 191 MV_PCI_MODE_OFS = 0xd00,
192 MV_PCI_MODE_MASK = 0x30,
193
522479fb
JG		 194 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
195 MV_PCI_DISC_TIMER = 0xd04,
196 MV_PCI_MSI_TRIGGER = 0xc38,
197 MV_PCI_SERR_MASK = 0xc28,
8e7decdb 198 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
522479fb
JG		 199 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
200 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
201 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
202 MV_PCI_ERR_COMMAND = 0x1d50,
203
02a121da
ML		 204 PCI_IRQ_CAUSE_OFS = 0x1d58,
205 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 206 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
207
02a121da
ML		 208 PCIE_IRQ_CAUSE_OFS = 0x1900,
209 PCIE_IRQ_MASK_OFS = 0x1910,
646a4da5 210 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 211
7368f919
ML		 212 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
213 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
214 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
215 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
216 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
40f21b11
ML		 217 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
218 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
20f733e7
BR		 219 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
220 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
2b748a0a
ML		 221 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
222 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
20f733e7 223 PCI_ERR = (1 << 18),
40f21b11
ML		 224 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
225 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
226 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
227 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
228 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
20f733e7
BR		 229 GPIO_INT = (1 << 22),
230 SELF_INT = (1 << 23),
231 TWSI_INT = (1 << 24),
232 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 233 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
e12bef50 234 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
20f733e7
BR		 235
236 /* SATAHC registers */
237 HC_CFG_OFS = 0,
238
239 HC_IRQ_CAUSE_OFS = 0x14,
352fab70
ML		 240 DMA_IRQ = (1 << 0), /* shift by port # */
241 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
20f733e7
BR		 242 DEV_IRQ = (1 << 8), /* shift by port # */
243
2b748a0a
ML		 244 /*
245 * Per-HC (Host-Controller) interrupt coalescing feature.
246 * This is present on all chip generations.
247 *
248 * Coalescing defers the interrupt until either the IO_THRESHOLD
249 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
250 */
251 HC_IRQ_COAL_IO_THRESHOLD_OFS = 0x000c,
252 HC_IRQ_COAL_TIME_THRESHOLD_OFS = 0x0010,
253
000b344f
ML		 254 SOC_LED_CTRL_OFS = 0x2c,
255 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
256 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
257 /* with dev activity LED */
258
20f733e7 259 /* Shadow block registers */
31961943
BR		 260 SHD_BLK_OFS = 0x100,
261 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 262
263 /* SATA registers */
264 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
265 SATA_ACTIVE_OFS = 0x350,
0c58912e 266 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
c443c500 267 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
17c5aab5 268
e12bef50 269 LTMODE_OFS = 0x30c,
17c5aab5
ML		 270 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
271
47c2b677 272 PHY_MODE3 = 0x310,
bca1c4eb 273 PHY_MODE4 = 0x314,
ba069e37
ML		 274 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
275 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
276 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
277 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
278
bca1c4eb 279 PHY_MODE2 = 0x330,
e12bef50 280 SATA_IFCTL_OFS = 0x344,
8e7decdb 281 SATA_TESTCTL_OFS = 0x348,
e12bef50
ML		 282 SATA_IFSTAT_OFS = 0x34c,
283 VENDOR_UNIQUE_FIS_OFS = 0x35c,
17c5aab5 284
8e7decdb
ML		 285 FISCFG_OFS = 0x360,
286 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
287 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
17c5aab5 288
c9d39130 289 MV5_PHY_MODE = 0x74,
8e7decdb
ML		 290 MV5_LTMODE_OFS = 0x30,
291 MV5_PHY_CTL_OFS = 0x0C,
292 SATA_INTERFACE_CFG_OFS = 0x050,
bca1c4eb
JG		 293
294 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 295
296 /* Port registers */
297 EDMA_CFG_OFS = 0,
0c58912e
ML		 298 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
299 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
300 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
301 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
302 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
e12bef50
ML		 303 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
304 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
20f733e7
BR		 305
306 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
307 EDMA_ERR_IRQ_MASK_OFS = 0xc,
6c1153e0
JG		 308 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
309 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
310 EDMA_ERR_DEV = (1 << 2), /* device error */
311 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
312 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
313 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 314 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
315 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 316 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 317 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 318 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
319 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
320 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
321 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 322
6c1153e0 323 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 324 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
325 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
326 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
327 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
328
6c1153e0 329 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 330
6c1153e0 331 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 332 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
333 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
334 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
335 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
336 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
337
6c1153e0 338 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 339
6c1153e0 340 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 341 EDMA_ERR_OVERRUN_5 = (1 << 5),
342 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 343
344 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
345 EDMA_ERR_LNK_CTRL_RX_1 |
346 EDMA_ERR_LNK_CTRL_RX_3 |
85afb934 347 EDMA_ERR_LNK_CTRL_TX,
646a4da5 348
bdd4ddde
JG		 349 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
350 EDMA_ERR_PRD_PAR |
351 EDMA_ERR_DEV_DCON |
352 EDMA_ERR_DEV_CON |
353 EDMA_ERR_SERR |
354 EDMA_ERR_SELF_DIS |
6c1153e0 355 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 356 EDMA_ERR_CRPB_PAR |
357 EDMA_ERR_INTRL_PAR |
358 EDMA_ERR_IORDY |
359 EDMA_ERR_LNK_CTRL_RX_2 |
360 EDMA_ERR_LNK_DATA_RX |
361 EDMA_ERR_LNK_DATA_TX |
362 EDMA_ERR_TRANS_PROTO,
e12bef50 363
bdd4ddde
JG		 364 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
365 EDMA_ERR_PRD_PAR |
366 EDMA_ERR_DEV_DCON |
367 EDMA_ERR_DEV_CON |
368 EDMA_ERR_OVERRUN_5 |
369 EDMA_ERR_UNDERRUN_5 |
370 EDMA_ERR_SELF_DIS_5 |
6c1153e0 371 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 372 EDMA_ERR_CRPB_PAR |
373 EDMA_ERR_INTRL_PAR |
374 EDMA_ERR_IORDY,
20f733e7 375
31961943
BR		 376 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
377 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 378
379 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
380 EDMA_REQ_Q_PTR_SHIFT = 5,
381
382 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
383 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
384 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 385 EDMA_RSP_Q_PTR_SHIFT = 3,
386
0ea9e179
JG		 387 EDMA_CMD_OFS = 0x28, /* EDMA command register */
388 EDMA_EN = (1 << 0), /* enable EDMA */
389 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
8e7decdb
ML		 390 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
391
392 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
393 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
394 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
20f733e7 395
8e7decdb
ML		 396 EDMA_IORDY_TMOUT_OFS = 0x34,
397 EDMA_ARB_CFG_OFS = 0x38,
398
399 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
c01e8a23 400 EDMA_UNKNOWN_RSVD_OFS = 0x6C, /* GenIIe unknown/reserved */
da14265e
ML		 401
402 BMDMA_CMD_OFS = 0x224, /* bmdma command register */
403 BMDMA_STATUS_OFS = 0x228, /* bmdma status register */
404 BMDMA_PRD_LOW_OFS = 0x22c, /* bmdma PRD addr 31:0 */
405 BMDMA_PRD_HIGH_OFS = 0x230, /* bmdma PRD addr 63:32 */
406
31961943
BR		 407 /* Host private flags (hp_flags) */
408 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 409 MV_HP_ERRATA_50XXB0 = (1 << 1),
410 MV_HP_ERRATA_50XXB2 = (1 << 2),
411 MV_HP_ERRATA_60X1B2 = (1 << 3),
412 MV_HP_ERRATA_60X1C0 = (1 << 4),
0ea9e179
JG		 413 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
414 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
415 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 416 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
616d4a98 417 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
1f398472 418 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
000b344f 419 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
20f733e7 420
31961943 421 /* Port private flags (pp_flags) */
0ea9e179 422 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 423 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
00f42eab 424 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
29d187bb 425 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
d16ab3f6 426 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
20f733e7
BR		 427};
428
ee9ccdf7
JG		 429#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
430#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 431#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
8e7decdb 432#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
1f398472 433#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
bca1c4eb 434
15a32632
LB		 435#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
436#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
437
095fec88 438enum {
baf14aa1
JG		 439 /* DMA boundary 0xffff is required by the s/g splitting
440 * we need on /length/ in mv_fill-sg().
441 */
442 MV_DMA_BOUNDARY = 0xffffU,
095fec88 443
0ea9e179
JG		 444 /* mask of register bits containing lower 32 bits
445 * of EDMA request queue DMA address
446 */
095fec88
JG		 447 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
448
0ea9e179 449 /* ditto, for response queue */
095fec88
JG		 450 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
451};
452
522479fb
JG		 453enum chip_type {
454 chip_504x,
455 chip_508x,
456 chip_5080,
457 chip_604x,
458 chip_608x,
e4e7b892
JG		 459 chip_6042,
460 chip_7042,
f351b2d6 461 chip_soc,
522479fb
JG		 462};
463
31961943
BR		 464/* Command ReQuest Block: 32B */
465struct mv_crqb {
e1469874
ML		 466 __le32 sg_addr;
467 __le32 sg_addr_hi;
468 __le16 ctrl_flags;
469 __le16 ata_cmd[11];
31961943 470};
20f733e7 471
e4e7b892 472struct mv_crqb_iie {
e1469874
ML		 473 __le32 addr;
474 __le32 addr_hi;
475 __le32 flags;
476 __le32 len;
477 __le32 ata_cmd[4];
e4e7b892
JG		 478};
479
31961943
BR		 480/* Command ResPonse Block: 8B */
481struct mv_crpb {
e1469874
ML		 482 __le16 id;
483 __le16 flags;
484 __le32 tmstmp;
20f733e7
BR		 485};
486
31961943
BR		 487/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
488struct mv_sg {
e1469874
ML		 489 __le32 addr;
490 __le32 flags_size;
491 __le32 addr_hi;
492 __le32 reserved;
31961943 493};
20f733e7 494
08da1759
ML		 495/*
496 * We keep a local cache of a few frequently accessed port
497 * registers here, to avoid having to read them (very slow)
498 * when switching between EDMA and non-EDMA modes.
499 */
500struct mv_cached_regs {
501 u32 fiscfg;
502 u32 ltmode;
503 u32 haltcond;
c01e8a23 504 u32 unknown_rsvd;
08da1759
ML		 505};
506
31961943
BR		 507struct mv_port_priv {
508 struct mv_crqb *crqb;
509 dma_addr_t crqb_dma;
510 struct mv_crpb *crpb;
511 dma_addr_t crpb_dma;
eb73d558
ML		 512 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
513 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
bdd4ddde
JG		 514
515 unsigned int req_idx;
516 unsigned int resp_idx;
517
31961943 518 u32 pp_flags;
08da1759 519 struct mv_cached_regs cached;
29d187bb 520 unsigned int delayed_eh_pmp_map;
31961943
BR		 521};
522
bca1c4eb
JG		 523struct mv_port_signal {
524 u32 amps;
525 u32 pre;
526};
527
02a121da
ML		 528struct mv_host_priv {
529 u32 hp_flags;
96e2c487 530 u32 main_irq_mask;
02a121da
ML		 531 struct mv_port_signal signal[8];
532 const struct mv_hw_ops *ops;
f351b2d6
SB		 533 int n_ports;
534 void __iomem *base;
7368f919
ML		 535 void __iomem *main_irq_cause_addr;
536 void __iomem *main_irq_mask_addr;
02a121da
ML		 537 u32 irq_cause_ofs;
538 u32 irq_mask_ofs;
539 u32 unmask_all_irqs;
da2fa9ba
ML		 540 /*
541 * These consistent DMA memory pools give us guaranteed
542 * alignment for hardware-accessed data structures,
543 * and less memory waste in accomplishing the alignment.
544 */
545 struct dma_pool *crqb_pool;
546 struct dma_pool *crpb_pool;
547 struct dma_pool *sg_tbl_pool;
02a121da
ML		 548};
549
47c2b677 550struct mv_hw_ops {
2a47ce06
JG		 551 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
552 unsigned int port);
47c2b677
JG		 553 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
554 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
555 void __iomem *mmio);
c9d39130
JG		 556 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
557 unsigned int n_hc);
522479fb 558 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 559 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
47c2b677
JG		 560};
561
82ef04fb
TH		 562static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
563static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
564static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
565static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
31961943
BR		 566static int mv_port_start(struct ata_port *ap);
567static void mv_port_stop(struct ata_port *ap);
3e4a1391 568static int mv_qc_defer(struct ata_queued_cmd *qc);
31961943 569static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 570static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 571static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
a1efdaba
TH		 572static int mv_hardreset(struct ata_link *link, unsigned int *class,
573 unsigned long deadline);
bdd4ddde
JG		 574static void mv_eh_freeze(struct ata_port *ap);
575static void mv_eh_thaw(struct ata_port *ap);
f273827e 576static void mv6_dev_config(struct ata_device *dev);
20f733e7 577
2a47ce06
JG		 578static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
579 unsigned int port);
47c2b677
JG		 580static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
581static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
582 void __iomem *mmio);
c9d39130
JG		 583static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
584 unsigned int n_hc);
522479fb 585static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 586static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
47c2b677 587
2a47ce06
JG		 588static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
589 unsigned int port);
47c2b677
JG		 590static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
591static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
592 void __iomem *mmio);
c9d39130
JG		 593static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
594 unsigned int n_hc);
522479fb 595static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
f351b2d6
SB		 596static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
597 void __iomem *mmio);
598static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
599 void __iomem *mmio);
600static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
601 void __iomem *mmio, unsigned int n_hc);
602static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
603 void __iomem *mmio);
604static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
7bb3c529 605static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
e12bef50 606static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130 607 unsigned int port_no);
e12bef50 608static int mv_stop_edma(struct ata_port *ap);
b562468c 609static int mv_stop_edma_engine(void __iomem *port_mmio);
00b81235 610static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
47c2b677 611
e49856d8
ML		 612static void mv_pmp_select(struct ata_port *ap, int pmp);
613static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
614 unsigned long deadline);
615static int mv_softreset(struct ata_link *link, unsigned int *class,
616 unsigned long deadline);
29d187bb 617static void mv_pmp_error_handler(struct ata_port *ap);
4c299ca3
ML		 618static void mv_process_crpb_entries(struct ata_port *ap,
619 struct mv_port_priv *pp);
47c2b677 620
da14265e
ML		 621static void mv_sff_irq_clear(struct ata_port *ap);
622static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
623static void mv_bmdma_setup(struct ata_queued_cmd *qc);
624static void mv_bmdma_start(struct ata_queued_cmd *qc);
625static void mv_bmdma_stop(struct ata_queued_cmd *qc);
626static u8 mv_bmdma_status(struct ata_port *ap);
d16ab3f6 627static u8 mv_sff_check_status(struct ata_port *ap);
da14265e 628
eb73d558
ML		 629/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
630 * because we have to allow room for worst case splitting of
631 * PRDs for 64K boundaries in mv_fill_sg().
632 */
c5d3e45a 633static struct scsi_host_template mv5_sht = {
68d1d07b 634 ATA_BASE_SHT(DRV_NAME),
baf14aa1 635 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a 636 .dma_boundary = MV_DMA_BOUNDARY,
c5d3e45a
JG		 637};
638
639static struct scsi_host_template mv6_sht = {
68d1d07b 640 ATA_NCQ_SHT(DRV_NAME),
138bfdd0 641 .can_queue = MV_MAX_Q_DEPTH - 1,
baf14aa1 642 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7 643 .dma_boundary = MV_DMA_BOUNDARY,
20f733e7
BR		 644};
645
029cfd6b
TH		 646static struct ata_port_operations mv5_ops = {
647 .inherits = &ata_sff_port_ops,
c9d39130 648
3e4a1391 649 .qc_defer = mv_qc_defer,
c9d39130
JG		 650 .qc_prep = mv_qc_prep,
651 .qc_issue = mv_qc_issue,
c9d39130 652
bdd4ddde
JG		 653 .freeze = mv_eh_freeze,
654 .thaw = mv_eh_thaw,
a1efdaba 655 .hardreset = mv_hardreset,
a1efdaba 656 .error_handler = ata_std_error_handler, /* avoid SFF EH */
029cfd6b 657 .post_internal_cmd = ATA_OP_NULL,
bdd4ddde 658
c9d39130
JG		 659 .scr_read = mv5_scr_read,
660 .scr_write = mv5_scr_write,
661
662 .port_start = mv_port_start,
663 .port_stop = mv_port_stop,
c9d39130
JG		 664};
665
029cfd6b
TH		 666static struct ata_port_operations mv6_ops = {
667 .inherits = &mv5_ops,
f273827e 668 .dev_config = mv6_dev_config,
20f733e7
BR		 669 .scr_read = mv_scr_read,
670 .scr_write = mv_scr_write,
671
e49856d8
ML		 672 .pmp_hardreset = mv_pmp_hardreset,
673 .pmp_softreset = mv_softreset,
674 .softreset = mv_softreset,
29d187bb 675 .error_handler = mv_pmp_error_handler,
da14265e 676
40f21b11 677 .sff_check_status = mv_sff_check_status,
da14265e
ML		 678 .sff_irq_clear = mv_sff_irq_clear,
679 .check_atapi_dma = mv_check_atapi_dma,
680 .bmdma_setup = mv_bmdma_setup,
681 .bmdma_start = mv_bmdma_start,
682 .bmdma_stop = mv_bmdma_stop,
683 .bmdma_status = mv_bmdma_status,
20f733e7
BR		 684};
685
029cfd6b
TH		 686static struct ata_port_operations mv_iie_ops = {
687 .inherits = &mv6_ops,
688 .dev_config = ATA_OP_NULL,
e4e7b892 689 .qc_prep = mv_qc_prep_iie,
e4e7b892
JG		 690};
691
98ac62de 692static const struct ata_port_info mv_port_info[] = {
20f733e7 693 { /* chip_504x */
91b1a84c 694 .flags = MV_GEN_I_FLAGS,
31961943 695 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 696 .udma_mask = ATA_UDMA6,
c9d39130 697 .port_ops = &mv5_ops,
20f733e7
BR		 698 },
699 { /* chip_508x */
91b1a84c 700 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
31961943 701 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 702 .udma_mask = ATA_UDMA6,
c9d39130 703 .port_ops = &mv5_ops,
20f733e7 704 },
47c2b677 705 { /* chip_5080 */
91b1a84c 706 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
47c2b677 707 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 708 .udma_mask = ATA_UDMA6,
c9d39130 709 .port_ops = &mv5_ops,
47c2b677 710 },
20f733e7 711 { /* chip_604x */
91b1a84c 712 .flags = MV_GEN_II_FLAGS,
31961943 713 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 714 .udma_mask = ATA_UDMA6,
c9d39130 715 .port_ops = &mv6_ops,
20f733e7
BR		 716 },
717 { /* chip_608x */
91b1a84c 718 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
31961943 719 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 720 .udma_mask = ATA_UDMA6,
c9d39130 721 .port_ops = &mv6_ops,
20f733e7 722 },
e4e7b892 723 { /* chip_6042 */
91b1a84c 724 .flags = MV_GEN_IIE_FLAGS,
e4e7b892 725 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 726 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 727 .port_ops = &mv_iie_ops,
728 },
729 { /* chip_7042 */
91b1a84c 730 .flags = MV_GEN_IIE_FLAGS,
e4e7b892 731 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 732 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 733 .port_ops = &mv_iie_ops,
734 },
f351b2d6 735 { /* chip_soc */
91b1a84c 736 .flags = MV_GEN_IIE_FLAGS,
17c5aab5
ML		 737 .pio_mask = 0x1f, /* pio0-4 */
738 .udma_mask = ATA_UDMA6,
739 .port_ops = &mv_iie_ops,
f351b2d6 740 },
20f733e7
BR		 741};
742
3b7d697d 743static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 744 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
745 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
746 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
747 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
46c5784c
ML		 748 /* RocketRAID 1720/174x have different identifiers */
749 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
4462254a
ML		 750 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
751 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
2d2744fc
JG		 752
753 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
754 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
755 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
756 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
757 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
758
759 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
760
d9f9c6bc
FA		 761 /* Adaptec 1430SA */
762 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
763
02a121da 764 /* Marvell 7042 support */
6a3d586d
MT		 765 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
766
02a121da
ML		 767 /* Highpoint RocketRAID PCIe series */
768 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
769 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
770
2d2744fc 771 { } /* terminate list */
20f733e7
BR		 772};
773
47c2b677
JG		 774static const struct mv_hw_ops mv5xxx_ops = {
775 .phy_errata = mv5_phy_errata,
776 .enable_leds = mv5_enable_leds,
777 .read_preamp = mv5_read_preamp,
778 .reset_hc = mv5_reset_hc,
522479fb
JG		 779 .reset_flash = mv5_reset_flash,
780 .reset_bus = mv5_reset_bus,
47c2b677
JG		 781};
782
783static const struct mv_hw_ops mv6xxx_ops = {
784 .phy_errata = mv6_phy_errata,
785 .enable_leds = mv6_enable_leds,
786 .read_preamp = mv6_read_preamp,
787 .reset_hc = mv6_reset_hc,
522479fb
JG		 788 .reset_flash = mv6_reset_flash,
789 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 790};
791
f351b2d6
SB		 792static const struct mv_hw_ops mv_soc_ops = {
793 .phy_errata = mv6_phy_errata,
794 .enable_leds = mv_soc_enable_leds,
795 .read_preamp = mv_soc_read_preamp,
796 .reset_hc = mv_soc_reset_hc,
797 .reset_flash = mv_soc_reset_flash,
798 .reset_bus = mv_soc_reset_bus,
799};
800
20f733e7
BR		 801/*
802 * Functions
803 */
804
805static inline void writelfl(unsigned long data, void __iomem *addr)
806{
807 writel(data, addr);
808 (void) readl(addr); /* flush to avoid PCI posted write */
809}
810
c9d39130
JG		 811static inline unsigned int mv_hc_from_port(unsigned int port)
812{
813 return port >> MV_PORT_HC_SHIFT;
814}
815
816static inline unsigned int mv_hardport_from_port(unsigned int port)
817{
818 return port & MV_PORT_MASK;
819}
820
1cfd19ae
ML		 821/*
822 * Consolidate some rather tricky bit shift calculations.
823 * This is hot-path stuff, so not a function.
824 * Simple code, with two return values, so macro rather than inline.
825 *
826 * port is the sole input, in range 0..7.
7368f919
ML		 827 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
828 * hardport is the other output, in range 0..3.
1cfd19ae
ML		 829 *
830 * Note that port and hardport may be the same variable in some cases.
831 */
832#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
833{ \
834 shift = mv_hc_from_port(port) * HC_SHIFT; \
835 hardport = mv_hardport_from_port(port); \
836 shift += hardport * 2; \
837}
838
352fab70
ML		 839static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
840{
841 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
842}
843
c9d39130
JG		 844static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
845 unsigned int port)
846{
847 return mv_hc_base(base, mv_hc_from_port(port));
848}
849
20f733e7
BR		 850static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
851{
c9d39130 852 return mv_hc_base_from_port(base, port) +
8b260248 853 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 854 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 855}
856
e12bef50
ML		 857static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
858{
859 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
860 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
861
862 return hc_mmio + ofs;
863}
864
f351b2d6
SB		 865static inline void __iomem *mv_host_base(struct ata_host *host)
866{
867 struct mv_host_priv *hpriv = host->private_data;
868 return hpriv->base;
869}
870
20f733e7
BR		 871static inline void __iomem *mv_ap_base(struct ata_port *ap)
872{
f351b2d6 873 return mv_port_base(mv_host_base(ap->host), ap->port_no);
20f733e7
BR		 874}
875
cca3974e 876static inline int mv_get_hc_count(unsigned long port_flags)
31961943 877{
cca3974e 878 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 879}
880
08da1759
ML		 881/**
882 * mv_save_cached_regs - (re-)initialize cached port registers
883 * @ap: the port whose registers we are caching
884 *
885 * Initialize the local cache of port registers,
886 * so that reading them over and over again can
887 * be avoided on the hotter paths of this driver.
888 * This saves a few microseconds each time we switch
889 * to/from EDMA mode to perform (eg.) a drive cache flush.
890 */
891static void mv_save_cached_regs(struct ata_port *ap)
892{
893 void __iomem *port_mmio = mv_ap_base(ap);
894 struct mv_port_priv *pp = ap->private_data;
895
896 pp->cached.fiscfg = readl(port_mmio + FISCFG_OFS);
897 pp->cached.ltmode = readl(port_mmio + LTMODE_OFS);
898 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
c01e8a23 899 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD_OFS);
08da1759
ML		 900}
901
902/**
903 * mv_write_cached_reg - write to a cached port register
904 * @addr: hardware address of the register
905 * @old: pointer to cached value of the register
906 * @new: new value for the register
907 *
908 * Write a new value to a cached register,
909 * but only if the value is different from before.
910 */
911static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
912{
913 if (new != *old) {
914 *old = new;
915 writel(new, addr);
916 }
917}
918
c5d3e45a
JG		 919static void mv_set_edma_ptrs(void __iomem *port_mmio,
920 struct mv_host_priv *hpriv,
921 struct mv_port_priv *pp)
922{
bdd4ddde
JG		 923 u32 index;
924
c5d3e45a
JG		 925 /*
926 * initialize request queue
927 */
fcfb1f77
ML		 928 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
929 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
bdd4ddde 930
c5d3e45a
JG		 931 WARN_ON(pp->crqb_dma & 0x3ff);
932 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
bdd4ddde 933 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
c5d3e45a 934 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
5cf73bfb 935 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
c5d3e45a
JG		 936
937 /*
938 * initialize response queue
939 */
fcfb1f77
ML		 940 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
941 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
bdd4ddde 942
c5d3e45a
JG		 943 WARN_ON(pp->crpb_dma & 0xff);
944 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
5cf73bfb 945 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
bdd4ddde 946 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
c5d3e45a 947 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
c5d3e45a
JG		 948}
949
2b748a0a
ML		 950static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
951{
952 /*
953 * When writing to the main_irq_mask in hardware,
954 * we must ensure exclusivity between the interrupt coalescing bits
955 * and the corresponding individual port DONE_IRQ bits.
956 *
957 * Note that this register is really an "IRQ enable" register,
958 * not an "IRQ mask" register as Marvell's naming might suggest.
959 */
960 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
961 mask &= ~DONE_IRQ_0_3;
962 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
963 mask &= ~DONE_IRQ_4_7;
964 writelfl(mask, hpriv->main_irq_mask_addr);
965}
966
c4de573b
ML		 967static void mv_set_main_irq_mask(struct ata_host *host,
968 u32 disable_bits, u32 enable_bits)
969{
970 struct mv_host_priv *hpriv = host->private_data;
971 u32 old_mask, new_mask;
972
96e2c487 973 old_mask = hpriv->main_irq_mask;
c4de573b 974 new_mask = (old_mask & ~disable_bits) | enable_bits;
96e2c487
ML		 975 if (new_mask != old_mask) {
976 hpriv->main_irq_mask = new_mask;
2b748a0a 977 mv_write_main_irq_mask(new_mask, hpriv);
96e2c487 978 }
c4de573b
ML		 979}
980
981static void mv_enable_port_irqs(struct ata_port *ap,
982 unsigned int port_bits)
983{
984 unsigned int shift, hardport, port = ap->port_no;
985 u32 disable_bits, enable_bits;
986
987 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
988
989 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
990 enable_bits = port_bits << shift;
991 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
992}
993
00b81235
ML		 994static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
995 void __iomem *port_mmio,
996 unsigned int port_irqs)
997{
998 struct mv_host_priv *hpriv = ap->host->private_data;
999 int hardport = mv_hardport_from_port(ap->port_no);
1000 void __iomem *hc_mmio = mv_hc_base_from_port(
1001 mv_host_base(ap->host), ap->port_no);
1002 u32 hc_irq_cause;
1003
1004 /* clear EDMA event indicators, if any */
1005 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1006
1007 /* clear pending irq events */
1008 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
1009 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1010
1011 /* clear FIS IRQ Cause */
1012 if (IS_GEN_IIE(hpriv))
1013 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1014
1015 mv_enable_port_irqs(ap, port_irqs);
1016}
1017
2b748a0a
ML		 1018static void mv_set_irq_coalescing(struct ata_host *host,
1019 unsigned int count, unsigned int usecs)
1020{
1021 struct mv_host_priv *hpriv = host->private_data;
1022 void __iomem *mmio = hpriv->base, *hc_mmio;
1023 u32 coal_enable = 0;
1024 unsigned long flags;
6abf4678 1025 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
2b748a0a
ML		 1026 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1027 ALL_PORTS_COAL_DONE;
1028
1029 /* Disable IRQ coalescing if either threshold is zero */
1030 if (!usecs || !count) {
1031 clks = count = 0;
1032 } else {
1033 /* Respect maximum limits of the hardware */
1034 clks = usecs * COAL_CLOCKS_PER_USEC;
1035 if (clks > MAX_COAL_TIME_THRESHOLD)
1036 clks = MAX_COAL_TIME_THRESHOLD;
1037 if (count > MAX_COAL_IO_COUNT)
1038 count = MAX_COAL_IO_COUNT;
1039 }
1040
1041 spin_lock_irqsave(&host->lock, flags);
6abf4678 1042 mv_set_main_irq_mask(host, coal_disable, 0);
2b748a0a 1043
6abf4678 1044 if (is_dual_hc && !IS_GEN_I(hpriv)) {
2b748a0a 1045 /*
6abf4678
ML		 1046 * GEN_II/GEN_IIE with dual host controllers:
1047 * one set of global thresholds for the entire chip.
2b748a0a
ML		 1048 */
1049 writel(clks, mmio + MV_IRQ_COAL_TIME_THRESHOLD);
1050 writel(count, mmio + MV_IRQ_COAL_IO_THRESHOLD);
1051 /* clear leftover coal IRQ bit */
6abf4678
ML		 1052 writel(~ALL_PORTS_COAL_IRQ, mmio + MV_IRQ_COAL_CAUSE);
1053 if (count)
1054 coal_enable = ALL_PORTS_COAL_DONE;
1055 clks = count = 0; /* force clearing of regular regs below */
2b748a0a 1056 }
6abf4678 1057
2b748a0a
ML		 1058 /*
1059 * All chips: independent thresholds for each HC on the chip.
1060 */
1061 hc_mmio = mv_hc_base_from_port(mmio, 0);
1062 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD_OFS);
1063 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD_OFS);
6abf4678
ML		 1064 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE_OFS);
1065 if (count)
1066 coal_enable |= PORTS_0_3_COAL_DONE;
1067 if (is_dual_hc) {
2b748a0a
ML		 1068 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
1069 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD_OFS);
1070 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD_OFS);
6abf4678
ML		 1071 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE_OFS);
1072 if (count)
1073 coal_enable |= PORTS_4_7_COAL_DONE;
2b748a0a 1074 }
2b748a0a 1075
6abf4678 1076 mv_set_main_irq_mask(host, 0, coal_enable);
2b748a0a
ML		 1077 spin_unlock_irqrestore(&host->lock, flags);
1078}
1079
05b308e1 1080/**
00b81235 1081 * mv_start_edma - Enable eDMA engine
05b308e1
BR		 1082 * @base: port base address
1083 * @pp: port private data
1084 *
beec7dbc
TH		 1085 * Verify the local cache of the eDMA state is accurate with a
1086 * WARN_ON.
05b308e1
BR		 1087 *
1088 * LOCKING:
1089 * Inherited from caller.
1090 */
00b81235 1091static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
72109168 1092 struct mv_port_priv *pp, u8 protocol)
20f733e7 1093{
72109168
ML		 1094 int want_ncq = (protocol == ATA_PROT_NCQ);
1095
1096 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1097 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1098 if (want_ncq != using_ncq)
b562468c 1099 mv_stop_edma(ap);
72109168 1100 }
c5d3e45a 1101 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e 1102 struct mv_host_priv *hpriv = ap->host->private_data;
0c58912e 1103
00b81235 1104 mv_edma_cfg(ap, want_ncq, 1);
0c58912e 1105
f630d562 1106 mv_set_edma_ptrs(port_mmio, hpriv, pp);
00b81235 1107 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
bdd4ddde 1108
f630d562 1109 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
afb0edd9
BR		 1110 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1111 }
20f733e7
BR		 1112}
1113
9b2c4e0b
ML		 1114static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1115{
1116 void __iomem *port_mmio = mv_ap_base(ap);
1117 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1118 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1119 int i;
1120
1121 /*
1122 * Wait for the EDMA engine to finish transactions in progress.
c46938cc
ML		 1123 * No idea what a good "timeout" value might be, but measurements
1124 * indicate that it often requires hundreds of microseconds
1125 * with two drives in-use. So we use the 15msec value above
1126 * as a rough guess at what even more drives might require.
9b2c4e0b
ML		 1127 */
1128 for (i = 0; i < timeout; ++i) {
1129 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
1130 if ((edma_stat & empty_idle) == empty_idle)
1131 break;
1132 udelay(per_loop);
1133 }
1134 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
1135}
1136
05b308e1 1137/**
e12bef50 1138 * mv_stop_edma_engine - Disable eDMA engine
b562468c 1139 * @port_mmio: io base address
05b308e1
BR		 1140 *
1141 * LOCKING:
1142 * Inherited from caller.
1143 */
b562468c 1144static int mv_stop_edma_engine(void __iomem *port_mmio)
20f733e7 1145{
b562468c 1146 int i;
31961943 1147
b562468c
ML		 1148 /* Disable eDMA. The disable bit auto clears. */
1149 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
8b260248 1150
b562468c
ML		 1151 /* Wait for the chip to confirm eDMA is off. */
1152 for (i = 10000; i > 0; i--) {
1153 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
4537deb5 1154 if (!(reg & EDMA_EN))
b562468c
ML		 1155 return 0;
1156 udelay(10);
31961943 1157 }
b562468c 1158 return -EIO;
20f733e7
BR		 1159}
1160
e12bef50 1161static int mv_stop_edma(struct ata_port *ap)
0ea9e179 1162{
b562468c
ML		 1163 void __iomem *port_mmio = mv_ap_base(ap);
1164 struct mv_port_priv *pp = ap->private_data;
66e57a2c 1165 int err = 0;
0ea9e179 1166
b562468c
ML		 1167 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1168 return 0;
1169 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
9b2c4e0b 1170 mv_wait_for_edma_empty_idle(ap);
b562468c
ML		 1171 if (mv_stop_edma_engine(port_mmio)) {
1172 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
66e57a2c 1173 err = -EIO;
b562468c 1174 }
66e57a2c
ML		 1175 mv_edma_cfg(ap, 0, 0);
1176 return err;
0ea9e179
JG		 1177}
1178
8a70f8dc 1179#ifdef ATA_DEBUG
31961943 1180static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 1181{
31961943
BR		 1182 int b, w;
1183 for (b = 0; b < bytes; ) {
1184 DPRINTK("%p: ", start + b);
1185 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 1186 printk("%08x ", readl(start + b));
31961943
BR		 1187 b += sizeof(u32);
1188 }
1189 printk("\n");
1190 }
31961943 1191}
8a70f8dc
JG		 1192#endif
1193
31961943
BR		 1194static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1195{
1196#ifdef ATA_DEBUG
1197 int b, w;
1198 u32 dw;
1199 for (b = 0; b < bytes; ) {
1200 DPRINTK("%02x: ", b);
1201 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 1202 (void) pci_read_config_dword(pdev, b, &dw);
1203 printk("%08x ", dw);
31961943
BR		 1204 b += sizeof(u32);
1205 }
1206 printk("\n");
1207 }
1208#endif
1209}
1210static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1211 struct pci_dev *pdev)
1212{
1213#ifdef ATA_DEBUG
8b260248 1214 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 1215 port >> MV_PORT_HC_SHIFT);
1216 void __iomem *port_base;
1217 int start_port, num_ports, p, start_hc, num_hcs, hc;
1218
1219 if (0 > port) {
1220 start_hc = start_port = 0;
1221 num_ports = 8; /* shld be benign for 4 port devs */
1222 num_hcs = 2;
1223 } else {
1224 start_hc = port >> MV_PORT_HC_SHIFT;
1225 start_port = port;
1226 num_ports = num_hcs = 1;
1227 }
8b260248 1228 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 1229 num_ports > 1 ? num_ports - 1 : start_port);
1230
1231 if (NULL != pdev) {
1232 DPRINTK("PCI config space regs:\n");
1233 mv_dump_pci_cfg(pdev, 0x68);
1234 }
1235 DPRINTK("PCI regs:\n");
1236 mv_dump_mem(mmio_base+0xc00, 0x3c);
1237 mv_dump_mem(mmio_base+0xd00, 0x34);
1238 mv_dump_mem(mmio_base+0xf00, 0x4);
1239 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1240 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 1241 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 1242 DPRINTK("HC regs (HC %i):\n", hc);
1243 mv_dump_mem(hc_base, 0x1c);
1244 }
1245 for (p = start_port; p < start_port + num_ports; p++) {
1246 port_base = mv_port_base(mmio_base, p);
2dcb407e 1247 DPRINTK("EDMA regs (port %i):\n", p);
31961943 1248 mv_dump_mem(port_base, 0x54);
2dcb407e 1249 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 1250 mv_dump_mem(port_base+0x300, 0x60);
1251 }
1252#endif
20f733e7
BR		 1253}
1254
1255static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1256{
1257 unsigned int ofs;
1258
1259 switch (sc_reg_in) {
1260 case SCR_STATUS:
1261 case SCR_CONTROL:
1262 case SCR_ERROR:
1263 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1264 break;
1265 case SCR_ACTIVE:
1266 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1267 break;
1268 default:
1269 ofs = 0xffffffffU;
1270 break;
1271 }
1272 return ofs;
1273}
1274
82ef04fb 1275static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1276{
1277 unsigned int ofs = mv_scr_offset(sc_reg_in);
1278
da3dbb17 1279 if (ofs != 0xffffffffU) {
82ef04fb 1280 *val = readl(mv_ap_base(link->ap) + ofs);
da3dbb17
TH		 1281 return 0;
1282 } else
1283 return -EINVAL;
20f733e7
BR		 1284}
1285
82ef04fb 1286static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1287{
1288 unsigned int ofs = mv_scr_offset(sc_reg_in);
1289
da3dbb17 1290 if (ofs != 0xffffffffU) {
82ef04fb 1291 writelfl(val, mv_ap_base(link->ap) + ofs);
da3dbb17
TH		 1292 return 0;
1293 } else
1294 return -EINVAL;
20f733e7
BR		 1295}
1296
f273827e
ML		 1297static void mv6_dev_config(struct ata_device *adev)
1298{
1299 /*
e49856d8
ML		 1300 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1301 *
1302 * Gen-II does not support NCQ over a port multiplier
1303 * (no FIS-based switching).
f273827e 1304 */
e49856d8 1305 if (adev->flags & ATA_DFLAG_NCQ) {
352fab70 1306 if (sata_pmp_attached(adev->link->ap)) {
e49856d8 1307 adev->flags &= ~ATA_DFLAG_NCQ;
352fab70
ML		 1308 ata_dev_printk(adev, KERN_INFO,
1309 "NCQ disabled for command-based switching\n");
352fab70 1310 }
e49856d8 1311 }
f273827e
ML		 1312}
1313
3e4a1391
ML		 1314static int mv_qc_defer(struct ata_queued_cmd *qc)
1315{
1316 struct ata_link *link = qc->dev->link;
1317 struct ata_port *ap = link->ap;
1318 struct mv_port_priv *pp = ap->private_data;
1319
29d187bb
ML		 1320 /*
1321 * Don't allow new commands if we're in a delayed EH state
1322 * for NCQ and/or FIS-based switching.
1323 */
1324 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1325 return ATA_DEFER_PORT;
3e4a1391
ML		 1326 /*
1327 * If the port is completely idle, then allow the new qc.
1328 */
1329 if (ap->nr_active_links == 0)
1330 return 0;
1331
4bdee6c5
TH		 1332 /*
1333 * The port is operating in host queuing mode (EDMA) with NCQ
1334 * enabled, allow multiple NCQ commands. EDMA also allows
1335 * queueing multiple DMA commands but libata core currently
1336 * doesn't allow it.
1337 */
1338 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1339 (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol))
1340 return 0;
1341
3e4a1391
ML		 1342 return ATA_DEFER_PORT;
1343}
1344
08da1759 1345static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
e49856d8 1346{
08da1759
ML		 1347 struct mv_port_priv *pp = ap->private_data;
1348 void __iomem *port_mmio;
00f42eab 1349
08da1759
ML		 1350 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1351 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1352 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
00f42eab 1353
08da1759
ML		 1354 ltmode = *old_ltmode & ~LTMODE_BIT8;
1355 haltcond = *old_haltcond | EDMA_ERR_DEV;
00f42eab
ML		 1356
1357 if (want_fbs) {
08da1759
ML		 1358 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1359 ltmode = *old_ltmode | LTMODE_BIT8;
4c299ca3 1360 if (want_ncq)
08da1759 1361 haltcond &= ~EDMA_ERR_DEV;
4c299ca3 1362 else
08da1759
ML		 1363 fiscfg |= FISCFG_WAIT_DEV_ERR;
1364 } else {
1365 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
e49856d8 1366 }
00f42eab 1367
08da1759
ML		 1368 port_mmio = mv_ap_base(ap);
1369 mv_write_cached_reg(port_mmio + FISCFG_OFS, old_fiscfg, fiscfg);
1370 mv_write_cached_reg(port_mmio + LTMODE_OFS, old_ltmode, ltmode);
1371 mv_write_cached_reg(port_mmio + EDMA_HALTCOND_OFS, old_haltcond, haltcond);
f273827e
ML		 1372}
1373
dd2890f6
ML		 1374static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1375{
1376 struct mv_host_priv *hpriv = ap->host->private_data;
1377 u32 old, new;
1378
1379 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1380 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1381 if (want_ncq)
1382 new = old | (1 << 22);
1383 else
1384 new = old & ~(1 << 22);
1385 if (new != old)
1386 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1387}
1388
c01e8a23 1389/**
40f21b11
ML		 1390 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1391 * @ap: Port being initialized
c01e8a23
ML		 1392 *
1393 * There are two DMA modes on these chips: basic DMA, and EDMA.
1394 *
1395 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1396 * of basic DMA on the GEN_IIE versions of the chips.
1397 *
1398 * This bit survives EDMA resets, and must be set for basic DMA
1399 * to function, and should be cleared when EDMA is active.
1400 */
1401static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1402{
1403 struct mv_port_priv *pp = ap->private_data;
1404 u32 new, *old = &pp->cached.unknown_rsvd;
1405
1406 if (enable_bmdma)
1407 new = *old | 1;
1408 else
1409 new = *old & ~1;
1410 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD_OFS, old, new);
1411}
1412
000b344f
ML		 1413/*
1414 * SOC chips have an issue whereby the HDD LEDs don't always blink
1415 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1416 * of the SOC takes care of it, generating a steady blink rate when
1417 * any drive on the chip is active.
1418 *
1419 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1420 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1421 *
1422 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1423 * LED operation works then, and provides better (more accurate) feedback.
1424 *
1425 * Note that this code assumes that an SOC never has more than one HC onboard.
1426 */
1427static void mv_soc_led_blink_enable(struct ata_port *ap)
1428{
1429 struct ata_host *host = ap->host;
1430 struct mv_host_priv *hpriv = host->private_data;
1431 void __iomem *hc_mmio;
1432 u32 led_ctrl;
1433
1434 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1435 return;
1436 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1437 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1438 led_ctrl = readl(hc_mmio + SOC_LED_CTRL_OFS);
1439 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL_OFS);
1440}
1441
1442static void mv_soc_led_blink_disable(struct ata_port *ap)
1443{
1444 struct ata_host *host = ap->host;
1445 struct mv_host_priv *hpriv = host->private_data;
1446 void __iomem *hc_mmio;
1447 u32 led_ctrl;
1448 unsigned int port;
1449
1450 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1451 return;
1452
1453 /* disable led-blink only if no ports are using NCQ */
1454 for (port = 0; port < hpriv->n_ports; port++) {
1455 struct ata_port *this_ap = host->ports[port];
1456 struct mv_port_priv *pp = this_ap->private_data;
1457
1458 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1459 return;
1460 }
1461
1462 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1463 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1464 led_ctrl = readl(hc_mmio + SOC_LED_CTRL_OFS);
1465 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL_OFS);
1466}
1467
00b81235 1468static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
e4e7b892 1469{
0c58912e 1470 u32 cfg;
e12bef50
ML		 1471 struct mv_port_priv *pp = ap->private_data;
1472 struct mv_host_priv *hpriv = ap->host->private_data;
1473 void __iomem *port_mmio = mv_ap_base(ap);
e4e7b892
JG		 1474
1475 /* set up non-NCQ EDMA configuration */
0c58912e 1476 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
d16ab3f6
ML		 1477 pp->pp_flags &=
1478 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
e4e7b892 1479
0c58912e 1480 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1481 cfg |= (1 << 8); /* enab config burst size mask */
1482
dd2890f6 1483 else if (IS_GEN_II(hpriv)) {
e4e7b892 1484 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
dd2890f6 1485 mv_60x1_errata_sata25(ap, want_ncq);
e4e7b892 1486
dd2890f6 1487 } else if (IS_GEN_IIE(hpriv)) {
00f42eab
ML		 1488 int want_fbs = sata_pmp_attached(ap);
1489 /*
1490 * Possible future enhancement:
1491 *
1492 * The chip can use FBS with non-NCQ, if we allow it,
1493 * But first we need to have the error handling in place
1494 * for this mode (datasheet section 7.3.15.4.2.3).
1495 * So disallow non-NCQ FBS for now.
1496 */
1497 want_fbs &= want_ncq;
1498
08da1759 1499 mv_config_fbs(ap, want_ncq, want_fbs);
00f42eab
ML		 1500
1501 if (want_fbs) {
1502 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1503 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1504 }
1505
e728eabe 1506 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
00b81235
ML		 1507 if (want_edma) {
1508 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1509 if (!IS_SOC(hpriv))
1510 cfg |= (1 << 18); /* enab early completion */
1511 }
616d4a98
ML		 1512 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1513 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
c01e8a23 1514 mv_bmdma_enable_iie(ap, !want_edma);
000b344f
ML		 1515
1516 if (IS_SOC(hpriv)) {
1517 if (want_ncq)
1518 mv_soc_led_blink_enable(ap);
1519 else
1520 mv_soc_led_blink_disable(ap);
1521 }
e4e7b892
JG		 1522 }
1523
72109168
ML		 1524 if (want_ncq) {
1525 cfg |= EDMA_CFG_NCQ;
1526 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
00b81235 1527 }
72109168 1528
e4e7b892
JG		 1529 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1530}
1531
da2fa9ba
ML		 1532static void mv_port_free_dma_mem(struct ata_port *ap)
1533{
1534 struct mv_host_priv *hpriv = ap->host->private_data;
1535 struct mv_port_priv *pp = ap->private_data;
eb73d558 1536 int tag;
da2fa9ba
ML		 1537
1538 if (pp->crqb) {
1539 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1540 pp->crqb = NULL;
1541 }
1542 if (pp->crpb) {
1543 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1544 pp->crpb = NULL;
1545 }
eb73d558
ML		 1546 /*
1547 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1548 * For later hardware, we have one unique sg_tbl per NCQ tag.
1549 */
1550 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1551 if (pp->sg_tbl[tag]) {
1552 if (tag == 0 || !IS_GEN_I(hpriv))
1553 dma_pool_free(hpriv->sg_tbl_pool,
1554 pp->sg_tbl[tag],
1555 pp->sg_tbl_dma[tag]);
1556 pp->sg_tbl[tag] = NULL;
1557 }
da2fa9ba
ML		 1558 }
1559}
1560
05b308e1
BR		 1561/**
1562 * mv_port_start - Port specific init/start routine.
1563 * @ap: ATA channel to manipulate
1564 *
1565 * Allocate and point to DMA memory, init port private memory,
1566 * zero indices.
1567 *
1568 * LOCKING:
1569 * Inherited from caller.
1570 */
31961943
BR		 1571static int mv_port_start(struct ata_port *ap)
1572{
cca3974e
JG		 1573 struct device *dev = ap->host->dev;
1574 struct mv_host_priv *hpriv = ap->host->private_data;
31961943 1575 struct mv_port_priv *pp;
dde20207 1576 int tag;
31961943 1577
24dc5f33 1578 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1579 if (!pp)
24dc5f33 1580 return -ENOMEM;
da2fa9ba 1581 ap->private_data = pp;
31961943 1582
da2fa9ba
ML		 1583 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1584 if (!pp->crqb)
1585 return -ENOMEM;
1586 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
31961943 1587
da2fa9ba
ML		 1588 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1589 if (!pp->crpb)
1590 goto out_port_free_dma_mem;
1591 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
31961943 1592
3bd0a70e
ML		 1593 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1594 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1595 ap->flags |= ATA_FLAG_AN;
eb73d558
ML		 1596 /*
1597 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1598 * For later hardware, we need one unique sg_tbl per NCQ tag.
1599 */
1600 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1601 if (tag == 0 || !IS_GEN_I(hpriv)) {
1602 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1603 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1604 if (!pp->sg_tbl[tag])
1605 goto out_port_free_dma_mem;
1606 } else {
1607 pp->sg_tbl[tag] = pp->sg_tbl[0];
1608 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1609 }
1610 }
08da1759 1611 mv_save_cached_regs(ap);
66e57a2c 1612 mv_edma_cfg(ap, 0, 0);
31961943 1613 return 0;
da2fa9ba
ML		 1614
1615out_port_free_dma_mem:
1616 mv_port_free_dma_mem(ap);
1617 return -ENOMEM;
31961943
BR		 1618}
1619
05b308e1
BR		 1620/**
1621 * mv_port_stop - Port specific cleanup/stop routine.
1622 * @ap: ATA channel to manipulate
1623 *
1624 * Stop DMA, cleanup port memory.
1625 *
1626 * LOCKING:
cca3974e 1627 * This routine uses the host lock to protect the DMA stop.
05b308e1 1628 */
31961943
BR		 1629static void mv_port_stop(struct ata_port *ap)
1630{
e12bef50 1631 mv_stop_edma(ap);
88e675e1 1632 mv_enable_port_irqs(ap, 0);
da2fa9ba 1633 mv_port_free_dma_mem(ap);
31961943
BR		 1634}
1635
05b308e1
BR		 1636/**
1637 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1638 * @qc: queued command whose SG list to source from
1639 *
1640 * Populate the SG list and mark the last entry.
1641 *
1642 * LOCKING:
1643 * Inherited from caller.
1644 */
6c08772e 1645static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1646{
1647 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1648 struct scatterlist *sg;
3be6cbd7 1649 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1650 unsigned int si;
31961943 1651
eb73d558 1652 mv_sg = pp->sg_tbl[qc->tag];
ff2aeb1e 1653 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1654 dma_addr_t addr = sg_dma_address(sg);
1655 u32 sg_len = sg_dma_len(sg);
22374677 1656
4007b493
OJ		 1657 while (sg_len) {
1658 u32 offset = addr & 0xffff;
1659 u32 len = sg_len;
22374677 1660
32cd11a6 1661 if (offset + len > 0x10000)
4007b493
OJ		 1662 len = 0x10000 - offset;
1663
1664 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1665 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1666 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
32cd11a6 1667 mv_sg->reserved = 0;
4007b493
OJ		 1668
1669 sg_len -= len;
1670 addr += len;
1671
3be6cbd7 1672 last_sg = mv_sg;
4007b493 1673 mv_sg++;
4007b493 1674 }
31961943 1675 }
3be6cbd7
JG		 1676
1677 if (likely(last_sg))
1678 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
32cd11a6 1679 mb(); /* ensure data structure is visible to the chipset */
31961943
BR		 1680}
1681
5796d1c4 1682static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1683{
559eedad 1684 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1685 (last ? CRQB_CMD_LAST : 0);
559eedad 1686 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1687}
1688
da14265e
ML		 1689/**
1690 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1691 * @ap: Port associated with this ATA transaction.
1692 *
1693 * We need this only for ATAPI bmdma transactions,
1694 * as otherwise we experience spurious interrupts
1695 * after libata-sff handles the bmdma interrupts.
1696 */
1697static void mv_sff_irq_clear(struct ata_port *ap)
1698{
1699 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1700}
1701
1702/**
1703 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1704 * @qc: queued command to check for chipset/DMA compatibility.
1705 *
1706 * The bmdma engines cannot handle speculative data sizes
1707 * (bytecount under/over flow). So only allow DMA for
1708 * data transfer commands with known data sizes.
1709 *
1710 * LOCKING:
1711 * Inherited from caller.
1712 */
1713static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1714{
1715 struct scsi_cmnd *scmd = qc->scsicmd;
1716
1717 if (scmd) {
1718 switch (scmd->cmnd[0]) {
1719 case READ_6:
1720 case READ_10:
1721 case READ_12:
1722 case WRITE_6:
1723 case WRITE_10:
1724 case WRITE_12:
1725 case GPCMD_READ_CD:
1726 case GPCMD_SEND_DVD_STRUCTURE:
1727 case GPCMD_SEND_CUE_SHEET:
1728 return 0; /* DMA is safe */
1729 }
1730 }
1731 return -EOPNOTSUPP; /* use PIO instead */
1732}
1733
1734/**
1735 * mv_bmdma_setup - Set up BMDMA transaction
1736 * @qc: queued command to prepare DMA for.
1737 *
1738 * LOCKING:
1739 * Inherited from caller.
1740 */
1741static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1742{
1743 struct ata_port *ap = qc->ap;
1744 void __iomem *port_mmio = mv_ap_base(ap);
1745 struct mv_port_priv *pp = ap->private_data;
1746
1747 mv_fill_sg(qc);
1748
1749 /* clear all DMA cmd bits */
1750 writel(0, port_mmio + BMDMA_CMD_OFS);
1751
1752 /* load PRD table addr. */
1753 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
1754 port_mmio + BMDMA_PRD_HIGH_OFS);
1755 writelfl(pp->sg_tbl_dma[qc->tag],
1756 port_mmio + BMDMA_PRD_LOW_OFS);
1757
1758 /* issue r/w command */
1759 ap->ops->sff_exec_command(ap, &qc->tf);
1760}
1761
1762/**
1763 * mv_bmdma_start - Start a BMDMA transaction
1764 * @qc: queued command to start DMA on.
1765 *
1766 * LOCKING:
1767 * Inherited from caller.
1768 */
1769static void mv_bmdma_start(struct ata_queued_cmd *qc)
1770{
1771 struct ata_port *ap = qc->ap;
1772 void __iomem *port_mmio = mv_ap_base(ap);
1773 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1774 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1775
1776 /* start host DMA transaction */
1777 writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
1778}
1779
1780/**
1781 * mv_bmdma_stop - Stop BMDMA transfer
1782 * @qc: queued command to stop DMA on.
1783 *
1784 * Clears the ATA_DMA_START flag in the bmdma control register
1785 *
1786 * LOCKING:
1787 * Inherited from caller.
1788 */
1789static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1790{
1791 struct ata_port *ap = qc->ap;
1792 void __iomem *port_mmio = mv_ap_base(ap);
1793 u32 cmd;
1794
1795 /* clear start/stop bit */
1796 cmd = readl(port_mmio + BMDMA_CMD_OFS);
1797 cmd &= ~ATA_DMA_START;
1798 writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
1799
1800 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1801 ata_sff_dma_pause(ap);
1802}
1803
1804/**
1805 * mv_bmdma_status - Read BMDMA status
1806 * @ap: port for which to retrieve DMA status.
1807 *
1808 * Read and return equivalent of the sff BMDMA status register.
1809 *
1810 * LOCKING:
1811 * Inherited from caller.
1812 */
1813static u8 mv_bmdma_status(struct ata_port *ap)
1814{
1815 void __iomem *port_mmio = mv_ap_base(ap);
1816 u32 reg, status;
1817
1818 /*
1819 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1820 * and the ATA_DMA_INTR bit doesn't exist.
1821 */
1822 reg = readl(port_mmio + BMDMA_STATUS_OFS);
1823 if (reg & ATA_DMA_ACTIVE)
1824 status = ATA_DMA_ACTIVE;
1825 else
1826 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1827 return status;
1828}
1829
05b308e1
BR		 1830/**
1831 * mv_qc_prep - Host specific command preparation.
1832 * @qc: queued command to prepare
1833 *
1834 * This routine simply redirects to the general purpose routine
1835 * if command is not DMA. Else, it handles prep of the CRQB
1836 * (command request block), does some sanity checking, and calls
1837 * the SG load routine.
1838 *
1839 * LOCKING:
1840 * Inherited from caller.
1841 */
31961943
BR		 1842static void mv_qc_prep(struct ata_queued_cmd *qc)
1843{
1844 struct ata_port *ap = qc->ap;
1845 struct mv_port_priv *pp = ap->private_data;
e1469874 1846 __le16 *cw;
31961943
BR		 1847 struct ata_taskfile *tf;
1848 u16 flags = 0;
a6432436 1849 unsigned in_index;
31961943 1850
138bfdd0
ML		 1851 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1852 (qc->tf.protocol != ATA_PROT_NCQ))
31961943 1853 return;
20f733e7 1854
31961943
BR		 1855 /* Fill in command request block
1856 */
e4e7b892 1857 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1858 flags |= CRQB_FLAG_READ;
beec7dbc 1859 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943 1860 flags |= qc->tag << CRQB_TAG_SHIFT;
e49856d8 1861 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
31961943 1862
bdd4ddde 1863 /* get current queue index from software */
fcfb1f77 1864 in_index = pp->req_idx;
a6432436
ML		 1865
1866 pp->crqb[in_index].sg_addr =
eb73d558 1867 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
a6432436 1868 pp->crqb[in_index].sg_addr_hi =
eb73d558 1869 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
a6432436 1870 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1871
a6432436 1872 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1873 tf = &qc->tf;
1874
1875 /* Sadly, the CRQB cannot accomodate all registers--there are
1876 * only 11 bytes...so we must pick and choose required
1877 * registers based on the command. So, we drop feature and
1878 * hob_feature for [RW] DMA commands, but they are needed for
cd12e1f7
ML		 1879 * NCQ. NCQ will drop hob_nsect, which is not needed there
1880 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
20f733e7 1881 */
31961943
BR		 1882 switch (tf->command) {
1883 case ATA_CMD_READ:
1884 case ATA_CMD_READ_EXT:
1885 case ATA_CMD_WRITE:
1886 case ATA_CMD_WRITE_EXT:
c15d85c8 1887 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1888 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1889 break;
31961943
BR		 1890 case ATA_CMD_FPDMA_READ:
1891 case ATA_CMD_FPDMA_WRITE:
8b260248 1892 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1893 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1894 break;
31961943
BR		 1895 default:
1896 /* The only other commands EDMA supports in non-queued and
1897 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1898 * of which are defined/used by Linux. If we get here, this
1899 * driver needs work.
1900 *
1901 * FIXME: modify libata to give qc_prep a return value and
1902 * return error here.
1903 */
1904 BUG_ON(tf->command);
1905 break;
1906 }
1907 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1908 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1909 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1910 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1911 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1912 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1913 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1914 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1915 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1916
e4e7b892
JG		 1917 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1918 return;
1919 mv_fill_sg(qc);
1920}
1921
1922/**
1923 * mv_qc_prep_iie - Host specific command preparation.
1924 * @qc: queued command to prepare
1925 *
1926 * This routine simply redirects to the general purpose routine
1927 * if command is not DMA. Else, it handles prep of the CRQB
1928 * (command request block), does some sanity checking, and calls
1929 * the SG load routine.
1930 *
1931 * LOCKING:
1932 * Inherited from caller.
1933 */
1934static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1935{
1936 struct ata_port *ap = qc->ap;
1937 struct mv_port_priv *pp = ap->private_data;
1938 struct mv_crqb_iie *crqb;
1939 struct ata_taskfile *tf;
a6432436 1940 unsigned in_index;
e4e7b892
JG		 1941 u32 flags = 0;
1942
138bfdd0
ML		 1943 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1944 (qc->tf.protocol != ATA_PROT_NCQ))
e4e7b892
JG		 1945 return;
1946
e12bef50 1947 /* Fill in Gen IIE command request block */
e4e7b892
JG		 1948 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1949 flags |= CRQB_FLAG_READ;
1950
beec7dbc 1951 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 1952 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 1953 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e49856d8 1954 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
e4e7b892 1955
bdd4ddde 1956 /* get current queue index from software */
fcfb1f77 1957 in_index = pp->req_idx;
a6432436
ML		 1958
1959 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
eb73d558
ML		 1960 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1961 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
e4e7b892
JG		 1962 crqb->flags = cpu_to_le32(flags);
1963
1964 tf = &qc->tf;
1965 crqb->ata_cmd[0] = cpu_to_le32(
1966 (tf->command << 16) |
1967 (tf->feature << 24)
1968 );
1969 crqb->ata_cmd[1] = cpu_to_le32(
1970 (tf->lbal << 0) |
1971 (tf->lbam << 8) |
1972 (tf->lbah << 16) |
1973 (tf->device << 24)
1974 );
1975 crqb->ata_cmd[2] = cpu_to_le32(
1976 (tf->hob_lbal << 0) |
1977 (tf->hob_lbam << 8) |
1978 (tf->hob_lbah << 16) |
1979 (tf->hob_feature << 24)
1980 );
1981 crqb->ata_cmd[3] = cpu_to_le32(
1982 (tf->nsect << 0) |
1983 (tf->hob_nsect << 8)
1984 );
1985
1986 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1987 return;
31961943
BR		 1988 mv_fill_sg(qc);
1989}
1990
d16ab3f6
ML		 1991/**
1992 * mv_sff_check_status - fetch device status, if valid
1993 * @ap: ATA port to fetch status from
1994 *
1995 * When using command issue via mv_qc_issue_fis(),
1996 * the initial ATA_BUSY state does not show up in the
1997 * ATA status (shadow) register. This can confuse libata!
1998 *
1999 * So we have a hook here to fake ATA_BUSY for that situation,
2000 * until the first time a BUSY, DRQ, or ERR bit is seen.
2001 *
2002 * The rest of the time, it simply returns the ATA status register.
2003 */
2004static u8 mv_sff_check_status(struct ata_port *ap)
2005{
2006 u8 stat = ioread8(ap->ioaddr.status_addr);
2007 struct mv_port_priv *pp = ap->private_data;
2008
2009 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2010 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2011 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2012 else
2013 stat = ATA_BUSY;
2014 }
2015 return stat;
2016}
2017
70f8b79c
ML		 2018/**
2019 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2020 * @fis: fis to be sent
2021 * @nwords: number of 32-bit words in the fis
2022 */
2023static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2024{
2025 void __iomem *port_mmio = mv_ap_base(ap);
2026 u32 ifctl, old_ifctl, ifstat;
2027 int i, timeout = 200, final_word = nwords - 1;
2028
2029 /* Initiate FIS transmission mode */
2030 old_ifctl = readl(port_mmio + SATA_IFCTL_OFS);
2031 ifctl = 0x100 | (old_ifctl & 0xf);
2032 writelfl(ifctl, port_mmio + SATA_IFCTL_OFS);
2033
2034 /* Send all words of the FIS except for the final word */
2035 for (i = 0; i < final_word; ++i)
2036 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS_OFS);
2037
2038 /* Flag end-of-transmission, and then send the final word */
2039 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL_OFS);
2040 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS_OFS);
2041
2042 /*
2043 * Wait for FIS transmission to complete.
2044 * This typically takes just a single iteration.
2045 */
2046 do {
2047 ifstat = readl(port_mmio + SATA_IFSTAT_OFS);
2048 } while (!(ifstat & 0x1000) && --timeout);
2049
2050 /* Restore original port configuration */
2051 writelfl(old_ifctl, port_mmio + SATA_IFCTL_OFS);
2052
2053 /* See if it worked */
2054 if ((ifstat & 0x3000) != 0x1000) {
2055 ata_port_printk(ap, KERN_WARNING,
2056 "%s transmission error, ifstat=%08x\n",
2057 __func__, ifstat);
2058 return AC_ERR_OTHER;
2059 }
2060 return 0;
2061}
2062
2063/**
2064 * mv_qc_issue_fis - Issue a command directly as a FIS
2065 * @qc: queued command to start
2066 *
2067 * Note that the ATA shadow registers are not updated
2068 * after command issue, so the device will appear "READY"
2069 * if polled, even while it is BUSY processing the command.
2070 *
2071 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2072 *
2073 * Note: we don't get updated shadow regs on *completion*
2074 * of non-data commands. So avoid sending them via this function,
2075 * as they will appear to have completed immediately.
2076 *
2077 * GEN_IIE has special registers that we could get the result tf from,
2078 * but earlier chipsets do not. For now, we ignore those registers.
2079 */
2080static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2081{
2082 struct ata_port *ap = qc->ap;
2083 struct mv_port_priv *pp = ap->private_data;
2084 struct ata_link *link = qc->dev->link;
2085 u32 fis[5];
2086 int err = 0;
2087
2088 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
2089 err = mv_send_fis(ap, fis, sizeof(fis) / sizeof(fis[0]));
2090 if (err)
2091 return err;
2092
2093 switch (qc->tf.protocol) {
2094 case ATAPI_PROT_PIO:
2095 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2096 /* fall through */
2097 case ATAPI_PROT_NODATA:
2098 ap->hsm_task_state = HSM_ST_FIRST;
2099 break;
2100 case ATA_PROT_PIO:
2101 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2102 if (qc->tf.flags & ATA_TFLAG_WRITE)
2103 ap->hsm_task_state = HSM_ST_FIRST;
2104 else
2105 ap->hsm_task_state = HSM_ST;
2106 break;
2107 default:
2108 ap->hsm_task_state = HSM_ST_LAST;
2109 break;
2110 }
2111
2112 if (qc->tf.flags & ATA_TFLAG_POLLING)
2113 ata_pio_queue_task(ap, qc, 0);
2114 return 0;
2115}
2116
05b308e1
BR		 2117/**
2118 * mv_qc_issue - Initiate a command to the host
2119 * @qc: queued command to start
2120 *
2121 * This routine simply redirects to the general purpose routine
2122 * if command is not DMA. Else, it sanity checks our local
2123 * caches of the request producer/consumer indices then enables
2124 * DMA and bumps the request producer index.
2125 *
2126 * LOCKING:
2127 * Inherited from caller.
2128 */
9a3d9eb0 2129static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 2130{
f48765cc 2131 static int limit_warnings = 10;
c5d3e45a
JG		 2132 struct ata_port *ap = qc->ap;
2133 void __iomem *port_mmio = mv_ap_base(ap);
2134 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 2135 u32 in_index;
42ed893d 2136 unsigned int port_irqs;
f48765cc 2137
d16ab3f6
ML		 2138 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2139
f48765cc
ML		 2140 switch (qc->tf.protocol) {
2141 case ATA_PROT_DMA:
2142 case ATA_PROT_NCQ:
2143 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2144 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2145 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2146
2147 /* Write the request in pointer to kick the EDMA to life */
2148 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
2149 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
2150 return 0;
31961943 2151
f48765cc 2152 case ATA_PROT_PIO:
c6112bd8
ML		 2153 /*
2154 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2155 *
2156 * Someday, we might implement special polling workarounds
2157 * for these, but it all seems rather unnecessary since we
2158 * normally use only DMA for commands which transfer more
2159 * than a single block of data.
2160 *
2161 * Much of the time, this could just work regardless.
2162 * So for now, just log the incident, and allow the attempt.
2163 */
c7843e8f 2164 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
c6112bd8
ML		 2165 --limit_warnings;
2166 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
2167 ": attempting PIO w/multiple DRQ: "
2168 "this may fail due to h/w errata\n");
2169 }
f48765cc 2170 /* drop through */
42ed893d 2171 case ATA_PROT_NODATA:
f48765cc 2172 case ATAPI_PROT_PIO:
42ed893d
ML		 2173 case ATAPI_PROT_NODATA:
2174 if (ap->flags & ATA_FLAG_PIO_POLLING)
2175 qc->tf.flags |= ATA_TFLAG_POLLING;
2176 break;
31961943 2177 }
42ed893d
ML		 2178
2179 if (qc->tf.flags & ATA_TFLAG_POLLING)
2180 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2181 else
2182 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2183
2184 /*
2185 * We're about to send a non-EDMA capable command to the
2186 * port. Turn off EDMA so there won't be problems accessing
2187 * shadow block, etc registers.
2188 */
2189 mv_stop_edma(ap);
2190 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2191 mv_pmp_select(ap, qc->dev->link->pmp);
70f8b79c
ML		 2192
2193 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2194 struct mv_host_priv *hpriv = ap->host->private_data;
2195 /*
2196 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
40f21b11 2197 *
70f8b79c
ML		 2198 * After any NCQ error, the READ_LOG_EXT command
2199 * from libata-eh *must* use mv_qc_issue_fis().
2200 * Otherwise it might fail, due to chip errata.
2201 *
2202 * Rather than special-case it, we'll just *always*
2203 * use this method here for READ_LOG_EXT, making for
2204 * easier testing.
2205 */
2206 if (IS_GEN_II(hpriv))
2207 return mv_qc_issue_fis(qc);
2208 }
42ed893d 2209 return ata_sff_qc_issue(qc);
31961943
BR		 2210}
2211
8f767f8a
ML		 2212static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2213{
2214 struct mv_port_priv *pp = ap->private_data;
2215 struct ata_queued_cmd *qc;
2216
2217 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2218 return NULL;
2219 qc = ata_qc_from_tag(ap, ap->link.active_tag);
95db5051
ML		 2220 if (qc) {
2221 if (qc->tf.flags & ATA_TFLAG_POLLING)
2222 qc = NULL;
2223 else if (!(qc->flags & ATA_QCFLAG_ACTIVE))
2224 qc = NULL;
2225 }
8f767f8a
ML		 2226 return qc;
2227}
2228
29d187bb
ML		 2229static void mv_pmp_error_handler(struct ata_port *ap)
2230{
2231 unsigned int pmp, pmp_map;
2232 struct mv_port_priv *pp = ap->private_data;
2233
2234 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2235 /*
2236 * Perform NCQ error analysis on failed PMPs
2237 * before we freeze the port entirely.
2238 *
2239 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2240 */
2241 pmp_map = pp->delayed_eh_pmp_map;
2242 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2243 for (pmp = 0; pmp_map != 0; pmp++) {
2244 unsigned int this_pmp = (1 << pmp);
2245 if (pmp_map & this_pmp) {
2246 struct ata_link *link = &ap->pmp_link[pmp];
2247 pmp_map &= ~this_pmp;
2248 ata_eh_analyze_ncq_error(link);
2249 }
2250 }
2251 ata_port_freeze(ap);
2252 }
2253 sata_pmp_error_handler(ap);
2254}
2255
4c299ca3
ML		 2256static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2257{
2258 void __iomem *port_mmio = mv_ap_base(ap);
2259
2260 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
2261}
2262
4c299ca3
ML		 2263static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2264{
2265 struct ata_eh_info *ehi;
2266 unsigned int pmp;
2267
2268 /*
2269 * Initialize EH info for PMPs which saw device errors
2270 */
2271 ehi = &ap->link.eh_info;
2272 for (pmp = 0; pmp_map != 0; pmp++) {
2273 unsigned int this_pmp = (1 << pmp);
2274 if (pmp_map & this_pmp) {
2275 struct ata_link *link = &ap->pmp_link[pmp];
2276
2277 pmp_map &= ~this_pmp;
2278 ehi = &link->eh_info;
2279 ata_ehi_clear_desc(ehi);
2280 ata_ehi_push_desc(ehi, "dev err");
2281 ehi->err_mask |= AC_ERR_DEV;
2282 ehi->action |= ATA_EH_RESET;
2283 ata_link_abort(link);
2284 }
2285 }
2286}
2287
06aaca3f
ML		 2288static int mv_req_q_empty(struct ata_port *ap)
2289{
2290 void __iomem *port_mmio = mv_ap_base(ap);
2291 u32 in_ptr, out_ptr;
2292
2293 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS)
2294 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2295 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
2296 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2297 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2298}
2299
4c299ca3
ML		 2300static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2301{
2302 struct mv_port_priv *pp = ap->private_data;
2303 int failed_links;
2304 unsigned int old_map, new_map;
2305
2306 /*
2307 * Device error during FBS+NCQ operation:
2308 *
2309 * Set a port flag to prevent further I/O being enqueued.
2310 * Leave the EDMA running to drain outstanding commands from this port.
2311 * Perform the post-mortem/EH only when all responses are complete.
2312 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2313 */
2314 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2315 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2316 pp->delayed_eh_pmp_map = 0;
2317 }
2318 old_map = pp->delayed_eh_pmp_map;
2319 new_map = old_map | mv_get_err_pmp_map(ap);
2320
2321 if (old_map != new_map) {
2322 pp->delayed_eh_pmp_map = new_map;
2323 mv_pmp_eh_prep(ap, new_map & ~old_map);
2324 }
c46938cc 2325 failed_links = hweight16(new_map);
4c299ca3
ML		 2326
2327 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
2328 "failed_links=%d nr_active_links=%d\n",
2329 __func__, pp->delayed_eh_pmp_map,
2330 ap->qc_active, failed_links,
2331 ap->nr_active_links);
2332
06aaca3f 2333 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
4c299ca3
ML		 2334 mv_process_crpb_entries(ap, pp);
2335 mv_stop_edma(ap);
2336 mv_eh_freeze(ap);
2337 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
2338 return 1; /* handled */
2339 }
2340 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
2341 return 1; /* handled */
2342}
2343
2344static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2345{
2346 /*
2347 * Possible future enhancement:
2348 *
2349 * FBS+non-NCQ operation is not yet implemented.
2350 * See related notes in mv_edma_cfg().
2351 *
2352 * Device error during FBS+non-NCQ operation:
2353 *
2354 * We need to snapshot the shadow registers for each failed command.
2355 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2356 */
2357 return 0; /* not handled */
2358}
2359
2360static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2361{
2362 struct mv_port_priv *pp = ap->private_data;
2363
2364 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2365 return 0; /* EDMA was not active: not handled */
2366 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2367 return 0; /* FBS was not active: not handled */
2368
2369 if (!(edma_err_cause & EDMA_ERR_DEV))
2370 return 0; /* non DEV error: not handled */
2371 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2372 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2373 return 0; /* other problems: not handled */
2374
2375 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2376 /*
2377 * EDMA should NOT have self-disabled for this case.
2378 * If it did, then something is wrong elsewhere,
2379 * and we cannot handle it here.
2380 */
2381 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2382 ata_port_printk(ap, KERN_WARNING,
2383 "%s: err_cause=0x%x pp_flags=0x%x\n",
2384 __func__, edma_err_cause, pp->pp_flags);
2385 return 0; /* not handled */
2386 }
2387 return mv_handle_fbs_ncq_dev_err(ap);
2388 } else {
2389 /*
2390 * EDMA should have self-disabled for this case.
2391 * If it did not, then something is wrong elsewhere,
2392 * and we cannot handle it here.
2393 */
2394 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2395 ata_port_printk(ap, KERN_WARNING,
2396 "%s: err_cause=0x%x pp_flags=0x%x\n",
2397 __func__, edma_err_cause, pp->pp_flags);
2398 return 0; /* not handled */
2399 }
2400 return mv_handle_fbs_non_ncq_dev_err(ap);
2401 }
2402 return 0; /* not handled */
2403}
2404
a9010329 2405static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
8f767f8a 2406{
8f767f8a 2407 struct ata_eh_info *ehi = &ap->link.eh_info;
a9010329 2408 char *when = "idle";
8f767f8a 2409
8f767f8a 2410 ata_ehi_clear_desc(ehi);
a9010329
ML		 2411 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2412 when = "disabled";
2413 } else if (edma_was_enabled) {
2414 when = "EDMA enabled";
8f767f8a
ML		 2415 } else {
2416 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2417 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
a9010329 2418 when = "polling";
8f767f8a 2419 }
a9010329 2420 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
8f767f8a
ML		 2421 ehi->err_mask |= AC_ERR_OTHER;
2422 ehi->action |= ATA_EH_RESET;
2423 ata_port_freeze(ap);
2424}
2425
05b308e1
BR		 2426/**
2427 * mv_err_intr - Handle error interrupts on the port
2428 * @ap: ATA channel to manipulate
2429 *
8d07379d
ML		 2430 * Most cases require a full reset of the chip's state machine,
2431 * which also performs a COMRESET.
2432 * Also, if the port disabled DMA, update our cached copy to match.
05b308e1
BR		 2433 *
2434 * LOCKING:
2435 * Inherited from caller.
2436 */
37b9046a 2437static void mv_err_intr(struct ata_port *ap)
31961943
BR		 2438{
2439 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde 2440 u32 edma_err_cause, eh_freeze_mask, serr = 0;
e4006077 2441 u32 fis_cause = 0;
bdd4ddde
JG		 2442 struct mv_port_priv *pp = ap->private_data;
2443 struct mv_host_priv *hpriv = ap->host->private_data;
bdd4ddde 2444 unsigned int action = 0, err_mask = 0;
9af5c9c9 2445 struct ata_eh_info *ehi = &ap->link.eh_info;
37b9046a
ML		 2446 struct ata_queued_cmd *qc;
2447 int abort = 0;
20f733e7 2448
8d07379d 2449 /*
37b9046a 2450 * Read and clear the SError and err_cause bits.
e4006077
ML		 2451 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2452 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
8d07379d 2453 */
37b9046a
ML		 2454 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2455 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2456
bdd4ddde 2457 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
e4006077
ML		 2458 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2459 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
2460 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
2461 }
8d07379d 2462 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 2463
4c299ca3
ML		 2464 if (edma_err_cause & EDMA_ERR_DEV) {
2465 /*
2466 * Device errors during FIS-based switching operation
2467 * require special handling.
2468 */
2469 if (mv_handle_dev_err(ap, edma_err_cause))
2470 return;
2471 }
2472
37b9046a
ML		 2473 qc = mv_get_active_qc(ap);
2474 ata_ehi_clear_desc(ehi);
2475 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2476 edma_err_cause, pp->pp_flags);
e4006077 2477
c443c500 2478 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
e4006077 2479 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
c443c500
ML		 2480 if (fis_cause & SATA_FIS_IRQ_AN) {
2481 u32 ec = edma_err_cause &
2482 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2483 sata_async_notification(ap);
2484 if (!ec)
2485 return; /* Just an AN; no need for the nukes */
2486 ata_ehi_push_desc(ehi, "SDB notify");
2487 }
2488 }
bdd4ddde 2489 /*
352fab70 2490 * All generations share these EDMA error cause bits:
bdd4ddde 2491 */
37b9046a 2492 if (edma_err_cause & EDMA_ERR_DEV) {
bdd4ddde 2493 err_mask |= AC_ERR_DEV;
37b9046a
ML		 2494 action |= ATA_EH_RESET;
2495 ata_ehi_push_desc(ehi, "dev error");
2496 }
bdd4ddde 2497 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 2498 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 2499 EDMA_ERR_INTRL_PAR)) {
2500 err_mask |= AC_ERR_ATA_BUS;
cf480626 2501 action |= ATA_EH_RESET;
b64bbc39 2502 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 2503 }
2504 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2505 ata_ehi_hotplugged(ehi);
2506 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 2507 "dev disconnect" : "dev connect");
cf480626 2508 action |= ATA_EH_RESET;
bdd4ddde
JG		 2509 }
2510
352fab70
ML		 2511 /*
2512 * Gen-I has a different SELF_DIS bit,
2513 * different FREEZE bits, and no SERR bit:
2514 */
ee9ccdf7 2515 if (IS_GEN_I(hpriv)) {
bdd4ddde 2516 eh_freeze_mask = EDMA_EH_FREEZE_5;
bdd4ddde 2517 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
bdd4ddde 2518 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 2519 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 2520 }
2521 } else {
2522 eh_freeze_mask = EDMA_EH_FREEZE;
bdd4ddde 2523 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
bdd4ddde 2524 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 2525 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde 2526 }
bdd4ddde 2527 if (edma_err_cause & EDMA_ERR_SERR) {
8d07379d
ML		 2528 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2529 err_mask |= AC_ERR_ATA_BUS;
cf480626 2530 action |= ATA_EH_RESET;
bdd4ddde 2531 }
afb0edd9 2532 }
20f733e7 2533
bdd4ddde
JG		 2534 if (!err_mask) {
2535 err_mask = AC_ERR_OTHER;
cf480626 2536 action |= ATA_EH_RESET;
bdd4ddde
JG		 2537 }
2538
2539 ehi->serror |= serr;
2540 ehi->action |= action;
2541
2542 if (qc)
2543 qc->err_mask |= err_mask;
2544 else
2545 ehi->err_mask |= err_mask;
2546
37b9046a
ML		 2547 if (err_mask == AC_ERR_DEV) {
2548 /*
2549 * Cannot do ata_port_freeze() here,
2550 * because it would kill PIO access,
2551 * which is needed for further diagnosis.
2552 */
2553 mv_eh_freeze(ap);
2554 abort = 1;
2555 } else if (edma_err_cause & eh_freeze_mask) {
2556 /*
2557 * Note to self: ata_port_freeze() calls ata_port_abort()
2558 */
bdd4ddde 2559 ata_port_freeze(ap);
37b9046a
ML		 2560 } else {
2561 abort = 1;
2562 }
2563
2564 if (abort) {
2565 if (qc)
2566 ata_link_abort(qc->dev->link);
2567 else
2568 ata_port_abort(ap);
2569 }
bdd4ddde
JG		 2570}
2571
fcfb1f77
ML		 2572static void mv_process_crpb_response(struct ata_port *ap,
2573 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2574{
2575 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
2576
2577 if (qc) {
2578 u8 ata_status;
2579 u16 edma_status = le16_to_cpu(response->flags);
2580 /*
2581 * edma_status from a response queue entry:
2582 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
2583 * MSB is saved ATA status from command completion.
2584 */
2585 if (!ncq_enabled) {
2586 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2587 if (err_cause) {
2588 /*
2589 * Error will be seen/handled by mv_err_intr().
2590 * So do nothing at all here.
2591 */
2592 return;
2593 }
2594 }
2595 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
37b9046a
ML		 2596 if (!ac_err_mask(ata_status))
2597 ata_qc_complete(qc);
2598 /* else: leave it for mv_err_intr() */
fcfb1f77
ML		 2599 } else {
2600 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2601 __func__, tag);
2602 }
2603}
2604
2605static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
bdd4ddde
JG		 2606{
2607 void __iomem *port_mmio = mv_ap_base(ap);
2608 struct mv_host_priv *hpriv = ap->host->private_data;
fcfb1f77 2609 u32 in_index;
bdd4ddde 2610 bool work_done = false;
fcfb1f77 2611 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
bdd4ddde 2612
fcfb1f77 2613 /* Get the hardware queue position index */
bdd4ddde
JG		 2614 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
2615 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2616
fcfb1f77
ML		 2617 /* Process new responses from since the last time we looked */
2618 while (in_index != pp->resp_idx) {
6c1153e0 2619 unsigned int tag;
fcfb1f77 2620 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
bdd4ddde 2621
fcfb1f77 2622 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
bdd4ddde 2623
fcfb1f77
ML		 2624 if (IS_GEN_I(hpriv)) {
2625 /* 50xx: no NCQ, only one command active at a time */
9af5c9c9 2626 tag = ap->link.active_tag;
fcfb1f77
ML		 2627 } else {
2628 /* Gen II/IIE: get command tag from CRPB entry */
2629 tag = le16_to_cpu(response->id) & 0x1f;
bdd4ddde 2630 }
fcfb1f77 2631 mv_process_crpb_response(ap, response, tag, ncq_enabled);
bdd4ddde 2632 work_done = true;
bdd4ddde
JG		 2633 }
2634
352fab70 2635 /* Update the software queue position index in hardware */
bdd4ddde
JG		 2636 if (work_done)
2637 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
fcfb1f77 2638 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
bdd4ddde 2639 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
20f733e7
BR		 2640}
2641
a9010329
ML		 2642static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2643{
2644 struct mv_port_priv *pp;
2645 int edma_was_enabled;
2646
2647 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2648 mv_unexpected_intr(ap, 0);
2649 return;
2650 }
2651 /*
2652 * Grab a snapshot of the EDMA_EN flag setting,
2653 * so that we have a consistent view for this port,
2654 * even if something we call of our routines changes it.
2655 */
2656 pp = ap->private_data;
2657 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2658 /*
2659 * Process completed CRPB response(s) before other events.
2660 */
2661 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2662 mv_process_crpb_entries(ap, pp);
4c299ca3
ML		 2663 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2664 mv_handle_fbs_ncq_dev_err(ap);
a9010329
ML		 2665 }
2666 /*
2667 * Handle chip-reported errors, or continue on to handle PIO.
2668 */
2669 if (unlikely(port_cause & ERR_IRQ)) {
2670 mv_err_intr(ap);
2671 } else if (!edma_was_enabled) {
2672 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2673 if (qc)
2674 ata_sff_host_intr(ap, qc);
2675 else
2676 mv_unexpected_intr(ap, edma_was_enabled);
2677 }
2678}
2679
05b308e1
BR		 2680/**
2681 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 2682 * @host: host specific structure
7368f919 2683 * @main_irq_cause: Main interrupt cause register for the chip.
05b308e1
BR		 2684 *
2685 * LOCKING:
2686 * Inherited from caller.
2687 */
7368f919 2688static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
20f733e7 2689{
f351b2d6 2690 struct mv_host_priv *hpriv = host->private_data;
eabd5eb1 2691 void __iomem *mmio = hpriv->base, *hc_mmio;
a3718c1f 2692 unsigned int handled = 0, port;
20f733e7 2693
2b748a0a
ML		 2694 /* If asserted, clear the "all ports" IRQ coalescing bit */
2695 if (main_irq_cause & ALL_PORTS_COAL_DONE)
2696 writel(~ALL_PORTS_COAL_IRQ, mmio + MV_IRQ_COAL_CAUSE);
2697
a3718c1f 2698 for (port = 0; port < hpriv->n_ports; port++) {
cca3974e 2699 struct ata_port *ap = host->ports[port];
eabd5eb1
ML		 2700 unsigned int p, shift, hardport, port_cause;
2701
a3718c1f 2702 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
a3718c1f 2703 /*
eabd5eb1
ML		 2704 * Each hc within the host has its own hc_irq_cause register,
2705 * where the interrupting ports bits get ack'd.
a3718c1f 2706 */
eabd5eb1
ML		 2707 if (hardport == 0) { /* first port on this hc ? */
2708 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2709 u32 port_mask, ack_irqs;
2710 /*
2711 * Skip this entire hc if nothing pending for any ports
2712 */
2713 if (!hc_cause) {
2714 port += MV_PORTS_PER_HC - 1;
2715 continue;
2716 }
2717 /*
2718 * We don't need/want to read the hc_irq_cause register,
2719 * because doing so hurts performance, and
2720 * main_irq_cause already gives us everything we need.
2721 *
2722 * But we do have to *write* to the hc_irq_cause to ack
2723 * the ports that we are handling this time through.
2724 *
2725 * This requires that we create a bitmap for those
2726 * ports which interrupted us, and use that bitmap
2727 * to ack (only) those ports via hc_irq_cause.
2728 */
2729 ack_irqs = 0;
2b748a0a
ML		 2730 if (hc_cause & PORTS_0_3_COAL_DONE)
2731 ack_irqs = HC_COAL_IRQ;
eabd5eb1
ML		 2732 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2733 if ((port + p) >= hpriv->n_ports)
2734 break;
2735 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2736 if (hc_cause & port_mask)
2737 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2738 }
a3718c1f 2739 hc_mmio = mv_hc_base_from_port(mmio, port);
eabd5eb1 2740 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
a3718c1f
ML		 2741 handled = 1;
2742 }
8f767f8a 2743 /*
a9010329 2744 * Handle interrupts signalled for this port:
8f767f8a 2745 */
a9010329
ML		 2746 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2747 if (port_cause)
2748 mv_port_intr(ap, port_cause);
20f733e7 2749 }
a3718c1f 2750 return handled;
20f733e7
BR		 2751}
2752
a3718c1f 2753static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
bdd4ddde 2754{
02a121da 2755 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 2756 struct ata_port *ap;
2757 struct ata_queued_cmd *qc;
2758 struct ata_eh_info *ehi;
2759 unsigned int i, err_mask, printed = 0;
2760 u32 err_cause;
2761
02a121da 2762 err_cause = readl(mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2763
2764 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2765 err_cause);
2766
2767 DPRINTK("All regs @ PCI error\n");
2768 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2769
02a121da 2770 writelfl(0, mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2771
2772 for (i = 0; i < host->n_ports; i++) {
2773 ap = host->ports[i];
936fd732 2774 if (!ata_link_offline(&ap->link)) {
9af5c9c9 2775 ehi = &ap->link.eh_info;
bdd4ddde
JG		 2776 ata_ehi_clear_desc(ehi);
2777 if (!printed++)
2778 ata_ehi_push_desc(ehi,
2779 "PCI err cause 0x%08x", err_cause);
2780 err_mask = AC_ERR_HOST_BUS;
cf480626 2781 ehi->action = ATA_EH_RESET;
9af5c9c9 2782 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 2783 if (qc)
2784 qc->err_mask |= err_mask;
2785 else
2786 ehi->err_mask |= err_mask;
2787
2788 ata_port_freeze(ap);
2789 }
2790 }
a3718c1f 2791 return 1; /* handled */
bdd4ddde
JG		 2792}
2793
05b308e1 2794/**
c5d3e45a 2795 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 2796 * @irq: unused
2797 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 2798 *
2799 * Read the read only register to determine if any host
2800 * controllers have pending interrupts. If so, call lower level
2801 * routine to handle. Also check for PCI errors which are only
2802 * reported here.
2803 *
8b260248 2804 * LOCKING:
cca3974e 2805 * This routine holds the host lock while processing pending
05b308e1
BR		 2806 * interrupts.
2807 */
7d12e780 2808static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 2809{
cca3974e 2810 struct ata_host *host = dev_instance;
f351b2d6 2811 struct mv_host_priv *hpriv = host->private_data;
a3718c1f 2812 unsigned int handled = 0;
6d3c30ef 2813 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
96e2c487 2814 u32 main_irq_cause, pending_irqs;
20f733e7 2815
646a4da5 2816 spin_lock(&host->lock);
6d3c30ef
ML		 2817
2818 /* for MSI: block new interrupts while in here */
2819 if (using_msi)
2b748a0a 2820 mv_write_main_irq_mask(0, hpriv);
6d3c30ef 2821
7368f919 2822 main_irq_cause = readl(hpriv->main_irq_cause_addr);
96e2c487 2823 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
352fab70
ML		 2824 /*
2825 * Deal with cases where we either have nothing pending, or have read
2826 * a bogus register value which can indicate HW removal or PCI fault.
20f733e7 2827 */
a44253d2 2828 if (pending_irqs && main_irq_cause != 0xffffffffU) {
1f398472 2829 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
a3718c1f
ML		 2830 handled = mv_pci_error(host, hpriv->base);
2831 else
a44253d2 2832 handled = mv_host_intr(host, pending_irqs);
bdd4ddde 2833 }
6d3c30ef
ML		 2834
2835 /* for MSI: unmask; interrupt cause bits will retrigger now */
2836 if (using_msi)
2b748a0a 2837 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
6d3c30ef 2838
9d51af7b
ML		 2839 spin_unlock(&host->lock);
2840
20f733e7
BR		 2841 return IRQ_RETVAL(handled);
2842}
2843
c9d39130
JG		 2844static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2845{
2846 unsigned int ofs;
2847
2848 switch (sc_reg_in) {
2849 case SCR_STATUS:
2850 case SCR_ERROR:
2851 case SCR_CONTROL:
2852 ofs = sc_reg_in * sizeof(u32);
2853 break;
2854 default:
2855 ofs = 0xffffffffU;
2856 break;
2857 }
2858 return ofs;
2859}
2860
82ef04fb 2861static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
c9d39130 2862{
82ef04fb 2863 struct mv_host_priv *hpriv = link->ap->host->private_data;
f351b2d6 2864 void __iomem *mmio = hpriv->base;
82ef04fb 2865 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
c9d39130
JG		 2866 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2867
da3dbb17
TH		 2868 if (ofs != 0xffffffffU) {
2869 *val = readl(addr + ofs);
2870 return 0;
2871 } else
2872 return -EINVAL;
c9d39130
JG		 2873}
2874
82ef04fb 2875static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
c9d39130 2876{
82ef04fb 2877 struct mv_host_priv *hpriv = link->ap->host->private_data;
f351b2d6 2878 void __iomem *mmio = hpriv->base;
82ef04fb 2879 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
c9d39130
JG		 2880 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2881
da3dbb17 2882 if (ofs != 0xffffffffU) {
0d5ff566 2883 writelfl(val, addr + ofs);
da3dbb17
TH		 2884 return 0;
2885 } else
2886 return -EINVAL;
c9d39130
JG		 2887}
2888
7bb3c529 2889static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
522479fb 2890{
7bb3c529 2891 struct pci_dev *pdev = to_pci_dev(host->dev);
522479fb
JG		 2892 int early_5080;
2893
44c10138 2894 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 2895
2896 if (!early_5080) {
2897 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2898 tmp |= (1 << 0);
2899 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2900 }
2901
7bb3c529 2902 mv_reset_pci_bus(host, mmio);
522479fb
JG		 2903}
2904
2905static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2906{
8e7decdb 2907 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
522479fb
JG		 2908}
2909
47c2b677 2910static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2911 void __iomem *mmio)
2912{
c9d39130
JG		 2913 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2914 u32 tmp;
2915
2916 tmp = readl(phy_mmio + MV5_PHY_MODE);
2917
2918 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2919 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 2920}
2921
47c2b677 2922static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2923{
522479fb
JG		 2924 u32 tmp;
2925
8e7decdb 2926 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
522479fb
JG		 2927
2928 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2929
2930 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2931 tmp |= ~(1 << 0);
2932 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 2933}
2934
2a47ce06
JG		 2935static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2936 unsigned int port)
bca1c4eb 2937{
c9d39130
JG		 2938 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2939 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2940 u32 tmp;
2941 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2942
2943 if (fix_apm_sq) {
8e7decdb 2944 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
c9d39130 2945 tmp |= (1 << 19);
8e7decdb 2946 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
c9d39130 2947
8e7decdb 2948 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2949 tmp &= ~0x3;
2950 tmp |= 0x1;
8e7decdb 2951 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2952 }
2953
2954 tmp = readl(phy_mmio + MV5_PHY_MODE);
2955 tmp &= ~mask;
2956 tmp |= hpriv->signal[port].pre;
2957 tmp |= hpriv->signal[port].amps;
2958 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 2959}
2960
c9d39130
JG		 2961
2962#undef ZERO
2963#define ZERO(reg) writel(0, port_mmio + (reg))
2964static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2965 unsigned int port)
2966{
2967 void __iomem *port_mmio = mv_port_base(mmio, port);
2968
e12bef50 2969 mv_reset_channel(hpriv, mmio, port);
c9d39130
JG		 2970
2971 ZERO(0x028); /* command */
2972 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2973 ZERO(0x004); /* timer */
2974 ZERO(0x008); /* irq err cause */
2975 ZERO(0x00c); /* irq err mask */
2976 ZERO(0x010); /* rq bah */
2977 ZERO(0x014); /* rq inp */
2978 ZERO(0x018); /* rq outp */
2979 ZERO(0x01c); /* respq bah */
2980 ZERO(0x024); /* respq outp */
2981 ZERO(0x020); /* respq inp */
2982 ZERO(0x02c); /* test control */
8e7decdb 2983 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
c9d39130
JG		 2984}
2985#undef ZERO
2986
2987#define ZERO(reg) writel(0, hc_mmio + (reg))
2988static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2989 unsigned int hc)
47c2b677 2990{
c9d39130
JG		 2991 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2992 u32 tmp;
2993
2994 ZERO(0x00c);
2995 ZERO(0x010);
2996 ZERO(0x014);
2997 ZERO(0x018);
2998
2999 tmp = readl(hc_mmio + 0x20);
3000 tmp &= 0x1c1c1c1c;
3001 tmp |= 0x03030303;
3002 writel(tmp, hc_mmio + 0x20);
3003}
3004#undef ZERO
3005
3006static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3007 unsigned int n_hc)
3008{
3009 unsigned int hc, port;
3010
3011 for (hc = 0; hc < n_hc; hc++) {
3012 for (port = 0; port < MV_PORTS_PER_HC; port++)
3013 mv5_reset_hc_port(hpriv, mmio,
3014 (hc * MV_PORTS_PER_HC) + port);
3015
3016 mv5_reset_one_hc(hpriv, mmio, hc);
3017 }
3018
3019 return 0;
47c2b677
JG		 3020}
3021
101ffae2
JG		 3022#undef ZERO
3023#define ZERO(reg) writel(0, mmio + (reg))
7bb3c529 3024static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
101ffae2 3025{
02a121da 3026 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 3027 u32 tmp;
3028
8e7decdb 3029 tmp = readl(mmio + MV_PCI_MODE_OFS);
101ffae2 3030 tmp &= 0xff00ffff;
8e7decdb 3031 writel(tmp, mmio + MV_PCI_MODE_OFS);
101ffae2
JG		 3032
3033 ZERO(MV_PCI_DISC_TIMER);
3034 ZERO(MV_PCI_MSI_TRIGGER);
8e7decdb 3035 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
101ffae2 3036 ZERO(MV_PCI_SERR_MASK);
02a121da
ML		 3037 ZERO(hpriv->irq_cause_ofs);
3038 ZERO(hpriv->irq_mask_ofs);
101ffae2
JG		 3039 ZERO(MV_PCI_ERR_LOW_ADDRESS);
3040 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3041 ZERO(MV_PCI_ERR_ATTRIBUTE);
3042 ZERO(MV_PCI_ERR_COMMAND);
3043}
3044#undef ZERO
3045
3046static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3047{
3048 u32 tmp;
3049
3050 mv5_reset_flash(hpriv, mmio);
3051
8e7decdb 3052 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 3053 tmp &= 0x3;
3054 tmp |= (1 << 5) | (1 << 6);
8e7decdb 3055 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 3056}
3057
3058/**
3059 * mv6_reset_hc - Perform the 6xxx global soft reset
3060 * @mmio: base address of the HBA
3061 *
3062 * This routine only applies to 6xxx parts.
3063 *
3064 * LOCKING:
3065 * Inherited from caller.
3066 */
c9d39130
JG		 3067static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3068 unsigned int n_hc)
101ffae2
JG		 3069{
3070 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
3071 int i, rc = 0;
3072 u32 t;
3073
3074 /* Following procedure defined in PCI "main command and status
3075 * register" table.
3076 */
3077 t = readl(reg);
3078 writel(t | STOP_PCI_MASTER, reg);
3079
3080 for (i = 0; i < 1000; i++) {
3081 udelay(1);
3082 t = readl(reg);
2dcb407e 3083 if (PCI_MASTER_EMPTY & t)
101ffae2 3084 break;
101ffae2
JG		 3085 }
3086 if (!(PCI_MASTER_EMPTY & t)) {
3087 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3088 rc = 1;
3089 goto done;
3090 }
3091
3092 /* set reset */
3093 i = 5;
3094 do {
3095 writel(t | GLOB_SFT_RST, reg);
3096 t = readl(reg);
3097 udelay(1);
3098 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3099
3100 if (!(GLOB_SFT_RST & t)) {
3101 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3102 rc = 1;
3103 goto done;
3104 }
3105
3106 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3107 i = 5;
3108 do {
3109 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3110 t = readl(reg);
3111 udelay(1);
3112 } while ((GLOB_SFT_RST & t) && (i-- > 0));
3113
3114 if (GLOB_SFT_RST & t) {
3115 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3116 rc = 1;
3117 }
3118done:
3119 return rc;
3120}
3121
47c2b677 3122static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 3123 void __iomem *mmio)
3124{
3125 void __iomem *port_mmio;
3126 u32 tmp;
3127
8e7decdb 3128 tmp = readl(mmio + MV_RESET_CFG_OFS);
ba3fe8fb 3129 if ((tmp & (1 << 0)) == 0) {
47c2b677 3130 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 3131 hpriv->signal[idx].pre = 0x1 << 5;
3132 return;
3133 }
3134
3135 port_mmio = mv_port_base(mmio, idx);
3136 tmp = readl(port_mmio + PHY_MODE2);
3137
3138 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3139 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3140}
3141
47c2b677 3142static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 3143{
8e7decdb 3144 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
ba3fe8fb
JG		 3145}
3146
c9d39130 3147static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 3148 unsigned int port)
bca1c4eb 3149{
c9d39130
JG		 3150 void __iomem *port_mmio = mv_port_base(mmio, port);
3151
bca1c4eb 3152 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 3153 int fix_phy_mode2 =
3154 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 3155 int fix_phy_mode4 =
47c2b677 3156 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
8c30a8b9 3157 u32 m2, m3;
47c2b677
JG		 3158
3159 if (fix_phy_mode2) {
3160 m2 = readl(port_mmio + PHY_MODE2);
3161 m2 &= ~(1 << 16);
3162 m2 |= (1 << 31);
3163 writel(m2, port_mmio + PHY_MODE2);
3164
3165 udelay(200);
3166
3167 m2 = readl(port_mmio + PHY_MODE2);
3168 m2 &= ~((1 << 16) | (1 << 31));
3169 writel(m2, port_mmio + PHY_MODE2);
3170
3171 udelay(200);
3172 }
3173
8c30a8b9
ML		 3174 /*
3175 * Gen-II/IIe PHY_MODE3 errata RM#2:
3176 * Achieves better receiver noise performance than the h/w default:
3177 */
3178 m3 = readl(port_mmio + PHY_MODE3);
3179 m3 = (m3 & 0x1f) | (0x5555601 << 5);
bca1c4eb 3180
0388a8c0
ML		 3181 /* Guideline 88F5182 (GL# SATA-S11) */
3182 if (IS_SOC(hpriv))
3183 m3 &= ~0x1c;
3184
bca1c4eb 3185 if (fix_phy_mode4) {
ba069e37
ML		 3186 u32 m4 = readl(port_mmio + PHY_MODE4);
3187 /*
3188 * Enforce reserved-bit restrictions on GenIIe devices only.
3189 * For earlier chipsets, force only the internal config field
3190 * (workaround for errata FEr SATA#10 part 1).
3191 */
8c30a8b9 3192 if (IS_GEN_IIE(hpriv))
ba069e37
ML		 3193 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3194 else
3195 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
8c30a8b9 3196 writel(m4, port_mmio + PHY_MODE4);
bca1c4eb 3197 }
b406c7a6
ML		 3198 /*
3199 * Workaround for 60x1-B2 errata SATA#13:
3200 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3201 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
3202 */
3203 writel(m3, port_mmio + PHY_MODE3);
bca1c4eb
JG		 3204
3205 /* Revert values of pre-emphasis and signal amps to the saved ones */
3206 m2 = readl(port_mmio + PHY_MODE2);
3207
3208 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 3209 m2 |= hpriv->signal[port].amps;
3210 m2 |= hpriv->signal[port].pre;
47c2b677 3211 m2 &= ~(1 << 16);
bca1c4eb 3212
e4e7b892
JG		 3213 /* according to mvSata 3.6.1, some IIE values are fixed */
3214 if (IS_GEN_IIE(hpriv)) {
3215 m2 &= ~0xC30FF01F;
3216 m2 |= 0x0000900F;
3217 }
3218
bca1c4eb
JG		 3219 writel(m2, port_mmio + PHY_MODE2);
3220}
3221
f351b2d6
SB		 3222/* TODO: use the generic LED interface to configure the SATA Presence */
3223/* & Acitivy LEDs on the board */
3224static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3225 void __iomem *mmio)
3226{
3227 return;
3228}
3229
3230static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3231 void __iomem *mmio)
3232{
3233 void __iomem *port_mmio;
3234 u32 tmp;
3235
3236 port_mmio = mv_port_base(mmio, idx);
3237 tmp = readl(port_mmio + PHY_MODE2);
3238
3239 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3240 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3241}
3242
3243#undef ZERO
3244#define ZERO(reg) writel(0, port_mmio + (reg))
3245static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3246 void __iomem *mmio, unsigned int port)
3247{
3248 void __iomem *port_mmio = mv_port_base(mmio, port);
3249
e12bef50 3250 mv_reset_channel(hpriv, mmio, port);
f351b2d6
SB		 3251
3252 ZERO(0x028); /* command */
3253 writel(0x101f, port_mmio + EDMA_CFG_OFS);
3254 ZERO(0x004); /* timer */
3255 ZERO(0x008); /* irq err cause */
3256 ZERO(0x00c); /* irq err mask */
3257 ZERO(0x010); /* rq bah */
3258 ZERO(0x014); /* rq inp */
3259 ZERO(0x018); /* rq outp */
3260 ZERO(0x01c); /* respq bah */
3261 ZERO(0x024); /* respq outp */
3262 ZERO(0x020); /* respq inp */
3263 ZERO(0x02c); /* test control */
8e7decdb 3264 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
f351b2d6
SB		 3265}
3266
3267#undef ZERO
3268
3269#define ZERO(reg) writel(0, hc_mmio + (reg))
3270static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3271 void __iomem *mmio)
3272{
3273 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3274
3275 ZERO(0x00c);
3276 ZERO(0x010);
3277 ZERO(0x014);
3278
3279}
3280
3281#undef ZERO
3282
3283static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3284 void __iomem *mmio, unsigned int n_hc)
3285{
3286 unsigned int port;
3287
3288 for (port = 0; port < hpriv->n_ports; port++)
3289 mv_soc_reset_hc_port(hpriv, mmio, port);
3290
3291 mv_soc_reset_one_hc(hpriv, mmio);
3292
3293 return 0;
3294}
3295
3296static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3297 void __iomem *mmio)
3298{
3299 return;
3300}
3301
3302static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3303{
3304 return;
3305}
3306
8e7decdb 3307static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
b67a1064 3308{
8e7decdb 3309 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064 3310
8e7decdb 3311 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
b67a1064 3312 if (want_gen2i)
8e7decdb
ML		 3313 ifcfg |= (1 << 7); /* enable gen2i speed */
3314 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064
ML		 3315}
3316
e12bef50 3317static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130
JG		 3318 unsigned int port_no)
3319{
3320 void __iomem *port_mmio = mv_port_base(mmio, port_no);
3321
8e7decdb
ML		 3322 /*
3323 * The datasheet warns against setting EDMA_RESET when EDMA is active
3324 * (but doesn't say what the problem might be). So we first try
3325 * to disable the EDMA engine before doing the EDMA_RESET operation.
3326 */
0d8be5cb 3327 mv_stop_edma_engine(port_mmio);
8e7decdb 3328 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
c9d39130 3329
b67a1064 3330 if (!IS_GEN_I(hpriv)) {
8e7decdb
ML		 3331 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3332 mv_setup_ifcfg(port_mmio, 1);
c9d39130 3333 }
b67a1064 3334 /*
8e7decdb 3335 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
b67a1064
ML		 3336 * link, and physical layers. It resets all SATA interface registers
3337 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
c9d39130 3338 */
8e7decdb 3339 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
b67a1064 3340 udelay(25); /* allow reset propagation */
c9d39130
JG		 3341 writelfl(0, port_mmio + EDMA_CMD_OFS);
3342
3343 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3344
ee9ccdf7 3345 if (IS_GEN_I(hpriv))
c9d39130
JG		 3346 mdelay(1);
3347}
3348
e49856d8 3349static void mv_pmp_select(struct ata_port *ap, int pmp)
20f733e7 3350{
e49856d8
ML		 3351 if (sata_pmp_supported(ap)) {
3352 void __iomem *port_mmio = mv_ap_base(ap);
3353 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
3354 int old = reg & 0xf;
22374677 3355
e49856d8
ML		 3356 if (old != pmp) {
3357 reg = (reg & ~0xf) | pmp;
3358 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
3359 }
22374677 3360 }
20f733e7
BR		 3361}
3362
e49856d8
ML		 3363static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3364 unsigned long deadline)
22374677 3365{
e49856d8
ML		 3366 mv_pmp_select(link->ap, sata_srst_pmp(link));
3367 return sata_std_hardreset(link, class, deadline);
3368}
bdd4ddde 3369
e49856d8
ML		 3370static int mv_softreset(struct ata_link *link, unsigned int *class,
3371 unsigned long deadline)
3372{
3373 mv_pmp_select(link->ap, sata_srst_pmp(link));
3374 return ata_sff_softreset(link, class, deadline);
22374677
JG		 3375}
3376
cc0680a5 3377static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 3378 unsigned long deadline)
31961943 3379{
cc0680a5 3380 struct ata_port *ap = link->ap;
bdd4ddde 3381 struct mv_host_priv *hpriv = ap->host->private_data;
b562468c 3382 struct mv_port_priv *pp = ap->private_data;
f351b2d6 3383 void __iomem *mmio = hpriv->base;
0d8be5cb
ML		 3384 int rc, attempts = 0, extra = 0;
3385 u32 sstatus;
3386 bool online;
31961943 3387
e12bef50 3388 mv_reset_channel(hpriv, mmio, ap->port_no);
b562468c 3389 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
d16ab3f6
ML		 3390 pp->pp_flags &=
3391 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
bdd4ddde 3392
0d8be5cb
ML		 3393 /* Workaround for errata FEr SATA#10 (part 2) */
3394 do {
17c5aab5
ML		 3395 const unsigned long *timing =
3396 sata_ehc_deb_timing(&link->eh_context);
bdd4ddde 3397
17c5aab5
ML		 3398 rc = sata_link_hardreset(link, timing, deadline + extra,
3399 &online, NULL);
9dcffd99 3400 rc = online ? -EAGAIN : rc;
17c5aab5 3401 if (rc)
0d8be5cb 3402 return rc;
0d8be5cb
ML		 3403 sata_scr_read(link, SCR_STATUS, &sstatus);
3404 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3405 /* Force 1.5gb/s link speed and try again */
8e7decdb 3406 mv_setup_ifcfg(mv_ap_base(ap), 0);
0d8be5cb
ML		 3407 if (time_after(jiffies + HZ, deadline))
3408 extra = HZ; /* only extend it once, max */
3409 }
3410 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
08da1759 3411 mv_save_cached_regs(ap);
66e57a2c 3412 mv_edma_cfg(ap, 0, 0);
bdd4ddde 3413
17c5aab5 3414 return rc;
bdd4ddde
JG		 3415}
3416
bdd4ddde
JG		 3417static void mv_eh_freeze(struct ata_port *ap)
3418{
1cfd19ae 3419 mv_stop_edma(ap);
c4de573b 3420 mv_enable_port_irqs(ap, 0);
bdd4ddde
JG		 3421}
3422
3423static void mv_eh_thaw(struct ata_port *ap)
3424{
f351b2d6 3425 struct mv_host_priv *hpriv = ap->host->private_data;
c4de573b
ML		 3426 unsigned int port = ap->port_no;
3427 unsigned int hardport = mv_hardport_from_port(port);
1cfd19ae 3428 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
bdd4ddde 3429 void __iomem *port_mmio = mv_ap_base(ap);
c4de573b 3430 u32 hc_irq_cause;
bdd4ddde 3431
bdd4ddde
JG		 3432 /* clear EDMA errors on this port */
3433 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
3434
3435 /* clear pending irq events */
cae6edc3 3436 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
1cfd19ae 3437 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
bdd4ddde 3438
88e675e1 3439 mv_enable_port_irqs(ap, ERR_IRQ);
31961943
BR		 3440}
3441
05b308e1
BR		 3442/**
3443 * mv_port_init - Perform some early initialization on a single port.
3444 * @port: libata data structure storing shadow register addresses
3445 * @port_mmio: base address of the port
3446 *
3447 * Initialize shadow register mmio addresses, clear outstanding
3448 * interrupts on the port, and unmask interrupts for the future
3449 * start of the port.
3450 *
3451 * LOCKING:
3452 * Inherited from caller.
3453 */
31961943 3454static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 3455{
0d5ff566 3456 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
31961943
BR		 3457 unsigned serr_ofs;
3458
8b260248 3459 /* PIO related setup
31961943
BR		 3460 */
3461 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 3462 port->error_addr =
31961943
BR		 3463 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3464 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3465 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3466 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3467 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3468 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 3469 port->status_addr =
31961943
BR		 3470 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3471 /* special case: control/altstatus doesn't have ATA_REG_ address */
3472 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
3473
3474 /* unused: */
8d9db2d2 3475 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
20f733e7 3476
31961943
BR		 3477 /* Clear any currently outstanding port interrupt conditions */
3478 serr_ofs = mv_scr_offset(SCR_ERROR);
3479 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
3480 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
3481
646a4da5
ML		 3482 /* unmask all non-transient EDMA error interrupts */
3483 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 3484
8b260248 3485 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 3486 readl(port_mmio + EDMA_CFG_OFS),
3487 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
3488 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 3489}
3490
616d4a98
ML		 3491static unsigned int mv_in_pcix_mode(struct ata_host *host)
3492{
3493 struct mv_host_priv *hpriv = host->private_data;
3494 void __iomem *mmio = hpriv->base;
3495 u32 reg;
3496
1f398472 3497 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
616d4a98
ML		 3498 return 0; /* not PCI-X capable */
3499 reg = readl(mmio + MV_PCI_MODE_OFS);
3500 if ((reg & MV_PCI_MODE_MASK) == 0)
3501 return 0; /* conventional PCI mode */
3502 return 1; /* chip is in PCI-X mode */
3503}
3504
3505static int mv_pci_cut_through_okay(struct ata_host *host)
3506{
3507 struct mv_host_priv *hpriv = host->private_data;
3508 void __iomem *mmio = hpriv->base;
3509 u32 reg;
3510
3511 if (!mv_in_pcix_mode(host)) {
3512 reg = readl(mmio + PCI_COMMAND_OFS);
3513 if (reg & PCI_COMMAND_MRDTRIG)
3514 return 0; /* not okay */
3515 }
3516 return 1; /* okay */
3517}
3518
4447d351 3519static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 3520{
4447d351
TH		 3521 struct pci_dev *pdev = to_pci_dev(host->dev);
3522 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 3523 u32 hp_flags = hpriv->hp_flags;
3524
5796d1c4 3525 switch (board_idx) {
47c2b677
JG		 3526 case chip_5080:
3527 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 3528 hp_flags |= MV_HP_GEN_I;
47c2b677 3529
44c10138 3530 switch (pdev->revision) {
47c2b677
JG		 3531 case 0x1:
3532 hp_flags |= MV_HP_ERRATA_50XXB0;
3533 break;
3534 case 0x3:
3535 hp_flags |= MV_HP_ERRATA_50XXB2;
3536 break;
3537 default:
3538 dev_printk(KERN_WARNING, &pdev->dev,
3539 "Applying 50XXB2 workarounds to unknown rev\n");
3540 hp_flags |= MV_HP_ERRATA_50XXB2;
3541 break;
3542 }
3543 break;
3544
bca1c4eb
JG		 3545 case chip_504x:
3546 case chip_508x:
47c2b677 3547 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 3548 hp_flags |= MV_HP_GEN_I;
bca1c4eb 3549
44c10138 3550 switch (pdev->revision) {
47c2b677
JG		 3551 case 0x0:
3552 hp_flags |= MV_HP_ERRATA_50XXB0;
3553 break;
3554 case 0x3:
3555 hp_flags |= MV_HP_ERRATA_50XXB2;
3556 break;
3557 default:
3558 dev_printk(KERN_WARNING, &pdev->dev,
3559 "Applying B2 workarounds to unknown rev\n");
3560 hp_flags |= MV_HP_ERRATA_50XXB2;
3561 break;
bca1c4eb
JG		 3562 }
3563 break;
3564
3565 case chip_604x:
3566 case chip_608x:
47c2b677 3567 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 3568 hp_flags |= MV_HP_GEN_II;
47c2b677 3569
44c10138 3570 switch (pdev->revision) {
47c2b677
JG		 3571 case 0x7:
3572 hp_flags |= MV_HP_ERRATA_60X1B2;
3573 break;
3574 case 0x9:
3575 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 3576 break;
3577 default:
3578 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 3579 "Applying B2 workarounds to unknown rev\n");
3580 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 3581 break;
3582 }
3583 break;
3584
e4e7b892 3585 case chip_7042:
616d4a98 3586 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
306b30f7
ML		 3587 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3588 (pdev->device == 0x2300 || pdev->device == 0x2310))
3589 {
4e520033
ML		 3590 /*
3591 * Highpoint RocketRAID PCIe 23xx series cards:
3592 *
3593 * Unconfigured drives are treated as "Legacy"
3594 * by the BIOS, and it overwrites sector 8 with
3595 * a "Lgcy" metadata block prior to Linux boot.
3596 *
3597 * Configured drives (RAID or JBOD) leave sector 8
3598 * alone, but instead overwrite a high numbered
3599 * sector for the RAID metadata. This sector can
3600 * be determined exactly, by truncating the physical
3601 * drive capacity to a nice even GB value.
3602 *
3603 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3604 *
3605 * Warn the user, lest they think we're just buggy.
3606 */
3607 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3608 " BIOS CORRUPTS DATA on all attached drives,"
3609 " regardless of if/how they are configured."
3610 " BEWARE!\n");
3611 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3612 " use sectors 8-9 on \"Legacy\" drives,"
3613 " and avoid the final two gigabytes on"
3614 " all RocketRAID BIOS initialized drives.\n");
306b30f7 3615 }
8e7decdb 3616 /* drop through */
e4e7b892
JG		 3617 case chip_6042:
3618 hpriv->ops = &mv6xxx_ops;
e4e7b892 3619 hp_flags |= MV_HP_GEN_IIE;
616d4a98
ML		 3620 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3621 hp_flags |= MV_HP_CUT_THROUGH;
e4e7b892 3622
44c10138 3623 switch (pdev->revision) {
5cf73bfb 3624 case 0x2: /* Rev.B0: the first/only public release */
e4e7b892
JG		 3625 hp_flags |= MV_HP_ERRATA_60X1C0;
3626 break;
3627 default:
3628 dev_printk(KERN_WARNING, &pdev->dev,
3629 "Applying 60X1C0 workarounds to unknown rev\n");
3630 hp_flags |= MV_HP_ERRATA_60X1C0;
3631 break;
3632 }
3633 break;
f351b2d6
SB		 3634 case chip_soc:
3635 hpriv->ops = &mv_soc_ops;
eb3a55a9
SB		 3636 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3637 MV_HP_ERRATA_60X1C0;
f351b2d6 3638 break;
e4e7b892 3639
bca1c4eb 3640 default:
f351b2d6 3641 dev_printk(KERN_ERR, host->dev,
5796d1c4 3642 "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 3643 return 1;
3644 }
3645
3646 hpriv->hp_flags = hp_flags;
02a121da
ML		 3647 if (hp_flags & MV_HP_PCIE) {
3648 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3649 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3650 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3651 } else {
3652 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3653 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3654 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3655 }
bca1c4eb
JG		 3656
3657 return 0;
3658}
3659
05b308e1 3660/**
47c2b677 3661 * mv_init_host - Perform some early initialization of the host.
4447d351
TH		 3662 * @host: ATA host to initialize
3663 * @board_idx: controller index
05b308e1
BR		 3664 *
3665 * If possible, do an early global reset of the host. Then do
3666 * our port init and clear/unmask all/relevant host interrupts.
3667 *
3668 * LOCKING:
3669 * Inherited from caller.
3670 */
4447d351 3671static int mv_init_host(struct ata_host *host, unsigned int board_idx)
20f733e7
BR		 3672{
3673 int rc = 0, n_hc, port, hc;
4447d351 3674 struct mv_host_priv *hpriv = host->private_data;
f351b2d6 3675 void __iomem *mmio = hpriv->base;
47c2b677 3676
4447d351 3677 rc = mv_chip_id(host, board_idx);
bca1c4eb 3678 if (rc)
352fab70 3679 goto done;
f351b2d6 3680
1f398472 3681 if (IS_SOC(hpriv)) {
7368f919
ML		 3682 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3683 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
1f398472
ML		 3684 } else {
3685 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3686 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 3687 }
352fab70 3688
5d0fb2e7
TR		 3689 /* initialize shadow irq mask with register's value */
3690 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3691
352fab70 3692 /* global interrupt mask: 0 == mask everything */
c4de573b 3693 mv_set_main_irq_mask(host, ~0, 0);
bca1c4eb 3694
4447d351 3695 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 3696
4447d351 3697 for (port = 0; port < host->n_ports; port++)
47c2b677 3698 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 3699
c9d39130 3700 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 3701 if (rc)
20f733e7 3702 goto done;
20f733e7 3703
522479fb 3704 hpriv->ops->reset_flash(hpriv, mmio);
7bb3c529 3705 hpriv->ops->reset_bus(host, mmio);
47c2b677 3706 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 3707
4447d351 3708 for (port = 0; port < host->n_ports; port++) {
cbcdd875 3709 struct ata_port *ap = host->ports[port];
2a47ce06 3710 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 3711
3712 mv_port_init(&ap->ioaddr, port_mmio);
3713
7bb3c529 3714#ifdef CONFIG_PCI
1f398472 3715 if (!IS_SOC(hpriv)) {
f351b2d6
SB		 3716 unsigned int offset = port_mmio - mmio;
3717 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3718 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3719 }
7bb3c529 3720#endif
20f733e7
BR		 3721 }
3722
3723 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 3724 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3725
3726 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3727 "(before clear)=0x%08x\n", hc,
3728 readl(hc_mmio + HC_CFG_OFS),
3729 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3730
3731 /* Clear any currently outstanding hc interrupt conditions */
3732 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 3733 }
3734
6be96ac1
ML		 3735 /* Clear any currently outstanding host interrupt conditions */
3736 writelfl(0, mmio + hpriv->irq_cause_ofs);
31961943 3737
6be96ac1
ML		 3738 /* and unmask interrupt generation for host regs */
3739 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
51de32d2 3740
6be96ac1
ML		 3741 /*
3742 * enable only global host interrupts for now.
3743 * The per-port interrupts get done later as ports are set up.
3744 */
3745 mv_set_main_irq_mask(host, 0, PCI_ERR);
2b748a0a
ML		 3746 mv_set_irq_coalescing(host, irq_coalescing_io_count,
3747 irq_coalescing_usecs);
f351b2d6
SB		 3748done:
3749 return rc;
3750}
fb621e2f 3751
fbf14e2f
BB		 3752static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3753{
3754 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3755 MV_CRQB_Q_SZ, 0);
3756 if (!hpriv->crqb_pool)
3757 return -ENOMEM;
3758
3759 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3760 MV_CRPB_Q_SZ, 0);
3761 if (!hpriv->crpb_pool)
3762 return -ENOMEM;
3763
3764 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3765 MV_SG_TBL_SZ, 0);
3766 if (!hpriv->sg_tbl_pool)
3767 return -ENOMEM;
3768
3769 return 0;
3770}
3771
15a32632
LB		 3772static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3773 struct mbus_dram_target_info *dram)
3774{
3775 int i;
3776
3777 for (i = 0; i < 4; i++) {
3778 writel(0, hpriv->base + WINDOW_CTRL(i));
3779 writel(0, hpriv->base + WINDOW_BASE(i));
3780 }
3781
3782 for (i = 0; i < dram->num_cs; i++) {
3783 struct mbus_dram_window *cs = dram->cs + i;
3784
3785 writel(((cs->size - 1) & 0xffff0000) |
3786 (cs->mbus_attr << 8) |
3787 (dram->mbus_dram_target_id << 4) | 1,
3788 hpriv->base + WINDOW_CTRL(i));
3789 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3790 }
3791}
3792
f351b2d6
SB		 3793/**
3794 * mv_platform_probe - handle a positive probe of an soc Marvell
3795 * host
3796 * @pdev: platform device found
3797 *
3798 * LOCKING:
3799 * Inherited from caller.
3800 */
3801static int mv_platform_probe(struct platform_device *pdev)
3802{
3803 static int printed_version;
3804 const struct mv_sata_platform_data *mv_platform_data;
3805 const struct ata_port_info *ppi[] =
3806 { &mv_port_info[chip_soc], NULL };
3807 struct ata_host *host;
3808 struct mv_host_priv *hpriv;
3809 struct resource *res;
3810 int n_ports, rc;
20f733e7 3811
f351b2d6
SB		 3812 if (!printed_version++)
3813 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
bca1c4eb 3814
f351b2d6
SB		 3815 /*
3816 * Simple resource validation ..
3817 */
3818 if (unlikely(pdev->num_resources != 2)) {
3819 dev_err(&pdev->dev, "invalid number of resources\n");
3820 return -EINVAL;
3821 }
3822
3823 /*
3824 * Get the register base first
3825 */
3826 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3827 if (res == NULL)
3828 return -EINVAL;
3829
3830 /* allocate host */
3831 mv_platform_data = pdev->dev.platform_data;
3832 n_ports = mv_platform_data->n_ports;
3833
3834 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3835 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3836
3837 if (!host || !hpriv)
3838 return -ENOMEM;
3839 host->private_data = hpriv;
3840 hpriv->n_ports = n_ports;
3841
3842 host->iomap = NULL;
f1cb0ea1
SB		 3843 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3844 res->end - res->start + 1);
f351b2d6
SB		 3845 hpriv->base -= MV_SATAHC0_REG_BASE;
3846
15a32632
LB		 3847 /*
3848 * (Re-)program MBUS remapping windows if we are asked to.
3849 */
3850 if (mv_platform_data->dram != NULL)
3851 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3852
fbf14e2f
BB		 3853 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3854 if (rc)
3855 return rc;
3856
f351b2d6
SB		 3857 /* initialize adapter */
3858 rc = mv_init_host(host, chip_soc);
3859 if (rc)
3860 return rc;
3861
3862 dev_printk(KERN_INFO, &pdev->dev,
3863 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3864 host->n_ports);
3865
3866 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3867 IRQF_SHARED, &mv6_sht);
3868}
3869
3870/*
3871 *
3872 * mv_platform_remove - unplug a platform interface
3873 * @pdev: platform device
3874 *
3875 * A platform bus SATA device has been unplugged. Perform the needed
3876 * cleanup. Also called on module unload for any active devices.
3877 */
3878static int __devexit mv_platform_remove(struct platform_device *pdev)
3879{
3880 struct device *dev = &pdev->dev;
3881 struct ata_host *host = dev_get_drvdata(dev);
f351b2d6
SB		 3882
3883 ata_host_detach(host);
f351b2d6 3884 return 0;
20f733e7
BR		 3885}
3886
f351b2d6
SB		 3887static struct platform_driver mv_platform_driver = {
3888 .probe = mv_platform_probe,
3889 .remove = __devexit_p(mv_platform_remove),
3890 .driver = {
3891 .name = DRV_NAME,
3892 .owner = THIS_MODULE,
3893 },
3894};
3895
3896
7bb3c529 3897#ifdef CONFIG_PCI
f351b2d6
SB		 3898static int mv_pci_init_one(struct pci_dev *pdev,
3899 const struct pci_device_id *ent);
3900
7bb3c529
SB		 3901
3902static struct pci_driver mv_pci_driver = {
3903 .name = DRV_NAME,
3904 .id_table = mv_pci_tbl,
f351b2d6 3905 .probe = mv_pci_init_one,
7bb3c529
SB		 3906 .remove = ata_pci_remove_one,
3907};
3908
7bb3c529
SB		 3909/* move to PCI layer or libata core? */
3910static int pci_go_64(struct pci_dev *pdev)
3911{
3912 int rc;
3913
3914 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3915 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3916 if (rc) {
3917 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3918 if (rc) {
3919 dev_printk(KERN_ERR, &pdev->dev,
3920 "64-bit DMA enable failed\n");
3921 return rc;
3922 }
3923 }
3924 } else {
3925 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3926 if (rc) {
3927 dev_printk(KERN_ERR, &pdev->dev,
3928 "32-bit DMA enable failed\n");
3929 return rc;
3930 }
3931 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3932 if (rc) {
3933 dev_printk(KERN_ERR, &pdev->dev,
3934 "32-bit consistent DMA enable failed\n");
3935 return rc;
3936 }
3937 }
3938
3939 return rc;
3940}
3941
05b308e1
BR		 3942/**
3943 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 3944 * @host: ATA host to print info about
05b308e1
BR		 3945 *
3946 * FIXME: complete this.
3947 *
3948 * LOCKING:
3949 * Inherited from caller.
3950 */
4447d351 3951static void mv_print_info(struct ata_host *host)
31961943 3952{
4447d351
TH		 3953 struct pci_dev *pdev = to_pci_dev(host->dev);
3954 struct mv_host_priv *hpriv = host->private_data;
44c10138 3955 u8 scc;
c1e4fe71 3956 const char *scc_s, *gen;
31961943
BR		 3957
3958 /* Use this to determine the HW stepping of the chip so we know
3959 * what errata to workaround
3960 */
31961943
BR		 3961 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3962 if (scc == 0)
3963 scc_s = "SCSI";
3964 else if (scc == 0x01)
3965 scc_s = "RAID";
3966 else
c1e4fe71
JG		 3967 scc_s = "?";
3968
3969 if (IS_GEN_I(hpriv))
3970 gen = "I";
3971 else if (IS_GEN_II(hpriv))
3972 gen = "II";
3973 else if (IS_GEN_IIE(hpriv))
3974 gen = "IIE";
3975 else
3976 gen = "?";
31961943 3977
a9524a76 3978 dev_printk(KERN_INFO, &pdev->dev,
c1e4fe71
JG		 3979 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3980 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
31961943
BR		 3981 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3982}
3983
05b308e1 3984/**
f351b2d6 3985 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
05b308e1
BR		 3986 * @pdev: PCI device found
3987 * @ent: PCI device ID entry for the matched host
3988 *
3989 * LOCKING:
3990 * Inherited from caller.
3991 */
f351b2d6
SB		 3992static int mv_pci_init_one(struct pci_dev *pdev,
3993 const struct pci_device_id *ent)
20f733e7 3994{
2dcb407e 3995 static int printed_version;
20f733e7 3996 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 3997 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3998 struct ata_host *host;
3999 struct mv_host_priv *hpriv;
4000 int n_ports, rc;
20f733e7 4001
a9524a76
JG		 4002 if (!printed_version++)
4003 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 4004
4447d351
TH		 4005 /* allocate host */
4006 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4007
4008 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4009 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4010 if (!host || !hpriv)
4011 return -ENOMEM;
4012 host->private_data = hpriv;
f351b2d6 4013 hpriv->n_ports = n_ports;
4447d351
TH		 4014
4015 /* acquire resources */
24dc5f33
TH		 4016 rc = pcim_enable_device(pdev);
4017 if (rc)
20f733e7 4018 return rc;
20f733e7 4019
0d5ff566
TH		 4020 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4021 if (rc == -EBUSY)
24dc5f33 4022 pcim_pin_device(pdev);
0d5ff566 4023 if (rc)
24dc5f33 4024 return rc;
4447d351 4025 host->iomap = pcim_iomap_table(pdev);
f351b2d6 4026 hpriv->base = host->iomap[MV_PRIMARY_BAR];
20f733e7 4027
d88184fb
JG		 4028 rc = pci_go_64(pdev);
4029 if (rc)
4030 return rc;
4031
da2fa9ba
ML		 4032 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4033 if (rc)
4034 return rc;
4035
20f733e7 4036 /* initialize adapter */
4447d351 4037 rc = mv_init_host(host, board_idx);
24dc5f33
TH		 4038 if (rc)
4039 return rc;
20f733e7 4040
6d3c30ef
ML		 4041 /* Enable message-switched interrupts, if requested */
4042 if (msi && pci_enable_msi(pdev) == 0)
4043 hpriv->hp_flags |= MV_HP_FLAG_MSI;
20f733e7 4044
31961943 4045 mv_dump_pci_cfg(pdev, 0x68);
4447d351 4046 mv_print_info(host);
20f733e7 4047
4447d351 4048 pci_set_master(pdev);
ea8b4db9 4049 pci_try_set_mwi(pdev);
4447d351 4050 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 4051 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7 4052}
7bb3c529 4053#endif
20f733e7 4054
f351b2d6
SB		 4055static int mv_platform_probe(struct platform_device *pdev);
4056static int __devexit mv_platform_remove(struct platform_device *pdev);
4057
20f733e7
BR		 4058static int __init mv_init(void)
4059{
7bb3c529
SB		 4060 int rc = -ENODEV;
4061#ifdef CONFIG_PCI
4062 rc = pci_register_driver(&mv_pci_driver);
f351b2d6
SB		 4063 if (rc < 0)
4064 return rc;
4065#endif
4066 rc = platform_driver_register(&mv_platform_driver);
4067
4068#ifdef CONFIG_PCI
4069 if (rc < 0)
4070 pci_unregister_driver(&mv_pci_driver);
7bb3c529
SB		 4071#endif
4072 return rc;
20f733e7
BR		 4073}
4074
4075static void __exit mv_exit(void)
4076{
7bb3c529 4077#ifdef CONFIG_PCI
20f733e7 4078 pci_unregister_driver(&mv_pci_driver);
7bb3c529 4079#endif
f351b2d6 4080 platform_driver_unregister(&mv_platform_driver);
20f733e7
BR		 4081}
4082
4083MODULE_AUTHOR("Brett Russ");
4084MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4085MODULE_LICENSE("GPL");
4086MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4087MODULE_VERSION(DRV_VERSION);
17c5aab5 4088MODULE_ALIAS("platform:" DRV_NAME);
20f733e7
BR		 4089
4090module_init(mv_init);
4091module_exit(mv_exit);
kernel source for telekom puls (alcatel/mediatek)