[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / pata_sil680.c

/*
 * pata_sil680.c 	- SIL680 PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *
 * based upon
 *
 * linux/drivers/ide/pci/siimage.c		Version 1.07	Nov 30, 2003
 *
 * Copyright (C) 2001-2002	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2003		Red Hat <alan@redhat.com>
 *
 *  May be copied or modified under the terms of the GNU General Public License
 *
 *  Documentation publicly available.
 *
 *	If you have strange problems with nVidia chipset systems please
 *	see the SI support documentation and update your system BIOS
 *	if necessary
 *
 * TODO
 *	If we know all our devices are LBA28 (or LBA28 sized)  we could use
 *	the command fifo mode.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_sil680"
#define DRV_VERSION "0.4.9"

#define SIL680_MMIO_BAR		5

/**
 *	sil680_selreg		-	return register base
 *	@ap: ATA interface
 *	@r: config offset
 *
 *	Turn a config register offset into the right address in PCI space
 *	to access the control register in question.
 *
 *	Thankfully this is a configuration operation so isn't performance
 *	criticial.
 */

static unsigned long sil680_selreg(struct ata_port *ap, int r)
{
	unsigned long base = 0xA0 + r;
	base += (ap->port_no << 4);
	return base;
}

/**
 *	sil680_seldev		-	return register base
 *	@ap: ATA interface
 *	@r: config offset
 *
 *	Turn a config register offset into the right address in PCI space
 *	to access the control register in question including accounting for
 *	the unit shift.
 */

static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r)
{
	unsigned long base = 0xA0 + r;
	base += (ap->port_no << 4);
	base |= adev->devno ? 2 : 0;
	return base;
}


/**
 *	sil680_cable_detect	-	cable detection
 *	@ap: ATA port
 *
 *	Perform cable detection. The SIL680 stores this in PCI config
 *	space for us.
 */

static int sil680_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned long addr = sil680_selreg(ap, 0);
	u8 ata66;
	pci_read_config_byte(pdev, addr, &ata66);
	if (ata66 & 1)
		return ATA_CBL_PATA80;
	else
		return ATA_CBL_PATA40;
}

/**
 *	sil680_set_piomode	-	set PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the SIL680 registers for PIO mode. Note that the task speed
 *	registers are shared between the devices so we must pick the lowest
 *	mode for command work.
 */

static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	static const u16 speed_p[5] = {
		0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1
	};
	static const u16 speed_t[5] = {
		0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1
	};

	unsigned long tfaddr = sil680_selreg(ap, 0x02);
	unsigned long addr = sil680_seldev(ap, adev, 0x04);
	unsigned long addr_mask = 0x80 + 4 * ap->port_no;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int pio = adev->pio_mode - XFER_PIO_0;
	int lowest_pio = pio;
	int port_shift = 4 * adev->devno;
	u16 reg;
	u8 mode;

	struct ata_device *pair = ata_dev_pair(adev);

	if (pair != NULL && adev->pio_mode > pair->pio_mode)
		lowest_pio = pair->pio_mode - XFER_PIO_0;

	pci_write_config_word(pdev, addr, speed_p[pio]);
	pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);

	pci_read_config_word(pdev, tfaddr-2, &reg);
	pci_read_config_byte(pdev, addr_mask, &mode);

	reg &= ~0x0200;			/* Clear IORDY */
	mode &= ~(3 << port_shift);	/* Clear IORDY and DMA bits */

	if (ata_pio_need_iordy(adev)) {
		reg |= 0x0200;		/* Enable IORDY */
		mode |= 1 << port_shift;
	}
	pci_write_config_word(pdev, tfaddr-2, reg);
	pci_write_config_byte(pdev, addr_mask, mode);
}

/**
 *	sil680_set_dmamode	-	set DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the MWDMA/UDMA modes for the sil680 chipset.
 *
 *	The MWDMA mode values are pulled from a lookup table
 *	while the chipset uses mode number for UDMA.
 */

static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static const u8 ultra_table[2][7] = {
		{ 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF },	/* 100MHz */
		{ 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 },	/* 133Mhz */
	};
	static const u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned long ma = sil680_seldev(ap, adev, 0x08);
	unsigned long ua = sil680_seldev(ap, adev, 0x0C);
	unsigned long addr_mask = 0x80 + 4 * ap->port_no;
	int port_shift = adev->devno * 4;
	u8 scsc, mode;
	u16 multi, ultra;

	pci_read_config_byte(pdev, 0x8A, &scsc);
	pci_read_config_byte(pdev, addr_mask, &mode);
	pci_read_config_word(pdev, ma, &multi);
	pci_read_config_word(pdev, ua, &ultra);

	/* Mask timing bits */
	ultra &= ~0x3F;
	mode &= ~(0x03 << port_shift);

	/* Extract scsc */
	scsc = (scsc & 0x30) ? 1 : 0;

	if (adev->dma_mode >= XFER_UDMA_0) {
		multi = 0x10C1;
		ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];
		mode |= (0x03 << port_shift);
	} else {
		multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];
		mode |= (0x02 << port_shift);
	}
	pci_write_config_byte(pdev, addr_mask, mode);
	pci_write_config_word(pdev, ma, multi);
	pci_write_config_word(pdev, ua, ultra);
}

/**
 *	sil680_sff_exec_command - issue ATA command to host controller
 *	@ap: port to which command is being issued
 *	@tf: ATA taskfile register set
 *
 *	Issues ATA command, with proper synchronization with interrupt
 *	handler / other threads. Use our MMIO space for PCI posting to avoid
 *	a hideously slow cycle all the way to the device.
 *
 *	LOCKING:
 *	spin_lock_irqsave(host lock)
 */
static void sil680_sff_exec_command(struct ata_port *ap,
				    const struct ata_taskfile *tf)
{
	DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
	iowrite8(tf->command, ap->ioaddr.command_addr);
	ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
}

static bool sil680_sff_irq_check(struct ata_port *ap)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	unsigned long addr	= sil680_selreg(ap, 1);
	u8 val;

	pci_read_config_byte(pdev, addr, &val);

	return val & 0x08;
}

static struct scsi_host_template sil680_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};


static struct ata_port_operations sil680_port_ops = {
	.inherits		= &ata_bmdma32_port_ops,
	.sff_exec_command	= sil680_sff_exec_command,
	.sff_irq_check		= sil680_sff_irq_check,
	.cable_detect		= sil680_cable_detect,
	.set_piomode		= sil680_set_piomode,
	.set_dmamode		= sil680_set_dmamode,
};

/**
 *	sil680_init_chip		-	chip setup
 *	@pdev: PCI device
 *
 *	Perform all the chip setup which must be done both when the device
 *	is powered up on boot and when we resume in case we resumed from RAM.
 *	Returns the final clock settings.
 */

static u8 sil680_init_chip(struct pci_dev *pdev, int *try_mmio)
{
	u8 tmpbyte	= 0;

	/* FIXME: double check */
	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
			      pdev->revision ? 1 : 255);

	pci_write_config_byte(pdev, 0x80, 0x00);
	pci_write_config_byte(pdev, 0x84, 0x00);

	pci_read_config_byte(pdev, 0x8A, &tmpbyte);

	dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
		tmpbyte & 1, tmpbyte & 0x30);

	*try_mmio = 0;
#ifdef CONFIG_PPC
	if (machine_is(cell))
		*try_mmio = (tmpbyte & 1) || pci_resource_start(pdev, 5);
#endif

	switch (tmpbyte & 0x30) {
	case 0x00:
		/* 133 clock attempt to force it on */
		pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10);
		break;
	case 0x30:
		/* if clocking is disabled */
		/* 133 clock attempt to force it on */
		pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);
		break;
	case 0x10:
		/* 133 already */
		break;
	case 0x20:
		/* BIOS set PCI x2 clocking */
		break;
	}

	pci_read_config_byte(pdev,   0x8A, &tmpbyte);
	dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
		tmpbyte & 1, tmpbyte & 0x30);

	pci_write_config_byte(pdev,  0xA1, 0x72);
	pci_write_config_word(pdev,  0xA2, 0x328A);
	pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);
	pci_write_config_dword(pdev, 0xA8, 0x43924392);
	pci_write_config_dword(pdev, 0xAC, 0x40094009);
	pci_write_config_byte(pdev,  0xB1, 0x72);
	pci_write_config_word(pdev,  0xB2, 0x328A);
	pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);
	pci_write_config_dword(pdev, 0xB8, 0x43924392);
	pci_write_config_dword(pdev, 0xBC, 0x40094009);

	switch (tmpbyte & 0x30) {
	case 0x00:
		printk(KERN_INFO "sil680: 100MHz clock.\n");
		break;
	case 0x10:
		printk(KERN_INFO "sil680: 133MHz clock.\n");
		break;
	case 0x20:
		printk(KERN_INFO "sil680: Using PCI clock.\n");
		break;
	/* This last case is _NOT_ ok */
	case 0x30:
		printk(KERN_ERR "sil680: Clock disabled ?\n");
	}
	return tmpbyte & 0x30;
}

static int sil680_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info info = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
		.mwdma_mask = ATA_MWDMA2,
		.udma_mask = ATA_UDMA6,
		.port_ops = &sil680_port_ops
	};
	static const struct ata_port_info info_slow = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
		.mwdma_mask = ATA_MWDMA2,
		.udma_mask = ATA_UDMA5,
		.port_ops = &sil680_port_ops
	};
	const struct ata_port_info *ppi[] = { &info, NULL };
	struct ata_host *host;
	void __iomem *mmio_base;
	int rc, try_mmio;

	ata_print_version_once(&pdev->dev, DRV_VERSION);

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	switch (sil680_init_chip(pdev, &try_mmio)) {
		case 0:
			ppi[0] = &info_slow;
			break;
		case 0x30:
			return -ENODEV;
	}

	if (!try_mmio)
		goto use_ioports;

	/* Try to acquire MMIO resources and fallback to PIO if
	 * that fails
	 */
	rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME);
	if (rc)
		goto use_ioports;

	/* Allocate host and set it up */
	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
	if (!host)
		return -ENOMEM;
	host->iomap = pcim_iomap_table(pdev);

	/* Setup DMA masks */
	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;
	pci_set_master(pdev);

	/* Get MMIO base and initialize port addresses */
	mmio_base = host->iomap[SIL680_MMIO_BAR];
	host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00;
	host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80;
	host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a;
	host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a;
	ata_sff_std_ports(&host->ports[0]->ioaddr);
	host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08;
	host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0;
	host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca;
	host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca;
	ata_sff_std_ports(&host->ports[1]->ioaddr);

	/* Register & activate */
	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
				 IRQF_SHARED, &sil680_sht);

use_ioports:
	return ata_pci_bmdma_init_one(pdev, ppi, &sil680_sht, NULL, 0);
}

#ifdef CONFIG_PM
static int sil680_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	int try_mmio, rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;
	sil680_init_chip(pdev, &try_mmio);
	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id sil680[] = {
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), },

	{ },
};

static struct pci_driver sil680_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= sil680,
	.probe 		= sil680_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= sil680_reinit_one,
#endif
};

module_pci_driver(sil680_pci_driver);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for SI680 PATA");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sil680);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_sil680.c - SIL680 PATA for new ATA layer
	3	* (C) 2005 Red Hat Inc
669a5db4 JG	4	*
	5	* based upon
	6	*
	7	* linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003
	8	*
	9	* Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
	10	* Copyright (C) 2003 Red Hat <alan@redhat.com>
	11	*
	12	* May be copied or modified under the terms of the GNU General Public License
	13	*
25985edc	14	* Documentation publicly available.
669a5db4 JG	15	*
	16	* If you have strange problems with nVidia chipset systems please
	17	* see the SI support documentation and update your system BIOS
3a4fa0a2	18	* if necessary
669a5db4 JG	19	*
	20	* TODO
	21	* If we know all our devices are LBA28 (or LBA28 sized) we could use
	22	* the command fifo mode.
	23	*/
	24
	25	#include <linux/kernel.h>
	26	#include <linux/module.h>
	27	#include <linux/pci.h>
	28	#include <linux/init.h>
	29	#include <linux/blkdev.h>
	30	#include <linux/delay.h>
	31	#include <scsi/scsi_host.h>
	32	#include <linux/libata.h>
	33
	34	#define DRV_NAME "pata_sil680"
871af121	35	#define DRV_VERSION "0.4.9"
669a5db4	36
79b0bde1 JG	37	#define SIL680_MMIO_BAR 5
79b0bde1 JG	38
669a5db4 JG	39	/**
669a5db4 JG	40	* sil680_selreg - return register base
6352187e	41	* @ap: ATA interface
669a5db4 JG	42	* @r: config offset
669a5db4 JG	43	*
6352187e BZ	44	* Turn a config register offset into the right address in PCI space
	45	* to access the control register in question.
	46	*
25985edc	47	* Thankfully this is a configuration operation so isn't performance
669a5db4 JG	48	* criticial.
	49	*/
	50
	51	static unsigned long sil680_selreg(struct ata_port *ap, int r)
	52	{
	53	unsigned long base = 0xA0 + r;
	54	base += (ap->port_no << 4);
	55	return base;
	56	}
	57
	58	/**
	59	* sil680_seldev - return register base
6352187e	60	* @ap: ATA interface
669a5db4 JG	61	* @r: config offset
669a5db4 JG	62	*
6352187e BZ	63	* Turn a config register offset into the right address in PCI space
	64	* to access the control register in question including accounting for
	65	* the unit shift.
669a5db4 JG	66	*/
	67
	68	static unsigned long sil680_seldev(struct ata_port ap, struct ata_device adev, int r)
	69	{
	70	unsigned long base = 0xA0 + r;
	71	base += (ap->port_no << 4);
	72	base \|= adev->devno ? 2 : 0;
	73	return base;
	74	}
	75
	76
	77	/**
	78	* sil680_cable_detect - cable detection
	79	* @ap: ATA port
	80	*
	81	* Perform cable detection. The SIL680 stores this in PCI config
	82	* space for us.
	83	*/
	84
7a113d38 BZ	85	static int sil680_cable_detect(struct ata_port *ap)
7a113d38 BZ	86	{
669a5db4 JG	87	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	88	unsigned long addr = sil680_selreg(ap, 0);
	89	u8 ata66;
	90	pci_read_config_byte(pdev, addr, &ata66);
	91	if (ata66 & 1)
	92	return ATA_CBL_PATA80;
	93	else
	94	return ATA_CBL_PATA40;
	95	}
	96
669a5db4	97	/**
6352187e	98	* sil680_set_piomode - set PIO mode data
669a5db4 JG	99	* @ap: ATA interface
	100	* @adev: ATA device
	101	*
	102	* Program the SIL680 registers for PIO mode. Note that the task speed
	103	* registers are shared between the devices so we must pick the lowest
	104	* mode for command work.
	105	*/
	106
	107	static void sil680_set_piomode(struct ata_port ap, struct ata_device adev)
	108	{
9b8ad4ac BZ	109	static const u16 speed_p[5] = {
	110	0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1
	111	};
	112	static const u16 speed_t[5] = {
	113	0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1
	114	};
669a5db4 JG	115
	116	unsigned long tfaddr = sil680_selreg(ap, 0x02);
	117	unsigned long addr = sil680_seldev(ap, adev, 0x04);
cb0e34ba	118	unsigned long addr_mask = 0x80 + 4 * ap->port_no;
669a5db4 JG	119	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	120	int pio = adev->pio_mode - XFER_PIO_0;
	121	int lowest_pio = pio;
cb0e34ba	122	int port_shift = 4 * adev->devno;
669a5db4	123	u16 reg;
cb0e34ba	124	u8 mode;
669a5db4 JG	125
	126	struct ata_device *pair = ata_dev_pair(adev);
	127
	128	if (pair != NULL && adev->pio_mode > pair->pio_mode)
	129	lowest_pio = pair->pio_mode - XFER_PIO_0;
	130
	131	pci_write_config_word(pdev, addr, speed_p[pio]);
	132	pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);
	133
	134	pci_read_config_word(pdev, tfaddr-2, &reg);
cb0e34ba	135	pci_read_config_byte(pdev, addr_mask, &mode);
a84471fe	136
669a5db4	137	reg &= ~0x0200; /* Clear IORDY */
cb0e34ba	138	mode &= ~(3 << port_shift); /* Clear IORDY and DMA bits */
a84471fe	139
cb0e34ba	140	if (ata_pio_need_iordy(adev)) {
669a5db4	141	reg \|= 0x0200; /* Enable IORDY */
cb0e34ba AC	142	mode \|= 1 << port_shift;
cb0e34ba AC	143	}
669a5db4	144	pci_write_config_word(pdev, tfaddr-2, reg);
cb0e34ba	145	pci_write_config_byte(pdev, addr_mask, mode);
669a5db4 JG	146	}
	147
	148	/**
6352187e	149	* sil680_set_dmamode - set DMA mode data
669a5db4 JG	150	* @ap: ATA interface
	151	* @adev: ATA device
	152	*
6352187e BZ	153	* Program the MWDMA/UDMA modes for the sil680 chipset.
	154	*
	155	* The MWDMA mode values are pulled from a lookup table
669a5db4 JG	156	* while the chipset uses mode number for UDMA.
	157	*/
	158
	159	static void sil680_set_dmamode(struct ata_port ap, struct ata_device adev)
	160	{
9b8ad4ac	161	static const u8 ultra_table[2][7] = {
669a5db4 JG	162	{ 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF }, /* 100MHz */
	163	{ 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, /* 133Mhz */
	164	};
9b8ad4ac	165	static const u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };
669a5db4 JG	166
	167	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	168	unsigned long ma = sil680_seldev(ap, adev, 0x08);
	169	unsigned long ua = sil680_seldev(ap, adev, 0x0C);
	170	unsigned long addr_mask = 0x80 + 4 * ap->port_no;
	171	int port_shift = adev->devno * 4;
	172	u8 scsc, mode;
	173	u16 multi, ultra;
	174
	175	pci_read_config_byte(pdev, 0x8A, &scsc);
	176	pci_read_config_byte(pdev, addr_mask, &mode);
	177	pci_read_config_word(pdev, ma, &multi);
	178	pci_read_config_word(pdev, ua, &ultra);
	179
	180	/* Mask timing bits */
	181	ultra &= ~0x3F;
	182	mode &= ~(0x03 << port_shift);
	183
	184	/* Extract scsc */
7a113d38	185	scsc = (scsc & 0x30) ? 1 : 0;
669a5db4 JG	186
	187	if (adev->dma_mode >= XFER_UDMA_0) {
	188	multi = 0x10C1;
	189	ultra \|= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];
	190	mode \|= (0x03 << port_shift);
	191	} else {
	192	multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];
	193	mode \|= (0x02 << port_shift);
	194	}
	195	pci_write_config_byte(pdev, addr_mask, mode);
	196	pci_write_config_word(pdev, ma, multi);
	197	pci_write_config_word(pdev, ua, ultra);
	198	}
	199
c4acf99b AC	200	/**
	201	* sil680_sff_exec_command - issue ATA command to host controller
	202	* @ap: port to which command is being issued
	203	* @tf: ATA taskfile register set
	204	*
	205	* Issues ATA command, with proper synchronization with interrupt
	206	* handler / other threads. Use our MMIO space for PCI posting to avoid
	207	* a hideously slow cycle all the way to the device.
	208	*
	209	* LOCKING:
	210	* spin_lock_irqsave(host lock)
	211	*/
ada5b12e SS	212	static void sil680_sff_exec_command(struct ata_port *ap,
ada5b12e SS	213	const struct ata_taskfile *tf)
c4acf99b AC	214	{
	215	DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
	216	iowrite8(tf->command, ap->ioaddr.command_addr);
	217	ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
	218	}
	219
9b980e10 SS	220	static bool sil680_sff_irq_check(struct ata_port *ap)
	221	{
	222	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	223	unsigned long addr = sil680_selreg(ap, 1);
	224	u8 val;
	225
	226	pci_read_config_byte(pdev, addr, &val);
	227
	228	return val & 0x08;
	229	}
	230
669a5db4	231	static struct scsi_host_template sil680_sht = {
68d1d07b	232	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	233	};
669a5db4 JG	234
c4acf99b	235
669a5db4	236	static struct ata_port_operations sil680_port_ops = {
c4acf99b AC	237	.inherits = &ata_bmdma32_port_ops,
c4acf99b AC	238	.sff_exec_command = sil680_sff_exec_command,
9b980e10	239	.sff_irq_check = sil680_sff_irq_check,
c4acf99b AC	240	.cable_detect = sil680_cable_detect,
	241	.set_piomode = sil680_set_piomode,
	242	.set_dmamode = sil680_set_dmamode,
669a5db4 JG	243	};
669a5db4 JG	244
8550c163 AC	245	/**
	246	* sil680_init_chip - chip setup
	247	* @pdev: PCI device
	248	*
	249	* Perform all the chip setup which must be done both when the device
	250	* is powered up on boot and when we resume in case we resumed from RAM.
	251	* Returns the final clock settings.
	252	*/
f20b16ff	253
2b9e68f7	254	static u8 sil680_init_chip(struct pci_dev pdev, int try_mmio)
669a5db4	255	{
669a5db4 JG	256	u8 tmpbyte = 0;
669a5db4 JG	257
7a113d38	258	/* FIXME: double check */
89d3b360 SS	259	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
89d3b360 SS	260	pdev->revision ? 1 : 255);
669a5db4 JG	261
	262	pci_write_config_byte(pdev, 0x80, 0x00);
	263	pci_write_config_byte(pdev, 0x84, 0x00);
	264
	265	pci_read_config_byte(pdev, 0x8A, &tmpbyte);
	266
79b0bde1 JG	267	dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
79b0bde1 JG	268	tmpbyte & 1, tmpbyte & 0x30);
669a5db4	269
0f436eff	270	*try_mmio = 0;
47d692a9	271	#ifdef CONFIG_PPC
0f436eff BH	272	if (machine_is(cell))
	273	*try_mmio = (tmpbyte & 1) \|\| pci_resource_start(pdev, 5);
	274	#endif
2b9e68f7	275
7a113d38 BZ	276	switch (tmpbyte & 0x30) {
	277	case 0x00:
	278	/* 133 clock attempt to force it on */
	279	pci_write_config_byte(pdev, 0x8A, tmpbyte\|0x10);
	280	break;
	281	case 0x30:
	282	/* if clocking is disabled */
	283	/* 133 clock attempt to force it on */
	284	pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);
	285	break;
	286	case 0x10:
	287	/* 133 already */
	288	break;
	289	case 0x20:
	290	/* BIOS set PCI x2 clocking */
	291	break;
669a5db4 JG	292	}
	293
	294	pci_read_config_byte(pdev, 0x8A, &tmpbyte);
79b0bde1 JG	295	dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
79b0bde1 JG	296	tmpbyte & 1, tmpbyte & 0x30);
669a5db4 JG	297
	298	pci_write_config_byte(pdev, 0xA1, 0x72);
	299	pci_write_config_word(pdev, 0xA2, 0x328A);
	300	pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);
	301	pci_write_config_dword(pdev, 0xA8, 0x43924392);
	302	pci_write_config_dword(pdev, 0xAC, 0x40094009);
	303	pci_write_config_byte(pdev, 0xB1, 0x72);
	304	pci_write_config_word(pdev, 0xB2, 0x328A);
	305	pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);
	306	pci_write_config_dword(pdev, 0xB8, 0x43924392);
	307	pci_write_config_dword(pdev, 0xBC, 0x40094009);
	308
7a113d38 BZ	309	switch (tmpbyte & 0x30) {
	310	case 0x00:
	311	printk(KERN_INFO "sil680: 100MHz clock.\n");
	312	break;
	313	case 0x10:
	314	printk(KERN_INFO "sil680: 133MHz clock.\n");
	315	break;
	316	case 0x20:
	317	printk(KERN_INFO "sil680: Using PCI clock.\n");
	318	break;
	319	/* This last case is _NOT_ ok */
	320	case 0x30:
	321	printk(KERN_ERR "sil680: Clock disabled ?\n");
8550c163 AC	322	}
	323	return tmpbyte & 0x30;
	324	}
	325
0ec24914	326	static int sil680_init_one(struct pci_dev pdev, const struct pci_device_id id)
8550c163	327	{
1626aeb8	328	static const struct ata_port_info info = {
1d2808fd	329	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	330	.pio_mask = ATA_PIO4,
14bdef98 EIB	331	.mwdma_mask = ATA_MWDMA2,
bf6263a8	332	.udma_mask = ATA_UDMA6,
8550c163 AC	333	.port_ops = &sil680_port_ops
8550c163 AC	334	};
1626aeb8	335	static const struct ata_port_info info_slow = {
1d2808fd	336	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	337	.pio_mask = ATA_PIO4,
14bdef98 EIB	338	.mwdma_mask = ATA_MWDMA2,
bf6263a8	339	.udma_mask = ATA_UDMA5,
8550c163 AC	340	.port_ops = &sil680_port_ops
8550c163 AC	341	};
1626aeb8	342	const struct ata_port_info *ppi[] = { &info, NULL };
2b9e68f7 BH	343	struct ata_host *host;
	344	void __iomem *mmio_base;
	345	int rc, try_mmio;
8550c163	346
06296a1e	347	ata_print_version_once(&pdev->dev, DRV_VERSION);
8550c163	348
f08048e9 TH	349	rc = pcim_enable_device(pdev);
	350	if (rc)
	351	return rc;
	352
2b9e68f7	353	switch (sil680_init_chip(pdev, &try_mmio)) {
8550c163	354	case 0:
1626aeb8	355	ppi[0] = &info_slow;
8550c163 AC	356	break;
	357	case 0x30:
	358	return -ENODEV;
669a5db4	359	}
2b9e68f7 BH	360
	361	if (!try_mmio)
	362	goto use_ioports;
	363
	364	/* Try to acquire MMIO resources and fallback to PIO if
	365	* that fails
	366	*/
2b9e68f7 BH	367	rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME);
	368	if (rc)
	369	goto use_ioports;
	370
	371	/* Allocate host and set it up */
	372	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
	373	if (!host)
	374	return -ENOMEM;
	375	host->iomap = pcim_iomap_table(pdev);
	376
	377	/* Setup DMA masks */
	378	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	379	if (rc)
	380	return rc;
	381	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	382	if (rc)
	383	return rc;
	384	pci_set_master(pdev);
	385
	386	/* Get MMIO base and initialize port addresses */
	387	mmio_base = host->iomap[SIL680_MMIO_BAR];
	388	host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00;
	389	host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80;
	390	host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a;
	391	host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a;
9363c382	392	ata_sff_std_ports(&host->ports[0]->ioaddr);
2b9e68f7 BH	393	host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08;
	394	host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0;
	395	host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca;
	396	host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca;
9363c382	397	ata_sff_std_ports(&host->ports[1]->ioaddr);
2b9e68f7 BH	398
2b9e68f7 BH	399	/* Register & activate */
c3b28894	400	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
9363c382	401	IRQF_SHARED, &sil680_sht);
2b9e68f7 BH	402
2b9e68f7 BH	403	use_ioports:
1c5afdf7	404	return ata_pci_bmdma_init_one(pdev, ppi, &sil680_sht, NULL, 0);
669a5db4 JG	405	}
669a5db4 JG	406
438ac6d5	407	#ifdef CONFIG_PM
8550c163 AC	408	static int sil680_reinit_one(struct pci_dev *pdev)
8550c163 AC	409	{
f08048e9 TH	410	struct ata_host *host = dev_get_drvdata(&pdev->dev);
f08048e9 TH	411	int try_mmio, rc;
2b9e68f7	412
f08048e9 TH	413	rc = ata_pci_device_do_resume(pdev);
	414	if (rc)
	415	return rc;
2b9e68f7	416	sil680_init_chip(pdev, &try_mmio);
f08048e9 TH	417	ata_host_resume(host);
f08048e9 TH	418	return 0;
8550c163	419	}
438ac6d5	420	#endif
8550c163	421
669a5db4	422	static const struct pci_device_id sil680[] = {
2d2744fc JG	423	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), },
	424
	425	{ },
669a5db4 JG	426	};
	427
	428	static struct pci_driver sil680_pci_driver = {
2d2744fc	429	.name = DRV_NAME,
669a5db4 JG	430	.id_table = sil680,
669a5db4 JG	431	.probe = sil680_init_one,
8550c163	432	.remove = ata_pci_remove_one,
438ac6d5	433	#ifdef CONFIG_PM
8550c163 AC	434	.suspend = ata_pci_device_suspend,
8550c163 AC	435	.resume = sil680_reinit_one,
438ac6d5	436	#endif
669a5db4 JG	437	};
669a5db4 JG	438
2fc75da0	439	module_pci_driver(sil680_pci_driver);
669a5db4	440
669a5db4 JG	441	MODULE_AUTHOR("Alan Cox");
	442	MODULE_DESCRIPTION("low-level driver for SI680 PATA");
	443	MODULE_LICENSE("GPL");
	444	MODULE_DEVICE_TABLE(pci, sil680);
	445	MODULE_VERSION(DRV_VERSION);