[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / pata_sil680.c

/*
 * pata_sil680.c 	- SIL680 PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 * based upon
 *
 * linux/drivers/ide/pci/siimage.c		Version 1.07	Nov 30, 2003
 *
 * Copyright (C) 2001-2002	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2003		Red Hat <alan@redhat.com>
 *
 *  May be copied or modified under the terms of the GNU General Public License
 *
 *  Documentation publically available.
 *
 *	If you have strange problems with nVidia chipset systems please
 *	see the SI support documentation and update your system BIOS
 *	if neccessary
 *
 * TODO
 *	If we know all our devices are LBA28 (or LBA28 sized)  we could use
 *	the command fifo mode.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_sil680"
#define DRV_VERSION "0.4.5"

/**
 *	sil680_selreg		-	return register base
 *	@hwif: interface
 *	@r: config offset
 *
 *	Turn a config register offset into the right address in either
 *	PCI space or MMIO space to access the control register in question
 *	Thankfully this is a configuration operation so isnt performance
 *	criticial.
 */

static unsigned long sil680_selreg(struct ata_port *ap, int r)
{
	unsigned long base = 0xA0 + r;
	base += (ap->port_no << 4);
	return base;
}

/**
 *	sil680_seldev		-	return register base
 *	@hwif: interface
 *	@r: config offset
 *
 *	Turn a config register offset into the right address in either
 *	PCI space or MMIO space to access the control register in question
 *	including accounting for the unit shift.
 */

static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r)
{
	unsigned long base = 0xA0 + r;
	base += (ap->port_no << 4);
	base |= adev->devno ? 2 : 0;
	return base;
}


/**
 *	sil680_cable_detect	-	cable detection
 *	@ap: ATA port
 *
 *	Perform cable detection. The SIL680 stores this in PCI config
 *	space for us.
 */

static int sil680_cable_detect(struct ata_port *ap) {
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned long addr = sil680_selreg(ap, 0);
	u8 ata66;
	pci_read_config_byte(pdev, addr, &ata66);
	if (ata66 & 1)
		return ATA_CBL_PATA80;
	else
		return ATA_CBL_PATA40;
}

static int sil680_pre_reset(struct ata_port *ap)
{
	ap->cbl = sil680_cable_detect(ap);
	return ata_std_prereset(ap);
}

/**
 *	sil680_bus_reset	-	reset the SIL680 bus
 *	@ap: ATA port to reset
 *
 *	Perform the SIL680 housekeeping when doing an ATA bus reset
 */

static int sil680_bus_reset(struct ata_port *ap,unsigned int *classes)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned long addr = sil680_selreg(ap, 0);
	u8 reset;

	pci_read_config_byte(pdev, addr, &reset);
	pci_write_config_byte(pdev, addr, reset | 0x03);
	udelay(25);
	pci_write_config_byte(pdev, addr, reset);
	return ata_std_softreset(ap, classes);
}

static void sil680_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, sil680_pre_reset, sil680_bus_reset, NULL, ata_std_postreset);
}

/**
 *	sil680_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the SIL680 registers for PIO mode. Note that the task speed
 *	registers are shared between the devices so we must pick the lowest
 *	mode for command work.
 */

static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	static u16 speed_p[5] = { 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 };
	static u16 speed_t[5] = { 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1 };

	unsigned long tfaddr = sil680_selreg(ap, 0x02);
	unsigned long addr = sil680_seldev(ap, adev, 0x04);
	unsigned long addr_mask = 0x80 + 4 * ap->port_no;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int pio = adev->pio_mode - XFER_PIO_0;
	int lowest_pio = pio;
	int port_shift = 4 * adev->devno;
	u16 reg;
	u8 mode;

	struct ata_device *pair = ata_dev_pair(adev);

	if (pair != NULL && adev->pio_mode > pair->pio_mode)
		lowest_pio = pair->pio_mode - XFER_PIO_0;

	pci_write_config_word(pdev, addr, speed_p[pio]);
	pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);

	pci_read_config_word(pdev, tfaddr-2, &reg);
	pci_read_config_byte(pdev, addr_mask, &mode);
	
	reg &= ~0x0200;			/* Clear IORDY */
	mode &= ~(3 << port_shift);	/* Clear IORDY and DMA bits */
	
	if (ata_pio_need_iordy(adev)) {
		reg |= 0x0200;		/* Enable IORDY */
		mode |= 1 << port_shift;
	}
	pci_write_config_word(pdev, tfaddr-2, reg);
	pci_write_config_byte(pdev, addr_mask, mode);
}

/**
 *	sil680_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the MWDMA/UDMA modes for the sil680 k
 *	chipset. The MWDMA mode values are pulled from a lookup table
 *	while the chipset uses mode number for UDMA.
 */

static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static u8 ultra_table[2][7] = {
		{ 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF },	/* 100MHz */
		{ 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 },	/* 133Mhz */
	};
	static u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned long ma = sil680_seldev(ap, adev, 0x08);
	unsigned long ua = sil680_seldev(ap, adev, 0x0C);
	unsigned long addr_mask = 0x80 + 4 * ap->port_no;
	int port_shift = adev->devno * 4;
	u8 scsc, mode;
	u16 multi, ultra;

	pci_read_config_byte(pdev, 0x8A, &scsc);
	pci_read_config_byte(pdev, addr_mask, &mode);
	pci_read_config_word(pdev, ma, &multi);
	pci_read_config_word(pdev, ua, &ultra);

	/* Mask timing bits */
	ultra &= ~0x3F;
	mode &= ~(0x03 << port_shift);

	/* Extract scsc */
	scsc = (scsc & 0x30) ? 1: 0;

	if (adev->dma_mode >= XFER_UDMA_0) {
		multi = 0x10C1;
		ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];
		mode |= (0x03 << port_shift);
	} else {
		multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];
		mode |= (0x02 << port_shift);
	}
	pci_write_config_byte(pdev, addr_mask, mode);
	pci_write_config_word(pdev, ma, multi);
	pci_write_config_word(pdev, ua, ultra);
}

static struct scsi_host_template sil680_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static struct ata_port_operations sil680_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= sil680_set_piomode,
	.set_dmamode	= sil680_set_dmamode,
	.mode_filter	= ata_pci_default_filter,
	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= sil680_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,
	.irq_ack	= ata_irq_ack,

	.port_start	= ata_port_start,
};

/**
 *	sil680_init_chip		-	chip setup
 *	@pdev: PCI device
 *
 *	Perform all the chip setup which must be done both when the device
 *	is powered up on boot and when we resume in case we resumed from RAM.
 *	Returns the final clock settings.
 */

static u8 sil680_init_chip(struct pci_dev *pdev)
{
	u32 class_rev	= 0;
	u8 tmpbyte	= 0;

        pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
        class_rev &= 0xff;
        /* FIXME: double check */
	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);

	pci_write_config_byte(pdev, 0x80, 0x00);
	pci_write_config_byte(pdev, 0x84, 0x00);

	pci_read_config_byte(pdev, 0x8A, &tmpbyte);

	printk(KERN_INFO "sil680: BA5_EN = %d clock = %02X\n",
			tmpbyte & 1, tmpbyte & 0x30);

	switch(tmpbyte & 0x30) {
		case 0x00:
			/* 133 clock attempt to force it on */
			pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10);
			break;
		case 0x30:
			/* if clocking is disabled */
			/* 133 clock attempt to force it on */
			pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);
			break;
		case 0x10:
			/* 133 already */
			break;
		case 0x20:
			/* BIOS set PCI x2 clocking */
			break;
	}

	pci_read_config_byte(pdev,   0x8A, &tmpbyte);
	printk(KERN_INFO "sil680: BA5_EN = %d clock = %02X\n",
			tmpbyte & 1, tmpbyte & 0x30);

	pci_write_config_byte(pdev,  0xA1, 0x72);
	pci_write_config_word(pdev,  0xA2, 0x328A);
	pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);
	pci_write_config_dword(pdev, 0xA8, 0x43924392);
	pci_write_config_dword(pdev, 0xAC, 0x40094009);
	pci_write_config_byte(pdev,  0xB1, 0x72);
	pci_write_config_word(pdev,  0xB2, 0x328A);
	pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);
	pci_write_config_dword(pdev, 0xB8, 0x43924392);
	pci_write_config_dword(pdev, 0xBC, 0x40094009);

	switch(tmpbyte & 0x30) {
		case 0x00: printk(KERN_INFO "sil680: 100MHz clock.\n");break;
		case 0x10: printk(KERN_INFO "sil680: 133MHz clock.\n");break;
		case 0x20: printk(KERN_INFO "sil680: Using PCI clock.\n");break;
		/* This last case is _NOT_ ok */
		case 0x30: printk(KERN_ERR "sil680: Clock disabled ?\n");
	}
	return tmpbyte & 0x30;
}

static int sil680_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static struct ata_port_info info = {
		.sht = &sil680_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = 0x7f,
		.port_ops = &sil680_port_ops
	};
	static struct ata_port_info info_slow = {
		.sht = &sil680_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = 0x3f,
		.port_ops = &sil680_port_ops
	};
	static struct ata_port_info *port_info[2] = {&info, &info};
	static int printed_version;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	switch(sil680_init_chip(pdev))
	{
		case 0:
			port_info[0] = port_info[1] = &info_slow;
			break;
		case 0x30:
			return -ENODEV;
	}
	return ata_pci_init_one(pdev, port_info, 2);
}

static int sil680_reinit_one(struct pci_dev *pdev)
{
	sil680_init_chip(pdev);
	return ata_pci_device_resume(pdev);
}

static const struct pci_device_id sil680[] = {
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), },

	{ },
};

static struct pci_driver sil680_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= sil680,
	.probe 		= sil680_init_one,
	.remove		= ata_pci_remove_one,
	.suspend	= ata_pci_device_suspend,
	.resume		= sil680_reinit_one,
};

static int __init sil680_init(void)
{
	return pci_register_driver(&sil680_pci_driver);
}

static void __exit sil680_exit(void)
{
	pci_unregister_driver(&sil680_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for SI680 PATA");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sil680);
MODULE_VERSION(DRV_VERSION);

module_init(sil680_init);
module_exit(sil680_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_sil680.c - SIL680 PATA for new ATA layer
	3	* (C) 2005 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* based upon
	7	*
	8	* linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003
	9	*
	10	* Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
	11	* Copyright (C) 2003 Red Hat <alan@redhat.com>
	12	*
	13	* May be copied or modified under the terms of the GNU General Public License
	14	*
	15	* Documentation publically available.
	16	*
	17	* If you have strange problems with nVidia chipset systems please
	18	* see the SI support documentation and update your system BIOS
	19	* if neccessary
	20	*
	21	* TODO
	22	* If we know all our devices are LBA28 (or LBA28 sized) we could use
	23	* the command fifo mode.
	24	*/
	25
	26	#include <linux/kernel.h>
	27	#include <linux/module.h>
	28	#include <linux/pci.h>
	29	#include <linux/init.h>
	30	#include <linux/blkdev.h>
	31	#include <linux/delay.h>
	32	#include <scsi/scsi_host.h>
	33	#include <linux/libata.h>
	34
	35	#define DRV_NAME "pata_sil680"
cb0e34ba	36	#define DRV_VERSION "0.4.5"
669a5db4 JG	37
	38	/**
	39	* sil680_selreg - return register base
	40	* @hwif: interface
	41	* @r: config offset
	42	*
	43	* Turn a config register offset into the right address in either
	44	* PCI space or MMIO space to access the control register in question
	45	* Thankfully this is a configuration operation so isnt performance
	46	* criticial.
	47	*/
	48
	49	static unsigned long sil680_selreg(struct ata_port *ap, int r)
	50	{
	51	unsigned long base = 0xA0 + r;
	52	base += (ap->port_no << 4);
	53	return base;
	54	}
	55
	56	/**
	57	* sil680_seldev - return register base
	58	* @hwif: interface
	59	* @r: config offset
	60	*
	61	* Turn a config register offset into the right address in either
	62	* PCI space or MMIO space to access the control register in question
	63	* including accounting for the unit shift.
	64	*/
	65
	66	static unsigned long sil680_seldev(struct ata_port ap, struct ata_device adev, int r)
	67	{
	68	unsigned long base = 0xA0 + r;
	69	base += (ap->port_no << 4);
	70	base \|= adev->devno ? 2 : 0;
	71	return base;
	72	}
	73
	74
	75	/**
	76	* sil680_cable_detect - cable detection
	77	* @ap: ATA port
	78	*
	79	* Perform cable detection. The SIL680 stores this in PCI config
	80	* space for us.
	81	*/
	82
	83	static int sil680_cable_detect(struct ata_port *ap) {
	84	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	85	unsigned long addr = sil680_selreg(ap, 0);
	86	u8 ata66;
	87	pci_read_config_byte(pdev, addr, &ata66);
	88	if (ata66 & 1)
	89	return ATA_CBL_PATA80;
	90	else
	91	return ATA_CBL_PATA40;
	92	}
	93
	94	static int sil680_pre_reset(struct ata_port *ap)
	95	{
	96	ap->cbl = sil680_cable_detect(ap);
	97	return ata_std_prereset(ap);
	98	}
	99
	100	/**
101	* sil680_bus_reset - reset the SIL680 bus
102	* @ap: ATA port to reset
103	*
104	* Perform the SIL680 housekeeping when doing an ATA bus reset
105	*/
106
107	static int sil680_bus_reset(struct ata_port ap,unsigned int classes)
108	{
109	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
110	unsigned long addr = sil680_selreg(ap, 0);
111	u8 reset;
112
113	pci_read_config_byte(pdev, addr, &reset);
114	pci_write_config_byte(pdev, addr, reset \| 0x03);
115	udelay(25);
116	pci_write_config_byte(pdev, addr, reset);
117	return ata_std_softreset(ap, classes);
118	}
119
120	static void sil680_error_handler(struct ata_port *ap)
121	{
122	ata_bmdma_drive_eh(ap, sil680_pre_reset, sil680_bus_reset, NULL, ata_std_postreset);
123	}
124
125	/**
126	* sil680_set_piomode - set initial PIO mode data
127	* @ap: ATA interface
128	* @adev: ATA device
129	*
130	* Program the SIL680 registers for PIO mode. Note that the task speed
131	* registers are shared between the devices so we must pick the lowest
132	* mode for command work.
133	*/
134
135	static void sil680_set_piomode(struct ata_port ap, struct ata_device adev)
136	{
137	static u16 speed_p[5] = { 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 };
5dcade90	138	static u16 speed_t[5] = { 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1 };
669a5db4 JG	139
	140	unsigned long tfaddr = sil680_selreg(ap, 0x02);
	141	unsigned long addr = sil680_seldev(ap, adev, 0x04);
cb0e34ba	142	unsigned long addr_mask = 0x80 + 4 * ap->port_no;
669a5db4 JG	143	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	144	int pio = adev->pio_mode - XFER_PIO_0;
	145	int lowest_pio = pio;
cb0e34ba	146	int port_shift = 4 * adev->devno;
669a5db4	147	u16 reg;
cb0e34ba	148	u8 mode;
669a5db4 JG	149
	150	struct ata_device *pair = ata_dev_pair(adev);
	151
	152	if (pair != NULL && adev->pio_mode > pair->pio_mode)
	153	lowest_pio = pair->pio_mode - XFER_PIO_0;
	154
	155	pci_write_config_word(pdev, addr, speed_p[pio]);
	156	pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);
	157
	158	pci_read_config_word(pdev, tfaddr-2, &reg);
cb0e34ba AC	159	pci_read_config_byte(pdev, addr_mask, &mode);
cb0e34ba AC	160
669a5db4	161	reg &= ~0x0200; /* Clear IORDY */
cb0e34ba AC	162	mode &= ~(3 << port_shift); /* Clear IORDY and DMA bits */
	163
	164	if (ata_pio_need_iordy(adev)) {
669a5db4	165	reg \|= 0x0200; /* Enable IORDY */
cb0e34ba AC	166	mode \|= 1 << port_shift;
cb0e34ba AC	167	}
669a5db4	168	pci_write_config_word(pdev, tfaddr-2, reg);
cb0e34ba	169	pci_write_config_byte(pdev, addr_mask, mode);
669a5db4 JG	170	}
	171
	172	/**
	173	* sil680_set_dmamode - set initial DMA mode data
	174	* @ap: ATA interface
	175	* @adev: ATA device
	176	*
	177	* Program the MWDMA/UDMA modes for the sil680 k
	178	* chipset. The MWDMA mode values are pulled from a lookup table
	179	* while the chipset uses mode number for UDMA.
	180	*/
	181
	182	static void sil680_set_dmamode(struct ata_port ap, struct ata_device adev)
	183	{
	184	static u8 ultra_table[2][7] = {
	185	{ 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF }, /* 100MHz */
	186	{ 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, /* 133Mhz */
	187	};
	188	static u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };
	189
	190	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	191	unsigned long ma = sil680_seldev(ap, adev, 0x08);
	192	unsigned long ua = sil680_seldev(ap, adev, 0x0C);
	193	unsigned long addr_mask = 0x80 + 4 * ap->port_no;
	194	int port_shift = adev->devno * 4;
	195	u8 scsc, mode;
	196	u16 multi, ultra;
	197
	198	pci_read_config_byte(pdev, 0x8A, &scsc);
	199	pci_read_config_byte(pdev, addr_mask, &mode);
	200	pci_read_config_word(pdev, ma, &multi);
	201	pci_read_config_word(pdev, ua, &ultra);
	202
	203	/* Mask timing bits */
	204	ultra &= ~0x3F;
	205	mode &= ~(0x03 << port_shift);
	206
	207	/* Extract scsc */
	208	scsc = (scsc & 0x30) ? 1: 0;
	209
	210	if (adev->dma_mode >= XFER_UDMA_0) {
	211	multi = 0x10C1;
	212	ultra \|= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];
	213	mode \|= (0x03 << port_shift);
	214	} else {
	215	multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];
	216	mode \|= (0x02 << port_shift);
	217	}
	218	pci_write_config_byte(pdev, addr_mask, mode);
	219	pci_write_config_word(pdev, ma, multi);
	220	pci_write_config_word(pdev, ua, ultra);
	221	}
	222
	223	static struct scsi_host_template sil680_sht = {
	224	.module = THIS_MODULE,
	225	.name = DRV_NAME,
	226	.ioctl = ata_scsi_ioctl,
	227	.queuecommand = ata_scsi_queuecmd,
	228	.can_queue = ATA_DEF_QUEUE,
	229	.this_id = ATA_SHT_THIS_ID,
	230	.sg_tablesize = LIBATA_MAX_PRD,
669a5db4 JG	231	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	232	.emulated = ATA_SHT_EMULATED,
	233	.use_clustering = ATA_SHT_USE_CLUSTERING,
	234	.proc_name = DRV_NAME,
	235	.dma_boundary = ATA_DMA_BOUNDARY,
	236	.slave_configure = ata_scsi_slave_config,
afdfe899	237	.slave_destroy = ata_scsi_slave_destroy,
669a5db4 JG	238	.bios_param = ata_std_bios_param,
	239	};
	240
	241	static struct ata_port_operations sil680_port_ops = {
	242	.port_disable = ata_port_disable,
	243	.set_piomode = sil680_set_piomode,
	244	.set_dmamode = sil680_set_dmamode,
	245	.mode_filter = ata_pci_default_filter,
	246	.tf_load = ata_tf_load,
	247	.tf_read = ata_tf_read,
	248	.check_status = ata_check_status,
	249	.exec_command = ata_exec_command,
	250	.dev_select = ata_std_dev_select,
	251
	252	.freeze = ata_bmdma_freeze,
	253	.thaw = ata_bmdma_thaw,
	254	.error_handler = sil680_error_handler,
	255	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	256
	257	.bmdma_setup = ata_bmdma_setup,
	258	.bmdma_start = ata_bmdma_start,
	259	.bmdma_stop = ata_bmdma_stop,
	260	.bmdma_status = ata_bmdma_status,
	261
	262	.qc_prep = ata_qc_prep,
	263	.qc_issue = ata_qc_issue_prot,
bda30288	264
0d5ff566	265	.data_xfer = ata_data_xfer,
669a5db4 JG	266
	267	.irq_handler = ata_interrupt,
	268	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	269	.irq_on = ata_irq_on,
246ce3b6 AI	270	.irq_ack = ata_irq_ack,
669a5db4 JG	271
669a5db4 JG	272	.port_start = ata_port_start,
669a5db4 JG	273	};
669a5db4 JG	274
8550c163 AC	275	/**
	276	* sil680_init_chip - chip setup
	277	* @pdev: PCI device
	278	*
	279	* Perform all the chip setup which must be done both when the device
	280	* is powered up on boot and when we resume in case we resumed from RAM.
	281	* Returns the final clock settings.
	282	*/
f20b16ff	283
8550c163	284	static u8 sil680_init_chip(struct pci_dev *pdev)
669a5db4	285	{
669a5db4 JG	286	u32 class_rev = 0;
	287	u8 tmpbyte = 0;
	288
669a5db4 JG	289	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
	290	class_rev &= 0xff;
	291	/* FIXME: double check */
	292	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
	293
	294	pci_write_config_byte(pdev, 0x80, 0x00);
	295	pci_write_config_byte(pdev, 0x84, 0x00);
	296
	297	pci_read_config_byte(pdev, 0x8A, &tmpbyte);
	298
	299	printk(KERN_INFO "sil680: BA5_EN = %d clock = %02X\n",
	300	tmpbyte & 1, tmpbyte & 0x30);
	301
	302	switch(tmpbyte & 0x30) {
	303	case 0x00:
	304	/* 133 clock attempt to force it on */
	305	pci_write_config_byte(pdev, 0x8A, tmpbyte\|0x10);
	306	break;
	307	case 0x30:
	308	/* if clocking is disabled */
	309	/* 133 clock attempt to force it on */
	310	pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);
	311	break;
	312	case 0x10:
	313	/* 133 already */
	314	break;
	315	case 0x20:
	316	/* BIOS set PCI x2 clocking */
	317	break;
	318	}
	319
	320	pci_read_config_byte(pdev, 0x8A, &tmpbyte);
	321	printk(KERN_INFO "sil680: BA5_EN = %d clock = %02X\n",
	322	tmpbyte & 1, tmpbyte & 0x30);
669a5db4 JG	323
	324	pci_write_config_byte(pdev, 0xA1, 0x72);
	325	pci_write_config_word(pdev, 0xA2, 0x328A);
	326	pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);
	327	pci_write_config_dword(pdev, 0xA8, 0x43924392);
	328	pci_write_config_dword(pdev, 0xAC, 0x40094009);
	329	pci_write_config_byte(pdev, 0xB1, 0x72);
	330	pci_write_config_word(pdev, 0xB2, 0x328A);
	331	pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);
	332	pci_write_config_dword(pdev, 0xB8, 0x43924392);
	333	pci_write_config_dword(pdev, 0xBC, 0x40094009);
	334
	335	switch(tmpbyte & 0x30) {
	336	case 0x00: printk(KERN_INFO "sil680: 100MHz clock.\n");break;
	337	case 0x10: printk(KERN_INFO "sil680: 133MHz clock.\n");break;
	338	case 0x20: printk(KERN_INFO "sil680: Using PCI clock.\n");break;
	339	/* This last case is _NOT_ ok */
	340	case 0x30: printk(KERN_ERR "sil680: Clock disabled ?\n");
8550c163 AC	341	}
	342	return tmpbyte & 0x30;
	343	}
	344
	345	static int sil680_init_one(struct pci_dev pdev, const struct pci_device_id id)
	346	{
	347	static struct ata_port_info info = {
	348	.sht = &sil680_sht,
	349	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	350	.pio_mask = 0x1f,
	351	.mwdma_mask = 0x07,
	352	.udma_mask = 0x7f,
	353	.port_ops = &sil680_port_ops
	354	};
	355	static struct ata_port_info info_slow = {
	356	.sht = &sil680_sht,
	357	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	358	.pio_mask = 0x1f,
	359	.mwdma_mask = 0x07,
	360	.udma_mask = 0x3f,
	361	.port_ops = &sil680_port_ops
	362	};
	363	static struct ata_port_info *port_info[2] = {&info, &info};
	364	static int printed_version;
	365
	366	if (!printed_version++)
	367	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
	368
	369	switch(sil680_init_chip(pdev))
	370	{
	371	case 0:
	372	port_info[0] = port_info[1] = &info_slow;
	373	break;
	374	case 0x30:
	375	return -ENODEV;
669a5db4 JG	376	}
	377	return ata_pci_init_one(pdev, port_info, 2);
	378	}
	379
8550c163 AC	380	static int sil680_reinit_one(struct pci_dev *pdev)
	381	{
	382	sil680_init_chip(pdev);
	383	return ata_pci_device_resume(pdev);
	384	}
	385
669a5db4	386	static const struct pci_device_id sil680[] = {
2d2744fc JG	387	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), },
	388
	389	{ },
669a5db4 JG	390	};
	391
	392	static struct pci_driver sil680_pci_driver = {
2d2744fc	393	.name = DRV_NAME,
669a5db4 JG	394	.id_table = sil680,
669a5db4 JG	395	.probe = sil680_init_one,
8550c163 AC	396	.remove = ata_pci_remove_one,
	397	.suspend = ata_pci_device_suspend,
	398	.resume = sil680_reinit_one,
669a5db4 JG	399	};
	400
	401	static int __init sil680_init(void)
	402	{
	403	return pci_register_driver(&sil680_pci_driver);
	404	}
	405
669a5db4 JG	406	static void __exit sil680_exit(void)
	407	{
	408	pci_unregister_driver(&sil680_pci_driver);
	409	}
	410
669a5db4 JG	411	MODULE_AUTHOR("Alan Cox");
	412	MODULE_DESCRIPTION("low-level driver for SI680 PATA");
	413	MODULE_LICENSE("GPL");
	414	MODULE_DEVICE_TABLE(pci, sil680);
	415	MODULE_VERSION(DRV_VERSION);
	416
	417	module_init(sil680_init);
	418	module_exit(sil680_exit);