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5b3b1688 DD |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2004-2007 Cavium Networks | |
f65aad41 RB |
7 | * Copyright (C) 2008, 2009 Wind River Systems |
8 | * written by Ralf Baechle <ralf@linux-mips.org> | |
5b3b1688 DD |
9 | */ |
10 | #include <linux/init.h> | |
f65aad41 | 11 | #include <linux/kernel.h> |
5b3b1688 DD |
12 | #include <linux/console.h> |
13 | #include <linux/delay.h> | |
f9ded569 | 14 | #include <linux/export.h> |
5b3b1688 DD |
15 | #include <linux/interrupt.h> |
16 | #include <linux/io.h> | |
5b3b1688 | 17 | #include <linux/serial.h> |
631330f5 | 18 | #include <linux/smp.h> |
5b3b1688 DD |
19 | #include <linux/types.h> |
20 | #include <linux/string.h> /* for memset */ | |
5b3b1688 DD |
21 | #include <linux/tty.h> |
22 | #include <linux/time.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/serial_core.h> | |
25 | #include <linux/serial_8250.h> | |
7ed18152 DD |
26 | #include <linux/of_fdt.h> |
27 | #include <linux/libfdt.h> | |
abe77f90 | 28 | #include <linux/kexec.h> |
5b3b1688 DD |
29 | |
30 | #include <asm/processor.h> | |
31 | #include <asm/reboot.h> | |
32 | #include <asm/smp-ops.h> | |
5b3b1688 DD |
33 | #include <asm/irq_cpu.h> |
34 | #include <asm/mipsregs.h> | |
35 | #include <asm/bootinfo.h> | |
36 | #include <asm/sections.h> | |
37 | #include <asm/time.h> | |
38 | ||
39 | #include <asm/octeon/octeon.h> | |
2b5987ab | 40 | #include <asm/octeon/pci-octeon.h> |
e195aa30 | 41 | #include <asm/octeon/cvmx-mio-defs.h> |
5b3b1688 DD |
42 | |
43 | #ifdef CONFIG_CAVIUM_DECODE_RSL | |
44 | extern void cvmx_interrupt_rsl_decode(void); | |
45 | extern int __cvmx_interrupt_ecc_report_single_bit_errors; | |
46 | extern void cvmx_interrupt_rsl_enable(void); | |
47 | #endif | |
48 | ||
49 | extern struct plat_smp_ops octeon_smp_ops; | |
50 | ||
51 | #ifdef CONFIG_PCI | |
52 | extern void pci_console_init(const char *arg); | |
53 | #endif | |
54 | ||
5b3b1688 DD |
55 | static unsigned long long MAX_MEMORY = 512ull << 20; |
56 | ||
57 | struct octeon_boot_descriptor *octeon_boot_desc_ptr; | |
58 | ||
59 | struct cvmx_bootinfo *octeon_bootinfo; | |
60 | EXPORT_SYMBOL(octeon_bootinfo); | |
61 | ||
abe77f90 RB |
62 | static unsigned long long RESERVE_LOW_MEM = 0ull; |
63 | #ifdef CONFIG_KEXEC | |
64 | #ifdef CONFIG_SMP | |
65 | /* | |
66 | * Wait for relocation code is prepared and send | |
67 | * secondary CPUs to spin until kernel is relocated. | |
68 | */ | |
69 | static void octeon_kexec_smp_down(void *ignored) | |
70 | { | |
71 | int cpu = smp_processor_id(); | |
72 | ||
73 | local_irq_disable(); | |
74 | set_cpu_online(cpu, false); | |
75 | while (!atomic_read(&kexec_ready_to_reboot)) | |
76 | cpu_relax(); | |
77 | ||
78 | asm volatile ( | |
79 | " sync \n" | |
80 | " synci ($0) \n"); | |
81 | ||
82 | relocated_kexec_smp_wait(NULL); | |
83 | } | |
84 | #endif | |
85 | ||
86 | #define OCTEON_DDR0_BASE (0x0ULL) | |
87 | #define OCTEON_DDR0_SIZE (0x010000000ULL) | |
88 | #define OCTEON_DDR1_BASE (0x410000000ULL) | |
89 | #define OCTEON_DDR1_SIZE (0x010000000ULL) | |
90 | #define OCTEON_DDR2_BASE (0x020000000ULL) | |
91 | #define OCTEON_DDR2_SIZE (0x3e0000000ULL) | |
92 | #define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL) | |
93 | ||
94 | static struct kimage *kimage_ptr; | |
95 | ||
96 | static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes) | |
97 | { | |
98 | int64_t addr; | |
99 | struct cvmx_bootmem_desc *bootmem_desc; | |
100 | ||
101 | bootmem_desc = cvmx_bootmem_get_desc(); | |
102 | ||
103 | if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) { | |
104 | mem_size = OCTEON_MAX_PHY_MEM_SIZE; | |
105 | pr_err("Error: requested memory too large," | |
106 | "truncating to maximum size\n"); | |
107 | } | |
108 | ||
109 | bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER; | |
110 | bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER; | |
111 | ||
112 | addr = (OCTEON_DDR0_BASE + RESERVE_LOW_MEM + low_reserved_bytes); | |
113 | bootmem_desc->head_addr = 0; | |
114 | ||
115 | if (mem_size <= OCTEON_DDR0_SIZE) { | |
116 | __cvmx_bootmem_phy_free(addr, | |
117 | mem_size - RESERVE_LOW_MEM - | |
118 | low_reserved_bytes, 0); | |
119 | return; | |
120 | } | |
121 | ||
122 | __cvmx_bootmem_phy_free(addr, | |
123 | OCTEON_DDR0_SIZE - RESERVE_LOW_MEM - | |
124 | low_reserved_bytes, 0); | |
125 | ||
126 | mem_size -= OCTEON_DDR0_SIZE; | |
127 | ||
128 | if (mem_size > OCTEON_DDR1_SIZE) { | |
129 | __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0); | |
130 | __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE, | |
131 | mem_size - OCTEON_DDR1_SIZE, 0); | |
132 | } else | |
133 | __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0); | |
134 | } | |
135 | ||
136 | static int octeon_kexec_prepare(struct kimage *image) | |
137 | { | |
138 | int i; | |
139 | char *bootloader = "kexec"; | |
140 | ||
141 | octeon_boot_desc_ptr->argc = 0; | |
142 | for (i = 0; i < image->nr_segments; i++) { | |
143 | if (!strncmp(bootloader, (char *)image->segment[i].buf, | |
144 | strlen(bootloader))) { | |
145 | /* | |
146 | * convert command line string to array | |
147 | * of parameters (as bootloader does). | |
148 | */ | |
149 | int argc = 0, offt; | |
150 | char *str = (char *)image->segment[i].buf; | |
151 | char *ptr = strchr(str, ' '); | |
152 | while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) { | |
153 | *ptr = '\0'; | |
154 | if (ptr[1] != ' ') { | |
155 | offt = (int)(ptr - str + 1); | |
156 | octeon_boot_desc_ptr->argv[argc] = | |
157 | image->segment[i].mem + offt; | |
158 | argc++; | |
159 | } | |
160 | ptr = strchr(ptr + 1, ' '); | |
161 | } | |
162 | octeon_boot_desc_ptr->argc = argc; | |
163 | break; | |
164 | } | |
165 | } | |
166 | ||
167 | /* | |
168 | * Information about segments will be needed during pre-boot memory | |
169 | * initialization. | |
170 | */ | |
171 | kimage_ptr = image; | |
172 | return 0; | |
173 | } | |
174 | ||
175 | static void octeon_generic_shutdown(void) | |
176 | { | |
ed1197f9 ES |
177 | int i; |
178 | #ifdef CONFIG_SMP | |
179 | int cpu; | |
180 | #endif | |
abe77f90 RB |
181 | struct cvmx_bootmem_desc *bootmem_desc; |
182 | void *named_block_array_ptr; | |
183 | ||
184 | bootmem_desc = cvmx_bootmem_get_desc(); | |
185 | named_block_array_ptr = | |
186 | cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr); | |
187 | ||
188 | #ifdef CONFIG_SMP | |
189 | /* disable watchdogs */ | |
190 | for_each_online_cpu(cpu) | |
191 | cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); | |
192 | #else | |
193 | cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); | |
194 | #endif | |
195 | if (kimage_ptr != kexec_crash_image) { | |
196 | memset(named_block_array_ptr, | |
197 | 0x0, | |
198 | CVMX_BOOTMEM_NUM_NAMED_BLOCKS * | |
199 | sizeof(struct cvmx_bootmem_named_block_desc)); | |
200 | /* | |
201 | * Mark all memory (except low 0x100000 bytes) as free. | |
202 | * It is the same thing that bootloader does. | |
203 | */ | |
204 | kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL, | |
205 | 0x100000); | |
206 | /* | |
207 | * Allocate all segments to avoid their corruption during boot. | |
208 | */ | |
209 | for (i = 0; i < kimage_ptr->nr_segments; i++) | |
210 | cvmx_bootmem_alloc_address( | |
211 | kimage_ptr->segment[i].memsz + 2*PAGE_SIZE, | |
212 | kimage_ptr->segment[i].mem - PAGE_SIZE, | |
213 | PAGE_SIZE); | |
214 | } else { | |
215 | /* | |
216 | * Do not mark all memory as free. Free only named sections | |
217 | * leaving the rest of memory unchanged. | |
218 | */ | |
219 | struct cvmx_bootmem_named_block_desc *ptr = | |
220 | (struct cvmx_bootmem_named_block_desc *) | |
221 | named_block_array_ptr; | |
222 | ||
223 | for (i = 0; i < bootmem_desc->named_block_num_blocks; i++) | |
224 | if (ptr[i].size) | |
225 | cvmx_bootmem_free_named(ptr[i].name); | |
226 | } | |
227 | kexec_args[2] = 1UL; /* running on octeon_main_processor */ | |
228 | kexec_args[3] = (unsigned long)octeon_boot_desc_ptr; | |
229 | #ifdef CONFIG_SMP | |
230 | secondary_kexec_args[2] = 0UL; /* running on secondary cpu */ | |
231 | secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr; | |
232 | #endif | |
233 | } | |
234 | ||
235 | static void octeon_shutdown(void) | |
236 | { | |
237 | octeon_generic_shutdown(); | |
238 | #ifdef CONFIG_SMP | |
239 | smp_call_function(octeon_kexec_smp_down, NULL, 0); | |
240 | smp_wmb(); | |
241 | while (num_online_cpus() > 1) { | |
242 | cpu_relax(); | |
243 | mdelay(1); | |
244 | } | |
245 | #endif | |
246 | } | |
247 | ||
248 | static void octeon_crash_shutdown(struct pt_regs *regs) | |
249 | { | |
250 | octeon_generic_shutdown(); | |
251 | default_machine_crash_shutdown(regs); | |
252 | } | |
253 | ||
254 | #endif /* CONFIG_KEXEC */ | |
255 | ||
5b3b1688 DD |
256 | #ifdef CONFIG_CAVIUM_RESERVE32 |
257 | uint64_t octeon_reserve32_memory; | |
258 | EXPORT_SYMBOL(octeon_reserve32_memory); | |
259 | #endif | |
260 | ||
abe77f90 RB |
261 | #ifdef CONFIG_KEXEC |
262 | /* crashkernel cmdline parameter is parsed _after_ memory setup | |
263 | * we also parse it here (workaround for EHB5200) */ | |
264 | static uint64_t crashk_size, crashk_base; | |
265 | #endif | |
266 | ||
5b3b1688 DD |
267 | static int octeon_uart; |
268 | ||
269 | extern asmlinkage void handle_int(void); | |
270 | extern asmlinkage void plat_irq_dispatch(void); | |
271 | ||
272 | /** | |
273 | * Return non zero if we are currently running in the Octeon simulator | |
274 | * | |
275 | * Returns | |
276 | */ | |
277 | int octeon_is_simulation(void) | |
278 | { | |
279 | return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM; | |
280 | } | |
281 | EXPORT_SYMBOL(octeon_is_simulation); | |
282 | ||
283 | /** | |
284 | * Return true if Octeon is in PCI Host mode. This means | |
285 | * Linux can control the PCI bus. | |
286 | * | |
287 | * Returns Non zero if Octeon in host mode. | |
288 | */ | |
289 | int octeon_is_pci_host(void) | |
290 | { | |
291 | #ifdef CONFIG_PCI | |
292 | return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST; | |
293 | #else | |
294 | return 0; | |
295 | #endif | |
296 | } | |
297 | ||
298 | /** | |
299 | * Get the clock rate of Octeon | |
300 | * | |
301 | * Returns Clock rate in HZ | |
302 | */ | |
303 | uint64_t octeon_get_clock_rate(void) | |
304 | { | |
e195aa30 DD |
305 | struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get(); |
306 | ||
307 | return sysinfo->cpu_clock_hz; | |
5b3b1688 DD |
308 | } |
309 | EXPORT_SYMBOL(octeon_get_clock_rate); | |
310 | ||
e195aa30 DD |
311 | static u64 octeon_io_clock_rate; |
312 | ||
313 | u64 octeon_get_io_clock_rate(void) | |
314 | { | |
315 | return octeon_io_clock_rate; | |
316 | } | |
317 | EXPORT_SYMBOL(octeon_get_io_clock_rate); | |
318 | ||
319 | ||
5b3b1688 DD |
320 | /** |
321 | * Write to the LCD display connected to the bootbus. This display | |
322 | * exists on most Cavium evaluation boards. If it doesn't exist, then | |
323 | * this function doesn't do anything. | |
324 | * | |
70342287 | 325 | * @s: String to write |
5b3b1688 DD |
326 | */ |
327 | void octeon_write_lcd(const char *s) | |
328 | { | |
329 | if (octeon_bootinfo->led_display_base_addr) { | |
330 | void __iomem *lcd_address = | |
331 | ioremap_nocache(octeon_bootinfo->led_display_base_addr, | |
332 | 8); | |
333 | int i; | |
334 | for (i = 0; i < 8; i++, s++) { | |
335 | if (*s) | |
336 | iowrite8(*s, lcd_address + i); | |
337 | else | |
338 | iowrite8(' ', lcd_address + i); | |
339 | } | |
340 | iounmap(lcd_address); | |
341 | } | |
342 | } | |
343 | ||
344 | /** | |
345 | * Return the console uart passed by the bootloader | |
346 | * | |
70342287 | 347 | * Returns uart (0 or 1) |
5b3b1688 DD |
348 | */ |
349 | int octeon_get_boot_uart(void) | |
350 | { | |
351 | int uart; | |
352 | #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL | |
353 | uart = 1; | |
354 | #else | |
355 | uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? | |
356 | 1 : 0; | |
357 | #endif | |
358 | return uart; | |
359 | } | |
360 | ||
361 | /** | |
362 | * Get the coremask Linux was booted on. | |
363 | * | |
364 | * Returns Core mask | |
365 | */ | |
366 | int octeon_get_boot_coremask(void) | |
367 | { | |
368 | return octeon_boot_desc_ptr->core_mask; | |
369 | } | |
370 | ||
371 | /** | |
372 | * Check the hardware BIST results for a CPU | |
373 | */ | |
374 | void octeon_check_cpu_bist(void) | |
375 | { | |
376 | const int coreid = cvmx_get_core_num(); | |
377 | unsigned long long mask; | |
378 | unsigned long long bist_val; | |
379 | ||
380 | /* Check BIST results for COP0 registers */ | |
381 | mask = 0x1f00000000ull; | |
382 | bist_val = read_octeon_c0_icacheerr(); | |
383 | if (bist_val & mask) | |
384 | pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n", | |
385 | coreid, bist_val); | |
386 | ||
387 | bist_val = read_octeon_c0_dcacheerr(); | |
388 | if (bist_val & 1) | |
389 | pr_err("Core%d L1 Dcache parity error: " | |
390 | "CacheErr(dcache) = 0x%llx\n", | |
391 | coreid, bist_val); | |
392 | ||
393 | mask = 0xfc00000000000000ull; | |
394 | bist_val = read_c0_cvmmemctl(); | |
395 | if (bist_val & mask) | |
396 | pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n", | |
397 | coreid, bist_val); | |
398 | ||
399 | write_octeon_c0_dcacheerr(0); | |
400 | } | |
401 | ||
5b3b1688 DD |
402 | /** |
403 | * Reboot Octeon | |
404 | * | |
405 | * @command: Command to pass to the bootloader. Currently ignored. | |
406 | */ | |
407 | static void octeon_restart(char *command) | |
408 | { | |
409 | /* Disable all watchdogs before soft reset. They don't get cleared */ | |
410 | #ifdef CONFIG_SMP | |
411 | int cpu; | |
412 | for_each_online_cpu(cpu) | |
413 | cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); | |
414 | #else | |
415 | cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); | |
416 | #endif | |
417 | ||
418 | mb(); | |
419 | while (1) | |
420 | cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); | |
421 | } | |
422 | ||
423 | ||
424 | /** | |
425 | * Permanently stop a core. | |
426 | * | |
427 | * @arg: Ignored. | |
428 | */ | |
429 | static void octeon_kill_core(void *arg) | |
430 | { | |
431 | mb(); | |
432 | if (octeon_is_simulation()) { | |
433 | /* The simulator needs the watchdog to stop for dead cores */ | |
434 | cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); | |
435 | /* A break instruction causes the simulator stop a core */ | |
436 | asm volatile ("sync\nbreak"); | |
437 | } | |
438 | } | |
439 | ||
440 | ||
441 | /** | |
442 | * Halt the system | |
443 | */ | |
444 | static void octeon_halt(void) | |
445 | { | |
446 | smp_call_function(octeon_kill_core, NULL, 0); | |
447 | ||
448 | switch (octeon_bootinfo->board_type) { | |
449 | case CVMX_BOARD_TYPE_NAO38: | |
450 | /* Driving a 1 to GPIO 12 shuts off this board */ | |
451 | cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); | |
452 | cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); | |
453 | break; | |
454 | default: | |
455 | octeon_write_lcd("PowerOff"); | |
456 | break; | |
457 | } | |
458 | ||
459 | octeon_kill_core(NULL); | |
460 | } | |
461 | ||
5b3b1688 DD |
462 | /** |
463 | * Handle all the error condition interrupts that might occur. | |
464 | * | |
465 | */ | |
466 | #ifdef CONFIG_CAVIUM_DECODE_RSL | |
467 | static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id) | |
468 | { | |
469 | cvmx_interrupt_rsl_decode(); | |
470 | return IRQ_HANDLED; | |
471 | } | |
472 | #endif | |
473 | ||
474 | /** | |
475 | * Return a string representing the system type | |
476 | * | |
477 | * Returns | |
478 | */ | |
479 | const char *octeon_board_type_string(void) | |
480 | { | |
481 | static char name[80]; | |
482 | sprintf(name, "%s (%s)", | |
483 | cvmx_board_type_to_string(octeon_bootinfo->board_type), | |
484 | octeon_model_get_string(read_c0_prid())); | |
485 | return name; | |
486 | } | |
487 | ||
488 | const char *get_system_type(void) | |
489 | __attribute__ ((alias("octeon_board_type_string"))); | |
490 | ||
491 | void octeon_user_io_init(void) | |
492 | { | |
493 | union octeon_cvmemctl cvmmemctl; | |
494 | union cvmx_iob_fau_timeout fau_timeout; | |
495 | union cvmx_pow_nw_tim nm_tim; | |
5b3b1688 DD |
496 | |
497 | /* Get the current settings for CP0_CVMMEMCTL_REG */ | |
498 | cvmmemctl.u64 = read_c0_cvmmemctl(); | |
499 | /* R/W If set, marked write-buffer entries time out the same | |
500 | * as as other entries; if clear, marked write-buffer entries | |
501 | * use the maximum timeout. */ | |
502 | cvmmemctl.s.dismarkwblongto = 1; | |
503 | /* R/W If set, a merged store does not clear the write-buffer | |
504 | * entry timeout state. */ | |
505 | cvmmemctl.s.dismrgclrwbto = 0; | |
506 | /* R/W Two bits that are the MSBs of the resultant CVMSEG LM | |
507 | * word location for an IOBDMA. The other 8 bits come from the | |
508 | * SCRADDR field of the IOBDMA. */ | |
509 | cvmmemctl.s.iobdmascrmsb = 0; | |
510 | /* R/W If set, SYNCWS and SYNCS only order marked stores; if | |
511 | * clear, SYNCWS and SYNCS only order unmarked | |
512 | * stores. SYNCWSMARKED has no effect when DISSYNCWS is | |
513 | * set. */ | |
514 | cvmmemctl.s.syncwsmarked = 0; | |
515 | /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */ | |
516 | cvmmemctl.s.dissyncws = 0; | |
517 | /* R/W If set, no stall happens on write buffer full. */ | |
518 | if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) | |
519 | cvmmemctl.s.diswbfst = 1; | |
520 | else | |
521 | cvmmemctl.s.diswbfst = 0; | |
522 | /* R/W If set (and SX set), supervisor-level loads/stores can | |
523 | * use XKPHYS addresses with <48>==0 */ | |
524 | cvmmemctl.s.xkmemenas = 0; | |
525 | ||
526 | /* R/W If set (and UX set), user-level loads/stores can use | |
527 | * XKPHYS addresses with VA<48>==0 */ | |
528 | cvmmemctl.s.xkmemenau = 0; | |
529 | ||
530 | /* R/W If set (and SX set), supervisor-level loads/stores can | |
531 | * use XKPHYS addresses with VA<48>==1 */ | |
532 | cvmmemctl.s.xkioenas = 0; | |
533 | ||
534 | /* R/W If set (and UX set), user-level loads/stores can use | |
535 | * XKPHYS addresses with VA<48>==1 */ | |
536 | cvmmemctl.s.xkioenau = 0; | |
537 | ||
538 | /* R/W If set, all stores act as SYNCW (NOMERGE must be set | |
539 | * when this is set) RW, reset to 0. */ | |
540 | cvmmemctl.s.allsyncw = 0; | |
541 | ||
542 | /* R/W If set, no stores merge, and all stores reach the | |
543 | * coherent bus in order. */ | |
544 | cvmmemctl.s.nomerge = 0; | |
545 | /* R/W Selects the bit in the counter used for DID time-outs 0 | |
546 | * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is | |
547 | * between 1x and 2x this interval. For example, with | |
548 | * DIDTTO=3, expiration interval is between 16K and 32K. */ | |
549 | cvmmemctl.s.didtto = 0; | |
550 | /* R/W If set, the (mem) CSR clock never turns off. */ | |
551 | cvmmemctl.s.csrckalwys = 0; | |
552 | /* R/W If set, mclk never turns off. */ | |
553 | cvmmemctl.s.mclkalwys = 0; | |
554 | /* R/W Selects the bit in the counter used for write buffer | |
555 | * flush time-outs (WBFLT+11) is the bit position in an | |
556 | * internal counter used to determine expiration. The write | |
557 | * buffer expires between 1x and 2x this interval. For | |
558 | * example, with WBFLT = 0, a write buffer expires between 2K | |
559 | * and 4K cycles after the write buffer entry is allocated. */ | |
560 | cvmmemctl.s.wbfltime = 0; | |
561 | /* R/W If set, do not put Istream in the L2 cache. */ | |
562 | cvmmemctl.s.istrnol2 = 0; | |
c9941158 DD |
563 | |
564 | /* | |
565 | * R/W The write buffer threshold. As per erratum Core-14752 | |
566 | * for CN63XX, a sc/scd might fail if the write buffer is | |
567 | * full. Lowering WBTHRESH greatly lowers the chances of the | |
568 | * write buffer ever being full and triggering the erratum. | |
569 | */ | |
570 | if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) | |
571 | cvmmemctl.s.wbthresh = 4; | |
572 | else | |
573 | cvmmemctl.s.wbthresh = 10; | |
574 | ||
5b3b1688 DD |
575 | /* R/W If set, CVMSEG is available for loads/stores in |
576 | * kernel/debug mode. */ | |
577 | #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 | |
578 | cvmmemctl.s.cvmsegenak = 1; | |
579 | #else | |
580 | cvmmemctl.s.cvmsegenak = 0; | |
581 | #endif | |
582 | /* R/W If set, CVMSEG is available for loads/stores in | |
583 | * supervisor mode. */ | |
584 | cvmmemctl.s.cvmsegenas = 0; | |
585 | /* R/W If set, CVMSEG is available for loads/stores in user | |
586 | * mode. */ | |
587 | cvmmemctl.s.cvmsegenau = 0; | |
588 | /* R/W Size of local memory in cache blocks, 54 (6912 bytes) | |
589 | * is max legal value. */ | |
590 | cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE; | |
591 | ||
c9941158 | 592 | write_c0_cvmmemctl(cvmmemctl.u64); |
5b3b1688 DD |
593 | |
594 | if (smp_processor_id() == 0) | |
595 | pr_notice("CVMSEG size: %d cache lines (%d bytes)\n", | |
596 | CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, | |
597 | CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); | |
598 | ||
5b3b1688 DD |
599 | /* Set a default for the hardware timeouts */ |
600 | fau_timeout.u64 = 0; | |
601 | fau_timeout.s.tout_val = 0xfff; | |
602 | /* Disable tagwait FAU timeout */ | |
603 | fau_timeout.s.tout_enb = 0; | |
604 | cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64); | |
605 | ||
606 | nm_tim.u64 = 0; | |
607 | /* 4096 cycles */ | |
608 | nm_tim.s.nw_tim = 3; | |
609 | cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64); | |
610 | ||
611 | write_octeon_c0_icacheerr(0); | |
612 | write_c0_derraddr1(0); | |
613 | } | |
614 | ||
615 | /** | |
616 | * Early entry point for arch setup | |
617 | */ | |
618 | void __init prom_init(void) | |
619 | { | |
620 | struct cvmx_sysinfo *sysinfo; | |
abe77f90 RB |
621 | const char *arg; |
622 | char *p; | |
5b3b1688 DD |
623 | int i; |
624 | int argc; | |
5b3b1688 DD |
625 | #ifdef CONFIG_CAVIUM_RESERVE32 |
626 | int64_t addr = -1; | |
627 | #endif | |
628 | /* | |
629 | * The bootloader passes a pointer to the boot descriptor in | |
630 | * $a3, this is available as fw_arg3. | |
631 | */ | |
632 | octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; | |
633 | octeon_bootinfo = | |
634 | cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); | |
635 | cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr)); | |
636 | ||
e195aa30 DD |
637 | sysinfo = cvmx_sysinfo_get(); |
638 | memset(sysinfo, 0, sizeof(*sysinfo)); | |
639 | sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20; | |
640 | sysinfo->phy_mem_desc_ptr = | |
641 | cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr); | |
642 | sysinfo->core_mask = octeon_bootinfo->core_mask; | |
643 | sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr; | |
644 | sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz; | |
645 | sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2; | |
646 | sysinfo->board_type = octeon_bootinfo->board_type; | |
647 | sysinfo->board_rev_major = octeon_bootinfo->board_rev_major; | |
648 | sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor; | |
649 | memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base, | |
650 | sizeof(sysinfo->mac_addr_base)); | |
651 | sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count; | |
652 | memcpy(sysinfo->board_serial_number, | |
653 | octeon_bootinfo->board_serial_number, | |
654 | sizeof(sysinfo->board_serial_number)); | |
655 | sysinfo->compact_flash_common_base_addr = | |
656 | octeon_bootinfo->compact_flash_common_base_addr; | |
657 | sysinfo->compact_flash_attribute_base_addr = | |
658 | octeon_bootinfo->compact_flash_attribute_base_addr; | |
659 | sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr; | |
660 | sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz; | |
661 | sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags; | |
662 | ||
663 | if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { | |
664 | /* I/O clock runs at a different rate than the CPU. */ | |
665 | union cvmx_mio_rst_boot rst_boot; | |
666 | rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); | |
667 | octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; | |
668 | } else { | |
669 | octeon_io_clock_rate = sysinfo->cpu_clock_hz; | |
670 | } | |
671 | ||
5b3b1688 DD |
672 | /* |
673 | * Only enable the LED controller if we're running on a CN38XX, CN58XX, | |
674 | * or CN56XX. The CN30XX and CN31XX don't have an LED controller. | |
675 | */ | |
676 | if (!octeon_is_simulation() && | |
677 | octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) { | |
678 | cvmx_write_csr(CVMX_LED_EN, 0); | |
679 | cvmx_write_csr(CVMX_LED_PRT, 0); | |
680 | cvmx_write_csr(CVMX_LED_DBG, 0); | |
681 | cvmx_write_csr(CVMX_LED_PRT_FMT, 0); | |
682 | cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32); | |
683 | cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32); | |
684 | cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); | |
685 | cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); | |
686 | cvmx_write_csr(CVMX_LED_EN, 1); | |
687 | } | |
688 | #ifdef CONFIG_CAVIUM_RESERVE32 | |
689 | /* | |
690 | * We need to temporarily allocate all memory in the reserve32 | |
691 | * region. This makes sure the kernel doesn't allocate this | |
692 | * memory when it is getting memory from the | |
693 | * bootloader. Later, after the memory allocations are | |
694 | * complete, the reserve32 will be freed. | |
1ef28870 | 695 | * |
5b3b1688 DD |
696 | * Allocate memory for RESERVED32 aligned on 2MB boundary. This |
697 | * is in case we later use hugetlb entries with it. | |
698 | */ | |
699 | addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, | |
700 | 0, 0, 2 << 20, | |
701 | "CAVIUM_RESERVE32", 0); | |
5b3b1688 DD |
702 | if (addr < 0) |
703 | pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n"); | |
704 | else | |
705 | octeon_reserve32_memory = addr; | |
706 | #endif | |
707 | ||
708 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 | |
709 | if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { | |
710 | pr_info("Skipping L2 locking due to reduced L2 cache size\n"); | |
711 | } else { | |
712 | uint32_t ebase = read_c0_ebase() & 0x3ffff000; | |
713 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB | |
714 | /* TLB refill */ | |
715 | cvmx_l2c_lock_mem_region(ebase, 0x100); | |
716 | #endif | |
717 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION | |
718 | /* General exception */ | |
719 | cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80); | |
720 | #endif | |
721 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT | |
722 | /* Interrupt handler */ | |
723 | cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80); | |
724 | #endif | |
725 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT | |
726 | cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100); | |
727 | cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80); | |
728 | #endif | |
729 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY | |
730 | cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480); | |
731 | #endif | |
732 | } | |
733 | #endif | |
734 | ||
5b3b1688 DD |
735 | octeon_check_cpu_bist(); |
736 | ||
737 | octeon_uart = octeon_get_boot_uart(); | |
738 | ||
5b3b1688 DD |
739 | #ifdef CONFIG_SMP |
740 | octeon_write_lcd("LinuxSMP"); | |
741 | #else | |
742 | octeon_write_lcd("Linux"); | |
743 | #endif | |
744 | ||
745 | #ifdef CONFIG_CAVIUM_GDB | |
746 | /* | |
747 | * When debugging the linux kernel, force the cores to enter | |
748 | * the debug exception handler to break in. | |
749 | */ | |
750 | if (octeon_get_boot_debug_flag()) { | |
751 | cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num()); | |
752 | cvmx_read_csr(CVMX_CIU_DINT); | |
753 | } | |
754 | #endif | |
755 | ||
70a26a21 DD |
756 | octeon_setup_delays(); |
757 | ||
5b3b1688 DD |
758 | /* |
759 | * BIST should always be enabled when doing a soft reset. L2 | |
760 | * Cache locking for instance is not cleared unless BIST is | |
761 | * enabled. Unfortunately due to a chip errata G-200 for | |
762 | * Cn38XX and CN31XX, BIST msut be disabled on these parts. | |
763 | */ | |
764 | if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || | |
765 | OCTEON_IS_MODEL(OCTEON_CN31XX)) | |
766 | cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); | |
767 | else | |
768 | cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1); | |
769 | ||
770 | /* Default to 64MB in the simulator to speed things up */ | |
771 | if (octeon_is_simulation()) | |
772 | MAX_MEMORY = 64ull << 20; | |
773 | ||
abe77f90 RB |
774 | arg = strstr(arcs_cmdline, "mem="); |
775 | if (arg) { | |
776 | MAX_MEMORY = memparse(arg + 4, &p); | |
777 | if (MAX_MEMORY == 0) | |
778 | MAX_MEMORY = 32ull << 30; | |
779 | if (*p == '@') | |
780 | RESERVE_LOW_MEM = memparse(p + 1, &p); | |
781 | } | |
782 | ||
5b3b1688 DD |
783 | arcs_cmdline[0] = 0; |
784 | argc = octeon_boot_desc_ptr->argc; | |
785 | for (i = 0; i < argc; i++) { | |
786 | const char *arg = | |
787 | cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); | |
788 | if ((strncmp(arg, "MEM=", 4) == 0) || | |
789 | (strncmp(arg, "mem=", 4) == 0)) { | |
abe77f90 | 790 | MAX_MEMORY = memparse(arg + 4, &p); |
5b3b1688 DD |
791 | if (MAX_MEMORY == 0) |
792 | MAX_MEMORY = 32ull << 30; | |
abe77f90 RB |
793 | if (*p == '@') |
794 | RESERVE_LOW_MEM = memparse(p + 1, &p); | |
5b3b1688 DD |
795 | } else if (strcmp(arg, "ecc_verbose") == 0) { |
796 | #ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC | |
797 | __cvmx_interrupt_ecc_report_single_bit_errors = 1; | |
798 | pr_notice("Reporting of single bit ECC errors is " | |
799 | "turned on\n"); | |
abe77f90 RB |
800 | #endif |
801 | #ifdef CONFIG_KEXEC | |
802 | } else if (strncmp(arg, "crashkernel=", 12) == 0) { | |
803 | crashk_size = memparse(arg+12, &p); | |
804 | if (*p == '@') | |
805 | crashk_base = memparse(p+1, &p); | |
806 | strcat(arcs_cmdline, " "); | |
807 | strcat(arcs_cmdline, arg); | |
808 | /* | |
809 | * To do: switch parsing to new style, something like: | |
810 | * parse_crashkernel(arg, sysinfo->system_dram_size, | |
70342287 | 811 | * &crashk_size, &crashk_base); |
abe77f90 | 812 | */ |
5b3b1688 DD |
813 | #endif |
814 | } else if (strlen(arcs_cmdline) + strlen(arg) + 1 < | |
815 | sizeof(arcs_cmdline) - 1) { | |
816 | strcat(arcs_cmdline, " "); | |
817 | strcat(arcs_cmdline, arg); | |
818 | } | |
819 | } | |
820 | ||
821 | if (strstr(arcs_cmdline, "console=") == NULL) { | |
5b3b1688 DD |
822 | #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL |
823 | strcat(arcs_cmdline, " console=ttyS0,115200"); | |
824 | #else | |
825 | if (octeon_uart == 1) | |
826 | strcat(arcs_cmdline, " console=ttyS1,115200"); | |
827 | else | |
828 | strcat(arcs_cmdline, " console=ttyS0,115200"); | |
5b3b1688 DD |
829 | #endif |
830 | } | |
831 | ||
832 | if (octeon_is_simulation()) { | |
833 | /* | |
834 | * The simulator uses a mtdram device pre filled with | |
835 | * the filesystem. Also specify the calibration delay | |
836 | * to avoid calculating it every time. | |
837 | */ | |
ca148125 | 838 | strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824"); |
5b3b1688 DD |
839 | } |
840 | ||
841 | mips_hpt_frequency = octeon_get_clock_rate(); | |
842 | ||
843 | octeon_init_cvmcount(); | |
844 | ||
845 | _machine_restart = octeon_restart; | |
846 | _machine_halt = octeon_halt; | |
847 | ||
abe77f90 RB |
848 | #ifdef CONFIG_KEXEC |
849 | _machine_kexec_shutdown = octeon_shutdown; | |
850 | _machine_crash_shutdown = octeon_crash_shutdown; | |
851 | _machine_kexec_prepare = octeon_kexec_prepare; | |
852 | #endif | |
853 | ||
5b3b1688 DD |
854 | octeon_user_io_init(); |
855 | register_smp_ops(&octeon_smp_ops); | |
856 | } | |
857 | ||
2b5987ab | 858 | /* Exclude a single page from the regions obtained in plat_mem_setup. */ |
abe77f90 | 859 | #ifndef CONFIG_CRASH_DUMP |
2b5987ab DD |
860 | static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size) |
861 | { | |
862 | if (addr > *mem && addr < *mem + *size) { | |
863 | u64 inc = addr - *mem; | |
864 | add_memory_region(*mem, inc, BOOT_MEM_RAM); | |
865 | *mem += inc; | |
866 | *size -= inc; | |
867 | } | |
868 | ||
869 | if (addr == *mem && *size > PAGE_SIZE) { | |
870 | *mem += PAGE_SIZE; | |
871 | *size -= PAGE_SIZE; | |
872 | } | |
873 | } | |
abe77f90 | 874 | #endif /* CONFIG_CRASH_DUMP */ |
2b5987ab | 875 | |
5b3b1688 DD |
876 | void __init plat_mem_setup(void) |
877 | { | |
878 | uint64_t mem_alloc_size; | |
879 | uint64_t total; | |
abe77f90 RB |
880 | uint64_t crashk_end; |
881 | #ifndef CONFIG_CRASH_DUMP | |
5b3b1688 | 882 | int64_t memory; |
abe77f90 RB |
883 | uint64_t kernel_start; |
884 | uint64_t kernel_size; | |
885 | #endif | |
5b3b1688 DD |
886 | |
887 | total = 0; | |
abe77f90 | 888 | crashk_end = 0; |
5b3b1688 | 889 | |
5b3b1688 DD |
890 | /* |
891 | * The Mips memory init uses the first memory location for | |
892 | * some memory vectors. When SPARSEMEM is in use, it doesn't | |
893 | * verify that the size is big enough for the final | |
894 | * vectors. Making the smallest chuck 4MB seems to be enough | |
25985edc | 895 | * to consistently work. |
5b3b1688 DD |
896 | */ |
897 | mem_alloc_size = 4 << 20; | |
898 | if (mem_alloc_size > MAX_MEMORY) | |
899 | mem_alloc_size = MAX_MEMORY; | |
900 | ||
abe77f90 RB |
901 | /* Crashkernel ignores bootmem list. It relies on mem=X@Y option */ |
902 | #ifdef CONFIG_CRASH_DUMP | |
903 | add_memory_region(RESERVE_LOW_MEM, MAX_MEMORY, BOOT_MEM_RAM); | |
904 | total += MAX_MEMORY; | |
905 | #else | |
906 | #ifdef CONFIG_KEXEC | |
907 | if (crashk_size > 0) { | |
908 | add_memory_region(crashk_base, crashk_size, BOOT_MEM_RAM); | |
909 | crashk_end = crashk_base + crashk_size; | |
910 | } | |
911 | #endif | |
5b3b1688 DD |
912 | /* |
913 | * When allocating memory, we want incrementing addresses from | |
914 | * bootmem_alloc so the code in add_memory_region can merge | |
915 | * regions next to each other. | |
916 | */ | |
917 | cvmx_bootmem_lock(); | |
918 | while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX) | |
919 | && (total < MAX_MEMORY)) { | |
5b3b1688 DD |
920 | memory = cvmx_bootmem_phy_alloc(mem_alloc_size, |
921 | __pa_symbol(&__init_end), -1, | |
922 | 0x100000, | |
923 | CVMX_BOOTMEM_FLAG_NO_LOCKING); | |
5b3b1688 | 924 | if (memory >= 0) { |
2b5987ab | 925 | u64 size = mem_alloc_size; |
abe77f90 RB |
926 | #ifdef CONFIG_KEXEC |
927 | uint64_t end; | |
928 | #endif | |
2b5987ab DD |
929 | |
930 | /* | |
931 | * exclude a page at the beginning and end of | |
932 | * the 256MB PCIe 'hole' so the kernel will not | |
933 | * try to allocate multi-page buffers that | |
934 | * span the discontinuity. | |
935 | */ | |
936 | memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE, | |
937 | &memory, &size); | |
938 | memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE + | |
939 | CVMX_PCIE_BAR1_PHYS_SIZE, | |
940 | &memory, &size); | |
abe77f90 RB |
941 | #ifdef CONFIG_KEXEC |
942 | end = memory + mem_alloc_size; | |
2b5987ab | 943 | |
5b3b1688 | 944 | /* |
abe77f90 RB |
945 | * This function automatically merges address regions |
946 | * next to each other if they are received in | |
947 | * incrementing order | |
5b3b1688 | 948 | */ |
abe77f90 RB |
949 | if (memory < crashk_base && end > crashk_end) { |
950 | /* region is fully in */ | |
951 | add_memory_region(memory, | |
952 | crashk_base - memory, | |
953 | BOOT_MEM_RAM); | |
954 | total += crashk_base - memory; | |
955 | add_memory_region(crashk_end, | |
956 | end - crashk_end, | |
957 | BOOT_MEM_RAM); | |
958 | total += end - crashk_end; | |
959 | continue; | |
960 | } | |
961 | ||
962 | if (memory >= crashk_base && end <= crashk_end) | |
963 | /* | |
964 | * Entire memory region is within the new | |
965 | * kernel's memory, ignore it. | |
966 | */ | |
967 | continue; | |
968 | ||
969 | if (memory > crashk_base && memory < crashk_end && | |
970 | end > crashk_end) { | |
971 | /* | |
972 | * Overlap with the beginning of the region, | |
973 | * reserve the beginning. | |
974 | */ | |
975 | mem_alloc_size -= crashk_end - memory; | |
976 | memory = crashk_end; | |
977 | } else if (memory < crashk_base && end > crashk_base && | |
978 | end < crashk_end) | |
979 | /* | |
980 | * Overlap with the beginning of the region, | |
981 | * chop of end. | |
982 | */ | |
983 | mem_alloc_size -= end - crashk_base; | |
984 | #endif | |
985 | add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); | |
5b3b1688 | 986 | total += mem_alloc_size; |
abe77f90 RB |
987 | /* Recovering mem_alloc_size */ |
988 | mem_alloc_size = 4 << 20; | |
5b3b1688 DD |
989 | } else { |
990 | break; | |
991 | } | |
992 | } | |
993 | cvmx_bootmem_unlock(); | |
abe77f90 RB |
994 | /* Add the memory region for the kernel. */ |
995 | kernel_start = (unsigned long) _text; | |
996 | kernel_size = ALIGN(_end - _text, 0x100000); | |
997 | ||
998 | /* Adjust for physical offset. */ | |
999 | kernel_start &= ~0xffffffff80000000ULL; | |
1000 | add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM); | |
1001 | #endif /* CONFIG_CRASH_DUMP */ | |
5b3b1688 DD |
1002 | |
1003 | #ifdef CONFIG_CAVIUM_RESERVE32 | |
1004 | /* | |
1005 | * Now that we've allocated the kernel memory it is safe to | |
1006 | * free the reserved region. We free it here so that builtin | |
1007 | * drivers can use the memory. | |
1008 | */ | |
1009 | if (octeon_reserve32_memory) | |
1010 | cvmx_bootmem_free_named("CAVIUM_RESERVE32"); | |
1011 | #endif /* CONFIG_CAVIUM_RESERVE32 */ | |
1012 | ||
1013 | if (total == 0) | |
1014 | panic("Unable to allocate memory from " | |
1015 | "cvmx_bootmem_phy_alloc\n"); | |
1016 | } | |
1017 | ||
ea435464 | 1018 | /* |
70342287 | 1019 | * Emit one character to the boot UART. Exported for use by the |
ea435464 DD |
1020 | * watchdog timer. |
1021 | */ | |
5b3b1688 DD |
1022 | int prom_putchar(char c) |
1023 | { | |
1024 | uint64_t lsrval; | |
1025 | ||
1026 | /* Spin until there is room */ | |
1027 | do { | |
1028 | lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart)); | |
1029 | } while ((lsrval & 0x20) == 0); | |
1030 | ||
1031 | /* Write the byte */ | |
606c958e | 1032 | cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull); |
5b3b1688 DD |
1033 | return 1; |
1034 | } | |
ea435464 | 1035 | EXPORT_SYMBOL(prom_putchar); |
5b3b1688 DD |
1036 | |
1037 | void prom_free_prom_memory(void) | |
1038 | { | |
c9941158 DD |
1039 | if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) { |
1040 | /* Check for presence of Core-14449 fix. */ | |
1041 | u32 insn; | |
1042 | u32 *foo; | |
1043 | ||
1044 | foo = &insn; | |
1045 | ||
1046 | asm volatile("# before" : : : "memory"); | |
1047 | prefetch(foo); | |
1048 | asm volatile( | |
1049 | ".set push\n\t" | |
1050 | ".set noreorder\n\t" | |
1051 | "bal 1f\n\t" | |
1052 | "nop\n" | |
1053 | "1:\tlw %0,-12($31)\n\t" | |
1054 | ".set pop\n\t" | |
1055 | : "=r" (insn) : : "$31", "memory"); | |
1056 | ||
1057 | if ((insn >> 26) != 0x33) | |
ab75dc02 | 1058 | panic("No PREF instruction at Core-14449 probe point."); |
c9941158 DD |
1059 | |
1060 | if (((insn >> 16) & 0x1f) != 28) | |
1061 | panic("Core-14449 WAR not in place (%04x).\n" | |
ab75dc02 | 1062 | "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn); |
c9941158 | 1063 | } |
5b3b1688 DD |
1064 | #ifdef CONFIG_CAVIUM_DECODE_RSL |
1065 | cvmx_interrupt_rsl_enable(); | |
1066 | ||
1067 | /* Add an interrupt handler for general failures. */ | |
1068 | if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED, | |
1069 | "RML/RSL", octeon_rlm_interrupt)) { | |
ab75dc02 | 1070 | panic("Unable to request_irq(OCTEON_IRQ_RML)"); |
5b3b1688 DD |
1071 | } |
1072 | #endif | |
5b3b1688 | 1073 | } |
7ed18152 DD |
1074 | |
1075 | int octeon_prune_device_tree(void); | |
1076 | ||
1077 | extern const char __dtb_octeon_3xxx_begin; | |
1078 | extern const char __dtb_octeon_3xxx_end; | |
1079 | extern const char __dtb_octeon_68xx_begin; | |
1080 | extern const char __dtb_octeon_68xx_end; | |
1081 | void __init device_tree_init(void) | |
1082 | { | |
1083 | int dt_size; | |
1084 | struct boot_param_header *fdt; | |
1085 | bool do_prune; | |
1086 | ||
1087 | if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) { | |
1088 | fdt = phys_to_virt(octeon_bootinfo->fdt_addr); | |
1089 | if (fdt_check_header(fdt)) | |
1090 | panic("Corrupt Device Tree passed to kernel."); | |
1091 | dt_size = be32_to_cpu(fdt->totalsize); | |
1092 | do_prune = false; | |
1093 | } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { | |
1094 | fdt = (struct boot_param_header *)&__dtb_octeon_68xx_begin; | |
1095 | dt_size = &__dtb_octeon_68xx_end - &__dtb_octeon_68xx_begin; | |
1096 | do_prune = true; | |
1097 | } else { | |
1098 | fdt = (struct boot_param_header *)&__dtb_octeon_3xxx_begin; | |
1099 | dt_size = &__dtb_octeon_3xxx_end - &__dtb_octeon_3xxx_begin; | |
1100 | do_prune = true; | |
1101 | } | |
1102 | ||
1103 | /* Copy the default tree from init memory. */ | |
1104 | initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8); | |
1105 | if (initial_boot_params == NULL) | |
1106 | panic("Could not allocate initial_boot_params\n"); | |
1107 | memcpy(initial_boot_params, fdt, dt_size); | |
1108 | ||
1109 | if (do_prune) { | |
1110 | octeon_prune_device_tree(); | |
1111 | pr_info("Using internal Device Tree.\n"); | |
1112 | } else { | |
1113 | pr_info("Using passed Device Tree.\n"); | |
1114 | } | |
1115 | unflatten_device_tree(); | |
1116 | } | |
f65aad41 | 1117 | |
e1ced097 DD |
1118 | static int __initdata disable_octeon_edac_p; |
1119 | ||
1120 | static int __init disable_octeon_edac(char *str) | |
1121 | { | |
1122 | disable_octeon_edac_p = 1; | |
1123 | return 0; | |
1124 | } | |
1125 | early_param("disable_octeon_edac", disable_octeon_edac); | |
1126 | ||
f65aad41 | 1127 | static char *edac_device_names[] = { |
e1ced097 DD |
1128 | "octeon_l2c_edac", |
1129 | "octeon_pc_edac", | |
f65aad41 RB |
1130 | }; |
1131 | ||
1132 | static int __init edac_devinit(void) | |
1133 | { | |
1134 | struct platform_device *dev; | |
1135 | int i, err = 0; | |
e1ced097 | 1136 | int num_lmc; |
f65aad41 RB |
1137 | char *name; |
1138 | ||
e1ced097 DD |
1139 | if (disable_octeon_edac_p) |
1140 | return 0; | |
1141 | ||
f65aad41 RB |
1142 | for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) { |
1143 | name = edac_device_names[i]; | |
1144 | dev = platform_device_register_simple(name, -1, NULL, 0); | |
1145 | if (IS_ERR(dev)) { | |
1146 | pr_err("Registation of %s failed!\n", name); | |
1147 | err = PTR_ERR(dev); | |
1148 | } | |
1149 | } | |
1150 | ||
e1ced097 DD |
1151 | num_lmc = OCTEON_IS_MODEL(OCTEON_CN68XX) ? 4 : |
1152 | (OCTEON_IS_MODEL(OCTEON_CN56XX) ? 2 : 1); | |
1153 | for (i = 0; i < num_lmc; i++) { | |
1154 | dev = platform_device_register_simple("octeon_lmc_edac", | |
1155 | i, NULL, 0); | |
1156 | if (IS_ERR(dev)) { | |
1157 | pr_err("Registation of octeon_lmc_edac %d failed!\n", i); | |
1158 | err = PTR_ERR(dev); | |
1159 | } | |
1160 | } | |
1161 | ||
f65aad41 RB |
1162 | return err; |
1163 | } | |
f65aad41 | 1164 | device_initcall(edac_devinit); |