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5b3b1688 DD |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2004-2007 Cavium Networks | |
7 | * Copyright (C) 2008 Wind River Systems | |
8 | */ | |
9 | #include <linux/init.h> | |
10 | #include <linux/console.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/io.h> | |
5b3b1688 | 14 | #include <linux/serial.h> |
631330f5 | 15 | #include <linux/smp.h> |
5b3b1688 DD |
16 | #include <linux/types.h> |
17 | #include <linux/string.h> /* for memset */ | |
5b3b1688 DD |
18 | #include <linux/tty.h> |
19 | #include <linux/time.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/serial_core.h> | |
22 | #include <linux/serial_8250.h> | |
5b3b1688 DD |
23 | |
24 | #include <asm/processor.h> | |
25 | #include <asm/reboot.h> | |
26 | #include <asm/smp-ops.h> | |
27 | #include <asm/system.h> | |
28 | #include <asm/irq_cpu.h> | |
29 | #include <asm/mipsregs.h> | |
30 | #include <asm/bootinfo.h> | |
31 | #include <asm/sections.h> | |
32 | #include <asm/time.h> | |
33 | ||
34 | #include <asm/octeon/octeon.h> | |
2b5987ab | 35 | #include <asm/octeon/pci-octeon.h> |
5b3b1688 DD |
36 | |
37 | #ifdef CONFIG_CAVIUM_DECODE_RSL | |
38 | extern void cvmx_interrupt_rsl_decode(void); | |
39 | extern int __cvmx_interrupt_ecc_report_single_bit_errors; | |
40 | extern void cvmx_interrupt_rsl_enable(void); | |
41 | #endif | |
42 | ||
43 | extern struct plat_smp_ops octeon_smp_ops; | |
44 | ||
45 | #ifdef CONFIG_PCI | |
46 | extern void pci_console_init(const char *arg); | |
47 | #endif | |
48 | ||
5b3b1688 DD |
49 | static unsigned long long MAX_MEMORY = 512ull << 20; |
50 | ||
51 | struct octeon_boot_descriptor *octeon_boot_desc_ptr; | |
52 | ||
53 | struct cvmx_bootinfo *octeon_bootinfo; | |
54 | EXPORT_SYMBOL(octeon_bootinfo); | |
55 | ||
56 | #ifdef CONFIG_CAVIUM_RESERVE32 | |
57 | uint64_t octeon_reserve32_memory; | |
58 | EXPORT_SYMBOL(octeon_reserve32_memory); | |
59 | #endif | |
60 | ||
61 | static int octeon_uart; | |
62 | ||
63 | extern asmlinkage void handle_int(void); | |
64 | extern asmlinkage void plat_irq_dispatch(void); | |
65 | ||
66 | /** | |
67 | * Return non zero if we are currently running in the Octeon simulator | |
68 | * | |
69 | * Returns | |
70 | */ | |
71 | int octeon_is_simulation(void) | |
72 | { | |
73 | return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM; | |
74 | } | |
75 | EXPORT_SYMBOL(octeon_is_simulation); | |
76 | ||
77 | /** | |
78 | * Return true if Octeon is in PCI Host mode. This means | |
79 | * Linux can control the PCI bus. | |
80 | * | |
81 | * Returns Non zero if Octeon in host mode. | |
82 | */ | |
83 | int octeon_is_pci_host(void) | |
84 | { | |
85 | #ifdef CONFIG_PCI | |
86 | return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST; | |
87 | #else | |
88 | return 0; | |
89 | #endif | |
90 | } | |
91 | ||
92 | /** | |
93 | * Get the clock rate of Octeon | |
94 | * | |
95 | * Returns Clock rate in HZ | |
96 | */ | |
97 | uint64_t octeon_get_clock_rate(void) | |
98 | { | |
5b3b1688 DD |
99 | return octeon_bootinfo->eclock_hz; |
100 | } | |
101 | EXPORT_SYMBOL(octeon_get_clock_rate); | |
102 | ||
103 | /** | |
104 | * Write to the LCD display connected to the bootbus. This display | |
105 | * exists on most Cavium evaluation boards. If it doesn't exist, then | |
106 | * this function doesn't do anything. | |
107 | * | |
108 | * @s: String to write | |
109 | */ | |
110 | void octeon_write_lcd(const char *s) | |
111 | { | |
112 | if (octeon_bootinfo->led_display_base_addr) { | |
113 | void __iomem *lcd_address = | |
114 | ioremap_nocache(octeon_bootinfo->led_display_base_addr, | |
115 | 8); | |
116 | int i; | |
117 | for (i = 0; i < 8; i++, s++) { | |
118 | if (*s) | |
119 | iowrite8(*s, lcd_address + i); | |
120 | else | |
121 | iowrite8(' ', lcd_address + i); | |
122 | } | |
123 | iounmap(lcd_address); | |
124 | } | |
125 | } | |
126 | ||
127 | /** | |
128 | * Return the console uart passed by the bootloader | |
129 | * | |
130 | * Returns uart (0 or 1) | |
131 | */ | |
132 | int octeon_get_boot_uart(void) | |
133 | { | |
134 | int uart; | |
135 | #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL | |
136 | uart = 1; | |
137 | #else | |
138 | uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? | |
139 | 1 : 0; | |
140 | #endif | |
141 | return uart; | |
142 | } | |
143 | ||
144 | /** | |
145 | * Get the coremask Linux was booted on. | |
146 | * | |
147 | * Returns Core mask | |
148 | */ | |
149 | int octeon_get_boot_coremask(void) | |
150 | { | |
151 | return octeon_boot_desc_ptr->core_mask; | |
152 | } | |
153 | ||
154 | /** | |
155 | * Check the hardware BIST results for a CPU | |
156 | */ | |
157 | void octeon_check_cpu_bist(void) | |
158 | { | |
159 | const int coreid = cvmx_get_core_num(); | |
160 | unsigned long long mask; | |
161 | unsigned long long bist_val; | |
162 | ||
163 | /* Check BIST results for COP0 registers */ | |
164 | mask = 0x1f00000000ull; | |
165 | bist_val = read_octeon_c0_icacheerr(); | |
166 | if (bist_val & mask) | |
167 | pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n", | |
168 | coreid, bist_val); | |
169 | ||
170 | bist_val = read_octeon_c0_dcacheerr(); | |
171 | if (bist_val & 1) | |
172 | pr_err("Core%d L1 Dcache parity error: " | |
173 | "CacheErr(dcache) = 0x%llx\n", | |
174 | coreid, bist_val); | |
175 | ||
176 | mask = 0xfc00000000000000ull; | |
177 | bist_val = read_c0_cvmmemctl(); | |
178 | if (bist_val & mask) | |
179 | pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n", | |
180 | coreid, bist_val); | |
181 | ||
182 | write_octeon_c0_dcacheerr(0); | |
183 | } | |
184 | ||
5b3b1688 DD |
185 | /** |
186 | * Reboot Octeon | |
187 | * | |
188 | * @command: Command to pass to the bootloader. Currently ignored. | |
189 | */ | |
190 | static void octeon_restart(char *command) | |
191 | { | |
192 | /* Disable all watchdogs before soft reset. They don't get cleared */ | |
193 | #ifdef CONFIG_SMP | |
194 | int cpu; | |
195 | for_each_online_cpu(cpu) | |
196 | cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); | |
197 | #else | |
198 | cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); | |
199 | #endif | |
200 | ||
201 | mb(); | |
202 | while (1) | |
203 | cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); | |
204 | } | |
205 | ||
206 | ||
207 | /** | |
208 | * Permanently stop a core. | |
209 | * | |
210 | * @arg: Ignored. | |
211 | */ | |
212 | static void octeon_kill_core(void *arg) | |
213 | { | |
214 | mb(); | |
215 | if (octeon_is_simulation()) { | |
216 | /* The simulator needs the watchdog to stop for dead cores */ | |
217 | cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); | |
218 | /* A break instruction causes the simulator stop a core */ | |
219 | asm volatile ("sync\nbreak"); | |
220 | } | |
221 | } | |
222 | ||
223 | ||
224 | /** | |
225 | * Halt the system | |
226 | */ | |
227 | static void octeon_halt(void) | |
228 | { | |
229 | smp_call_function(octeon_kill_core, NULL, 0); | |
230 | ||
231 | switch (octeon_bootinfo->board_type) { | |
232 | case CVMX_BOARD_TYPE_NAO38: | |
233 | /* Driving a 1 to GPIO 12 shuts off this board */ | |
234 | cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); | |
235 | cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); | |
236 | break; | |
237 | default: | |
238 | octeon_write_lcd("PowerOff"); | |
239 | break; | |
240 | } | |
241 | ||
242 | octeon_kill_core(NULL); | |
243 | } | |
244 | ||
5b3b1688 DD |
245 | /** |
246 | * Handle all the error condition interrupts that might occur. | |
247 | * | |
248 | */ | |
249 | #ifdef CONFIG_CAVIUM_DECODE_RSL | |
250 | static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id) | |
251 | { | |
252 | cvmx_interrupt_rsl_decode(); | |
253 | return IRQ_HANDLED; | |
254 | } | |
255 | #endif | |
256 | ||
257 | /** | |
258 | * Return a string representing the system type | |
259 | * | |
260 | * Returns | |
261 | */ | |
262 | const char *octeon_board_type_string(void) | |
263 | { | |
264 | static char name[80]; | |
265 | sprintf(name, "%s (%s)", | |
266 | cvmx_board_type_to_string(octeon_bootinfo->board_type), | |
267 | octeon_model_get_string(read_c0_prid())); | |
268 | return name; | |
269 | } | |
270 | ||
271 | const char *get_system_type(void) | |
272 | __attribute__ ((alias("octeon_board_type_string"))); | |
273 | ||
274 | void octeon_user_io_init(void) | |
275 | { | |
276 | union octeon_cvmemctl cvmmemctl; | |
277 | union cvmx_iob_fau_timeout fau_timeout; | |
278 | union cvmx_pow_nw_tim nm_tim; | |
279 | uint64_t cvmctl; | |
280 | ||
281 | /* Get the current settings for CP0_CVMMEMCTL_REG */ | |
282 | cvmmemctl.u64 = read_c0_cvmmemctl(); | |
283 | /* R/W If set, marked write-buffer entries time out the same | |
284 | * as as other entries; if clear, marked write-buffer entries | |
285 | * use the maximum timeout. */ | |
286 | cvmmemctl.s.dismarkwblongto = 1; | |
287 | /* R/W If set, a merged store does not clear the write-buffer | |
288 | * entry timeout state. */ | |
289 | cvmmemctl.s.dismrgclrwbto = 0; | |
290 | /* R/W Two bits that are the MSBs of the resultant CVMSEG LM | |
291 | * word location for an IOBDMA. The other 8 bits come from the | |
292 | * SCRADDR field of the IOBDMA. */ | |
293 | cvmmemctl.s.iobdmascrmsb = 0; | |
294 | /* R/W If set, SYNCWS and SYNCS only order marked stores; if | |
295 | * clear, SYNCWS and SYNCS only order unmarked | |
296 | * stores. SYNCWSMARKED has no effect when DISSYNCWS is | |
297 | * set. */ | |
298 | cvmmemctl.s.syncwsmarked = 0; | |
299 | /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */ | |
300 | cvmmemctl.s.dissyncws = 0; | |
301 | /* R/W If set, no stall happens on write buffer full. */ | |
302 | if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) | |
303 | cvmmemctl.s.diswbfst = 1; | |
304 | else | |
305 | cvmmemctl.s.diswbfst = 0; | |
306 | /* R/W If set (and SX set), supervisor-level loads/stores can | |
307 | * use XKPHYS addresses with <48>==0 */ | |
308 | cvmmemctl.s.xkmemenas = 0; | |
309 | ||
310 | /* R/W If set (and UX set), user-level loads/stores can use | |
311 | * XKPHYS addresses with VA<48>==0 */ | |
312 | cvmmemctl.s.xkmemenau = 0; | |
313 | ||
314 | /* R/W If set (and SX set), supervisor-level loads/stores can | |
315 | * use XKPHYS addresses with VA<48>==1 */ | |
316 | cvmmemctl.s.xkioenas = 0; | |
317 | ||
318 | /* R/W If set (and UX set), user-level loads/stores can use | |
319 | * XKPHYS addresses with VA<48>==1 */ | |
320 | cvmmemctl.s.xkioenau = 0; | |
321 | ||
322 | /* R/W If set, all stores act as SYNCW (NOMERGE must be set | |
323 | * when this is set) RW, reset to 0. */ | |
324 | cvmmemctl.s.allsyncw = 0; | |
325 | ||
326 | /* R/W If set, no stores merge, and all stores reach the | |
327 | * coherent bus in order. */ | |
328 | cvmmemctl.s.nomerge = 0; | |
329 | /* R/W Selects the bit in the counter used for DID time-outs 0 | |
330 | * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is | |
331 | * between 1x and 2x this interval. For example, with | |
332 | * DIDTTO=3, expiration interval is between 16K and 32K. */ | |
333 | cvmmemctl.s.didtto = 0; | |
334 | /* R/W If set, the (mem) CSR clock never turns off. */ | |
335 | cvmmemctl.s.csrckalwys = 0; | |
336 | /* R/W If set, mclk never turns off. */ | |
337 | cvmmemctl.s.mclkalwys = 0; | |
338 | /* R/W Selects the bit in the counter used for write buffer | |
339 | * flush time-outs (WBFLT+11) is the bit position in an | |
340 | * internal counter used to determine expiration. The write | |
341 | * buffer expires between 1x and 2x this interval. For | |
342 | * example, with WBFLT = 0, a write buffer expires between 2K | |
343 | * and 4K cycles after the write buffer entry is allocated. */ | |
344 | cvmmemctl.s.wbfltime = 0; | |
345 | /* R/W If set, do not put Istream in the L2 cache. */ | |
346 | cvmmemctl.s.istrnol2 = 0; | |
347 | /* R/W The write buffer threshold. */ | |
348 | cvmmemctl.s.wbthresh = 10; | |
349 | /* R/W If set, CVMSEG is available for loads/stores in | |
350 | * kernel/debug mode. */ | |
351 | #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 | |
352 | cvmmemctl.s.cvmsegenak = 1; | |
353 | #else | |
354 | cvmmemctl.s.cvmsegenak = 0; | |
355 | #endif | |
356 | /* R/W If set, CVMSEG is available for loads/stores in | |
357 | * supervisor mode. */ | |
358 | cvmmemctl.s.cvmsegenas = 0; | |
359 | /* R/W If set, CVMSEG is available for loads/stores in user | |
360 | * mode. */ | |
361 | cvmmemctl.s.cvmsegenau = 0; | |
362 | /* R/W Size of local memory in cache blocks, 54 (6912 bytes) | |
363 | * is max legal value. */ | |
364 | cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE; | |
365 | ||
366 | ||
367 | if (smp_processor_id() == 0) | |
368 | pr_notice("CVMSEG size: %d cache lines (%d bytes)\n", | |
369 | CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, | |
370 | CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); | |
371 | ||
372 | write_c0_cvmmemctl(cvmmemctl.u64); | |
373 | ||
374 | /* Move the performance counter interrupts to IRQ 6 */ | |
375 | cvmctl = read_c0_cvmctl(); | |
376 | cvmctl &= ~(7 << 7); | |
377 | cvmctl |= 6 << 7; | |
378 | write_c0_cvmctl(cvmctl); | |
379 | ||
380 | /* Set a default for the hardware timeouts */ | |
381 | fau_timeout.u64 = 0; | |
382 | fau_timeout.s.tout_val = 0xfff; | |
383 | /* Disable tagwait FAU timeout */ | |
384 | fau_timeout.s.tout_enb = 0; | |
385 | cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64); | |
386 | ||
387 | nm_tim.u64 = 0; | |
388 | /* 4096 cycles */ | |
389 | nm_tim.s.nw_tim = 3; | |
390 | cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64); | |
391 | ||
392 | write_octeon_c0_icacheerr(0); | |
393 | write_c0_derraddr1(0); | |
394 | } | |
395 | ||
396 | /** | |
397 | * Early entry point for arch setup | |
398 | */ | |
399 | void __init prom_init(void) | |
400 | { | |
401 | struct cvmx_sysinfo *sysinfo; | |
402 | const int coreid = cvmx_get_core_num(); | |
403 | int i; | |
404 | int argc; | |
5b3b1688 DD |
405 | #ifdef CONFIG_CAVIUM_RESERVE32 |
406 | int64_t addr = -1; | |
407 | #endif | |
408 | /* | |
409 | * The bootloader passes a pointer to the boot descriptor in | |
410 | * $a3, this is available as fw_arg3. | |
411 | */ | |
412 | octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; | |
413 | octeon_bootinfo = | |
414 | cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); | |
415 | cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr)); | |
416 | ||
417 | /* | |
418 | * Only enable the LED controller if we're running on a CN38XX, CN58XX, | |
419 | * or CN56XX. The CN30XX and CN31XX don't have an LED controller. | |
420 | */ | |
421 | if (!octeon_is_simulation() && | |
422 | octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) { | |
423 | cvmx_write_csr(CVMX_LED_EN, 0); | |
424 | cvmx_write_csr(CVMX_LED_PRT, 0); | |
425 | cvmx_write_csr(CVMX_LED_DBG, 0); | |
426 | cvmx_write_csr(CVMX_LED_PRT_FMT, 0); | |
427 | cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32); | |
428 | cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32); | |
429 | cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); | |
430 | cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); | |
431 | cvmx_write_csr(CVMX_LED_EN, 1); | |
432 | } | |
433 | #ifdef CONFIG_CAVIUM_RESERVE32 | |
434 | /* | |
435 | * We need to temporarily allocate all memory in the reserve32 | |
436 | * region. This makes sure the kernel doesn't allocate this | |
437 | * memory when it is getting memory from the | |
438 | * bootloader. Later, after the memory allocations are | |
439 | * complete, the reserve32 will be freed. | |
1ef28870 | 440 | * |
5b3b1688 DD |
441 | * Allocate memory for RESERVED32 aligned on 2MB boundary. This |
442 | * is in case we later use hugetlb entries with it. | |
443 | */ | |
444 | addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, | |
445 | 0, 0, 2 << 20, | |
446 | "CAVIUM_RESERVE32", 0); | |
5b3b1688 DD |
447 | if (addr < 0) |
448 | pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n"); | |
449 | else | |
450 | octeon_reserve32_memory = addr; | |
451 | #endif | |
452 | ||
453 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 | |
454 | if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { | |
455 | pr_info("Skipping L2 locking due to reduced L2 cache size\n"); | |
456 | } else { | |
457 | uint32_t ebase = read_c0_ebase() & 0x3ffff000; | |
458 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB | |
459 | /* TLB refill */ | |
460 | cvmx_l2c_lock_mem_region(ebase, 0x100); | |
461 | #endif | |
462 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION | |
463 | /* General exception */ | |
464 | cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80); | |
465 | #endif | |
466 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT | |
467 | /* Interrupt handler */ | |
468 | cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80); | |
469 | #endif | |
470 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT | |
471 | cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100); | |
472 | cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80); | |
473 | #endif | |
474 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY | |
475 | cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480); | |
476 | #endif | |
477 | } | |
478 | #endif | |
479 | ||
480 | sysinfo = cvmx_sysinfo_get(); | |
481 | memset(sysinfo, 0, sizeof(*sysinfo)); | |
482 | sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20; | |
483 | sysinfo->phy_mem_desc_ptr = | |
484 | cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr); | |
485 | sysinfo->core_mask = octeon_bootinfo->core_mask; | |
486 | sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr; | |
487 | sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz; | |
488 | sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2; | |
489 | sysinfo->board_type = octeon_bootinfo->board_type; | |
490 | sysinfo->board_rev_major = octeon_bootinfo->board_rev_major; | |
491 | sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor; | |
492 | memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base, | |
493 | sizeof(sysinfo->mac_addr_base)); | |
494 | sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count; | |
495 | memcpy(sysinfo->board_serial_number, | |
496 | octeon_bootinfo->board_serial_number, | |
497 | sizeof(sysinfo->board_serial_number)); | |
498 | sysinfo->compact_flash_common_base_addr = | |
499 | octeon_bootinfo->compact_flash_common_base_addr; | |
500 | sysinfo->compact_flash_attribute_base_addr = | |
501 | octeon_bootinfo->compact_flash_attribute_base_addr; | |
502 | sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr; | |
503 | sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz; | |
504 | sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags; | |
505 | ||
506 | ||
507 | octeon_check_cpu_bist(); | |
508 | ||
509 | octeon_uart = octeon_get_boot_uart(); | |
510 | ||
511 | /* | |
512 | * Disable All CIU Interrupts. The ones we need will be | |
513 | * enabled later. Read the SUM register so we know the write | |
514 | * completed. | |
515 | */ | |
516 | cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0); | |
517 | cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); | |
518 | cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); | |
519 | cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); | |
520 | cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2))); | |
521 | ||
522 | #ifdef CONFIG_SMP | |
523 | octeon_write_lcd("LinuxSMP"); | |
524 | #else | |
525 | octeon_write_lcd("Linux"); | |
526 | #endif | |
527 | ||
528 | #ifdef CONFIG_CAVIUM_GDB | |
529 | /* | |
530 | * When debugging the linux kernel, force the cores to enter | |
531 | * the debug exception handler to break in. | |
532 | */ | |
533 | if (octeon_get_boot_debug_flag()) { | |
534 | cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num()); | |
535 | cvmx_read_csr(CVMX_CIU_DINT); | |
536 | } | |
537 | #endif | |
538 | ||
539 | /* | |
540 | * BIST should always be enabled when doing a soft reset. L2 | |
541 | * Cache locking for instance is not cleared unless BIST is | |
542 | * enabled. Unfortunately due to a chip errata G-200 for | |
543 | * Cn38XX and CN31XX, BIST msut be disabled on these parts. | |
544 | */ | |
545 | if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || | |
546 | OCTEON_IS_MODEL(OCTEON_CN31XX)) | |
547 | cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); | |
548 | else | |
549 | cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1); | |
550 | ||
551 | /* Default to 64MB in the simulator to speed things up */ | |
552 | if (octeon_is_simulation()) | |
553 | MAX_MEMORY = 64ull << 20; | |
554 | ||
555 | arcs_cmdline[0] = 0; | |
556 | argc = octeon_boot_desc_ptr->argc; | |
557 | for (i = 0; i < argc; i++) { | |
558 | const char *arg = | |
559 | cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); | |
560 | if ((strncmp(arg, "MEM=", 4) == 0) || | |
561 | (strncmp(arg, "mem=", 4) == 0)) { | |
562 | sscanf(arg + 4, "%llu", &MAX_MEMORY); | |
563 | MAX_MEMORY <<= 20; | |
564 | if (MAX_MEMORY == 0) | |
565 | MAX_MEMORY = 32ull << 30; | |
566 | } else if (strcmp(arg, "ecc_verbose") == 0) { | |
567 | #ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC | |
568 | __cvmx_interrupt_ecc_report_single_bit_errors = 1; | |
569 | pr_notice("Reporting of single bit ECC errors is " | |
570 | "turned on\n"); | |
571 | #endif | |
572 | } else if (strlen(arcs_cmdline) + strlen(arg) + 1 < | |
573 | sizeof(arcs_cmdline) - 1) { | |
574 | strcat(arcs_cmdline, " "); | |
575 | strcat(arcs_cmdline, arg); | |
576 | } | |
577 | } | |
578 | ||
579 | if (strstr(arcs_cmdline, "console=") == NULL) { | |
5b3b1688 DD |
580 | #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL |
581 | strcat(arcs_cmdline, " console=ttyS0,115200"); | |
582 | #else | |
583 | if (octeon_uart == 1) | |
584 | strcat(arcs_cmdline, " console=ttyS1,115200"); | |
585 | else | |
586 | strcat(arcs_cmdline, " console=ttyS0,115200"); | |
5b3b1688 DD |
587 | #endif |
588 | } | |
589 | ||
590 | if (octeon_is_simulation()) { | |
591 | /* | |
592 | * The simulator uses a mtdram device pre filled with | |
593 | * the filesystem. Also specify the calibration delay | |
594 | * to avoid calculating it every time. | |
595 | */ | |
ca148125 | 596 | strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824"); |
5b3b1688 DD |
597 | } |
598 | ||
599 | mips_hpt_frequency = octeon_get_clock_rate(); | |
600 | ||
601 | octeon_init_cvmcount(); | |
ca148125 | 602 | octeon_setup_delays(); |
5b3b1688 DD |
603 | |
604 | _machine_restart = octeon_restart; | |
605 | _machine_halt = octeon_halt; | |
606 | ||
5b3b1688 DD |
607 | octeon_user_io_init(); |
608 | register_smp_ops(&octeon_smp_ops); | |
609 | } | |
610 | ||
2b5987ab DD |
611 | /* Exclude a single page from the regions obtained in plat_mem_setup. */ |
612 | static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size) | |
613 | { | |
614 | if (addr > *mem && addr < *mem + *size) { | |
615 | u64 inc = addr - *mem; | |
616 | add_memory_region(*mem, inc, BOOT_MEM_RAM); | |
617 | *mem += inc; | |
618 | *size -= inc; | |
619 | } | |
620 | ||
621 | if (addr == *mem && *size > PAGE_SIZE) { | |
622 | *mem += PAGE_SIZE; | |
623 | *size -= PAGE_SIZE; | |
624 | } | |
625 | } | |
626 | ||
5b3b1688 DD |
627 | void __init plat_mem_setup(void) |
628 | { | |
629 | uint64_t mem_alloc_size; | |
630 | uint64_t total; | |
631 | int64_t memory; | |
632 | ||
633 | total = 0; | |
634 | ||
635 | /* First add the init memory we will be returning. */ | |
636 | memory = __pa_symbol(&__init_begin) & PAGE_MASK; | |
637 | mem_alloc_size = (__pa_symbol(&__init_end) & PAGE_MASK) - memory; | |
638 | if (mem_alloc_size > 0) { | |
639 | add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); | |
640 | total += mem_alloc_size; | |
641 | } | |
642 | ||
643 | /* | |
644 | * The Mips memory init uses the first memory location for | |
645 | * some memory vectors. When SPARSEMEM is in use, it doesn't | |
646 | * verify that the size is big enough for the final | |
647 | * vectors. Making the smallest chuck 4MB seems to be enough | |
648 | * to consistantly work. | |
649 | */ | |
650 | mem_alloc_size = 4 << 20; | |
651 | if (mem_alloc_size > MAX_MEMORY) | |
652 | mem_alloc_size = MAX_MEMORY; | |
653 | ||
654 | /* | |
655 | * When allocating memory, we want incrementing addresses from | |
656 | * bootmem_alloc so the code in add_memory_region can merge | |
657 | * regions next to each other. | |
658 | */ | |
659 | cvmx_bootmem_lock(); | |
660 | while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX) | |
661 | && (total < MAX_MEMORY)) { | |
662 | #if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR) | |
663 | memory = cvmx_bootmem_phy_alloc(mem_alloc_size, | |
664 | __pa_symbol(&__init_end), -1, | |
665 | 0x100000, | |
666 | CVMX_BOOTMEM_FLAG_NO_LOCKING); | |
667 | #elif defined(CONFIG_HIGHMEM) | |
668 | memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 1ull << 31, | |
669 | 0x100000, | |
670 | CVMX_BOOTMEM_FLAG_NO_LOCKING); | |
671 | #else | |
672 | memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 512 << 20, | |
673 | 0x100000, | |
674 | CVMX_BOOTMEM_FLAG_NO_LOCKING); | |
675 | #endif | |
676 | if (memory >= 0) { | |
2b5987ab DD |
677 | u64 size = mem_alloc_size; |
678 | ||
679 | /* | |
680 | * exclude a page at the beginning and end of | |
681 | * the 256MB PCIe 'hole' so the kernel will not | |
682 | * try to allocate multi-page buffers that | |
683 | * span the discontinuity. | |
684 | */ | |
685 | memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE, | |
686 | &memory, &size); | |
687 | memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE + | |
688 | CVMX_PCIE_BAR1_PHYS_SIZE, | |
689 | &memory, &size); | |
690 | ||
5b3b1688 DD |
691 | /* |
692 | * This function automatically merges address | |
693 | * regions next to each other if they are | |
694 | * received in incrementing order. | |
695 | */ | |
2b5987ab DD |
696 | if (size) |
697 | add_memory_region(memory, size, BOOT_MEM_RAM); | |
5b3b1688 DD |
698 | total += mem_alloc_size; |
699 | } else { | |
700 | break; | |
701 | } | |
702 | } | |
703 | cvmx_bootmem_unlock(); | |
704 | ||
705 | #ifdef CONFIG_CAVIUM_RESERVE32 | |
706 | /* | |
707 | * Now that we've allocated the kernel memory it is safe to | |
708 | * free the reserved region. We free it here so that builtin | |
709 | * drivers can use the memory. | |
710 | */ | |
711 | if (octeon_reserve32_memory) | |
712 | cvmx_bootmem_free_named("CAVIUM_RESERVE32"); | |
713 | #endif /* CONFIG_CAVIUM_RESERVE32 */ | |
714 | ||
715 | if (total == 0) | |
716 | panic("Unable to allocate memory from " | |
717 | "cvmx_bootmem_phy_alloc\n"); | |
718 | } | |
719 | ||
ea435464 DD |
720 | /* |
721 | * Emit one character to the boot UART. Exported for use by the | |
722 | * watchdog timer. | |
723 | */ | |
5b3b1688 DD |
724 | int prom_putchar(char c) |
725 | { | |
726 | uint64_t lsrval; | |
727 | ||
728 | /* Spin until there is room */ | |
729 | do { | |
730 | lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart)); | |
731 | } while ((lsrval & 0x20) == 0); | |
732 | ||
733 | /* Write the byte */ | |
606c958e | 734 | cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull); |
5b3b1688 DD |
735 | return 1; |
736 | } | |
ea435464 | 737 | EXPORT_SYMBOL(prom_putchar); |
5b3b1688 DD |
738 | |
739 | void prom_free_prom_memory(void) | |
740 | { | |
741 | #ifdef CONFIG_CAVIUM_DECODE_RSL | |
742 | cvmx_interrupt_rsl_enable(); | |
743 | ||
744 | /* Add an interrupt handler for general failures. */ | |
745 | if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED, | |
746 | "RML/RSL", octeon_rlm_interrupt)) { | |
747 | panic("Unable to request_irq(OCTEON_IRQ_RML)\n"); | |
748 | } | |
749 | #endif | |
5b3b1688 | 750 | } |