Commit | Line | Data |
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6b5de091 S |
1 | /* |
2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * Based on "omap4.dtsi" | |
8 | */ | |
9 | ||
10 | /* | |
11 | * Carveout for multimedia usecases | |
12 | * It should be the last 48MB of the first 512MB memory part | |
13 | * In theory, it should not even exist. That zone should be reserved | |
14 | * dynamically during the .reserve callback. | |
15 | */ | |
16 | /memreserve/ 0x9d000000 0x03000000; | |
17 | ||
18 | /include/ "skeleton.dtsi" | |
19 | ||
20 | / { | |
21 | compatible = "ti,omap5"; | |
22 | interrupt-parent = <&gic>; | |
23 | ||
24 | aliases { | |
25 | serial0 = &uart1; | |
26 | serial1 = &uart2; | |
27 | serial2 = &uart3; | |
28 | serial3 = &uart4; | |
29 | serial4 = &uart5; | |
30 | serial5 = &uart6; | |
31 | }; | |
32 | ||
33 | cpus { | |
34 | cpu@0 { | |
35 | compatible = "arm,cortex-a15"; | |
36 | }; | |
37 | cpu@1 { | |
38 | compatible = "arm,cortex-a15"; | |
39 | }; | |
40 | }; | |
41 | ||
b45ccc4e SS |
42 | timer { |
43 | compatible = "arm,armv7-timer"; | |
44 | /* 14th PPI IRQ, active low level-sensitive */ | |
45 | interrupts = <1 14 0x308>; | |
46 | clock-frequency = <6144000>; | |
47 | }; | |
48 | ||
6b5de091 S |
49 | /* |
50 | * The soc node represents the soc top level view. It is uses for IPs | |
51 | * that are not memory mapped in the MPU view or for the MPU itself. | |
52 | */ | |
53 | soc { | |
54 | compatible = "ti,omap-infra"; | |
55 | mpu { | |
56 | compatible = "ti,omap5-mpu"; | |
57 | ti,hwmods = "mpu"; | |
58 | }; | |
59 | }; | |
60 | ||
61 | /* | |
62 | * XXX: Use a flat representation of the OMAP3 interconnect. | |
63 | * The real OMAP interconnect network is quite complex. | |
64 | * Since that will not bring real advantage to represent that in DT for | |
65 | * the moment, just use a fake OCP bus entry to represent the whole bus | |
66 | * hierarchy. | |
67 | */ | |
68 | ocp { | |
69 | compatible = "ti,omap4-l3-noc", "simple-bus"; | |
70 | #address-cells = <1>; | |
71 | #size-cells = <1>; | |
72 | ranges; | |
73 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; | |
74 | ||
3b3132f7 JH |
75 | counter32k: counter@4ae04000 { |
76 | compatible = "ti,omap-counter32k"; | |
77 | reg = <0x4ae04000 0x40>; | |
78 | ti,hwmods = "counter_32k"; | |
79 | }; | |
80 | ||
5da6a2d5 PU |
81 | omap5_pmx_core: pinmux@4a002840 { |
82 | compatible = "ti,omap4-padconf", "pinctrl-single"; | |
83 | reg = <0x4a002840 0x01b6>; | |
84 | #address-cells = <1>; | |
85 | #size-cells = <0>; | |
86 | pinctrl-single,register-width = <16>; | |
87 | pinctrl-single,function-mask = <0x7fff>; | |
88 | }; | |
89 | omap5_pmx_wkup: pinmux@4ae0c840 { | |
90 | compatible = "ti,omap4-padconf", "pinctrl-single"; | |
91 | reg = <0x4ae0c840 0x0038>; | |
92 | #address-cells = <1>; | |
93 | #size-cells = <0>; | |
94 | pinctrl-single,register-width = <16>; | |
95 | pinctrl-single,function-mask = <0x7fff>; | |
96 | }; | |
97 | ||
6b5de091 S |
98 | gic: interrupt-controller@48211000 { |
99 | compatible = "arm,cortex-a15-gic"; | |
100 | interrupt-controller; | |
101 | #interrupt-cells = <3>; | |
102 | reg = <0x48211000 0x1000>, | |
103 | <0x48212000 0x1000>; | |
104 | }; | |
105 | ||
2c2dc545 JH |
106 | sdma: dma-controller@4a056000 { |
107 | compatible = "ti,omap4430-sdma"; | |
108 | reg = <0x4a056000 0x1000>; | |
109 | interrupts = <0 12 0x4>, | |
110 | <0 13 0x4>, | |
111 | <0 14 0x4>, | |
112 | <0 15 0x4>; | |
113 | #dma-cells = <1>; | |
114 | #dma-channels = <32>; | |
115 | #dma-requests = <127>; | |
116 | }; | |
117 | ||
6b5de091 S |
118 | gpio1: gpio@4ae10000 { |
119 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
120 | reg = <0x4ae10000 0x200>; |
121 | interrupts = <0 29 0x4>; | |
6b5de091 S |
122 | ti,hwmods = "gpio1"; |
123 | gpio-controller; | |
124 | #gpio-cells = <2>; | |
125 | interrupt-controller; | |
ff5c9059 | 126 | #interrupt-cells = <2>; |
6b5de091 S |
127 | }; |
128 | ||
129 | gpio2: gpio@48055000 { | |
130 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
131 | reg = <0x48055000 0x200>; |
132 | interrupts = <0 30 0x4>; | |
6b5de091 S |
133 | ti,hwmods = "gpio2"; |
134 | gpio-controller; | |
135 | #gpio-cells = <2>; | |
136 | interrupt-controller; | |
ff5c9059 | 137 | #interrupt-cells = <2>; |
6b5de091 S |
138 | }; |
139 | ||
140 | gpio3: gpio@48057000 { | |
141 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
142 | reg = <0x48057000 0x200>; |
143 | interrupts = <0 31 0x4>; | |
6b5de091 S |
144 | ti,hwmods = "gpio3"; |
145 | gpio-controller; | |
146 | #gpio-cells = <2>; | |
147 | interrupt-controller; | |
ff5c9059 | 148 | #interrupt-cells = <2>; |
6b5de091 S |
149 | }; |
150 | ||
151 | gpio4: gpio@48059000 { | |
152 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
153 | reg = <0x48059000 0x200>; |
154 | interrupts = <0 32 0x4>; | |
6b5de091 S |
155 | ti,hwmods = "gpio4"; |
156 | gpio-controller; | |
157 | #gpio-cells = <2>; | |
158 | interrupt-controller; | |
ff5c9059 | 159 | #interrupt-cells = <2>; |
6b5de091 S |
160 | }; |
161 | ||
162 | gpio5: gpio@4805b000 { | |
163 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
164 | reg = <0x4805b000 0x200>; |
165 | interrupts = <0 33 0x4>; | |
6b5de091 S |
166 | ti,hwmods = "gpio5"; |
167 | gpio-controller; | |
168 | #gpio-cells = <2>; | |
169 | interrupt-controller; | |
ff5c9059 | 170 | #interrupt-cells = <2>; |
6b5de091 S |
171 | }; |
172 | ||
173 | gpio6: gpio@4805d000 { | |
174 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
175 | reg = <0x4805d000 0x200>; |
176 | interrupts = <0 34 0x4>; | |
6b5de091 S |
177 | ti,hwmods = "gpio6"; |
178 | gpio-controller; | |
179 | #gpio-cells = <2>; | |
180 | interrupt-controller; | |
ff5c9059 | 181 | #interrupt-cells = <2>; |
6b5de091 S |
182 | }; |
183 | ||
184 | gpio7: gpio@48051000 { | |
185 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
186 | reg = <0x48051000 0x200>; |
187 | interrupts = <0 35 0x4>; | |
6b5de091 S |
188 | ti,hwmods = "gpio7"; |
189 | gpio-controller; | |
190 | #gpio-cells = <2>; | |
191 | interrupt-controller; | |
ff5c9059 | 192 | #interrupt-cells = <2>; |
6b5de091 S |
193 | }; |
194 | ||
195 | gpio8: gpio@48053000 { | |
196 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
197 | reg = <0x48053000 0x200>; |
198 | interrupts = <0 121 0x4>; | |
6b5de091 S |
199 | ti,hwmods = "gpio8"; |
200 | gpio-controller; | |
201 | #gpio-cells = <2>; | |
202 | interrupt-controller; | |
ff5c9059 | 203 | #interrupt-cells = <2>; |
6b5de091 S |
204 | }; |
205 | ||
1c7dbb55 JH |
206 | gpmc: gpmc@50000000 { |
207 | compatible = "ti,omap4430-gpmc"; | |
208 | reg = <0x50000000 0x1000>; | |
209 | #address-cells = <2>; | |
210 | #size-cells = <1>; | |
211 | interrupts = <0 20 0x4>; | |
212 | gpmc,num-cs = <8>; | |
213 | gpmc,num-waitpins = <4>; | |
214 | ti,hwmods = "gpmc"; | |
215 | }; | |
216 | ||
6e6a9a50 SP |
217 | i2c1: i2c@48070000 { |
218 | compatible = "ti,omap4-i2c"; | |
d7118bbd SG |
219 | reg = <0x48070000 0x100>; |
220 | interrupts = <0 56 0x4>; | |
6e6a9a50 SP |
221 | #address-cells = <1>; |
222 | #size-cells = <0>; | |
223 | ti,hwmods = "i2c1"; | |
224 | }; | |
225 | ||
226 | i2c2: i2c@48072000 { | |
227 | compatible = "ti,omap4-i2c"; | |
d7118bbd SG |
228 | reg = <0x48072000 0x100>; |
229 | interrupts = <0 57 0x4>; | |
6e6a9a50 SP |
230 | #address-cells = <1>; |
231 | #size-cells = <0>; | |
232 | ti,hwmods = "i2c2"; | |
233 | }; | |
234 | ||
235 | i2c3: i2c@48060000 { | |
236 | compatible = "ti,omap4-i2c"; | |
d7118bbd SG |
237 | reg = <0x48060000 0x100>; |
238 | interrupts = <0 61 0x4>; | |
6e6a9a50 SP |
239 | #address-cells = <1>; |
240 | #size-cells = <0>; | |
241 | ti,hwmods = "i2c3"; | |
242 | }; | |
243 | ||
d7118bbd | 244 | i2c4: i2c@4807a000 { |
6e6a9a50 | 245 | compatible = "ti,omap4-i2c"; |
d7118bbd SG |
246 | reg = <0x4807a000 0x100>; |
247 | interrupts = <0 62 0x4>; | |
6e6a9a50 SP |
248 | #address-cells = <1>; |
249 | #size-cells = <0>; | |
250 | ti,hwmods = "i2c4"; | |
251 | }; | |
252 | ||
d7118bbd | 253 | i2c5: i2c@4807c000 { |
6e6a9a50 | 254 | compatible = "ti,omap4-i2c"; |
d7118bbd SG |
255 | reg = <0x4807c000 0x100>; |
256 | interrupts = <0 60 0x4>; | |
6e6a9a50 SP |
257 | #address-cells = <1>; |
258 | #size-cells = <0>; | |
259 | ti,hwmods = "i2c5"; | |
260 | }; | |
261 | ||
43286b11 FB |
262 | mcspi1: spi@48098000 { |
263 | compatible = "ti,omap4-mcspi"; | |
264 | reg = <0x48098000 0x200>; | |
265 | interrupts = <0 65 0x4>; | |
266 | #address-cells = <1>; | |
267 | #size-cells = <0>; | |
268 | ti,hwmods = "mcspi1"; | |
269 | ti,spi-num-cs = <4>; | |
2c2dc545 JH |
270 | dmas = <&sdma 35>, |
271 | <&sdma 36>, | |
272 | <&sdma 37>, | |
273 | <&sdma 38>, | |
274 | <&sdma 39>, | |
275 | <&sdma 40>, | |
276 | <&sdma 41>, | |
277 | <&sdma 42>; | |
278 | dma-names = "tx0", "rx0", "tx1", "rx1", | |
279 | "tx2", "rx2", "tx3", "rx3"; | |
43286b11 FB |
280 | }; |
281 | ||
282 | mcspi2: spi@4809a000 { | |
283 | compatible = "ti,omap4-mcspi"; | |
284 | reg = <0x4809a000 0x200>; | |
285 | interrupts = <0 66 0x4>; | |
286 | #address-cells = <1>; | |
287 | #size-cells = <0>; | |
288 | ti,hwmods = "mcspi2"; | |
289 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
290 | dmas = <&sdma 43>, |
291 | <&sdma 44>, | |
292 | <&sdma 45>, | |
293 | <&sdma 46>; | |
294 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
43286b11 FB |
295 | }; |
296 | ||
297 | mcspi3: spi@480b8000 { | |
298 | compatible = "ti,omap4-mcspi"; | |
299 | reg = <0x480b8000 0x200>; | |
300 | interrupts = <0 91 0x4>; | |
301 | #address-cells = <1>; | |
302 | #size-cells = <0>; | |
303 | ti,hwmods = "mcspi3"; | |
304 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
305 | dmas = <&sdma 15>, <&sdma 16>; |
306 | dma-names = "tx0", "rx0"; | |
43286b11 FB |
307 | }; |
308 | ||
309 | mcspi4: spi@480ba000 { | |
310 | compatible = "ti,omap4-mcspi"; | |
311 | reg = <0x480ba000 0x200>; | |
312 | interrupts = <0 48 0x4>; | |
313 | #address-cells = <1>; | |
314 | #size-cells = <0>; | |
315 | ti,hwmods = "mcspi4"; | |
316 | ti,spi-num-cs = <1>; | |
2c2dc545 JH |
317 | dmas = <&sdma 70>, <&sdma 71>; |
318 | dma-names = "tx0", "rx0"; | |
43286b11 FB |
319 | }; |
320 | ||
6b5de091 S |
321 | uart1: serial@4806a000 { |
322 | compatible = "ti,omap4-uart"; | |
8e80f660 SG |
323 | reg = <0x4806a000 0x100>; |
324 | interrupts = <0 72 0x4>; | |
6b5de091 S |
325 | ti,hwmods = "uart1"; |
326 | clock-frequency = <48000000>; | |
327 | }; | |
328 | ||
329 | uart2: serial@4806c000 { | |
330 | compatible = "ti,omap4-uart"; | |
8e80f660 SG |
331 | reg = <0x4806c000 0x100>; |
332 | interrupts = <0 73 0x4>; | |
6b5de091 S |
333 | ti,hwmods = "uart2"; |
334 | clock-frequency = <48000000>; | |
335 | }; | |
336 | ||
337 | uart3: serial@48020000 { | |
338 | compatible = "ti,omap4-uart"; | |
8e80f660 SG |
339 | reg = <0x48020000 0x100>; |
340 | interrupts = <0 74 0x4>; | |
6b5de091 S |
341 | ti,hwmods = "uart3"; |
342 | clock-frequency = <48000000>; | |
343 | }; | |
344 | ||
345 | uart4: serial@4806e000 { | |
346 | compatible = "ti,omap4-uart"; | |
8e80f660 SG |
347 | reg = <0x4806e000 0x100>; |
348 | interrupts = <0 70 0x4>; | |
6b5de091 S |
349 | ti,hwmods = "uart4"; |
350 | clock-frequency = <48000000>; | |
351 | }; | |
352 | ||
353 | uart5: serial@48066000 { | |
8e80f660 SG |
354 | compatible = "ti,omap4-uart"; |
355 | reg = <0x48066000 0x100>; | |
356 | interrupts = <0 105 0x4>; | |
6b5de091 S |
357 | ti,hwmods = "uart5"; |
358 | clock-frequency = <48000000>; | |
359 | }; | |
360 | ||
361 | uart6: serial@48068000 { | |
8e80f660 SG |
362 | compatible = "ti,omap4-uart"; |
363 | reg = <0x48068000 0x100>; | |
364 | interrupts = <0 106 0x4>; | |
6b5de091 S |
365 | ti,hwmods = "uart6"; |
366 | clock-frequency = <48000000>; | |
367 | }; | |
5dd18b01 B |
368 | |
369 | mmc1: mmc@4809c000 { | |
370 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
371 | reg = <0x4809c000 0x400>; |
372 | interrupts = <0 83 0x4>; | |
5dd18b01 B |
373 | ti,hwmods = "mmc1"; |
374 | ti,dual-volt; | |
375 | ti,needs-special-reset; | |
2c2dc545 JH |
376 | dmas = <&sdma 61>, <&sdma 62>; |
377 | dma-names = "tx", "rx"; | |
5dd18b01 B |
378 | }; |
379 | ||
380 | mmc2: mmc@480b4000 { | |
381 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
382 | reg = <0x480b4000 0x400>; |
383 | interrupts = <0 86 0x4>; | |
5dd18b01 B |
384 | ti,hwmods = "mmc2"; |
385 | ti,needs-special-reset; | |
2c2dc545 JH |
386 | dmas = <&sdma 47>, <&sdma 48>; |
387 | dma-names = "tx", "rx"; | |
5dd18b01 B |
388 | }; |
389 | ||
390 | mmc3: mmc@480ad000 { | |
391 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
392 | reg = <0x480ad000 0x400>; |
393 | interrupts = <0 94 0x4>; | |
5dd18b01 B |
394 | ti,hwmods = "mmc3"; |
395 | ti,needs-special-reset; | |
2c2dc545 JH |
396 | dmas = <&sdma 77>, <&sdma 78>; |
397 | dma-names = "tx", "rx"; | |
5dd18b01 B |
398 | }; |
399 | ||
400 | mmc4: mmc@480d1000 { | |
401 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
402 | reg = <0x480d1000 0x400>; |
403 | interrupts = <0 96 0x4>; | |
5dd18b01 B |
404 | ti,hwmods = "mmc4"; |
405 | ti,needs-special-reset; | |
2c2dc545 JH |
406 | dmas = <&sdma 57>, <&sdma 58>; |
407 | dma-names = "tx", "rx"; | |
5dd18b01 B |
408 | }; |
409 | ||
410 | mmc5: mmc@480d5000 { | |
411 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
412 | reg = <0x480d5000 0x400>; |
413 | interrupts = <0 59 0x4>; | |
5dd18b01 B |
414 | ti,hwmods = "mmc5"; |
415 | ti,needs-special-reset; | |
2c2dc545 JH |
416 | dmas = <&sdma 59>, <&sdma 60>; |
417 | dma-names = "tx", "rx"; | |
5dd18b01 | 418 | }; |
5449fbc2 SP |
419 | |
420 | keypad: keypad@4ae1c000 { | |
421 | compatible = "ti,omap4-keypad"; | |
422 | ti,hwmods = "kbd"; | |
423 | }; | |
ffd5db24 | 424 | |
cbb57f07 PU |
425 | mcpdm: mcpdm@40132000 { |
426 | compatible = "ti,omap4-mcpdm"; | |
427 | reg = <0x40132000 0x7f>, /* MPU private access */ | |
428 | <0x49032000 0x7f>; /* L3 Interconnect */ | |
429 | reg-names = "mpu", "dma"; | |
430 | interrupts = <0 112 0x4>; | |
cbb57f07 | 431 | ti,hwmods = "mcpdm"; |
4e4ead73 SG |
432 | dmas = <&sdma 65>, |
433 | <&sdma 66>; | |
434 | dma-names = "up_link", "dn_link"; | |
cbb57f07 PU |
435 | }; |
436 | ||
437 | dmic: dmic@4012e000 { | |
438 | compatible = "ti,omap4-dmic"; | |
439 | reg = <0x4012e000 0x7f>, /* MPU private access */ | |
440 | <0x4902e000 0x7f>; /* L3 Interconnect */ | |
441 | reg-names = "mpu", "dma"; | |
442 | interrupts = <0 114 0x4>; | |
cbb57f07 | 443 | ti,hwmods = "dmic"; |
4e4ead73 SG |
444 | dmas = <&sdma 67>; |
445 | dma-names = "up_link"; | |
cbb57f07 PU |
446 | }; |
447 | ||
ffd5db24 PU |
448 | mcbsp1: mcbsp@40122000 { |
449 | compatible = "ti,omap4-mcbsp"; | |
450 | reg = <0x40122000 0xff>, /* MPU private access */ | |
451 | <0x49022000 0xff>; /* L3 Interconnect */ | |
452 | reg-names = "mpu", "dma"; | |
453 | interrupts = <0 17 0x4>; | |
454 | interrupt-names = "common"; | |
ffd5db24 PU |
455 | ti,buffer-size = <128>; |
456 | ti,hwmods = "mcbsp1"; | |
4e4ead73 SG |
457 | dmas = <&sdma 33>, |
458 | <&sdma 34>; | |
459 | dma-names = "tx", "rx"; | |
ffd5db24 PU |
460 | }; |
461 | ||
462 | mcbsp2: mcbsp@40124000 { | |
463 | compatible = "ti,omap4-mcbsp"; | |
464 | reg = <0x40124000 0xff>, /* MPU private access */ | |
465 | <0x49024000 0xff>; /* L3 Interconnect */ | |
466 | reg-names = "mpu", "dma"; | |
467 | interrupts = <0 22 0x4>; | |
468 | interrupt-names = "common"; | |
ffd5db24 PU |
469 | ti,buffer-size = <128>; |
470 | ti,hwmods = "mcbsp2"; | |
4e4ead73 SG |
471 | dmas = <&sdma 17>, |
472 | <&sdma 18>; | |
473 | dma-names = "tx", "rx"; | |
ffd5db24 PU |
474 | }; |
475 | ||
476 | mcbsp3: mcbsp@40126000 { | |
477 | compatible = "ti,omap4-mcbsp"; | |
478 | reg = <0x40126000 0xff>, /* MPU private access */ | |
479 | <0x49026000 0xff>; /* L3 Interconnect */ | |
480 | reg-names = "mpu", "dma"; | |
481 | interrupts = <0 23 0x4>; | |
482 | interrupt-names = "common"; | |
ffd5db24 PU |
483 | ti,buffer-size = <128>; |
484 | ti,hwmods = "mcbsp3"; | |
4e4ead73 SG |
485 | dmas = <&sdma 19>, |
486 | <&sdma 20>; | |
487 | dma-names = "tx", "rx"; | |
ffd5db24 | 488 | }; |
df692a92 JH |
489 | |
490 | timer1: timer@4ae18000 { | |
491 | compatible = "ti,omap2-timer"; | |
492 | reg = <0x4ae18000 0x80>; | |
493 | interrupts = <0 37 0x4>; | |
494 | ti,hwmods = "timer1"; | |
495 | ti,timer-alwon; | |
496 | }; | |
497 | ||
498 | timer2: timer@48032000 { | |
499 | compatible = "ti,omap2-timer"; | |
500 | reg = <0x48032000 0x80>; | |
501 | interrupts = <0 38 0x4>; | |
502 | ti,hwmods = "timer2"; | |
503 | }; | |
504 | ||
505 | timer3: timer@48034000 { | |
506 | compatible = "ti,omap2-timer"; | |
507 | reg = <0x48034000 0x80>; | |
508 | interrupts = <0 39 0x4>; | |
509 | ti,hwmods = "timer3"; | |
510 | }; | |
511 | ||
512 | timer4: timer@48036000 { | |
513 | compatible = "ti,omap2-timer"; | |
514 | reg = <0x48036000 0x80>; | |
515 | interrupts = <0 40 0x4>; | |
516 | ti,hwmods = "timer4"; | |
517 | }; | |
518 | ||
519 | timer5: timer@40138000 { | |
520 | compatible = "ti,omap2-timer"; | |
521 | reg = <0x40138000 0x80>, | |
522 | <0x49038000 0x80>; | |
523 | interrupts = <0 41 0x4>; | |
524 | ti,hwmods = "timer5"; | |
525 | ti,timer-dsp; | |
526 | }; | |
527 | ||
528 | timer6: timer@4013a000 { | |
529 | compatible = "ti,omap2-timer"; | |
530 | reg = <0x4013a000 0x80>, | |
531 | <0x4903a000 0x80>; | |
532 | interrupts = <0 42 0x4>; | |
533 | ti,hwmods = "timer6"; | |
534 | ti,timer-dsp; | |
535 | ti,timer-pwm; | |
536 | }; | |
537 | ||
538 | timer7: timer@4013c000 { | |
539 | compatible = "ti,omap2-timer"; | |
540 | reg = <0x4013c000 0x80>, | |
541 | <0x4903c000 0x80>; | |
542 | interrupts = <0 43 0x4>; | |
543 | ti,hwmods = "timer7"; | |
544 | ti,timer-dsp; | |
545 | }; | |
546 | ||
547 | timer8: timer@4013e000 { | |
548 | compatible = "ti,omap2-timer"; | |
549 | reg = <0x4013e000 0x80>, | |
550 | <0x4903e000 0x80>; | |
551 | interrupts = <0 44 0x4>; | |
552 | ti,hwmods = "timer8"; | |
553 | ti,timer-dsp; | |
554 | ti,timer-pwm; | |
555 | }; | |
556 | ||
557 | timer9: timer@4803e000 { | |
558 | compatible = "ti,omap2-timer"; | |
559 | reg = <0x4803e000 0x80>; | |
560 | interrupts = <0 45 0x4>; | |
561 | ti,hwmods = "timer9"; | |
562 | }; | |
563 | ||
564 | timer10: timer@48086000 { | |
565 | compatible = "ti,omap2-timer"; | |
566 | reg = <0x48086000 0x80>; | |
567 | interrupts = <0 46 0x4>; | |
568 | ti,hwmods = "timer10"; | |
569 | }; | |
570 | ||
571 | timer11: timer@48088000 { | |
572 | compatible = "ti,omap2-timer"; | |
573 | reg = <0x48088000 0x80>; | |
574 | interrupts = <0 47 0x4>; | |
575 | ti,hwmods = "timer11"; | |
576 | ti,timer-pwm; | |
577 | }; | |
e6900ddf LV |
578 | |
579 | emif1: emif@0x4c000000 { | |
580 | compatible = "ti,emif-4d5"; | |
581 | ti,hwmods = "emif1"; | |
582 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ | |
583 | reg = <0x4c000000 0x400>; | |
584 | interrupts = <0 110 0x4>; | |
585 | hw-caps-read-idle-ctrl; | |
586 | hw-caps-ll-interface; | |
587 | hw-caps-temp-alert; | |
588 | }; | |
589 | ||
590 | emif2: emif@0x4d000000 { | |
591 | compatible = "ti,emif-4d5"; | |
592 | ti,hwmods = "emif2"; | |
593 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ | |
594 | reg = <0x4d000000 0x400>; | |
595 | interrupts = <0 111 0x4>; | |
596 | hw-caps-read-idle-ctrl; | |
597 | hw-caps-ll-interface; | |
598 | hw-caps-temp-alert; | |
599 | }; | |
fedc428e KVA |
600 | |
601 | omap_control_usb: omap-control-usb@4a002300 { | |
602 | compatible = "ti,omap-control-usb"; | |
603 | reg = <0x4a002300 0x4>, | |
604 | <0x4a002370 0x4>; | |
605 | reg-names = "control_dev_conf", "phy_power_usb"; | |
606 | ti,type = <2>; | |
607 | }; | |
e9831967 | 608 | |
72f6f957 KVA |
609 | omap_dwc3@4a020000 { |
610 | compatible = "ti,dwc3"; | |
611 | ti,hwmods = "usb_otg_ss"; | |
612 | reg = <0x4a020000 0x1000>; | |
613 | interrupts = <0 93 4>; | |
614 | #address-cells = <1>; | |
615 | #size-cells = <1>; | |
616 | utmi-mode = <2>; | |
617 | ranges; | |
618 | dwc3@4a030000 { | |
619 | compatible = "synopsys,dwc3"; | |
620 | reg = <0x4a030000 0x1000>; | |
621 | interrupts = <0 92 4>; | |
622 | usb-phy = <&usb2_phy>, <&usb3_phy>; | |
623 | tx-fifo-resize; | |
624 | }; | |
625 | }; | |
626 | ||
e9831967 KVA |
627 | ocp2scp { |
628 | compatible = "ti,omap-ocp2scp"; | |
629 | #address-cells = <1>; | |
630 | #size-cells = <1>; | |
631 | ranges; | |
632 | ti,hwmods = "ocp2scp1"; | |
ae6a32d2 KVA |
633 | usb2_phy: usb2phy@4a084000 { |
634 | compatible = "ti,omap-usb2"; | |
635 | reg = <0x4a084000 0x7c>; | |
636 | ctrl-module = <&omap_control_usb>; | |
637 | }; | |
638 | ||
639 | usb3_phy: usb3phy@4a084400 { | |
640 | compatible = "ti,omap-usb3"; | |
641 | reg = <0x4a084400 0x80>, | |
642 | <0x4a084800 0x64>, | |
643 | <0x4a084c00 0x40>; | |
644 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
645 | ctrl-module = <&omap_control_usb>; | |
646 | }; | |
e9831967 | 647 | }; |
6b5de091 S |
648 | }; |
649 | }; |