[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / boot / dts / omap5.dtsi

/*
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 * Based on "omap4.dtsi"
 */

/*
 * Carveout for multimedia usecases
 * It should be the last 48MB of the first 512MB memory part
 * In theory, it should not even exist. That zone should be reserved
 * dynamically during the .reserve callback.
 */
/memreserve/ 0x9d000000 0x03000000;

/include/ "skeleton.dtsi"

/ {
	compatible = "ti,omap5";
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
	};

	cpus {
		cpu@0 {
			compatible = "arm,cortex-a15";
		};
		cpu@1 {
			compatible = "arm,cortex-a15";
		};
	};

	/*
	 * The soc node represents the soc top level view. It is uses for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap5-mpu";
			ti,hwmods = "mpu";
		};
	};

	/*
	 * XXX: Use a flat representation of the OMAP3 interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since that will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "ti,omap4-l3-noc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";

		gic: interrupt-controller@48211000 {
			compatible = "arm,cortex-a15-gic";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x48211000 0x1000>,
			      <0x48212000 0x1000>;
		};

		gpio1: gpio@4ae10000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio1";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio2: gpio@48055000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio3: gpio@48057000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio4: gpio@48059000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio5: gpio@4805b000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio6: gpio@4805d000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio7: gpio@48051000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio7";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio8: gpio@48053000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio8";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		i2c1: i2c@48070000 {
			compatible = "ti,omap4-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c1";
		};

		i2c2: i2c@48072000 {
			compatible = "ti,omap4-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c2";
		};

		i2c3: i2c@48060000 {
			compatible = "ti,omap4-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c3";
		};

		i2c4: i2c@4807A000 {
			compatible = "ti,omap4-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c4";
		};

		i2c5: i2c@4807C000 {
			compatible = "ti,omap4-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c5";
		};

		uart1: serial@4806a000 {
			compatible = "ti,omap4-uart";
			ti,hwmods = "uart1";
			clock-frequency = <48000000>;
		};

		uart2: serial@4806c000 {
			compatible = "ti,omap4-uart";
			ti,hwmods = "uart2";
			clock-frequency = <48000000>;
		};

		uart3: serial@48020000 {
			compatible = "ti,omap4-uart";
			ti,hwmods = "uart3";
			clock-frequency = <48000000>;
		};

		uart4: serial@4806e000 {
			compatible = "ti,omap4-uart";
			ti,hwmods = "uart4";
			clock-frequency = <48000000>;
		};

		uart5: serial@48066000 {
			compatible = "ti,omap5-uart";
			ti,hwmods = "uart5";
			clock-frequency = <48000000>;
		};

		uart6: serial@48068000 {
			compatible = "ti,omap6-uart";
			ti,hwmods = "uart6";
			clock-frequency = <48000000>;
		};

		mmc1: mmc@4809c000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
		};

		mmc2: mmc@480b4000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
		};

		mmc3: mmc@480ad000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
		};

		mmc4: mmc@480d1000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc4";
			ti,needs-special-reset;
		};

		mmc5: mmc@480d5000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc5";
			ti,needs-special-reset;
		};

		keypad: keypad@4ae1c000 {
			compatible = "ti,omap4-keypad";
			ti,hwmods = "kbd";
		};
	};
};
Commit	Line	Data
6b5de091 S	1	/*
	2	* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	* Based on "omap4.dtsi"
	8	*/
	9
	10	/*
	11	* Carveout for multimedia usecases
	12	* It should be the last 48MB of the first 512MB memory part
	13	* In theory, it should not even exist. That zone should be reserved
	14	* dynamically during the .reserve callback.
	15	*/
	16	/memreserve/ 0x9d000000 0x03000000;
	17
	18	/include/ "skeleton.dtsi"
	19
	20	/ {
	21	compatible = "ti,omap5";
	22	interrupt-parent = <&gic>;
	23
	24	aliases {
	25	serial0 = &uart1;
	26	serial1 = &uart2;
	27	serial2 = &uart3;
	28	serial3 = &uart4;
	29	serial4 = &uart5;
	30	serial5 = &uart6;
	31	};
	32
	33	cpus {
	34	cpu@0 {
	35	compatible = "arm,cortex-a15";
	36	};
	37	cpu@1 {
	38	compatible = "arm,cortex-a15";
	39	};
	40	};
	41
	42	/*
	43	* The soc node represents the soc top level view. It is uses for IPs
	44	* that are not memory mapped in the MPU view or for the MPU itself.
	45	*/
	46	soc {
	47	compatible = "ti,omap-infra";
	48	mpu {
	49	compatible = "ti,omap5-mpu";
	50	ti,hwmods = "mpu";
	51	};
	52	};
	53
	54	/*
	55	* XXX: Use a flat representation of the OMAP3 interconnect.
	56	* The real OMAP interconnect network is quite complex.
	57	* Since that will not bring real advantage to represent that in DT for
	58	* the moment, just use a fake OCP bus entry to represent the whole bus
	59	* hierarchy.
	60	*/
	61	ocp {
	62	compatible = "ti,omap4-l3-noc", "simple-bus";
	63	#address-cells = <1>;
	64	#size-cells = <1>;
65	ranges;
66	ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
67
68	gic: interrupt-controller@48211000 {
69	compatible = "arm,cortex-a15-gic";
70	interrupt-controller;
71	#interrupt-cells = <3>;
72	reg = <0x48211000 0x1000>,
73	<0x48212000 0x1000>;
74	};
75
76	gpio1: gpio@4ae10000 {
77	compatible = "ti,omap4-gpio";
78	ti,hwmods = "gpio1";
79	gpio-controller;
80	#gpio-cells = <2>;
81	interrupt-controller;
82	#interrupt-cells = <1>;
83	};
84
85	gpio2: gpio@48055000 {
86	compatible = "ti,omap4-gpio";
87	ti,hwmods = "gpio2";
88	gpio-controller;
89	#gpio-cells = <2>;
90	interrupt-controller;
91	#interrupt-cells = <1>;
92	};
93
94	gpio3: gpio@48057000 {
95	compatible = "ti,omap4-gpio";
96	ti,hwmods = "gpio3";
97	gpio-controller;
98	#gpio-cells = <2>;
99	interrupt-controller;
100	#interrupt-cells = <1>;
101	};
102
103	gpio4: gpio@48059000 {
104	compatible = "ti,omap4-gpio";
105	ti,hwmods = "gpio4";
106	gpio-controller;
107	#gpio-cells = <2>;
108	interrupt-controller;
109	#interrupt-cells = <1>;
110	};
111
112	gpio5: gpio@4805b000 {
113	compatible = "ti,omap4-gpio";
114	ti,hwmods = "gpio5";
115	gpio-controller;
116	#gpio-cells = <2>;
117	interrupt-controller;
118	#interrupt-cells = <1>;
119	};
120
121	gpio6: gpio@4805d000 {
122	compatible = "ti,omap4-gpio";
123	ti,hwmods = "gpio6";
124	gpio-controller;
125	#gpio-cells = <2>;
126	interrupt-controller;
127	#interrupt-cells = <1>;
128	};
129
130	gpio7: gpio@48051000 {
131	compatible = "ti,omap4-gpio";
132	ti,hwmods = "gpio7";
133	gpio-controller;
134	#gpio-cells = <2>;
135	interrupt-controller;
136	#interrupt-cells = <1>;
137	};
138
139	gpio8: gpio@48053000 {
140	compatible = "ti,omap4-gpio";
141	ti,hwmods = "gpio8";
142	gpio-controller;
143	#gpio-cells = <2>;
144	interrupt-controller;
145	#interrupt-cells = <1>;
146	};
147
6e6a9a50 SP	148	i2c1: i2c@48070000 {
	149	compatible = "ti,omap4-i2c";
	150	#address-cells = <1>;
	151	#size-cells = <0>;
	152	ti,hwmods = "i2c1";
	153	};
	154
	155	i2c2: i2c@48072000 {
	156	compatible = "ti,omap4-i2c";
	157	#address-cells = <1>;
	158	#size-cells = <0>;
	159	ti,hwmods = "i2c2";
	160	};
	161
	162	i2c3: i2c@48060000 {
	163	compatible = "ti,omap4-i2c";
	164	#address-cells = <1>;
	165	#size-cells = <0>;
	166	ti,hwmods = "i2c3";
	167	};
	168
	169	i2c4: i2c@4807A000 {
	170	compatible = "ti,omap4-i2c";
	171	#address-cells = <1>;
	172	#size-cells = <0>;
	173	ti,hwmods = "i2c4";
	174	};
	175
	176	i2c5: i2c@4807C000 {
	177	compatible = "ti,omap4-i2c";
	178	#address-cells = <1>;
	179	#size-cells = <0>;
	180	ti,hwmods = "i2c5";
	181	};
	182
6b5de091 S	183	uart1: serial@4806a000 {
	184	compatible = "ti,omap4-uart";
	185	ti,hwmods = "uart1";
	186	clock-frequency = <48000000>;
	187	};
	188
	189	uart2: serial@4806c000 {
	190	compatible = "ti,omap4-uart";
	191	ti,hwmods = "uart2";
	192	clock-frequency = <48000000>;
	193	};
	194
	195	uart3: serial@48020000 {
	196	compatible = "ti,omap4-uart";
	197	ti,hwmods = "uart3";
	198	clock-frequency = <48000000>;
	199	};
	200
	201	uart4: serial@4806e000 {
	202	compatible = "ti,omap4-uart";
	203	ti,hwmods = "uart4";
	204	clock-frequency = <48000000>;
	205	};
	206
	207	uart5: serial@48066000 {
	208	compatible = "ti,omap5-uart";
	209	ti,hwmods = "uart5";
	210	clock-frequency = <48000000>;
	211	};
	212
	213	uart6: serial@48068000 {
	214	compatible = "ti,omap6-uart";
	215	ti,hwmods = "uart6";
	216	clock-frequency = <48000000>;
	217	};
5dd18b01 B	218
	219	mmc1: mmc@4809c000 {
	220	compatible = "ti,omap4-hsmmc";
	221	ti,hwmods = "mmc1";
	222	ti,dual-volt;
	223	ti,needs-special-reset;
	224	};
	225
	226	mmc2: mmc@480b4000 {
	227	compatible = "ti,omap4-hsmmc";
	228	ti,hwmods = "mmc2";
	229	ti,needs-special-reset;
	230	};
	231
	232	mmc3: mmc@480ad000 {
	233	compatible = "ti,omap4-hsmmc";
	234	ti,hwmods = "mmc3";
	235	ti,needs-special-reset;
	236	};
	237
	238	mmc4: mmc@480d1000 {
	239	compatible = "ti,omap4-hsmmc";
	240	ti,hwmods = "mmc4";
	241	ti,needs-special-reset;
	242	};
	243
	244	mmc5: mmc@480d5000 {
	245	compatible = "ti,omap4-hsmmc";
	246	ti,hwmods = "mmc5";
	247	ti,needs-special-reset;
	248	};
5449fbc2 SP	249
	250	keypad: keypad@4ae1c000 {
	251	compatible = "ti,omap4-keypad";
	252	ti,hwmods = "kbd";
	253	};
6b5de091 S	254	};
6b5de091 S	255	};