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Merge 4.14.69 into android-4.14-p
[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / drivers / usb / dwc3 / core.c
1 /**
2 * core.c - DesignWare USB3 DRD Controller Core file
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include <linux/version.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/io.h>
32 #include <linux/list.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/of.h>
36 #include <linux/acpi.h>
37 #include <linux/pinctrl/consumer.h>
38
39 #include <linux/usb/ch9.h>
40 #include <linux/usb/gadget.h>
41 #include <linux/usb/of.h>
42 #include <linux/usb/otg.h>
43
44 #include "core.h"
45 #include "gadget.h"
46 #include "io.h"
47
48 #include "debug.h"
49
50 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
51
52 /**
53 * dwc3_get_dr_mode - Validates and sets dr_mode
54 * @dwc: pointer to our context structure
55 */
56 static int dwc3_get_dr_mode(struct dwc3 *dwc)
57 {
58 enum usb_dr_mode mode;
59 struct device *dev = dwc->dev;
60 unsigned int hw_mode;
61
62 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
63 dwc->dr_mode = USB_DR_MODE_OTG;
64
65 mode = dwc->dr_mode;
66 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
67
68 switch (hw_mode) {
69 case DWC3_GHWPARAMS0_MODE_GADGET:
70 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
71 dev_err(dev,
72 "Controller does not support host mode.\n");
73 return -EINVAL;
74 }
75 mode = USB_DR_MODE_PERIPHERAL;
76 break;
77 case DWC3_GHWPARAMS0_MODE_HOST:
78 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
79 dev_err(dev,
80 "Controller does not support device mode.\n");
81 return -EINVAL;
82 }
83 mode = USB_DR_MODE_HOST;
84 break;
85 default:
86 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
87 mode = USB_DR_MODE_HOST;
88 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
89 mode = USB_DR_MODE_PERIPHERAL;
90 }
91
92 if (mode != dwc->dr_mode) {
93 dev_warn(dev,
94 "Configuration mismatch. dr_mode forced to %s\n",
95 mode == USB_DR_MODE_HOST ? "host" : "gadget");
96
97 dwc->dr_mode = mode;
98 }
99
100 return 0;
101 }
102
103 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
104 static int dwc3_event_buffers_setup(struct dwc3 *dwc);
105
106 static void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
107 {
108 u32 reg;
109
110 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
111 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
112 reg |= DWC3_GCTL_PRTCAPDIR(mode);
113 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
114 }
115
116 static void __dwc3_set_mode(struct work_struct *work)
117 {
118 struct dwc3 *dwc = work_to_dwc(work);
119 unsigned long flags;
120 int ret;
121
122 if (!dwc->desired_dr_role)
123 return;
124
125 if (dwc->desired_dr_role == dwc->current_dr_role)
126 return;
127
128 if (dwc->dr_mode != USB_DR_MODE_OTG)
129 return;
130
131 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG)
132 return;
133
134 switch (dwc->current_dr_role) {
135 case DWC3_GCTL_PRTCAP_HOST:
136 dwc3_host_exit(dwc);
137 break;
138 case DWC3_GCTL_PRTCAP_DEVICE:
139 dwc3_gadget_exit(dwc);
140 dwc3_event_buffers_cleanup(dwc);
141 break;
142 default:
143 break;
144 }
145
146 spin_lock_irqsave(&dwc->lock, flags);
147
148 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
149
150 dwc->current_dr_role = dwc->desired_dr_role;
151
152 spin_unlock_irqrestore(&dwc->lock, flags);
153
154 switch (dwc->desired_dr_role) {
155 case DWC3_GCTL_PRTCAP_HOST:
156 ret = dwc3_host_init(dwc);
157 if (ret) {
158 dev_err(dwc->dev, "failed to initialize host\n");
159 } else {
160 if (dwc->usb2_phy)
161 otg_set_vbus(dwc->usb2_phy->otg, true);
162 if (dwc->usb2_generic_phy)
163 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
164
165 }
166 break;
167 case DWC3_GCTL_PRTCAP_DEVICE:
168 dwc3_event_buffers_setup(dwc);
169
170 if (dwc->usb2_phy)
171 otg_set_vbus(dwc->usb2_phy->otg, false);
172 if (dwc->usb2_generic_phy)
173 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
174
175 ret = dwc3_gadget_init(dwc);
176 if (ret)
177 dev_err(dwc->dev, "failed to initialize peripheral\n");
178 break;
179 default:
180 break;
181 }
182 }
183
184 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
185 {
186 unsigned long flags;
187
188 spin_lock_irqsave(&dwc->lock, flags);
189 dwc->desired_dr_role = mode;
190 spin_unlock_irqrestore(&dwc->lock, flags);
191
192 queue_work(system_freezable_wq, &dwc->drd_work);
193 }
194
195 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
196 {
197 struct dwc3 *dwc = dep->dwc;
198 u32 reg;
199
200 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
201 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
202 DWC3_GDBGFIFOSPACE_TYPE(type));
203
204 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
205
206 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
207 }
208
209 /**
210 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
211 * @dwc: pointer to our context structure
212 */
213 static int dwc3_core_soft_reset(struct dwc3 *dwc)
214 {
215 u32 reg;
216 int retries = 1000;
217 int ret;
218
219 usb_phy_init(dwc->usb2_phy);
220 usb_phy_init(dwc->usb3_phy);
221 ret = phy_init(dwc->usb2_generic_phy);
222 if (ret < 0)
223 return ret;
224
225 ret = phy_init(dwc->usb3_generic_phy);
226 if (ret < 0) {
227 phy_exit(dwc->usb2_generic_phy);
228 return ret;
229 }
230
231 /*
232 * We're resetting only the device side because, if we're in host mode,
233 * XHCI driver will reset the host block. If dwc3 was configured for
234 * host-only mode, then we can return early.
235 */
236 if (dwc->dr_mode == USB_DR_MODE_HOST)
237 return 0;
238
239 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
240 reg |= DWC3_DCTL_CSFTRST;
241 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
242
243 do {
244 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
245 if (!(reg & DWC3_DCTL_CSFTRST))
246 goto done;
247
248 udelay(1);
249 } while (--retries);
250
251 phy_exit(dwc->usb3_generic_phy);
252 phy_exit(dwc->usb2_generic_phy);
253
254 return -ETIMEDOUT;
255
256 done:
257 /*
258 * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
259 * we must wait at least 50ms before accessing the PHY domain
260 * (synchronization delay). DWC_usb31 programming guide section 1.3.2.
261 */
262 if (dwc3_is_usb31(dwc))
263 msleep(50);
264
265 return 0;
266 }
267
268 /*
269 * dwc3_frame_length_adjustment - Adjusts frame length if required
270 * @dwc3: Pointer to our controller context structure
271 */
272 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
273 {
274 u32 reg;
275 u32 dft;
276
277 if (dwc->revision < DWC3_REVISION_250A)
278 return;
279
280 if (dwc->fladj == 0)
281 return;
282
283 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
284 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
285 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
286 "request value same as default, ignoring\n")) {
287 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
288 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
289 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
290 }
291 }
292
293 /**
294 * dwc3_free_one_event_buffer - Frees one event buffer
295 * @dwc: Pointer to our controller context structure
296 * @evt: Pointer to event buffer to be freed
297 */
298 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
299 struct dwc3_event_buffer *evt)
300 {
301 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
302 }
303
304 /**
305 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
306 * @dwc: Pointer to our controller context structure
307 * @length: size of the event buffer
308 *
309 * Returns a pointer to the allocated event buffer structure on success
310 * otherwise ERR_PTR(errno).
311 */
312 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
313 unsigned length)
314 {
315 struct dwc3_event_buffer *evt;
316
317 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
318 if (!evt)
319 return ERR_PTR(-ENOMEM);
320
321 evt->dwc = dwc;
322 evt->length = length;
323 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
324 if (!evt->cache)
325 return ERR_PTR(-ENOMEM);
326
327 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
328 &evt->dma, GFP_KERNEL);
329 if (!evt->buf)
330 return ERR_PTR(-ENOMEM);
331
332 return evt;
333 }
334
335 /**
336 * dwc3_free_event_buffers - frees all allocated event buffers
337 * @dwc: Pointer to our controller context structure
338 */
339 static void dwc3_free_event_buffers(struct dwc3 *dwc)
340 {
341 struct dwc3_event_buffer *evt;
342
343 evt = dwc->ev_buf;
344 if (evt)
345 dwc3_free_one_event_buffer(dwc, evt);
346 }
347
348 /**
349 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
350 * @dwc: pointer to our controller context structure
351 * @length: size of event buffer
352 *
353 * Returns 0 on success otherwise negative errno. In the error case, dwc
354 * may contain some buffers allocated but not all which were requested.
355 */
356 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
357 {
358 struct dwc3_event_buffer *evt;
359
360 evt = dwc3_alloc_one_event_buffer(dwc, length);
361 if (IS_ERR(evt)) {
362 dev_err(dwc->dev, "can't allocate event buffer\n");
363 return PTR_ERR(evt);
364 }
365 dwc->ev_buf = evt;
366
367 return 0;
368 }
369
370 /**
371 * dwc3_event_buffers_setup - setup our allocated event buffers
372 * @dwc: pointer to our controller context structure
373 *
374 * Returns 0 on success otherwise negative errno.
375 */
376 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
377 {
378 struct dwc3_event_buffer *evt;
379
380 evt = dwc->ev_buf;
381 evt->lpos = 0;
382 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
383 lower_32_bits(evt->dma));
384 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
385 upper_32_bits(evt->dma));
386 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
387 DWC3_GEVNTSIZ_SIZE(evt->length));
388 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
389
390 return 0;
391 }
392
393 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
394 {
395 struct dwc3_event_buffer *evt;
396
397 evt = dwc->ev_buf;
398
399 evt->lpos = 0;
400
401 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
402 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
403 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
404 | DWC3_GEVNTSIZ_SIZE(0));
405 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
406 }
407
408 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
409 {
410 if (!dwc->has_hibernation)
411 return 0;
412
413 if (!dwc->nr_scratch)
414 return 0;
415
416 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
417 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
418 if (!dwc->scratchbuf)
419 return -ENOMEM;
420
421 return 0;
422 }
423
424 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
425 {
426 dma_addr_t scratch_addr;
427 u32 param;
428 int ret;
429
430 if (!dwc->has_hibernation)
431 return 0;
432
433 if (!dwc->nr_scratch)
434 return 0;
435
436 /* should never fall here */
437 if (!WARN_ON(dwc->scratchbuf))
438 return 0;
439
440 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
441 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
442 DMA_BIDIRECTIONAL);
443 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
444 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
445 ret = -EFAULT;
446 goto err0;
447 }
448
449 dwc->scratch_addr = scratch_addr;
450
451 param = lower_32_bits(scratch_addr);
452
453 ret = dwc3_send_gadget_generic_command(dwc,
454 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
455 if (ret < 0)
456 goto err1;
457
458 param = upper_32_bits(scratch_addr);
459
460 ret = dwc3_send_gadget_generic_command(dwc,
461 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
462 if (ret < 0)
463 goto err1;
464
465 return 0;
466
467 err1:
468 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
469 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
470
471 err0:
472 return ret;
473 }
474
475 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
476 {
477 if (!dwc->has_hibernation)
478 return;
479
480 if (!dwc->nr_scratch)
481 return;
482
483 /* should never fall here */
484 if (!WARN_ON(dwc->scratchbuf))
485 return;
486
487 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
488 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
489 kfree(dwc->scratchbuf);
490 }
491
492 static void dwc3_core_num_eps(struct dwc3 *dwc)
493 {
494 struct dwc3_hwparams *parms = &dwc->hwparams;
495
496 dwc->num_eps = DWC3_NUM_EPS(parms);
497 }
498
499 static void dwc3_cache_hwparams(struct dwc3 *dwc)
500 {
501 struct dwc3_hwparams *parms = &dwc->hwparams;
502
503 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
504 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
505 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
506 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
507 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
508 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
509 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
510 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
511 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
512 }
513
514 /**
515 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
516 * @dwc: Pointer to our controller context structure
517 *
518 * Returns 0 on success. The USB PHY interfaces are configured but not
519 * initialized. The PHY interfaces and the PHYs get initialized together with
520 * the core in dwc3_core_init.
521 */
522 static int dwc3_phy_setup(struct dwc3 *dwc)
523 {
524 u32 reg;
525 int ret;
526
527 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
528
529 /*
530 * Make sure UX_EXIT_PX is cleared as that causes issues with some
531 * PHYs. Also, this bit is not supposed to be used in normal operation.
532 */
533 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
534
535 /*
536 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
537 * to '0' during coreConsultant configuration. So default value
538 * will be '0' when the core is reset. Application needs to set it
539 * to '1' after the core initialization is completed.
540 */
541 if (dwc->revision > DWC3_REVISION_194A)
542 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
543
544 if (dwc->u2ss_inp3_quirk)
545 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
546
547 if (dwc->dis_rxdet_inp3_quirk)
548 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
549
550 if (dwc->req_p1p2p3_quirk)
551 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
552
553 if (dwc->del_p1p2p3_quirk)
554 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
555
556 if (dwc->del_phy_power_chg_quirk)
557 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
558
559 if (dwc->lfps_filter_quirk)
560 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
561
562 if (dwc->rx_detect_poll_quirk)
563 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
564
565 if (dwc->tx_de_emphasis_quirk)
566 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
567
568 if (dwc->dis_u3_susphy_quirk)
569 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
570
571 if (dwc->dis_del_phy_power_chg_quirk)
572 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
573
574 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
575
576 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
577
578 /* Select the HS PHY interface */
579 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
580 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
581 if (dwc->hsphy_interface &&
582 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
583 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
584 break;
585 } else if (dwc->hsphy_interface &&
586 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
587 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
588 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
589 } else {
590 /* Relying on default value. */
591 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
592 break;
593 }
594 /* FALLTHROUGH */
595 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
596 ret = dwc3_ulpi_init(dwc);
597 if (ret)
598 return ret;
599 /* FALLTHROUGH */
600 default:
601 break;
602 }
603
604 switch (dwc->hsphy_mode) {
605 case USBPHY_INTERFACE_MODE_UTMI:
606 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
607 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
608 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
609 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
610 break;
611 case USBPHY_INTERFACE_MODE_UTMIW:
612 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
613 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
614 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
615 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
616 break;
617 default:
618 break;
619 }
620
621 /*
622 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
623 * '0' during coreConsultant configuration. So default value will
624 * be '0' when the core is reset. Application needs to set it to
625 * '1' after the core initialization is completed.
626 */
627 if (dwc->revision > DWC3_REVISION_194A)
628 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
629
630 if (dwc->dis_u2_susphy_quirk)
631 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
632
633 if (dwc->dis_enblslpm_quirk)
634 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
635
636 if (dwc->dis_u2_freeclk_exists_quirk)
637 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
638
639 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
640
641 return 0;
642 }
643
644 static void dwc3_core_exit(struct dwc3 *dwc)
645 {
646 dwc3_event_buffers_cleanup(dwc);
647
648 usb_phy_shutdown(dwc->usb2_phy);
649 usb_phy_shutdown(dwc->usb3_phy);
650 phy_exit(dwc->usb2_generic_phy);
651 phy_exit(dwc->usb3_generic_phy);
652
653 usb_phy_set_suspend(dwc->usb2_phy, 1);
654 usb_phy_set_suspend(dwc->usb3_phy, 1);
655 phy_power_off(dwc->usb2_generic_phy);
656 phy_power_off(dwc->usb3_generic_phy);
657 }
658
659 static bool dwc3_core_is_valid(struct dwc3 *dwc)
660 {
661 u32 reg;
662
663 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
664
665 /* This should read as U3 followed by revision number */
666 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
667 /* Detected DWC_usb3 IP */
668 dwc->revision = reg;
669 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
670 /* Detected DWC_usb31 IP */
671 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
672 dwc->revision |= DWC3_REVISION_IS_DWC31;
673 } else {
674 return false;
675 }
676
677 return true;
678 }
679
680 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
681 {
682 u32 hwparams4 = dwc->hwparams.hwparams4;
683 u32 reg;
684
685 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
686 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
687
688 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
689 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
690 /**
691 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
692 * issue which would cause xHCI compliance tests to fail.
693 *
694 * Because of that we cannot enable clock gating on such
695 * configurations.
696 *
697 * Refers to:
698 *
699 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
700 * SOF/ITP Mode Used
701 */
702 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
703 dwc->dr_mode == USB_DR_MODE_OTG) &&
704 (dwc->revision >= DWC3_REVISION_210A &&
705 dwc->revision <= DWC3_REVISION_250A))
706 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
707 else
708 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
709 break;
710 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
711 /* enable hibernation here */
712 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
713
714 /*
715 * REVISIT Enabling this bit so that host-mode hibernation
716 * will work. Device-mode hibernation is not yet implemented.
717 */
718 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
719 break;
720 default:
721 /* nothing */
722 break;
723 }
724
725 /* check if current dwc3 is on simulation board */
726 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
727 dev_info(dwc->dev, "Running with FPGA optmizations\n");
728 dwc->is_fpga = true;
729 }
730
731 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
732 "disable_scramble cannot be used on non-FPGA builds\n");
733
734 if (dwc->disable_scramble_quirk && dwc->is_fpga)
735 reg |= DWC3_GCTL_DISSCRAMBLE;
736 else
737 reg &= ~DWC3_GCTL_DISSCRAMBLE;
738
739 if (dwc->u2exit_lfps_quirk)
740 reg |= DWC3_GCTL_U2EXIT_LFPS;
741
742 /*
743 * WORKAROUND: DWC3 revisions <1.90a have a bug
744 * where the device can fail to connect at SuperSpeed
745 * and falls back to high-speed mode which causes
746 * the device to enter a Connect/Disconnect loop
747 */
748 if (dwc->revision < DWC3_REVISION_190A)
749 reg |= DWC3_GCTL_U2RSTECN;
750
751 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
752 }
753
754 static int dwc3_core_get_phy(struct dwc3 *dwc);
755
756 /**
757 * dwc3_core_init - Low-level initialization of DWC3 Core
758 * @dwc: Pointer to our controller context structure
759 *
760 * Returns 0 on success otherwise negative errno.
761 */
762 static int dwc3_core_init(struct dwc3 *dwc)
763 {
764 u32 reg;
765 int ret;
766
767 if (!dwc3_core_is_valid(dwc)) {
768 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
769 ret = -ENODEV;
770 goto err0;
771 }
772
773 /*
774 * Write Linux Version Code to our GUID register so it's easy to figure
775 * out which kernel version a bug was found.
776 */
777 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
778
779 /* Handle USB2.0-only core configuration */
780 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
781 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
782 if (dwc->maximum_speed == USB_SPEED_SUPER)
783 dwc->maximum_speed = USB_SPEED_HIGH;
784 }
785
786 ret = dwc3_core_get_phy(dwc);
787 if (ret)
788 goto err0;
789
790 ret = dwc3_core_soft_reset(dwc);
791 if (ret)
792 goto err0;
793
794 ret = dwc3_phy_setup(dwc);
795 if (ret)
796 goto err0;
797
798 dwc3_core_setup_global_control(dwc);
799 dwc3_core_num_eps(dwc);
800
801 ret = dwc3_setup_scratch_buffers(dwc);
802 if (ret)
803 goto err1;
804
805 /* Adjust Frame Length */
806 dwc3_frame_length_adjustment(dwc);
807
808 usb_phy_set_suspend(dwc->usb2_phy, 0);
809 usb_phy_set_suspend(dwc->usb3_phy, 0);
810 ret = phy_power_on(dwc->usb2_generic_phy);
811 if (ret < 0)
812 goto err2;
813
814 ret = phy_power_on(dwc->usb3_generic_phy);
815 if (ret < 0)
816 goto err3;
817
818 ret = dwc3_event_buffers_setup(dwc);
819 if (ret) {
820 dev_err(dwc->dev, "failed to setup event buffers\n");
821 goto err4;
822 }
823
824 /*
825 * ENDXFER polling is available on version 3.10a and later of
826 * the DWC_usb3 controller. It is NOT available in the
827 * DWC_usb31 controller.
828 */
829 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
830 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
831 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
832 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
833 }
834
835 if (dwc->revision >= DWC3_REVISION_250A) {
836 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
837
838 /*
839 * Enable hardware control of sending remote wakeup
840 * in HS when the device is in the L1 state.
841 */
842 if (dwc->revision >= DWC3_REVISION_290A)
843 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
844
845 if (dwc->dis_tx_ipgap_linecheck_quirk)
846 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
847
848 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
849 }
850
851 return 0;
852
853 err4:
854 phy_power_off(dwc->usb3_generic_phy);
855
856 err3:
857 phy_power_off(dwc->usb2_generic_phy);
858
859 err2:
860 usb_phy_set_suspend(dwc->usb2_phy, 1);
861 usb_phy_set_suspend(dwc->usb3_phy, 1);
862
863 err1:
864 usb_phy_shutdown(dwc->usb2_phy);
865 usb_phy_shutdown(dwc->usb3_phy);
866 phy_exit(dwc->usb2_generic_phy);
867 phy_exit(dwc->usb3_generic_phy);
868
869 err0:
870 return ret;
871 }
872
873 static int dwc3_core_get_phy(struct dwc3 *dwc)
874 {
875 struct device *dev = dwc->dev;
876 struct device_node *node = dev->of_node;
877 int ret;
878
879 if (node) {
880 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
881 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
882 } else {
883 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
884 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
885 }
886
887 if (IS_ERR(dwc->usb2_phy)) {
888 ret = PTR_ERR(dwc->usb2_phy);
889 if (ret == -ENXIO || ret == -ENODEV) {
890 dwc->usb2_phy = NULL;
891 } else if (ret == -EPROBE_DEFER) {
892 return ret;
893 } else {
894 dev_err(dev, "no usb2 phy configured\n");
895 return ret;
896 }
897 }
898
899 if (IS_ERR(dwc->usb3_phy)) {
900 ret = PTR_ERR(dwc->usb3_phy);
901 if (ret == -ENXIO || ret == -ENODEV) {
902 dwc->usb3_phy = NULL;
903 } else if (ret == -EPROBE_DEFER) {
904 return ret;
905 } else {
906 dev_err(dev, "no usb3 phy configured\n");
907 return ret;
908 }
909 }
910
911 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
912 if (IS_ERR(dwc->usb2_generic_phy)) {
913 ret = PTR_ERR(dwc->usb2_generic_phy);
914 if (ret == -ENOSYS || ret == -ENODEV) {
915 dwc->usb2_generic_phy = NULL;
916 } else if (ret == -EPROBE_DEFER) {
917 return ret;
918 } else {
919 dev_err(dev, "no usb2 phy configured\n");
920 return ret;
921 }
922 }
923
924 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
925 if (IS_ERR(dwc->usb3_generic_phy)) {
926 ret = PTR_ERR(dwc->usb3_generic_phy);
927 if (ret == -ENOSYS || ret == -ENODEV) {
928 dwc->usb3_generic_phy = NULL;
929 } else if (ret == -EPROBE_DEFER) {
930 return ret;
931 } else {
932 dev_err(dev, "no usb3 phy configured\n");
933 return ret;
934 }
935 }
936
937 return 0;
938 }
939
940 static int dwc3_core_init_mode(struct dwc3 *dwc)
941 {
942 struct device *dev = dwc->dev;
943 int ret;
944
945 switch (dwc->dr_mode) {
946 case USB_DR_MODE_PERIPHERAL:
947 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
948
949 if (dwc->usb2_phy)
950 otg_set_vbus(dwc->usb2_phy->otg, false);
951 if (dwc->usb2_generic_phy)
952 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
953
954 ret = dwc3_gadget_init(dwc);
955 if (ret) {
956 if (ret != -EPROBE_DEFER)
957 dev_err(dev, "failed to initialize gadget\n");
958 return ret;
959 }
960 break;
961 case USB_DR_MODE_HOST:
962 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
963
964 if (dwc->usb2_phy)
965 otg_set_vbus(dwc->usb2_phy->otg, true);
966 if (dwc->usb2_generic_phy)
967 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
968
969 ret = dwc3_host_init(dwc);
970 if (ret) {
971 if (ret != -EPROBE_DEFER)
972 dev_err(dev, "failed to initialize host\n");
973 return ret;
974 }
975 break;
976 case USB_DR_MODE_OTG:
977 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
978 ret = dwc3_drd_init(dwc);
979 if (ret) {
980 if (ret != -EPROBE_DEFER)
981 dev_err(dev, "failed to initialize dual-role\n");
982 return ret;
983 }
984 break;
985 default:
986 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
987 return -EINVAL;
988 }
989
990 return 0;
991 }
992
993 static void dwc3_core_exit_mode(struct dwc3 *dwc)
994 {
995 switch (dwc->dr_mode) {
996 case USB_DR_MODE_PERIPHERAL:
997 dwc3_gadget_exit(dwc);
998 break;
999 case USB_DR_MODE_HOST:
1000 dwc3_host_exit(dwc);
1001 break;
1002 case USB_DR_MODE_OTG:
1003 dwc3_drd_exit(dwc);
1004 break;
1005 default:
1006 /* do nothing */
1007 break;
1008 }
1009 }
1010
1011 static void dwc3_get_properties(struct dwc3 *dwc)
1012 {
1013 struct device *dev = dwc->dev;
1014 u8 lpm_nyet_threshold;
1015 u8 tx_de_emphasis;
1016 u8 hird_threshold;
1017
1018 /* default to highest possible threshold */
1019 lpm_nyet_threshold = 0xff;
1020
1021 /* default to -3.5dB de-emphasis */
1022 tx_de_emphasis = 1;
1023
1024 /*
1025 * default to assert utmi_sleep_n and use maximum allowed HIRD
1026 * threshold value of 0b1100
1027 */
1028 hird_threshold = 12;
1029
1030 dwc->maximum_speed = usb_get_maximum_speed(dev);
1031 dwc->dr_mode = usb_get_dr_mode(dev);
1032 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1033
1034 dwc->sysdev_is_parent = device_property_read_bool(dev,
1035 "linux,sysdev_is_parent");
1036 if (dwc->sysdev_is_parent)
1037 dwc->sysdev = dwc->dev->parent;
1038 else
1039 dwc->sysdev = dwc->dev;
1040
1041 dwc->has_lpm_erratum = device_property_read_bool(dev,
1042 "snps,has-lpm-erratum");
1043 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1044 &lpm_nyet_threshold);
1045 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1046 "snps,is-utmi-l1-suspend");
1047 device_property_read_u8(dev, "snps,hird-threshold",
1048 &hird_threshold);
1049 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1050 "snps,usb3_lpm_capable");
1051
1052 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1053 "snps,disable_scramble_quirk");
1054 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1055 "snps,u2exit_lfps_quirk");
1056 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1057 "snps,u2ss_inp3_quirk");
1058 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1059 "snps,req_p1p2p3_quirk");
1060 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1061 "snps,del_p1p2p3_quirk");
1062 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1063 "snps,del_phy_power_chg_quirk");
1064 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1065 "snps,lfps_filter_quirk");
1066 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1067 "snps,rx_detect_poll_quirk");
1068 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1069 "snps,dis_u3_susphy_quirk");
1070 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1071 "snps,dis_u2_susphy_quirk");
1072 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1073 "snps,dis_enblslpm_quirk");
1074 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1075 "snps,dis_rxdet_inp3_quirk");
1076 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1077 "snps,dis-u2-freeclk-exists-quirk");
1078 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1079 "snps,dis-del-phy-power-chg-quirk");
1080 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1081 "snps,dis-tx-ipgap-linecheck-quirk");
1082
1083 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1084 "snps,tx_de_emphasis_quirk");
1085 device_property_read_u8(dev, "snps,tx_de_emphasis",
1086 &tx_de_emphasis);
1087 device_property_read_string(dev, "snps,hsphy_interface",
1088 &dwc->hsphy_interface);
1089 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1090 &dwc->fladj);
1091
1092 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1093 dwc->tx_de_emphasis = tx_de_emphasis;
1094
1095 dwc->hird_threshold = hird_threshold
1096 | (dwc->is_utmi_l1_suspend << 4);
1097
1098 dwc->imod_interval = 0;
1099 }
1100
1101 /* check whether the core supports IMOD */
1102 bool dwc3_has_imod(struct dwc3 *dwc)
1103 {
1104 return ((dwc3_is_usb3(dwc) &&
1105 dwc->revision >= DWC3_REVISION_300A) ||
1106 (dwc3_is_usb31(dwc) &&
1107 dwc->revision >= DWC3_USB31_REVISION_120A));
1108 }
1109
1110 static void dwc3_check_params(struct dwc3 *dwc)
1111 {
1112 struct device *dev = dwc->dev;
1113
1114 /* Check for proper value of imod_interval */
1115 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1116 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1117 dwc->imod_interval = 0;
1118 }
1119
1120 /*
1121 * Workaround for STAR 9000961433 which affects only version
1122 * 3.00a of the DWC_usb3 core. This prevents the controller
1123 * interrupt from being masked while handling events. IMOD
1124 * allows us to work around this issue. Enable it for the
1125 * affected version.
1126 */
1127 if (!dwc->imod_interval &&
1128 (dwc->revision == DWC3_REVISION_300A))
1129 dwc->imod_interval = 1;
1130
1131 /* Check the maximum_speed parameter */
1132 switch (dwc->maximum_speed) {
1133 case USB_SPEED_LOW:
1134 case USB_SPEED_FULL:
1135 case USB_SPEED_HIGH:
1136 case USB_SPEED_SUPER:
1137 case USB_SPEED_SUPER_PLUS:
1138 break;
1139 default:
1140 dev_err(dev, "invalid maximum_speed parameter %d\n",
1141 dwc->maximum_speed);
1142 /* fall through */
1143 case USB_SPEED_UNKNOWN:
1144 /* default to superspeed */
1145 dwc->maximum_speed = USB_SPEED_SUPER;
1146
1147 /*
1148 * default to superspeed plus if we are capable.
1149 */
1150 if (dwc3_is_usb31(dwc) &&
1151 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1152 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1153 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1154
1155 break;
1156 }
1157 }
1158
1159 static int dwc3_probe(struct platform_device *pdev)
1160 {
1161 struct device *dev = &pdev->dev;
1162 struct resource *res;
1163 struct dwc3 *dwc;
1164
1165 int ret;
1166
1167 void __iomem *regs;
1168
1169 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1170 if (!dwc)
1171 return -ENOMEM;
1172
1173 dwc->dev = dev;
1174
1175 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1176 if (!res) {
1177 dev_err(dev, "missing memory resource\n");
1178 return -ENODEV;
1179 }
1180
1181 dwc->xhci_resources[0].start = res->start;
1182 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1183 DWC3_XHCI_REGS_END;
1184 dwc->xhci_resources[0].flags = res->flags;
1185 dwc->xhci_resources[0].name = res->name;
1186
1187 res->start += DWC3_GLOBALS_REGS_START;
1188
1189 /*
1190 * Request memory region but exclude xHCI regs,
1191 * since it will be requested by the xhci-plat driver.
1192 */
1193 regs = devm_ioremap_resource(dev, res);
1194 if (IS_ERR(regs)) {
1195 ret = PTR_ERR(regs);
1196 goto err0;
1197 }
1198
1199 dwc->regs = regs;
1200 dwc->regs_size = resource_size(res);
1201
1202 dwc3_get_properties(dwc);
1203
1204 platform_set_drvdata(pdev, dwc);
1205 dwc3_cache_hwparams(dwc);
1206
1207 spin_lock_init(&dwc->lock);
1208
1209 pm_runtime_set_active(dev);
1210 pm_runtime_use_autosuspend(dev);
1211 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1212 pm_runtime_enable(dev);
1213 ret = pm_runtime_get_sync(dev);
1214 if (ret < 0)
1215 goto err1;
1216
1217 pm_runtime_forbid(dev);
1218
1219 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1220 if (ret) {
1221 dev_err(dwc->dev, "failed to allocate event buffers\n");
1222 ret = -ENOMEM;
1223 goto err2;
1224 }
1225
1226 ret = dwc3_get_dr_mode(dwc);
1227 if (ret)
1228 goto err3;
1229
1230 ret = dwc3_alloc_scratch_buffers(dwc);
1231 if (ret)
1232 goto err3;
1233
1234 ret = dwc3_core_init(dwc);
1235 if (ret) {
1236 dev_err(dev, "failed to initialize core\n");
1237 goto err4;
1238 }
1239
1240 dwc3_check_params(dwc);
1241
1242 ret = dwc3_core_init_mode(dwc);
1243 if (ret)
1244 goto err5;
1245
1246 dwc3_debugfs_init(dwc);
1247 pm_runtime_put(dev);
1248
1249 return 0;
1250
1251 err5:
1252 dwc3_event_buffers_cleanup(dwc);
1253
1254 err4:
1255 dwc3_free_scratch_buffers(dwc);
1256
1257 err3:
1258 dwc3_free_event_buffers(dwc);
1259 dwc3_ulpi_exit(dwc);
1260
1261 err2:
1262 pm_runtime_allow(&pdev->dev);
1263
1264 err1:
1265 pm_runtime_put_sync(&pdev->dev);
1266 pm_runtime_disable(&pdev->dev);
1267
1268 err0:
1269 /*
1270 * restore res->start back to its original value so that, in case the
1271 * probe is deferred, we don't end up getting error in request the
1272 * memory region the next time probe is called.
1273 */
1274 res->start -= DWC3_GLOBALS_REGS_START;
1275
1276 return ret;
1277 }
1278
1279 static int dwc3_remove(struct platform_device *pdev)
1280 {
1281 struct dwc3 *dwc = platform_get_drvdata(pdev);
1282 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1283
1284 pm_runtime_get_sync(&pdev->dev);
1285 /*
1286 * restore res->start back to its original value so that, in case the
1287 * probe is deferred, we don't end up getting error in request the
1288 * memory region the next time probe is called.
1289 */
1290 res->start -= DWC3_GLOBALS_REGS_START;
1291
1292 dwc3_debugfs_exit(dwc);
1293 dwc3_core_exit_mode(dwc);
1294
1295 dwc3_core_exit(dwc);
1296 dwc3_ulpi_exit(dwc);
1297
1298 pm_runtime_put_sync(&pdev->dev);
1299 pm_runtime_allow(&pdev->dev);
1300 pm_runtime_disable(&pdev->dev);
1301
1302 dwc3_free_event_buffers(dwc);
1303 dwc3_free_scratch_buffers(dwc);
1304
1305 return 0;
1306 }
1307
1308 #ifdef CONFIG_PM
1309 static int dwc3_suspend_common(struct dwc3 *dwc)
1310 {
1311 unsigned long flags;
1312
1313 switch (dwc->dr_mode) {
1314 case USB_DR_MODE_PERIPHERAL:
1315 case USB_DR_MODE_OTG:
1316 spin_lock_irqsave(&dwc->lock, flags);
1317 dwc3_gadget_suspend(dwc);
1318 spin_unlock_irqrestore(&dwc->lock, flags);
1319 break;
1320 case USB_DR_MODE_HOST:
1321 default:
1322 /* do nothing */
1323 break;
1324 }
1325
1326 dwc3_core_exit(dwc);
1327
1328 return 0;
1329 }
1330
1331 static int dwc3_resume_common(struct dwc3 *dwc)
1332 {
1333 unsigned long flags;
1334 int ret;
1335
1336 ret = dwc3_core_init(dwc);
1337 if (ret)
1338 return ret;
1339
1340 switch (dwc->dr_mode) {
1341 case USB_DR_MODE_PERIPHERAL:
1342 case USB_DR_MODE_OTG:
1343 spin_lock_irqsave(&dwc->lock, flags);
1344 dwc3_gadget_resume(dwc);
1345 spin_unlock_irqrestore(&dwc->lock, flags);
1346 /* FALLTHROUGH */
1347 case USB_DR_MODE_HOST:
1348 default:
1349 /* do nothing */
1350 break;
1351 }
1352
1353 return 0;
1354 }
1355
1356 static int dwc3_runtime_checks(struct dwc3 *dwc)
1357 {
1358 switch (dwc->dr_mode) {
1359 case USB_DR_MODE_PERIPHERAL:
1360 case USB_DR_MODE_OTG:
1361 if (dwc->connected)
1362 return -EBUSY;
1363 break;
1364 case USB_DR_MODE_HOST:
1365 default:
1366 /* do nothing */
1367 break;
1368 }
1369
1370 return 0;
1371 }
1372
1373 static int dwc3_runtime_suspend(struct device *dev)
1374 {
1375 struct dwc3 *dwc = dev_get_drvdata(dev);
1376 int ret;
1377
1378 if (dwc3_runtime_checks(dwc))
1379 return -EBUSY;
1380
1381 ret = dwc3_suspend_common(dwc);
1382 if (ret)
1383 return ret;
1384
1385 device_init_wakeup(dev, true);
1386
1387 return 0;
1388 }
1389
1390 static int dwc3_runtime_resume(struct device *dev)
1391 {
1392 struct dwc3 *dwc = dev_get_drvdata(dev);
1393 int ret;
1394
1395 device_init_wakeup(dev, false);
1396
1397 ret = dwc3_resume_common(dwc);
1398 if (ret)
1399 return ret;
1400
1401 switch (dwc->dr_mode) {
1402 case USB_DR_MODE_PERIPHERAL:
1403 case USB_DR_MODE_OTG:
1404 dwc3_gadget_process_pending_events(dwc);
1405 break;
1406 case USB_DR_MODE_HOST:
1407 default:
1408 /* do nothing */
1409 break;
1410 }
1411
1412 pm_runtime_mark_last_busy(dev);
1413 pm_runtime_put(dev);
1414
1415 return 0;
1416 }
1417
1418 static int dwc3_runtime_idle(struct device *dev)
1419 {
1420 struct dwc3 *dwc = dev_get_drvdata(dev);
1421
1422 switch (dwc->dr_mode) {
1423 case USB_DR_MODE_PERIPHERAL:
1424 case USB_DR_MODE_OTG:
1425 if (dwc3_runtime_checks(dwc))
1426 return -EBUSY;
1427 break;
1428 case USB_DR_MODE_HOST:
1429 default:
1430 /* do nothing */
1431 break;
1432 }
1433
1434 pm_runtime_mark_last_busy(dev);
1435 pm_runtime_autosuspend(dev);
1436
1437 return 0;
1438 }
1439 #endif /* CONFIG_PM */
1440
1441 #ifdef CONFIG_PM_SLEEP
1442 static int dwc3_suspend(struct device *dev)
1443 {
1444 struct dwc3 *dwc = dev_get_drvdata(dev);
1445 int ret;
1446
1447 ret = dwc3_suspend_common(dwc);
1448 if (ret)
1449 return ret;
1450
1451 pinctrl_pm_select_sleep_state(dev);
1452
1453 return 0;
1454 }
1455
1456 static int dwc3_resume(struct device *dev)
1457 {
1458 struct dwc3 *dwc = dev_get_drvdata(dev);
1459 int ret;
1460
1461 pinctrl_pm_select_default_state(dev);
1462
1463 ret = dwc3_resume_common(dwc);
1464 if (ret)
1465 return ret;
1466
1467 pm_runtime_disable(dev);
1468 pm_runtime_set_active(dev);
1469 pm_runtime_enable(dev);
1470
1471 return 0;
1472 }
1473 #endif /* CONFIG_PM_SLEEP */
1474
1475 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1476 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1477 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1478 dwc3_runtime_idle)
1479 };
1480
1481 #ifdef CONFIG_OF
1482 static const struct of_device_id of_dwc3_match[] = {
1483 {
1484 .compatible = "snps,dwc3"
1485 },
1486 {
1487 .compatible = "synopsys,dwc3"
1488 },
1489 { },
1490 };
1491 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1492 #endif
1493
1494 #ifdef CONFIG_ACPI
1495
1496 #define ACPI_ID_INTEL_BSW "808622B7"
1497
1498 static const struct acpi_device_id dwc3_acpi_match[] = {
1499 { ACPI_ID_INTEL_BSW, 0 },
1500 { },
1501 };
1502 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1503 #endif
1504
1505 static struct platform_driver dwc3_driver = {
1506 .probe = dwc3_probe,
1507 .remove = dwc3_remove,
1508 .driver = {
1509 .name = "dwc3",
1510 .of_match_table = of_match_ptr(of_dwc3_match),
1511 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1512 .pm = &dwc3_dev_pm_ops,
1513 },
1514 };
1515
1516 module_platform_driver(dwc3_driver);
1517
1518 MODULE_ALIAS("platform:dwc3");
1519 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1520 MODULE_LICENSE("GPL v2");
1521 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");