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[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / drivers / net / wireless / admtek / adm8211.c
1
2 /*
3 * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP)
4 *
5 * Copyright (c) 2003, Jouni Malinen <j@w1.fi>
6 * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net>
7 * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com>
8 * and used with permission.
9 *
10 * Much thanks to Infineon-ADMtek for their support of this driver.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation. See README and COPYING for
15 * more details.
16 */
17
18 #include <linux/interrupt.h>
19 #include <linux/if.h>
20 #include <linux/skbuff.h>
21 #include <linux/slab.h>
22 #include <linux/etherdevice.h>
23 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <linux/crc32.h>
26 #include <linux/eeprom_93cx6.h>
27 #include <linux/module.h>
28 #include <net/mac80211.h>
29
30 #include "adm8211.h"
31
32 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
33 MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
34 MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211");
35 MODULE_SUPPORTED_DEVICE("ADM8211");
36 MODULE_LICENSE("GPL");
37
38 static unsigned int tx_ring_size __read_mostly = 16;
39 static unsigned int rx_ring_size __read_mostly = 16;
40
41 module_param(tx_ring_size, uint, 0);
42 module_param(rx_ring_size, uint, 0);
43
44 static const struct pci_device_id adm8211_pci_id_table[] = {
45 /* ADMtek ADM8211 */
46 { PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */
47 { PCI_DEVICE(0x1200, 0x8201) }, /* ? */
48 { PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */
49 { PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */
50 { 0 }
51 };
52
53 static struct ieee80211_rate adm8211_rates[] = {
54 { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
55 { .bitrate = 20, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
56 { .bitrate = 55, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
57 { .bitrate = 110, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
58 { .bitrate = 220, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, /* XX ?? */
59 };
60
61 static const struct ieee80211_channel adm8211_channels[] = {
62 { .center_freq = 2412},
63 { .center_freq = 2417},
64 { .center_freq = 2422},
65 { .center_freq = 2427},
66 { .center_freq = 2432},
67 { .center_freq = 2437},
68 { .center_freq = 2442},
69 { .center_freq = 2447},
70 { .center_freq = 2452},
71 { .center_freq = 2457},
72 { .center_freq = 2462},
73 { .center_freq = 2467},
74 { .center_freq = 2472},
75 { .center_freq = 2484},
76 };
77
78
79 static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom)
80 {
81 struct adm8211_priv *priv = eeprom->data;
82 u32 reg = ADM8211_CSR_READ(SPR);
83
84 eeprom->reg_data_in = reg & ADM8211_SPR_SDI;
85 eeprom->reg_data_out = reg & ADM8211_SPR_SDO;
86 eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK;
87 eeprom->reg_chip_select = reg & ADM8211_SPR_SCS;
88 }
89
90 static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom)
91 {
92 struct adm8211_priv *priv = eeprom->data;
93 u32 reg = 0x4000 | ADM8211_SPR_SRS;
94
95 if (eeprom->reg_data_in)
96 reg |= ADM8211_SPR_SDI;
97 if (eeprom->reg_data_out)
98 reg |= ADM8211_SPR_SDO;
99 if (eeprom->reg_data_clock)
100 reg |= ADM8211_SPR_SCLK;
101 if (eeprom->reg_chip_select)
102 reg |= ADM8211_SPR_SCS;
103
104 ADM8211_CSR_WRITE(SPR, reg);
105 ADM8211_CSR_READ(SPR); /* eeprom_delay */
106 }
107
108 static int adm8211_read_eeprom(struct ieee80211_hw *dev)
109 {
110 struct adm8211_priv *priv = dev->priv;
111 unsigned int words, i;
112 struct ieee80211_chan_range chan_range;
113 u16 cr49;
114 struct eeprom_93cx6 eeprom = {
115 .data = priv,
116 .register_read = adm8211_eeprom_register_read,
117 .register_write = adm8211_eeprom_register_write
118 };
119
120 if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
121 /* 256 * 16-bit = 512 bytes */
122 eeprom.width = PCI_EEPROM_WIDTH_93C66;
123 words = 256;
124 } else {
125 /* 64 * 16-bit = 128 bytes */
126 eeprom.width = PCI_EEPROM_WIDTH_93C46;
127 words = 64;
128 }
129
130 priv->eeprom_len = words * 2;
131 priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL);
132 if (!priv->eeprom)
133 return -ENOMEM;
134
135 eeprom_93cx6_multiread(&eeprom, 0, (__le16 *)priv->eeprom, words);
136
137 cr49 = le16_to_cpu(priv->eeprom->cr49);
138 priv->rf_type = (cr49 >> 3) & 0x7;
139 switch (priv->rf_type) {
140 case ADM8211_TYPE_INTERSIL:
141 case ADM8211_TYPE_RFMD:
142 case ADM8211_TYPE_MARVEL:
143 case ADM8211_TYPE_AIROHA:
144 case ADM8211_TYPE_ADMTEK:
145 break;
146
147 default:
148 if (priv->pdev->revision < ADM8211_REV_CA)
149 priv->rf_type = ADM8211_TYPE_RFMD;
150 else
151 priv->rf_type = ADM8211_TYPE_AIROHA;
152
153 printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n",
154 pci_name(priv->pdev), (cr49 >> 3) & 0x7);
155 }
156
157 priv->bbp_type = cr49 & 0x7;
158 switch (priv->bbp_type) {
159 case ADM8211_TYPE_INTERSIL:
160 case ADM8211_TYPE_RFMD:
161 case ADM8211_TYPE_MARVEL:
162 case ADM8211_TYPE_AIROHA:
163 case ADM8211_TYPE_ADMTEK:
164 break;
165 default:
166 if (priv->pdev->revision < ADM8211_REV_CA)
167 priv->bbp_type = ADM8211_TYPE_RFMD;
168 else
169 priv->bbp_type = ADM8211_TYPE_ADMTEK;
170
171 printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n",
172 pci_name(priv->pdev), cr49 >> 3);
173 }
174
175 if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) {
176 printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n",
177 pci_name(priv->pdev), priv->eeprom->country_code);
178
179 chan_range = cranges[2];
180 } else
181 chan_range = cranges[priv->eeprom->country_code];
182
183 printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n",
184 pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max);
185
186 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(adm8211_channels));
187
188 memcpy(priv->channels, adm8211_channels, sizeof(priv->channels));
189 priv->band.channels = priv->channels;
190 priv->band.n_channels = ARRAY_SIZE(adm8211_channels);
191 priv->band.bitrates = adm8211_rates;
192 priv->band.n_bitrates = ARRAY_SIZE(adm8211_rates);
193
194 for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++)
195 if (i < chan_range.min || i > chan_range.max)
196 priv->channels[i - 1].flags |= IEEE80211_CHAN_DISABLED;
197
198 switch (priv->eeprom->specific_bbptype) {
199 case ADM8211_BBP_RFMD3000:
200 case ADM8211_BBP_RFMD3002:
201 case ADM8211_BBP_ADM8011:
202 priv->specific_bbptype = priv->eeprom->specific_bbptype;
203 break;
204
205 default:
206 if (priv->pdev->revision < ADM8211_REV_CA)
207 priv->specific_bbptype = ADM8211_BBP_RFMD3000;
208 else
209 priv->specific_bbptype = ADM8211_BBP_ADM8011;
210
211 printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n",
212 pci_name(priv->pdev), priv->eeprom->specific_bbptype);
213 }
214
215 switch (priv->eeprom->specific_rftype) {
216 case ADM8211_RFMD2948:
217 case ADM8211_RFMD2958:
218 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
219 case ADM8211_MAX2820:
220 case ADM8211_AL2210L:
221 priv->transceiver_type = priv->eeprom->specific_rftype;
222 break;
223
224 default:
225 if (priv->pdev->revision == ADM8211_REV_BA)
226 priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER;
227 else if (priv->pdev->revision == ADM8211_REV_CA)
228 priv->transceiver_type = ADM8211_AL2210L;
229 else if (priv->pdev->revision == ADM8211_REV_AB)
230 priv->transceiver_type = ADM8211_RFMD2948;
231
232 printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n",
233 pci_name(priv->pdev), priv->eeprom->specific_rftype);
234
235 break;
236 }
237
238 printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d "
239 "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type,
240 priv->bbp_type, priv->specific_bbptype, priv->transceiver_type);
241
242 return 0;
243 }
244
245 static inline void adm8211_write_sram(struct ieee80211_hw *dev,
246 u32 addr, u32 data)
247 {
248 struct adm8211_priv *priv = dev->priv;
249
250 ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR |
251 (priv->pdev->revision < ADM8211_REV_BA ?
252 0 : ADM8211_WEPCTL_SEL_WEPTABLE ));
253 ADM8211_CSR_READ(WEPCTL);
254 msleep(1);
255
256 ADM8211_CSR_WRITE(WESK, data);
257 ADM8211_CSR_READ(WESK);
258 msleep(1);
259 }
260
261 static void adm8211_write_sram_bytes(struct ieee80211_hw *dev,
262 unsigned int addr, u8 *buf,
263 unsigned int len)
264 {
265 struct adm8211_priv *priv = dev->priv;
266 u32 reg = ADM8211_CSR_READ(WEPCTL);
267 unsigned int i;
268
269 if (priv->pdev->revision < ADM8211_REV_BA) {
270 for (i = 0; i < len; i += 2) {
271 u16 val = buf[i] | (buf[i + 1] << 8);
272 adm8211_write_sram(dev, addr + i / 2, val);
273 }
274 } else {
275 for (i = 0; i < len; i += 4) {
276 u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) |
277 (buf[i + 2] << 16) | (buf[i + 3] << 24);
278 adm8211_write_sram(dev, addr + i / 4, val);
279 }
280 }
281
282 ADM8211_CSR_WRITE(WEPCTL, reg);
283 }
284
285 static void adm8211_clear_sram(struct ieee80211_hw *dev)
286 {
287 struct adm8211_priv *priv = dev->priv;
288 u32 reg = ADM8211_CSR_READ(WEPCTL);
289 unsigned int addr;
290
291 for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++)
292 adm8211_write_sram(dev, addr, 0);
293
294 ADM8211_CSR_WRITE(WEPCTL, reg);
295 }
296
297 static int adm8211_get_stats(struct ieee80211_hw *dev,
298 struct ieee80211_low_level_stats *stats)
299 {
300 struct adm8211_priv *priv = dev->priv;
301
302 memcpy(stats, &priv->stats, sizeof(*stats));
303
304 return 0;
305 }
306
307 static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
308 {
309 struct adm8211_priv *priv = dev->priv;
310 unsigned int dirty_tx;
311
312 spin_lock(&priv->lock);
313
314 for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
315 unsigned int entry = dirty_tx % priv->tx_ring_size;
316 u32 status = le32_to_cpu(priv->tx_ring[entry].status);
317 struct ieee80211_tx_info *txi;
318 struct adm8211_tx_ring_info *info;
319 struct sk_buff *skb;
320
321 if (status & TDES0_CONTROL_OWN ||
322 !(status & TDES0_CONTROL_DONE))
323 break;
324
325 info = &priv->tx_buffers[entry];
326 skb = info->skb;
327 txi = IEEE80211_SKB_CB(skb);
328
329 /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
330
331 pci_unmap_single(priv->pdev, info->mapping,
332 info->skb->len, PCI_DMA_TODEVICE);
333
334 ieee80211_tx_info_clear_status(txi);
335
336 skb_pull(skb, sizeof(struct adm8211_tx_hdr));
337 memcpy(skb_push(skb, info->hdrlen), skb->cb, info->hdrlen);
338 if (!(txi->flags & IEEE80211_TX_CTL_NO_ACK) &&
339 !(status & TDES0_STATUS_ES))
340 txi->flags |= IEEE80211_TX_STAT_ACK;
341
342 ieee80211_tx_status_irqsafe(dev, skb);
343
344 info->skb = NULL;
345 }
346
347 if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2)
348 ieee80211_wake_queue(dev, 0);
349
350 priv->dirty_tx = dirty_tx;
351 spin_unlock(&priv->lock);
352 }
353
354
355 static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
356 {
357 struct adm8211_priv *priv = dev->priv;
358 unsigned int entry = priv->cur_rx % priv->rx_ring_size;
359 u32 status;
360 unsigned int pktlen;
361 struct sk_buff *skb, *newskb;
362 unsigned int limit = priv->rx_ring_size;
363 u8 rssi, rate;
364
365 while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) {
366 if (!limit--)
367 break;
368
369 status = le32_to_cpu(priv->rx_ring[entry].status);
370 rate = (status & RDES0_STATUS_RXDR) >> 12;
371 rssi = le32_to_cpu(priv->rx_ring[entry].length) &
372 RDES1_STATUS_RSSI;
373
374 pktlen = status & RDES0_STATUS_FL;
375 if (pktlen > RX_PKT_SIZE) {
376 if (net_ratelimit())
377 wiphy_debug(dev->wiphy, "frame too long (%d)\n",
378 pktlen);
379 pktlen = RX_PKT_SIZE;
380 }
381
382 if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) {
383 skb = NULL; /* old buffer will be reused */
384 /* TODO: update RX error stats */
385 /* TODO: check RDES0_STATUS_CRC*E */
386 } else if (pktlen < RX_COPY_BREAK) {
387 skb = dev_alloc_skb(pktlen);
388 if (skb) {
389 pci_dma_sync_single_for_cpu(
390 priv->pdev,
391 priv->rx_buffers[entry].mapping,
392 pktlen, PCI_DMA_FROMDEVICE);
393 skb_put_data(skb,
394 skb_tail_pointer(priv->rx_buffers[entry].skb),
395 pktlen);
396 pci_dma_sync_single_for_device(
397 priv->pdev,
398 priv->rx_buffers[entry].mapping,
399 RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
400 }
401 } else {
402 newskb = dev_alloc_skb(RX_PKT_SIZE);
403 if (newskb) {
404 skb = priv->rx_buffers[entry].skb;
405 skb_put(skb, pktlen);
406 pci_unmap_single(
407 priv->pdev,
408 priv->rx_buffers[entry].mapping,
409 RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
410 priv->rx_buffers[entry].skb = newskb;
411 priv->rx_buffers[entry].mapping =
412 pci_map_single(priv->pdev,
413 skb_tail_pointer(newskb),
414 RX_PKT_SIZE,
415 PCI_DMA_FROMDEVICE);
416 if (pci_dma_mapping_error(priv->pdev,
417 priv->rx_buffers[entry].mapping)) {
418 priv->rx_buffers[entry].skb = NULL;
419 dev_kfree_skb(newskb);
420 skb = NULL;
421 /* TODO: update rx dropped stats */
422 }
423 } else {
424 skb = NULL;
425 /* TODO: update rx dropped stats */
426 }
427
428 priv->rx_ring[entry].buffer1 =
429 cpu_to_le32(priv->rx_buffers[entry].mapping);
430 }
431
432 priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN |
433 RDES0_STATUS_SQL);
434 priv->rx_ring[entry].length =
435 cpu_to_le32(RX_PKT_SIZE |
436 (entry == priv->rx_ring_size - 1 ?
437 RDES1_CONTROL_RER : 0));
438
439 if (skb) {
440 struct ieee80211_rx_status rx_status = {0};
441
442 if (priv->pdev->revision < ADM8211_REV_CA)
443 rx_status.signal = rssi;
444 else
445 rx_status.signal = 100 - rssi;
446
447 rx_status.rate_idx = rate;
448
449 rx_status.freq = adm8211_channels[priv->channel - 1].center_freq;
450 rx_status.band = NL80211_BAND_2GHZ;
451
452 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
453 ieee80211_rx_irqsafe(dev, skb);
454 }
455
456 entry = (++priv->cur_rx) % priv->rx_ring_size;
457 }
458
459 /* TODO: check LPC and update stats? */
460 }
461
462
463 static irqreturn_t adm8211_interrupt(int irq, void *dev_id)
464 {
465 #define ADM8211_INT(x) \
466 do { \
467 if (unlikely(stsr & ADM8211_STSR_ ## x)) \
468 wiphy_debug(dev->wiphy, "%s\n", #x); \
469 } while (0)
470
471 struct ieee80211_hw *dev = dev_id;
472 struct adm8211_priv *priv = dev->priv;
473 u32 stsr = ADM8211_CSR_READ(STSR);
474 ADM8211_CSR_WRITE(STSR, stsr);
475 if (stsr == 0xffffffff)
476 return IRQ_HANDLED;
477
478 if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS)))
479 return IRQ_HANDLED;
480
481 if (stsr & ADM8211_STSR_RCI)
482 adm8211_interrupt_rci(dev);
483 if (stsr & ADM8211_STSR_TCI)
484 adm8211_interrupt_tci(dev);
485
486 ADM8211_INT(PCF);
487 ADM8211_INT(BCNTC);
488 ADM8211_INT(GPINT);
489 ADM8211_INT(ATIMTC);
490 ADM8211_INT(TSFTF);
491 ADM8211_INT(TSCZ);
492 ADM8211_INT(SQL);
493 ADM8211_INT(WEPTD);
494 ADM8211_INT(ATIME);
495 ADM8211_INT(TEIS);
496 ADM8211_INT(FBE);
497 ADM8211_INT(REIS);
498 ADM8211_INT(GPTT);
499 ADM8211_INT(RPS);
500 ADM8211_INT(RDU);
501 ADM8211_INT(TUF);
502 ADM8211_INT(TPS);
503
504 return IRQ_HANDLED;
505
506 #undef ADM8211_INT
507 }
508
509 #define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\
510 static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev, \
511 u16 addr, u32 value) { \
512 struct adm8211_priv *priv = dev->priv; \
513 unsigned int i; \
514 u32 reg, bitbuf; \
515 \
516 value &= v_mask; \
517 addr &= a_mask; \
518 bitbuf = (value << v_shift) | (addr << a_shift); \
519 \
520 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1); \
521 ADM8211_CSR_READ(SYNRF); \
522 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0); \
523 ADM8211_CSR_READ(SYNRF); \
524 \
525 if (prewrite) { \
526 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0); \
527 ADM8211_CSR_READ(SYNRF); \
528 } \
529 \
530 for (i = 0; i <= bits; i++) { \
531 if (bitbuf & (1 << (bits - i))) \
532 reg = ADM8211_SYNRF_WRITE_SYNDATA_1; \
533 else \
534 reg = ADM8211_SYNRF_WRITE_SYNDATA_0; \
535 \
536 ADM8211_CSR_WRITE(SYNRF, reg); \
537 ADM8211_CSR_READ(SYNRF); \
538 \
539 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \
540 ADM8211_CSR_READ(SYNRF); \
541 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \
542 ADM8211_CSR_READ(SYNRF); \
543 } \
544 \
545 if (postwrite == 1) { \
546 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0); \
547 ADM8211_CSR_READ(SYNRF); \
548 } \
549 if (postwrite == 2) { \
550 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1); \
551 ADM8211_CSR_READ(SYNRF); \
552 } \
553 \
554 ADM8211_CSR_WRITE(SYNRF, 0); \
555 ADM8211_CSR_READ(SYNRF); \
556 }
557
558 WRITE_SYN(max2820, 0x00FFF, 0, 0x0F, 12, 15, 1, 1)
559 WRITE_SYN(al2210l, 0xFFFFF, 4, 0x0F, 0, 23, 1, 1)
560 WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1)
561 WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F, 0, 21, 0, 2)
562
563 #undef WRITE_SYN
564
565 static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data)
566 {
567 struct adm8211_priv *priv = dev->priv;
568 unsigned int timeout;
569 u32 reg;
570
571 timeout = 10;
572 while (timeout > 0) {
573 reg = ADM8211_CSR_READ(BBPCTL);
574 if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD)))
575 break;
576 timeout--;
577 msleep(2);
578 }
579
580 if (timeout == 0) {
581 wiphy_debug(dev->wiphy,
582 "adm8211_write_bbp(%d,%d) failed prewrite (reg=0x%08x)\n",
583 addr, data, reg);
584 return -ETIMEDOUT;
585 }
586
587 switch (priv->bbp_type) {
588 case ADM8211_TYPE_INTERSIL:
589 reg = ADM8211_BBPCTL_MMISEL; /* three wire interface */
590 break;
591 case ADM8211_TYPE_RFMD:
592 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
593 (0x01 << 18);
594 break;
595 case ADM8211_TYPE_ADMTEK:
596 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
597 (0x05 << 18);
598 break;
599 }
600 reg |= ADM8211_BBPCTL_WR | (addr << 8) | data;
601
602 ADM8211_CSR_WRITE(BBPCTL, reg);
603
604 timeout = 10;
605 while (timeout > 0) {
606 reg = ADM8211_CSR_READ(BBPCTL);
607 if (!(reg & ADM8211_BBPCTL_WR))
608 break;
609 timeout--;
610 msleep(2);
611 }
612
613 if (timeout == 0) {
614 ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
615 ~ADM8211_BBPCTL_WR);
616 wiphy_debug(dev->wiphy,
617 "adm8211_write_bbp(%d,%d) failed postwrite (reg=0x%08x)\n",
618 addr, data, reg);
619 return -ETIMEDOUT;
620 }
621
622 return 0;
623 }
624
625 static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
626 {
627 static const u32 adm8211_rfmd2958_reg5[] =
628 {0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340,
629 0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7};
630 static const u32 adm8211_rfmd2958_reg6[] =
631 {0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000,
632 0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745};
633
634 struct adm8211_priv *priv = dev->priv;
635 u8 ant_power = priv->ant_power > 0x3F ?
636 priv->eeprom->antenna_power[chan - 1] : priv->ant_power;
637 u8 tx_power = priv->tx_power > 0x3F ?
638 priv->eeprom->tx_power[chan - 1] : priv->tx_power;
639 u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ?
640 priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff;
641 u8 lnags_thresh = priv->lnags_threshold == 0xFF ?
642 priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold;
643 u32 reg;
644
645 ADM8211_IDLE();
646
647 /* Program synthesizer to new channel */
648 switch (priv->transceiver_type) {
649 case ADM8211_RFMD2958:
650 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
651 adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007);
652 adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033);
653
654 adm8211_rf_write_syn_rfmd2958(dev, 0x05,
655 adm8211_rfmd2958_reg5[chan - 1]);
656 adm8211_rf_write_syn_rfmd2958(dev, 0x06,
657 adm8211_rfmd2958_reg6[chan - 1]);
658 break;
659
660 case ADM8211_RFMD2948:
661 adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,
662 SI4126_MAIN_XINDIV2);
663 adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
664 SI4126_POWERDOWN_PDIB |
665 SI4126_POWERDOWN_PDRB);
666 adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
667 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,
668 (chan == 14 ?
669 2110 : (2033 + (chan * 5))));
670 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
671 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
672 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
673 break;
674
675 case ADM8211_MAX2820:
676 adm8211_rf_write_syn_max2820(dev, 0x3,
677 (chan == 14 ? 0x054 : (0x7 + (chan * 5))));
678 break;
679
680 case ADM8211_AL2210L:
681 adm8211_rf_write_syn_al2210l(dev, 0x0,
682 (chan == 14 ? 0x229B4 : (0x22967 + (chan * 5))));
683 break;
684
685 default:
686 wiphy_debug(dev->wiphy, "unsupported transceiver type %d\n",
687 priv->transceiver_type);
688 break;
689 }
690
691 /* write BBP regs */
692 if (priv->bbp_type == ADM8211_TYPE_RFMD) {
693
694 /* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */
695 /* TODO: remove if SMC 2635W doesn't need this */
696 if (priv->transceiver_type == ADM8211_RFMD2948) {
697 reg = ADM8211_CSR_READ(GPIO);
698 reg &= 0xfffc0000;
699 reg |= ADM8211_CSR_GPIO_EN0;
700 if (chan != 14)
701 reg |= ADM8211_CSR_GPIO_O0;
702 ADM8211_CSR_WRITE(GPIO, reg);
703 }
704
705 if (priv->transceiver_type == ADM8211_RFMD2958) {
706 /* set PCNT2 */
707 adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100);
708 /* set PCNT1 P_DESIRED/MID_BIAS */
709 reg = le16_to_cpu(priv->eeprom->cr49);
710 reg >>= 13;
711 reg <<= 15;
712 reg |= ant_power << 9;
713 adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg);
714 /* set TXRX TX_GAIN */
715 adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 |
716 (priv->pdev->revision < ADM8211_REV_CA ? tx_power : 0));
717 } else {
718 reg = ADM8211_CSR_READ(PLCPHD);
719 reg &= 0xff00ffff;
720 reg |= tx_power << 18;
721 ADM8211_CSR_WRITE(PLCPHD, reg);
722 }
723
724 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
725 ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
726 ADM8211_CSR_READ(SYNRF);
727 msleep(30);
728
729 /* RF3000 BBP */
730 if (priv->transceiver_type != ADM8211_RFMD2958)
731 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT,
732 tx_power<<2);
733 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff);
734 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh);
735 adm8211_write_bbp(dev, 0x1c, priv->pdev->revision == ADM8211_REV_BA ?
736 priv->eeprom->cr28 : 0);
737 adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
738
739 ADM8211_CSR_WRITE(SYNRF, 0);
740
741 /* Nothing to do for ADMtek BBP */
742 } else if (priv->bbp_type != ADM8211_TYPE_ADMTEK)
743 wiphy_debug(dev->wiphy, "unsupported BBP type %d\n",
744 priv->bbp_type);
745
746 ADM8211_RESTORE();
747
748 /* update current channel for adhoc (and maybe AP mode) */
749 reg = ADM8211_CSR_READ(CAP0);
750 reg &= ~0xF;
751 reg |= chan;
752 ADM8211_CSR_WRITE(CAP0, reg);
753
754 return 0;
755 }
756
757 static void adm8211_update_mode(struct ieee80211_hw *dev)
758 {
759 struct adm8211_priv *priv = dev->priv;
760
761 ADM8211_IDLE();
762
763 priv->soft_rx_crc = 0;
764 switch (priv->mode) {
765 case NL80211_IFTYPE_STATION:
766 priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA);
767 priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR;
768 break;
769 case NL80211_IFTYPE_ADHOC:
770 priv->nar &= ~ADM8211_NAR_PR;
771 priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR;
772
773 /* don't trust the error bits on rev 0x20 and up in adhoc */
774 if (priv->pdev->revision >= ADM8211_REV_BA)
775 priv->soft_rx_crc = 1;
776 break;
777 case NL80211_IFTYPE_MONITOR:
778 priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST);
779 priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR;
780 break;
781 }
782
783 ADM8211_RESTORE();
784 }
785
786 static void adm8211_hw_init_syn(struct ieee80211_hw *dev)
787 {
788 struct adm8211_priv *priv = dev->priv;
789
790 switch (priv->transceiver_type) {
791 case ADM8211_RFMD2958:
792 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
793 /* comments taken from ADMtek vendor driver */
794
795 /* Reset RF2958 after power on */
796 adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000);
797 /* Initialize RF VCO Core Bias to maximum */
798 adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F);
799 /* Initialize IF PLL */
800 adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03);
801 /* Initialize IF PLL Coarse Tuning */
802 adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F);
803 /* Initialize RF PLL */
804 adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403);
805 /* Initialize RF PLL Coarse Tuning */
806 adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F);
807 /* Initialize TX gain and filter BW (R9) */
808 adm8211_rf_write_syn_rfmd2958(dev, 0x09,
809 (priv->transceiver_type == ADM8211_RFMD2958 ?
810 0x10050 : 0x00050));
811 /* Initialize CAL register */
812 adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8);
813 break;
814
815 case ADM8211_MAX2820:
816 adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E);
817 adm8211_rf_write_syn_max2820(dev, 0x2, 0x001);
818 adm8211_rf_write_syn_max2820(dev, 0x3, 0x054);
819 adm8211_rf_write_syn_max2820(dev, 0x4, 0x310);
820 adm8211_rf_write_syn_max2820(dev, 0x5, 0x000);
821 break;
822
823 case ADM8211_AL2210L:
824 adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C);
825 adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB);
826 adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F);
827 adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9);
828 adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280);
829 adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641);
830 adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130);
831 adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000);
832 adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F);
833 adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C);
834 adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000);
835 adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000);
836 break;
837
838 case ADM8211_RFMD2948:
839 default:
840 break;
841 }
842 }
843
844 static int adm8211_hw_init_bbp(struct ieee80211_hw *dev)
845 {
846 struct adm8211_priv *priv = dev->priv;
847 u32 reg;
848
849 /* write addresses */
850 if (priv->bbp_type == ADM8211_TYPE_INTERSIL) {
851 ADM8211_CSR_WRITE(MMIWA, 0x100E0C0A);
852 ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E);
853 ADM8211_CSR_WRITE(MMIRD1, 0x00100000);
854 } else if (priv->bbp_type == ADM8211_TYPE_RFMD ||
855 priv->bbp_type == ADM8211_TYPE_ADMTEK) {
856 /* check specific BBP type */
857 switch (priv->specific_bbptype) {
858 case ADM8211_BBP_RFMD3000:
859 case ADM8211_BBP_RFMD3002:
860 ADM8211_CSR_WRITE(MMIWA, 0x00009101);
861 ADM8211_CSR_WRITE(MMIRD0, 0x00000301);
862 break;
863
864 case ADM8211_BBP_ADM8011:
865 ADM8211_CSR_WRITE(MMIWA, 0x00008903);
866 ADM8211_CSR_WRITE(MMIRD0, 0x00001716);
867
868 reg = ADM8211_CSR_READ(BBPCTL);
869 reg &= ~ADM8211_BBPCTL_TYPE;
870 reg |= 0x5 << 18;
871 ADM8211_CSR_WRITE(BBPCTL, reg);
872 break;
873 }
874
875 switch (priv->pdev->revision) {
876 case ADM8211_REV_CA:
877 if (priv->transceiver_type == ADM8211_RFMD2958 ||
878 priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
879 priv->transceiver_type == ADM8211_RFMD2948)
880 ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22);
881 else if (priv->transceiver_type == ADM8211_MAX2820 ||
882 priv->transceiver_type == ADM8211_AL2210L)
883 ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22);
884 break;
885
886 case ADM8211_REV_BA:
887 reg = ADM8211_CSR_READ(MMIRD1);
888 reg &= 0x0000FFFF;
889 reg |= 0x7e100000;
890 ADM8211_CSR_WRITE(MMIRD1, reg);
891 break;
892
893 case ADM8211_REV_AB:
894 case ADM8211_REV_AF:
895 default:
896 ADM8211_CSR_WRITE(MMIRD1, 0x7e100000);
897 break;
898 }
899
900 /* For RFMD */
901 ADM8211_CSR_WRITE(MACTEST, 0x800);
902 }
903
904 adm8211_hw_init_syn(dev);
905
906 /* Set RF Power control IF pin to PE1+PHYRST# */
907 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
908 ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
909 ADM8211_CSR_READ(SYNRF);
910 msleep(20);
911
912 /* write BBP regs */
913 if (priv->bbp_type == ADM8211_TYPE_RFMD) {
914 /* RF3000 BBP */
915 /* another set:
916 * 11: c8
917 * 14: 14
918 * 15: 50 (chan 1..13; chan 14: d0)
919 * 1c: 00
920 * 1d: 84
921 */
922 adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80);
923 /* antenna selection: diversity */
924 adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80);
925 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74);
926 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38);
927 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40);
928
929 if (priv->eeprom->major_version < 2) {
930 adm8211_write_bbp(dev, 0x1c, 0x00);
931 adm8211_write_bbp(dev, 0x1d, 0x80);
932 } else {
933 if (priv->pdev->revision == ADM8211_REV_BA)
934 adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28);
935 else
936 adm8211_write_bbp(dev, 0x1c, 0x00);
937
938 adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
939 }
940 } else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) {
941 /* reset baseband */
942 adm8211_write_bbp(dev, 0x00, 0xFF);
943 /* antenna selection: diversity */
944 adm8211_write_bbp(dev, 0x07, 0x0A);
945
946 /* TODO: find documentation for this */
947 switch (priv->transceiver_type) {
948 case ADM8211_RFMD2958:
949 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
950 adm8211_write_bbp(dev, 0x00, 0x00);
951 adm8211_write_bbp(dev, 0x01, 0x00);
952 adm8211_write_bbp(dev, 0x02, 0x00);
953 adm8211_write_bbp(dev, 0x03, 0x00);
954 adm8211_write_bbp(dev, 0x06, 0x0f);
955 adm8211_write_bbp(dev, 0x09, 0x00);
956 adm8211_write_bbp(dev, 0x0a, 0x00);
957 adm8211_write_bbp(dev, 0x0b, 0x00);
958 adm8211_write_bbp(dev, 0x0c, 0x00);
959 adm8211_write_bbp(dev, 0x0f, 0xAA);
960 adm8211_write_bbp(dev, 0x10, 0x8c);
961 adm8211_write_bbp(dev, 0x11, 0x43);
962 adm8211_write_bbp(dev, 0x18, 0x40);
963 adm8211_write_bbp(dev, 0x20, 0x23);
964 adm8211_write_bbp(dev, 0x21, 0x02);
965 adm8211_write_bbp(dev, 0x22, 0x28);
966 adm8211_write_bbp(dev, 0x23, 0x30);
967 adm8211_write_bbp(dev, 0x24, 0x2d);
968 adm8211_write_bbp(dev, 0x28, 0x35);
969 adm8211_write_bbp(dev, 0x2a, 0x8c);
970 adm8211_write_bbp(dev, 0x2b, 0x81);
971 adm8211_write_bbp(dev, 0x2c, 0x44);
972 adm8211_write_bbp(dev, 0x2d, 0x0A);
973 adm8211_write_bbp(dev, 0x29, 0x40);
974 adm8211_write_bbp(dev, 0x60, 0x08);
975 adm8211_write_bbp(dev, 0x64, 0x01);
976 break;
977
978 case ADM8211_MAX2820:
979 adm8211_write_bbp(dev, 0x00, 0x00);
980 adm8211_write_bbp(dev, 0x01, 0x00);
981 adm8211_write_bbp(dev, 0x02, 0x00);
982 adm8211_write_bbp(dev, 0x03, 0x00);
983 adm8211_write_bbp(dev, 0x06, 0x0f);
984 adm8211_write_bbp(dev, 0x09, 0x05);
985 adm8211_write_bbp(dev, 0x0a, 0x02);
986 adm8211_write_bbp(dev, 0x0b, 0x00);
987 adm8211_write_bbp(dev, 0x0c, 0x0f);
988 adm8211_write_bbp(dev, 0x0f, 0x55);
989 adm8211_write_bbp(dev, 0x10, 0x8d);
990 adm8211_write_bbp(dev, 0x11, 0x43);
991 adm8211_write_bbp(dev, 0x18, 0x4a);
992 adm8211_write_bbp(dev, 0x20, 0x20);
993 adm8211_write_bbp(dev, 0x21, 0x02);
994 adm8211_write_bbp(dev, 0x22, 0x23);
995 adm8211_write_bbp(dev, 0x23, 0x30);
996 adm8211_write_bbp(dev, 0x24, 0x2d);
997 adm8211_write_bbp(dev, 0x2a, 0x8c);
998 adm8211_write_bbp(dev, 0x2b, 0x81);
999 adm8211_write_bbp(dev, 0x2c, 0x44);
1000 adm8211_write_bbp(dev, 0x29, 0x4a);
1001 adm8211_write_bbp(dev, 0x60, 0x2b);
1002 adm8211_write_bbp(dev, 0x64, 0x01);
1003 break;
1004
1005 case ADM8211_AL2210L:
1006 adm8211_write_bbp(dev, 0x00, 0x00);
1007 adm8211_write_bbp(dev, 0x01, 0x00);
1008 adm8211_write_bbp(dev, 0x02, 0x00);
1009 adm8211_write_bbp(dev, 0x03, 0x00);
1010 adm8211_write_bbp(dev, 0x06, 0x0f);
1011 adm8211_write_bbp(dev, 0x07, 0x05);
1012 adm8211_write_bbp(dev, 0x08, 0x03);
1013 adm8211_write_bbp(dev, 0x09, 0x00);
1014 adm8211_write_bbp(dev, 0x0a, 0x00);
1015 adm8211_write_bbp(dev, 0x0b, 0x00);
1016 adm8211_write_bbp(dev, 0x0c, 0x10);
1017 adm8211_write_bbp(dev, 0x0f, 0x55);
1018 adm8211_write_bbp(dev, 0x10, 0x8d);
1019 adm8211_write_bbp(dev, 0x11, 0x43);
1020 adm8211_write_bbp(dev, 0x18, 0x4a);
1021 adm8211_write_bbp(dev, 0x20, 0x20);
1022 adm8211_write_bbp(dev, 0x21, 0x02);
1023 adm8211_write_bbp(dev, 0x22, 0x23);
1024 adm8211_write_bbp(dev, 0x23, 0x30);
1025 adm8211_write_bbp(dev, 0x24, 0x2d);
1026 adm8211_write_bbp(dev, 0x2a, 0xaa);
1027 adm8211_write_bbp(dev, 0x2b, 0x81);
1028 adm8211_write_bbp(dev, 0x2c, 0x44);
1029 adm8211_write_bbp(dev, 0x29, 0xfa);
1030 adm8211_write_bbp(dev, 0x60, 0x2d);
1031 adm8211_write_bbp(dev, 0x64, 0x01);
1032 break;
1033
1034 case ADM8211_RFMD2948:
1035 break;
1036
1037 default:
1038 wiphy_debug(dev->wiphy, "unsupported transceiver %d\n",
1039 priv->transceiver_type);
1040 break;
1041 }
1042 } else
1043 wiphy_debug(dev->wiphy, "unsupported BBP %d\n", priv->bbp_type);
1044
1045 ADM8211_CSR_WRITE(SYNRF, 0);
1046
1047 /* Set RF CAL control source to MAC control */
1048 reg = ADM8211_CSR_READ(SYNCTL);
1049 reg |= ADM8211_SYNCTL_SELCAL;
1050 ADM8211_CSR_WRITE(SYNCTL, reg);
1051
1052 return 0;
1053 }
1054
1055 /* configures hw beacons/probe responses */
1056 static int adm8211_set_rate(struct ieee80211_hw *dev)
1057 {
1058 struct adm8211_priv *priv = dev->priv;
1059 u32 reg;
1060 int i = 0;
1061 u8 rate_buf[12] = {0};
1062
1063 /* write supported rates */
1064 if (priv->pdev->revision != ADM8211_REV_BA) {
1065 rate_buf[0] = ARRAY_SIZE(adm8211_rates);
1066 for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++)
1067 rate_buf[i + 1] = (adm8211_rates[i].bitrate / 5) | 0x80;
1068 } else {
1069 /* workaround for rev BA specific bug */
1070 rate_buf[0] = 0x04;
1071 rate_buf[1] = 0x82;
1072 rate_buf[2] = 0x04;
1073 rate_buf[3] = 0x0b;
1074 rate_buf[4] = 0x16;
1075 }
1076
1077 adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf,
1078 ARRAY_SIZE(adm8211_rates) + 1);
1079
1080 reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
1081 reg |= 1 << 15; /* short preamble */
1082 reg |= 110 << 24;
1083 ADM8211_CSR_WRITE(PLCPHD, reg);
1084
1085 /* MTMLT = 512 TU (max TX MSDU lifetime)
1086 * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate)
1087 * SRTYLIM = 224 (short retry limit, TX header value is default) */
1088 ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0));
1089
1090 return 0;
1091 }
1092
1093 static void adm8211_hw_init(struct ieee80211_hw *dev)
1094 {
1095 struct adm8211_priv *priv = dev->priv;
1096 u32 reg;
1097 u8 cline;
1098
1099 reg = ADM8211_CSR_READ(PAR);
1100 reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME;
1101 reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL);
1102
1103 if (!pci_set_mwi(priv->pdev)) {
1104 reg |= 0x1 << 24;
1105 pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
1106
1107 switch (cline) {
1108 case 0x8:
1109 reg |= (0x1 << 14);
1110 break;
1111 case 0x10:
1112 reg |= (0x2 << 14);
1113 break;
1114 case 0x20:
1115 reg |= (0x3 << 14);
1116 break;
1117 default:
1118 reg |= (0x0 << 14);
1119 break;
1120 }
1121 }
1122
1123 ADM8211_CSR_WRITE(PAR, reg);
1124
1125 reg = ADM8211_CSR_READ(CSR_TEST1);
1126 reg &= ~(0xF << 28);
1127 reg |= (1 << 28) | (1 << 31);
1128 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1129
1130 /* lose link after 4 lost beacons */
1131 reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE;
1132 ADM8211_CSR_WRITE(WCSR, reg);
1133
1134 /* Disable APM, enable receive FIFO threshold, and set drain receive
1135 * threshold to store-and-forward */
1136 reg = ADM8211_CSR_READ(CMDR);
1137 reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT);
1138 reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF;
1139 ADM8211_CSR_WRITE(CMDR, reg);
1140
1141 adm8211_set_rate(dev);
1142
1143 /* 4-bit values:
1144 * PWR1UP = 8 * 2 ms
1145 * PWR0PAPE = 8 us or 5 us
1146 * PWR1PAPE = 1 us or 3 us
1147 * PWR0TRSW = 5 us
1148 * PWR1TRSW = 12 us
1149 * PWR0PE2 = 13 us
1150 * PWR1PE2 = 1 us
1151 * PWR0TXPE = 8 or 6 */
1152 if (priv->pdev->revision < ADM8211_REV_CA)
1153 ADM8211_CSR_WRITE(TOFS2, 0x8815cd18);
1154 else
1155 ADM8211_CSR_WRITE(TOFS2, 0x8535cd16);
1156
1157 /* Enable store and forward for transmit */
1158 priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB;
1159 ADM8211_CSR_WRITE(NAR, priv->nar);
1160
1161 /* Reset RF */
1162 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO);
1163 ADM8211_CSR_READ(SYNRF);
1164 msleep(10);
1165 ADM8211_CSR_WRITE(SYNRF, 0);
1166 ADM8211_CSR_READ(SYNRF);
1167 msleep(5);
1168
1169 /* Set CFP Max Duration to 0x10 TU */
1170 reg = ADM8211_CSR_READ(CFPP);
1171 reg &= ~(0xffff << 8);
1172 reg |= 0x0010 << 8;
1173 ADM8211_CSR_WRITE(CFPP, reg);
1174
1175 /* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us
1176 * TUCNT = 0x3ff - Tu counter 1024 us */
1177 ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff);
1178
1179 /* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us),
1180 * DIFS=50 us, EIFS=100 us */
1181 if (priv->pdev->revision < ADM8211_REV_CA)
1182 ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) |
1183 (50 << 9) | 100);
1184 else
1185 ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) |
1186 (50 << 9) | 100);
1187
1188 /* PCNT = 1 (MAC idle time awake/sleep, unit S)
1189 * RMRD = 2346 * 8 + 1 us (max RX duration) */
1190 ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769);
1191
1192 /* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */
1193 ADM8211_CSR_WRITE(RSPT, 0xffffff00);
1194
1195 /* Initialize BBP (and SYN) */
1196 adm8211_hw_init_bbp(dev);
1197
1198 /* make sure interrupts are off */
1199 ADM8211_CSR_WRITE(IER, 0);
1200
1201 /* ACK interrupts */
1202 ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
1203
1204 /* Setup WEP (turns it off for now) */
1205 reg = ADM8211_CSR_READ(MACTEST);
1206 reg &= ~(7 << 20);
1207 ADM8211_CSR_WRITE(MACTEST, reg);
1208
1209 reg = ADM8211_CSR_READ(WEPCTL);
1210 reg &= ~ADM8211_WEPCTL_WEPENABLE;
1211 reg |= ADM8211_WEPCTL_WEPRXBYP;
1212 ADM8211_CSR_WRITE(WEPCTL, reg);
1213
1214 /* Clear the missed-packet counter. */
1215 ADM8211_CSR_READ(LPC);
1216 }
1217
1218 static int adm8211_hw_reset(struct ieee80211_hw *dev)
1219 {
1220 struct adm8211_priv *priv = dev->priv;
1221 u32 reg, tmp;
1222 int timeout = 100;
1223
1224 /* Power-on issue */
1225 /* TODO: check if this is necessary */
1226 ADM8211_CSR_WRITE(FRCTL, 0);
1227
1228 /* Reset the chip */
1229 tmp = ADM8211_CSR_READ(PAR);
1230 ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
1231
1232 while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
1233 msleep(50);
1234
1235 if (timeout <= 0)
1236 return -ETIMEDOUT;
1237
1238 ADM8211_CSR_WRITE(PAR, tmp);
1239
1240 if (priv->pdev->revision == ADM8211_REV_BA &&
1241 (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
1242 priv->transceiver_type == ADM8211_RFMD2958)) {
1243 reg = ADM8211_CSR_READ(CSR_TEST1);
1244 reg |= (1 << 4) | (1 << 5);
1245 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1246 } else if (priv->pdev->revision == ADM8211_REV_CA) {
1247 reg = ADM8211_CSR_READ(CSR_TEST1);
1248 reg &= ~((1 << 4) | (1 << 5));
1249 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1250 }
1251
1252 ADM8211_CSR_WRITE(FRCTL, 0);
1253
1254 reg = ADM8211_CSR_READ(CSR_TEST0);
1255 reg |= ADM8211_CSR_TEST0_EPRLD; /* EEPROM Recall */
1256 ADM8211_CSR_WRITE(CSR_TEST0, reg);
1257
1258 adm8211_clear_sram(dev);
1259
1260 return 0;
1261 }
1262
1263 static u64 adm8211_get_tsft(struct ieee80211_hw *dev,
1264 struct ieee80211_vif *vif)
1265 {
1266 struct adm8211_priv *priv = dev->priv;
1267 u32 tsftl;
1268 u64 tsft;
1269
1270 tsftl = ADM8211_CSR_READ(TSFTL);
1271 tsft = ADM8211_CSR_READ(TSFTH);
1272 tsft <<= 32;
1273 tsft |= tsftl;
1274
1275 return tsft;
1276 }
1277
1278 static void adm8211_set_interval(struct ieee80211_hw *dev,
1279 unsigned short bi, unsigned short li)
1280 {
1281 struct adm8211_priv *priv = dev->priv;
1282 u32 reg;
1283
1284 /* BP (beacon interval) = data->beacon_interval
1285 * LI (listen interval) = data->listen_interval (in beacon intervals) */
1286 reg = (bi << 16) | li;
1287 ADM8211_CSR_WRITE(BPLI, reg);
1288 }
1289
1290 static void adm8211_set_bssid(struct ieee80211_hw *dev, const u8 *bssid)
1291 {
1292 struct adm8211_priv *priv = dev->priv;
1293 u32 reg;
1294
1295 ADM8211_CSR_WRITE(BSSID0, le32_to_cpu(*(__le32 *)bssid));
1296 reg = ADM8211_CSR_READ(ABDA1);
1297 reg &= 0x0000ffff;
1298 reg |= (bssid[4] << 16) | (bssid[5] << 24);
1299 ADM8211_CSR_WRITE(ABDA1, reg);
1300 }
1301
1302 static int adm8211_config(struct ieee80211_hw *dev, u32 changed)
1303 {
1304 struct adm8211_priv *priv = dev->priv;
1305 struct ieee80211_conf *conf = &dev->conf;
1306 int channel =
1307 ieee80211_frequency_to_channel(conf->chandef.chan->center_freq);
1308
1309 if (channel != priv->channel) {
1310 priv->channel = channel;
1311 adm8211_rf_set_channel(dev, priv->channel);
1312 }
1313
1314 return 0;
1315 }
1316
1317 static void adm8211_bss_info_changed(struct ieee80211_hw *dev,
1318 struct ieee80211_vif *vif,
1319 struct ieee80211_bss_conf *conf,
1320 u32 changes)
1321 {
1322 struct adm8211_priv *priv = dev->priv;
1323
1324 if (!(changes & BSS_CHANGED_BSSID))
1325 return;
1326
1327 if (!ether_addr_equal(conf->bssid, priv->bssid)) {
1328 adm8211_set_bssid(dev, conf->bssid);
1329 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1330 }
1331 }
1332
1333 static u64 adm8211_prepare_multicast(struct ieee80211_hw *hw,
1334 struct netdev_hw_addr_list *mc_list)
1335 {
1336 unsigned int bit_nr;
1337 u32 mc_filter[2];
1338 struct netdev_hw_addr *ha;
1339
1340 mc_filter[1] = mc_filter[0] = 0;
1341
1342 netdev_hw_addr_list_for_each(ha, mc_list) {
1343 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1344
1345 bit_nr &= 0x3F;
1346 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1347 }
1348
1349 return mc_filter[0] | ((u64)(mc_filter[1]) << 32);
1350 }
1351
1352 static void adm8211_configure_filter(struct ieee80211_hw *dev,
1353 unsigned int changed_flags,
1354 unsigned int *total_flags,
1355 u64 multicast)
1356 {
1357 static const u8 bcast[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1358 struct adm8211_priv *priv = dev->priv;
1359 unsigned int new_flags;
1360 u32 mc_filter[2];
1361
1362 mc_filter[0] = multicast;
1363 mc_filter[1] = multicast >> 32;
1364
1365 new_flags = 0;
1366
1367 if (*total_flags & FIF_ALLMULTI || multicast == ~(0ULL)) {
1368 new_flags |= FIF_ALLMULTI;
1369 priv->nar &= ~ADM8211_NAR_PR;
1370 priv->nar |= ADM8211_NAR_MM;
1371 mc_filter[1] = mc_filter[0] = ~0;
1372 } else {
1373 priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR);
1374 }
1375
1376 ADM8211_IDLE_RX();
1377
1378 ADM8211_CSR_WRITE(MAR0, mc_filter[0]);
1379 ADM8211_CSR_WRITE(MAR1, mc_filter[1]);
1380 ADM8211_CSR_READ(NAR);
1381
1382 if (priv->nar & ADM8211_NAR_PR)
1383 ieee80211_hw_set(dev, RX_INCLUDES_FCS);
1384 else
1385 __clear_bit(IEEE80211_HW_RX_INCLUDES_FCS, dev->flags);
1386
1387 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1388 adm8211_set_bssid(dev, bcast);
1389 else
1390 adm8211_set_bssid(dev, priv->bssid);
1391
1392 ADM8211_RESTORE();
1393
1394 *total_flags = new_flags;
1395 }
1396
1397 static int adm8211_add_interface(struct ieee80211_hw *dev,
1398 struct ieee80211_vif *vif)
1399 {
1400 struct adm8211_priv *priv = dev->priv;
1401 if (priv->mode != NL80211_IFTYPE_MONITOR)
1402 return -EOPNOTSUPP;
1403
1404 switch (vif->type) {
1405 case NL80211_IFTYPE_STATION:
1406 priv->mode = vif->type;
1407 break;
1408 default:
1409 return -EOPNOTSUPP;
1410 }
1411
1412 ADM8211_IDLE();
1413
1414 ADM8211_CSR_WRITE(PAR0, le32_to_cpu(*(__le32 *)vif->addr));
1415 ADM8211_CSR_WRITE(PAR1, le16_to_cpu(*(__le16 *)(vif->addr + 4)));
1416
1417 adm8211_update_mode(dev);
1418
1419 ADM8211_RESTORE();
1420
1421 return 0;
1422 }
1423
1424 static void adm8211_remove_interface(struct ieee80211_hw *dev,
1425 struct ieee80211_vif *vif)
1426 {
1427 struct adm8211_priv *priv = dev->priv;
1428 priv->mode = NL80211_IFTYPE_MONITOR;
1429 }
1430
1431 static int adm8211_init_rings(struct ieee80211_hw *dev)
1432 {
1433 struct adm8211_priv *priv = dev->priv;
1434 struct adm8211_desc *desc = NULL;
1435 struct adm8211_rx_ring_info *rx_info;
1436 struct adm8211_tx_ring_info *tx_info;
1437 unsigned int i;
1438
1439 for (i = 0; i < priv->rx_ring_size; i++) {
1440 desc = &priv->rx_ring[i];
1441 desc->status = 0;
1442 desc->length = cpu_to_le32(RX_PKT_SIZE);
1443 priv->rx_buffers[i].skb = NULL;
1444 }
1445 /* Mark the end of RX ring; hw returns to base address after this
1446 * descriptor */
1447 desc->length |= cpu_to_le32(RDES1_CONTROL_RER);
1448
1449 for (i = 0; i < priv->rx_ring_size; i++) {
1450 desc = &priv->rx_ring[i];
1451 rx_info = &priv->rx_buffers[i];
1452
1453 rx_info->skb = dev_alloc_skb(RX_PKT_SIZE);
1454 if (rx_info->skb == NULL)
1455 break;
1456 rx_info->mapping = pci_map_single(priv->pdev,
1457 skb_tail_pointer(rx_info->skb),
1458 RX_PKT_SIZE,
1459 PCI_DMA_FROMDEVICE);
1460 if (pci_dma_mapping_error(priv->pdev, rx_info->mapping)) {
1461 dev_kfree_skb(rx_info->skb);
1462 rx_info->skb = NULL;
1463 break;
1464 }
1465
1466 desc->buffer1 = cpu_to_le32(rx_info->mapping);
1467 desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL);
1468 }
1469
1470 /* Setup TX ring. TX buffers descriptors will be filled in as needed */
1471 for (i = 0; i < priv->tx_ring_size; i++) {
1472 desc = &priv->tx_ring[i];
1473 tx_info = &priv->tx_buffers[i];
1474
1475 tx_info->skb = NULL;
1476 tx_info->mapping = 0;
1477 desc->status = 0;
1478 }
1479 desc->length = cpu_to_le32(TDES1_CONTROL_TER);
1480
1481 priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0;
1482 ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma);
1483 ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma);
1484
1485 return 0;
1486 }
1487
1488 static void adm8211_free_rings(struct ieee80211_hw *dev)
1489 {
1490 struct adm8211_priv *priv = dev->priv;
1491 unsigned int i;
1492
1493 for (i = 0; i < priv->rx_ring_size; i++) {
1494 if (!priv->rx_buffers[i].skb)
1495 continue;
1496
1497 pci_unmap_single(
1498 priv->pdev,
1499 priv->rx_buffers[i].mapping,
1500 RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
1501
1502 dev_kfree_skb(priv->rx_buffers[i].skb);
1503 }
1504
1505 for (i = 0; i < priv->tx_ring_size; i++) {
1506 if (!priv->tx_buffers[i].skb)
1507 continue;
1508
1509 pci_unmap_single(priv->pdev,
1510 priv->tx_buffers[i].mapping,
1511 priv->tx_buffers[i].skb->len,
1512 PCI_DMA_TODEVICE);
1513
1514 dev_kfree_skb(priv->tx_buffers[i].skb);
1515 }
1516 }
1517
1518 static int adm8211_start(struct ieee80211_hw *dev)
1519 {
1520 struct adm8211_priv *priv = dev->priv;
1521 int retval;
1522
1523 /* Power up MAC and RF chips */
1524 retval = adm8211_hw_reset(dev);
1525 if (retval) {
1526 wiphy_err(dev->wiphy, "hardware reset failed\n");
1527 goto fail;
1528 }
1529
1530 retval = adm8211_init_rings(dev);
1531 if (retval) {
1532 wiphy_err(dev->wiphy, "failed to initialize rings\n");
1533 goto fail;
1534 }
1535
1536 /* Init hardware */
1537 adm8211_hw_init(dev);
1538 adm8211_rf_set_channel(dev, priv->channel);
1539
1540 retval = request_irq(priv->pdev->irq, adm8211_interrupt,
1541 IRQF_SHARED, "adm8211", dev);
1542 if (retval) {
1543 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
1544 goto fail;
1545 }
1546
1547 ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
1548 ADM8211_IER_RCIE | ADM8211_IER_TCIE |
1549 ADM8211_IER_TDUIE | ADM8211_IER_GPTIE);
1550 priv->mode = NL80211_IFTYPE_MONITOR;
1551 adm8211_update_mode(dev);
1552 ADM8211_CSR_WRITE(RDR, 0);
1553
1554 adm8211_set_interval(dev, 100, 10);
1555 return 0;
1556
1557 fail:
1558 return retval;
1559 }
1560
1561 static void adm8211_stop(struct ieee80211_hw *dev)
1562 {
1563 struct adm8211_priv *priv = dev->priv;
1564
1565 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
1566 priv->nar = 0;
1567 ADM8211_CSR_WRITE(NAR, 0);
1568 ADM8211_CSR_WRITE(IER, 0);
1569 ADM8211_CSR_READ(NAR);
1570
1571 free_irq(priv->pdev->irq, dev);
1572
1573 adm8211_free_rings(dev);
1574 }
1575
1576 static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len,
1577 int plcp_signal, int short_preamble)
1578 {
1579 /* Alternative calculation from NetBSD: */
1580
1581 /* IEEE 802.11b durations for DSSS PHY in microseconds */
1582 #define IEEE80211_DUR_DS_LONG_PREAMBLE 144
1583 #define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
1584 #define IEEE80211_DUR_DS_FAST_PLCPHDR 24
1585 #define IEEE80211_DUR_DS_SLOW_PLCPHDR 48
1586 #define IEEE80211_DUR_DS_SLOW_ACK 112
1587 #define IEEE80211_DUR_DS_FAST_ACK 56
1588 #define IEEE80211_DUR_DS_SLOW_CTS 112
1589 #define IEEE80211_DUR_DS_FAST_CTS 56
1590 #define IEEE80211_DUR_DS_SLOT 20
1591 #define IEEE80211_DUR_DS_SIFS 10
1592
1593 int remainder;
1594
1595 *dur = (80 * (24 + payload_len) + plcp_signal - 1)
1596 / plcp_signal;
1597
1598 if (plcp_signal <= PLCP_SIGNAL_2M)
1599 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */
1600 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1601 IEEE80211_DUR_DS_SHORT_PREAMBLE +
1602 IEEE80211_DUR_DS_FAST_PLCPHDR) +
1603 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK;
1604 else
1605 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */
1606 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1607 IEEE80211_DUR_DS_SHORT_PREAMBLE +
1608 IEEE80211_DUR_DS_FAST_PLCPHDR) +
1609 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK;
1610
1611 /* lengthen duration if long preamble */
1612 if (!short_preamble)
1613 *dur += 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE -
1614 IEEE80211_DUR_DS_SHORT_PREAMBLE) +
1615 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR -
1616 IEEE80211_DUR_DS_FAST_PLCPHDR);
1617
1618
1619 *plcp = (80 * len) / plcp_signal;
1620 remainder = (80 * len) % plcp_signal;
1621 if (plcp_signal == PLCP_SIGNAL_11M &&
1622 remainder <= 30 && remainder > 0)
1623 *plcp = (*plcp | 0x8000) + 1;
1624 else if (remainder)
1625 (*plcp)++;
1626 }
1627
1628 /* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
1629 static int adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1630 u16 plcp_signal,
1631 size_t hdrlen)
1632 {
1633 struct adm8211_priv *priv = dev->priv;
1634 unsigned long flags;
1635 dma_addr_t mapping;
1636 unsigned int entry;
1637 u32 flag;
1638
1639 mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1640 PCI_DMA_TODEVICE);
1641 if (pci_dma_mapping_error(priv->pdev, mapping))
1642 return -ENOMEM;
1643
1644 spin_lock_irqsave(&priv->lock, flags);
1645
1646 if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2)
1647 flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1648 else
1649 flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1650
1651 if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2)
1652 ieee80211_stop_queue(dev, 0);
1653
1654 entry = priv->cur_tx % priv->tx_ring_size;
1655
1656 priv->tx_buffers[entry].skb = skb;
1657 priv->tx_buffers[entry].mapping = mapping;
1658 priv->tx_buffers[entry].hdrlen = hdrlen;
1659 priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
1660
1661 if (entry == priv->tx_ring_size - 1)
1662 flag |= TDES1_CONTROL_TER;
1663 priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len);
1664
1665 /* Set TX rate (SIGNAL field in PLCP PPDU format) */
1666 flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */;
1667 priv->tx_ring[entry].status = cpu_to_le32(flag);
1668
1669 priv->cur_tx++;
1670
1671 spin_unlock_irqrestore(&priv->lock, flags);
1672
1673 /* Trigger transmit poll */
1674 ADM8211_CSR_WRITE(TDR, 0);
1675
1676 return 0;
1677 }
1678
1679 /* Put adm8211_tx_hdr on skb and transmit */
1680 static void adm8211_tx(struct ieee80211_hw *dev,
1681 struct ieee80211_tx_control *control,
1682 struct sk_buff *skb)
1683 {
1684 struct adm8211_tx_hdr *txhdr;
1685 size_t payload_len, hdrlen;
1686 int plcp, dur, len, plcp_signal, short_preamble;
1687 struct ieee80211_hdr *hdr;
1688 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1689 struct ieee80211_rate *txrate = ieee80211_get_tx_rate(dev, info);
1690 u8 rc_flags;
1691
1692 rc_flags = info->control.rates[0].flags;
1693 short_preamble = !!(rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1694 plcp_signal = txrate->bitrate;
1695
1696 hdr = (struct ieee80211_hdr *)skb->data;
1697 hdrlen = ieee80211_hdrlen(hdr->frame_control);
1698 memcpy(skb->cb, skb->data, hdrlen);
1699 hdr = (struct ieee80211_hdr *)skb->cb;
1700 skb_pull(skb, hdrlen);
1701 payload_len = skb->len;
1702
1703 txhdr = (struct adm8211_tx_hdr *) skb_push(skb, sizeof(*txhdr));
1704 memset(txhdr, 0, sizeof(*txhdr));
1705 memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN);
1706 txhdr->signal = plcp_signal;
1707 txhdr->frame_body_size = cpu_to_le16(payload_len);
1708 txhdr->frame_control = hdr->frame_control;
1709
1710 len = hdrlen + payload_len + FCS_LEN;
1711
1712 txhdr->frag = cpu_to_le16(0x0FFF);
1713 adm8211_calc_durations(&dur, &plcp, payload_len,
1714 len, plcp_signal, short_preamble);
1715 txhdr->plcp_frag_head_len = cpu_to_le16(plcp);
1716 txhdr->plcp_frag_tail_len = cpu_to_le16(plcp);
1717 txhdr->dur_frag_head = cpu_to_le16(dur);
1718 txhdr->dur_frag_tail = cpu_to_le16(dur);
1719
1720 txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER);
1721
1722 if (short_preamble)
1723 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
1724
1725 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
1726 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
1727
1728 txhdr->retry_limit = info->control.rates[0].count;
1729
1730 if (adm8211_tx_raw(dev, skb, plcp_signal, hdrlen)) {
1731 /* Drop packet */
1732 ieee80211_free_txskb(dev, skb);
1733 }
1734 }
1735
1736 static int adm8211_alloc_rings(struct ieee80211_hw *dev)
1737 {
1738 struct adm8211_priv *priv = dev->priv;
1739 unsigned int ring_size;
1740
1741 priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size +
1742 sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL);
1743 if (!priv->rx_buffers)
1744 return -ENOMEM;
1745
1746 priv->tx_buffers = (void *)priv->rx_buffers +
1747 sizeof(*priv->rx_buffers) * priv->rx_ring_size;
1748
1749 /* Allocate TX/RX descriptors */
1750 ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size +
1751 sizeof(struct adm8211_desc) * priv->tx_ring_size;
1752 priv->rx_ring = pci_alloc_consistent(priv->pdev, ring_size,
1753 &priv->rx_ring_dma);
1754
1755 if (!priv->rx_ring) {
1756 kfree(priv->rx_buffers);
1757 priv->rx_buffers = NULL;
1758 priv->tx_buffers = NULL;
1759 return -ENOMEM;
1760 }
1761
1762 priv->tx_ring = priv->rx_ring + priv->rx_ring_size;
1763 priv->tx_ring_dma = priv->rx_ring_dma +
1764 sizeof(struct adm8211_desc) * priv->rx_ring_size;
1765
1766 return 0;
1767 }
1768
1769 static const struct ieee80211_ops adm8211_ops = {
1770 .tx = adm8211_tx,
1771 .start = adm8211_start,
1772 .stop = adm8211_stop,
1773 .add_interface = adm8211_add_interface,
1774 .remove_interface = adm8211_remove_interface,
1775 .config = adm8211_config,
1776 .bss_info_changed = adm8211_bss_info_changed,
1777 .prepare_multicast = adm8211_prepare_multicast,
1778 .configure_filter = adm8211_configure_filter,
1779 .get_stats = adm8211_get_stats,
1780 .get_tsf = adm8211_get_tsft
1781 };
1782
1783 static int adm8211_probe(struct pci_dev *pdev,
1784 const struct pci_device_id *id)
1785 {
1786 struct ieee80211_hw *dev;
1787 struct adm8211_priv *priv;
1788 unsigned long mem_addr, mem_len;
1789 unsigned int io_addr, io_len;
1790 int err;
1791 u32 reg;
1792 u8 perm_addr[ETH_ALEN];
1793
1794 err = pci_enable_device(pdev);
1795 if (err) {
1796 printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n",
1797 pci_name(pdev));
1798 return err;
1799 }
1800
1801 io_addr = pci_resource_start(pdev, 0);
1802 io_len = pci_resource_len(pdev, 0);
1803 mem_addr = pci_resource_start(pdev, 1);
1804 mem_len = pci_resource_len(pdev, 1);
1805 if (io_len < 256 || mem_len < 1024) {
1806 printk(KERN_ERR "%s (adm8211): Too short PCI resources\n",
1807 pci_name(pdev));
1808 goto err_disable_pdev;
1809 }
1810
1811
1812 /* check signature */
1813 pci_read_config_dword(pdev, 0x80 /* CR32 */, &reg);
1814 if (reg != ADM8211_SIG1 && reg != ADM8211_SIG2) {
1815 printk(KERN_ERR "%s (adm8211): Invalid signature (0x%x)\n",
1816 pci_name(pdev), reg);
1817 goto err_disable_pdev;
1818 }
1819
1820 err = pci_request_regions(pdev, "adm8211");
1821 if (err) {
1822 printk(KERN_ERR "%s (adm8211): Cannot obtain PCI resources\n",
1823 pci_name(pdev));
1824 return err; /* someone else grabbed it? don't disable it */
1825 }
1826
1827 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
1828 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1829 printk(KERN_ERR "%s (adm8211): No suitable DMA available\n",
1830 pci_name(pdev));
1831 goto err_free_reg;
1832 }
1833
1834 pci_set_master(pdev);
1835
1836 dev = ieee80211_alloc_hw(sizeof(*priv), &adm8211_ops);
1837 if (!dev) {
1838 printk(KERN_ERR "%s (adm8211): ieee80211 alloc failed\n",
1839 pci_name(pdev));
1840 err = -ENOMEM;
1841 goto err_free_reg;
1842 }
1843 priv = dev->priv;
1844 priv->pdev = pdev;
1845
1846 spin_lock_init(&priv->lock);
1847
1848 SET_IEEE80211_DEV(dev, &pdev->dev);
1849
1850 pci_set_drvdata(pdev, dev);
1851
1852 priv->map = pci_iomap(pdev, 1, mem_len);
1853 if (!priv->map)
1854 priv->map = pci_iomap(pdev, 0, io_len);
1855
1856 if (!priv->map) {
1857 printk(KERN_ERR "%s (adm8211): Cannot map device memory\n",
1858 pci_name(pdev));
1859 err = -ENOMEM;
1860 goto err_free_dev;
1861 }
1862
1863 priv->rx_ring_size = rx_ring_size;
1864 priv->tx_ring_size = tx_ring_size;
1865
1866 err = adm8211_alloc_rings(dev);
1867 if (err) {
1868 printk(KERN_ERR "%s (adm8211): Cannot allocate TX/RX ring\n",
1869 pci_name(pdev));
1870 goto err_iounmap;
1871 }
1872
1873 *(__le32 *)perm_addr = cpu_to_le32(ADM8211_CSR_READ(PAR0));
1874 *(__le16 *)&perm_addr[4] =
1875 cpu_to_le16(ADM8211_CSR_READ(PAR1) & 0xFFFF);
1876
1877 if (!is_valid_ether_addr(perm_addr)) {
1878 printk(KERN_WARNING "%s (adm8211): Invalid hwaddr in EEPROM!\n",
1879 pci_name(pdev));
1880 eth_random_addr(perm_addr);
1881 }
1882 SET_IEEE80211_PERM_ADDR(dev, perm_addr);
1883
1884 dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr);
1885 /* dev->flags = RX_INCLUDES_FCS in promisc mode */
1886 ieee80211_hw_set(dev, SIGNAL_UNSPEC);
1887 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1888
1889 dev->max_signal = 100; /* FIXME: find better value */
1890
1891 dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */
1892
1893 priv->retry_limit = 3;
1894 priv->ant_power = 0x40;
1895 priv->tx_power = 0x40;
1896 priv->lpf_cutoff = 0xFF;
1897 priv->lnags_threshold = 0xFF;
1898 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
1899
1900 /* Power-on issue. EEPROM won't read correctly without */
1901 if (pdev->revision >= ADM8211_REV_BA) {
1902 ADM8211_CSR_WRITE(FRCTL, 0);
1903 ADM8211_CSR_READ(FRCTL);
1904 ADM8211_CSR_WRITE(FRCTL, 1);
1905 ADM8211_CSR_READ(FRCTL);
1906 msleep(100);
1907 }
1908
1909 err = adm8211_read_eeprom(dev);
1910 if (err) {
1911 printk(KERN_ERR "%s (adm8211): Can't alloc eeprom buffer\n",
1912 pci_name(pdev));
1913 goto err_free_desc;
1914 }
1915
1916 priv->channel = 1;
1917
1918 dev->wiphy->bands[NL80211_BAND_2GHZ] = &priv->band;
1919
1920 wiphy_ext_feature_set(dev->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
1921
1922 err = ieee80211_register_hw(dev);
1923 if (err) {
1924 printk(KERN_ERR "%s (adm8211): Cannot register device\n",
1925 pci_name(pdev));
1926 goto err_free_eeprom;
1927 }
1928
1929 wiphy_info(dev->wiphy, "hwaddr %pM, Rev 0x%02x\n",
1930 dev->wiphy->perm_addr, pdev->revision);
1931
1932 return 0;
1933
1934 err_free_eeprom:
1935 kfree(priv->eeprom);
1936
1937 err_free_desc:
1938 pci_free_consistent(pdev,
1939 sizeof(struct adm8211_desc) * priv->rx_ring_size +
1940 sizeof(struct adm8211_desc) * priv->tx_ring_size,
1941 priv->rx_ring, priv->rx_ring_dma);
1942 kfree(priv->rx_buffers);
1943
1944 err_iounmap:
1945 pci_iounmap(pdev, priv->map);
1946
1947 err_free_dev:
1948 ieee80211_free_hw(dev);
1949
1950 err_free_reg:
1951 pci_release_regions(pdev);
1952
1953 err_disable_pdev:
1954 pci_disable_device(pdev);
1955 return err;
1956 }
1957
1958
1959 static void adm8211_remove(struct pci_dev *pdev)
1960 {
1961 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1962 struct adm8211_priv *priv;
1963
1964 if (!dev)
1965 return;
1966
1967 ieee80211_unregister_hw(dev);
1968
1969 priv = dev->priv;
1970
1971 pci_free_consistent(pdev,
1972 sizeof(struct adm8211_desc) * priv->rx_ring_size +
1973 sizeof(struct adm8211_desc) * priv->tx_ring_size,
1974 priv->rx_ring, priv->rx_ring_dma);
1975
1976 kfree(priv->rx_buffers);
1977 kfree(priv->eeprom);
1978 pci_iounmap(pdev, priv->map);
1979 pci_release_regions(pdev);
1980 pci_disable_device(pdev);
1981 ieee80211_free_hw(dev);
1982 }
1983
1984
1985 #ifdef CONFIG_PM
1986 static int adm8211_suspend(struct pci_dev *pdev, pm_message_t state)
1987 {
1988 pci_save_state(pdev);
1989 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1990 return 0;
1991 }
1992
1993 static int adm8211_resume(struct pci_dev *pdev)
1994 {
1995 pci_set_power_state(pdev, PCI_D0);
1996 pci_restore_state(pdev);
1997 return 0;
1998 }
1999 #endif /* CONFIG_PM */
2000
2001
2002 MODULE_DEVICE_TABLE(pci, adm8211_pci_id_table);
2003
2004 /* TODO: implement enable_wake */
2005 static struct pci_driver adm8211_driver = {
2006 .name = "adm8211",
2007 .id_table = adm8211_pci_id_table,
2008 .probe = adm8211_probe,
2009 .remove = adm8211_remove,
2010 #ifdef CONFIG_PM
2011 .suspend = adm8211_suspend,
2012 .resume = adm8211_resume,
2013 #endif /* CONFIG_PM */
2014 };
2015
2016 module_pci_driver(adm8211_driver);