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KVM: x86: remove code for lazy FPU handling
[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31 #include "pmu.h"
32 #include "hyperv.h"
33
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
37 #include <linux/fs.h>
38 #include <linux/vmalloc.h>
39 #include <linux/export.h>
40 #include <linux/moduleparam.h>
41 #include <linux/mman.h>
42 #include <linux/highmem.h>
43 #include <linux/iommu.h>
44 #include <linux/intel-iommu.h>
45 #include <linux/cpufreq.h>
46 #include <linux/user-return-notifier.h>
47 #include <linux/srcu.h>
48 #include <linux/slab.h>
49 #include <linux/perf_event.h>
50 #include <linux/uaccess.h>
51 #include <linux/hash.h>
52 #include <linux/pci.h>
53 #include <linux/timekeeper_internal.h>
54 #include <linux/pvclock_gtod.h>
55 #include <linux/kvm_irqfd.h>
56 #include <linux/irqbypass.h>
57 #include <trace/events/kvm.h>
58
59 #include <asm/debugreg.h>
60 #include <asm/msr.h>
61 #include <asm/desc.h>
62 #include <asm/mce.h>
63 #include <linux/kernel_stat.h>
64 #include <asm/fpu/internal.h> /* Ugh! */
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67 #include <asm/irq_remapping.h>
68
69 #define CREATE_TRACE_POINTS
70 #include "trace.h"
71
72 #define MAX_IO_MSRS 256
73 #define KVM_MAX_MCE_BANKS 32
74 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
75 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
76
77 #define emul_to_vcpu(ctxt) \
78 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
79
80 /* EFER defaults:
81 * - enable syscall per default because its emulated by KVM
82 * - enable LME and LMA per default on 64 bit KVM
83 */
84 #ifdef CONFIG_X86_64
85 static
86 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
87 #else
88 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
89 #endif
90
91 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
92 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
93
94 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
95 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
96
97 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
98 static void process_nmi(struct kvm_vcpu *vcpu);
99 static void enter_smm(struct kvm_vcpu *vcpu);
100 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
101
102 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
103 EXPORT_SYMBOL_GPL(kvm_x86_ops);
104
105 static bool __read_mostly ignore_msrs = 0;
106 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
107
108 unsigned int min_timer_period_us = 500;
109 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
110
111 static bool __read_mostly kvmclock_periodic_sync = true;
112 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
113
114 bool __read_mostly kvm_has_tsc_control;
115 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
116 u32 __read_mostly kvm_max_guest_tsc_khz;
117 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
118 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
119 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
120 u64 __read_mostly kvm_max_tsc_scaling_ratio;
121 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
122 u64 __read_mostly kvm_default_tsc_scaling_ratio;
123 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
124
125 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
126 static u32 __read_mostly tsc_tolerance_ppm = 250;
127 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
128
129 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
130 unsigned int __read_mostly lapic_timer_advance_ns = 0;
131 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
132
133 static bool __read_mostly vector_hashing = true;
134 module_param(vector_hashing, bool, S_IRUGO);
135
136 static bool __read_mostly backwards_tsc_observed = false;
137
138 #define KVM_NR_SHARED_MSRS 16
139
140 struct kvm_shared_msrs_global {
141 int nr;
142 u32 msrs[KVM_NR_SHARED_MSRS];
143 };
144
145 struct kvm_shared_msrs {
146 struct user_return_notifier urn;
147 bool registered;
148 struct kvm_shared_msr_values {
149 u64 host;
150 u64 curr;
151 } values[KVM_NR_SHARED_MSRS];
152 };
153
154 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
155 static struct kvm_shared_msrs __percpu *shared_msrs;
156
157 struct kvm_stats_debugfs_item debugfs_entries[] = {
158 { "pf_fixed", VCPU_STAT(pf_fixed) },
159 { "pf_guest", VCPU_STAT(pf_guest) },
160 { "tlb_flush", VCPU_STAT(tlb_flush) },
161 { "invlpg", VCPU_STAT(invlpg) },
162 { "exits", VCPU_STAT(exits) },
163 { "io_exits", VCPU_STAT(io_exits) },
164 { "mmio_exits", VCPU_STAT(mmio_exits) },
165 { "signal_exits", VCPU_STAT(signal_exits) },
166 { "irq_window", VCPU_STAT(irq_window_exits) },
167 { "nmi_window", VCPU_STAT(nmi_window_exits) },
168 { "halt_exits", VCPU_STAT(halt_exits) },
169 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
170 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
171 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
172 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
173 { "hypercalls", VCPU_STAT(hypercalls) },
174 { "request_irq", VCPU_STAT(request_irq_exits) },
175 { "irq_exits", VCPU_STAT(irq_exits) },
176 { "host_state_reload", VCPU_STAT(host_state_reload) },
177 { "efer_reload", VCPU_STAT(efer_reload) },
178 { "fpu_reload", VCPU_STAT(fpu_reload) },
179 { "insn_emulation", VCPU_STAT(insn_emulation) },
180 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
181 { "irq_injections", VCPU_STAT(irq_injections) },
182 { "nmi_injections", VCPU_STAT(nmi_injections) },
183 { "req_event", VCPU_STAT(req_event) },
184 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
185 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
186 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
187 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
188 { "mmu_flooded", VM_STAT(mmu_flooded) },
189 { "mmu_recycled", VM_STAT(mmu_recycled) },
190 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
191 { "mmu_unsync", VM_STAT(mmu_unsync) },
192 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
193 { "largepages", VM_STAT(lpages) },
194 { "max_mmu_page_hash_collisions",
195 VM_STAT(max_mmu_page_hash_collisions) },
196 { NULL }
197 };
198
199 u64 __read_mostly host_xcr0;
200
201 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
202
203 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
204 {
205 int i;
206 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
207 vcpu->arch.apf.gfns[i] = ~0;
208 }
209
210 static void kvm_on_user_return(struct user_return_notifier *urn)
211 {
212 unsigned slot;
213 struct kvm_shared_msrs *locals
214 = container_of(urn, struct kvm_shared_msrs, urn);
215 struct kvm_shared_msr_values *values;
216 unsigned long flags;
217
218 /*
219 * Disabling irqs at this point since the following code could be
220 * interrupted and executed through kvm_arch_hardware_disable()
221 */
222 local_irq_save(flags);
223 if (locals->registered) {
224 locals->registered = false;
225 user_return_notifier_unregister(urn);
226 }
227 local_irq_restore(flags);
228 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
229 values = &locals->values[slot];
230 if (values->host != values->curr) {
231 wrmsrl(shared_msrs_global.msrs[slot], values->host);
232 values->curr = values->host;
233 }
234 }
235 }
236
237 static void shared_msr_update(unsigned slot, u32 msr)
238 {
239 u64 value;
240 unsigned int cpu = smp_processor_id();
241 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
242
243 /* only read, and nobody should modify it at this time,
244 * so don't need lock */
245 if (slot >= shared_msrs_global.nr) {
246 printk(KERN_ERR "kvm: invalid MSR slot!");
247 return;
248 }
249 rdmsrl_safe(msr, &value);
250 smsr->values[slot].host = value;
251 smsr->values[slot].curr = value;
252 }
253
254 void kvm_define_shared_msr(unsigned slot, u32 msr)
255 {
256 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
257 shared_msrs_global.msrs[slot] = msr;
258 if (slot >= shared_msrs_global.nr)
259 shared_msrs_global.nr = slot + 1;
260 }
261 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
262
263 static void kvm_shared_msr_cpu_online(void)
264 {
265 unsigned i;
266
267 for (i = 0; i < shared_msrs_global.nr; ++i)
268 shared_msr_update(i, shared_msrs_global.msrs[i]);
269 }
270
271 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
272 {
273 unsigned int cpu = smp_processor_id();
274 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
275 int err;
276
277 if (((value ^ smsr->values[slot].curr) & mask) == 0)
278 return 0;
279 smsr->values[slot].curr = value;
280 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
281 if (err)
282 return 1;
283
284 if (!smsr->registered) {
285 smsr->urn.on_user_return = kvm_on_user_return;
286 user_return_notifier_register(&smsr->urn);
287 smsr->registered = true;
288 }
289 return 0;
290 }
291 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
292
293 static void drop_user_return_notifiers(void)
294 {
295 unsigned int cpu = smp_processor_id();
296 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
297
298 if (smsr->registered)
299 kvm_on_user_return(&smsr->urn);
300 }
301
302 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
303 {
304 return vcpu->arch.apic_base;
305 }
306 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
307
308 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
309 {
310 u64 old_state = vcpu->arch.apic_base &
311 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
312 u64 new_state = msr_info->data &
313 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
314 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
315 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
316
317 if (!msr_info->host_initiated &&
318 ((msr_info->data & reserved_bits) != 0 ||
319 new_state == X2APIC_ENABLE ||
320 (new_state == MSR_IA32_APICBASE_ENABLE &&
321 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
322 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
323 old_state == 0)))
324 return 1;
325
326 kvm_lapic_set_base(vcpu, msr_info->data);
327 return 0;
328 }
329 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
330
331 asmlinkage __visible void kvm_spurious_fault(void)
332 {
333 /* Fault while not rebooting. We want the trace. */
334 BUG();
335 }
336 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
337
338 #define EXCPT_BENIGN 0
339 #define EXCPT_CONTRIBUTORY 1
340 #define EXCPT_PF 2
341
342 static int exception_class(int vector)
343 {
344 switch (vector) {
345 case PF_VECTOR:
346 return EXCPT_PF;
347 case DE_VECTOR:
348 case TS_VECTOR:
349 case NP_VECTOR:
350 case SS_VECTOR:
351 case GP_VECTOR:
352 return EXCPT_CONTRIBUTORY;
353 default:
354 break;
355 }
356 return EXCPT_BENIGN;
357 }
358
359 #define EXCPT_FAULT 0
360 #define EXCPT_TRAP 1
361 #define EXCPT_ABORT 2
362 #define EXCPT_INTERRUPT 3
363
364 static int exception_type(int vector)
365 {
366 unsigned int mask;
367
368 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
369 return EXCPT_INTERRUPT;
370
371 mask = 1 << vector;
372
373 /* #DB is trap, as instruction watchpoints are handled elsewhere */
374 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
375 return EXCPT_TRAP;
376
377 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
378 return EXCPT_ABORT;
379
380 /* Reserved exceptions will result in fault */
381 return EXCPT_FAULT;
382 }
383
384 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
385 unsigned nr, bool has_error, u32 error_code,
386 bool reinject)
387 {
388 u32 prev_nr;
389 int class1, class2;
390
391 kvm_make_request(KVM_REQ_EVENT, vcpu);
392
393 if (!vcpu->arch.exception.pending) {
394 queue:
395 if (has_error && !is_protmode(vcpu))
396 has_error = false;
397 vcpu->arch.exception.pending = true;
398 vcpu->arch.exception.has_error_code = has_error;
399 vcpu->arch.exception.nr = nr;
400 vcpu->arch.exception.error_code = error_code;
401 vcpu->arch.exception.reinject = reinject;
402 return;
403 }
404
405 /* to check exception */
406 prev_nr = vcpu->arch.exception.nr;
407 if (prev_nr == DF_VECTOR) {
408 /* triple fault -> shutdown */
409 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
410 return;
411 }
412 class1 = exception_class(prev_nr);
413 class2 = exception_class(nr);
414 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
415 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
416 /* generate double fault per SDM Table 5-5 */
417 vcpu->arch.exception.pending = true;
418 vcpu->arch.exception.has_error_code = true;
419 vcpu->arch.exception.nr = DF_VECTOR;
420 vcpu->arch.exception.error_code = 0;
421 } else
422 /* replace previous exception with a new one in a hope
423 that instruction re-execution will regenerate lost
424 exception */
425 goto queue;
426 }
427
428 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
429 {
430 kvm_multiple_exception(vcpu, nr, false, 0, false);
431 }
432 EXPORT_SYMBOL_GPL(kvm_queue_exception);
433
434 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
435 {
436 kvm_multiple_exception(vcpu, nr, false, 0, true);
437 }
438 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
439
440 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
441 {
442 if (err)
443 kvm_inject_gp(vcpu, 0);
444 else
445 return kvm_skip_emulated_instruction(vcpu);
446
447 return 1;
448 }
449 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
450
451 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
452 {
453 ++vcpu->stat.pf_guest;
454 vcpu->arch.cr2 = fault->address;
455 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
456 }
457 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
458
459 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
460 {
461 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
462 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
463 else
464 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
465
466 return fault->nested_page_fault;
467 }
468
469 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
470 {
471 atomic_inc(&vcpu->arch.nmi_queued);
472 kvm_make_request(KVM_REQ_NMI, vcpu);
473 }
474 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
475
476 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
477 {
478 kvm_multiple_exception(vcpu, nr, true, error_code, false);
479 }
480 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
481
482 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
483 {
484 kvm_multiple_exception(vcpu, nr, true, error_code, true);
485 }
486 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
487
488 /*
489 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
490 * a #GP and return false.
491 */
492 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
493 {
494 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
495 return true;
496 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
497 return false;
498 }
499 EXPORT_SYMBOL_GPL(kvm_require_cpl);
500
501 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
502 {
503 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
504 return true;
505
506 kvm_queue_exception(vcpu, UD_VECTOR);
507 return false;
508 }
509 EXPORT_SYMBOL_GPL(kvm_require_dr);
510
511 /*
512 * This function will be used to read from the physical memory of the currently
513 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
514 * can read from guest physical or from the guest's guest physical memory.
515 */
516 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
517 gfn_t ngfn, void *data, int offset, int len,
518 u32 access)
519 {
520 struct x86_exception exception;
521 gfn_t real_gfn;
522 gpa_t ngpa;
523
524 ngpa = gfn_to_gpa(ngfn);
525 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
526 if (real_gfn == UNMAPPED_GVA)
527 return -EFAULT;
528
529 real_gfn = gpa_to_gfn(real_gfn);
530
531 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
532 }
533 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
534
535 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
536 void *data, int offset, int len, u32 access)
537 {
538 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
539 data, offset, len, access);
540 }
541
542 /*
543 * Load the pae pdptrs. Return true is they are all valid.
544 */
545 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
546 {
547 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
548 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
549 int i;
550 int ret;
551 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
552
553 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
554 offset * sizeof(u64), sizeof(pdpte),
555 PFERR_USER_MASK|PFERR_WRITE_MASK);
556 if (ret < 0) {
557 ret = 0;
558 goto out;
559 }
560 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
561 if ((pdpte[i] & PT_PRESENT_MASK) &&
562 (pdpte[i] &
563 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
564 ret = 0;
565 goto out;
566 }
567 }
568 ret = 1;
569
570 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
571 __set_bit(VCPU_EXREG_PDPTR,
572 (unsigned long *)&vcpu->arch.regs_avail);
573 __set_bit(VCPU_EXREG_PDPTR,
574 (unsigned long *)&vcpu->arch.regs_dirty);
575 out:
576
577 return ret;
578 }
579 EXPORT_SYMBOL_GPL(load_pdptrs);
580
581 bool pdptrs_changed(struct kvm_vcpu *vcpu)
582 {
583 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
584 bool changed = true;
585 int offset;
586 gfn_t gfn;
587 int r;
588
589 if (is_long_mode(vcpu) || !is_pae(vcpu))
590 return false;
591
592 if (!test_bit(VCPU_EXREG_PDPTR,
593 (unsigned long *)&vcpu->arch.regs_avail))
594 return true;
595
596 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
597 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
598 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
599 PFERR_USER_MASK | PFERR_WRITE_MASK);
600 if (r < 0)
601 goto out;
602 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
603 out:
604
605 return changed;
606 }
607 EXPORT_SYMBOL_GPL(pdptrs_changed);
608
609 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
610 {
611 unsigned long old_cr0 = kvm_read_cr0(vcpu);
612 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
613
614 cr0 |= X86_CR0_ET;
615
616 #ifdef CONFIG_X86_64
617 if (cr0 & 0xffffffff00000000UL)
618 return 1;
619 #endif
620
621 cr0 &= ~CR0_RESERVED_BITS;
622
623 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
624 return 1;
625
626 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
627 return 1;
628
629 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
630 #ifdef CONFIG_X86_64
631 if ((vcpu->arch.efer & EFER_LME)) {
632 int cs_db, cs_l;
633
634 if (!is_pae(vcpu))
635 return 1;
636 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
637 if (cs_l)
638 return 1;
639 } else
640 #endif
641 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
642 kvm_read_cr3(vcpu)))
643 return 1;
644 }
645
646 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
647 return 1;
648
649 kvm_x86_ops->set_cr0(vcpu, cr0);
650
651 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
652 kvm_clear_async_pf_completion_queue(vcpu);
653 kvm_async_pf_hash_reset(vcpu);
654 }
655
656 if ((cr0 ^ old_cr0) & update_bits)
657 kvm_mmu_reset_context(vcpu);
658
659 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
660 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
661 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
662 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
663
664 return 0;
665 }
666 EXPORT_SYMBOL_GPL(kvm_set_cr0);
667
668 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
669 {
670 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
671 }
672 EXPORT_SYMBOL_GPL(kvm_lmsw);
673
674 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
675 {
676 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
677 !vcpu->guest_xcr0_loaded) {
678 /* kvm_set_xcr() also depends on this */
679 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
680 vcpu->guest_xcr0_loaded = 1;
681 }
682 }
683
684 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
685 {
686 if (vcpu->guest_xcr0_loaded) {
687 if (vcpu->arch.xcr0 != host_xcr0)
688 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
689 vcpu->guest_xcr0_loaded = 0;
690 }
691 }
692
693 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
694 {
695 u64 xcr0 = xcr;
696 u64 old_xcr0 = vcpu->arch.xcr0;
697 u64 valid_bits;
698
699 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
700 if (index != XCR_XFEATURE_ENABLED_MASK)
701 return 1;
702 if (!(xcr0 & XFEATURE_MASK_FP))
703 return 1;
704 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
705 return 1;
706
707 /*
708 * Do not allow the guest to set bits that we do not support
709 * saving. However, xcr0 bit 0 is always set, even if the
710 * emulated CPU does not support XSAVE (see fx_init).
711 */
712 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
713 if (xcr0 & ~valid_bits)
714 return 1;
715
716 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
717 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
718 return 1;
719
720 if (xcr0 & XFEATURE_MASK_AVX512) {
721 if (!(xcr0 & XFEATURE_MASK_YMM))
722 return 1;
723 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
724 return 1;
725 }
726 vcpu->arch.xcr0 = xcr0;
727
728 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
729 kvm_update_cpuid(vcpu);
730 return 0;
731 }
732
733 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
734 {
735 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
736 __kvm_set_xcr(vcpu, index, xcr)) {
737 kvm_inject_gp(vcpu, 0);
738 return 1;
739 }
740 return 0;
741 }
742 EXPORT_SYMBOL_GPL(kvm_set_xcr);
743
744 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
745 {
746 unsigned long old_cr4 = kvm_read_cr4(vcpu);
747 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
748 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
749
750 if (cr4 & CR4_RESERVED_BITS)
751 return 1;
752
753 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
754 return 1;
755
756 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
757 return 1;
758
759 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
760 return 1;
761
762 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
763 return 1;
764
765 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
766 return 1;
767
768 if (is_long_mode(vcpu)) {
769 if (!(cr4 & X86_CR4_PAE))
770 return 1;
771 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
772 && ((cr4 ^ old_cr4) & pdptr_bits)
773 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
774 kvm_read_cr3(vcpu)))
775 return 1;
776
777 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
778 if (!guest_cpuid_has_pcid(vcpu))
779 return 1;
780
781 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
782 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
783 return 1;
784 }
785
786 if (kvm_x86_ops->set_cr4(vcpu, cr4))
787 return 1;
788
789 if (((cr4 ^ old_cr4) & pdptr_bits) ||
790 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
791 kvm_mmu_reset_context(vcpu);
792
793 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
794 kvm_update_cpuid(vcpu);
795
796 return 0;
797 }
798 EXPORT_SYMBOL_GPL(kvm_set_cr4);
799
800 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
801 {
802 #ifdef CONFIG_X86_64
803 cr3 &= ~CR3_PCID_INVD;
804 #endif
805
806 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
807 kvm_mmu_sync_roots(vcpu);
808 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
809 return 0;
810 }
811
812 if (is_long_mode(vcpu)) {
813 if (cr3 & CR3_L_MODE_RESERVED_BITS)
814 return 1;
815 } else if (is_pae(vcpu) && is_paging(vcpu) &&
816 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
817 return 1;
818
819 vcpu->arch.cr3 = cr3;
820 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
821 kvm_mmu_new_cr3(vcpu);
822 return 0;
823 }
824 EXPORT_SYMBOL_GPL(kvm_set_cr3);
825
826 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
827 {
828 if (cr8 & CR8_RESERVED_BITS)
829 return 1;
830 if (lapic_in_kernel(vcpu))
831 kvm_lapic_set_tpr(vcpu, cr8);
832 else
833 vcpu->arch.cr8 = cr8;
834 return 0;
835 }
836 EXPORT_SYMBOL_GPL(kvm_set_cr8);
837
838 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
839 {
840 if (lapic_in_kernel(vcpu))
841 return kvm_lapic_get_cr8(vcpu);
842 else
843 return vcpu->arch.cr8;
844 }
845 EXPORT_SYMBOL_GPL(kvm_get_cr8);
846
847 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
848 {
849 int i;
850
851 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
852 for (i = 0; i < KVM_NR_DB_REGS; i++)
853 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
854 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
855 }
856 }
857
858 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
859 {
860 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
861 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
862 }
863
864 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
865 {
866 unsigned long dr7;
867
868 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
869 dr7 = vcpu->arch.guest_debug_dr7;
870 else
871 dr7 = vcpu->arch.dr7;
872 kvm_x86_ops->set_dr7(vcpu, dr7);
873 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
874 if (dr7 & DR7_BP_EN_MASK)
875 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
876 }
877
878 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
879 {
880 u64 fixed = DR6_FIXED_1;
881
882 if (!guest_cpuid_has_rtm(vcpu))
883 fixed |= DR6_RTM;
884 return fixed;
885 }
886
887 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
888 {
889 switch (dr) {
890 case 0 ... 3:
891 vcpu->arch.db[dr] = val;
892 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
893 vcpu->arch.eff_db[dr] = val;
894 break;
895 case 4:
896 /* fall through */
897 case 6:
898 if (val & 0xffffffff00000000ULL)
899 return -1; /* #GP */
900 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
901 kvm_update_dr6(vcpu);
902 break;
903 case 5:
904 /* fall through */
905 default: /* 7 */
906 if (val & 0xffffffff00000000ULL)
907 return -1; /* #GP */
908 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
909 kvm_update_dr7(vcpu);
910 break;
911 }
912
913 return 0;
914 }
915
916 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
917 {
918 if (__kvm_set_dr(vcpu, dr, val)) {
919 kvm_inject_gp(vcpu, 0);
920 return 1;
921 }
922 return 0;
923 }
924 EXPORT_SYMBOL_GPL(kvm_set_dr);
925
926 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
927 {
928 switch (dr) {
929 case 0 ... 3:
930 *val = vcpu->arch.db[dr];
931 break;
932 case 4:
933 /* fall through */
934 case 6:
935 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
936 *val = vcpu->arch.dr6;
937 else
938 *val = kvm_x86_ops->get_dr6(vcpu);
939 break;
940 case 5:
941 /* fall through */
942 default: /* 7 */
943 *val = vcpu->arch.dr7;
944 break;
945 }
946 return 0;
947 }
948 EXPORT_SYMBOL_GPL(kvm_get_dr);
949
950 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
951 {
952 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
953 u64 data;
954 int err;
955
956 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
957 if (err)
958 return err;
959 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
960 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
961 return err;
962 }
963 EXPORT_SYMBOL_GPL(kvm_rdpmc);
964
965 /*
966 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
967 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
968 *
969 * This list is modified at module load time to reflect the
970 * capabilities of the host cpu. This capabilities test skips MSRs that are
971 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
972 * may depend on host virtualization features rather than host cpu features.
973 */
974
975 static u32 msrs_to_save[] = {
976 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
977 MSR_STAR,
978 #ifdef CONFIG_X86_64
979 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
980 #endif
981 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
982 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
983 };
984
985 static unsigned num_msrs_to_save;
986
987 static u32 emulated_msrs[] = {
988 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
989 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
990 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
991 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
992 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
993 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
994 HV_X64_MSR_RESET,
995 HV_X64_MSR_VP_INDEX,
996 HV_X64_MSR_VP_RUNTIME,
997 HV_X64_MSR_SCONTROL,
998 HV_X64_MSR_STIMER0_CONFIG,
999 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1000 MSR_KVM_PV_EOI_EN,
1001
1002 MSR_IA32_TSC_ADJUST,
1003 MSR_IA32_TSCDEADLINE,
1004 MSR_IA32_MISC_ENABLE,
1005 MSR_IA32_MCG_STATUS,
1006 MSR_IA32_MCG_CTL,
1007 MSR_IA32_MCG_EXT_CTL,
1008 MSR_IA32_SMBASE,
1009 };
1010
1011 static unsigned num_emulated_msrs;
1012
1013 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1014 {
1015 if (efer & efer_reserved_bits)
1016 return false;
1017
1018 if (efer & EFER_FFXSR) {
1019 struct kvm_cpuid_entry2 *feat;
1020
1021 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1022 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
1023 return false;
1024 }
1025
1026 if (efer & EFER_SVME) {
1027 struct kvm_cpuid_entry2 *feat;
1028
1029 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1030 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
1031 return false;
1032 }
1033
1034 return true;
1035 }
1036 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1037
1038 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1039 {
1040 u64 old_efer = vcpu->arch.efer;
1041
1042 if (!kvm_valid_efer(vcpu, efer))
1043 return 1;
1044
1045 if (is_paging(vcpu)
1046 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1047 return 1;
1048
1049 efer &= ~EFER_LMA;
1050 efer |= vcpu->arch.efer & EFER_LMA;
1051
1052 kvm_x86_ops->set_efer(vcpu, efer);
1053
1054 /* Update reserved bits */
1055 if ((efer ^ old_efer) & EFER_NX)
1056 kvm_mmu_reset_context(vcpu);
1057
1058 return 0;
1059 }
1060
1061 void kvm_enable_efer_bits(u64 mask)
1062 {
1063 efer_reserved_bits &= ~mask;
1064 }
1065 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1066
1067 /*
1068 * Writes msr value into into the appropriate "register".
1069 * Returns 0 on success, non-0 otherwise.
1070 * Assumes vcpu_load() was already called.
1071 */
1072 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1073 {
1074 switch (msr->index) {
1075 case MSR_FS_BASE:
1076 case MSR_GS_BASE:
1077 case MSR_KERNEL_GS_BASE:
1078 case MSR_CSTAR:
1079 case MSR_LSTAR:
1080 if (is_noncanonical_address(msr->data))
1081 return 1;
1082 break;
1083 case MSR_IA32_SYSENTER_EIP:
1084 case MSR_IA32_SYSENTER_ESP:
1085 /*
1086 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1087 * non-canonical address is written on Intel but not on
1088 * AMD (which ignores the top 32-bits, because it does
1089 * not implement 64-bit SYSENTER).
1090 *
1091 * 64-bit code should hence be able to write a non-canonical
1092 * value on AMD. Making the address canonical ensures that
1093 * vmentry does not fail on Intel after writing a non-canonical
1094 * value, and that something deterministic happens if the guest
1095 * invokes 64-bit SYSENTER.
1096 */
1097 msr->data = get_canonical(msr->data);
1098 }
1099 return kvm_x86_ops->set_msr(vcpu, msr);
1100 }
1101 EXPORT_SYMBOL_GPL(kvm_set_msr);
1102
1103 /*
1104 * Adapt set_msr() to msr_io()'s calling convention
1105 */
1106 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1107 {
1108 struct msr_data msr;
1109 int r;
1110
1111 msr.index = index;
1112 msr.host_initiated = true;
1113 r = kvm_get_msr(vcpu, &msr);
1114 if (r)
1115 return r;
1116
1117 *data = msr.data;
1118 return 0;
1119 }
1120
1121 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1122 {
1123 struct msr_data msr;
1124
1125 msr.data = *data;
1126 msr.index = index;
1127 msr.host_initiated = true;
1128 return kvm_set_msr(vcpu, &msr);
1129 }
1130
1131 #ifdef CONFIG_X86_64
1132 struct pvclock_gtod_data {
1133 seqcount_t seq;
1134
1135 struct { /* extract of a clocksource struct */
1136 int vclock_mode;
1137 u64 cycle_last;
1138 u64 mask;
1139 u32 mult;
1140 u32 shift;
1141 } clock;
1142
1143 u64 boot_ns;
1144 u64 nsec_base;
1145 u64 wall_time_sec;
1146 };
1147
1148 static struct pvclock_gtod_data pvclock_gtod_data;
1149
1150 static void update_pvclock_gtod(struct timekeeper *tk)
1151 {
1152 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1153 u64 boot_ns;
1154
1155 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1156
1157 write_seqcount_begin(&vdata->seq);
1158
1159 /* copy pvclock gtod data */
1160 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1161 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1162 vdata->clock.mask = tk->tkr_mono.mask;
1163 vdata->clock.mult = tk->tkr_mono.mult;
1164 vdata->clock.shift = tk->tkr_mono.shift;
1165
1166 vdata->boot_ns = boot_ns;
1167 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1168
1169 vdata->wall_time_sec = tk->xtime_sec;
1170
1171 write_seqcount_end(&vdata->seq);
1172 }
1173 #endif
1174
1175 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1176 {
1177 /*
1178 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1179 * vcpu_enter_guest. This function is only called from
1180 * the physical CPU that is running vcpu.
1181 */
1182 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1183 }
1184
1185 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1186 {
1187 int version;
1188 int r;
1189 struct pvclock_wall_clock wc;
1190 struct timespec64 boot;
1191
1192 if (!wall_clock)
1193 return;
1194
1195 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1196 if (r)
1197 return;
1198
1199 if (version & 1)
1200 ++version; /* first time write, random junk */
1201
1202 ++version;
1203
1204 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1205 return;
1206
1207 /*
1208 * The guest calculates current wall clock time by adding
1209 * system time (updated by kvm_guest_time_update below) to the
1210 * wall clock specified here. guest system time equals host
1211 * system time for us, thus we must fill in host boot time here.
1212 */
1213 getboottime64(&boot);
1214
1215 if (kvm->arch.kvmclock_offset) {
1216 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1217 boot = timespec64_sub(boot, ts);
1218 }
1219 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1220 wc.nsec = boot.tv_nsec;
1221 wc.version = version;
1222
1223 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1224
1225 version++;
1226 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1227 }
1228
1229 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1230 {
1231 do_shl32_div32(dividend, divisor);
1232 return dividend;
1233 }
1234
1235 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1236 s8 *pshift, u32 *pmultiplier)
1237 {
1238 uint64_t scaled64;
1239 int32_t shift = 0;
1240 uint64_t tps64;
1241 uint32_t tps32;
1242
1243 tps64 = base_hz;
1244 scaled64 = scaled_hz;
1245 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1246 tps64 >>= 1;
1247 shift--;
1248 }
1249
1250 tps32 = (uint32_t)tps64;
1251 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1252 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1253 scaled64 >>= 1;
1254 else
1255 tps32 <<= 1;
1256 shift++;
1257 }
1258
1259 *pshift = shift;
1260 *pmultiplier = div_frac(scaled64, tps32);
1261
1262 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1263 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1264 }
1265
1266 #ifdef CONFIG_X86_64
1267 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1268 #endif
1269
1270 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1271 static unsigned long max_tsc_khz;
1272
1273 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1274 {
1275 u64 v = (u64)khz * (1000000 + ppm);
1276 do_div(v, 1000000);
1277 return v;
1278 }
1279
1280 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1281 {
1282 u64 ratio;
1283
1284 /* Guest TSC same frequency as host TSC? */
1285 if (!scale) {
1286 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1287 return 0;
1288 }
1289
1290 /* TSC scaling supported? */
1291 if (!kvm_has_tsc_control) {
1292 if (user_tsc_khz > tsc_khz) {
1293 vcpu->arch.tsc_catchup = 1;
1294 vcpu->arch.tsc_always_catchup = 1;
1295 return 0;
1296 } else {
1297 WARN(1, "user requested TSC rate below hardware speed\n");
1298 return -1;
1299 }
1300 }
1301
1302 /* TSC scaling required - calculate ratio */
1303 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1304 user_tsc_khz, tsc_khz);
1305
1306 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1307 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1308 user_tsc_khz);
1309 return -1;
1310 }
1311
1312 vcpu->arch.tsc_scaling_ratio = ratio;
1313 return 0;
1314 }
1315
1316 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1317 {
1318 u32 thresh_lo, thresh_hi;
1319 int use_scaling = 0;
1320
1321 /* tsc_khz can be zero if TSC calibration fails */
1322 if (user_tsc_khz == 0) {
1323 /* set tsc_scaling_ratio to a safe value */
1324 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1325 return -1;
1326 }
1327
1328 /* Compute a scale to convert nanoseconds in TSC cycles */
1329 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1330 &vcpu->arch.virtual_tsc_shift,
1331 &vcpu->arch.virtual_tsc_mult);
1332 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1333
1334 /*
1335 * Compute the variation in TSC rate which is acceptable
1336 * within the range of tolerance and decide if the
1337 * rate being applied is within that bounds of the hardware
1338 * rate. If so, no scaling or compensation need be done.
1339 */
1340 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1341 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1342 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1343 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1344 use_scaling = 1;
1345 }
1346 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1347 }
1348
1349 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1350 {
1351 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1352 vcpu->arch.virtual_tsc_mult,
1353 vcpu->arch.virtual_tsc_shift);
1354 tsc += vcpu->arch.this_tsc_write;
1355 return tsc;
1356 }
1357
1358 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1359 {
1360 #ifdef CONFIG_X86_64
1361 bool vcpus_matched;
1362 struct kvm_arch *ka = &vcpu->kvm->arch;
1363 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1364
1365 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1366 atomic_read(&vcpu->kvm->online_vcpus));
1367
1368 /*
1369 * Once the masterclock is enabled, always perform request in
1370 * order to update it.
1371 *
1372 * In order to enable masterclock, the host clocksource must be TSC
1373 * and the vcpus need to have matched TSCs. When that happens,
1374 * perform request to enable masterclock.
1375 */
1376 if (ka->use_master_clock ||
1377 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1378 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1379
1380 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1381 atomic_read(&vcpu->kvm->online_vcpus),
1382 ka->use_master_clock, gtod->clock.vclock_mode);
1383 #endif
1384 }
1385
1386 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1387 {
1388 u64 curr_offset = vcpu->arch.tsc_offset;
1389 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1390 }
1391
1392 /*
1393 * Multiply tsc by a fixed point number represented by ratio.
1394 *
1395 * The most significant 64-N bits (mult) of ratio represent the
1396 * integral part of the fixed point number; the remaining N bits
1397 * (frac) represent the fractional part, ie. ratio represents a fixed
1398 * point number (mult + frac * 2^(-N)).
1399 *
1400 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1401 */
1402 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1403 {
1404 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1405 }
1406
1407 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1408 {
1409 u64 _tsc = tsc;
1410 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1411
1412 if (ratio != kvm_default_tsc_scaling_ratio)
1413 _tsc = __scale_tsc(ratio, tsc);
1414
1415 return _tsc;
1416 }
1417 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1418
1419 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1420 {
1421 u64 tsc;
1422
1423 tsc = kvm_scale_tsc(vcpu, rdtsc());
1424
1425 return target_tsc - tsc;
1426 }
1427
1428 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1429 {
1430 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1431 }
1432 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1433
1434 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1435 {
1436 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1437 vcpu->arch.tsc_offset = offset;
1438 }
1439
1440 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1441 {
1442 struct kvm *kvm = vcpu->kvm;
1443 u64 offset, ns, elapsed;
1444 unsigned long flags;
1445 s64 usdiff;
1446 bool matched;
1447 bool already_matched;
1448 u64 data = msr->data;
1449
1450 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1451 offset = kvm_compute_tsc_offset(vcpu, data);
1452 ns = ktime_get_boot_ns();
1453 elapsed = ns - kvm->arch.last_tsc_nsec;
1454
1455 if (vcpu->arch.virtual_tsc_khz) {
1456 int faulted = 0;
1457
1458 /* n.b - signed multiplication and division required */
1459 usdiff = data - kvm->arch.last_tsc_write;
1460 #ifdef CONFIG_X86_64
1461 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1462 #else
1463 /* do_div() only does unsigned */
1464 asm("1: idivl %[divisor]\n"
1465 "2: xor %%edx, %%edx\n"
1466 " movl $0, %[faulted]\n"
1467 "3:\n"
1468 ".section .fixup,\"ax\"\n"
1469 "4: movl $1, %[faulted]\n"
1470 " jmp 3b\n"
1471 ".previous\n"
1472
1473 _ASM_EXTABLE(1b, 4b)
1474
1475 : "=A"(usdiff), [faulted] "=r" (faulted)
1476 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1477
1478 #endif
1479 do_div(elapsed, 1000);
1480 usdiff -= elapsed;
1481 if (usdiff < 0)
1482 usdiff = -usdiff;
1483
1484 /* idivl overflow => difference is larger than USEC_PER_SEC */
1485 if (faulted)
1486 usdiff = USEC_PER_SEC;
1487 } else
1488 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1489
1490 /*
1491 * Special case: TSC write with a small delta (1 second) of virtual
1492 * cycle time against real time is interpreted as an attempt to
1493 * synchronize the CPU.
1494 *
1495 * For a reliable TSC, we can match TSC offsets, and for an unstable
1496 * TSC, we add elapsed time in this computation. We could let the
1497 * compensation code attempt to catch up if we fall behind, but
1498 * it's better to try to match offsets from the beginning.
1499 */
1500 if (usdiff < USEC_PER_SEC &&
1501 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1502 if (!check_tsc_unstable()) {
1503 offset = kvm->arch.cur_tsc_offset;
1504 pr_debug("kvm: matched tsc offset for %llu\n", data);
1505 } else {
1506 u64 delta = nsec_to_cycles(vcpu, elapsed);
1507 data += delta;
1508 offset = kvm_compute_tsc_offset(vcpu, data);
1509 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1510 }
1511 matched = true;
1512 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1513 } else {
1514 /*
1515 * We split periods of matched TSC writes into generations.
1516 * For each generation, we track the original measured
1517 * nanosecond time, offset, and write, so if TSCs are in
1518 * sync, we can match exact offset, and if not, we can match
1519 * exact software computation in compute_guest_tsc()
1520 *
1521 * These values are tracked in kvm->arch.cur_xxx variables.
1522 */
1523 kvm->arch.cur_tsc_generation++;
1524 kvm->arch.cur_tsc_nsec = ns;
1525 kvm->arch.cur_tsc_write = data;
1526 kvm->arch.cur_tsc_offset = offset;
1527 matched = false;
1528 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1529 kvm->arch.cur_tsc_generation, data);
1530 }
1531
1532 /*
1533 * We also track th most recent recorded KHZ, write and time to
1534 * allow the matching interval to be extended at each write.
1535 */
1536 kvm->arch.last_tsc_nsec = ns;
1537 kvm->arch.last_tsc_write = data;
1538 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1539
1540 vcpu->arch.last_guest_tsc = data;
1541
1542 /* Keep track of which generation this VCPU has synchronized to */
1543 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1544 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1545 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1546
1547 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1548 update_ia32_tsc_adjust_msr(vcpu, offset);
1549 kvm_vcpu_write_tsc_offset(vcpu, offset);
1550 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1551
1552 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1553 if (!matched) {
1554 kvm->arch.nr_vcpus_matched_tsc = 0;
1555 } else if (!already_matched) {
1556 kvm->arch.nr_vcpus_matched_tsc++;
1557 }
1558
1559 kvm_track_tsc_matching(vcpu);
1560 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1561 }
1562
1563 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1564
1565 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1566 s64 adjustment)
1567 {
1568 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
1569 }
1570
1571 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1572 {
1573 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1574 WARN_ON(adjustment < 0);
1575 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1576 adjust_tsc_offset_guest(vcpu, adjustment);
1577 }
1578
1579 #ifdef CONFIG_X86_64
1580
1581 static u64 read_tsc(void)
1582 {
1583 u64 ret = (u64)rdtsc_ordered();
1584 u64 last = pvclock_gtod_data.clock.cycle_last;
1585
1586 if (likely(ret >= last))
1587 return ret;
1588
1589 /*
1590 * GCC likes to generate cmov here, but this branch is extremely
1591 * predictable (it's just a function of time and the likely is
1592 * very likely) and there's a data dependence, so force GCC
1593 * to generate a branch instead. I don't barrier() because
1594 * we don't actually need a barrier, and if this function
1595 * ever gets inlined it will generate worse code.
1596 */
1597 asm volatile ("");
1598 return last;
1599 }
1600
1601 static inline u64 vgettsc(u64 *cycle_now)
1602 {
1603 long v;
1604 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1605
1606 *cycle_now = read_tsc();
1607
1608 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1609 return v * gtod->clock.mult;
1610 }
1611
1612 static int do_monotonic_boot(s64 *t, u64 *cycle_now)
1613 {
1614 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1615 unsigned long seq;
1616 int mode;
1617 u64 ns;
1618
1619 do {
1620 seq = read_seqcount_begin(&gtod->seq);
1621 mode = gtod->clock.vclock_mode;
1622 ns = gtod->nsec_base;
1623 ns += vgettsc(cycle_now);
1624 ns >>= gtod->clock.shift;
1625 ns += gtod->boot_ns;
1626 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1627 *t = ns;
1628
1629 return mode;
1630 }
1631
1632 static int do_realtime(struct timespec *ts, u64 *cycle_now)
1633 {
1634 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1635 unsigned long seq;
1636 int mode;
1637 u64 ns;
1638
1639 do {
1640 seq = read_seqcount_begin(&gtod->seq);
1641 mode = gtod->clock.vclock_mode;
1642 ts->tv_sec = gtod->wall_time_sec;
1643 ns = gtod->nsec_base;
1644 ns += vgettsc(cycle_now);
1645 ns >>= gtod->clock.shift;
1646 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1647
1648 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1649 ts->tv_nsec = ns;
1650
1651 return mode;
1652 }
1653
1654 /* returns true if host is using tsc clocksource */
1655 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
1656 {
1657 /* checked again under seqlock below */
1658 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1659 return false;
1660
1661 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1662 }
1663
1664 /* returns true if host is using tsc clocksource */
1665 static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1666 u64 *cycle_now)
1667 {
1668 /* checked again under seqlock below */
1669 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1670 return false;
1671
1672 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1673 }
1674 #endif
1675
1676 /*
1677 *
1678 * Assuming a stable TSC across physical CPUS, and a stable TSC
1679 * across virtual CPUs, the following condition is possible.
1680 * Each numbered line represents an event visible to both
1681 * CPUs at the next numbered event.
1682 *
1683 * "timespecX" represents host monotonic time. "tscX" represents
1684 * RDTSC value.
1685 *
1686 * VCPU0 on CPU0 | VCPU1 on CPU1
1687 *
1688 * 1. read timespec0,tsc0
1689 * 2. | timespec1 = timespec0 + N
1690 * | tsc1 = tsc0 + M
1691 * 3. transition to guest | transition to guest
1692 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1693 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1694 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1695 *
1696 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1697 *
1698 * - ret0 < ret1
1699 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1700 * ...
1701 * - 0 < N - M => M < N
1702 *
1703 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1704 * always the case (the difference between two distinct xtime instances
1705 * might be smaller then the difference between corresponding TSC reads,
1706 * when updating guest vcpus pvclock areas).
1707 *
1708 * To avoid that problem, do not allow visibility of distinct
1709 * system_timestamp/tsc_timestamp values simultaneously: use a master
1710 * copy of host monotonic time values. Update that master copy
1711 * in lockstep.
1712 *
1713 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1714 *
1715 */
1716
1717 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1718 {
1719 #ifdef CONFIG_X86_64
1720 struct kvm_arch *ka = &kvm->arch;
1721 int vclock_mode;
1722 bool host_tsc_clocksource, vcpus_matched;
1723
1724 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1725 atomic_read(&kvm->online_vcpus));
1726
1727 /*
1728 * If the host uses TSC clock, then passthrough TSC as stable
1729 * to the guest.
1730 */
1731 host_tsc_clocksource = kvm_get_time_and_clockread(
1732 &ka->master_kernel_ns,
1733 &ka->master_cycle_now);
1734
1735 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1736 && !backwards_tsc_observed
1737 && !ka->boot_vcpu_runs_old_kvmclock;
1738
1739 if (ka->use_master_clock)
1740 atomic_set(&kvm_guest_has_master_clock, 1);
1741
1742 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1743 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1744 vcpus_matched);
1745 #endif
1746 }
1747
1748 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1749 {
1750 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1751 }
1752
1753 static void kvm_gen_update_masterclock(struct kvm *kvm)
1754 {
1755 #ifdef CONFIG_X86_64
1756 int i;
1757 struct kvm_vcpu *vcpu;
1758 struct kvm_arch *ka = &kvm->arch;
1759
1760 spin_lock(&ka->pvclock_gtod_sync_lock);
1761 kvm_make_mclock_inprogress_request(kvm);
1762 /* no guest entries from this point */
1763 pvclock_update_vm_gtod_copy(kvm);
1764
1765 kvm_for_each_vcpu(i, vcpu, kvm)
1766 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1767
1768 /* guest entries allowed */
1769 kvm_for_each_vcpu(i, vcpu, kvm)
1770 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1771
1772 spin_unlock(&ka->pvclock_gtod_sync_lock);
1773 #endif
1774 }
1775
1776 static u64 __get_kvmclock_ns(struct kvm *kvm)
1777 {
1778 struct kvm_arch *ka = &kvm->arch;
1779 struct pvclock_vcpu_time_info hv_clock;
1780
1781 spin_lock(&ka->pvclock_gtod_sync_lock);
1782 if (!ka->use_master_clock) {
1783 spin_unlock(&ka->pvclock_gtod_sync_lock);
1784 return ktime_get_boot_ns() + ka->kvmclock_offset;
1785 }
1786
1787 hv_clock.tsc_timestamp = ka->master_cycle_now;
1788 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1789 spin_unlock(&ka->pvclock_gtod_sync_lock);
1790
1791 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1792 &hv_clock.tsc_shift,
1793 &hv_clock.tsc_to_system_mul);
1794 return __pvclock_read_cycles(&hv_clock, rdtsc());
1795 }
1796
1797 u64 get_kvmclock_ns(struct kvm *kvm)
1798 {
1799 unsigned long flags;
1800 s64 ns;
1801
1802 local_irq_save(flags);
1803 ns = __get_kvmclock_ns(kvm);
1804 local_irq_restore(flags);
1805
1806 return ns;
1807 }
1808
1809 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1810 {
1811 struct kvm_vcpu_arch *vcpu = &v->arch;
1812 struct pvclock_vcpu_time_info guest_hv_clock;
1813
1814 if (unlikely(kvm_vcpu_read_guest_cached(v, &vcpu->pv_time,
1815 &guest_hv_clock, sizeof(guest_hv_clock))))
1816 return;
1817
1818 /* This VCPU is paused, but it's legal for a guest to read another
1819 * VCPU's kvmclock, so we really have to follow the specification where
1820 * it says that version is odd if data is being modified, and even after
1821 * it is consistent.
1822 *
1823 * Version field updates must be kept separate. This is because
1824 * kvm_write_guest_cached might use a "rep movs" instruction, and
1825 * writes within a string instruction are weakly ordered. So there
1826 * are three writes overall.
1827 *
1828 * As a small optimization, only write the version field in the first
1829 * and third write. The vcpu->pv_time cache is still valid, because the
1830 * version field is the first in the struct.
1831 */
1832 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1833
1834 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1835 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1836 &vcpu->hv_clock,
1837 sizeof(vcpu->hv_clock.version));
1838
1839 smp_wmb();
1840
1841 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1842 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1843
1844 if (vcpu->pvclock_set_guest_stopped_request) {
1845 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1846 vcpu->pvclock_set_guest_stopped_request = false;
1847 }
1848
1849 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1850
1851 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1852 &vcpu->hv_clock,
1853 sizeof(vcpu->hv_clock));
1854
1855 smp_wmb();
1856
1857 vcpu->hv_clock.version++;
1858 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1859 &vcpu->hv_clock,
1860 sizeof(vcpu->hv_clock.version));
1861 }
1862
1863 static int kvm_guest_time_update(struct kvm_vcpu *v)
1864 {
1865 unsigned long flags, tgt_tsc_khz;
1866 struct kvm_vcpu_arch *vcpu = &v->arch;
1867 struct kvm_arch *ka = &v->kvm->arch;
1868 s64 kernel_ns;
1869 u64 tsc_timestamp, host_tsc;
1870 u8 pvclock_flags;
1871 bool use_master_clock;
1872
1873 kernel_ns = 0;
1874 host_tsc = 0;
1875
1876 /*
1877 * If the host uses TSC clock, then passthrough TSC as stable
1878 * to the guest.
1879 */
1880 spin_lock(&ka->pvclock_gtod_sync_lock);
1881 use_master_clock = ka->use_master_clock;
1882 if (use_master_clock) {
1883 host_tsc = ka->master_cycle_now;
1884 kernel_ns = ka->master_kernel_ns;
1885 }
1886 spin_unlock(&ka->pvclock_gtod_sync_lock);
1887
1888 /* Keep irq disabled to prevent changes to the clock */
1889 local_irq_save(flags);
1890 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1891 if (unlikely(tgt_tsc_khz == 0)) {
1892 local_irq_restore(flags);
1893 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1894 return 1;
1895 }
1896 if (!use_master_clock) {
1897 host_tsc = rdtsc();
1898 kernel_ns = ktime_get_boot_ns();
1899 }
1900
1901 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1902
1903 /*
1904 * We may have to catch up the TSC to match elapsed wall clock
1905 * time for two reasons, even if kvmclock is used.
1906 * 1) CPU could have been running below the maximum TSC rate
1907 * 2) Broken TSC compensation resets the base at each VCPU
1908 * entry to avoid unknown leaps of TSC even when running
1909 * again on the same CPU. This may cause apparent elapsed
1910 * time to disappear, and the guest to stand still or run
1911 * very slowly.
1912 */
1913 if (vcpu->tsc_catchup) {
1914 u64 tsc = compute_guest_tsc(v, kernel_ns);
1915 if (tsc > tsc_timestamp) {
1916 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1917 tsc_timestamp = tsc;
1918 }
1919 }
1920
1921 local_irq_restore(flags);
1922
1923 /* With all the info we got, fill in the values */
1924
1925 if (kvm_has_tsc_control)
1926 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1927
1928 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
1929 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
1930 &vcpu->hv_clock.tsc_shift,
1931 &vcpu->hv_clock.tsc_to_system_mul);
1932 vcpu->hw_tsc_khz = tgt_tsc_khz;
1933 }
1934
1935 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1936 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1937 vcpu->last_guest_tsc = tsc_timestamp;
1938
1939 /* If the host uses TSC clocksource, then it is stable */
1940 pvclock_flags = 0;
1941 if (use_master_clock)
1942 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1943
1944 vcpu->hv_clock.flags = pvclock_flags;
1945
1946 if (vcpu->pv_time_enabled)
1947 kvm_setup_pvclock_page(v);
1948 if (v == kvm_get_vcpu(v->kvm, 0))
1949 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
1950 return 0;
1951 }
1952
1953 /*
1954 * kvmclock updates which are isolated to a given vcpu, such as
1955 * vcpu->cpu migration, should not allow system_timestamp from
1956 * the rest of the vcpus to remain static. Otherwise ntp frequency
1957 * correction applies to one vcpu's system_timestamp but not
1958 * the others.
1959 *
1960 * So in those cases, request a kvmclock update for all vcpus.
1961 * We need to rate-limit these requests though, as they can
1962 * considerably slow guests that have a large number of vcpus.
1963 * The time for a remote vcpu to update its kvmclock is bound
1964 * by the delay we use to rate-limit the updates.
1965 */
1966
1967 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1968
1969 static void kvmclock_update_fn(struct work_struct *work)
1970 {
1971 int i;
1972 struct delayed_work *dwork = to_delayed_work(work);
1973 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1974 kvmclock_update_work);
1975 struct kvm *kvm = container_of(ka, struct kvm, arch);
1976 struct kvm_vcpu *vcpu;
1977
1978 kvm_for_each_vcpu(i, vcpu, kvm) {
1979 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1980 kvm_vcpu_kick(vcpu);
1981 }
1982 }
1983
1984 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1985 {
1986 struct kvm *kvm = v->kvm;
1987
1988 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1989 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1990 KVMCLOCK_UPDATE_DELAY);
1991 }
1992
1993 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1994
1995 static void kvmclock_sync_fn(struct work_struct *work)
1996 {
1997 struct delayed_work *dwork = to_delayed_work(work);
1998 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1999 kvmclock_sync_work);
2000 struct kvm *kvm = container_of(ka, struct kvm, arch);
2001
2002 if (!kvmclock_periodic_sync)
2003 return;
2004
2005 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2006 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2007 KVMCLOCK_SYNC_PERIOD);
2008 }
2009
2010 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2011 {
2012 u64 mcg_cap = vcpu->arch.mcg_cap;
2013 unsigned bank_num = mcg_cap & 0xff;
2014
2015 switch (msr) {
2016 case MSR_IA32_MCG_STATUS:
2017 vcpu->arch.mcg_status = data;
2018 break;
2019 case MSR_IA32_MCG_CTL:
2020 if (!(mcg_cap & MCG_CTL_P))
2021 return 1;
2022 if (data != 0 && data != ~(u64)0)
2023 return -1;
2024 vcpu->arch.mcg_ctl = data;
2025 break;
2026 default:
2027 if (msr >= MSR_IA32_MC0_CTL &&
2028 msr < MSR_IA32_MCx_CTL(bank_num)) {
2029 u32 offset = msr - MSR_IA32_MC0_CTL;
2030 /* only 0 or all 1s can be written to IA32_MCi_CTL
2031 * some Linux kernels though clear bit 10 in bank 4 to
2032 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2033 * this to avoid an uncatched #GP in the guest
2034 */
2035 if ((offset & 0x3) == 0 &&
2036 data != 0 && (data | (1 << 10)) != ~(u64)0)
2037 return -1;
2038 vcpu->arch.mce_banks[offset] = data;
2039 break;
2040 }
2041 return 1;
2042 }
2043 return 0;
2044 }
2045
2046 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2047 {
2048 struct kvm *kvm = vcpu->kvm;
2049 int lm = is_long_mode(vcpu);
2050 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2051 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2052 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2053 : kvm->arch.xen_hvm_config.blob_size_32;
2054 u32 page_num = data & ~PAGE_MASK;
2055 u64 page_addr = data & PAGE_MASK;
2056 u8 *page;
2057 int r;
2058
2059 r = -E2BIG;
2060 if (page_num >= blob_size)
2061 goto out;
2062 r = -ENOMEM;
2063 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2064 if (IS_ERR(page)) {
2065 r = PTR_ERR(page);
2066 goto out;
2067 }
2068 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2069 goto out_free;
2070 r = 0;
2071 out_free:
2072 kfree(page);
2073 out:
2074 return r;
2075 }
2076
2077 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2078 {
2079 gpa_t gpa = data & ~0x3f;
2080
2081 /* Bits 2:5 are reserved, Should be zero */
2082 if (data & 0x3c)
2083 return 1;
2084
2085 vcpu->arch.apf.msr_val = data;
2086
2087 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2088 kvm_clear_async_pf_completion_queue(vcpu);
2089 kvm_async_pf_hash_reset(vcpu);
2090 return 0;
2091 }
2092
2093 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu, &vcpu->arch.apf.data, gpa,
2094 sizeof(u32)))
2095 return 1;
2096
2097 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2098 kvm_async_pf_wakeup_all(vcpu);
2099 return 0;
2100 }
2101
2102 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2103 {
2104 vcpu->arch.pv_time_enabled = false;
2105 }
2106
2107 static void record_steal_time(struct kvm_vcpu *vcpu)
2108 {
2109 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2110 return;
2111
2112 if (unlikely(kvm_vcpu_read_guest_cached(vcpu, &vcpu->arch.st.stime,
2113 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2114 return;
2115
2116 vcpu->arch.st.steal.preempted = 0;
2117
2118 if (vcpu->arch.st.steal.version & 1)
2119 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2120
2121 vcpu->arch.st.steal.version += 1;
2122
2123 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
2124 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2125
2126 smp_wmb();
2127
2128 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2129 vcpu->arch.st.last_steal;
2130 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2131
2132 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
2133 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2134
2135 smp_wmb();
2136
2137 vcpu->arch.st.steal.version += 1;
2138
2139 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
2140 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2141 }
2142
2143 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2144 {
2145 bool pr = false;
2146 u32 msr = msr_info->index;
2147 u64 data = msr_info->data;
2148
2149 switch (msr) {
2150 case MSR_AMD64_NB_CFG:
2151 case MSR_IA32_UCODE_REV:
2152 case MSR_IA32_UCODE_WRITE:
2153 case MSR_VM_HSAVE_PA:
2154 case MSR_AMD64_PATCH_LOADER:
2155 case MSR_AMD64_BU_CFG2:
2156 break;
2157
2158 case MSR_EFER:
2159 return set_efer(vcpu, data);
2160 case MSR_K7_HWCR:
2161 data &= ~(u64)0x40; /* ignore flush filter disable */
2162 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2163 data &= ~(u64)0x8; /* ignore TLB cache disable */
2164 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2165 if (data != 0) {
2166 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2167 data);
2168 return 1;
2169 }
2170 break;
2171 case MSR_FAM10H_MMIO_CONF_BASE:
2172 if (data != 0) {
2173 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2174 "0x%llx\n", data);
2175 return 1;
2176 }
2177 break;
2178 case MSR_IA32_DEBUGCTLMSR:
2179 if (!data) {
2180 /* We support the non-activated case already */
2181 break;
2182 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2183 /* Values other than LBR and BTF are vendor-specific,
2184 thus reserved and should throw a #GP */
2185 return 1;
2186 }
2187 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2188 __func__, data);
2189 break;
2190 case 0x200 ... 0x2ff:
2191 return kvm_mtrr_set_msr(vcpu, msr, data);
2192 case MSR_IA32_APICBASE:
2193 return kvm_set_apic_base(vcpu, msr_info);
2194 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2195 return kvm_x2apic_msr_write(vcpu, msr, data);
2196 case MSR_IA32_TSCDEADLINE:
2197 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2198 break;
2199 case MSR_IA32_TSC_ADJUST:
2200 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2201 if (!msr_info->host_initiated) {
2202 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2203 adjust_tsc_offset_guest(vcpu, adj);
2204 }
2205 vcpu->arch.ia32_tsc_adjust_msr = data;
2206 }
2207 break;
2208 case MSR_IA32_MISC_ENABLE:
2209 vcpu->arch.ia32_misc_enable_msr = data;
2210 break;
2211 case MSR_IA32_SMBASE:
2212 if (!msr_info->host_initiated)
2213 return 1;
2214 vcpu->arch.smbase = data;
2215 break;
2216 case MSR_KVM_WALL_CLOCK_NEW:
2217 case MSR_KVM_WALL_CLOCK:
2218 vcpu->kvm->arch.wall_clock = data;
2219 kvm_write_wall_clock(vcpu->kvm, data);
2220 break;
2221 case MSR_KVM_SYSTEM_TIME_NEW:
2222 case MSR_KVM_SYSTEM_TIME: {
2223 struct kvm_arch *ka = &vcpu->kvm->arch;
2224
2225 kvmclock_reset(vcpu);
2226
2227 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2228 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2229
2230 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2231 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2232 &vcpu->requests);
2233
2234 ka->boot_vcpu_runs_old_kvmclock = tmp;
2235 }
2236
2237 vcpu->arch.time = data;
2238 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2239
2240 /* we verify if the enable bit is set... */
2241 if (!(data & 1))
2242 break;
2243
2244 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu,
2245 &vcpu->arch.pv_time, data & ~1ULL,
2246 sizeof(struct pvclock_vcpu_time_info)))
2247 vcpu->arch.pv_time_enabled = false;
2248 else
2249 vcpu->arch.pv_time_enabled = true;
2250
2251 break;
2252 }
2253 case MSR_KVM_ASYNC_PF_EN:
2254 if (kvm_pv_enable_async_pf(vcpu, data))
2255 return 1;
2256 break;
2257 case MSR_KVM_STEAL_TIME:
2258
2259 if (unlikely(!sched_info_on()))
2260 return 1;
2261
2262 if (data & KVM_STEAL_RESERVED_MASK)
2263 return 1;
2264
2265 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu, &vcpu->arch.st.stime,
2266 data & KVM_STEAL_VALID_BITS,
2267 sizeof(struct kvm_steal_time)))
2268 return 1;
2269
2270 vcpu->arch.st.msr_val = data;
2271
2272 if (!(data & KVM_MSR_ENABLED))
2273 break;
2274
2275 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2276
2277 break;
2278 case MSR_KVM_PV_EOI_EN:
2279 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2280 return 1;
2281 break;
2282
2283 case MSR_IA32_MCG_CTL:
2284 case MSR_IA32_MCG_STATUS:
2285 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2286 return set_msr_mce(vcpu, msr, data);
2287
2288 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2289 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2290 pr = true; /* fall through */
2291 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2292 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2293 if (kvm_pmu_is_valid_msr(vcpu, msr))
2294 return kvm_pmu_set_msr(vcpu, msr_info);
2295
2296 if (pr || data != 0)
2297 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2298 "0x%x data 0x%llx\n", msr, data);
2299 break;
2300 case MSR_K7_CLK_CTL:
2301 /*
2302 * Ignore all writes to this no longer documented MSR.
2303 * Writes are only relevant for old K7 processors,
2304 * all pre-dating SVM, but a recommended workaround from
2305 * AMD for these chips. It is possible to specify the
2306 * affected processor models on the command line, hence
2307 * the need to ignore the workaround.
2308 */
2309 break;
2310 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2311 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2312 case HV_X64_MSR_CRASH_CTL:
2313 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2314 return kvm_hv_set_msr_common(vcpu, msr, data,
2315 msr_info->host_initiated);
2316 case MSR_IA32_BBL_CR_CTL3:
2317 /* Drop writes to this legacy MSR -- see rdmsr
2318 * counterpart for further detail.
2319 */
2320 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
2321 break;
2322 case MSR_AMD64_OSVW_ID_LENGTH:
2323 if (!guest_cpuid_has_osvw(vcpu))
2324 return 1;
2325 vcpu->arch.osvw.length = data;
2326 break;
2327 case MSR_AMD64_OSVW_STATUS:
2328 if (!guest_cpuid_has_osvw(vcpu))
2329 return 1;
2330 vcpu->arch.osvw.status = data;
2331 break;
2332 default:
2333 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2334 return xen_hvm_config(vcpu, data);
2335 if (kvm_pmu_is_valid_msr(vcpu, msr))
2336 return kvm_pmu_set_msr(vcpu, msr_info);
2337 if (!ignore_msrs) {
2338 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2339 msr, data);
2340 return 1;
2341 } else {
2342 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2343 msr, data);
2344 break;
2345 }
2346 }
2347 return 0;
2348 }
2349 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2350
2351
2352 /*
2353 * Reads an msr value (of 'msr_index') into 'pdata'.
2354 * Returns 0 on success, non-0 otherwise.
2355 * Assumes vcpu_load() was already called.
2356 */
2357 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2358 {
2359 return kvm_x86_ops->get_msr(vcpu, msr);
2360 }
2361 EXPORT_SYMBOL_GPL(kvm_get_msr);
2362
2363 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2364 {
2365 u64 data;
2366 u64 mcg_cap = vcpu->arch.mcg_cap;
2367 unsigned bank_num = mcg_cap & 0xff;
2368
2369 switch (msr) {
2370 case MSR_IA32_P5_MC_ADDR:
2371 case MSR_IA32_P5_MC_TYPE:
2372 data = 0;
2373 break;
2374 case MSR_IA32_MCG_CAP:
2375 data = vcpu->arch.mcg_cap;
2376 break;
2377 case MSR_IA32_MCG_CTL:
2378 if (!(mcg_cap & MCG_CTL_P))
2379 return 1;
2380 data = vcpu->arch.mcg_ctl;
2381 break;
2382 case MSR_IA32_MCG_STATUS:
2383 data = vcpu->arch.mcg_status;
2384 break;
2385 default:
2386 if (msr >= MSR_IA32_MC0_CTL &&
2387 msr < MSR_IA32_MCx_CTL(bank_num)) {
2388 u32 offset = msr - MSR_IA32_MC0_CTL;
2389 data = vcpu->arch.mce_banks[offset];
2390 break;
2391 }
2392 return 1;
2393 }
2394 *pdata = data;
2395 return 0;
2396 }
2397
2398 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2399 {
2400 switch (msr_info->index) {
2401 case MSR_IA32_PLATFORM_ID:
2402 case MSR_IA32_EBL_CR_POWERON:
2403 case MSR_IA32_DEBUGCTLMSR:
2404 case MSR_IA32_LASTBRANCHFROMIP:
2405 case MSR_IA32_LASTBRANCHTOIP:
2406 case MSR_IA32_LASTINTFROMIP:
2407 case MSR_IA32_LASTINTTOIP:
2408 case MSR_K8_SYSCFG:
2409 case MSR_K8_TSEG_ADDR:
2410 case MSR_K8_TSEG_MASK:
2411 case MSR_K7_HWCR:
2412 case MSR_VM_HSAVE_PA:
2413 case MSR_K8_INT_PENDING_MSG:
2414 case MSR_AMD64_NB_CFG:
2415 case MSR_FAM10H_MMIO_CONF_BASE:
2416 case MSR_AMD64_BU_CFG2:
2417 case MSR_IA32_PERF_CTL:
2418 msr_info->data = 0;
2419 break;
2420 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2421 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2422 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2423 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2424 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2425 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2426 msr_info->data = 0;
2427 break;
2428 case MSR_IA32_UCODE_REV:
2429 msr_info->data = 0x100000000ULL;
2430 break;
2431 case MSR_MTRRcap:
2432 case 0x200 ... 0x2ff:
2433 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2434 case 0xcd: /* fsb frequency */
2435 msr_info->data = 3;
2436 break;
2437 /*
2438 * MSR_EBC_FREQUENCY_ID
2439 * Conservative value valid for even the basic CPU models.
2440 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2441 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2442 * and 266MHz for model 3, or 4. Set Core Clock
2443 * Frequency to System Bus Frequency Ratio to 1 (bits
2444 * 31:24) even though these are only valid for CPU
2445 * models > 2, however guests may end up dividing or
2446 * multiplying by zero otherwise.
2447 */
2448 case MSR_EBC_FREQUENCY_ID:
2449 msr_info->data = 1 << 24;
2450 break;
2451 case MSR_IA32_APICBASE:
2452 msr_info->data = kvm_get_apic_base(vcpu);
2453 break;
2454 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2455 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2456 break;
2457 case MSR_IA32_TSCDEADLINE:
2458 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2459 break;
2460 case MSR_IA32_TSC_ADJUST:
2461 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2462 break;
2463 case MSR_IA32_MISC_ENABLE:
2464 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2465 break;
2466 case MSR_IA32_SMBASE:
2467 if (!msr_info->host_initiated)
2468 return 1;
2469 msr_info->data = vcpu->arch.smbase;
2470 break;
2471 case MSR_IA32_PERF_STATUS:
2472 /* TSC increment by tick */
2473 msr_info->data = 1000ULL;
2474 /* CPU multiplier */
2475 msr_info->data |= (((uint64_t)4ULL) << 40);
2476 break;
2477 case MSR_EFER:
2478 msr_info->data = vcpu->arch.efer;
2479 break;
2480 case MSR_KVM_WALL_CLOCK:
2481 case MSR_KVM_WALL_CLOCK_NEW:
2482 msr_info->data = vcpu->kvm->arch.wall_clock;
2483 break;
2484 case MSR_KVM_SYSTEM_TIME:
2485 case MSR_KVM_SYSTEM_TIME_NEW:
2486 msr_info->data = vcpu->arch.time;
2487 break;
2488 case MSR_KVM_ASYNC_PF_EN:
2489 msr_info->data = vcpu->arch.apf.msr_val;
2490 break;
2491 case MSR_KVM_STEAL_TIME:
2492 msr_info->data = vcpu->arch.st.msr_val;
2493 break;
2494 case MSR_KVM_PV_EOI_EN:
2495 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2496 break;
2497 case MSR_IA32_P5_MC_ADDR:
2498 case MSR_IA32_P5_MC_TYPE:
2499 case MSR_IA32_MCG_CAP:
2500 case MSR_IA32_MCG_CTL:
2501 case MSR_IA32_MCG_STATUS:
2502 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2503 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2504 case MSR_K7_CLK_CTL:
2505 /*
2506 * Provide expected ramp-up count for K7. All other
2507 * are set to zero, indicating minimum divisors for
2508 * every field.
2509 *
2510 * This prevents guest kernels on AMD host with CPU
2511 * type 6, model 8 and higher from exploding due to
2512 * the rdmsr failing.
2513 */
2514 msr_info->data = 0x20000000;
2515 break;
2516 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2517 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2518 case HV_X64_MSR_CRASH_CTL:
2519 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2520 return kvm_hv_get_msr_common(vcpu,
2521 msr_info->index, &msr_info->data);
2522 break;
2523 case MSR_IA32_BBL_CR_CTL3:
2524 /* This legacy MSR exists but isn't fully documented in current
2525 * silicon. It is however accessed by winxp in very narrow
2526 * scenarios where it sets bit #19, itself documented as
2527 * a "reserved" bit. Best effort attempt to source coherent
2528 * read data here should the balance of the register be
2529 * interpreted by the guest:
2530 *
2531 * L2 cache control register 3: 64GB range, 256KB size,
2532 * enabled, latency 0x1, configured
2533 */
2534 msr_info->data = 0xbe702111;
2535 break;
2536 case MSR_AMD64_OSVW_ID_LENGTH:
2537 if (!guest_cpuid_has_osvw(vcpu))
2538 return 1;
2539 msr_info->data = vcpu->arch.osvw.length;
2540 break;
2541 case MSR_AMD64_OSVW_STATUS:
2542 if (!guest_cpuid_has_osvw(vcpu))
2543 return 1;
2544 msr_info->data = vcpu->arch.osvw.status;
2545 break;
2546 default:
2547 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2548 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2549 if (!ignore_msrs) {
2550 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2551 msr_info->index);
2552 return 1;
2553 } else {
2554 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2555 msr_info->data = 0;
2556 }
2557 break;
2558 }
2559 return 0;
2560 }
2561 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2562
2563 /*
2564 * Read or write a bunch of msrs. All parameters are kernel addresses.
2565 *
2566 * @return number of msrs set successfully.
2567 */
2568 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2569 struct kvm_msr_entry *entries,
2570 int (*do_msr)(struct kvm_vcpu *vcpu,
2571 unsigned index, u64 *data))
2572 {
2573 int i, idx;
2574
2575 idx = srcu_read_lock(&vcpu->kvm->srcu);
2576 for (i = 0; i < msrs->nmsrs; ++i)
2577 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2578 break;
2579 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2580
2581 return i;
2582 }
2583
2584 /*
2585 * Read or write a bunch of msrs. Parameters are user addresses.
2586 *
2587 * @return number of msrs set successfully.
2588 */
2589 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2590 int (*do_msr)(struct kvm_vcpu *vcpu,
2591 unsigned index, u64 *data),
2592 int writeback)
2593 {
2594 struct kvm_msrs msrs;
2595 struct kvm_msr_entry *entries;
2596 int r, n;
2597 unsigned size;
2598
2599 r = -EFAULT;
2600 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2601 goto out;
2602
2603 r = -E2BIG;
2604 if (msrs.nmsrs >= MAX_IO_MSRS)
2605 goto out;
2606
2607 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2608 entries = memdup_user(user_msrs->entries, size);
2609 if (IS_ERR(entries)) {
2610 r = PTR_ERR(entries);
2611 goto out;
2612 }
2613
2614 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2615 if (r < 0)
2616 goto out_free;
2617
2618 r = -EFAULT;
2619 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2620 goto out_free;
2621
2622 r = n;
2623
2624 out_free:
2625 kfree(entries);
2626 out:
2627 return r;
2628 }
2629
2630 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2631 {
2632 int r;
2633
2634 switch (ext) {
2635 case KVM_CAP_IRQCHIP:
2636 case KVM_CAP_HLT:
2637 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2638 case KVM_CAP_SET_TSS_ADDR:
2639 case KVM_CAP_EXT_CPUID:
2640 case KVM_CAP_EXT_EMUL_CPUID:
2641 case KVM_CAP_CLOCKSOURCE:
2642 case KVM_CAP_PIT:
2643 case KVM_CAP_NOP_IO_DELAY:
2644 case KVM_CAP_MP_STATE:
2645 case KVM_CAP_SYNC_MMU:
2646 case KVM_CAP_USER_NMI:
2647 case KVM_CAP_REINJECT_CONTROL:
2648 case KVM_CAP_IRQ_INJECT_STATUS:
2649 case KVM_CAP_IOEVENTFD:
2650 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2651 case KVM_CAP_PIT2:
2652 case KVM_CAP_PIT_STATE2:
2653 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2654 case KVM_CAP_XEN_HVM:
2655 case KVM_CAP_VCPU_EVENTS:
2656 case KVM_CAP_HYPERV:
2657 case KVM_CAP_HYPERV_VAPIC:
2658 case KVM_CAP_HYPERV_SPIN:
2659 case KVM_CAP_HYPERV_SYNIC:
2660 case KVM_CAP_PCI_SEGMENT:
2661 case KVM_CAP_DEBUGREGS:
2662 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2663 case KVM_CAP_XSAVE:
2664 case KVM_CAP_ASYNC_PF:
2665 case KVM_CAP_GET_TSC_KHZ:
2666 case KVM_CAP_KVMCLOCK_CTRL:
2667 case KVM_CAP_READONLY_MEM:
2668 case KVM_CAP_HYPERV_TIME:
2669 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2670 case KVM_CAP_TSC_DEADLINE_TIMER:
2671 case KVM_CAP_ENABLE_CAP_VM:
2672 case KVM_CAP_DISABLE_QUIRKS:
2673 case KVM_CAP_SET_BOOT_CPU_ID:
2674 case KVM_CAP_SPLIT_IRQCHIP:
2675 case KVM_CAP_IMMEDIATE_EXIT:
2676 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2677 case KVM_CAP_ASSIGN_DEV_IRQ:
2678 case KVM_CAP_PCI_2_3:
2679 #endif
2680 r = 1;
2681 break;
2682 case KVM_CAP_ADJUST_CLOCK:
2683 r = KVM_CLOCK_TSC_STABLE;
2684 break;
2685 case KVM_CAP_X86_SMM:
2686 /* SMBASE is usually relocated above 1M on modern chipsets,
2687 * and SMM handlers might indeed rely on 4G segment limits,
2688 * so do not report SMM to be available if real mode is
2689 * emulated via vm86 mode. Still, do not go to great lengths
2690 * to avoid userspace's usage of the feature, because it is a
2691 * fringe case that is not enabled except via specific settings
2692 * of the module parameters.
2693 */
2694 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2695 break;
2696 case KVM_CAP_COALESCED_MMIO:
2697 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2698 break;
2699 case KVM_CAP_VAPIC:
2700 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2701 break;
2702 case KVM_CAP_NR_VCPUS:
2703 r = KVM_SOFT_MAX_VCPUS;
2704 break;
2705 case KVM_CAP_MAX_VCPUS:
2706 r = KVM_MAX_VCPUS;
2707 break;
2708 case KVM_CAP_NR_MEMSLOTS:
2709 r = KVM_USER_MEM_SLOTS;
2710 break;
2711 case KVM_CAP_PV_MMU: /* obsolete */
2712 r = 0;
2713 break;
2714 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2715 case KVM_CAP_IOMMU:
2716 r = iommu_present(&pci_bus_type);
2717 break;
2718 #endif
2719 case KVM_CAP_MCE:
2720 r = KVM_MAX_MCE_BANKS;
2721 break;
2722 case KVM_CAP_XCRS:
2723 r = boot_cpu_has(X86_FEATURE_XSAVE);
2724 break;
2725 case KVM_CAP_TSC_CONTROL:
2726 r = kvm_has_tsc_control;
2727 break;
2728 case KVM_CAP_X2APIC_API:
2729 r = KVM_X2APIC_API_VALID_FLAGS;
2730 break;
2731 default:
2732 r = 0;
2733 break;
2734 }
2735 return r;
2736
2737 }
2738
2739 long kvm_arch_dev_ioctl(struct file *filp,
2740 unsigned int ioctl, unsigned long arg)
2741 {
2742 void __user *argp = (void __user *)arg;
2743 long r;
2744
2745 switch (ioctl) {
2746 case KVM_GET_MSR_INDEX_LIST: {
2747 struct kvm_msr_list __user *user_msr_list = argp;
2748 struct kvm_msr_list msr_list;
2749 unsigned n;
2750
2751 r = -EFAULT;
2752 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2753 goto out;
2754 n = msr_list.nmsrs;
2755 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2756 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2757 goto out;
2758 r = -E2BIG;
2759 if (n < msr_list.nmsrs)
2760 goto out;
2761 r = -EFAULT;
2762 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2763 num_msrs_to_save * sizeof(u32)))
2764 goto out;
2765 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2766 &emulated_msrs,
2767 num_emulated_msrs * sizeof(u32)))
2768 goto out;
2769 r = 0;
2770 break;
2771 }
2772 case KVM_GET_SUPPORTED_CPUID:
2773 case KVM_GET_EMULATED_CPUID: {
2774 struct kvm_cpuid2 __user *cpuid_arg = argp;
2775 struct kvm_cpuid2 cpuid;
2776
2777 r = -EFAULT;
2778 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2779 goto out;
2780
2781 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2782 ioctl);
2783 if (r)
2784 goto out;
2785
2786 r = -EFAULT;
2787 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2788 goto out;
2789 r = 0;
2790 break;
2791 }
2792 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2793 r = -EFAULT;
2794 if (copy_to_user(argp, &kvm_mce_cap_supported,
2795 sizeof(kvm_mce_cap_supported)))
2796 goto out;
2797 r = 0;
2798 break;
2799 }
2800 default:
2801 r = -EINVAL;
2802 }
2803 out:
2804 return r;
2805 }
2806
2807 static void wbinvd_ipi(void *garbage)
2808 {
2809 wbinvd();
2810 }
2811
2812 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2813 {
2814 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2815 }
2816
2817 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2818 {
2819 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2820 }
2821
2822 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2823 {
2824 /* Address WBINVD may be executed by guest */
2825 if (need_emulate_wbinvd(vcpu)) {
2826 if (kvm_x86_ops->has_wbinvd_exit())
2827 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2828 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2829 smp_call_function_single(vcpu->cpu,
2830 wbinvd_ipi, NULL, 1);
2831 }
2832
2833 kvm_x86_ops->vcpu_load(vcpu, cpu);
2834
2835 /* Apply any externally detected TSC adjustments (due to suspend) */
2836 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2837 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2838 vcpu->arch.tsc_offset_adjustment = 0;
2839 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2840 }
2841
2842 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2843 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2844 rdtsc() - vcpu->arch.last_host_tsc;
2845 if (tsc_delta < 0)
2846 mark_tsc_unstable("KVM discovered backwards TSC");
2847
2848 if (check_tsc_unstable()) {
2849 u64 offset = kvm_compute_tsc_offset(vcpu,
2850 vcpu->arch.last_guest_tsc);
2851 kvm_vcpu_write_tsc_offset(vcpu, offset);
2852 vcpu->arch.tsc_catchup = 1;
2853 }
2854 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2855 kvm_x86_ops->set_hv_timer(vcpu,
2856 kvm_get_lapic_target_expiration_tsc(vcpu)))
2857 kvm_lapic_switch_to_sw_timer(vcpu);
2858 /*
2859 * On a host with synchronized TSC, there is no need to update
2860 * kvmclock on vcpu->cpu migration
2861 */
2862 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2863 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2864 if (vcpu->cpu != cpu)
2865 kvm_migrate_timers(vcpu);
2866 vcpu->cpu = cpu;
2867 }
2868
2869 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2870 }
2871
2872 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2873 {
2874 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2875 return;
2876
2877 vcpu->arch.st.steal.preempted = 1;
2878
2879 kvm_vcpu_write_guest_offset_cached(vcpu, &vcpu->arch.st.stime,
2880 &vcpu->arch.st.steal.preempted,
2881 offsetof(struct kvm_steal_time, preempted),
2882 sizeof(vcpu->arch.st.steal.preempted));
2883 }
2884
2885 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2886 {
2887 int idx;
2888 /*
2889 * Disable page faults because we're in atomic context here.
2890 * kvm_write_guest_offset_cached() would call might_fault()
2891 * that relies on pagefault_disable() to tell if there's a
2892 * bug. NOTE: the write to guest memory may not go through if
2893 * during postcopy live migration or if there's heavy guest
2894 * paging.
2895 */
2896 pagefault_disable();
2897 /*
2898 * kvm_memslots() will be called by
2899 * kvm_write_guest_offset_cached() so take the srcu lock.
2900 */
2901 idx = srcu_read_lock(&vcpu->kvm->srcu);
2902 kvm_steal_time_set_preempted(vcpu);
2903 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2904 pagefault_enable();
2905 kvm_x86_ops->vcpu_put(vcpu);
2906 kvm_put_guest_fpu(vcpu);
2907 vcpu->arch.last_host_tsc = rdtsc();
2908 }
2909
2910 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2911 struct kvm_lapic_state *s)
2912 {
2913 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
2914 kvm_x86_ops->sync_pir_to_irr(vcpu);
2915
2916 return kvm_apic_get_state(vcpu, s);
2917 }
2918
2919 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2920 struct kvm_lapic_state *s)
2921 {
2922 int r;
2923
2924 r = kvm_apic_set_state(vcpu, s);
2925 if (r)
2926 return r;
2927 update_cr8_intercept(vcpu);
2928
2929 return 0;
2930 }
2931
2932 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2933 {
2934 return (!lapic_in_kernel(vcpu) ||
2935 kvm_apic_accept_pic_intr(vcpu));
2936 }
2937
2938 /*
2939 * if userspace requested an interrupt window, check that the
2940 * interrupt window is open.
2941 *
2942 * No need to exit to userspace if we already have an interrupt queued.
2943 */
2944 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2945 {
2946 return kvm_arch_interrupt_allowed(vcpu) &&
2947 !kvm_cpu_has_interrupt(vcpu) &&
2948 !kvm_event_needs_reinjection(vcpu) &&
2949 kvm_cpu_accept_dm_intr(vcpu);
2950 }
2951
2952 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2953 struct kvm_interrupt *irq)
2954 {
2955 if (irq->irq >= KVM_NR_INTERRUPTS)
2956 return -EINVAL;
2957
2958 if (!irqchip_in_kernel(vcpu->kvm)) {
2959 kvm_queue_interrupt(vcpu, irq->irq, false);
2960 kvm_make_request(KVM_REQ_EVENT, vcpu);
2961 return 0;
2962 }
2963
2964 /*
2965 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2966 * fail for in-kernel 8259.
2967 */
2968 if (pic_in_kernel(vcpu->kvm))
2969 return -ENXIO;
2970
2971 if (vcpu->arch.pending_external_vector != -1)
2972 return -EEXIST;
2973
2974 vcpu->arch.pending_external_vector = irq->irq;
2975 kvm_make_request(KVM_REQ_EVENT, vcpu);
2976 return 0;
2977 }
2978
2979 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2980 {
2981 kvm_inject_nmi(vcpu);
2982
2983 return 0;
2984 }
2985
2986 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2987 {
2988 kvm_make_request(KVM_REQ_SMI, vcpu);
2989
2990 return 0;
2991 }
2992
2993 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2994 struct kvm_tpr_access_ctl *tac)
2995 {
2996 if (tac->flags)
2997 return -EINVAL;
2998 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2999 return 0;
3000 }
3001
3002 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3003 u64 mcg_cap)
3004 {
3005 int r;
3006 unsigned bank_num = mcg_cap & 0xff, bank;
3007
3008 r = -EINVAL;
3009 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3010 goto out;
3011 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3012 goto out;
3013 r = 0;
3014 vcpu->arch.mcg_cap = mcg_cap;
3015 /* Init IA32_MCG_CTL to all 1s */
3016 if (mcg_cap & MCG_CTL_P)
3017 vcpu->arch.mcg_ctl = ~(u64)0;
3018 /* Init IA32_MCi_CTL to all 1s */
3019 for (bank = 0; bank < bank_num; bank++)
3020 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3021
3022 if (kvm_x86_ops->setup_mce)
3023 kvm_x86_ops->setup_mce(vcpu);
3024 out:
3025 return r;
3026 }
3027
3028 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3029 struct kvm_x86_mce *mce)
3030 {
3031 u64 mcg_cap = vcpu->arch.mcg_cap;
3032 unsigned bank_num = mcg_cap & 0xff;
3033 u64 *banks = vcpu->arch.mce_banks;
3034
3035 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3036 return -EINVAL;
3037 /*
3038 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3039 * reporting is disabled
3040 */
3041 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3042 vcpu->arch.mcg_ctl != ~(u64)0)
3043 return 0;
3044 banks += 4 * mce->bank;
3045 /*
3046 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3047 * reporting is disabled for the bank
3048 */
3049 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3050 return 0;
3051 if (mce->status & MCI_STATUS_UC) {
3052 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3053 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3054 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3055 return 0;
3056 }
3057 if (banks[1] & MCI_STATUS_VAL)
3058 mce->status |= MCI_STATUS_OVER;
3059 banks[2] = mce->addr;
3060 banks[3] = mce->misc;
3061 vcpu->arch.mcg_status = mce->mcg_status;
3062 banks[1] = mce->status;
3063 kvm_queue_exception(vcpu, MC_VECTOR);
3064 } else if (!(banks[1] & MCI_STATUS_VAL)
3065 || !(banks[1] & MCI_STATUS_UC)) {
3066 if (banks[1] & MCI_STATUS_VAL)
3067 mce->status |= MCI_STATUS_OVER;
3068 banks[2] = mce->addr;
3069 banks[3] = mce->misc;
3070 banks[1] = mce->status;
3071 } else
3072 banks[1] |= MCI_STATUS_OVER;
3073 return 0;
3074 }
3075
3076 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3077 struct kvm_vcpu_events *events)
3078 {
3079 process_nmi(vcpu);
3080 events->exception.injected =
3081 vcpu->arch.exception.pending &&
3082 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3083 events->exception.nr = vcpu->arch.exception.nr;
3084 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3085 events->exception.pad = 0;
3086 events->exception.error_code = vcpu->arch.exception.error_code;
3087
3088 events->interrupt.injected =
3089 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3090 events->interrupt.nr = vcpu->arch.interrupt.nr;
3091 events->interrupt.soft = 0;
3092 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3093
3094 events->nmi.injected = vcpu->arch.nmi_injected;
3095 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3096 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3097 events->nmi.pad = 0;
3098
3099 events->sipi_vector = 0; /* never valid when reporting to user space */
3100
3101 events->smi.smm = is_smm(vcpu);
3102 events->smi.pending = vcpu->arch.smi_pending;
3103 events->smi.smm_inside_nmi =
3104 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3105 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3106
3107 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3108 | KVM_VCPUEVENT_VALID_SHADOW
3109 | KVM_VCPUEVENT_VALID_SMM);
3110 memset(&events->reserved, 0, sizeof(events->reserved));
3111 }
3112
3113 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3114
3115 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3116 struct kvm_vcpu_events *events)
3117 {
3118 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3119 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3120 | KVM_VCPUEVENT_VALID_SHADOW
3121 | KVM_VCPUEVENT_VALID_SMM))
3122 return -EINVAL;
3123
3124 if (events->exception.injected &&
3125 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3126 return -EINVAL;
3127
3128 process_nmi(vcpu);
3129 vcpu->arch.exception.pending = events->exception.injected;
3130 vcpu->arch.exception.nr = events->exception.nr;
3131 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3132 vcpu->arch.exception.error_code = events->exception.error_code;
3133
3134 vcpu->arch.interrupt.pending = events->interrupt.injected;
3135 vcpu->arch.interrupt.nr = events->interrupt.nr;
3136 vcpu->arch.interrupt.soft = events->interrupt.soft;
3137 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3138 kvm_x86_ops->set_interrupt_shadow(vcpu,
3139 events->interrupt.shadow);
3140
3141 vcpu->arch.nmi_injected = events->nmi.injected;
3142 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3143 vcpu->arch.nmi_pending = events->nmi.pending;
3144 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3145
3146 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3147 lapic_in_kernel(vcpu))
3148 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3149
3150 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3151 u32 hflags = vcpu->arch.hflags;
3152 if (events->smi.smm)
3153 hflags |= HF_SMM_MASK;
3154 else
3155 hflags &= ~HF_SMM_MASK;
3156 kvm_set_hflags(vcpu, hflags);
3157
3158 vcpu->arch.smi_pending = events->smi.pending;
3159 if (events->smi.smm_inside_nmi)
3160 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3161 else
3162 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3163 if (lapic_in_kernel(vcpu)) {
3164 if (events->smi.latched_init)
3165 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3166 else
3167 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3168 }
3169 }
3170
3171 kvm_make_request(KVM_REQ_EVENT, vcpu);
3172
3173 return 0;
3174 }
3175
3176 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3177 struct kvm_debugregs *dbgregs)
3178 {
3179 unsigned long val;
3180
3181 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3182 kvm_get_dr(vcpu, 6, &val);
3183 dbgregs->dr6 = val;
3184 dbgregs->dr7 = vcpu->arch.dr7;
3185 dbgregs->flags = 0;
3186 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3187 }
3188
3189 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3190 struct kvm_debugregs *dbgregs)
3191 {
3192 if (dbgregs->flags)
3193 return -EINVAL;
3194
3195 if (dbgregs->dr6 & ~0xffffffffull)
3196 return -EINVAL;
3197 if (dbgregs->dr7 & ~0xffffffffull)
3198 return -EINVAL;
3199
3200 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3201 kvm_update_dr0123(vcpu);
3202 vcpu->arch.dr6 = dbgregs->dr6;
3203 kvm_update_dr6(vcpu);
3204 vcpu->arch.dr7 = dbgregs->dr7;
3205 kvm_update_dr7(vcpu);
3206
3207 return 0;
3208 }
3209
3210 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3211
3212 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3213 {
3214 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3215 u64 xstate_bv = xsave->header.xfeatures;
3216 u64 valid;
3217
3218 /*
3219 * Copy legacy XSAVE area, to avoid complications with CPUID
3220 * leaves 0 and 1 in the loop below.
3221 */
3222 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3223
3224 /* Set XSTATE_BV */
3225 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3226
3227 /*
3228 * Copy each region from the possibly compacted offset to the
3229 * non-compacted offset.
3230 */
3231 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3232 while (valid) {
3233 u64 feature = valid & -valid;
3234 int index = fls64(feature) - 1;
3235 void *src = get_xsave_addr(xsave, feature);
3236
3237 if (src) {
3238 u32 size, offset, ecx, edx;
3239 cpuid_count(XSTATE_CPUID, index,
3240 &size, &offset, &ecx, &edx);
3241 memcpy(dest + offset, src, size);
3242 }
3243
3244 valid -= feature;
3245 }
3246 }
3247
3248 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3249 {
3250 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3251 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3252 u64 valid;
3253
3254 /*
3255 * Copy legacy XSAVE area, to avoid complications with CPUID
3256 * leaves 0 and 1 in the loop below.
3257 */
3258 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3259
3260 /* Set XSTATE_BV and possibly XCOMP_BV. */
3261 xsave->header.xfeatures = xstate_bv;
3262 if (boot_cpu_has(X86_FEATURE_XSAVES))
3263 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3264
3265 /*
3266 * Copy each region from the non-compacted offset to the
3267 * possibly compacted offset.
3268 */
3269 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3270 while (valid) {
3271 u64 feature = valid & -valid;
3272 int index = fls64(feature) - 1;
3273 void *dest = get_xsave_addr(xsave, feature);
3274
3275 if (dest) {
3276 u32 size, offset, ecx, edx;
3277 cpuid_count(XSTATE_CPUID, index,
3278 &size, &offset, &ecx, &edx);
3279 memcpy(dest, src + offset, size);
3280 }
3281
3282 valid -= feature;
3283 }
3284 }
3285
3286 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3287 struct kvm_xsave *guest_xsave)
3288 {
3289 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3290 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3291 fill_xsave((u8 *) guest_xsave->region, vcpu);
3292 } else {
3293 memcpy(guest_xsave->region,
3294 &vcpu->arch.guest_fpu.state.fxsave,
3295 sizeof(struct fxregs_state));
3296 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3297 XFEATURE_MASK_FPSSE;
3298 }
3299 }
3300
3301 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3302 struct kvm_xsave *guest_xsave)
3303 {
3304 u64 xstate_bv =
3305 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3306
3307 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3308 /*
3309 * Here we allow setting states that are not present in
3310 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3311 * with old userspace.
3312 */
3313 if (xstate_bv & ~kvm_supported_xcr0())
3314 return -EINVAL;
3315 load_xsave(vcpu, (u8 *)guest_xsave->region);
3316 } else {
3317 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
3318 return -EINVAL;
3319 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3320 guest_xsave->region, sizeof(struct fxregs_state));
3321 }
3322 return 0;
3323 }
3324
3325 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3326 struct kvm_xcrs *guest_xcrs)
3327 {
3328 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3329 guest_xcrs->nr_xcrs = 0;
3330 return;
3331 }
3332
3333 guest_xcrs->nr_xcrs = 1;
3334 guest_xcrs->flags = 0;
3335 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3336 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3337 }
3338
3339 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3340 struct kvm_xcrs *guest_xcrs)
3341 {
3342 int i, r = 0;
3343
3344 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3345 return -EINVAL;
3346
3347 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3348 return -EINVAL;
3349
3350 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3351 /* Only support XCR0 currently */
3352 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3353 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3354 guest_xcrs->xcrs[i].value);
3355 break;
3356 }
3357 if (r)
3358 r = -EINVAL;
3359 return r;
3360 }
3361
3362 /*
3363 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3364 * stopped by the hypervisor. This function will be called from the host only.
3365 * EINVAL is returned when the host attempts to set the flag for a guest that
3366 * does not support pv clocks.
3367 */
3368 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3369 {
3370 if (!vcpu->arch.pv_time_enabled)
3371 return -EINVAL;
3372 vcpu->arch.pvclock_set_guest_stopped_request = true;
3373 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3374 return 0;
3375 }
3376
3377 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3378 struct kvm_enable_cap *cap)
3379 {
3380 if (cap->flags)
3381 return -EINVAL;
3382
3383 switch (cap->cap) {
3384 case KVM_CAP_HYPERV_SYNIC:
3385 if (!irqchip_in_kernel(vcpu->kvm))
3386 return -EINVAL;
3387 return kvm_hv_activate_synic(vcpu);
3388 default:
3389 return -EINVAL;
3390 }
3391 }
3392
3393 long kvm_arch_vcpu_ioctl(struct file *filp,
3394 unsigned int ioctl, unsigned long arg)
3395 {
3396 struct kvm_vcpu *vcpu = filp->private_data;
3397 void __user *argp = (void __user *)arg;
3398 int r;
3399 union {
3400 struct kvm_lapic_state *lapic;
3401 struct kvm_xsave *xsave;
3402 struct kvm_xcrs *xcrs;
3403 void *buffer;
3404 } u;
3405
3406 u.buffer = NULL;
3407 switch (ioctl) {
3408 case KVM_GET_LAPIC: {
3409 r = -EINVAL;
3410 if (!lapic_in_kernel(vcpu))
3411 goto out;
3412 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3413
3414 r = -ENOMEM;
3415 if (!u.lapic)
3416 goto out;
3417 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3418 if (r)
3419 goto out;
3420 r = -EFAULT;
3421 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3422 goto out;
3423 r = 0;
3424 break;
3425 }
3426 case KVM_SET_LAPIC: {
3427 r = -EINVAL;
3428 if (!lapic_in_kernel(vcpu))
3429 goto out;
3430 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3431 if (IS_ERR(u.lapic))
3432 return PTR_ERR(u.lapic);
3433
3434 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3435 break;
3436 }
3437 case KVM_INTERRUPT: {
3438 struct kvm_interrupt irq;
3439
3440 r = -EFAULT;
3441 if (copy_from_user(&irq, argp, sizeof irq))
3442 goto out;
3443 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3444 break;
3445 }
3446 case KVM_NMI: {
3447 r = kvm_vcpu_ioctl_nmi(vcpu);
3448 break;
3449 }
3450 case KVM_SMI: {
3451 r = kvm_vcpu_ioctl_smi(vcpu);
3452 break;
3453 }
3454 case KVM_SET_CPUID: {
3455 struct kvm_cpuid __user *cpuid_arg = argp;
3456 struct kvm_cpuid cpuid;
3457
3458 r = -EFAULT;
3459 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3460 goto out;
3461 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3462 break;
3463 }
3464 case KVM_SET_CPUID2: {
3465 struct kvm_cpuid2 __user *cpuid_arg = argp;
3466 struct kvm_cpuid2 cpuid;
3467
3468 r = -EFAULT;
3469 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3470 goto out;
3471 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3472 cpuid_arg->entries);
3473 break;
3474 }
3475 case KVM_GET_CPUID2: {
3476 struct kvm_cpuid2 __user *cpuid_arg = argp;
3477 struct kvm_cpuid2 cpuid;
3478
3479 r = -EFAULT;
3480 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3481 goto out;
3482 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3483 cpuid_arg->entries);
3484 if (r)
3485 goto out;
3486 r = -EFAULT;
3487 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3488 goto out;
3489 r = 0;
3490 break;
3491 }
3492 case KVM_GET_MSRS:
3493 r = msr_io(vcpu, argp, do_get_msr, 1);
3494 break;
3495 case KVM_SET_MSRS:
3496 r = msr_io(vcpu, argp, do_set_msr, 0);
3497 break;
3498 case KVM_TPR_ACCESS_REPORTING: {
3499 struct kvm_tpr_access_ctl tac;
3500
3501 r = -EFAULT;
3502 if (copy_from_user(&tac, argp, sizeof tac))
3503 goto out;
3504 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3505 if (r)
3506 goto out;
3507 r = -EFAULT;
3508 if (copy_to_user(argp, &tac, sizeof tac))
3509 goto out;
3510 r = 0;
3511 break;
3512 };
3513 case KVM_SET_VAPIC_ADDR: {
3514 struct kvm_vapic_addr va;
3515 int idx;
3516
3517 r = -EINVAL;
3518 if (!lapic_in_kernel(vcpu))
3519 goto out;
3520 r = -EFAULT;
3521 if (copy_from_user(&va, argp, sizeof va))
3522 goto out;
3523 idx = srcu_read_lock(&vcpu->kvm->srcu);
3524 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3525 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3526 break;
3527 }
3528 case KVM_X86_SETUP_MCE: {
3529 u64 mcg_cap;
3530
3531 r = -EFAULT;
3532 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3533 goto out;
3534 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3535 break;
3536 }
3537 case KVM_X86_SET_MCE: {
3538 struct kvm_x86_mce mce;
3539
3540 r = -EFAULT;
3541 if (copy_from_user(&mce, argp, sizeof mce))
3542 goto out;
3543 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3544 break;
3545 }
3546 case KVM_GET_VCPU_EVENTS: {
3547 struct kvm_vcpu_events events;
3548
3549 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3550
3551 r = -EFAULT;
3552 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3553 break;
3554 r = 0;
3555 break;
3556 }
3557 case KVM_SET_VCPU_EVENTS: {
3558 struct kvm_vcpu_events events;
3559
3560 r = -EFAULT;
3561 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3562 break;
3563
3564 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3565 break;
3566 }
3567 case KVM_GET_DEBUGREGS: {
3568 struct kvm_debugregs dbgregs;
3569
3570 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3571
3572 r = -EFAULT;
3573 if (copy_to_user(argp, &dbgregs,
3574 sizeof(struct kvm_debugregs)))
3575 break;
3576 r = 0;
3577 break;
3578 }
3579 case KVM_SET_DEBUGREGS: {
3580 struct kvm_debugregs dbgregs;
3581
3582 r = -EFAULT;
3583 if (copy_from_user(&dbgregs, argp,
3584 sizeof(struct kvm_debugregs)))
3585 break;
3586
3587 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3588 break;
3589 }
3590 case KVM_GET_XSAVE: {
3591 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3592 r = -ENOMEM;
3593 if (!u.xsave)
3594 break;
3595
3596 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3597
3598 r = -EFAULT;
3599 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3600 break;
3601 r = 0;
3602 break;
3603 }
3604 case KVM_SET_XSAVE: {
3605 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3606 if (IS_ERR(u.xsave))
3607 return PTR_ERR(u.xsave);
3608
3609 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3610 break;
3611 }
3612 case KVM_GET_XCRS: {
3613 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3614 r = -ENOMEM;
3615 if (!u.xcrs)
3616 break;
3617
3618 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3619
3620 r = -EFAULT;
3621 if (copy_to_user(argp, u.xcrs,
3622 sizeof(struct kvm_xcrs)))
3623 break;
3624 r = 0;
3625 break;
3626 }
3627 case KVM_SET_XCRS: {
3628 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3629 if (IS_ERR(u.xcrs))
3630 return PTR_ERR(u.xcrs);
3631
3632 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3633 break;
3634 }
3635 case KVM_SET_TSC_KHZ: {
3636 u32 user_tsc_khz;
3637
3638 r = -EINVAL;
3639 user_tsc_khz = (u32)arg;
3640
3641 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3642 goto out;
3643
3644 if (user_tsc_khz == 0)
3645 user_tsc_khz = tsc_khz;
3646
3647 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3648 r = 0;
3649
3650 goto out;
3651 }
3652 case KVM_GET_TSC_KHZ: {
3653 r = vcpu->arch.virtual_tsc_khz;
3654 goto out;
3655 }
3656 case KVM_KVMCLOCK_CTRL: {
3657 r = kvm_set_guest_paused(vcpu);
3658 goto out;
3659 }
3660 case KVM_ENABLE_CAP: {
3661 struct kvm_enable_cap cap;
3662
3663 r = -EFAULT;
3664 if (copy_from_user(&cap, argp, sizeof(cap)))
3665 goto out;
3666 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3667 break;
3668 }
3669 default:
3670 r = -EINVAL;
3671 }
3672 out:
3673 kfree(u.buffer);
3674 return r;
3675 }
3676
3677 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3678 {
3679 return VM_FAULT_SIGBUS;
3680 }
3681
3682 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3683 {
3684 int ret;
3685
3686 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3687 return -EINVAL;
3688 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3689 return ret;
3690 }
3691
3692 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3693 u64 ident_addr)
3694 {
3695 kvm->arch.ept_identity_map_addr = ident_addr;
3696 return 0;
3697 }
3698
3699 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3700 u32 kvm_nr_mmu_pages)
3701 {
3702 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3703 return -EINVAL;
3704
3705 mutex_lock(&kvm->slots_lock);
3706
3707 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3708 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3709
3710 mutex_unlock(&kvm->slots_lock);
3711 return 0;
3712 }
3713
3714 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3715 {
3716 return kvm->arch.n_max_mmu_pages;
3717 }
3718
3719 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3720 {
3721 int r;
3722
3723 r = 0;
3724 switch (chip->chip_id) {
3725 case KVM_IRQCHIP_PIC_MASTER:
3726 memcpy(&chip->chip.pic,
3727 &pic_irqchip(kvm)->pics[0],
3728 sizeof(struct kvm_pic_state));
3729 break;
3730 case KVM_IRQCHIP_PIC_SLAVE:
3731 memcpy(&chip->chip.pic,
3732 &pic_irqchip(kvm)->pics[1],
3733 sizeof(struct kvm_pic_state));
3734 break;
3735 case KVM_IRQCHIP_IOAPIC:
3736 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3737 break;
3738 default:
3739 r = -EINVAL;
3740 break;
3741 }
3742 return r;
3743 }
3744
3745 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3746 {
3747 int r;
3748
3749 r = 0;
3750 switch (chip->chip_id) {
3751 case KVM_IRQCHIP_PIC_MASTER:
3752 spin_lock(&pic_irqchip(kvm)->lock);
3753 memcpy(&pic_irqchip(kvm)->pics[0],
3754 &chip->chip.pic,
3755 sizeof(struct kvm_pic_state));
3756 spin_unlock(&pic_irqchip(kvm)->lock);
3757 break;
3758 case KVM_IRQCHIP_PIC_SLAVE:
3759 spin_lock(&pic_irqchip(kvm)->lock);
3760 memcpy(&pic_irqchip(kvm)->pics[1],
3761 &chip->chip.pic,
3762 sizeof(struct kvm_pic_state));
3763 spin_unlock(&pic_irqchip(kvm)->lock);
3764 break;
3765 case KVM_IRQCHIP_IOAPIC:
3766 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3767 break;
3768 default:
3769 r = -EINVAL;
3770 break;
3771 }
3772 kvm_pic_update_irq(pic_irqchip(kvm));
3773 return r;
3774 }
3775
3776 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3777 {
3778 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3779
3780 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3781
3782 mutex_lock(&kps->lock);
3783 memcpy(ps, &kps->channels, sizeof(*ps));
3784 mutex_unlock(&kps->lock);
3785 return 0;
3786 }
3787
3788 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3789 {
3790 int i;
3791 struct kvm_pit *pit = kvm->arch.vpit;
3792
3793 mutex_lock(&pit->pit_state.lock);
3794 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
3795 for (i = 0; i < 3; i++)
3796 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3797 mutex_unlock(&pit->pit_state.lock);
3798 return 0;
3799 }
3800
3801 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3802 {
3803 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3804 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3805 sizeof(ps->channels));
3806 ps->flags = kvm->arch.vpit->pit_state.flags;
3807 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3808 memset(&ps->reserved, 0, sizeof(ps->reserved));
3809 return 0;
3810 }
3811
3812 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3813 {
3814 int start = 0;
3815 int i;
3816 u32 prev_legacy, cur_legacy;
3817 struct kvm_pit *pit = kvm->arch.vpit;
3818
3819 mutex_lock(&pit->pit_state.lock);
3820 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3821 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3822 if (!prev_legacy && cur_legacy)
3823 start = 1;
3824 memcpy(&pit->pit_state.channels, &ps->channels,
3825 sizeof(pit->pit_state.channels));
3826 pit->pit_state.flags = ps->flags;
3827 for (i = 0; i < 3; i++)
3828 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
3829 start && i == 0);
3830 mutex_unlock(&pit->pit_state.lock);
3831 return 0;
3832 }
3833
3834 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3835 struct kvm_reinject_control *control)
3836 {
3837 struct kvm_pit *pit = kvm->arch.vpit;
3838
3839 if (!pit)
3840 return -ENXIO;
3841
3842 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3843 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3844 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3845 */
3846 mutex_lock(&pit->pit_state.lock);
3847 kvm_pit_set_reinject(pit, control->pit_reinject);
3848 mutex_unlock(&pit->pit_state.lock);
3849
3850 return 0;
3851 }
3852
3853 /**
3854 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3855 * @kvm: kvm instance
3856 * @log: slot id and address to which we copy the log
3857 *
3858 * Steps 1-4 below provide general overview of dirty page logging. See
3859 * kvm_get_dirty_log_protect() function description for additional details.
3860 *
3861 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3862 * always flush the TLB (step 4) even if previous step failed and the dirty
3863 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3864 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3865 * writes will be marked dirty for next log read.
3866 *
3867 * 1. Take a snapshot of the bit and clear it if needed.
3868 * 2. Write protect the corresponding page.
3869 * 3. Copy the snapshot to the userspace.
3870 * 4. Flush TLB's if needed.
3871 */
3872 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3873 {
3874 bool is_dirty = false;
3875 int r;
3876
3877 mutex_lock(&kvm->slots_lock);
3878
3879 /*
3880 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3881 */
3882 if (kvm_x86_ops->flush_log_dirty)
3883 kvm_x86_ops->flush_log_dirty(kvm);
3884
3885 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3886
3887 /*
3888 * All the TLBs can be flushed out of mmu lock, see the comments in
3889 * kvm_mmu_slot_remove_write_access().
3890 */
3891 lockdep_assert_held(&kvm->slots_lock);
3892 if (is_dirty)
3893 kvm_flush_remote_tlbs(kvm);
3894
3895 mutex_unlock(&kvm->slots_lock);
3896 return r;
3897 }
3898
3899 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3900 bool line_status)
3901 {
3902 if (!irqchip_in_kernel(kvm))
3903 return -ENXIO;
3904
3905 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3906 irq_event->irq, irq_event->level,
3907 line_status);
3908 return 0;
3909 }
3910
3911 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3912 struct kvm_enable_cap *cap)
3913 {
3914 int r;
3915
3916 if (cap->flags)
3917 return -EINVAL;
3918
3919 switch (cap->cap) {
3920 case KVM_CAP_DISABLE_QUIRKS:
3921 kvm->arch.disabled_quirks = cap->args[0];
3922 r = 0;
3923 break;
3924 case KVM_CAP_SPLIT_IRQCHIP: {
3925 mutex_lock(&kvm->lock);
3926 r = -EINVAL;
3927 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3928 goto split_irqchip_unlock;
3929 r = -EEXIST;
3930 if (irqchip_in_kernel(kvm))
3931 goto split_irqchip_unlock;
3932 if (kvm->created_vcpus)
3933 goto split_irqchip_unlock;
3934 r = kvm_setup_empty_irq_routing(kvm);
3935 if (r)
3936 goto split_irqchip_unlock;
3937 /* Pairs with irqchip_in_kernel. */
3938 smp_wmb();
3939 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
3940 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3941 r = 0;
3942 split_irqchip_unlock:
3943 mutex_unlock(&kvm->lock);
3944 break;
3945 }
3946 case KVM_CAP_X2APIC_API:
3947 r = -EINVAL;
3948 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3949 break;
3950
3951 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3952 kvm->arch.x2apic_format = true;
3953 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3954 kvm->arch.x2apic_broadcast_quirk_disabled = true;
3955
3956 r = 0;
3957 break;
3958 default:
3959 r = -EINVAL;
3960 break;
3961 }
3962 return r;
3963 }
3964
3965 long kvm_arch_vm_ioctl(struct file *filp,
3966 unsigned int ioctl, unsigned long arg)
3967 {
3968 struct kvm *kvm = filp->private_data;
3969 void __user *argp = (void __user *)arg;
3970 int r = -ENOTTY;
3971 /*
3972 * This union makes it completely explicit to gcc-3.x
3973 * that these two variables' stack usage should be
3974 * combined, not added together.
3975 */
3976 union {
3977 struct kvm_pit_state ps;
3978 struct kvm_pit_state2 ps2;
3979 struct kvm_pit_config pit_config;
3980 } u;
3981
3982 switch (ioctl) {
3983 case KVM_SET_TSS_ADDR:
3984 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3985 break;
3986 case KVM_SET_IDENTITY_MAP_ADDR: {
3987 u64 ident_addr;
3988
3989 r = -EFAULT;
3990 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3991 goto out;
3992 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3993 break;
3994 }
3995 case KVM_SET_NR_MMU_PAGES:
3996 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3997 break;
3998 case KVM_GET_NR_MMU_PAGES:
3999 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4000 break;
4001 case KVM_CREATE_IRQCHIP: {
4002 mutex_lock(&kvm->lock);
4003
4004 r = -EEXIST;
4005 if (irqchip_in_kernel(kvm))
4006 goto create_irqchip_unlock;
4007
4008 r = -EINVAL;
4009 if (kvm->created_vcpus)
4010 goto create_irqchip_unlock;
4011
4012 r = kvm_pic_init(kvm);
4013 if (r)
4014 goto create_irqchip_unlock;
4015
4016 r = kvm_ioapic_init(kvm);
4017 if (r) {
4018 mutex_lock(&kvm->slots_lock);
4019 kvm_pic_destroy(kvm);
4020 mutex_unlock(&kvm->slots_lock);
4021 goto create_irqchip_unlock;
4022 }
4023
4024 r = kvm_setup_default_irq_routing(kvm);
4025 if (r) {
4026 mutex_lock(&kvm->slots_lock);
4027 mutex_lock(&kvm->irq_lock);
4028 kvm_ioapic_destroy(kvm);
4029 kvm_pic_destroy(kvm);
4030 mutex_unlock(&kvm->irq_lock);
4031 mutex_unlock(&kvm->slots_lock);
4032 goto create_irqchip_unlock;
4033 }
4034 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4035 smp_wmb();
4036 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4037 create_irqchip_unlock:
4038 mutex_unlock(&kvm->lock);
4039 break;
4040 }
4041 case KVM_CREATE_PIT:
4042 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4043 goto create_pit;
4044 case KVM_CREATE_PIT2:
4045 r = -EFAULT;
4046 if (copy_from_user(&u.pit_config, argp,
4047 sizeof(struct kvm_pit_config)))
4048 goto out;
4049 create_pit:
4050 mutex_lock(&kvm->lock);
4051 r = -EEXIST;
4052 if (kvm->arch.vpit)
4053 goto create_pit_unlock;
4054 r = -ENOMEM;
4055 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4056 if (kvm->arch.vpit)
4057 r = 0;
4058 create_pit_unlock:
4059 mutex_unlock(&kvm->lock);
4060 break;
4061 case KVM_GET_IRQCHIP: {
4062 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4063 struct kvm_irqchip *chip;
4064
4065 chip = memdup_user(argp, sizeof(*chip));
4066 if (IS_ERR(chip)) {
4067 r = PTR_ERR(chip);
4068 goto out;
4069 }
4070
4071 r = -ENXIO;
4072 if (!irqchip_kernel(kvm))
4073 goto get_irqchip_out;
4074 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4075 if (r)
4076 goto get_irqchip_out;
4077 r = -EFAULT;
4078 if (copy_to_user(argp, chip, sizeof *chip))
4079 goto get_irqchip_out;
4080 r = 0;
4081 get_irqchip_out:
4082 kfree(chip);
4083 break;
4084 }
4085 case KVM_SET_IRQCHIP: {
4086 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4087 struct kvm_irqchip *chip;
4088
4089 chip = memdup_user(argp, sizeof(*chip));
4090 if (IS_ERR(chip)) {
4091 r = PTR_ERR(chip);
4092 goto out;
4093 }
4094
4095 r = -ENXIO;
4096 if (!irqchip_kernel(kvm))
4097 goto set_irqchip_out;
4098 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4099 if (r)
4100 goto set_irqchip_out;
4101 r = 0;
4102 set_irqchip_out:
4103 kfree(chip);
4104 break;
4105 }
4106 case KVM_GET_PIT: {
4107 r = -EFAULT;
4108 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4109 goto out;
4110 r = -ENXIO;
4111 if (!kvm->arch.vpit)
4112 goto out;
4113 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4114 if (r)
4115 goto out;
4116 r = -EFAULT;
4117 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4118 goto out;
4119 r = 0;
4120 break;
4121 }
4122 case KVM_SET_PIT: {
4123 r = -EFAULT;
4124 if (copy_from_user(&u.ps, argp, sizeof u.ps))
4125 goto out;
4126 r = -ENXIO;
4127 if (!kvm->arch.vpit)
4128 goto out;
4129 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4130 break;
4131 }
4132 case KVM_GET_PIT2: {
4133 r = -ENXIO;
4134 if (!kvm->arch.vpit)
4135 goto out;
4136 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4137 if (r)
4138 goto out;
4139 r = -EFAULT;
4140 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4141 goto out;
4142 r = 0;
4143 break;
4144 }
4145 case KVM_SET_PIT2: {
4146 r = -EFAULT;
4147 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4148 goto out;
4149 r = -ENXIO;
4150 if (!kvm->arch.vpit)
4151 goto out;
4152 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4153 break;
4154 }
4155 case KVM_REINJECT_CONTROL: {
4156 struct kvm_reinject_control control;
4157 r = -EFAULT;
4158 if (copy_from_user(&control, argp, sizeof(control)))
4159 goto out;
4160 r = kvm_vm_ioctl_reinject(kvm, &control);
4161 break;
4162 }
4163 case KVM_SET_BOOT_CPU_ID:
4164 r = 0;
4165 mutex_lock(&kvm->lock);
4166 if (kvm->created_vcpus)
4167 r = -EBUSY;
4168 else
4169 kvm->arch.bsp_vcpu_id = arg;
4170 mutex_unlock(&kvm->lock);
4171 break;
4172 case KVM_XEN_HVM_CONFIG: {
4173 r = -EFAULT;
4174 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4175 sizeof(struct kvm_xen_hvm_config)))
4176 goto out;
4177 r = -EINVAL;
4178 if (kvm->arch.xen_hvm_config.flags)
4179 goto out;
4180 r = 0;
4181 break;
4182 }
4183 case KVM_SET_CLOCK: {
4184 struct kvm_clock_data user_ns;
4185 u64 now_ns;
4186
4187 r = -EFAULT;
4188 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4189 goto out;
4190
4191 r = -EINVAL;
4192 if (user_ns.flags)
4193 goto out;
4194
4195 r = 0;
4196 local_irq_disable();
4197 now_ns = __get_kvmclock_ns(kvm);
4198 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4199 local_irq_enable();
4200 kvm_gen_update_masterclock(kvm);
4201 break;
4202 }
4203 case KVM_GET_CLOCK: {
4204 struct kvm_clock_data user_ns;
4205 u64 now_ns;
4206
4207 local_irq_disable();
4208 now_ns = __get_kvmclock_ns(kvm);
4209 user_ns.clock = now_ns;
4210 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4211 local_irq_enable();
4212 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4213
4214 r = -EFAULT;
4215 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4216 goto out;
4217 r = 0;
4218 break;
4219 }
4220 case KVM_ENABLE_CAP: {
4221 struct kvm_enable_cap cap;
4222
4223 r = -EFAULT;
4224 if (copy_from_user(&cap, argp, sizeof(cap)))
4225 goto out;
4226 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4227 break;
4228 }
4229 default:
4230 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
4231 }
4232 out:
4233 return r;
4234 }
4235
4236 static void kvm_init_msr_list(void)
4237 {
4238 u32 dummy[2];
4239 unsigned i, j;
4240
4241 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4242 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4243 continue;
4244
4245 /*
4246 * Even MSRs that are valid in the host may not be exposed
4247 * to the guests in some cases.
4248 */
4249 switch (msrs_to_save[i]) {
4250 case MSR_IA32_BNDCFGS:
4251 if (!kvm_x86_ops->mpx_supported())
4252 continue;
4253 break;
4254 case MSR_TSC_AUX:
4255 if (!kvm_x86_ops->rdtscp_supported())
4256 continue;
4257 break;
4258 default:
4259 break;
4260 }
4261
4262 if (j < i)
4263 msrs_to_save[j] = msrs_to_save[i];
4264 j++;
4265 }
4266 num_msrs_to_save = j;
4267
4268 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4269 switch (emulated_msrs[i]) {
4270 case MSR_IA32_SMBASE:
4271 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4272 continue;
4273 break;
4274 default:
4275 break;
4276 }
4277
4278 if (j < i)
4279 emulated_msrs[j] = emulated_msrs[i];
4280 j++;
4281 }
4282 num_emulated_msrs = j;
4283 }
4284
4285 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4286 const void *v)
4287 {
4288 int handled = 0;
4289 int n;
4290
4291 do {
4292 n = min(len, 8);
4293 if (!(lapic_in_kernel(vcpu) &&
4294 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4295 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4296 break;
4297 handled += n;
4298 addr += n;
4299 len -= n;
4300 v += n;
4301 } while (len);
4302
4303 return handled;
4304 }
4305
4306 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4307 {
4308 int handled = 0;
4309 int n;
4310
4311 do {
4312 n = min(len, 8);
4313 if (!(lapic_in_kernel(vcpu) &&
4314 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4315 addr, n, v))
4316 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4317 break;
4318 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4319 handled += n;
4320 addr += n;
4321 len -= n;
4322 v += n;
4323 } while (len);
4324
4325 return handled;
4326 }
4327
4328 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4329 struct kvm_segment *var, int seg)
4330 {
4331 kvm_x86_ops->set_segment(vcpu, var, seg);
4332 }
4333
4334 void kvm_get_segment(struct kvm_vcpu *vcpu,
4335 struct kvm_segment *var, int seg)
4336 {
4337 kvm_x86_ops->get_segment(vcpu, var, seg);
4338 }
4339
4340 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4341 struct x86_exception *exception)
4342 {
4343 gpa_t t_gpa;
4344
4345 BUG_ON(!mmu_is_nested(vcpu));
4346
4347 /* NPT walks are always user-walks */
4348 access |= PFERR_USER_MASK;
4349 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4350
4351 return t_gpa;
4352 }
4353
4354 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4355 struct x86_exception *exception)
4356 {
4357 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4358 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4359 }
4360
4361 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4362 struct x86_exception *exception)
4363 {
4364 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4365 access |= PFERR_FETCH_MASK;
4366 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4367 }
4368
4369 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4370 struct x86_exception *exception)
4371 {
4372 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4373 access |= PFERR_WRITE_MASK;
4374 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4375 }
4376
4377 /* uses this to access any guest's mapped memory without checking CPL */
4378 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4379 struct x86_exception *exception)
4380 {
4381 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4382 }
4383
4384 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4385 struct kvm_vcpu *vcpu, u32 access,
4386 struct x86_exception *exception)
4387 {
4388 void *data = val;
4389 int r = X86EMUL_CONTINUE;
4390
4391 while (bytes) {
4392 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4393 exception);
4394 unsigned offset = addr & (PAGE_SIZE-1);
4395 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4396 int ret;
4397
4398 if (gpa == UNMAPPED_GVA)
4399 return X86EMUL_PROPAGATE_FAULT;
4400 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4401 offset, toread);
4402 if (ret < 0) {
4403 r = X86EMUL_IO_NEEDED;
4404 goto out;
4405 }
4406
4407 bytes -= toread;
4408 data += toread;
4409 addr += toread;
4410 }
4411 out:
4412 return r;
4413 }
4414
4415 /* used for instruction fetching */
4416 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4417 gva_t addr, void *val, unsigned int bytes,
4418 struct x86_exception *exception)
4419 {
4420 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4421 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4422 unsigned offset;
4423 int ret;
4424
4425 /* Inline kvm_read_guest_virt_helper for speed. */
4426 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4427 exception);
4428 if (unlikely(gpa == UNMAPPED_GVA))
4429 return X86EMUL_PROPAGATE_FAULT;
4430
4431 offset = addr & (PAGE_SIZE-1);
4432 if (WARN_ON(offset + bytes > PAGE_SIZE))
4433 bytes = (unsigned)PAGE_SIZE - offset;
4434 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4435 offset, bytes);
4436 if (unlikely(ret < 0))
4437 return X86EMUL_IO_NEEDED;
4438
4439 return X86EMUL_CONTINUE;
4440 }
4441
4442 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4443 gva_t addr, void *val, unsigned int bytes,
4444 struct x86_exception *exception)
4445 {
4446 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4447 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4448
4449 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4450 exception);
4451 }
4452 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4453
4454 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4455 gva_t addr, void *val, unsigned int bytes,
4456 struct x86_exception *exception)
4457 {
4458 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4459 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4460 }
4461
4462 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4463 unsigned long addr, void *val, unsigned int bytes)
4464 {
4465 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4466 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4467
4468 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4469 }
4470
4471 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4472 gva_t addr, void *val,
4473 unsigned int bytes,
4474 struct x86_exception *exception)
4475 {
4476 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4477 void *data = val;
4478 int r = X86EMUL_CONTINUE;
4479
4480 while (bytes) {
4481 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4482 PFERR_WRITE_MASK,
4483 exception);
4484 unsigned offset = addr & (PAGE_SIZE-1);
4485 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4486 int ret;
4487
4488 if (gpa == UNMAPPED_GVA)
4489 return X86EMUL_PROPAGATE_FAULT;
4490 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4491 if (ret < 0) {
4492 r = X86EMUL_IO_NEEDED;
4493 goto out;
4494 }
4495
4496 bytes -= towrite;
4497 data += towrite;
4498 addr += towrite;
4499 }
4500 out:
4501 return r;
4502 }
4503 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4504
4505 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4506 gpa_t gpa, bool write)
4507 {
4508 /* For APIC access vmexit */
4509 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4510 return 1;
4511
4512 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4513 trace_vcpu_match_mmio(gva, gpa, write, true);
4514 return 1;
4515 }
4516
4517 return 0;
4518 }
4519
4520 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4521 gpa_t *gpa, struct x86_exception *exception,
4522 bool write)
4523 {
4524 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4525 | (write ? PFERR_WRITE_MASK : 0);
4526
4527 /*
4528 * currently PKRU is only applied to ept enabled guest so
4529 * there is no pkey in EPT page table for L1 guest or EPT
4530 * shadow page table for L2 guest.
4531 */
4532 if (vcpu_match_mmio_gva(vcpu, gva)
4533 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4534 vcpu->arch.access, 0, access)) {
4535 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4536 (gva & (PAGE_SIZE - 1));
4537 trace_vcpu_match_mmio(gva, *gpa, write, false);
4538 return 1;
4539 }
4540
4541 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4542
4543 if (*gpa == UNMAPPED_GVA)
4544 return -1;
4545
4546 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
4547 }
4548
4549 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4550 const void *val, int bytes)
4551 {
4552 int ret;
4553
4554 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4555 if (ret < 0)
4556 return 0;
4557 kvm_page_track_write(vcpu, gpa, val, bytes);
4558 return 1;
4559 }
4560
4561 struct read_write_emulator_ops {
4562 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4563 int bytes);
4564 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4565 void *val, int bytes);
4566 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4567 int bytes, void *val);
4568 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4569 void *val, int bytes);
4570 bool write;
4571 };
4572
4573 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4574 {
4575 if (vcpu->mmio_read_completed) {
4576 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4577 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4578 vcpu->mmio_read_completed = 0;
4579 return 1;
4580 }
4581
4582 return 0;
4583 }
4584
4585 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4586 void *val, int bytes)
4587 {
4588 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4589 }
4590
4591 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4592 void *val, int bytes)
4593 {
4594 return emulator_write_phys(vcpu, gpa, val, bytes);
4595 }
4596
4597 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4598 {
4599 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4600 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4601 }
4602
4603 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4604 void *val, int bytes)
4605 {
4606 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4607 return X86EMUL_IO_NEEDED;
4608 }
4609
4610 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4611 void *val, int bytes)
4612 {
4613 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4614
4615 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4616 return X86EMUL_CONTINUE;
4617 }
4618
4619 static const struct read_write_emulator_ops read_emultor = {
4620 .read_write_prepare = read_prepare,
4621 .read_write_emulate = read_emulate,
4622 .read_write_mmio = vcpu_mmio_read,
4623 .read_write_exit_mmio = read_exit_mmio,
4624 };
4625
4626 static const struct read_write_emulator_ops write_emultor = {
4627 .read_write_emulate = write_emulate,
4628 .read_write_mmio = write_mmio,
4629 .read_write_exit_mmio = write_exit_mmio,
4630 .write = true,
4631 };
4632
4633 static int emulator_read_write_onepage(unsigned long addr, void *val,
4634 unsigned int bytes,
4635 struct x86_exception *exception,
4636 struct kvm_vcpu *vcpu,
4637 const struct read_write_emulator_ops *ops)
4638 {
4639 gpa_t gpa;
4640 int handled, ret;
4641 bool write = ops->write;
4642 struct kvm_mmio_fragment *frag;
4643 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4644
4645 /*
4646 * If the exit was due to a NPF we may already have a GPA.
4647 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4648 * Note, this cannot be used on string operations since string
4649 * operation using rep will only have the initial GPA from the NPF
4650 * occurred.
4651 */
4652 if (vcpu->arch.gpa_available &&
4653 emulator_can_use_gpa(ctxt) &&
4654 vcpu_is_mmio_gpa(vcpu, addr, exception->address, write) &&
4655 (addr & ~PAGE_MASK) == (exception->address & ~PAGE_MASK)) {
4656 gpa = exception->address;
4657 goto mmio;
4658 }
4659
4660 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4661
4662 if (ret < 0)
4663 return X86EMUL_PROPAGATE_FAULT;
4664
4665 /* For APIC access vmexit */
4666 if (ret)
4667 goto mmio;
4668
4669 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4670 return X86EMUL_CONTINUE;
4671
4672 mmio:
4673 /*
4674 * Is this MMIO handled locally?
4675 */
4676 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4677 if (handled == bytes)
4678 return X86EMUL_CONTINUE;
4679
4680 gpa += handled;
4681 bytes -= handled;
4682 val += handled;
4683
4684 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4685 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4686 frag->gpa = gpa;
4687 frag->data = val;
4688 frag->len = bytes;
4689 return X86EMUL_CONTINUE;
4690 }
4691
4692 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4693 unsigned long addr,
4694 void *val, unsigned int bytes,
4695 struct x86_exception *exception,
4696 const struct read_write_emulator_ops *ops)
4697 {
4698 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4699 gpa_t gpa;
4700 int rc;
4701
4702 if (ops->read_write_prepare &&
4703 ops->read_write_prepare(vcpu, val, bytes))
4704 return X86EMUL_CONTINUE;
4705
4706 vcpu->mmio_nr_fragments = 0;
4707
4708 /* Crossing a page boundary? */
4709 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4710 int now;
4711
4712 now = -addr & ~PAGE_MASK;
4713 rc = emulator_read_write_onepage(addr, val, now, exception,
4714 vcpu, ops);
4715
4716 if (rc != X86EMUL_CONTINUE)
4717 return rc;
4718 addr += now;
4719 if (ctxt->mode != X86EMUL_MODE_PROT64)
4720 addr = (u32)addr;
4721 val += now;
4722 bytes -= now;
4723 }
4724
4725 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4726 vcpu, ops);
4727 if (rc != X86EMUL_CONTINUE)
4728 return rc;
4729
4730 if (!vcpu->mmio_nr_fragments)
4731 return rc;
4732
4733 gpa = vcpu->mmio_fragments[0].gpa;
4734
4735 vcpu->mmio_needed = 1;
4736 vcpu->mmio_cur_fragment = 0;
4737
4738 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4739 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4740 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4741 vcpu->run->mmio.phys_addr = gpa;
4742
4743 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4744 }
4745
4746 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4747 unsigned long addr,
4748 void *val,
4749 unsigned int bytes,
4750 struct x86_exception *exception)
4751 {
4752 return emulator_read_write(ctxt, addr, val, bytes,
4753 exception, &read_emultor);
4754 }
4755
4756 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4757 unsigned long addr,
4758 const void *val,
4759 unsigned int bytes,
4760 struct x86_exception *exception)
4761 {
4762 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4763 exception, &write_emultor);
4764 }
4765
4766 #define CMPXCHG_TYPE(t, ptr, old, new) \
4767 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4768
4769 #ifdef CONFIG_X86_64
4770 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4771 #else
4772 # define CMPXCHG64(ptr, old, new) \
4773 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4774 #endif
4775
4776 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4777 unsigned long addr,
4778 const void *old,
4779 const void *new,
4780 unsigned int bytes,
4781 struct x86_exception *exception)
4782 {
4783 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4784 gpa_t gpa;
4785 struct page *page;
4786 char *kaddr;
4787 bool exchanged;
4788
4789 /* guests cmpxchg8b have to be emulated atomically */
4790 if (bytes > 8 || (bytes & (bytes - 1)))
4791 goto emul_write;
4792
4793 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4794
4795 if (gpa == UNMAPPED_GVA ||
4796 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4797 goto emul_write;
4798
4799 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4800 goto emul_write;
4801
4802 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4803 if (is_error_page(page))
4804 goto emul_write;
4805
4806 kaddr = kmap_atomic(page);
4807 kaddr += offset_in_page(gpa);
4808 switch (bytes) {
4809 case 1:
4810 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4811 break;
4812 case 2:
4813 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4814 break;
4815 case 4:
4816 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4817 break;
4818 case 8:
4819 exchanged = CMPXCHG64(kaddr, old, new);
4820 break;
4821 default:
4822 BUG();
4823 }
4824 kunmap_atomic(kaddr);
4825 kvm_release_page_dirty(page);
4826
4827 if (!exchanged)
4828 return X86EMUL_CMPXCHG_FAILED;
4829
4830 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4831 kvm_page_track_write(vcpu, gpa, new, bytes);
4832
4833 return X86EMUL_CONTINUE;
4834
4835 emul_write:
4836 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4837
4838 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4839 }
4840
4841 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4842 {
4843 /* TODO: String I/O for in kernel device */
4844 int r;
4845
4846 if (vcpu->arch.pio.in)
4847 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4848 vcpu->arch.pio.size, pd);
4849 else
4850 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4851 vcpu->arch.pio.port, vcpu->arch.pio.size,
4852 pd);
4853 return r;
4854 }
4855
4856 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4857 unsigned short port, void *val,
4858 unsigned int count, bool in)
4859 {
4860 vcpu->arch.pio.port = port;
4861 vcpu->arch.pio.in = in;
4862 vcpu->arch.pio.count = count;
4863 vcpu->arch.pio.size = size;
4864
4865 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4866 vcpu->arch.pio.count = 0;
4867 return 1;
4868 }
4869
4870 vcpu->run->exit_reason = KVM_EXIT_IO;
4871 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4872 vcpu->run->io.size = size;
4873 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4874 vcpu->run->io.count = count;
4875 vcpu->run->io.port = port;
4876
4877 return 0;
4878 }
4879
4880 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4881 int size, unsigned short port, void *val,
4882 unsigned int count)
4883 {
4884 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4885 int ret;
4886
4887 if (vcpu->arch.pio.count)
4888 goto data_avail;
4889
4890 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4891 if (ret) {
4892 data_avail:
4893 memcpy(val, vcpu->arch.pio_data, size * count);
4894 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4895 vcpu->arch.pio.count = 0;
4896 return 1;
4897 }
4898
4899 return 0;
4900 }
4901
4902 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4903 int size, unsigned short port,
4904 const void *val, unsigned int count)
4905 {
4906 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4907
4908 memcpy(vcpu->arch.pio_data, val, size * count);
4909 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4910 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4911 }
4912
4913 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4914 {
4915 return kvm_x86_ops->get_segment_base(vcpu, seg);
4916 }
4917
4918 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4919 {
4920 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4921 }
4922
4923 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4924 {
4925 if (!need_emulate_wbinvd(vcpu))
4926 return X86EMUL_CONTINUE;
4927
4928 if (kvm_x86_ops->has_wbinvd_exit()) {
4929 int cpu = get_cpu();
4930
4931 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4932 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4933 wbinvd_ipi, NULL, 1);
4934 put_cpu();
4935 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4936 } else
4937 wbinvd();
4938 return X86EMUL_CONTINUE;
4939 }
4940
4941 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4942 {
4943 kvm_emulate_wbinvd_noskip(vcpu);
4944 return kvm_skip_emulated_instruction(vcpu);
4945 }
4946 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4947
4948
4949
4950 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4951 {
4952 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4953 }
4954
4955 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4956 unsigned long *dest)
4957 {
4958 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4959 }
4960
4961 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4962 unsigned long value)
4963 {
4964
4965 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4966 }
4967
4968 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4969 {
4970 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4971 }
4972
4973 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4974 {
4975 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4976 unsigned long value;
4977
4978 switch (cr) {
4979 case 0:
4980 value = kvm_read_cr0(vcpu);
4981 break;
4982 case 2:
4983 value = vcpu->arch.cr2;
4984 break;
4985 case 3:
4986 value = kvm_read_cr3(vcpu);
4987 break;
4988 case 4:
4989 value = kvm_read_cr4(vcpu);
4990 break;
4991 case 8:
4992 value = kvm_get_cr8(vcpu);
4993 break;
4994 default:
4995 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4996 return 0;
4997 }
4998
4999 return value;
5000 }
5001
5002 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5003 {
5004 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5005 int res = 0;
5006
5007 switch (cr) {
5008 case 0:
5009 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5010 break;
5011 case 2:
5012 vcpu->arch.cr2 = val;
5013 break;
5014 case 3:
5015 res = kvm_set_cr3(vcpu, val);
5016 break;
5017 case 4:
5018 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5019 break;
5020 case 8:
5021 res = kvm_set_cr8(vcpu, val);
5022 break;
5023 default:
5024 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5025 res = -1;
5026 }
5027
5028 return res;
5029 }
5030
5031 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5032 {
5033 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5034 }
5035
5036 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5037 {
5038 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5039 }
5040
5041 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5042 {
5043 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5044 }
5045
5046 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5047 {
5048 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5049 }
5050
5051 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5052 {
5053 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5054 }
5055
5056 static unsigned long emulator_get_cached_segment_base(
5057 struct x86_emulate_ctxt *ctxt, int seg)
5058 {
5059 return get_segment_base(emul_to_vcpu(ctxt), seg);
5060 }
5061
5062 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5063 struct desc_struct *desc, u32 *base3,
5064 int seg)
5065 {
5066 struct kvm_segment var;
5067
5068 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5069 *selector = var.selector;
5070
5071 if (var.unusable) {
5072 memset(desc, 0, sizeof(*desc));
5073 return false;
5074 }
5075
5076 if (var.g)
5077 var.limit >>= 12;
5078 set_desc_limit(desc, var.limit);
5079 set_desc_base(desc, (unsigned long)var.base);
5080 #ifdef CONFIG_X86_64
5081 if (base3)
5082 *base3 = var.base >> 32;
5083 #endif
5084 desc->type = var.type;
5085 desc->s = var.s;
5086 desc->dpl = var.dpl;
5087 desc->p = var.present;
5088 desc->avl = var.avl;
5089 desc->l = var.l;
5090 desc->d = var.db;
5091 desc->g = var.g;
5092
5093 return true;
5094 }
5095
5096 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5097 struct desc_struct *desc, u32 base3,
5098 int seg)
5099 {
5100 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5101 struct kvm_segment var;
5102
5103 var.selector = selector;
5104 var.base = get_desc_base(desc);
5105 #ifdef CONFIG_X86_64
5106 var.base |= ((u64)base3) << 32;
5107 #endif
5108 var.limit = get_desc_limit(desc);
5109 if (desc->g)
5110 var.limit = (var.limit << 12) | 0xfff;
5111 var.type = desc->type;
5112 var.dpl = desc->dpl;
5113 var.db = desc->d;
5114 var.s = desc->s;
5115 var.l = desc->l;
5116 var.g = desc->g;
5117 var.avl = desc->avl;
5118 var.present = desc->p;
5119 var.unusable = !var.present;
5120 var.padding = 0;
5121
5122 kvm_set_segment(vcpu, &var, seg);
5123 return;
5124 }
5125
5126 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5127 u32 msr_index, u64 *pdata)
5128 {
5129 struct msr_data msr;
5130 int r;
5131
5132 msr.index = msr_index;
5133 msr.host_initiated = false;
5134 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5135 if (r)
5136 return r;
5137
5138 *pdata = msr.data;
5139 return 0;
5140 }
5141
5142 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5143 u32 msr_index, u64 data)
5144 {
5145 struct msr_data msr;
5146
5147 msr.data = data;
5148 msr.index = msr_index;
5149 msr.host_initiated = false;
5150 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5151 }
5152
5153 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5154 {
5155 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5156
5157 return vcpu->arch.smbase;
5158 }
5159
5160 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5161 {
5162 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5163
5164 vcpu->arch.smbase = smbase;
5165 }
5166
5167 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5168 u32 pmc)
5169 {
5170 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5171 }
5172
5173 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5174 u32 pmc, u64 *pdata)
5175 {
5176 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5177 }
5178
5179 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5180 {
5181 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5182 }
5183
5184 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5185 {
5186 preempt_disable();
5187 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5188 }
5189
5190 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5191 {
5192 preempt_enable();
5193 }
5194
5195 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5196 struct x86_instruction_info *info,
5197 enum x86_intercept_stage stage)
5198 {
5199 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5200 }
5201
5202 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5203 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5204 {
5205 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
5206 }
5207
5208 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5209 {
5210 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5211 }
5212
5213 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5214 {
5215 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5216 }
5217
5218 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5219 {
5220 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5221 }
5222
5223 static const struct x86_emulate_ops emulate_ops = {
5224 .read_gpr = emulator_read_gpr,
5225 .write_gpr = emulator_write_gpr,
5226 .read_std = kvm_read_guest_virt_system,
5227 .write_std = kvm_write_guest_virt_system,
5228 .read_phys = kvm_read_guest_phys_system,
5229 .fetch = kvm_fetch_guest_virt,
5230 .read_emulated = emulator_read_emulated,
5231 .write_emulated = emulator_write_emulated,
5232 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5233 .invlpg = emulator_invlpg,
5234 .pio_in_emulated = emulator_pio_in_emulated,
5235 .pio_out_emulated = emulator_pio_out_emulated,
5236 .get_segment = emulator_get_segment,
5237 .set_segment = emulator_set_segment,
5238 .get_cached_segment_base = emulator_get_cached_segment_base,
5239 .get_gdt = emulator_get_gdt,
5240 .get_idt = emulator_get_idt,
5241 .set_gdt = emulator_set_gdt,
5242 .set_idt = emulator_set_idt,
5243 .get_cr = emulator_get_cr,
5244 .set_cr = emulator_set_cr,
5245 .cpl = emulator_get_cpl,
5246 .get_dr = emulator_get_dr,
5247 .set_dr = emulator_set_dr,
5248 .get_smbase = emulator_get_smbase,
5249 .set_smbase = emulator_set_smbase,
5250 .set_msr = emulator_set_msr,
5251 .get_msr = emulator_get_msr,
5252 .check_pmc = emulator_check_pmc,
5253 .read_pmc = emulator_read_pmc,
5254 .halt = emulator_halt,
5255 .wbinvd = emulator_wbinvd,
5256 .fix_hypercall = emulator_fix_hypercall,
5257 .get_fpu = emulator_get_fpu,
5258 .put_fpu = emulator_put_fpu,
5259 .intercept = emulator_intercept,
5260 .get_cpuid = emulator_get_cpuid,
5261 .set_nmi_mask = emulator_set_nmi_mask,
5262 };
5263
5264 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5265 {
5266 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5267 /*
5268 * an sti; sti; sequence only disable interrupts for the first
5269 * instruction. So, if the last instruction, be it emulated or
5270 * not, left the system with the INT_STI flag enabled, it
5271 * means that the last instruction is an sti. We should not
5272 * leave the flag on in this case. The same goes for mov ss
5273 */
5274 if (int_shadow & mask)
5275 mask = 0;
5276 if (unlikely(int_shadow || mask)) {
5277 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5278 if (!mask)
5279 kvm_make_request(KVM_REQ_EVENT, vcpu);
5280 }
5281 }
5282
5283 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5284 {
5285 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5286 if (ctxt->exception.vector == PF_VECTOR)
5287 return kvm_propagate_fault(vcpu, &ctxt->exception);
5288
5289 if (ctxt->exception.error_code_valid)
5290 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5291 ctxt->exception.error_code);
5292 else
5293 kvm_queue_exception(vcpu, ctxt->exception.vector);
5294 return false;
5295 }
5296
5297 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5298 {
5299 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5300 int cs_db, cs_l;
5301
5302 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5303
5304 ctxt->eflags = kvm_get_rflags(vcpu);
5305 ctxt->eip = kvm_rip_read(vcpu);
5306 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5307 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5308 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5309 cs_db ? X86EMUL_MODE_PROT32 :
5310 X86EMUL_MODE_PROT16;
5311 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5312 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5313 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5314 ctxt->emul_flags = vcpu->arch.hflags;
5315
5316 init_decode_cache(ctxt);
5317 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5318 }
5319
5320 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5321 {
5322 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5323 int ret;
5324
5325 init_emulate_ctxt(vcpu);
5326
5327 ctxt->op_bytes = 2;
5328 ctxt->ad_bytes = 2;
5329 ctxt->_eip = ctxt->eip + inc_eip;
5330 ret = emulate_int_real(ctxt, irq);
5331
5332 if (ret != X86EMUL_CONTINUE)
5333 return EMULATE_FAIL;
5334
5335 ctxt->eip = ctxt->_eip;
5336 kvm_rip_write(vcpu, ctxt->eip);
5337 kvm_set_rflags(vcpu, ctxt->eflags);
5338
5339 if (irq == NMI_VECTOR)
5340 vcpu->arch.nmi_pending = 0;
5341 else
5342 vcpu->arch.interrupt.pending = false;
5343
5344 return EMULATE_DONE;
5345 }
5346 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5347
5348 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5349 {
5350 int r = EMULATE_DONE;
5351
5352 ++vcpu->stat.insn_emulation_fail;
5353 trace_kvm_emulate_insn_failed(vcpu);
5354 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5355 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5356 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5357 vcpu->run->internal.ndata = 0;
5358 r = EMULATE_FAIL;
5359 }
5360 kvm_queue_exception(vcpu, UD_VECTOR);
5361
5362 return r;
5363 }
5364
5365 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5366 bool write_fault_to_shadow_pgtable,
5367 int emulation_type)
5368 {
5369 gpa_t gpa = cr2;
5370 kvm_pfn_t pfn;
5371
5372 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5373 return false;
5374
5375 if (!vcpu->arch.mmu.direct_map) {
5376 /*
5377 * Write permission should be allowed since only
5378 * write access need to be emulated.
5379 */
5380 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5381
5382 /*
5383 * If the mapping is invalid in guest, let cpu retry
5384 * it to generate fault.
5385 */
5386 if (gpa == UNMAPPED_GVA)
5387 return true;
5388 }
5389
5390 /*
5391 * Do not retry the unhandleable instruction if it faults on the
5392 * readonly host memory, otherwise it will goto a infinite loop:
5393 * retry instruction -> write #PF -> emulation fail -> retry
5394 * instruction -> ...
5395 */
5396 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5397
5398 /*
5399 * If the instruction failed on the error pfn, it can not be fixed,
5400 * report the error to userspace.
5401 */
5402 if (is_error_noslot_pfn(pfn))
5403 return false;
5404
5405 kvm_release_pfn_clean(pfn);
5406
5407 /* The instructions are well-emulated on direct mmu. */
5408 if (vcpu->arch.mmu.direct_map) {
5409 unsigned int indirect_shadow_pages;
5410
5411 spin_lock(&vcpu->kvm->mmu_lock);
5412 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5413 spin_unlock(&vcpu->kvm->mmu_lock);
5414
5415 if (indirect_shadow_pages)
5416 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5417
5418 return true;
5419 }
5420
5421 /*
5422 * if emulation was due to access to shadowed page table
5423 * and it failed try to unshadow page and re-enter the
5424 * guest to let CPU execute the instruction.
5425 */
5426 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5427
5428 /*
5429 * If the access faults on its page table, it can not
5430 * be fixed by unprotecting shadow page and it should
5431 * be reported to userspace.
5432 */
5433 return !write_fault_to_shadow_pgtable;
5434 }
5435
5436 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5437 unsigned long cr2, int emulation_type)
5438 {
5439 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5440 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5441
5442 last_retry_eip = vcpu->arch.last_retry_eip;
5443 last_retry_addr = vcpu->arch.last_retry_addr;
5444
5445 /*
5446 * If the emulation is caused by #PF and it is non-page_table
5447 * writing instruction, it means the VM-EXIT is caused by shadow
5448 * page protected, we can zap the shadow page and retry this
5449 * instruction directly.
5450 *
5451 * Note: if the guest uses a non-page-table modifying instruction
5452 * on the PDE that points to the instruction, then we will unmap
5453 * the instruction and go to an infinite loop. So, we cache the
5454 * last retried eip and the last fault address, if we meet the eip
5455 * and the address again, we can break out of the potential infinite
5456 * loop.
5457 */
5458 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5459
5460 if (!(emulation_type & EMULTYPE_RETRY))
5461 return false;
5462
5463 if (x86_page_table_writing_insn(ctxt))
5464 return false;
5465
5466 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5467 return false;
5468
5469 vcpu->arch.last_retry_eip = ctxt->eip;
5470 vcpu->arch.last_retry_addr = cr2;
5471
5472 if (!vcpu->arch.mmu.direct_map)
5473 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5474
5475 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5476
5477 return true;
5478 }
5479
5480 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5481 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5482
5483 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5484 {
5485 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5486 /* This is a good place to trace that we are exiting SMM. */
5487 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5488
5489 /* Process a latched INIT or SMI, if any. */
5490 kvm_make_request(KVM_REQ_EVENT, vcpu);
5491 }
5492
5493 kvm_mmu_reset_context(vcpu);
5494 }
5495
5496 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5497 {
5498 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5499
5500 vcpu->arch.hflags = emul_flags;
5501
5502 if (changed & HF_SMM_MASK)
5503 kvm_smm_changed(vcpu);
5504 }
5505
5506 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5507 unsigned long *db)
5508 {
5509 u32 dr6 = 0;
5510 int i;
5511 u32 enable, rwlen;
5512
5513 enable = dr7;
5514 rwlen = dr7 >> 16;
5515 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5516 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5517 dr6 |= (1 << i);
5518 return dr6;
5519 }
5520
5521 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5522 {
5523 struct kvm_run *kvm_run = vcpu->run;
5524
5525 /*
5526 * rflags is the old, "raw" value of the flags. The new value has
5527 * not been saved yet.
5528 *
5529 * This is correct even for TF set by the guest, because "the
5530 * processor will not generate this exception after the instruction
5531 * that sets the TF flag".
5532 */
5533 if (unlikely(rflags & X86_EFLAGS_TF)) {
5534 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5535 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5536 DR6_RTM;
5537 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5538 kvm_run->debug.arch.exception = DB_VECTOR;
5539 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5540 *r = EMULATE_USER_EXIT;
5541 } else {
5542 /*
5543 * "Certain debug exceptions may clear bit 0-3. The
5544 * remaining contents of the DR6 register are never
5545 * cleared by the processor".
5546 */
5547 vcpu->arch.dr6 &= ~15;
5548 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5549 kvm_queue_exception(vcpu, DB_VECTOR);
5550 }
5551 }
5552 }
5553
5554 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5555 {
5556 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5557 int r = EMULATE_DONE;
5558
5559 kvm_x86_ops->skip_emulated_instruction(vcpu);
5560 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5561 return r == EMULATE_DONE;
5562 }
5563 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5564
5565 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5566 {
5567 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5568 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5569 struct kvm_run *kvm_run = vcpu->run;
5570 unsigned long eip = kvm_get_linear_rip(vcpu);
5571 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5572 vcpu->arch.guest_debug_dr7,
5573 vcpu->arch.eff_db);
5574
5575 if (dr6 != 0) {
5576 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5577 kvm_run->debug.arch.pc = eip;
5578 kvm_run->debug.arch.exception = DB_VECTOR;
5579 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5580 *r = EMULATE_USER_EXIT;
5581 return true;
5582 }
5583 }
5584
5585 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5586 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5587 unsigned long eip = kvm_get_linear_rip(vcpu);
5588 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5589 vcpu->arch.dr7,
5590 vcpu->arch.db);
5591
5592 if (dr6 != 0) {
5593 vcpu->arch.dr6 &= ~15;
5594 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5595 kvm_queue_exception(vcpu, DB_VECTOR);
5596 *r = EMULATE_DONE;
5597 return true;
5598 }
5599 }
5600
5601 return false;
5602 }
5603
5604 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5605 unsigned long cr2,
5606 int emulation_type,
5607 void *insn,
5608 int insn_len)
5609 {
5610 int r;
5611 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5612 bool writeback = true;
5613 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5614
5615 /*
5616 * Clear write_fault_to_shadow_pgtable here to ensure it is
5617 * never reused.
5618 */
5619 vcpu->arch.write_fault_to_shadow_pgtable = false;
5620 kvm_clear_exception_queue(vcpu);
5621
5622 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5623 init_emulate_ctxt(vcpu);
5624
5625 /*
5626 * We will reenter on the same instruction since
5627 * we do not set complete_userspace_io. This does not
5628 * handle watchpoints yet, those would be handled in
5629 * the emulate_ops.
5630 */
5631 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5632 return r;
5633
5634 ctxt->interruptibility = 0;
5635 ctxt->have_exception = false;
5636 ctxt->exception.vector = -1;
5637 ctxt->perm_ok = false;
5638
5639 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5640
5641 r = x86_decode_insn(ctxt, insn, insn_len);
5642
5643 trace_kvm_emulate_insn_start(vcpu);
5644 ++vcpu->stat.insn_emulation;
5645 if (r != EMULATION_OK) {
5646 if (emulation_type & EMULTYPE_TRAP_UD)
5647 return EMULATE_FAIL;
5648 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5649 emulation_type))
5650 return EMULATE_DONE;
5651 if (emulation_type & EMULTYPE_SKIP)
5652 return EMULATE_FAIL;
5653 return handle_emulation_failure(vcpu);
5654 }
5655 }
5656
5657 if (emulation_type & EMULTYPE_SKIP) {
5658 kvm_rip_write(vcpu, ctxt->_eip);
5659 if (ctxt->eflags & X86_EFLAGS_RF)
5660 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5661 return EMULATE_DONE;
5662 }
5663
5664 if (retry_instruction(ctxt, cr2, emulation_type))
5665 return EMULATE_DONE;
5666
5667 /* this is needed for vmware backdoor interface to work since it
5668 changes registers values during IO operation */
5669 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5670 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5671 emulator_invalidate_register_cache(ctxt);
5672 }
5673
5674 restart:
5675 /* Save the faulting GPA (cr2) in the address field */
5676 ctxt->exception.address = cr2;
5677
5678 r = x86_emulate_insn(ctxt);
5679
5680 if (r == EMULATION_INTERCEPTED)
5681 return EMULATE_DONE;
5682
5683 if (r == EMULATION_FAILED) {
5684 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5685 emulation_type))
5686 return EMULATE_DONE;
5687
5688 return handle_emulation_failure(vcpu);
5689 }
5690
5691 if (ctxt->have_exception) {
5692 r = EMULATE_DONE;
5693 if (inject_emulated_exception(vcpu))
5694 return r;
5695 } else if (vcpu->arch.pio.count) {
5696 if (!vcpu->arch.pio.in) {
5697 /* FIXME: return into emulator if single-stepping. */
5698 vcpu->arch.pio.count = 0;
5699 } else {
5700 writeback = false;
5701 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5702 }
5703 r = EMULATE_USER_EXIT;
5704 } else if (vcpu->mmio_needed) {
5705 if (!vcpu->mmio_is_write)
5706 writeback = false;
5707 r = EMULATE_USER_EXIT;
5708 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5709 } else if (r == EMULATION_RESTART)
5710 goto restart;
5711 else
5712 r = EMULATE_DONE;
5713
5714 if (writeback) {
5715 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5716 toggle_interruptibility(vcpu, ctxt->interruptibility);
5717 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5718 if (vcpu->arch.hflags != ctxt->emul_flags)
5719 kvm_set_hflags(vcpu, ctxt->emul_flags);
5720 kvm_rip_write(vcpu, ctxt->eip);
5721 if (r == EMULATE_DONE)
5722 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5723 if (!ctxt->have_exception ||
5724 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5725 __kvm_set_rflags(vcpu, ctxt->eflags);
5726
5727 /*
5728 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5729 * do nothing, and it will be requested again as soon as
5730 * the shadow expires. But we still need to check here,
5731 * because POPF has no interrupt shadow.
5732 */
5733 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5734 kvm_make_request(KVM_REQ_EVENT, vcpu);
5735 } else
5736 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5737
5738 return r;
5739 }
5740 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5741
5742 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5743 {
5744 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5745 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5746 size, port, &val, 1);
5747 /* do not return to emulator after return from userspace */
5748 vcpu->arch.pio.count = 0;
5749 return ret;
5750 }
5751 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5752
5753 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5754 {
5755 unsigned long val;
5756
5757 /* We should only ever be called with arch.pio.count equal to 1 */
5758 BUG_ON(vcpu->arch.pio.count != 1);
5759
5760 /* For size less than 4 we merge, else we zero extend */
5761 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5762 : 0;
5763
5764 /*
5765 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5766 * the copy and tracing
5767 */
5768 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5769 vcpu->arch.pio.port, &val, 1);
5770 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5771
5772 return 1;
5773 }
5774
5775 int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5776 {
5777 unsigned long val;
5778 int ret;
5779
5780 /* For size less than 4 we merge, else we zero extend */
5781 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5782
5783 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5784 &val, 1);
5785 if (ret) {
5786 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5787 return ret;
5788 }
5789
5790 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5791
5792 return 0;
5793 }
5794 EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5795
5796 static int kvmclock_cpu_down_prep(unsigned int cpu)
5797 {
5798 __this_cpu_write(cpu_tsc_khz, 0);
5799 return 0;
5800 }
5801
5802 static void tsc_khz_changed(void *data)
5803 {
5804 struct cpufreq_freqs *freq = data;
5805 unsigned long khz = 0;
5806
5807 if (data)
5808 khz = freq->new;
5809 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5810 khz = cpufreq_quick_get(raw_smp_processor_id());
5811 if (!khz)
5812 khz = tsc_khz;
5813 __this_cpu_write(cpu_tsc_khz, khz);
5814 }
5815
5816 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5817 void *data)
5818 {
5819 struct cpufreq_freqs *freq = data;
5820 struct kvm *kvm;
5821 struct kvm_vcpu *vcpu;
5822 int i, send_ipi = 0;
5823
5824 /*
5825 * We allow guests to temporarily run on slowing clocks,
5826 * provided we notify them after, or to run on accelerating
5827 * clocks, provided we notify them before. Thus time never
5828 * goes backwards.
5829 *
5830 * However, we have a problem. We can't atomically update
5831 * the frequency of a given CPU from this function; it is
5832 * merely a notifier, which can be called from any CPU.
5833 * Changing the TSC frequency at arbitrary points in time
5834 * requires a recomputation of local variables related to
5835 * the TSC for each VCPU. We must flag these local variables
5836 * to be updated and be sure the update takes place with the
5837 * new frequency before any guests proceed.
5838 *
5839 * Unfortunately, the combination of hotplug CPU and frequency
5840 * change creates an intractable locking scenario; the order
5841 * of when these callouts happen is undefined with respect to
5842 * CPU hotplug, and they can race with each other. As such,
5843 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5844 * undefined; you can actually have a CPU frequency change take
5845 * place in between the computation of X and the setting of the
5846 * variable. To protect against this problem, all updates of
5847 * the per_cpu tsc_khz variable are done in an interrupt
5848 * protected IPI, and all callers wishing to update the value
5849 * must wait for a synchronous IPI to complete (which is trivial
5850 * if the caller is on the CPU already). This establishes the
5851 * necessary total order on variable updates.
5852 *
5853 * Note that because a guest time update may take place
5854 * anytime after the setting of the VCPU's request bit, the
5855 * correct TSC value must be set before the request. However,
5856 * to ensure the update actually makes it to any guest which
5857 * starts running in hardware virtualization between the set
5858 * and the acquisition of the spinlock, we must also ping the
5859 * CPU after setting the request bit.
5860 *
5861 */
5862
5863 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5864 return 0;
5865 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5866 return 0;
5867
5868 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5869
5870 spin_lock(&kvm_lock);
5871 list_for_each_entry(kvm, &vm_list, vm_list) {
5872 kvm_for_each_vcpu(i, vcpu, kvm) {
5873 if (vcpu->cpu != freq->cpu)
5874 continue;
5875 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5876 if (vcpu->cpu != smp_processor_id())
5877 send_ipi = 1;
5878 }
5879 }
5880 spin_unlock(&kvm_lock);
5881
5882 if (freq->old < freq->new && send_ipi) {
5883 /*
5884 * We upscale the frequency. Must make the guest
5885 * doesn't see old kvmclock values while running with
5886 * the new frequency, otherwise we risk the guest sees
5887 * time go backwards.
5888 *
5889 * In case we update the frequency for another cpu
5890 * (which might be in guest context) send an interrupt
5891 * to kick the cpu out of guest context. Next time
5892 * guest context is entered kvmclock will be updated,
5893 * so the guest will not see stale values.
5894 */
5895 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5896 }
5897 return 0;
5898 }
5899
5900 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5901 .notifier_call = kvmclock_cpufreq_notifier
5902 };
5903
5904 static int kvmclock_cpu_online(unsigned int cpu)
5905 {
5906 tsc_khz_changed(NULL);
5907 return 0;
5908 }
5909
5910 static void kvm_timer_init(void)
5911 {
5912 max_tsc_khz = tsc_khz;
5913
5914 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5915 #ifdef CONFIG_CPU_FREQ
5916 struct cpufreq_policy policy;
5917 int cpu;
5918
5919 memset(&policy, 0, sizeof(policy));
5920 cpu = get_cpu();
5921 cpufreq_get_policy(&policy, cpu);
5922 if (policy.cpuinfo.max_freq)
5923 max_tsc_khz = policy.cpuinfo.max_freq;
5924 put_cpu();
5925 #endif
5926 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5927 CPUFREQ_TRANSITION_NOTIFIER);
5928 }
5929 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5930
5931 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
5932 kvmclock_cpu_online, kvmclock_cpu_down_prep);
5933 }
5934
5935 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5936
5937 int kvm_is_in_guest(void)
5938 {
5939 return __this_cpu_read(current_vcpu) != NULL;
5940 }
5941
5942 static int kvm_is_user_mode(void)
5943 {
5944 int user_mode = 3;
5945
5946 if (__this_cpu_read(current_vcpu))
5947 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5948
5949 return user_mode != 0;
5950 }
5951
5952 static unsigned long kvm_get_guest_ip(void)
5953 {
5954 unsigned long ip = 0;
5955
5956 if (__this_cpu_read(current_vcpu))
5957 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5958
5959 return ip;
5960 }
5961
5962 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5963 .is_in_guest = kvm_is_in_guest,
5964 .is_user_mode = kvm_is_user_mode,
5965 .get_guest_ip = kvm_get_guest_ip,
5966 };
5967
5968 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5969 {
5970 __this_cpu_write(current_vcpu, vcpu);
5971 }
5972 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5973
5974 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5975 {
5976 __this_cpu_write(current_vcpu, NULL);
5977 }
5978 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5979
5980 static void kvm_set_mmio_spte_mask(void)
5981 {
5982 u64 mask;
5983 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5984
5985 /*
5986 * Set the reserved bits and the present bit of an paging-structure
5987 * entry to generate page fault with PFER.RSV = 1.
5988 */
5989 /* Mask the reserved physical address bits. */
5990 mask = rsvd_bits(maxphyaddr, 51);
5991
5992 /* Set the present bit. */
5993 mask |= 1ull;
5994
5995 #ifdef CONFIG_X86_64
5996 /*
5997 * If reserved bit is not supported, clear the present bit to disable
5998 * mmio page fault.
5999 */
6000 if (maxphyaddr == 52)
6001 mask &= ~1ull;
6002 #endif
6003
6004 kvm_mmu_set_mmio_spte_mask(mask);
6005 }
6006
6007 #ifdef CONFIG_X86_64
6008 static void pvclock_gtod_update_fn(struct work_struct *work)
6009 {
6010 struct kvm *kvm;
6011
6012 struct kvm_vcpu *vcpu;
6013 int i;
6014
6015 spin_lock(&kvm_lock);
6016 list_for_each_entry(kvm, &vm_list, vm_list)
6017 kvm_for_each_vcpu(i, vcpu, kvm)
6018 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6019 atomic_set(&kvm_guest_has_master_clock, 0);
6020 spin_unlock(&kvm_lock);
6021 }
6022
6023 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6024
6025 /*
6026 * Notification about pvclock gtod data update.
6027 */
6028 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6029 void *priv)
6030 {
6031 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6032 struct timekeeper *tk = priv;
6033
6034 update_pvclock_gtod(tk);
6035
6036 /* disable master clock if host does not trust, or does not
6037 * use, TSC clocksource
6038 */
6039 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6040 atomic_read(&kvm_guest_has_master_clock) != 0)
6041 queue_work(system_long_wq, &pvclock_gtod_work);
6042
6043 return 0;
6044 }
6045
6046 static struct notifier_block pvclock_gtod_notifier = {
6047 .notifier_call = pvclock_gtod_notify,
6048 };
6049 #endif
6050
6051 int kvm_arch_init(void *opaque)
6052 {
6053 int r;
6054 struct kvm_x86_ops *ops = opaque;
6055
6056 if (kvm_x86_ops) {
6057 printk(KERN_ERR "kvm: already loaded the other module\n");
6058 r = -EEXIST;
6059 goto out;
6060 }
6061
6062 if (!ops->cpu_has_kvm_support()) {
6063 printk(KERN_ERR "kvm: no hardware support\n");
6064 r = -EOPNOTSUPP;
6065 goto out;
6066 }
6067 if (ops->disabled_by_bios()) {
6068 printk(KERN_ERR "kvm: disabled by bios\n");
6069 r = -EOPNOTSUPP;
6070 goto out;
6071 }
6072
6073 r = -ENOMEM;
6074 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6075 if (!shared_msrs) {
6076 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6077 goto out;
6078 }
6079
6080 r = kvm_mmu_module_init();
6081 if (r)
6082 goto out_free_percpu;
6083
6084 kvm_set_mmio_spte_mask();
6085
6086 kvm_x86_ops = ops;
6087
6088 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
6089 PT_DIRTY_MASK, PT64_NX_MASK, 0,
6090 PT_PRESENT_MASK, 0);
6091 kvm_timer_init();
6092
6093 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6094
6095 if (boot_cpu_has(X86_FEATURE_XSAVE))
6096 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6097
6098 kvm_lapic_init();
6099 #ifdef CONFIG_X86_64
6100 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6101 #endif
6102
6103 return 0;
6104
6105 out_free_percpu:
6106 free_percpu(shared_msrs);
6107 out:
6108 return r;
6109 }
6110
6111 void kvm_arch_exit(void)
6112 {
6113 kvm_lapic_exit();
6114 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6115
6116 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6117 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6118 CPUFREQ_TRANSITION_NOTIFIER);
6119 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
6120 #ifdef CONFIG_X86_64
6121 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6122 #endif
6123 kvm_x86_ops = NULL;
6124 kvm_mmu_module_exit();
6125 free_percpu(shared_msrs);
6126 }
6127
6128 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
6129 {
6130 ++vcpu->stat.halt_exits;
6131 if (lapic_in_kernel(vcpu)) {
6132 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
6133 return 1;
6134 } else {
6135 vcpu->run->exit_reason = KVM_EXIT_HLT;
6136 return 0;
6137 }
6138 }
6139 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6140
6141 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6142 {
6143 int ret = kvm_skip_emulated_instruction(vcpu);
6144 /*
6145 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6146 * KVM_EXIT_DEBUG here.
6147 */
6148 return kvm_vcpu_halt(vcpu) && ret;
6149 }
6150 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6151
6152 #ifdef CONFIG_X86_64
6153 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6154 unsigned long clock_type)
6155 {
6156 struct kvm_clock_pairing clock_pairing;
6157 struct timespec ts;
6158 u64 cycle;
6159 int ret;
6160
6161 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6162 return -KVM_EOPNOTSUPP;
6163
6164 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6165 return -KVM_EOPNOTSUPP;
6166
6167 clock_pairing.sec = ts.tv_sec;
6168 clock_pairing.nsec = ts.tv_nsec;
6169 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6170 clock_pairing.flags = 0;
6171
6172 ret = 0;
6173 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6174 sizeof(struct kvm_clock_pairing)))
6175 ret = -KVM_EFAULT;
6176
6177 return ret;
6178 }
6179 #endif
6180
6181 /*
6182 * kvm_pv_kick_cpu_op: Kick a vcpu.
6183 *
6184 * @apicid - apicid of vcpu to be kicked.
6185 */
6186 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6187 {
6188 struct kvm_lapic_irq lapic_irq;
6189
6190 lapic_irq.shorthand = 0;
6191 lapic_irq.dest_mode = 0;
6192 lapic_irq.dest_id = apicid;
6193 lapic_irq.msi_redir_hint = false;
6194
6195 lapic_irq.delivery_mode = APIC_DM_REMRD;
6196 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6197 }
6198
6199 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6200 {
6201 vcpu->arch.apicv_active = false;
6202 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6203 }
6204
6205 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6206 {
6207 unsigned long nr, a0, a1, a2, a3, ret;
6208 int op_64_bit, r;
6209
6210 r = kvm_skip_emulated_instruction(vcpu);
6211
6212 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6213 return kvm_hv_hypercall(vcpu);
6214
6215 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6216 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6217 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6218 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6219 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
6220
6221 trace_kvm_hypercall(nr, a0, a1, a2, a3);
6222
6223 op_64_bit = is_64_bit_mode(vcpu);
6224 if (!op_64_bit) {
6225 nr &= 0xFFFFFFFF;
6226 a0 &= 0xFFFFFFFF;
6227 a1 &= 0xFFFFFFFF;
6228 a2 &= 0xFFFFFFFF;
6229 a3 &= 0xFFFFFFFF;
6230 }
6231
6232 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6233 ret = -KVM_EPERM;
6234 goto out;
6235 }
6236
6237 switch (nr) {
6238 case KVM_HC_VAPIC_POLL_IRQ:
6239 ret = 0;
6240 break;
6241 case KVM_HC_KICK_CPU:
6242 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6243 ret = 0;
6244 break;
6245 #ifdef CONFIG_X86_64
6246 case KVM_HC_CLOCK_PAIRING:
6247 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6248 break;
6249 #endif
6250 default:
6251 ret = -KVM_ENOSYS;
6252 break;
6253 }
6254 out:
6255 if (!op_64_bit)
6256 ret = (u32)ret;
6257 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6258 ++vcpu->stat.hypercalls;
6259 return r;
6260 }
6261 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6262
6263 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6264 {
6265 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6266 char instruction[3];
6267 unsigned long rip = kvm_rip_read(vcpu);
6268
6269 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6270
6271 return emulator_write_emulated(ctxt, rip, instruction, 3,
6272 &ctxt->exception);
6273 }
6274
6275 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6276 {
6277 return vcpu->run->request_interrupt_window &&
6278 likely(!pic_in_kernel(vcpu->kvm));
6279 }
6280
6281 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6282 {
6283 struct kvm_run *kvm_run = vcpu->run;
6284
6285 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6286 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6287 kvm_run->cr8 = kvm_get_cr8(vcpu);
6288 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6289 kvm_run->ready_for_interrupt_injection =
6290 pic_in_kernel(vcpu->kvm) ||
6291 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6292 }
6293
6294 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6295 {
6296 int max_irr, tpr;
6297
6298 if (!kvm_x86_ops->update_cr8_intercept)
6299 return;
6300
6301 if (!lapic_in_kernel(vcpu))
6302 return;
6303
6304 if (vcpu->arch.apicv_active)
6305 return;
6306
6307 if (!vcpu->arch.apic->vapic_addr)
6308 max_irr = kvm_lapic_find_highest_irr(vcpu);
6309 else
6310 max_irr = -1;
6311
6312 if (max_irr != -1)
6313 max_irr >>= 4;
6314
6315 tpr = kvm_lapic_get_cr8(vcpu);
6316
6317 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6318 }
6319
6320 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6321 {
6322 int r;
6323
6324 /* try to reinject previous events if any */
6325 if (vcpu->arch.exception.pending) {
6326 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6327 vcpu->arch.exception.has_error_code,
6328 vcpu->arch.exception.error_code);
6329
6330 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6331 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6332 X86_EFLAGS_RF);
6333
6334 if (vcpu->arch.exception.nr == DB_VECTOR &&
6335 (vcpu->arch.dr7 & DR7_GD)) {
6336 vcpu->arch.dr7 &= ~DR7_GD;
6337 kvm_update_dr7(vcpu);
6338 }
6339
6340 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6341 vcpu->arch.exception.has_error_code,
6342 vcpu->arch.exception.error_code,
6343 vcpu->arch.exception.reinject);
6344 return 0;
6345 }
6346
6347 if (vcpu->arch.nmi_injected) {
6348 kvm_x86_ops->set_nmi(vcpu);
6349 return 0;
6350 }
6351
6352 if (vcpu->arch.interrupt.pending) {
6353 kvm_x86_ops->set_irq(vcpu);
6354 return 0;
6355 }
6356
6357 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6358 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6359 if (r != 0)
6360 return r;
6361 }
6362
6363 /* try to inject new event if pending */
6364 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6365 vcpu->arch.smi_pending = false;
6366 enter_smm(vcpu);
6367 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6368 --vcpu->arch.nmi_pending;
6369 vcpu->arch.nmi_injected = true;
6370 kvm_x86_ops->set_nmi(vcpu);
6371 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6372 /*
6373 * Because interrupts can be injected asynchronously, we are
6374 * calling check_nested_events again here to avoid a race condition.
6375 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6376 * proposal and current concerns. Perhaps we should be setting
6377 * KVM_REQ_EVENT only on certain events and not unconditionally?
6378 */
6379 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6380 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6381 if (r != 0)
6382 return r;
6383 }
6384 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6385 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6386 false);
6387 kvm_x86_ops->set_irq(vcpu);
6388 }
6389 }
6390
6391 return 0;
6392 }
6393
6394 static void process_nmi(struct kvm_vcpu *vcpu)
6395 {
6396 unsigned limit = 2;
6397
6398 /*
6399 * x86 is limited to one NMI running, and one NMI pending after it.
6400 * If an NMI is already in progress, limit further NMIs to just one.
6401 * Otherwise, allow two (and we'll inject the first one immediately).
6402 */
6403 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6404 limit = 1;
6405
6406 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6407 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6408 kvm_make_request(KVM_REQ_EVENT, vcpu);
6409 }
6410
6411 #define put_smstate(type, buf, offset, val) \
6412 *(type *)((buf) + (offset) - 0x7e00) = val
6413
6414 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
6415 {
6416 u32 flags = 0;
6417 flags |= seg->g << 23;
6418 flags |= seg->db << 22;
6419 flags |= seg->l << 21;
6420 flags |= seg->avl << 20;
6421 flags |= seg->present << 15;
6422 flags |= seg->dpl << 13;
6423 flags |= seg->s << 12;
6424 flags |= seg->type << 8;
6425 return flags;
6426 }
6427
6428 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6429 {
6430 struct kvm_segment seg;
6431 int offset;
6432
6433 kvm_get_segment(vcpu, &seg, n);
6434 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6435
6436 if (n < 3)
6437 offset = 0x7f84 + n * 12;
6438 else
6439 offset = 0x7f2c + (n - 3) * 12;
6440
6441 put_smstate(u32, buf, offset + 8, seg.base);
6442 put_smstate(u32, buf, offset + 4, seg.limit);
6443 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
6444 }
6445
6446 #ifdef CONFIG_X86_64
6447 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6448 {
6449 struct kvm_segment seg;
6450 int offset;
6451 u16 flags;
6452
6453 kvm_get_segment(vcpu, &seg, n);
6454 offset = 0x7e00 + n * 16;
6455
6456 flags = enter_smm_get_segment_flags(&seg) >> 8;
6457 put_smstate(u16, buf, offset, seg.selector);
6458 put_smstate(u16, buf, offset + 2, flags);
6459 put_smstate(u32, buf, offset + 4, seg.limit);
6460 put_smstate(u64, buf, offset + 8, seg.base);
6461 }
6462 #endif
6463
6464 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6465 {
6466 struct desc_ptr dt;
6467 struct kvm_segment seg;
6468 unsigned long val;
6469 int i;
6470
6471 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6472 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6473 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6474 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6475
6476 for (i = 0; i < 8; i++)
6477 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6478
6479 kvm_get_dr(vcpu, 6, &val);
6480 put_smstate(u32, buf, 0x7fcc, (u32)val);
6481 kvm_get_dr(vcpu, 7, &val);
6482 put_smstate(u32, buf, 0x7fc8, (u32)val);
6483
6484 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6485 put_smstate(u32, buf, 0x7fc4, seg.selector);
6486 put_smstate(u32, buf, 0x7f64, seg.base);
6487 put_smstate(u32, buf, 0x7f60, seg.limit);
6488 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
6489
6490 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6491 put_smstate(u32, buf, 0x7fc0, seg.selector);
6492 put_smstate(u32, buf, 0x7f80, seg.base);
6493 put_smstate(u32, buf, 0x7f7c, seg.limit);
6494 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
6495
6496 kvm_x86_ops->get_gdt(vcpu, &dt);
6497 put_smstate(u32, buf, 0x7f74, dt.address);
6498 put_smstate(u32, buf, 0x7f70, dt.size);
6499
6500 kvm_x86_ops->get_idt(vcpu, &dt);
6501 put_smstate(u32, buf, 0x7f58, dt.address);
6502 put_smstate(u32, buf, 0x7f54, dt.size);
6503
6504 for (i = 0; i < 6; i++)
6505 enter_smm_save_seg_32(vcpu, buf, i);
6506
6507 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6508
6509 /* revision id */
6510 put_smstate(u32, buf, 0x7efc, 0x00020000);
6511 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6512 }
6513
6514 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6515 {
6516 #ifdef CONFIG_X86_64
6517 struct desc_ptr dt;
6518 struct kvm_segment seg;
6519 unsigned long val;
6520 int i;
6521
6522 for (i = 0; i < 16; i++)
6523 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6524
6525 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6526 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6527
6528 kvm_get_dr(vcpu, 6, &val);
6529 put_smstate(u64, buf, 0x7f68, val);
6530 kvm_get_dr(vcpu, 7, &val);
6531 put_smstate(u64, buf, 0x7f60, val);
6532
6533 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6534 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6535 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6536
6537 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6538
6539 /* revision id */
6540 put_smstate(u32, buf, 0x7efc, 0x00020064);
6541
6542 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6543
6544 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6545 put_smstate(u16, buf, 0x7e90, seg.selector);
6546 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
6547 put_smstate(u32, buf, 0x7e94, seg.limit);
6548 put_smstate(u64, buf, 0x7e98, seg.base);
6549
6550 kvm_x86_ops->get_idt(vcpu, &dt);
6551 put_smstate(u32, buf, 0x7e84, dt.size);
6552 put_smstate(u64, buf, 0x7e88, dt.address);
6553
6554 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6555 put_smstate(u16, buf, 0x7e70, seg.selector);
6556 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
6557 put_smstate(u32, buf, 0x7e74, seg.limit);
6558 put_smstate(u64, buf, 0x7e78, seg.base);
6559
6560 kvm_x86_ops->get_gdt(vcpu, &dt);
6561 put_smstate(u32, buf, 0x7e64, dt.size);
6562 put_smstate(u64, buf, 0x7e68, dt.address);
6563
6564 for (i = 0; i < 6; i++)
6565 enter_smm_save_seg_64(vcpu, buf, i);
6566 #else
6567 WARN_ON_ONCE(1);
6568 #endif
6569 }
6570
6571 static void enter_smm(struct kvm_vcpu *vcpu)
6572 {
6573 struct kvm_segment cs, ds;
6574 struct desc_ptr dt;
6575 char buf[512];
6576 u32 cr0;
6577
6578 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6579 vcpu->arch.hflags |= HF_SMM_MASK;
6580 memset(buf, 0, 512);
6581 if (guest_cpuid_has_longmode(vcpu))
6582 enter_smm_save_state_64(vcpu, buf);
6583 else
6584 enter_smm_save_state_32(vcpu, buf);
6585
6586 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6587
6588 if (kvm_x86_ops->get_nmi_mask(vcpu))
6589 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6590 else
6591 kvm_x86_ops->set_nmi_mask(vcpu, true);
6592
6593 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6594 kvm_rip_write(vcpu, 0x8000);
6595
6596 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6597 kvm_x86_ops->set_cr0(vcpu, cr0);
6598 vcpu->arch.cr0 = cr0;
6599
6600 kvm_x86_ops->set_cr4(vcpu, 0);
6601
6602 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6603 dt.address = dt.size = 0;
6604 kvm_x86_ops->set_idt(vcpu, &dt);
6605
6606 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6607
6608 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6609 cs.base = vcpu->arch.smbase;
6610
6611 ds.selector = 0;
6612 ds.base = 0;
6613
6614 cs.limit = ds.limit = 0xffffffff;
6615 cs.type = ds.type = 0x3;
6616 cs.dpl = ds.dpl = 0;
6617 cs.db = ds.db = 0;
6618 cs.s = ds.s = 1;
6619 cs.l = ds.l = 0;
6620 cs.g = ds.g = 1;
6621 cs.avl = ds.avl = 0;
6622 cs.present = ds.present = 1;
6623 cs.unusable = ds.unusable = 0;
6624 cs.padding = ds.padding = 0;
6625
6626 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6627 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6628 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6629 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6630 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6631 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6632
6633 if (guest_cpuid_has_longmode(vcpu))
6634 kvm_x86_ops->set_efer(vcpu, 0);
6635
6636 kvm_update_cpuid(vcpu);
6637 kvm_mmu_reset_context(vcpu);
6638 }
6639
6640 static void process_smi(struct kvm_vcpu *vcpu)
6641 {
6642 vcpu->arch.smi_pending = true;
6643 kvm_make_request(KVM_REQ_EVENT, vcpu);
6644 }
6645
6646 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6647 {
6648 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6649 }
6650
6651 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6652 {
6653 u64 eoi_exit_bitmap[4];
6654
6655 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6656 return;
6657
6658 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6659
6660 if (irqchip_split(vcpu->kvm))
6661 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6662 else {
6663 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6664 kvm_x86_ops->sync_pir_to_irr(vcpu);
6665 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6666 }
6667 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6668 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6669 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6670 }
6671
6672 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6673 {
6674 ++vcpu->stat.tlb_flush;
6675 kvm_x86_ops->tlb_flush(vcpu);
6676 }
6677
6678 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6679 {
6680 struct page *page = NULL;
6681
6682 if (!lapic_in_kernel(vcpu))
6683 return;
6684
6685 if (!kvm_x86_ops->set_apic_access_page_addr)
6686 return;
6687
6688 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6689 if (is_error_page(page))
6690 return;
6691 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6692
6693 /*
6694 * Do not pin apic access page in memory, the MMU notifier
6695 * will call us again if it is migrated or swapped out.
6696 */
6697 put_page(page);
6698 }
6699 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6700
6701 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6702 unsigned long address)
6703 {
6704 /*
6705 * The physical address of apic access page is stored in the VMCS.
6706 * Update it when it becomes invalid.
6707 */
6708 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6709 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6710 }
6711
6712 /*
6713 * Returns 1 to let vcpu_run() continue the guest execution loop without
6714 * exiting to the userspace. Otherwise, the value will be returned to the
6715 * userspace.
6716 */
6717 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6718 {
6719 int r;
6720 bool req_int_win =
6721 dm_request_for_irq_injection(vcpu) &&
6722 kvm_cpu_accept_dm_intr(vcpu);
6723
6724 bool req_immediate_exit = false;
6725
6726 if (vcpu->requests) {
6727 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6728 kvm_mmu_unload(vcpu);
6729 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6730 __kvm_migrate_timers(vcpu);
6731 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6732 kvm_gen_update_masterclock(vcpu->kvm);
6733 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6734 kvm_gen_kvmclock_update(vcpu);
6735 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6736 r = kvm_guest_time_update(vcpu);
6737 if (unlikely(r))
6738 goto out;
6739 }
6740 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6741 kvm_mmu_sync_roots(vcpu);
6742 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6743 kvm_vcpu_flush_tlb(vcpu);
6744 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6745 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6746 r = 0;
6747 goto out;
6748 }
6749 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6750 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6751 r = 0;
6752 goto out;
6753 }
6754 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6755 /* Page is swapped out. Do synthetic halt */
6756 vcpu->arch.apf.halted = true;
6757 r = 1;
6758 goto out;
6759 }
6760 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6761 record_steal_time(vcpu);
6762 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6763 process_smi(vcpu);
6764 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6765 process_nmi(vcpu);
6766 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6767 kvm_pmu_handle_event(vcpu);
6768 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6769 kvm_pmu_deliver_pmi(vcpu);
6770 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6771 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6772 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6773 vcpu->arch.ioapic_handled_vectors)) {
6774 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6775 vcpu->run->eoi.vector =
6776 vcpu->arch.pending_ioapic_eoi;
6777 r = 0;
6778 goto out;
6779 }
6780 }
6781 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6782 vcpu_scan_ioapic(vcpu);
6783 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6784 kvm_vcpu_reload_apic_access_page(vcpu);
6785 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6786 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6787 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6788 r = 0;
6789 goto out;
6790 }
6791 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6792 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6793 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6794 r = 0;
6795 goto out;
6796 }
6797 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6798 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6799 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6800 r = 0;
6801 goto out;
6802 }
6803
6804 /*
6805 * KVM_REQ_HV_STIMER has to be processed after
6806 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6807 * depend on the guest clock being up-to-date
6808 */
6809 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6810 kvm_hv_process_stimers(vcpu);
6811 }
6812
6813 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6814 ++vcpu->stat.req_event;
6815 kvm_apic_accept_events(vcpu);
6816 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6817 r = 1;
6818 goto out;
6819 }
6820
6821 if (inject_pending_event(vcpu, req_int_win) != 0)
6822 req_immediate_exit = true;
6823 else {
6824 /* Enable NMI/IRQ window open exits if needed.
6825 *
6826 * SMIs have two cases: 1) they can be nested, and
6827 * then there is nothing to do here because RSM will
6828 * cause a vmexit anyway; 2) or the SMI can be pending
6829 * because inject_pending_event has completed the
6830 * injection of an IRQ or NMI from the previous vmexit,
6831 * and then we request an immediate exit to inject the SMI.
6832 */
6833 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6834 req_immediate_exit = true;
6835 if (vcpu->arch.nmi_pending)
6836 kvm_x86_ops->enable_nmi_window(vcpu);
6837 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6838 kvm_x86_ops->enable_irq_window(vcpu);
6839 }
6840
6841 if (kvm_lapic_enabled(vcpu)) {
6842 update_cr8_intercept(vcpu);
6843 kvm_lapic_sync_to_vapic(vcpu);
6844 }
6845 }
6846
6847 r = kvm_mmu_reload(vcpu);
6848 if (unlikely(r)) {
6849 goto cancel_injection;
6850 }
6851
6852 preempt_disable();
6853
6854 kvm_x86_ops->prepare_guest_switch(vcpu);
6855 kvm_load_guest_fpu(vcpu);
6856
6857 /*
6858 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6859 * IPI are then delayed after guest entry, which ensures that they
6860 * result in virtual interrupt delivery.
6861 */
6862 local_irq_disable();
6863 vcpu->mode = IN_GUEST_MODE;
6864
6865 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6866
6867 /*
6868 * 1) We should set ->mode before checking ->requests. Please see
6869 * the comment in kvm_make_all_cpus_request.
6870 *
6871 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6872 * pairs with the memory barrier implicit in pi_test_and_set_on
6873 * (see vmx_deliver_posted_interrupt).
6874 *
6875 * 3) This also orders the write to mode from any reads to the page
6876 * tables done while the VCPU is running. Please see the comment
6877 * in kvm_flush_remote_tlbs.
6878 */
6879 smp_mb__after_srcu_read_unlock();
6880
6881 /*
6882 * This handles the case where a posted interrupt was
6883 * notified with kvm_vcpu_kick.
6884 */
6885 if (kvm_lapic_enabled(vcpu)) {
6886 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6887 kvm_x86_ops->sync_pir_to_irr(vcpu);
6888 }
6889
6890 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6891 || need_resched() || signal_pending(current)) {
6892 vcpu->mode = OUTSIDE_GUEST_MODE;
6893 smp_wmb();
6894 local_irq_enable();
6895 preempt_enable();
6896 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6897 r = 1;
6898 goto cancel_injection;
6899 }
6900
6901 kvm_load_guest_xcr0(vcpu);
6902
6903 if (req_immediate_exit) {
6904 kvm_make_request(KVM_REQ_EVENT, vcpu);
6905 smp_send_reschedule(vcpu->cpu);
6906 }
6907
6908 trace_kvm_entry(vcpu->vcpu_id);
6909 wait_lapic_expire(vcpu);
6910 guest_enter_irqoff();
6911
6912 if (unlikely(vcpu->arch.switch_db_regs)) {
6913 set_debugreg(0, 7);
6914 set_debugreg(vcpu->arch.eff_db[0], 0);
6915 set_debugreg(vcpu->arch.eff_db[1], 1);
6916 set_debugreg(vcpu->arch.eff_db[2], 2);
6917 set_debugreg(vcpu->arch.eff_db[3], 3);
6918 set_debugreg(vcpu->arch.dr6, 6);
6919 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6920 }
6921
6922 kvm_x86_ops->run(vcpu);
6923
6924 /*
6925 * Do this here before restoring debug registers on the host. And
6926 * since we do this before handling the vmexit, a DR access vmexit
6927 * can (a) read the correct value of the debug registers, (b) set
6928 * KVM_DEBUGREG_WONT_EXIT again.
6929 */
6930 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6931 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6932 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6933 kvm_update_dr0123(vcpu);
6934 kvm_update_dr6(vcpu);
6935 kvm_update_dr7(vcpu);
6936 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6937 }
6938
6939 /*
6940 * If the guest has used debug registers, at least dr7
6941 * will be disabled while returning to the host.
6942 * If we don't have active breakpoints in the host, we don't
6943 * care about the messed up debug address registers. But if
6944 * we have some of them active, restore the old state.
6945 */
6946 if (hw_breakpoint_active())
6947 hw_breakpoint_restore();
6948
6949 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6950
6951 vcpu->mode = OUTSIDE_GUEST_MODE;
6952 smp_wmb();
6953
6954 kvm_put_guest_xcr0(vcpu);
6955
6956 kvm_x86_ops->handle_external_intr(vcpu);
6957
6958 ++vcpu->stat.exits;
6959
6960 guest_exit_irqoff();
6961
6962 local_irq_enable();
6963 preempt_enable();
6964
6965 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6966
6967 /*
6968 * Profile KVM exit RIPs:
6969 */
6970 if (unlikely(prof_on == KVM_PROFILING)) {
6971 unsigned long rip = kvm_rip_read(vcpu);
6972 profile_hit(KVM_PROFILING, (void *)rip);
6973 }
6974
6975 if (unlikely(vcpu->arch.tsc_always_catchup))
6976 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6977
6978 if (vcpu->arch.apic_attention)
6979 kvm_lapic_sync_from_vapic(vcpu);
6980
6981 r = kvm_x86_ops->handle_exit(vcpu);
6982 return r;
6983
6984 cancel_injection:
6985 kvm_x86_ops->cancel_injection(vcpu);
6986 if (unlikely(vcpu->arch.apic_attention))
6987 kvm_lapic_sync_from_vapic(vcpu);
6988 out:
6989 return r;
6990 }
6991
6992 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6993 {
6994 if (!kvm_arch_vcpu_runnable(vcpu) &&
6995 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
6996 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6997 kvm_vcpu_block(vcpu);
6998 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6999
7000 if (kvm_x86_ops->post_block)
7001 kvm_x86_ops->post_block(vcpu);
7002
7003 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7004 return 1;
7005 }
7006
7007 kvm_apic_accept_events(vcpu);
7008 switch(vcpu->arch.mp_state) {
7009 case KVM_MP_STATE_HALTED:
7010 vcpu->arch.pv.pv_unhalted = false;
7011 vcpu->arch.mp_state =
7012 KVM_MP_STATE_RUNNABLE;
7013 case KVM_MP_STATE_RUNNABLE:
7014 vcpu->arch.apf.halted = false;
7015 break;
7016 case KVM_MP_STATE_INIT_RECEIVED:
7017 break;
7018 default:
7019 return -EINTR;
7020 break;
7021 }
7022 return 1;
7023 }
7024
7025 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7026 {
7027 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7028 kvm_x86_ops->check_nested_events(vcpu, false);
7029
7030 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7031 !vcpu->arch.apf.halted);
7032 }
7033
7034 static int vcpu_run(struct kvm_vcpu *vcpu)
7035 {
7036 int r;
7037 struct kvm *kvm = vcpu->kvm;
7038
7039 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7040
7041 for (;;) {
7042 if (kvm_vcpu_running(vcpu)) {
7043 r = vcpu_enter_guest(vcpu);
7044 } else {
7045 r = vcpu_block(kvm, vcpu);
7046 }
7047
7048 if (r <= 0)
7049 break;
7050
7051 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
7052 if (kvm_cpu_has_pending_timer(vcpu))
7053 kvm_inject_pending_timer_irqs(vcpu);
7054
7055 if (dm_request_for_irq_injection(vcpu) &&
7056 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
7057 r = 0;
7058 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
7059 ++vcpu->stat.request_irq_exits;
7060 break;
7061 }
7062
7063 kvm_check_async_pf_completion(vcpu);
7064
7065 if (signal_pending(current)) {
7066 r = -EINTR;
7067 vcpu->run->exit_reason = KVM_EXIT_INTR;
7068 ++vcpu->stat.signal_exits;
7069 break;
7070 }
7071 if (need_resched()) {
7072 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7073 cond_resched();
7074 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7075 }
7076 }
7077
7078 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7079
7080 return r;
7081 }
7082
7083 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7084 {
7085 int r;
7086 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7087 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7088 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7089 if (r != EMULATE_DONE)
7090 return 0;
7091 return 1;
7092 }
7093
7094 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7095 {
7096 BUG_ON(!vcpu->arch.pio.count);
7097
7098 return complete_emulated_io(vcpu);
7099 }
7100
7101 /*
7102 * Implements the following, as a state machine:
7103 *
7104 * read:
7105 * for each fragment
7106 * for each mmio piece in the fragment
7107 * write gpa, len
7108 * exit
7109 * copy data
7110 * execute insn
7111 *
7112 * write:
7113 * for each fragment
7114 * for each mmio piece in the fragment
7115 * write gpa, len
7116 * copy data
7117 * exit
7118 */
7119 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
7120 {
7121 struct kvm_run *run = vcpu->run;
7122 struct kvm_mmio_fragment *frag;
7123 unsigned len;
7124
7125 BUG_ON(!vcpu->mmio_needed);
7126
7127 /* Complete previous fragment */
7128 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7129 len = min(8u, frag->len);
7130 if (!vcpu->mmio_is_write)
7131 memcpy(frag->data, run->mmio.data, len);
7132
7133 if (frag->len <= 8) {
7134 /* Switch to the next fragment. */
7135 frag++;
7136 vcpu->mmio_cur_fragment++;
7137 } else {
7138 /* Go forward to the next mmio piece. */
7139 frag->data += len;
7140 frag->gpa += len;
7141 frag->len -= len;
7142 }
7143
7144 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
7145 vcpu->mmio_needed = 0;
7146
7147 /* FIXME: return into emulator if single-stepping. */
7148 if (vcpu->mmio_is_write)
7149 return 1;
7150 vcpu->mmio_read_completed = 1;
7151 return complete_emulated_io(vcpu);
7152 }
7153
7154 run->exit_reason = KVM_EXIT_MMIO;
7155 run->mmio.phys_addr = frag->gpa;
7156 if (vcpu->mmio_is_write)
7157 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7158 run->mmio.len = min(8u, frag->len);
7159 run->mmio.is_write = vcpu->mmio_is_write;
7160 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7161 return 0;
7162 }
7163
7164
7165 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7166 {
7167 struct fpu *fpu = &current->thread.fpu;
7168 int r;
7169 sigset_t sigsaved;
7170
7171 fpu__activate_curr(fpu);
7172
7173 if (vcpu->sigset_active)
7174 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7175
7176 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
7177 kvm_vcpu_block(vcpu);
7178 kvm_apic_accept_events(vcpu);
7179 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
7180 r = -EAGAIN;
7181 goto out;
7182 }
7183
7184 /* re-sync apic's tpr */
7185 if (!lapic_in_kernel(vcpu)) {
7186 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7187 r = -EINVAL;
7188 goto out;
7189 }
7190 }
7191
7192 if (unlikely(vcpu->arch.complete_userspace_io)) {
7193 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7194 vcpu->arch.complete_userspace_io = NULL;
7195 r = cui(vcpu);
7196 if (r <= 0)
7197 goto out;
7198 } else
7199 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
7200
7201 if (kvm_run->immediate_exit)
7202 r = -EINTR;
7203 else
7204 r = vcpu_run(vcpu);
7205
7206 out:
7207 post_kvm_run_save(vcpu);
7208 if (vcpu->sigset_active)
7209 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7210
7211 return r;
7212 }
7213
7214 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7215 {
7216 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7217 /*
7218 * We are here if userspace calls get_regs() in the middle of
7219 * instruction emulation. Registers state needs to be copied
7220 * back from emulation context to vcpu. Userspace shouldn't do
7221 * that usually, but some bad designed PV devices (vmware
7222 * backdoor interface) need this to work
7223 */
7224 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7225 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7226 }
7227 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7228 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7229 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7230 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7231 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7232 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7233 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7234 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
7235 #ifdef CONFIG_X86_64
7236 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7237 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7238 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7239 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7240 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7241 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7242 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7243 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
7244 #endif
7245
7246 regs->rip = kvm_rip_read(vcpu);
7247 regs->rflags = kvm_get_rflags(vcpu);
7248
7249 return 0;
7250 }
7251
7252 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7253 {
7254 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7255 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7256
7257 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7258 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7259 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7260 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7261 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7262 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7263 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7264 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
7265 #ifdef CONFIG_X86_64
7266 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7267 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7268 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7269 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7270 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7271 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7272 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7273 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
7274 #endif
7275
7276 kvm_rip_write(vcpu, regs->rip);
7277 kvm_set_rflags(vcpu, regs->rflags);
7278
7279 vcpu->arch.exception.pending = false;
7280
7281 kvm_make_request(KVM_REQ_EVENT, vcpu);
7282
7283 return 0;
7284 }
7285
7286 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7287 {
7288 struct kvm_segment cs;
7289
7290 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7291 *db = cs.db;
7292 *l = cs.l;
7293 }
7294 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7295
7296 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7297 struct kvm_sregs *sregs)
7298 {
7299 struct desc_ptr dt;
7300
7301 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7302 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7303 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7304 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7305 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7306 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7307
7308 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7309 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7310
7311 kvm_x86_ops->get_idt(vcpu, &dt);
7312 sregs->idt.limit = dt.size;
7313 sregs->idt.base = dt.address;
7314 kvm_x86_ops->get_gdt(vcpu, &dt);
7315 sregs->gdt.limit = dt.size;
7316 sregs->gdt.base = dt.address;
7317
7318 sregs->cr0 = kvm_read_cr0(vcpu);
7319 sregs->cr2 = vcpu->arch.cr2;
7320 sregs->cr3 = kvm_read_cr3(vcpu);
7321 sregs->cr4 = kvm_read_cr4(vcpu);
7322 sregs->cr8 = kvm_get_cr8(vcpu);
7323 sregs->efer = vcpu->arch.efer;
7324 sregs->apic_base = kvm_get_apic_base(vcpu);
7325
7326 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7327
7328 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7329 set_bit(vcpu->arch.interrupt.nr,
7330 (unsigned long *)sregs->interrupt_bitmap);
7331
7332 return 0;
7333 }
7334
7335 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7336 struct kvm_mp_state *mp_state)
7337 {
7338 kvm_apic_accept_events(vcpu);
7339 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7340 vcpu->arch.pv.pv_unhalted)
7341 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7342 else
7343 mp_state->mp_state = vcpu->arch.mp_state;
7344
7345 return 0;
7346 }
7347
7348 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7349 struct kvm_mp_state *mp_state)
7350 {
7351 if (!lapic_in_kernel(vcpu) &&
7352 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7353 return -EINVAL;
7354
7355 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7356 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7357 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7358 } else
7359 vcpu->arch.mp_state = mp_state->mp_state;
7360 kvm_make_request(KVM_REQ_EVENT, vcpu);
7361 return 0;
7362 }
7363
7364 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7365 int reason, bool has_error_code, u32 error_code)
7366 {
7367 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7368 int ret;
7369
7370 init_emulate_ctxt(vcpu);
7371
7372 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7373 has_error_code, error_code);
7374
7375 if (ret)
7376 return EMULATE_FAIL;
7377
7378 kvm_rip_write(vcpu, ctxt->eip);
7379 kvm_set_rflags(vcpu, ctxt->eflags);
7380 kvm_make_request(KVM_REQ_EVENT, vcpu);
7381 return EMULATE_DONE;
7382 }
7383 EXPORT_SYMBOL_GPL(kvm_task_switch);
7384
7385 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7386 struct kvm_sregs *sregs)
7387 {
7388 struct msr_data apic_base_msr;
7389 int mmu_reset_needed = 0;
7390 int pending_vec, max_bits, idx;
7391 struct desc_ptr dt;
7392
7393 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7394 return -EINVAL;
7395
7396 dt.size = sregs->idt.limit;
7397 dt.address = sregs->idt.base;
7398 kvm_x86_ops->set_idt(vcpu, &dt);
7399 dt.size = sregs->gdt.limit;
7400 dt.address = sregs->gdt.base;
7401 kvm_x86_ops->set_gdt(vcpu, &dt);
7402
7403 vcpu->arch.cr2 = sregs->cr2;
7404 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7405 vcpu->arch.cr3 = sregs->cr3;
7406 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7407
7408 kvm_set_cr8(vcpu, sregs->cr8);
7409
7410 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7411 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7412 apic_base_msr.data = sregs->apic_base;
7413 apic_base_msr.host_initiated = true;
7414 kvm_set_apic_base(vcpu, &apic_base_msr);
7415
7416 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7417 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7418 vcpu->arch.cr0 = sregs->cr0;
7419
7420 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7421 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7422 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
7423 kvm_update_cpuid(vcpu);
7424
7425 idx = srcu_read_lock(&vcpu->kvm->srcu);
7426 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7427 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7428 mmu_reset_needed = 1;
7429 }
7430 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7431
7432 if (mmu_reset_needed)
7433 kvm_mmu_reset_context(vcpu);
7434
7435 max_bits = KVM_NR_INTERRUPTS;
7436 pending_vec = find_first_bit(
7437 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7438 if (pending_vec < max_bits) {
7439 kvm_queue_interrupt(vcpu, pending_vec, false);
7440 pr_debug("Set back pending irq %d\n", pending_vec);
7441 }
7442
7443 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7444 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7445 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7446 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7447 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7448 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7449
7450 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7451 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7452
7453 update_cr8_intercept(vcpu);
7454
7455 /* Older userspace won't unhalt the vcpu on reset. */
7456 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7457 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7458 !is_protmode(vcpu))
7459 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7460
7461 kvm_make_request(KVM_REQ_EVENT, vcpu);
7462
7463 return 0;
7464 }
7465
7466 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7467 struct kvm_guest_debug *dbg)
7468 {
7469 unsigned long rflags;
7470 int i, r;
7471
7472 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7473 r = -EBUSY;
7474 if (vcpu->arch.exception.pending)
7475 goto out;
7476 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7477 kvm_queue_exception(vcpu, DB_VECTOR);
7478 else
7479 kvm_queue_exception(vcpu, BP_VECTOR);
7480 }
7481
7482 /*
7483 * Read rflags as long as potentially injected trace flags are still
7484 * filtered out.
7485 */
7486 rflags = kvm_get_rflags(vcpu);
7487
7488 vcpu->guest_debug = dbg->control;
7489 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7490 vcpu->guest_debug = 0;
7491
7492 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7493 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7494 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7495 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7496 } else {
7497 for (i = 0; i < KVM_NR_DB_REGS; i++)
7498 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7499 }
7500 kvm_update_dr7(vcpu);
7501
7502 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7503 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7504 get_segment_base(vcpu, VCPU_SREG_CS);
7505
7506 /*
7507 * Trigger an rflags update that will inject or remove the trace
7508 * flags.
7509 */
7510 kvm_set_rflags(vcpu, rflags);
7511
7512 kvm_x86_ops->update_bp_intercept(vcpu);
7513
7514 r = 0;
7515
7516 out:
7517
7518 return r;
7519 }
7520
7521 /*
7522 * Translate a guest virtual address to a guest physical address.
7523 */
7524 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7525 struct kvm_translation *tr)
7526 {
7527 unsigned long vaddr = tr->linear_address;
7528 gpa_t gpa;
7529 int idx;
7530
7531 idx = srcu_read_lock(&vcpu->kvm->srcu);
7532 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7533 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7534 tr->physical_address = gpa;
7535 tr->valid = gpa != UNMAPPED_GVA;
7536 tr->writeable = 1;
7537 tr->usermode = 0;
7538
7539 return 0;
7540 }
7541
7542 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7543 {
7544 struct fxregs_state *fxsave =
7545 &vcpu->arch.guest_fpu.state.fxsave;
7546
7547 memcpy(fpu->fpr, fxsave->st_space, 128);
7548 fpu->fcw = fxsave->cwd;
7549 fpu->fsw = fxsave->swd;
7550 fpu->ftwx = fxsave->twd;
7551 fpu->last_opcode = fxsave->fop;
7552 fpu->last_ip = fxsave->rip;
7553 fpu->last_dp = fxsave->rdp;
7554 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7555
7556 return 0;
7557 }
7558
7559 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7560 {
7561 struct fxregs_state *fxsave =
7562 &vcpu->arch.guest_fpu.state.fxsave;
7563
7564 memcpy(fxsave->st_space, fpu->fpr, 128);
7565 fxsave->cwd = fpu->fcw;
7566 fxsave->swd = fpu->fsw;
7567 fxsave->twd = fpu->ftwx;
7568 fxsave->fop = fpu->last_opcode;
7569 fxsave->rip = fpu->last_ip;
7570 fxsave->rdp = fpu->last_dp;
7571 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7572
7573 return 0;
7574 }
7575
7576 static void fx_init(struct kvm_vcpu *vcpu)
7577 {
7578 fpstate_init(&vcpu->arch.guest_fpu.state);
7579 if (boot_cpu_has(X86_FEATURE_XSAVES))
7580 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7581 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7582
7583 /*
7584 * Ensure guest xcr0 is valid for loading
7585 */
7586 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7587
7588 vcpu->arch.cr0 |= X86_CR0_ET;
7589 }
7590
7591 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7592 {
7593 if (vcpu->guest_fpu_loaded)
7594 return;
7595
7596 /*
7597 * Restore all possible states in the guest,
7598 * and assume host would use all available bits.
7599 * Guest xcr0 would be loaded later.
7600 */
7601 vcpu->guest_fpu_loaded = 1;
7602 __kernel_fpu_begin();
7603 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7604 trace_kvm_fpu(1);
7605 }
7606
7607 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7608 {
7609 if (!vcpu->guest_fpu_loaded)
7610 return;
7611
7612 vcpu->guest_fpu_loaded = 0;
7613 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7614 __kernel_fpu_end();
7615 ++vcpu->stat.fpu_reload;
7616 trace_kvm_fpu(0);
7617 }
7618
7619 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7620 {
7621 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7622
7623 kvmclock_reset(vcpu);
7624
7625 kvm_x86_ops->vcpu_free(vcpu);
7626 free_cpumask_var(wbinvd_dirty_mask);
7627 }
7628
7629 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7630 unsigned int id)
7631 {
7632 struct kvm_vcpu *vcpu;
7633
7634 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7635 printk_once(KERN_WARNING
7636 "kvm: SMP vm created on host with unstable TSC; "
7637 "guest TSC will not be reliable\n");
7638
7639 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7640
7641 return vcpu;
7642 }
7643
7644 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7645 {
7646 int r;
7647
7648 kvm_vcpu_mtrr_init(vcpu);
7649 r = vcpu_load(vcpu);
7650 if (r)
7651 return r;
7652 kvm_vcpu_reset(vcpu, false);
7653 kvm_mmu_setup(vcpu);
7654 vcpu_put(vcpu);
7655 return r;
7656 }
7657
7658 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7659 {
7660 struct msr_data msr;
7661 struct kvm *kvm = vcpu->kvm;
7662
7663 if (vcpu_load(vcpu))
7664 return;
7665 msr.data = 0x0;
7666 msr.index = MSR_IA32_TSC;
7667 msr.host_initiated = true;
7668 kvm_write_tsc(vcpu, &msr);
7669 vcpu_put(vcpu);
7670
7671 if (!kvmclock_periodic_sync)
7672 return;
7673
7674 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7675 KVMCLOCK_SYNC_PERIOD);
7676 }
7677
7678 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7679 {
7680 int r;
7681 vcpu->arch.apf.msr_val = 0;
7682
7683 r = vcpu_load(vcpu);
7684 BUG_ON(r);
7685 kvm_mmu_unload(vcpu);
7686 vcpu_put(vcpu);
7687
7688 kvm_x86_ops->vcpu_free(vcpu);
7689 }
7690
7691 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7692 {
7693 vcpu->arch.hflags = 0;
7694
7695 vcpu->arch.smi_pending = 0;
7696 atomic_set(&vcpu->arch.nmi_queued, 0);
7697 vcpu->arch.nmi_pending = 0;
7698 vcpu->arch.nmi_injected = false;
7699 kvm_clear_interrupt_queue(vcpu);
7700 kvm_clear_exception_queue(vcpu);
7701
7702 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7703 kvm_update_dr0123(vcpu);
7704 vcpu->arch.dr6 = DR6_INIT;
7705 kvm_update_dr6(vcpu);
7706 vcpu->arch.dr7 = DR7_FIXED_1;
7707 kvm_update_dr7(vcpu);
7708
7709 vcpu->arch.cr2 = 0;
7710
7711 kvm_make_request(KVM_REQ_EVENT, vcpu);
7712 vcpu->arch.apf.msr_val = 0;
7713 vcpu->arch.st.msr_val = 0;
7714
7715 kvmclock_reset(vcpu);
7716
7717 kvm_clear_async_pf_completion_queue(vcpu);
7718 kvm_async_pf_hash_reset(vcpu);
7719 vcpu->arch.apf.halted = false;
7720
7721 if (!init_event) {
7722 kvm_pmu_reset(vcpu);
7723 vcpu->arch.smbase = 0x30000;
7724 }
7725
7726 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7727 vcpu->arch.regs_avail = ~0;
7728 vcpu->arch.regs_dirty = ~0;
7729
7730 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7731 }
7732
7733 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7734 {
7735 struct kvm_segment cs;
7736
7737 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7738 cs.selector = vector << 8;
7739 cs.base = vector << 12;
7740 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7741 kvm_rip_write(vcpu, 0);
7742 }
7743
7744 int kvm_arch_hardware_enable(void)
7745 {
7746 struct kvm *kvm;
7747 struct kvm_vcpu *vcpu;
7748 int i;
7749 int ret;
7750 u64 local_tsc;
7751 u64 max_tsc = 0;
7752 bool stable, backwards_tsc = false;
7753
7754 kvm_shared_msr_cpu_online();
7755 ret = kvm_x86_ops->hardware_enable();
7756 if (ret != 0)
7757 return ret;
7758
7759 local_tsc = rdtsc();
7760 stable = !check_tsc_unstable();
7761 list_for_each_entry(kvm, &vm_list, vm_list) {
7762 kvm_for_each_vcpu(i, vcpu, kvm) {
7763 if (!stable && vcpu->cpu == smp_processor_id())
7764 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7765 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7766 backwards_tsc = true;
7767 if (vcpu->arch.last_host_tsc > max_tsc)
7768 max_tsc = vcpu->arch.last_host_tsc;
7769 }
7770 }
7771 }
7772
7773 /*
7774 * Sometimes, even reliable TSCs go backwards. This happens on
7775 * platforms that reset TSC during suspend or hibernate actions, but
7776 * maintain synchronization. We must compensate. Fortunately, we can
7777 * detect that condition here, which happens early in CPU bringup,
7778 * before any KVM threads can be running. Unfortunately, we can't
7779 * bring the TSCs fully up to date with real time, as we aren't yet far
7780 * enough into CPU bringup that we know how much real time has actually
7781 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
7782 * variables that haven't been updated yet.
7783 *
7784 * So we simply find the maximum observed TSC above, then record the
7785 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7786 * the adjustment will be applied. Note that we accumulate
7787 * adjustments, in case multiple suspend cycles happen before some VCPU
7788 * gets a chance to run again. In the event that no KVM threads get a
7789 * chance to run, we will miss the entire elapsed period, as we'll have
7790 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7791 * loose cycle time. This isn't too big a deal, since the loss will be
7792 * uniform across all VCPUs (not to mention the scenario is extremely
7793 * unlikely). It is possible that a second hibernate recovery happens
7794 * much faster than a first, causing the observed TSC here to be
7795 * smaller; this would require additional padding adjustment, which is
7796 * why we set last_host_tsc to the local tsc observed here.
7797 *
7798 * N.B. - this code below runs only on platforms with reliable TSC,
7799 * as that is the only way backwards_tsc is set above. Also note
7800 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7801 * have the same delta_cyc adjustment applied if backwards_tsc
7802 * is detected. Note further, this adjustment is only done once,
7803 * as we reset last_host_tsc on all VCPUs to stop this from being
7804 * called multiple times (one for each physical CPU bringup).
7805 *
7806 * Platforms with unreliable TSCs don't have to deal with this, they
7807 * will be compensated by the logic in vcpu_load, which sets the TSC to
7808 * catchup mode. This will catchup all VCPUs to real time, but cannot
7809 * guarantee that they stay in perfect synchronization.
7810 */
7811 if (backwards_tsc) {
7812 u64 delta_cyc = max_tsc - local_tsc;
7813 backwards_tsc_observed = true;
7814 list_for_each_entry(kvm, &vm_list, vm_list) {
7815 kvm_for_each_vcpu(i, vcpu, kvm) {
7816 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7817 vcpu->arch.last_host_tsc = local_tsc;
7818 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7819 }
7820
7821 /*
7822 * We have to disable TSC offset matching.. if you were
7823 * booting a VM while issuing an S4 host suspend....
7824 * you may have some problem. Solving this issue is
7825 * left as an exercise to the reader.
7826 */
7827 kvm->arch.last_tsc_nsec = 0;
7828 kvm->arch.last_tsc_write = 0;
7829 }
7830
7831 }
7832 return 0;
7833 }
7834
7835 void kvm_arch_hardware_disable(void)
7836 {
7837 kvm_x86_ops->hardware_disable();
7838 drop_user_return_notifiers();
7839 }
7840
7841 int kvm_arch_hardware_setup(void)
7842 {
7843 int r;
7844
7845 r = kvm_x86_ops->hardware_setup();
7846 if (r != 0)
7847 return r;
7848
7849 if (kvm_has_tsc_control) {
7850 /*
7851 * Make sure the user can only configure tsc_khz values that
7852 * fit into a signed integer.
7853 * A min value is not calculated needed because it will always
7854 * be 1 on all machines.
7855 */
7856 u64 max = min(0x7fffffffULL,
7857 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7858 kvm_max_guest_tsc_khz = max;
7859
7860 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
7861 }
7862
7863 kvm_init_msr_list();
7864 return 0;
7865 }
7866
7867 void kvm_arch_hardware_unsetup(void)
7868 {
7869 kvm_x86_ops->hardware_unsetup();
7870 }
7871
7872 void kvm_arch_check_processor_compat(void *rtn)
7873 {
7874 kvm_x86_ops->check_processor_compatibility(rtn);
7875 }
7876
7877 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7878 {
7879 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7880 }
7881 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7882
7883 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7884 {
7885 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7886 }
7887
7888 struct static_key kvm_no_apic_vcpu __read_mostly;
7889 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
7890
7891 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7892 {
7893 struct page *page;
7894 struct kvm *kvm;
7895 int r;
7896
7897 BUG_ON(vcpu->kvm == NULL);
7898 kvm = vcpu->kvm;
7899
7900 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
7901 vcpu->arch.pv.pv_unhalted = false;
7902 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7903 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7904 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7905 else
7906 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7907
7908 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7909 if (!page) {
7910 r = -ENOMEM;
7911 goto fail;
7912 }
7913 vcpu->arch.pio_data = page_address(page);
7914
7915 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7916
7917 r = kvm_mmu_create(vcpu);
7918 if (r < 0)
7919 goto fail_free_pio_data;
7920
7921 if (irqchip_in_kernel(kvm)) {
7922 r = kvm_create_lapic(vcpu);
7923 if (r < 0)
7924 goto fail_mmu_destroy;
7925 } else
7926 static_key_slow_inc(&kvm_no_apic_vcpu);
7927
7928 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7929 GFP_KERNEL);
7930 if (!vcpu->arch.mce_banks) {
7931 r = -ENOMEM;
7932 goto fail_free_lapic;
7933 }
7934 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7935
7936 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7937 r = -ENOMEM;
7938 goto fail_free_mce_banks;
7939 }
7940
7941 fx_init(vcpu);
7942
7943 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7944 vcpu->arch.pv_time_enabled = false;
7945
7946 vcpu->arch.guest_supported_xcr0 = 0;
7947 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7948
7949 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7950
7951 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7952
7953 kvm_async_pf_hash_reset(vcpu);
7954 kvm_pmu_init(vcpu);
7955
7956 vcpu->arch.pending_external_vector = -1;
7957
7958 kvm_hv_vcpu_init(vcpu);
7959
7960 return 0;
7961
7962 fail_free_mce_banks:
7963 kfree(vcpu->arch.mce_banks);
7964 fail_free_lapic:
7965 kvm_free_lapic(vcpu);
7966 fail_mmu_destroy:
7967 kvm_mmu_destroy(vcpu);
7968 fail_free_pio_data:
7969 free_page((unsigned long)vcpu->arch.pio_data);
7970 fail:
7971 return r;
7972 }
7973
7974 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7975 {
7976 int idx;
7977
7978 kvm_hv_vcpu_uninit(vcpu);
7979 kvm_pmu_destroy(vcpu);
7980 kfree(vcpu->arch.mce_banks);
7981 kvm_free_lapic(vcpu);
7982 idx = srcu_read_lock(&vcpu->kvm->srcu);
7983 kvm_mmu_destroy(vcpu);
7984 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7985 free_page((unsigned long)vcpu->arch.pio_data);
7986 if (!lapic_in_kernel(vcpu))
7987 static_key_slow_dec(&kvm_no_apic_vcpu);
7988 }
7989
7990 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7991 {
7992 kvm_x86_ops->sched_in(vcpu, cpu);
7993 }
7994
7995 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7996 {
7997 if (type)
7998 return -EINVAL;
7999
8000 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
8001 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
8002 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
8003 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
8004 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
8005
8006 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8007 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
8008 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8009 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8010 &kvm->arch.irq_sources_bitmap);
8011
8012 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
8013 mutex_init(&kvm->arch.apic_map_lock);
8014 mutex_init(&kvm->arch.hyperv.hv_lock);
8015 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8016
8017 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
8018 pvclock_update_vm_gtod_copy(kvm);
8019
8020 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
8021 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
8022
8023 kvm_page_track_init(kvm);
8024 kvm_mmu_init_vm(kvm);
8025
8026 if (kvm_x86_ops->vm_init)
8027 return kvm_x86_ops->vm_init(kvm);
8028
8029 return 0;
8030 }
8031
8032 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8033 {
8034 int r;
8035 r = vcpu_load(vcpu);
8036 BUG_ON(r);
8037 kvm_mmu_unload(vcpu);
8038 vcpu_put(vcpu);
8039 }
8040
8041 static void kvm_free_vcpus(struct kvm *kvm)
8042 {
8043 unsigned int i;
8044 struct kvm_vcpu *vcpu;
8045
8046 /*
8047 * Unpin any mmu pages first.
8048 */
8049 kvm_for_each_vcpu(i, vcpu, kvm) {
8050 kvm_clear_async_pf_completion_queue(vcpu);
8051 kvm_unload_vcpu_mmu(vcpu);
8052 }
8053 kvm_for_each_vcpu(i, vcpu, kvm)
8054 kvm_arch_vcpu_free(vcpu);
8055
8056 mutex_lock(&kvm->lock);
8057 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8058 kvm->vcpus[i] = NULL;
8059
8060 atomic_set(&kvm->online_vcpus, 0);
8061 mutex_unlock(&kvm->lock);
8062 }
8063
8064 void kvm_arch_sync_events(struct kvm *kvm)
8065 {
8066 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
8067 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
8068 kvm_free_all_assigned_devices(kvm);
8069 kvm_free_pit(kvm);
8070 }
8071
8072 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8073 {
8074 int i, r;
8075 unsigned long hva;
8076 struct kvm_memslots *slots = kvm_memslots(kvm);
8077 struct kvm_memory_slot *slot, old;
8078
8079 /* Called with kvm->slots_lock held. */
8080 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8081 return -EINVAL;
8082
8083 slot = id_to_memslot(slots, id);
8084 if (size) {
8085 if (slot->npages)
8086 return -EEXIST;
8087
8088 /*
8089 * MAP_SHARED to prevent internal slot pages from being moved
8090 * by fork()/COW.
8091 */
8092 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8093 MAP_SHARED | MAP_ANONYMOUS, 0);
8094 if (IS_ERR((void *)hva))
8095 return PTR_ERR((void *)hva);
8096 } else {
8097 if (!slot->npages)
8098 return 0;
8099
8100 hva = 0;
8101 }
8102
8103 old = *slot;
8104 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
8105 struct kvm_userspace_memory_region m;
8106
8107 m.slot = id | (i << 16);
8108 m.flags = 0;
8109 m.guest_phys_addr = gpa;
8110 m.userspace_addr = hva;
8111 m.memory_size = size;
8112 r = __kvm_set_memory_region(kvm, &m);
8113 if (r < 0)
8114 return r;
8115 }
8116
8117 if (!size) {
8118 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8119 WARN_ON(r < 0);
8120 }
8121
8122 return 0;
8123 }
8124 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8125
8126 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8127 {
8128 int r;
8129
8130 mutex_lock(&kvm->slots_lock);
8131 r = __x86_set_memory_region(kvm, id, gpa, size);
8132 mutex_unlock(&kvm->slots_lock);
8133
8134 return r;
8135 }
8136 EXPORT_SYMBOL_GPL(x86_set_memory_region);
8137
8138 void kvm_arch_destroy_vm(struct kvm *kvm)
8139 {
8140 if (current->mm == kvm->mm) {
8141 /*
8142 * Free memory regions allocated on behalf of userspace,
8143 * unless the the memory map has changed due to process exit
8144 * or fd copying.
8145 */
8146 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8147 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8148 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
8149 }
8150 if (kvm_x86_ops->vm_destroy)
8151 kvm_x86_ops->vm_destroy(kvm);
8152 kvm_iommu_unmap_guest(kvm);
8153 kfree(kvm->arch.vpic);
8154 kfree(kvm->arch.vioapic);
8155 kvm_free_vcpus(kvm);
8156 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
8157 kvm_mmu_uninit_vm(kvm);
8158 }
8159
8160 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
8161 struct kvm_memory_slot *dont)
8162 {
8163 int i;
8164
8165 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8166 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
8167 kvfree(free->arch.rmap[i]);
8168 free->arch.rmap[i] = NULL;
8169 }
8170 if (i == 0)
8171 continue;
8172
8173 if (!dont || free->arch.lpage_info[i - 1] !=
8174 dont->arch.lpage_info[i - 1]) {
8175 kvfree(free->arch.lpage_info[i - 1]);
8176 free->arch.lpage_info[i - 1] = NULL;
8177 }
8178 }
8179
8180 kvm_page_track_free_memslot(free, dont);
8181 }
8182
8183 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8184 unsigned long npages)
8185 {
8186 int i;
8187
8188 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8189 struct kvm_lpage_info *linfo;
8190 unsigned long ugfn;
8191 int lpages;
8192 int level = i + 1;
8193
8194 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8195 slot->base_gfn, level) + 1;
8196
8197 slot->arch.rmap[i] =
8198 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
8199 if (!slot->arch.rmap[i])
8200 goto out_free;
8201 if (i == 0)
8202 continue;
8203
8204 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
8205 if (!linfo)
8206 goto out_free;
8207
8208 slot->arch.lpage_info[i - 1] = linfo;
8209
8210 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
8211 linfo[0].disallow_lpage = 1;
8212 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
8213 linfo[lpages - 1].disallow_lpage = 1;
8214 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8215 /*
8216 * If the gfn and userspace address are not aligned wrt each
8217 * other, or if explicitly asked to, disable large page
8218 * support for this slot
8219 */
8220 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8221 !kvm_largepages_enabled()) {
8222 unsigned long j;
8223
8224 for (j = 0; j < lpages; ++j)
8225 linfo[j].disallow_lpage = 1;
8226 }
8227 }
8228
8229 if (kvm_page_track_create_memslot(slot, npages))
8230 goto out_free;
8231
8232 return 0;
8233
8234 out_free:
8235 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8236 kvfree(slot->arch.rmap[i]);
8237 slot->arch.rmap[i] = NULL;
8238 if (i == 0)
8239 continue;
8240
8241 kvfree(slot->arch.lpage_info[i - 1]);
8242 slot->arch.lpage_info[i - 1] = NULL;
8243 }
8244 return -ENOMEM;
8245 }
8246
8247 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
8248 {
8249 /*
8250 * memslots->generation has been incremented.
8251 * mmio generation may have reached its maximum value.
8252 */
8253 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
8254 }
8255
8256 int kvm_arch_prepare_memory_region(struct kvm *kvm,
8257 struct kvm_memory_slot *memslot,
8258 const struct kvm_userspace_memory_region *mem,
8259 enum kvm_mr_change change)
8260 {
8261 return 0;
8262 }
8263
8264 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8265 struct kvm_memory_slot *new)
8266 {
8267 /* Still write protect RO slot */
8268 if (new->flags & KVM_MEM_READONLY) {
8269 kvm_mmu_slot_remove_write_access(kvm, new);
8270 return;
8271 }
8272
8273 /*
8274 * Call kvm_x86_ops dirty logging hooks when they are valid.
8275 *
8276 * kvm_x86_ops->slot_disable_log_dirty is called when:
8277 *
8278 * - KVM_MR_CREATE with dirty logging is disabled
8279 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8280 *
8281 * The reason is, in case of PML, we need to set D-bit for any slots
8282 * with dirty logging disabled in order to eliminate unnecessary GPA
8283 * logging in PML buffer (and potential PML buffer full VMEXT). This
8284 * guarantees leaving PML enabled during guest's lifetime won't have
8285 * any additonal overhead from PML when guest is running with dirty
8286 * logging disabled for memory slots.
8287 *
8288 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8289 * to dirty logging mode.
8290 *
8291 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8292 *
8293 * In case of write protect:
8294 *
8295 * Write protect all pages for dirty logging.
8296 *
8297 * All the sptes including the large sptes which point to this
8298 * slot are set to readonly. We can not create any new large
8299 * spte on this slot until the end of the logging.
8300 *
8301 * See the comments in fast_page_fault().
8302 */
8303 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8304 if (kvm_x86_ops->slot_enable_log_dirty)
8305 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8306 else
8307 kvm_mmu_slot_remove_write_access(kvm, new);
8308 } else {
8309 if (kvm_x86_ops->slot_disable_log_dirty)
8310 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8311 }
8312 }
8313
8314 void kvm_arch_commit_memory_region(struct kvm *kvm,
8315 const struct kvm_userspace_memory_region *mem,
8316 const struct kvm_memory_slot *old,
8317 const struct kvm_memory_slot *new,
8318 enum kvm_mr_change change)
8319 {
8320 int nr_mmu_pages = 0;
8321
8322 if (!kvm->arch.n_requested_mmu_pages)
8323 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8324
8325 if (nr_mmu_pages)
8326 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8327
8328 /*
8329 * Dirty logging tracks sptes in 4k granularity, meaning that large
8330 * sptes have to be split. If live migration is successful, the guest
8331 * in the source machine will be destroyed and large sptes will be
8332 * created in the destination. However, if the guest continues to run
8333 * in the source machine (for example if live migration fails), small
8334 * sptes will remain around and cause bad performance.
8335 *
8336 * Scan sptes if dirty logging has been stopped, dropping those
8337 * which can be collapsed into a single large-page spte. Later
8338 * page faults will create the large-page sptes.
8339 */
8340 if ((change != KVM_MR_DELETE) &&
8341 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8342 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8343 kvm_mmu_zap_collapsible_sptes(kvm, new);
8344
8345 /*
8346 * Set up write protection and/or dirty logging for the new slot.
8347 *
8348 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8349 * been zapped so no dirty logging staff is needed for old slot. For
8350 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8351 * new and it's also covered when dealing with the new slot.
8352 *
8353 * FIXME: const-ify all uses of struct kvm_memory_slot.
8354 */
8355 if (change != KVM_MR_DELETE)
8356 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8357 }
8358
8359 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8360 {
8361 kvm_mmu_invalidate_zap_all_pages(kvm);
8362 }
8363
8364 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8365 struct kvm_memory_slot *slot)
8366 {
8367 kvm_page_track_flush_slot(kvm, slot);
8368 }
8369
8370 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8371 {
8372 if (!list_empty_careful(&vcpu->async_pf.done))
8373 return true;
8374
8375 if (kvm_apic_has_events(vcpu))
8376 return true;
8377
8378 if (vcpu->arch.pv.pv_unhalted)
8379 return true;
8380
8381 if (atomic_read(&vcpu->arch.nmi_queued))
8382 return true;
8383
8384 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8385 return true;
8386
8387 if (kvm_arch_interrupt_allowed(vcpu) &&
8388 kvm_cpu_has_interrupt(vcpu))
8389 return true;
8390
8391 if (kvm_hv_has_stimer_pending(vcpu))
8392 return true;
8393
8394 return false;
8395 }
8396
8397 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8398 {
8399 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8400 }
8401
8402 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8403 {
8404 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8405 }
8406
8407 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8408 {
8409 return kvm_x86_ops->interrupt_allowed(vcpu);
8410 }
8411
8412 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8413 {
8414 if (is_64_bit_mode(vcpu))
8415 return kvm_rip_read(vcpu);
8416 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8417 kvm_rip_read(vcpu));
8418 }
8419 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8420
8421 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8422 {
8423 return kvm_get_linear_rip(vcpu) == linear_rip;
8424 }
8425 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8426
8427 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8428 {
8429 unsigned long rflags;
8430
8431 rflags = kvm_x86_ops->get_rflags(vcpu);
8432 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8433 rflags &= ~X86_EFLAGS_TF;
8434 return rflags;
8435 }
8436 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8437
8438 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8439 {
8440 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8441 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8442 rflags |= X86_EFLAGS_TF;
8443 kvm_x86_ops->set_rflags(vcpu, rflags);
8444 }
8445
8446 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8447 {
8448 __kvm_set_rflags(vcpu, rflags);
8449 kvm_make_request(KVM_REQ_EVENT, vcpu);
8450 }
8451 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8452
8453 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8454 {
8455 int r;
8456
8457 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8458 work->wakeup_all)
8459 return;
8460
8461 r = kvm_mmu_reload(vcpu);
8462 if (unlikely(r))
8463 return;
8464
8465 if (!vcpu->arch.mmu.direct_map &&
8466 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8467 return;
8468
8469 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8470 }
8471
8472 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8473 {
8474 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8475 }
8476
8477 static inline u32 kvm_async_pf_next_probe(u32 key)
8478 {
8479 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8480 }
8481
8482 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8483 {
8484 u32 key = kvm_async_pf_hash_fn(gfn);
8485
8486 while (vcpu->arch.apf.gfns[key] != ~0)
8487 key = kvm_async_pf_next_probe(key);
8488
8489 vcpu->arch.apf.gfns[key] = gfn;
8490 }
8491
8492 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8493 {
8494 int i;
8495 u32 key = kvm_async_pf_hash_fn(gfn);
8496
8497 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8498 (vcpu->arch.apf.gfns[key] != gfn &&
8499 vcpu->arch.apf.gfns[key] != ~0); i++)
8500 key = kvm_async_pf_next_probe(key);
8501
8502 return key;
8503 }
8504
8505 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8506 {
8507 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8508 }
8509
8510 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8511 {
8512 u32 i, j, k;
8513
8514 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8515 while (true) {
8516 vcpu->arch.apf.gfns[i] = ~0;
8517 do {
8518 j = kvm_async_pf_next_probe(j);
8519 if (vcpu->arch.apf.gfns[j] == ~0)
8520 return;
8521 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8522 /*
8523 * k lies cyclically in ]i,j]
8524 * | i.k.j |
8525 * |....j i.k.| or |.k..j i...|
8526 */
8527 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8528 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8529 i = j;
8530 }
8531 }
8532
8533 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8534 {
8535 return kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.apf.data, &val,
8536 sizeof(val));
8537 }
8538
8539 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8540 struct kvm_async_pf *work)
8541 {
8542 struct x86_exception fault;
8543
8544 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8545 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8546
8547 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8548 (vcpu->arch.apf.send_user_only &&
8549 kvm_x86_ops->get_cpl(vcpu) == 0))
8550 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8551 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8552 fault.vector = PF_VECTOR;
8553 fault.error_code_valid = true;
8554 fault.error_code = 0;
8555 fault.nested_page_fault = false;
8556 fault.address = work->arch.token;
8557 kvm_inject_page_fault(vcpu, &fault);
8558 }
8559 }
8560
8561 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8562 struct kvm_async_pf *work)
8563 {
8564 struct x86_exception fault;
8565
8566 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8567 if (work->wakeup_all)
8568 work->arch.token = ~0; /* broadcast wakeup */
8569 else
8570 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8571
8572 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8573 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8574 fault.vector = PF_VECTOR;
8575 fault.error_code_valid = true;
8576 fault.error_code = 0;
8577 fault.nested_page_fault = false;
8578 fault.address = work->arch.token;
8579 kvm_inject_page_fault(vcpu, &fault);
8580 }
8581 vcpu->arch.apf.halted = false;
8582 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8583 }
8584
8585 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8586 {
8587 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8588 return true;
8589 else
8590 return !kvm_event_needs_reinjection(vcpu) &&
8591 kvm_x86_ops->interrupt_allowed(vcpu);
8592 }
8593
8594 void kvm_arch_start_assignment(struct kvm *kvm)
8595 {
8596 atomic_inc(&kvm->arch.assigned_device_count);
8597 }
8598 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8599
8600 void kvm_arch_end_assignment(struct kvm *kvm)
8601 {
8602 atomic_dec(&kvm->arch.assigned_device_count);
8603 }
8604 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8605
8606 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8607 {
8608 return atomic_read(&kvm->arch.assigned_device_count);
8609 }
8610 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8611
8612 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8613 {
8614 atomic_inc(&kvm->arch.noncoherent_dma_count);
8615 }
8616 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8617
8618 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8619 {
8620 atomic_dec(&kvm->arch.noncoherent_dma_count);
8621 }
8622 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8623
8624 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8625 {
8626 return atomic_read(&kvm->arch.noncoherent_dma_count);
8627 }
8628 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8629
8630 bool kvm_arch_has_irq_bypass(void)
8631 {
8632 return kvm_x86_ops->update_pi_irte != NULL;
8633 }
8634
8635 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8636 struct irq_bypass_producer *prod)
8637 {
8638 struct kvm_kernel_irqfd *irqfd =
8639 container_of(cons, struct kvm_kernel_irqfd, consumer);
8640
8641 irqfd->producer = prod;
8642
8643 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8644 prod->irq, irqfd->gsi, 1);
8645 }
8646
8647 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8648 struct irq_bypass_producer *prod)
8649 {
8650 int ret;
8651 struct kvm_kernel_irqfd *irqfd =
8652 container_of(cons, struct kvm_kernel_irqfd, consumer);
8653
8654 WARN_ON(irqfd->producer != prod);
8655 irqfd->producer = NULL;
8656
8657 /*
8658 * When producer of consumer is unregistered, we change back to
8659 * remapped mode, so we can re-use the current implementation
8660 * when the irq is masked/disabled or the consumer side (KVM
8661 * int this case doesn't want to receive the interrupts.
8662 */
8663 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8664 if (ret)
8665 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8666 " fails: %d\n", irqfd->consumer.token, ret);
8667 }
8668
8669 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8670 uint32_t guest_irq, bool set)
8671 {
8672 if (!kvm_x86_ops->update_pi_irte)
8673 return -EINVAL;
8674
8675 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8676 }
8677
8678 bool kvm_vector_hashing_enabled(void)
8679 {
8680 return vector_hashing;
8681 }
8682 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8683
8684 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8685 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8686 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8687 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8688 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8689 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8690 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8691 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8692 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8693 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8694 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8695 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8696 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8697 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8698 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8699 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8700 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
8701 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8702 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);