Merge 4.4.100 into android-4.4
[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / scsi / ufs / ufshcd.c
1 /*
2 * Universal Flash Storage Host controller driver Core
3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
5 * Copyright (C) 2011-2013 Samsung India Software Operations
6 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
7 *
8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
38 */
39
40 #include <linux/async.h>
41 #include <linux/devfreq.h>
42 #include <linux/blkdev.h>
43
44 #include "ufshcd.h"
45 #include "unipro.h"
46
47 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
48 UTP_TASK_REQ_COMPL |\
49 UFSHCD_ERROR_MASK)
50 /* UIC command timeout, unit: ms */
51 #define UIC_CMD_TIMEOUT 500
52
53 /* NOP OUT retries waiting for NOP IN response */
54 #define NOP_OUT_RETRIES 10
55 /* Timeout after 30 msecs if NOP OUT hangs without response */
56 #define NOP_OUT_TIMEOUT 30 /* msecs */
57
58 /* Query request retries */
59 #define QUERY_REQ_RETRIES 10
60 /* Query request timeout */
61 #define QUERY_REQ_TIMEOUT 30 /* msec */
62
63 /* Task management command timeout */
64 #define TM_CMD_TIMEOUT 100 /* msecs */
65
66 /* maximum number of link-startup retries */
67 #define DME_LINKSTARTUP_RETRIES 3
68
69 /* maximum number of reset retries before giving up */
70 #define MAX_HOST_RESET_RETRIES 5
71
72 /* Expose the flag value from utp_upiu_query.value */
73 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
74
75 /* Interrupt aggregation default timeout, unit: 40us */
76 #define INT_AGGR_DEF_TO 0x02
77
78 #define ufshcd_toggle_vreg(_dev, _vreg, _on) \
79 ({ \
80 int _ret; \
81 if (_on) \
82 _ret = ufshcd_enable_vreg(_dev, _vreg); \
83 else \
84 _ret = ufshcd_disable_vreg(_dev, _vreg); \
85 _ret; \
86 })
87
88 static u32 ufs_query_desc_max_size[] = {
89 QUERY_DESC_DEVICE_MAX_SIZE,
90 QUERY_DESC_CONFIGURAION_MAX_SIZE,
91 QUERY_DESC_UNIT_MAX_SIZE,
92 QUERY_DESC_RFU_MAX_SIZE,
93 QUERY_DESC_INTERCONNECT_MAX_SIZE,
94 QUERY_DESC_STRING_MAX_SIZE,
95 QUERY_DESC_RFU_MAX_SIZE,
96 QUERY_DESC_GEOMETRY_MAZ_SIZE,
97 QUERY_DESC_POWER_MAX_SIZE,
98 QUERY_DESC_RFU_MAX_SIZE,
99 };
100
101 enum {
102 UFSHCD_MAX_CHANNEL = 0,
103 UFSHCD_MAX_ID = 1,
104 UFSHCD_CMD_PER_LUN = 32,
105 UFSHCD_CAN_QUEUE = 32,
106 };
107
108 /* UFSHCD states */
109 enum {
110 UFSHCD_STATE_RESET,
111 UFSHCD_STATE_ERROR,
112 UFSHCD_STATE_OPERATIONAL,
113 };
114
115 /* UFSHCD error handling flags */
116 enum {
117 UFSHCD_EH_IN_PROGRESS = (1 << 0),
118 };
119
120 /* UFSHCD UIC layer error flags */
121 enum {
122 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
123 UFSHCD_UIC_NL_ERROR = (1 << 1), /* Network layer error */
124 UFSHCD_UIC_TL_ERROR = (1 << 2), /* Transport Layer error */
125 UFSHCD_UIC_DME_ERROR = (1 << 3), /* DME error */
126 };
127
128 /* Interrupt configuration options */
129 enum {
130 UFSHCD_INT_DISABLE,
131 UFSHCD_INT_ENABLE,
132 UFSHCD_INT_CLEAR,
133 };
134
135 #define ufshcd_set_eh_in_progress(h) \
136 (h->eh_flags |= UFSHCD_EH_IN_PROGRESS)
137 #define ufshcd_eh_in_progress(h) \
138 (h->eh_flags & UFSHCD_EH_IN_PROGRESS)
139 #define ufshcd_clear_eh_in_progress(h) \
140 (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
141
142 #define ufshcd_set_ufs_dev_active(h) \
143 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
144 #define ufshcd_set_ufs_dev_sleep(h) \
145 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
146 #define ufshcd_set_ufs_dev_poweroff(h) \
147 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
148 #define ufshcd_is_ufs_dev_active(h) \
149 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
150 #define ufshcd_is_ufs_dev_sleep(h) \
151 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
152 #define ufshcd_is_ufs_dev_poweroff(h) \
153 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
154
155 static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
156 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
157 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
158 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
159 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
160 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
161 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
162 };
163
164 static inline enum ufs_dev_pwr_mode
165 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
166 {
167 return ufs_pm_lvl_states[lvl].dev_state;
168 }
169
170 static inline enum uic_link_state
171 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
172 {
173 return ufs_pm_lvl_states[lvl].link_state;
174 }
175
176 static void ufshcd_tmc_handler(struct ufs_hba *hba);
177 static void ufshcd_async_scan(void *data, async_cookie_t cookie);
178 static int ufshcd_reset_and_restore(struct ufs_hba *hba);
179 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
180 static void ufshcd_hba_exit(struct ufs_hba *hba);
181 static int ufshcd_probe_hba(struct ufs_hba *hba);
182 static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
183 bool skip_ref_clk);
184 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
185 static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
186 static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
187 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
188 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
189 static irqreturn_t ufshcd_intr(int irq, void *__hba);
190 static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
191 struct ufs_pa_layer_attr *desired_pwr_mode);
192 static int ufshcd_change_power_mode(struct ufs_hba *hba,
193 struct ufs_pa_layer_attr *pwr_mode);
194
195 static inline int ufshcd_enable_irq(struct ufs_hba *hba)
196 {
197 int ret = 0;
198
199 if (!hba->is_irq_enabled) {
200 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
201 hba);
202 if (ret)
203 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
204 __func__, ret);
205 hba->is_irq_enabled = true;
206 }
207
208 return ret;
209 }
210
211 static inline void ufshcd_disable_irq(struct ufs_hba *hba)
212 {
213 if (hba->is_irq_enabled) {
214 free_irq(hba->irq, hba);
215 hba->is_irq_enabled = false;
216 }
217 }
218
219 /*
220 * ufshcd_wait_for_register - wait for register value to change
221 * @hba - per-adapter interface
222 * @reg - mmio register offset
223 * @mask - mask to apply to read register value
224 * @val - wait condition
225 * @interval_us - polling interval in microsecs
226 * @timeout_ms - timeout in millisecs
227 *
228 * Returns -ETIMEDOUT on error, zero on success
229 */
230 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
231 u32 val, unsigned long interval_us, unsigned long timeout_ms)
232 {
233 int err = 0;
234 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
235
236 /* ignore bits that we don't intend to wait on */
237 val = val & mask;
238
239 while ((ufshcd_readl(hba, reg) & mask) != val) {
240 /* wakeup within 50us of expiry */
241 usleep_range(interval_us, interval_us + 50);
242
243 if (time_after(jiffies, timeout)) {
244 if ((ufshcd_readl(hba, reg) & mask) != val)
245 err = -ETIMEDOUT;
246 break;
247 }
248 }
249
250 return err;
251 }
252
253 /**
254 * ufshcd_get_intr_mask - Get the interrupt bit mask
255 * @hba - Pointer to adapter instance
256 *
257 * Returns interrupt bit mask per version
258 */
259 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
260 {
261 if (hba->ufs_version == UFSHCI_VERSION_10)
262 return INTERRUPT_MASK_ALL_VER_10;
263 else
264 return INTERRUPT_MASK_ALL_VER_11;
265 }
266
267 /**
268 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
269 * @hba - Pointer to adapter instance
270 *
271 * Returns UFSHCI version supported by the controller
272 */
273 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
274 {
275 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
276 return ufshcd_vops_get_ufs_hci_version(hba);
277
278 return ufshcd_readl(hba, REG_UFS_VERSION);
279 }
280
281 /**
282 * ufshcd_is_device_present - Check if any device connected to
283 * the host controller
284 * @hba: pointer to adapter instance
285 *
286 * Returns 1 if device present, 0 if no device detected
287 */
288 static inline int ufshcd_is_device_present(struct ufs_hba *hba)
289 {
290 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
291 DEVICE_PRESENT) ? 1 : 0;
292 }
293
294 /**
295 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
296 * @lrb: pointer to local command reference block
297 *
298 * This function is used to get the OCS field from UTRD
299 * Returns the OCS field in the UTRD
300 */
301 static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
302 {
303 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
304 }
305
306 /**
307 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
308 * @task_req_descp: pointer to utp_task_req_desc structure
309 *
310 * This function is used to get the OCS field from UTMRD
311 * Returns the OCS field in the UTMRD
312 */
313 static inline int
314 ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
315 {
316 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
317 }
318
319 /**
320 * ufshcd_get_tm_free_slot - get a free slot for task management request
321 * @hba: per adapter instance
322 * @free_slot: pointer to variable with available slot value
323 *
324 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
325 * Returns 0 if free slot is not available, else return 1 with tag value
326 * in @free_slot.
327 */
328 static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
329 {
330 int tag;
331 bool ret = false;
332
333 if (!free_slot)
334 goto out;
335
336 do {
337 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
338 if (tag >= hba->nutmrs)
339 goto out;
340 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
341
342 *free_slot = tag;
343 ret = true;
344 out:
345 return ret;
346 }
347
348 static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
349 {
350 clear_bit_unlock(slot, &hba->tm_slots_in_use);
351 }
352
353 /**
354 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
355 * @hba: per adapter instance
356 * @pos: position of the bit to be cleared
357 */
358 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
359 {
360 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
361 }
362
363 /**
364 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
365 * @reg: Register value of host controller status
366 *
367 * Returns integer, 0 on Success and positive value if failed
368 */
369 static inline int ufshcd_get_lists_status(u32 reg)
370 {
371 /*
372 * The mask 0xFF is for the following HCS register bits
373 * Bit Description
374 * 0 Device Present
375 * 1 UTRLRDY
376 * 2 UTMRLRDY
377 * 3 UCRDY
378 * 4 HEI
379 * 5 DEI
380 * 6-7 reserved
381 */
382 return (((reg) & (0xFF)) >> 1) ^ (0x07);
383 }
384
385 /**
386 * ufshcd_get_uic_cmd_result - Get the UIC command result
387 * @hba: Pointer to adapter instance
388 *
389 * This function gets the result of UIC command completion
390 * Returns 0 on success, non zero value on error
391 */
392 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
393 {
394 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
395 MASK_UIC_COMMAND_RESULT;
396 }
397
398 /**
399 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
400 * @hba: Pointer to adapter instance
401 *
402 * This function gets UIC command argument3
403 * Returns 0 on success, non zero value on error
404 */
405 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
406 {
407 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
408 }
409
410 /**
411 * ufshcd_get_req_rsp - returns the TR response transaction type
412 * @ucd_rsp_ptr: pointer to response UPIU
413 */
414 static inline int
415 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
416 {
417 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
418 }
419
420 /**
421 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
422 * @ucd_rsp_ptr: pointer to response UPIU
423 *
424 * This function gets the response status and scsi_status from response UPIU
425 * Returns the response result code.
426 */
427 static inline int
428 ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
429 {
430 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
431 }
432
433 /*
434 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
435 * from response UPIU
436 * @ucd_rsp_ptr: pointer to response UPIU
437 *
438 * Return the data segment length.
439 */
440 static inline unsigned int
441 ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
442 {
443 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
444 MASK_RSP_UPIU_DATA_SEG_LEN;
445 }
446
447 /**
448 * ufshcd_is_exception_event - Check if the device raised an exception event
449 * @ucd_rsp_ptr: pointer to response UPIU
450 *
451 * The function checks if the device raised an exception event indicated in
452 * the Device Information field of response UPIU.
453 *
454 * Returns true if exception is raised, false otherwise.
455 */
456 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
457 {
458 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
459 MASK_RSP_EXCEPTION_EVENT ? true : false;
460 }
461
462 /**
463 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
464 * @hba: per adapter instance
465 */
466 static inline void
467 ufshcd_reset_intr_aggr(struct ufs_hba *hba)
468 {
469 ufshcd_writel(hba, INT_AGGR_ENABLE |
470 INT_AGGR_COUNTER_AND_TIMER_RESET,
471 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
472 }
473
474 /**
475 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
476 * @hba: per adapter instance
477 * @cnt: Interrupt aggregation counter threshold
478 * @tmout: Interrupt aggregation timeout value
479 */
480 static inline void
481 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
482 {
483 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
484 INT_AGGR_COUNTER_THLD_VAL(cnt) |
485 INT_AGGR_TIMEOUT_VAL(tmout),
486 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
487 }
488
489 /**
490 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
491 * @hba: per adapter instance
492 */
493 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
494 {
495 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
496 }
497
498 /**
499 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
500 * When run-stop registers are set to 1, it indicates the
501 * host controller that it can process the requests
502 * @hba: per adapter instance
503 */
504 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
505 {
506 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
507 REG_UTP_TASK_REQ_LIST_RUN_STOP);
508 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
509 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
510 }
511
512 /**
513 * ufshcd_hba_start - Start controller initialization sequence
514 * @hba: per adapter instance
515 */
516 static inline void ufshcd_hba_start(struct ufs_hba *hba)
517 {
518 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
519 }
520
521 /**
522 * ufshcd_is_hba_active - Get controller state
523 * @hba: per adapter instance
524 *
525 * Returns zero if controller is active, 1 otherwise
526 */
527 static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
528 {
529 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
530 }
531
532 static void ufshcd_ungate_work(struct work_struct *work)
533 {
534 int ret;
535 unsigned long flags;
536 struct ufs_hba *hba = container_of(work, struct ufs_hba,
537 clk_gating.ungate_work);
538
539 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
540
541 spin_lock_irqsave(hba->host->host_lock, flags);
542 if (hba->clk_gating.state == CLKS_ON) {
543 spin_unlock_irqrestore(hba->host->host_lock, flags);
544 goto unblock_reqs;
545 }
546
547 spin_unlock_irqrestore(hba->host->host_lock, flags);
548 ufshcd_setup_clocks(hba, true);
549
550 /* Exit from hibern8 */
551 if (ufshcd_can_hibern8_during_gating(hba)) {
552 /* Prevent gating in this path */
553 hba->clk_gating.is_suspended = true;
554 if (ufshcd_is_link_hibern8(hba)) {
555 ret = ufshcd_uic_hibern8_exit(hba);
556 if (ret)
557 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
558 __func__, ret);
559 else
560 ufshcd_set_link_active(hba);
561 }
562 hba->clk_gating.is_suspended = false;
563 }
564 unblock_reqs:
565 if (ufshcd_is_clkscaling_enabled(hba))
566 devfreq_resume_device(hba->devfreq);
567 scsi_unblock_requests(hba->host);
568 }
569
570 /**
571 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
572 * Also, exit from hibern8 mode and set the link as active.
573 * @hba: per adapter instance
574 * @async: This indicates whether caller should ungate clocks asynchronously.
575 */
576 int ufshcd_hold(struct ufs_hba *hba, bool async)
577 {
578 int rc = 0;
579 unsigned long flags;
580
581 if (!ufshcd_is_clkgating_allowed(hba))
582 goto out;
583 spin_lock_irqsave(hba->host->host_lock, flags);
584 hba->clk_gating.active_reqs++;
585
586 start:
587 switch (hba->clk_gating.state) {
588 case CLKS_ON:
589 break;
590 case REQ_CLKS_OFF:
591 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
592 hba->clk_gating.state = CLKS_ON;
593 break;
594 }
595 /*
596 * If we here, it means gating work is either done or
597 * currently running. Hence, fall through to cancel gating
598 * work and to enable clocks.
599 */
600 case CLKS_OFF:
601 scsi_block_requests(hba->host);
602 hba->clk_gating.state = REQ_CLKS_ON;
603 schedule_work(&hba->clk_gating.ungate_work);
604 /*
605 * fall through to check if we should wait for this
606 * work to be done or not.
607 */
608 case REQ_CLKS_ON:
609 if (async) {
610 rc = -EAGAIN;
611 hba->clk_gating.active_reqs--;
612 break;
613 }
614
615 spin_unlock_irqrestore(hba->host->host_lock, flags);
616 flush_work(&hba->clk_gating.ungate_work);
617 /* Make sure state is CLKS_ON before returning */
618 spin_lock_irqsave(hba->host->host_lock, flags);
619 goto start;
620 default:
621 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
622 __func__, hba->clk_gating.state);
623 break;
624 }
625 spin_unlock_irqrestore(hba->host->host_lock, flags);
626 out:
627 return rc;
628 }
629 EXPORT_SYMBOL_GPL(ufshcd_hold);
630
631 static void ufshcd_gate_work(struct work_struct *work)
632 {
633 struct ufs_hba *hba = container_of(work, struct ufs_hba,
634 clk_gating.gate_work.work);
635 unsigned long flags;
636
637 spin_lock_irqsave(hba->host->host_lock, flags);
638 if (hba->clk_gating.is_suspended) {
639 hba->clk_gating.state = CLKS_ON;
640 goto rel_lock;
641 }
642
643 if (hba->clk_gating.active_reqs
644 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
645 || hba->lrb_in_use || hba->outstanding_tasks
646 || hba->active_uic_cmd || hba->uic_async_done)
647 goto rel_lock;
648
649 spin_unlock_irqrestore(hba->host->host_lock, flags);
650
651 /* put the link into hibern8 mode before turning off clocks */
652 if (ufshcd_can_hibern8_during_gating(hba)) {
653 if (ufshcd_uic_hibern8_enter(hba)) {
654 hba->clk_gating.state = CLKS_ON;
655 goto out;
656 }
657 ufshcd_set_link_hibern8(hba);
658 }
659
660 if (ufshcd_is_clkscaling_enabled(hba)) {
661 devfreq_suspend_device(hba->devfreq);
662 hba->clk_scaling.window_start_t = 0;
663 }
664
665 if (!ufshcd_is_link_active(hba))
666 ufshcd_setup_clocks(hba, false);
667 else
668 /* If link is active, device ref_clk can't be switched off */
669 __ufshcd_setup_clocks(hba, false, true);
670
671 /*
672 * In case you are here to cancel this work the gating state
673 * would be marked as REQ_CLKS_ON. In this case keep the state
674 * as REQ_CLKS_ON which would anyway imply that clocks are off
675 * and a request to turn them on is pending. By doing this way,
676 * we keep the state machine in tact and this would ultimately
677 * prevent from doing cancel work multiple times when there are
678 * new requests arriving before the current cancel work is done.
679 */
680 spin_lock_irqsave(hba->host->host_lock, flags);
681 if (hba->clk_gating.state == REQ_CLKS_OFF)
682 hba->clk_gating.state = CLKS_OFF;
683
684 rel_lock:
685 spin_unlock_irqrestore(hba->host->host_lock, flags);
686 out:
687 return;
688 }
689
690 /* host lock must be held before calling this variant */
691 static void __ufshcd_release(struct ufs_hba *hba)
692 {
693 if (!ufshcd_is_clkgating_allowed(hba))
694 return;
695
696 hba->clk_gating.active_reqs--;
697
698 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
699 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
700 || hba->lrb_in_use || hba->outstanding_tasks
701 || hba->active_uic_cmd || hba->uic_async_done)
702 return;
703
704 hba->clk_gating.state = REQ_CLKS_OFF;
705 schedule_delayed_work(&hba->clk_gating.gate_work,
706 msecs_to_jiffies(hba->clk_gating.delay_ms));
707 }
708
709 void ufshcd_release(struct ufs_hba *hba)
710 {
711 unsigned long flags;
712
713 spin_lock_irqsave(hba->host->host_lock, flags);
714 __ufshcd_release(hba);
715 spin_unlock_irqrestore(hba->host->host_lock, flags);
716 }
717 EXPORT_SYMBOL_GPL(ufshcd_release);
718
719 static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
720 struct device_attribute *attr, char *buf)
721 {
722 struct ufs_hba *hba = dev_get_drvdata(dev);
723
724 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
725 }
726
727 static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
728 struct device_attribute *attr, const char *buf, size_t count)
729 {
730 struct ufs_hba *hba = dev_get_drvdata(dev);
731 unsigned long flags, value;
732
733 if (kstrtoul(buf, 0, &value))
734 return -EINVAL;
735
736 spin_lock_irqsave(hba->host->host_lock, flags);
737 hba->clk_gating.delay_ms = value;
738 spin_unlock_irqrestore(hba->host->host_lock, flags);
739 return count;
740 }
741
742 static void ufshcd_init_clk_gating(struct ufs_hba *hba)
743 {
744 if (!ufshcd_is_clkgating_allowed(hba))
745 return;
746
747 hba->clk_gating.delay_ms = 150;
748 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
749 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
750
751 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
752 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
753 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
754 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
755 hba->clk_gating.delay_attr.attr.mode = S_IRUGO | S_IWUSR;
756 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
757 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
758 }
759
760 static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
761 {
762 if (!ufshcd_is_clkgating_allowed(hba))
763 return;
764 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
765 cancel_work_sync(&hba->clk_gating.ungate_work);
766 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
767 }
768
769 /* Must be called with host lock acquired */
770 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
771 {
772 if (!ufshcd_is_clkscaling_enabled(hba))
773 return;
774
775 if (!hba->clk_scaling.is_busy_started) {
776 hba->clk_scaling.busy_start_t = ktime_get();
777 hba->clk_scaling.is_busy_started = true;
778 }
779 }
780
781 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
782 {
783 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
784
785 if (!ufshcd_is_clkscaling_enabled(hba))
786 return;
787
788 if (!hba->outstanding_reqs && scaling->is_busy_started) {
789 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
790 scaling->busy_start_t));
791 scaling->busy_start_t = ktime_set(0, 0);
792 scaling->is_busy_started = false;
793 }
794 }
795 /**
796 * ufshcd_send_command - Send SCSI or device management commands
797 * @hba: per adapter instance
798 * @task_tag: Task tag of the command
799 */
800 static inline
801 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
802 {
803 ufshcd_clk_scaling_start_busy(hba);
804 __set_bit(task_tag, &hba->outstanding_reqs);
805 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
806 }
807
808 /**
809 * ufshcd_copy_sense_data - Copy sense data in case of check condition
810 * @lrb - pointer to local reference block
811 */
812 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
813 {
814 int len;
815 if (lrbp->sense_buffer &&
816 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
817 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
818 memcpy(lrbp->sense_buffer,
819 lrbp->ucd_rsp_ptr->sr.sense_data,
820 min_t(int, len, SCSI_SENSE_BUFFERSIZE));
821 }
822 }
823
824 /**
825 * ufshcd_copy_query_response() - Copy the Query Response and the data
826 * descriptor
827 * @hba: per adapter instance
828 * @lrb - pointer to local reference block
829 */
830 static
831 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
832 {
833 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
834
835 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
836
837 /* Get the descriptor */
838 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
839 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
840 GENERAL_UPIU_REQUEST_SIZE;
841 u16 resp_len;
842 u16 buf_len;
843
844 /* data segment length */
845 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
846 MASK_QUERY_DATA_SEG_LEN;
847 buf_len = be16_to_cpu(
848 hba->dev_cmd.query.request.upiu_req.length);
849 if (likely(buf_len >= resp_len)) {
850 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
851 } else {
852 dev_warn(hba->dev,
853 "%s: Response size is bigger than buffer",
854 __func__);
855 return -EINVAL;
856 }
857 }
858
859 return 0;
860 }
861
862 /**
863 * ufshcd_hba_capabilities - Read controller capabilities
864 * @hba: per adapter instance
865 */
866 static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
867 {
868 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
869
870 /* nutrs and nutmrs are 0 based values */
871 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
872 hba->nutmrs =
873 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
874 }
875
876 /**
877 * ufshcd_ready_for_uic_cmd - Check if controller is ready
878 * to accept UIC commands
879 * @hba: per adapter instance
880 * Return true on success, else false
881 */
882 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
883 {
884 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
885 return true;
886 else
887 return false;
888 }
889
890 /**
891 * ufshcd_get_upmcrs - Get the power mode change request status
892 * @hba: Pointer to adapter instance
893 *
894 * This function gets the UPMCRS field of HCS register
895 * Returns value of UPMCRS field
896 */
897 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
898 {
899 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
900 }
901
902 /**
903 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
904 * @hba: per adapter instance
905 * @uic_cmd: UIC command
906 *
907 * Mutex must be held.
908 */
909 static inline void
910 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
911 {
912 WARN_ON(hba->active_uic_cmd);
913
914 hba->active_uic_cmd = uic_cmd;
915
916 /* Write Args */
917 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
918 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
919 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
920
921 /* Write UIC Cmd */
922 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
923 REG_UIC_COMMAND);
924 }
925
926 /**
927 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
928 * @hba: per adapter instance
929 * @uic_command: UIC command
930 *
931 * Must be called with mutex held.
932 * Returns 0 only if success.
933 */
934 static int
935 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
936 {
937 int ret;
938 unsigned long flags;
939
940 if (wait_for_completion_timeout(&uic_cmd->done,
941 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
942 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
943 else
944 ret = -ETIMEDOUT;
945
946 spin_lock_irqsave(hba->host->host_lock, flags);
947 hba->active_uic_cmd = NULL;
948 spin_unlock_irqrestore(hba->host->host_lock, flags);
949
950 return ret;
951 }
952
953 /**
954 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
955 * @hba: per adapter instance
956 * @uic_cmd: UIC command
957 *
958 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
959 * with mutex held and host_lock locked.
960 * Returns 0 only if success.
961 */
962 static int
963 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
964 {
965 if (!ufshcd_ready_for_uic_cmd(hba)) {
966 dev_err(hba->dev,
967 "Controller not ready to accept UIC commands\n");
968 return -EIO;
969 }
970
971 init_completion(&uic_cmd->done);
972
973 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
974
975 return 0;
976 }
977
978 /**
979 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
980 * @hba: per adapter instance
981 * @uic_cmd: UIC command
982 *
983 * Returns 0 only if success.
984 */
985 static int
986 ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
987 {
988 int ret;
989 unsigned long flags;
990
991 ufshcd_hold(hba, false);
992 mutex_lock(&hba->uic_cmd_mutex);
993 ufshcd_add_delay_before_dme_cmd(hba);
994
995 spin_lock_irqsave(hba->host->host_lock, flags);
996 ret = __ufshcd_send_uic_cmd(hba, uic_cmd);
997 spin_unlock_irqrestore(hba->host->host_lock, flags);
998 if (!ret)
999 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
1000
1001 mutex_unlock(&hba->uic_cmd_mutex);
1002
1003 ufshcd_release(hba);
1004 return ret;
1005 }
1006
1007 /**
1008 * ufshcd_map_sg - Map scatter-gather list to prdt
1009 * @lrbp - pointer to local reference block
1010 *
1011 * Returns 0 in case of success, non-zero value in case of failure
1012 */
1013 static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
1014 {
1015 struct ufshcd_sg_entry *prd_table;
1016 struct scatterlist *sg;
1017 struct scsi_cmnd *cmd;
1018 int sg_segments;
1019 int i;
1020
1021 cmd = lrbp->cmd;
1022 sg_segments = scsi_dma_map(cmd);
1023 if (sg_segments < 0)
1024 return sg_segments;
1025
1026 if (sg_segments) {
1027 lrbp->utr_descriptor_ptr->prd_table_length =
1028 cpu_to_le16((u16) (sg_segments));
1029
1030 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
1031
1032 scsi_for_each_sg(cmd, sg, sg_segments, i) {
1033 prd_table[i].size =
1034 cpu_to_le32(((u32) sg_dma_len(sg))-1);
1035 prd_table[i].base_addr =
1036 cpu_to_le32(lower_32_bits(sg->dma_address));
1037 prd_table[i].upper_addr =
1038 cpu_to_le32(upper_32_bits(sg->dma_address));
1039 }
1040 } else {
1041 lrbp->utr_descriptor_ptr->prd_table_length = 0;
1042 }
1043
1044 return 0;
1045 }
1046
1047 /**
1048 * ufshcd_enable_intr - enable interrupts
1049 * @hba: per adapter instance
1050 * @intrs: interrupt bits
1051 */
1052 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
1053 {
1054 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1055
1056 if (hba->ufs_version == UFSHCI_VERSION_10) {
1057 u32 rw;
1058 rw = set & INTERRUPT_MASK_RW_VER_10;
1059 set = rw | ((set ^ intrs) & intrs);
1060 } else {
1061 set |= intrs;
1062 }
1063
1064 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
1065 }
1066
1067 /**
1068 * ufshcd_disable_intr - disable interrupts
1069 * @hba: per adapter instance
1070 * @intrs: interrupt bits
1071 */
1072 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
1073 {
1074 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1075
1076 if (hba->ufs_version == UFSHCI_VERSION_10) {
1077 u32 rw;
1078 rw = (set & INTERRUPT_MASK_RW_VER_10) &
1079 ~(intrs & INTERRUPT_MASK_RW_VER_10);
1080 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
1081
1082 } else {
1083 set &= ~intrs;
1084 }
1085
1086 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
1087 }
1088
1089 /**
1090 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
1091 * descriptor according to request
1092 * @lrbp: pointer to local reference block
1093 * @upiu_flags: flags required in the header
1094 * @cmd_dir: requests data direction
1095 */
1096 static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
1097 u32 *upiu_flags, enum dma_data_direction cmd_dir)
1098 {
1099 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
1100 u32 data_direction;
1101 u32 dword_0;
1102
1103 if (cmd_dir == DMA_FROM_DEVICE) {
1104 data_direction = UTP_DEVICE_TO_HOST;
1105 *upiu_flags = UPIU_CMD_FLAGS_READ;
1106 } else if (cmd_dir == DMA_TO_DEVICE) {
1107 data_direction = UTP_HOST_TO_DEVICE;
1108 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
1109 } else {
1110 data_direction = UTP_NO_DATA_TRANSFER;
1111 *upiu_flags = UPIU_CMD_FLAGS_NONE;
1112 }
1113
1114 dword_0 = data_direction | (lrbp->command_type
1115 << UPIU_COMMAND_TYPE_OFFSET);
1116 if (lrbp->intr_cmd)
1117 dword_0 |= UTP_REQ_DESC_INT_CMD;
1118
1119 /* Transfer request descriptor header fields */
1120 req_desc->header.dword_0 = cpu_to_le32(dword_0);
1121
1122 /*
1123 * assigning invalid value for command status. Controller
1124 * updates OCS on command completion, with the command
1125 * status
1126 */
1127 req_desc->header.dword_2 =
1128 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
1129 }
1130
1131 /**
1132 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
1133 * for scsi commands
1134 * @lrbp - local reference block pointer
1135 * @upiu_flags - flags
1136 */
1137 static
1138 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
1139 {
1140 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1141
1142 /* command descriptor fields */
1143 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1144 UPIU_TRANSACTION_COMMAND, upiu_flags,
1145 lrbp->lun, lrbp->task_tag);
1146 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1147 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
1148
1149 /* Total EHS length and Data segment length will be zero */
1150 ucd_req_ptr->header.dword_2 = 0;
1151
1152 ucd_req_ptr->sc.exp_data_transfer_len =
1153 cpu_to_be32(lrbp->cmd->sdb.length);
1154
1155 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd,
1156 (min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE)));
1157 }
1158
1159 /**
1160 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
1161 * for query requsts
1162 * @hba: UFS hba
1163 * @lrbp: local reference block pointer
1164 * @upiu_flags: flags
1165 */
1166 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
1167 struct ufshcd_lrb *lrbp, u32 upiu_flags)
1168 {
1169 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1170 struct ufs_query *query = &hba->dev_cmd.query;
1171 u16 len = be16_to_cpu(query->request.upiu_req.length);
1172 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
1173
1174 /* Query request header */
1175 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1176 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
1177 lrbp->lun, lrbp->task_tag);
1178 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1179 0, query->request.query_func, 0, 0);
1180
1181 /* Data segment length */
1182 ucd_req_ptr->header.dword_2 = UPIU_HEADER_DWORD(
1183 0, 0, len >> 8, (u8)len);
1184
1185 /* Copy the Query Request buffer as is */
1186 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
1187 QUERY_OSF_SIZE);
1188
1189 /* Copy the Descriptor */
1190 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
1191 memcpy(descp, query->descriptor, len);
1192
1193 }
1194
1195 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
1196 {
1197 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1198
1199 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
1200
1201 /* command descriptor fields */
1202 ucd_req_ptr->header.dword_0 =
1203 UPIU_HEADER_DWORD(
1204 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
1205 }
1206
1207 /**
1208 * ufshcd_compose_upiu - form UFS Protocol Information Unit(UPIU)
1209 * @hba - per adapter instance
1210 * @lrb - pointer to local reference block
1211 */
1212 static int ufshcd_compose_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1213 {
1214 u32 upiu_flags;
1215 int ret = 0;
1216
1217 switch (lrbp->command_type) {
1218 case UTP_CMD_TYPE_SCSI:
1219 if (likely(lrbp->cmd)) {
1220 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
1221 lrbp->cmd->sc_data_direction);
1222 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
1223 } else {
1224 ret = -EINVAL;
1225 }
1226 break;
1227 case UTP_CMD_TYPE_DEV_MANAGE:
1228 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
1229 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
1230 ufshcd_prepare_utp_query_req_upiu(
1231 hba, lrbp, upiu_flags);
1232 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
1233 ufshcd_prepare_utp_nop_upiu(lrbp);
1234 else
1235 ret = -EINVAL;
1236 break;
1237 case UTP_CMD_TYPE_UFS:
1238 /* For UFS native command implementation */
1239 ret = -ENOTSUPP;
1240 dev_err(hba->dev, "%s: UFS native command are not supported\n",
1241 __func__);
1242 break;
1243 default:
1244 ret = -ENOTSUPP;
1245 dev_err(hba->dev, "%s: unknown command type: 0x%x\n",
1246 __func__, lrbp->command_type);
1247 break;
1248 } /* end of switch */
1249
1250 return ret;
1251 }
1252
1253 /*
1254 * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
1255 * @scsi_lun: scsi LUN id
1256 *
1257 * Returns UPIU LUN id
1258 */
1259 static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
1260 {
1261 if (scsi_is_wlun(scsi_lun))
1262 return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
1263 | UFS_UPIU_WLUN_ID;
1264 else
1265 return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
1266 }
1267
1268 /**
1269 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
1270 * @scsi_lun: UPIU W-LUN id
1271 *
1272 * Returns SCSI W-LUN id
1273 */
1274 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
1275 {
1276 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
1277 }
1278
1279 /**
1280 * ufshcd_queuecommand - main entry point for SCSI requests
1281 * @cmd: command from SCSI Midlayer
1282 * @done: call back function
1283 *
1284 * Returns 0 for success, non-zero in case of failure
1285 */
1286 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
1287 {
1288 struct ufshcd_lrb *lrbp;
1289 struct ufs_hba *hba;
1290 unsigned long flags;
1291 int tag;
1292 int err = 0;
1293
1294 hba = shost_priv(host);
1295
1296 tag = cmd->request->tag;
1297
1298 spin_lock_irqsave(hba->host->host_lock, flags);
1299 switch (hba->ufshcd_state) {
1300 case UFSHCD_STATE_OPERATIONAL:
1301 break;
1302 case UFSHCD_STATE_RESET:
1303 err = SCSI_MLQUEUE_HOST_BUSY;
1304 goto out_unlock;
1305 case UFSHCD_STATE_ERROR:
1306 set_host_byte(cmd, DID_ERROR);
1307 cmd->scsi_done(cmd);
1308 goto out_unlock;
1309 default:
1310 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
1311 __func__, hba->ufshcd_state);
1312 set_host_byte(cmd, DID_BAD_TARGET);
1313 cmd->scsi_done(cmd);
1314 goto out_unlock;
1315 }
1316 spin_unlock_irqrestore(hba->host->host_lock, flags);
1317
1318 /* acquire the tag to make sure device cmds don't use it */
1319 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
1320 /*
1321 * Dev manage command in progress, requeue the command.
1322 * Requeuing the command helps in cases where the request *may*
1323 * find different tag instead of waiting for dev manage command
1324 * completion.
1325 */
1326 err = SCSI_MLQUEUE_HOST_BUSY;
1327 goto out;
1328 }
1329
1330 err = ufshcd_hold(hba, true);
1331 if (err) {
1332 err = SCSI_MLQUEUE_HOST_BUSY;
1333 clear_bit_unlock(tag, &hba->lrb_in_use);
1334 goto out;
1335 }
1336
1337 /* IO svc time latency histogram */
1338 if (hba != NULL && cmd->request != NULL) {
1339 if (hba->latency_hist_enabled &&
1340 (cmd->request->cmd_type == REQ_TYPE_FS)) {
1341 cmd->request->lat_hist_io_start = ktime_get();
1342 cmd->request->lat_hist_enabled = 1;
1343 } else
1344 cmd->request->lat_hist_enabled = 0;
1345 }
1346
1347 WARN_ON(hba->clk_gating.state != CLKS_ON);
1348
1349 lrbp = &hba->lrb[tag];
1350
1351 WARN_ON(lrbp->cmd);
1352 lrbp->cmd = cmd;
1353 lrbp->sense_bufflen = SCSI_SENSE_BUFFERSIZE;
1354 lrbp->sense_buffer = cmd->sense_buffer;
1355 lrbp->task_tag = tag;
1356 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
1357 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
1358 lrbp->command_type = UTP_CMD_TYPE_SCSI;
1359
1360 /* form UPIU before issuing the command */
1361 ufshcd_compose_upiu(hba, lrbp);
1362 err = ufshcd_map_sg(lrbp);
1363 if (err) {
1364 lrbp->cmd = NULL;
1365 clear_bit_unlock(tag, &hba->lrb_in_use);
1366 goto out;
1367 }
1368
1369 /* issue command to the controller */
1370 spin_lock_irqsave(hba->host->host_lock, flags);
1371 ufshcd_send_command(hba, tag);
1372 out_unlock:
1373 spin_unlock_irqrestore(hba->host->host_lock, flags);
1374 out:
1375 return err;
1376 }
1377
1378 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
1379 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
1380 {
1381 lrbp->cmd = NULL;
1382 lrbp->sense_bufflen = 0;
1383 lrbp->sense_buffer = NULL;
1384 lrbp->task_tag = tag;
1385 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
1386 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
1387 lrbp->intr_cmd = true; /* No interrupt aggregation */
1388 hba->dev_cmd.type = cmd_type;
1389
1390 return ufshcd_compose_upiu(hba, lrbp);
1391 }
1392
1393 static int
1394 ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
1395 {
1396 int err = 0;
1397 unsigned long flags;
1398 u32 mask = 1 << tag;
1399
1400 /* clear outstanding transaction before retry */
1401 spin_lock_irqsave(hba->host->host_lock, flags);
1402 ufshcd_utrl_clear(hba, tag);
1403 spin_unlock_irqrestore(hba->host->host_lock, flags);
1404
1405 /*
1406 * wait for for h/w to clear corresponding bit in door-bell.
1407 * max. wait is 1 sec.
1408 */
1409 err = ufshcd_wait_for_register(hba,
1410 REG_UTP_TRANSFER_REQ_DOOR_BELL,
1411 mask, ~mask, 1000, 1000);
1412
1413 return err;
1414 }
1415
1416 static int
1417 ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1418 {
1419 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1420
1421 /* Get the UPIU response */
1422 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
1423 UPIU_RSP_CODE_OFFSET;
1424 return query_res->response;
1425 }
1426
1427 /**
1428 * ufshcd_dev_cmd_completion() - handles device management command responses
1429 * @hba: per adapter instance
1430 * @lrbp: pointer to local reference block
1431 */
1432 static int
1433 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1434 {
1435 int resp;
1436 int err = 0;
1437
1438 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
1439
1440 switch (resp) {
1441 case UPIU_TRANSACTION_NOP_IN:
1442 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
1443 err = -EINVAL;
1444 dev_err(hba->dev, "%s: unexpected response %x\n",
1445 __func__, resp);
1446 }
1447 break;
1448 case UPIU_TRANSACTION_QUERY_RSP:
1449 err = ufshcd_check_query_response(hba, lrbp);
1450 if (!err)
1451 err = ufshcd_copy_query_response(hba, lrbp);
1452 break;
1453 case UPIU_TRANSACTION_REJECT_UPIU:
1454 /* TODO: handle Reject UPIU Response */
1455 err = -EPERM;
1456 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
1457 __func__);
1458 break;
1459 default:
1460 err = -EINVAL;
1461 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
1462 __func__, resp);
1463 break;
1464 }
1465
1466 return err;
1467 }
1468
1469 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
1470 struct ufshcd_lrb *lrbp, int max_timeout)
1471 {
1472 int err = 0;
1473 unsigned long time_left;
1474 unsigned long flags;
1475
1476 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
1477 msecs_to_jiffies(max_timeout));
1478
1479 spin_lock_irqsave(hba->host->host_lock, flags);
1480 hba->dev_cmd.complete = NULL;
1481 if (likely(time_left)) {
1482 err = ufshcd_get_tr_ocs(lrbp);
1483 if (!err)
1484 err = ufshcd_dev_cmd_completion(hba, lrbp);
1485 }
1486 spin_unlock_irqrestore(hba->host->host_lock, flags);
1487
1488 if (!time_left) {
1489 err = -ETIMEDOUT;
1490 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
1491 /* sucessfully cleared the command, retry if needed */
1492 err = -EAGAIN;
1493 }
1494
1495 return err;
1496 }
1497
1498 /**
1499 * ufshcd_get_dev_cmd_tag - Get device management command tag
1500 * @hba: per-adapter instance
1501 * @tag: pointer to variable with available slot value
1502 *
1503 * Get a free slot and lock it until device management command
1504 * completes.
1505 *
1506 * Returns false if free slot is unavailable for locking, else
1507 * return true with tag value in @tag.
1508 */
1509 static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
1510 {
1511 int tag;
1512 bool ret = false;
1513 unsigned long tmp;
1514
1515 if (!tag_out)
1516 goto out;
1517
1518 do {
1519 tmp = ~hba->lrb_in_use;
1520 tag = find_last_bit(&tmp, hba->nutrs);
1521 if (tag >= hba->nutrs)
1522 goto out;
1523 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
1524
1525 *tag_out = tag;
1526 ret = true;
1527 out:
1528 return ret;
1529 }
1530
1531 static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
1532 {
1533 clear_bit_unlock(tag, &hba->lrb_in_use);
1534 }
1535
1536 /**
1537 * ufshcd_exec_dev_cmd - API for sending device management requests
1538 * @hba - UFS hba
1539 * @cmd_type - specifies the type (NOP, Query...)
1540 * @timeout - time in seconds
1541 *
1542 * NOTE: Since there is only one available tag for device management commands,
1543 * it is expected you hold the hba->dev_cmd.lock mutex.
1544 */
1545 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
1546 enum dev_cmd_type cmd_type, int timeout)
1547 {
1548 struct ufshcd_lrb *lrbp;
1549 int err;
1550 int tag;
1551 struct completion wait;
1552 unsigned long flags;
1553
1554 /*
1555 * Get free slot, sleep if slots are unavailable.
1556 * Even though we use wait_event() which sleeps indefinitely,
1557 * the maximum wait time is bounded by SCSI request timeout.
1558 */
1559 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
1560
1561 init_completion(&wait);
1562 lrbp = &hba->lrb[tag];
1563 WARN_ON(lrbp->cmd);
1564 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
1565 if (unlikely(err))
1566 goto out_put_tag;
1567
1568 hba->dev_cmd.complete = &wait;
1569
1570 spin_lock_irqsave(hba->host->host_lock, flags);
1571 ufshcd_send_command(hba, tag);
1572 spin_unlock_irqrestore(hba->host->host_lock, flags);
1573
1574 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
1575
1576 out_put_tag:
1577 ufshcd_put_dev_cmd_tag(hba, tag);
1578 wake_up(&hba->dev_cmd.tag_wq);
1579 return err;
1580 }
1581
1582 /**
1583 * ufshcd_init_query() - init the query response and request parameters
1584 * @hba: per-adapter instance
1585 * @request: address of the request pointer to be initialized
1586 * @response: address of the response pointer to be initialized
1587 * @opcode: operation to perform
1588 * @idn: flag idn to access
1589 * @index: LU number to access
1590 * @selector: query/flag/descriptor further identification
1591 */
1592 static inline void ufshcd_init_query(struct ufs_hba *hba,
1593 struct ufs_query_req **request, struct ufs_query_res **response,
1594 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
1595 {
1596 *request = &hba->dev_cmd.query.request;
1597 *response = &hba->dev_cmd.query.response;
1598 memset(*request, 0, sizeof(struct ufs_query_req));
1599 memset(*response, 0, sizeof(struct ufs_query_res));
1600 (*request)->upiu_req.opcode = opcode;
1601 (*request)->upiu_req.idn = idn;
1602 (*request)->upiu_req.index = index;
1603 (*request)->upiu_req.selector = selector;
1604 }
1605
1606 /**
1607 * ufshcd_query_flag() - API function for sending flag query requests
1608 * hba: per-adapter instance
1609 * query_opcode: flag query to perform
1610 * idn: flag idn to access
1611 * flag_res: the flag value after the query request completes
1612 *
1613 * Returns 0 for success, non-zero in case of failure
1614 */
1615 static int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
1616 enum flag_idn idn, bool *flag_res)
1617 {
1618 struct ufs_query_req *request = NULL;
1619 struct ufs_query_res *response = NULL;
1620 int err, index = 0, selector = 0;
1621
1622 BUG_ON(!hba);
1623
1624 ufshcd_hold(hba, false);
1625 mutex_lock(&hba->dev_cmd.lock);
1626 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1627 selector);
1628
1629 switch (opcode) {
1630 case UPIU_QUERY_OPCODE_SET_FLAG:
1631 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
1632 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
1633 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1634 break;
1635 case UPIU_QUERY_OPCODE_READ_FLAG:
1636 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1637 if (!flag_res) {
1638 /* No dummy reads */
1639 dev_err(hba->dev, "%s: Invalid argument for read request\n",
1640 __func__);
1641 err = -EINVAL;
1642 goto out_unlock;
1643 }
1644 break;
1645 default:
1646 dev_err(hba->dev,
1647 "%s: Expected query flag opcode but got = %d\n",
1648 __func__, opcode);
1649 err = -EINVAL;
1650 goto out_unlock;
1651 }
1652
1653 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
1654
1655 if (err) {
1656 dev_err(hba->dev,
1657 "%s: Sending flag query for idn %d failed, err = %d\n",
1658 __func__, idn, err);
1659 goto out_unlock;
1660 }
1661
1662 if (flag_res)
1663 *flag_res = (be32_to_cpu(response->upiu_res.value) &
1664 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
1665
1666 out_unlock:
1667 mutex_unlock(&hba->dev_cmd.lock);
1668 ufshcd_release(hba);
1669 return err;
1670 }
1671
1672 /**
1673 * ufshcd_query_attr - API function for sending attribute requests
1674 * hba: per-adapter instance
1675 * opcode: attribute opcode
1676 * idn: attribute idn to access
1677 * index: index field
1678 * selector: selector field
1679 * attr_val: the attribute value after the query request completes
1680 *
1681 * Returns 0 for success, non-zero in case of failure
1682 */
1683 static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
1684 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
1685 {
1686 struct ufs_query_req *request = NULL;
1687 struct ufs_query_res *response = NULL;
1688 int err;
1689
1690 BUG_ON(!hba);
1691
1692 ufshcd_hold(hba, false);
1693 if (!attr_val) {
1694 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
1695 __func__, opcode);
1696 err = -EINVAL;
1697 goto out;
1698 }
1699
1700 mutex_lock(&hba->dev_cmd.lock);
1701 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1702 selector);
1703
1704 switch (opcode) {
1705 case UPIU_QUERY_OPCODE_WRITE_ATTR:
1706 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1707 request->upiu_req.value = cpu_to_be32(*attr_val);
1708 break;
1709 case UPIU_QUERY_OPCODE_READ_ATTR:
1710 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1711 break;
1712 default:
1713 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
1714 __func__, opcode);
1715 err = -EINVAL;
1716 goto out_unlock;
1717 }
1718
1719 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
1720
1721 if (err) {
1722 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
1723 __func__, opcode, idn, err);
1724 goto out_unlock;
1725 }
1726
1727 *attr_val = be32_to_cpu(response->upiu_res.value);
1728
1729 out_unlock:
1730 mutex_unlock(&hba->dev_cmd.lock);
1731 out:
1732 ufshcd_release(hba);
1733 return err;
1734 }
1735
1736 /**
1737 * ufshcd_query_descriptor - API function for sending descriptor requests
1738 * hba: per-adapter instance
1739 * opcode: attribute opcode
1740 * idn: attribute idn to access
1741 * index: index field
1742 * selector: selector field
1743 * desc_buf: the buffer that contains the descriptor
1744 * buf_len: length parameter passed to the device
1745 *
1746 * Returns 0 for success, non-zero in case of failure.
1747 * The buf_len parameter will contain, on return, the length parameter
1748 * received on the response.
1749 */
1750 static int ufshcd_query_descriptor(struct ufs_hba *hba,
1751 enum query_opcode opcode, enum desc_idn idn, u8 index,
1752 u8 selector, u8 *desc_buf, int *buf_len)
1753 {
1754 struct ufs_query_req *request = NULL;
1755 struct ufs_query_res *response = NULL;
1756 int err;
1757
1758 BUG_ON(!hba);
1759
1760 ufshcd_hold(hba, false);
1761 if (!desc_buf) {
1762 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
1763 __func__, opcode);
1764 err = -EINVAL;
1765 goto out;
1766 }
1767
1768 if (*buf_len <= QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
1769 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
1770 __func__, *buf_len);
1771 err = -EINVAL;
1772 goto out;
1773 }
1774
1775 mutex_lock(&hba->dev_cmd.lock);
1776 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1777 selector);
1778 hba->dev_cmd.query.descriptor = desc_buf;
1779 request->upiu_req.length = cpu_to_be16(*buf_len);
1780
1781 switch (opcode) {
1782 case UPIU_QUERY_OPCODE_WRITE_DESC:
1783 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1784 break;
1785 case UPIU_QUERY_OPCODE_READ_DESC:
1786 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1787 break;
1788 default:
1789 dev_err(hba->dev,
1790 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
1791 __func__, opcode);
1792 err = -EINVAL;
1793 goto out_unlock;
1794 }
1795
1796 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
1797
1798 if (err) {
1799 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
1800 __func__, opcode, idn, err);
1801 goto out_unlock;
1802 }
1803
1804 hba->dev_cmd.query.descriptor = NULL;
1805 *buf_len = be16_to_cpu(response->upiu_res.length);
1806
1807 out_unlock:
1808 mutex_unlock(&hba->dev_cmd.lock);
1809 out:
1810 ufshcd_release(hba);
1811 return err;
1812 }
1813
1814 /**
1815 * ufshcd_read_desc_param - read the specified descriptor parameter
1816 * @hba: Pointer to adapter instance
1817 * @desc_id: descriptor idn value
1818 * @desc_index: descriptor index
1819 * @param_offset: offset of the parameter to read
1820 * @param_read_buf: pointer to buffer where parameter would be read
1821 * @param_size: sizeof(param_read_buf)
1822 *
1823 * Return 0 in case of success, non-zero otherwise
1824 */
1825 static int ufshcd_read_desc_param(struct ufs_hba *hba,
1826 enum desc_idn desc_id,
1827 int desc_index,
1828 u32 param_offset,
1829 u8 *param_read_buf,
1830 u32 param_size)
1831 {
1832 int ret;
1833 u8 *desc_buf;
1834 u32 buff_len;
1835 bool is_kmalloc = true;
1836
1837 /* safety checks */
1838 if (desc_id >= QUERY_DESC_IDN_MAX)
1839 return -EINVAL;
1840
1841 buff_len = ufs_query_desc_max_size[desc_id];
1842 if ((param_offset + param_size) > buff_len)
1843 return -EINVAL;
1844
1845 if (!param_offset && (param_size == buff_len)) {
1846 /* memory space already available to hold full descriptor */
1847 desc_buf = param_read_buf;
1848 is_kmalloc = false;
1849 } else {
1850 /* allocate memory to hold full descriptor */
1851 desc_buf = kmalloc(buff_len, GFP_KERNEL);
1852 if (!desc_buf)
1853 return -ENOMEM;
1854 }
1855
1856 ret = ufshcd_query_descriptor(hba, UPIU_QUERY_OPCODE_READ_DESC,
1857 desc_id, desc_index, 0, desc_buf,
1858 &buff_len);
1859
1860 if (ret || (buff_len < ufs_query_desc_max_size[desc_id]) ||
1861 (desc_buf[QUERY_DESC_LENGTH_OFFSET] !=
1862 ufs_query_desc_max_size[desc_id])
1863 || (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id)) {
1864 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d param_offset %d buff_len %d ret %d",
1865 __func__, desc_id, param_offset, buff_len, ret);
1866 if (!ret)
1867 ret = -EINVAL;
1868
1869 goto out;
1870 }
1871
1872 if (is_kmalloc)
1873 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
1874 out:
1875 if (is_kmalloc)
1876 kfree(desc_buf);
1877 return ret;
1878 }
1879
1880 static inline int ufshcd_read_desc(struct ufs_hba *hba,
1881 enum desc_idn desc_id,
1882 int desc_index,
1883 u8 *buf,
1884 u32 size)
1885 {
1886 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
1887 }
1888
1889 static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
1890 u8 *buf,
1891 u32 size)
1892 {
1893 return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
1894 }
1895
1896 /**
1897 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
1898 * @hba: Pointer to adapter instance
1899 * @lun: lun id
1900 * @param_offset: offset of the parameter to read
1901 * @param_read_buf: pointer to buffer where parameter would be read
1902 * @param_size: sizeof(param_read_buf)
1903 *
1904 * Return 0 in case of success, non-zero otherwise
1905 */
1906 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
1907 int lun,
1908 enum unit_desc_param param_offset,
1909 u8 *param_read_buf,
1910 u32 param_size)
1911 {
1912 /*
1913 * Unit descriptors are only available for general purpose LUs (LUN id
1914 * from 0 to 7) and RPMB Well known LU.
1915 */
1916 if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN))
1917 return -EOPNOTSUPP;
1918
1919 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
1920 param_offset, param_read_buf, param_size);
1921 }
1922
1923 /**
1924 * ufshcd_memory_alloc - allocate memory for host memory space data structures
1925 * @hba: per adapter instance
1926 *
1927 * 1. Allocate DMA memory for Command Descriptor array
1928 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
1929 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
1930 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
1931 * (UTMRDL)
1932 * 4. Allocate memory for local reference block(lrb).
1933 *
1934 * Returns 0 for success, non-zero in case of failure
1935 */
1936 static int ufshcd_memory_alloc(struct ufs_hba *hba)
1937 {
1938 size_t utmrdl_size, utrdl_size, ucdl_size;
1939
1940 /* Allocate memory for UTP command descriptors */
1941 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
1942 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
1943 ucdl_size,
1944 &hba->ucdl_dma_addr,
1945 GFP_KERNEL);
1946
1947 /*
1948 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
1949 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
1950 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
1951 * be aligned to 128 bytes as well
1952 */
1953 if (!hba->ucdl_base_addr ||
1954 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
1955 dev_err(hba->dev,
1956 "Command Descriptor Memory allocation failed\n");
1957 goto out;
1958 }
1959
1960 /*
1961 * Allocate memory for UTP Transfer descriptors
1962 * UFSHCI requires 1024 byte alignment of UTRD
1963 */
1964 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
1965 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
1966 utrdl_size,
1967 &hba->utrdl_dma_addr,
1968 GFP_KERNEL);
1969 if (!hba->utrdl_base_addr ||
1970 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
1971 dev_err(hba->dev,
1972 "Transfer Descriptor Memory allocation failed\n");
1973 goto out;
1974 }
1975
1976 /*
1977 * Allocate memory for UTP Task Management descriptors
1978 * UFSHCI requires 1024 byte alignment of UTMRD
1979 */
1980 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
1981 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
1982 utmrdl_size,
1983 &hba->utmrdl_dma_addr,
1984 GFP_KERNEL);
1985 if (!hba->utmrdl_base_addr ||
1986 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
1987 dev_err(hba->dev,
1988 "Task Management Descriptor Memory allocation failed\n");
1989 goto out;
1990 }
1991
1992 /* Allocate memory for local reference block */
1993 hba->lrb = devm_kzalloc(hba->dev,
1994 hba->nutrs * sizeof(struct ufshcd_lrb),
1995 GFP_KERNEL);
1996 if (!hba->lrb) {
1997 dev_err(hba->dev, "LRB Memory allocation failed\n");
1998 goto out;
1999 }
2000 return 0;
2001 out:
2002 return -ENOMEM;
2003 }
2004
2005 /**
2006 * ufshcd_host_memory_configure - configure local reference block with
2007 * memory offsets
2008 * @hba: per adapter instance
2009 *
2010 * Configure Host memory space
2011 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
2012 * address.
2013 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
2014 * and PRDT offset.
2015 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
2016 * into local reference block.
2017 */
2018 static void ufshcd_host_memory_configure(struct ufs_hba *hba)
2019 {
2020 struct utp_transfer_cmd_desc *cmd_descp;
2021 struct utp_transfer_req_desc *utrdlp;
2022 dma_addr_t cmd_desc_dma_addr;
2023 dma_addr_t cmd_desc_element_addr;
2024 u16 response_offset;
2025 u16 prdt_offset;
2026 int cmd_desc_size;
2027 int i;
2028
2029 utrdlp = hba->utrdl_base_addr;
2030 cmd_descp = hba->ucdl_base_addr;
2031
2032 response_offset =
2033 offsetof(struct utp_transfer_cmd_desc, response_upiu);
2034 prdt_offset =
2035 offsetof(struct utp_transfer_cmd_desc, prd_table);
2036
2037 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
2038 cmd_desc_dma_addr = hba->ucdl_dma_addr;
2039
2040 for (i = 0; i < hba->nutrs; i++) {
2041 /* Configure UTRD with command descriptor base address */
2042 cmd_desc_element_addr =
2043 (cmd_desc_dma_addr + (cmd_desc_size * i));
2044 utrdlp[i].command_desc_base_addr_lo =
2045 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
2046 utrdlp[i].command_desc_base_addr_hi =
2047 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
2048
2049 /* Response upiu and prdt offset should be in double words */
2050 utrdlp[i].response_upiu_offset =
2051 cpu_to_le16((response_offset >> 2));
2052 utrdlp[i].prd_table_offset =
2053 cpu_to_le16((prdt_offset >> 2));
2054 utrdlp[i].response_upiu_length =
2055 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
2056
2057 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
2058 hba->lrb[i].ucd_req_ptr =
2059 (struct utp_upiu_req *)(cmd_descp + i);
2060 hba->lrb[i].ucd_rsp_ptr =
2061 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2062 hba->lrb[i].ucd_prdt_ptr =
2063 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
2064 }
2065 }
2066
2067 /**
2068 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
2069 * @hba: per adapter instance
2070 *
2071 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
2072 * in order to initialize the Unipro link startup procedure.
2073 * Once the Unipro links are up, the device connected to the controller
2074 * is detected.
2075 *
2076 * Returns 0 on success, non-zero value on failure
2077 */
2078 static int ufshcd_dme_link_startup(struct ufs_hba *hba)
2079 {
2080 struct uic_command uic_cmd = {0};
2081 int ret;
2082
2083 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
2084
2085 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2086 if (ret)
2087 dev_err(hba->dev,
2088 "dme-link-startup: error code %d\n", ret);
2089 return ret;
2090 }
2091
2092 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
2093 {
2094 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
2095 unsigned long min_sleep_time_us;
2096
2097 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
2098 return;
2099
2100 /*
2101 * last_dme_cmd_tstamp will be 0 only for 1st call to
2102 * this function
2103 */
2104 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
2105 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
2106 } else {
2107 unsigned long delta =
2108 (unsigned long) ktime_to_us(
2109 ktime_sub(ktime_get(),
2110 hba->last_dme_cmd_tstamp));
2111
2112 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
2113 min_sleep_time_us =
2114 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
2115 else
2116 return; /* no more delay required */
2117 }
2118
2119 /* allow sleep for extra 50us if needed */
2120 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
2121 }
2122
2123 /**
2124 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
2125 * @hba: per adapter instance
2126 * @attr_sel: uic command argument1
2127 * @attr_set: attribute set type as uic command argument2
2128 * @mib_val: setting value as uic command argument3
2129 * @peer: indicate whether peer or local
2130 *
2131 * Returns 0 on success, non-zero value on failure
2132 */
2133 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
2134 u8 attr_set, u32 mib_val, u8 peer)
2135 {
2136 struct uic_command uic_cmd = {0};
2137 static const char *const action[] = {
2138 "dme-set",
2139 "dme-peer-set"
2140 };
2141 const char *set = action[!!peer];
2142 int ret;
2143
2144 uic_cmd.command = peer ?
2145 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
2146 uic_cmd.argument1 = attr_sel;
2147 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
2148 uic_cmd.argument3 = mib_val;
2149
2150 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2151 if (ret)
2152 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
2153 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
2154
2155 return ret;
2156 }
2157 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
2158
2159 /**
2160 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
2161 * @hba: per adapter instance
2162 * @attr_sel: uic command argument1
2163 * @mib_val: the value of the attribute as returned by the UIC command
2164 * @peer: indicate whether peer or local
2165 *
2166 * Returns 0 on success, non-zero value on failure
2167 */
2168 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
2169 u32 *mib_val, u8 peer)
2170 {
2171 struct uic_command uic_cmd = {0};
2172 static const char *const action[] = {
2173 "dme-get",
2174 "dme-peer-get"
2175 };
2176 const char *get = action[!!peer];
2177 int ret;
2178 struct ufs_pa_layer_attr orig_pwr_info;
2179 struct ufs_pa_layer_attr temp_pwr_info;
2180 bool pwr_mode_change = false;
2181
2182 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
2183 orig_pwr_info = hba->pwr_info;
2184 temp_pwr_info = orig_pwr_info;
2185
2186 if (orig_pwr_info.pwr_tx == FAST_MODE ||
2187 orig_pwr_info.pwr_rx == FAST_MODE) {
2188 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
2189 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
2190 pwr_mode_change = true;
2191 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
2192 orig_pwr_info.pwr_rx == SLOW_MODE) {
2193 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
2194 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
2195 pwr_mode_change = true;
2196 }
2197 if (pwr_mode_change) {
2198 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
2199 if (ret)
2200 goto out;
2201 }
2202 }
2203
2204 uic_cmd.command = peer ?
2205 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
2206 uic_cmd.argument1 = attr_sel;
2207
2208 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2209 if (ret) {
2210 dev_err(hba->dev, "%s: attr-id 0x%x error code %d\n",
2211 get, UIC_GET_ATTR_ID(attr_sel), ret);
2212 goto out;
2213 }
2214
2215 if (mib_val)
2216 *mib_val = uic_cmd.argument3;
2217
2218 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
2219 && pwr_mode_change)
2220 ufshcd_change_power_mode(hba, &orig_pwr_info);
2221 out:
2222 return ret;
2223 }
2224 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
2225
2226 /**
2227 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
2228 * state) and waits for it to take effect.
2229 *
2230 * @hba: per adapter instance
2231 * @cmd: UIC command to execute
2232 *
2233 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
2234 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
2235 * and device UniPro link and hence it's final completion would be indicated by
2236 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
2237 * addition to normal UIC command completion Status (UCCS). This function only
2238 * returns after the relevant status bits indicate the completion.
2239 *
2240 * Returns 0 on success, non-zero value on failure
2241 */
2242 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
2243 {
2244 struct completion uic_async_done;
2245 unsigned long flags;
2246 u8 status;
2247 int ret;
2248
2249 mutex_lock(&hba->uic_cmd_mutex);
2250 init_completion(&uic_async_done);
2251 ufshcd_add_delay_before_dme_cmd(hba);
2252
2253 spin_lock_irqsave(hba->host->host_lock, flags);
2254 hba->uic_async_done = &uic_async_done;
2255 ret = __ufshcd_send_uic_cmd(hba, cmd);
2256 spin_unlock_irqrestore(hba->host->host_lock, flags);
2257 if (ret) {
2258 dev_err(hba->dev,
2259 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
2260 cmd->command, cmd->argument3, ret);
2261 goto out;
2262 }
2263 ret = ufshcd_wait_for_uic_cmd(hba, cmd);
2264 if (ret) {
2265 dev_err(hba->dev,
2266 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
2267 cmd->command, cmd->argument3, ret);
2268 goto out;
2269 }
2270
2271 if (!wait_for_completion_timeout(hba->uic_async_done,
2272 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2273 dev_err(hba->dev,
2274 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
2275 cmd->command, cmd->argument3);
2276 ret = -ETIMEDOUT;
2277 goto out;
2278 }
2279
2280 status = ufshcd_get_upmcrs(hba);
2281 if (status != PWR_LOCAL) {
2282 dev_err(hba->dev,
2283 "pwr ctrl cmd 0x%0x failed, host umpcrs:0x%x\n",
2284 cmd->command, status);
2285 ret = (status != PWR_OK) ? status : -1;
2286 }
2287 out:
2288 spin_lock_irqsave(hba->host->host_lock, flags);
2289 hba->uic_async_done = NULL;
2290 spin_unlock_irqrestore(hba->host->host_lock, flags);
2291 mutex_unlock(&hba->uic_cmd_mutex);
2292
2293 return ret;
2294 }
2295
2296 /**
2297 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
2298 * using DME_SET primitives.
2299 * @hba: per adapter instance
2300 * @mode: powr mode value
2301 *
2302 * Returns 0 on success, non-zero value on failure
2303 */
2304 static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
2305 {
2306 struct uic_command uic_cmd = {0};
2307 int ret;
2308
2309 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
2310 ret = ufshcd_dme_set(hba,
2311 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
2312 if (ret) {
2313 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
2314 __func__, ret);
2315 goto out;
2316 }
2317 }
2318
2319 uic_cmd.command = UIC_CMD_DME_SET;
2320 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
2321 uic_cmd.argument3 = mode;
2322 ufshcd_hold(hba, false);
2323 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2324 ufshcd_release(hba);
2325
2326 out:
2327 return ret;
2328 }
2329
2330 static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
2331 {
2332 struct uic_command uic_cmd = {0};
2333
2334 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
2335
2336 return ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2337 }
2338
2339 static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
2340 {
2341 struct uic_command uic_cmd = {0};
2342 int ret;
2343
2344 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
2345 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2346 if (ret) {
2347 ufshcd_set_link_off(hba);
2348 ret = ufshcd_host_reset_and_restore(hba);
2349 }
2350
2351 return ret;
2352 }
2353
2354 /**
2355 * ufshcd_init_pwr_info - setting the POR (power on reset)
2356 * values in hba power info
2357 * @hba: per-adapter instance
2358 */
2359 static void ufshcd_init_pwr_info(struct ufs_hba *hba)
2360 {
2361 hba->pwr_info.gear_rx = UFS_PWM_G1;
2362 hba->pwr_info.gear_tx = UFS_PWM_G1;
2363 hba->pwr_info.lane_rx = 1;
2364 hba->pwr_info.lane_tx = 1;
2365 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
2366 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
2367 hba->pwr_info.hs_rate = 0;
2368 }
2369
2370 /**
2371 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
2372 * @hba: per-adapter instance
2373 */
2374 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
2375 {
2376 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
2377
2378 if (hba->max_pwr_info.is_valid)
2379 return 0;
2380
2381 pwr_info->pwr_tx = FASTAUTO_MODE;
2382 pwr_info->pwr_rx = FASTAUTO_MODE;
2383 pwr_info->hs_rate = PA_HS_MODE_B;
2384
2385 /* Get the connected lane count */
2386 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
2387 &pwr_info->lane_rx);
2388 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
2389 &pwr_info->lane_tx);
2390
2391 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
2392 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
2393 __func__,
2394 pwr_info->lane_rx,
2395 pwr_info->lane_tx);
2396 return -EINVAL;
2397 }
2398
2399 /*
2400 * First, get the maximum gears of HS speed.
2401 * If a zero value, it means there is no HSGEAR capability.
2402 * Then, get the maximum gears of PWM speed.
2403 */
2404 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
2405 if (!pwr_info->gear_rx) {
2406 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
2407 &pwr_info->gear_rx);
2408 if (!pwr_info->gear_rx) {
2409 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
2410 __func__, pwr_info->gear_rx);
2411 return -EINVAL;
2412 }
2413 pwr_info->pwr_rx = SLOWAUTO_MODE;
2414 }
2415
2416 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
2417 &pwr_info->gear_tx);
2418 if (!pwr_info->gear_tx) {
2419 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
2420 &pwr_info->gear_tx);
2421 if (!pwr_info->gear_tx) {
2422 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
2423 __func__, pwr_info->gear_tx);
2424 return -EINVAL;
2425 }
2426 pwr_info->pwr_tx = SLOWAUTO_MODE;
2427 }
2428
2429 hba->max_pwr_info.is_valid = true;
2430 return 0;
2431 }
2432
2433 static int ufshcd_change_power_mode(struct ufs_hba *hba,
2434 struct ufs_pa_layer_attr *pwr_mode)
2435 {
2436 int ret;
2437
2438 /* if already configured to the requested pwr_mode */
2439 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
2440 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
2441 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
2442 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
2443 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
2444 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
2445 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
2446 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
2447 return 0;
2448 }
2449
2450 /*
2451 * Configure attributes for power mode change with below.
2452 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
2453 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
2454 * - PA_HSSERIES
2455 */
2456 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
2457 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
2458 pwr_mode->lane_rx);
2459 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
2460 pwr_mode->pwr_rx == FAST_MODE)
2461 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
2462 else
2463 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
2464
2465 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
2466 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
2467 pwr_mode->lane_tx);
2468 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
2469 pwr_mode->pwr_tx == FAST_MODE)
2470 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
2471 else
2472 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
2473
2474 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
2475 pwr_mode->pwr_tx == FASTAUTO_MODE ||
2476 pwr_mode->pwr_rx == FAST_MODE ||
2477 pwr_mode->pwr_tx == FAST_MODE)
2478 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
2479 pwr_mode->hs_rate);
2480
2481 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
2482 | pwr_mode->pwr_tx);
2483
2484 if (ret) {
2485 dev_err(hba->dev,
2486 "%s: power mode change failed %d\n", __func__, ret);
2487 } else {
2488 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
2489 pwr_mode);
2490
2491 memcpy(&hba->pwr_info, pwr_mode,
2492 sizeof(struct ufs_pa_layer_attr));
2493 }
2494
2495 return ret;
2496 }
2497
2498 /**
2499 * ufshcd_config_pwr_mode - configure a new power mode
2500 * @hba: per-adapter instance
2501 * @desired_pwr_mode: desired power configuration
2502 */
2503 static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
2504 struct ufs_pa_layer_attr *desired_pwr_mode)
2505 {
2506 struct ufs_pa_layer_attr final_params = { 0 };
2507 int ret;
2508
2509 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
2510 desired_pwr_mode, &final_params);
2511
2512 if (ret)
2513 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
2514
2515 ret = ufshcd_change_power_mode(hba, &final_params);
2516
2517 return ret;
2518 }
2519
2520 /**
2521 * ufshcd_complete_dev_init() - checks device readiness
2522 * hba: per-adapter instance
2523 *
2524 * Set fDeviceInit flag and poll until device toggles it.
2525 */
2526 static int ufshcd_complete_dev_init(struct ufs_hba *hba)
2527 {
2528 int i, retries, err = 0;
2529 bool flag_res = 1;
2530
2531 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2532 /* Set the fDeviceInit flag */
2533 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG,
2534 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
2535 if (!err || err == -ETIMEDOUT)
2536 break;
2537 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
2538 }
2539 if (err) {
2540 dev_err(hba->dev,
2541 "%s setting fDeviceInit flag failed with error %d\n",
2542 __func__, err);
2543 goto out;
2544 }
2545
2546 /* poll for max. 100 iterations for fDeviceInit flag to clear */
2547 for (i = 0; i < 100 && !err && flag_res; i++) {
2548 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2549 err = ufshcd_query_flag(hba,
2550 UPIU_QUERY_OPCODE_READ_FLAG,
2551 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
2552 if (!err || err == -ETIMEDOUT)
2553 break;
2554 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__,
2555 err);
2556 }
2557 }
2558 if (err)
2559 dev_err(hba->dev,
2560 "%s reading fDeviceInit flag failed with error %d\n",
2561 __func__, err);
2562 else if (flag_res)
2563 dev_err(hba->dev,
2564 "%s fDeviceInit was not cleared by the device\n",
2565 __func__);
2566
2567 out:
2568 return err;
2569 }
2570
2571 /**
2572 * ufshcd_make_hba_operational - Make UFS controller operational
2573 * @hba: per adapter instance
2574 *
2575 * To bring UFS host controller to operational state,
2576 * 1. Enable required interrupts
2577 * 2. Configure interrupt aggregation
2578 * 3. Program UTRL and UTMRL base addres
2579 * 4. Configure run-stop-registers
2580 *
2581 * Returns 0 on success, non-zero value on failure
2582 */
2583 static int ufshcd_make_hba_operational(struct ufs_hba *hba)
2584 {
2585 int err = 0;
2586 u32 reg;
2587
2588 /* Enable required interrupts */
2589 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
2590
2591 /* Configure interrupt aggregation */
2592 if (ufshcd_is_intr_aggr_allowed(hba))
2593 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
2594 else
2595 ufshcd_disable_intr_aggr(hba);
2596
2597 /* Configure UTRL and UTMRL base address registers */
2598 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
2599 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
2600 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
2601 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
2602 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
2603 REG_UTP_TASK_REQ_LIST_BASE_L);
2604 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
2605 REG_UTP_TASK_REQ_LIST_BASE_H);
2606
2607 /*
2608 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
2609 * DEI, HEI bits must be 0
2610 */
2611 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
2612 if (!(ufshcd_get_lists_status(reg))) {
2613 ufshcd_enable_run_stop_reg(hba);
2614 } else {
2615 dev_err(hba->dev,
2616 "Host controller not ready to process requests");
2617 err = -EIO;
2618 goto out;
2619 }
2620
2621 out:
2622 return err;
2623 }
2624
2625 /**
2626 * ufshcd_hba_enable - initialize the controller
2627 * @hba: per adapter instance
2628 *
2629 * The controller resets itself and controller firmware initialization
2630 * sequence kicks off. When controller is ready it will set
2631 * the Host Controller Enable bit to 1.
2632 *
2633 * Returns 0 on success, non-zero value on failure
2634 */
2635 static int ufshcd_hba_enable(struct ufs_hba *hba)
2636 {
2637 int retry;
2638
2639 /*
2640 * msleep of 1 and 5 used in this function might result in msleep(20),
2641 * but it was necessary to send the UFS FPGA to reset mode during
2642 * development and testing of this driver. msleep can be changed to
2643 * mdelay and retry count can be reduced based on the controller.
2644 */
2645 if (!ufshcd_is_hba_active(hba)) {
2646
2647 /* change controller state to "reset state" */
2648 ufshcd_hba_stop(hba);
2649
2650 /*
2651 * This delay is based on the testing done with UFS host
2652 * controller FPGA. The delay can be changed based on the
2653 * host controller used.
2654 */
2655 msleep(5);
2656 }
2657
2658 /* UniPro link is disabled at this point */
2659 ufshcd_set_link_off(hba);
2660
2661 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
2662
2663 /* start controller initialization sequence */
2664 ufshcd_hba_start(hba);
2665
2666 /*
2667 * To initialize a UFS host controller HCE bit must be set to 1.
2668 * During initialization the HCE bit value changes from 1->0->1.
2669 * When the host controller completes initialization sequence
2670 * it sets the value of HCE bit to 1. The same HCE bit is read back
2671 * to check if the controller has completed initialization sequence.
2672 * So without this delay the value HCE = 1, set in the previous
2673 * instruction might be read back.
2674 * This delay can be changed based on the controller.
2675 */
2676 msleep(1);
2677
2678 /* wait for the host controller to complete initialization */
2679 retry = 10;
2680 while (ufshcd_is_hba_active(hba)) {
2681 if (retry) {
2682 retry--;
2683 } else {
2684 dev_err(hba->dev,
2685 "Controller enable failed\n");
2686 return -EIO;
2687 }
2688 msleep(5);
2689 }
2690
2691 /* enable UIC related interrupts */
2692 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
2693
2694 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
2695
2696 return 0;
2697 }
2698
2699 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
2700 {
2701 int tx_lanes, i, err = 0;
2702
2703 if (!peer)
2704 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
2705 &tx_lanes);
2706 else
2707 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
2708 &tx_lanes);
2709 for (i = 0; i < tx_lanes; i++) {
2710 if (!peer)
2711 err = ufshcd_dme_set(hba,
2712 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
2713 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
2714 0);
2715 else
2716 err = ufshcd_dme_peer_set(hba,
2717 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
2718 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
2719 0);
2720 if (err) {
2721 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
2722 __func__, peer, i, err);
2723 break;
2724 }
2725 }
2726
2727 return err;
2728 }
2729
2730 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
2731 {
2732 return ufshcd_disable_tx_lcc(hba, true);
2733 }
2734
2735 /**
2736 * ufshcd_link_startup - Initialize unipro link startup
2737 * @hba: per adapter instance
2738 *
2739 * Returns 0 for success, non-zero in case of failure
2740 */
2741 static int ufshcd_link_startup(struct ufs_hba *hba)
2742 {
2743 int ret;
2744 int retries = DME_LINKSTARTUP_RETRIES;
2745
2746 do {
2747 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
2748
2749 ret = ufshcd_dme_link_startup(hba);
2750
2751 /* check if device is detected by inter-connect layer */
2752 if (!ret && !ufshcd_is_device_present(hba)) {
2753 dev_err(hba->dev, "%s: Device not present\n", __func__);
2754 ret = -ENXIO;
2755 goto out;
2756 }
2757
2758 /*
2759 * DME link lost indication is only received when link is up,
2760 * but we can't be sure if the link is up until link startup
2761 * succeeds. So reset the local Uni-Pro and try again.
2762 */
2763 if (ret && ufshcd_hba_enable(hba))
2764 goto out;
2765 } while (ret && retries--);
2766
2767 if (ret)
2768 /* failed to get the link up... retire */
2769 goto out;
2770
2771 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
2772 ret = ufshcd_disable_device_tx_lcc(hba);
2773 if (ret)
2774 goto out;
2775 }
2776
2777 /* Include any host controller configuration via UIC commands */
2778 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
2779 if (ret)
2780 goto out;
2781
2782 ret = ufshcd_make_hba_operational(hba);
2783 out:
2784 if (ret)
2785 dev_err(hba->dev, "link startup failed %d\n", ret);
2786 return ret;
2787 }
2788
2789 /**
2790 * ufshcd_verify_dev_init() - Verify device initialization
2791 * @hba: per-adapter instance
2792 *
2793 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
2794 * device Transport Protocol (UTP) layer is ready after a reset.
2795 * If the UTP layer at the device side is not initialized, it may
2796 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
2797 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
2798 */
2799 static int ufshcd_verify_dev_init(struct ufs_hba *hba)
2800 {
2801 int err = 0;
2802 int retries;
2803
2804 ufshcd_hold(hba, false);
2805 mutex_lock(&hba->dev_cmd.lock);
2806 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
2807 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
2808 NOP_OUT_TIMEOUT);
2809
2810 if (!err || err == -ETIMEDOUT)
2811 break;
2812
2813 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
2814 }
2815 mutex_unlock(&hba->dev_cmd.lock);
2816 ufshcd_release(hba);
2817
2818 if (err)
2819 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
2820 return err;
2821 }
2822
2823 /**
2824 * ufshcd_set_queue_depth - set lun queue depth
2825 * @sdev: pointer to SCSI device
2826 *
2827 * Read bLUQueueDepth value and activate scsi tagged command
2828 * queueing. For WLUN, queue depth is set to 1. For best-effort
2829 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
2830 * value that host can queue.
2831 */
2832 static void ufshcd_set_queue_depth(struct scsi_device *sdev)
2833 {
2834 int ret = 0;
2835 u8 lun_qdepth;
2836 struct ufs_hba *hba;
2837
2838 hba = shost_priv(sdev->host);
2839
2840 lun_qdepth = hba->nutrs;
2841 ret = ufshcd_read_unit_desc_param(hba,
2842 ufshcd_scsi_to_upiu_lun(sdev->lun),
2843 UNIT_DESC_PARAM_LU_Q_DEPTH,
2844 &lun_qdepth,
2845 sizeof(lun_qdepth));
2846
2847 /* Some WLUN doesn't support unit descriptor */
2848 if (ret == -EOPNOTSUPP)
2849 lun_qdepth = 1;
2850 else if (!lun_qdepth)
2851 /* eventually, we can figure out the real queue depth */
2852 lun_qdepth = hba->nutrs;
2853 else
2854 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
2855
2856 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
2857 __func__, lun_qdepth);
2858 scsi_change_queue_depth(sdev, lun_qdepth);
2859 }
2860
2861 /*
2862 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
2863 * @hba: per-adapter instance
2864 * @lun: UFS device lun id
2865 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
2866 *
2867 * Returns 0 in case of success and b_lu_write_protect status would be returned
2868 * @b_lu_write_protect parameter.
2869 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
2870 * Returns -EINVAL in case of invalid parameters passed to this function.
2871 */
2872 static int ufshcd_get_lu_wp(struct ufs_hba *hba,
2873 u8 lun,
2874 u8 *b_lu_write_protect)
2875 {
2876 int ret;
2877
2878 if (!b_lu_write_protect)
2879 ret = -EINVAL;
2880 /*
2881 * According to UFS device spec, RPMB LU can't be write
2882 * protected so skip reading bLUWriteProtect parameter for
2883 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
2884 */
2885 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
2886 ret = -ENOTSUPP;
2887 else
2888 ret = ufshcd_read_unit_desc_param(hba,
2889 lun,
2890 UNIT_DESC_PARAM_LU_WR_PROTECT,
2891 b_lu_write_protect,
2892 sizeof(*b_lu_write_protect));
2893 return ret;
2894 }
2895
2896 /**
2897 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
2898 * status
2899 * @hba: per-adapter instance
2900 * @sdev: pointer to SCSI device
2901 *
2902 */
2903 static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
2904 struct scsi_device *sdev)
2905 {
2906 if (hba->dev_info.f_power_on_wp_en &&
2907 !hba->dev_info.is_lu_power_on_wp) {
2908 u8 b_lu_write_protect;
2909
2910 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
2911 &b_lu_write_protect) &&
2912 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
2913 hba->dev_info.is_lu_power_on_wp = true;
2914 }
2915 }
2916
2917 /**
2918 * ufshcd_slave_alloc - handle initial SCSI device configurations
2919 * @sdev: pointer to SCSI device
2920 *
2921 * Returns success
2922 */
2923 static int ufshcd_slave_alloc(struct scsi_device *sdev)
2924 {
2925 struct ufs_hba *hba;
2926
2927 hba = shost_priv(sdev->host);
2928
2929 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
2930 sdev->use_10_for_ms = 1;
2931
2932 /* allow SCSI layer to restart the device in case of errors */
2933 sdev->allow_restart = 1;
2934
2935 /* REPORT SUPPORTED OPERATION CODES is not supported */
2936 sdev->no_report_opcodes = 1;
2937
2938
2939 ufshcd_set_queue_depth(sdev);
2940
2941 ufshcd_get_lu_power_on_wp_status(hba, sdev);
2942
2943 return 0;
2944 }
2945
2946 /**
2947 * ufshcd_change_queue_depth - change queue depth
2948 * @sdev: pointer to SCSI device
2949 * @depth: required depth to set
2950 *
2951 * Change queue depth and make sure the max. limits are not crossed.
2952 */
2953 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
2954 {
2955 struct ufs_hba *hba = shost_priv(sdev->host);
2956
2957 if (depth > hba->nutrs)
2958 depth = hba->nutrs;
2959 return scsi_change_queue_depth(sdev, depth);
2960 }
2961
2962 /**
2963 * ufshcd_slave_configure - adjust SCSI device configurations
2964 * @sdev: pointer to SCSI device
2965 */
2966 static int ufshcd_slave_configure(struct scsi_device *sdev)
2967 {
2968 struct request_queue *q = sdev->request_queue;
2969
2970 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
2971 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
2972
2973 return 0;
2974 }
2975
2976 /**
2977 * ufshcd_slave_destroy - remove SCSI device configurations
2978 * @sdev: pointer to SCSI device
2979 */
2980 static void ufshcd_slave_destroy(struct scsi_device *sdev)
2981 {
2982 struct ufs_hba *hba;
2983
2984 hba = shost_priv(sdev->host);
2985 /* Drop the reference as it won't be needed anymore */
2986 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
2987 unsigned long flags;
2988
2989 spin_lock_irqsave(hba->host->host_lock, flags);
2990 hba->sdev_ufs_device = NULL;
2991 spin_unlock_irqrestore(hba->host->host_lock, flags);
2992 }
2993 }
2994
2995 /**
2996 * ufshcd_task_req_compl - handle task management request completion
2997 * @hba: per adapter instance
2998 * @index: index of the completed request
2999 * @resp: task management service response
3000 *
3001 * Returns non-zero value on error, zero on success
3002 */
3003 static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
3004 {
3005 struct utp_task_req_desc *task_req_descp;
3006 struct utp_upiu_task_rsp *task_rsp_upiup;
3007 unsigned long flags;
3008 int ocs_value;
3009 int task_result;
3010
3011 spin_lock_irqsave(hba->host->host_lock, flags);
3012
3013 /* Clear completed tasks from outstanding_tasks */
3014 __clear_bit(index, &hba->outstanding_tasks);
3015
3016 task_req_descp = hba->utmrdl_base_addr;
3017 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
3018
3019 if (ocs_value == OCS_SUCCESS) {
3020 task_rsp_upiup = (struct utp_upiu_task_rsp *)
3021 task_req_descp[index].task_rsp_upiu;
3022 task_result = be32_to_cpu(task_rsp_upiup->header.dword_1);
3023 task_result = ((task_result & MASK_TASK_RESPONSE) >> 8);
3024 if (resp)
3025 *resp = (u8)task_result;
3026 } else {
3027 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
3028 __func__, ocs_value);
3029 }
3030 spin_unlock_irqrestore(hba->host->host_lock, flags);
3031
3032 return ocs_value;
3033 }
3034
3035 /**
3036 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
3037 * @lrb: pointer to local reference block of completed command
3038 * @scsi_status: SCSI command status
3039 *
3040 * Returns value base on SCSI command status
3041 */
3042 static inline int
3043 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
3044 {
3045 int result = 0;
3046
3047 switch (scsi_status) {
3048 case SAM_STAT_CHECK_CONDITION:
3049 ufshcd_copy_sense_data(lrbp);
3050 case SAM_STAT_GOOD:
3051 result |= DID_OK << 16 |
3052 COMMAND_COMPLETE << 8 |
3053 scsi_status;
3054 break;
3055 case SAM_STAT_TASK_SET_FULL:
3056 case SAM_STAT_BUSY:
3057 case SAM_STAT_TASK_ABORTED:
3058 ufshcd_copy_sense_data(lrbp);
3059 result |= scsi_status;
3060 break;
3061 default:
3062 result |= DID_ERROR << 16;
3063 break;
3064 } /* end of switch */
3065
3066 return result;
3067 }
3068
3069 /**
3070 * ufshcd_transfer_rsp_status - Get overall status of the response
3071 * @hba: per adapter instance
3072 * @lrb: pointer to local reference block of completed command
3073 *
3074 * Returns result of the command to notify SCSI midlayer
3075 */
3076 static inline int
3077 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
3078 {
3079 int result = 0;
3080 int scsi_status;
3081 int ocs;
3082
3083 /* overall command status of utrd */
3084 ocs = ufshcd_get_tr_ocs(lrbp);
3085
3086 switch (ocs) {
3087 case OCS_SUCCESS:
3088 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
3089
3090 switch (result) {
3091 case UPIU_TRANSACTION_RESPONSE:
3092 /*
3093 * get the response UPIU result to extract
3094 * the SCSI command status
3095 */
3096 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
3097
3098 /*
3099 * get the result based on SCSI status response
3100 * to notify the SCSI midlayer of the command status
3101 */
3102 scsi_status = result & MASK_SCSI_STATUS;
3103 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
3104
3105 if (ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
3106 schedule_work(&hba->eeh_work);
3107 break;
3108 case UPIU_TRANSACTION_REJECT_UPIU:
3109 /* TODO: handle Reject UPIU Response */
3110 result = DID_ERROR << 16;
3111 dev_err(hba->dev,
3112 "Reject UPIU not fully implemented\n");
3113 break;
3114 default:
3115 result = DID_ERROR << 16;
3116 dev_err(hba->dev,
3117 "Unexpected request response code = %x\n",
3118 result);
3119 break;
3120 }
3121 break;
3122 case OCS_ABORTED:
3123 result |= DID_ABORT << 16;
3124 break;
3125 case OCS_INVALID_COMMAND_STATUS:
3126 result |= DID_REQUEUE << 16;
3127 break;
3128 case OCS_INVALID_CMD_TABLE_ATTR:
3129 case OCS_INVALID_PRDT_ATTR:
3130 case OCS_MISMATCH_DATA_BUF_SIZE:
3131 case OCS_MISMATCH_RESP_UPIU_SIZE:
3132 case OCS_PEER_COMM_FAILURE:
3133 case OCS_FATAL_ERROR:
3134 default:
3135 result |= DID_ERROR << 16;
3136 dev_err(hba->dev,
3137 "OCS error from controller = %x\n", ocs);
3138 break;
3139 } /* end of switch */
3140
3141 return result;
3142 }
3143
3144 /**
3145 * ufshcd_uic_cmd_compl - handle completion of uic command
3146 * @hba: per adapter instance
3147 * @intr_status: interrupt status generated by the controller
3148 */
3149 static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
3150 {
3151 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
3152 hba->active_uic_cmd->argument2 |=
3153 ufshcd_get_uic_cmd_result(hba);
3154 hba->active_uic_cmd->argument3 =
3155 ufshcd_get_dme_attr_val(hba);
3156 complete(&hba->active_uic_cmd->done);
3157 }
3158
3159 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
3160 complete(hba->uic_async_done);
3161 }
3162
3163 /**
3164 * ufshcd_transfer_req_compl - handle SCSI and query command completion
3165 * @hba: per adapter instance
3166 */
3167 static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
3168 {
3169 struct ufshcd_lrb *lrbp;
3170 struct scsi_cmnd *cmd;
3171 unsigned long completed_reqs;
3172 u32 tr_doorbell;
3173 int result;
3174 int index;
3175 struct request *req;
3176
3177 /* Resetting interrupt aggregation counters first and reading the
3178 * DOOR_BELL afterward allows us to handle all the completed requests.
3179 * In order to prevent other interrupts starvation the DB is read once
3180 * after reset. The down side of this solution is the possibility of
3181 * false interrupt if device completes another request after resetting
3182 * aggregation and before reading the DB.
3183 */
3184 if (ufshcd_is_intr_aggr_allowed(hba))
3185 ufshcd_reset_intr_aggr(hba);
3186
3187 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
3188 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
3189
3190 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
3191 lrbp = &hba->lrb[index];
3192 cmd = lrbp->cmd;
3193 if (cmd) {
3194 result = ufshcd_transfer_rsp_status(hba, lrbp);
3195 scsi_dma_unmap(cmd);
3196 cmd->result = result;
3197 /* Mark completed command as NULL in LRB */
3198 lrbp->cmd = NULL;
3199 clear_bit_unlock(index, &hba->lrb_in_use);
3200 req = cmd->request;
3201 if (req) {
3202 /* Update IO svc time latency histogram */
3203 if (req->lat_hist_enabled) {
3204 ktime_t completion;
3205 u_int64_t delta_us;
3206
3207 completion = ktime_get();
3208 delta_us = ktime_us_delta(completion,
3209 req->lat_hist_io_start);
3210 /* rq_data_dir() => true if WRITE */
3211 blk_update_latency_hist(&hba->io_lat_s,
3212 (rq_data_dir(req) == READ),
3213 delta_us);
3214 }
3215 }
3216 /* Do not touch lrbp after scsi done */
3217 cmd->scsi_done(cmd);
3218 __ufshcd_release(hba);
3219 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE) {
3220 if (hba->dev_cmd.complete)
3221 complete(hba->dev_cmd.complete);
3222 }
3223 }
3224
3225 /* clear corresponding bits of completed commands */
3226 hba->outstanding_reqs ^= completed_reqs;
3227
3228 ufshcd_clk_scaling_update_busy(hba);
3229
3230 /* we might have free'd some tags above */
3231 wake_up(&hba->dev_cmd.tag_wq);
3232 }
3233
3234 /**
3235 * ufshcd_disable_ee - disable exception event
3236 * @hba: per-adapter instance
3237 * @mask: exception event to disable
3238 *
3239 * Disables exception event in the device so that the EVENT_ALERT
3240 * bit is not set.
3241 *
3242 * Returns zero on success, non-zero error value on failure.
3243 */
3244 static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
3245 {
3246 int err = 0;
3247 u32 val;
3248
3249 if (!(hba->ee_ctrl_mask & mask))
3250 goto out;
3251
3252 val = hba->ee_ctrl_mask & ~mask;
3253 val &= 0xFFFF; /* 2 bytes */
3254 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
3255 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
3256 if (!err)
3257 hba->ee_ctrl_mask &= ~mask;
3258 out:
3259 return err;
3260 }
3261
3262 /**
3263 * ufshcd_enable_ee - enable exception event
3264 * @hba: per-adapter instance
3265 * @mask: exception event to enable
3266 *
3267 * Enable corresponding exception event in the device to allow
3268 * device to alert host in critical scenarios.
3269 *
3270 * Returns zero on success, non-zero error value on failure.
3271 */
3272 static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
3273 {
3274 int err = 0;
3275 u32 val;
3276
3277 if (hba->ee_ctrl_mask & mask)
3278 goto out;
3279
3280 val = hba->ee_ctrl_mask | mask;
3281 val &= 0xFFFF; /* 2 bytes */
3282 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
3283 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
3284 if (!err)
3285 hba->ee_ctrl_mask |= mask;
3286 out:
3287 return err;
3288 }
3289
3290 /**
3291 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
3292 * @hba: per-adapter instance
3293 *
3294 * Allow device to manage background operations on its own. Enabling
3295 * this might lead to inconsistent latencies during normal data transfers
3296 * as the device is allowed to manage its own way of handling background
3297 * operations.
3298 *
3299 * Returns zero on success, non-zero on failure.
3300 */
3301 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
3302 {
3303 int err = 0;
3304
3305 if (hba->auto_bkops_enabled)
3306 goto out;
3307
3308 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG,
3309 QUERY_FLAG_IDN_BKOPS_EN, NULL);
3310 if (err) {
3311 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
3312 __func__, err);
3313 goto out;
3314 }
3315
3316 hba->auto_bkops_enabled = true;
3317
3318 /* No need of URGENT_BKOPS exception from the device */
3319 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
3320 if (err)
3321 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
3322 __func__, err);
3323 out:
3324 return err;
3325 }
3326
3327 /**
3328 * ufshcd_disable_auto_bkops - block device in doing background operations
3329 * @hba: per-adapter instance
3330 *
3331 * Disabling background operations improves command response latency but
3332 * has drawback of device moving into critical state where the device is
3333 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
3334 * host is idle so that BKOPS are managed effectively without any negative
3335 * impacts.
3336 *
3337 * Returns zero on success, non-zero on failure.
3338 */
3339 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
3340 {
3341 int err = 0;
3342
3343 if (!hba->auto_bkops_enabled)
3344 goto out;
3345
3346 /*
3347 * If host assisted BKOPs is to be enabled, make sure
3348 * urgent bkops exception is allowed.
3349 */
3350 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
3351 if (err) {
3352 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
3353 __func__, err);
3354 goto out;
3355 }
3356
3357 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
3358 QUERY_FLAG_IDN_BKOPS_EN, NULL);
3359 if (err) {
3360 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
3361 __func__, err);
3362 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
3363 goto out;
3364 }
3365
3366 hba->auto_bkops_enabled = false;
3367 out:
3368 return err;
3369 }
3370
3371 /**
3372 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
3373 * @hba: per adapter instance
3374 *
3375 * After a device reset the device may toggle the BKOPS_EN flag
3376 * to default value. The s/w tracking variables should be updated
3377 * as well. This function would change the auto-bkops state based on
3378 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
3379 */
3380 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
3381 {
3382 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
3383 hba->auto_bkops_enabled = false;
3384 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
3385 ufshcd_enable_auto_bkops(hba);
3386 } else {
3387 hba->auto_bkops_enabled = true;
3388 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
3389 ufshcd_disable_auto_bkops(hba);
3390 }
3391 }
3392
3393 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
3394 {
3395 return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3396 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
3397 }
3398
3399 /**
3400 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
3401 * @hba: per-adapter instance
3402 * @status: bkops_status value
3403 *
3404 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
3405 * flag in the device to permit background operations if the device
3406 * bkops_status is greater than or equal to "status" argument passed to
3407 * this function, disable otherwise.
3408 *
3409 * Returns 0 for success, non-zero in case of failure.
3410 *
3411 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
3412 * to know whether auto bkops is enabled or disabled after this function
3413 * returns control to it.
3414 */
3415 static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
3416 enum bkops_status status)
3417 {
3418 int err;
3419 u32 curr_status = 0;
3420
3421 err = ufshcd_get_bkops_status(hba, &curr_status);
3422 if (err) {
3423 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
3424 __func__, err);
3425 goto out;
3426 } else if (curr_status > BKOPS_STATUS_MAX) {
3427 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
3428 __func__, curr_status);
3429 err = -EINVAL;
3430 goto out;
3431 }
3432
3433 if (curr_status >= status)
3434 err = ufshcd_enable_auto_bkops(hba);
3435 else
3436 err = ufshcd_disable_auto_bkops(hba);
3437 out:
3438 return err;
3439 }
3440
3441 /**
3442 * ufshcd_urgent_bkops - handle urgent bkops exception event
3443 * @hba: per-adapter instance
3444 *
3445 * Enable fBackgroundOpsEn flag in the device to permit background
3446 * operations.
3447 *
3448 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
3449 * and negative error value for any other failure.
3450 */
3451 static int ufshcd_urgent_bkops(struct ufs_hba *hba)
3452 {
3453 return ufshcd_bkops_ctrl(hba, BKOPS_STATUS_PERF_IMPACT);
3454 }
3455
3456 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
3457 {
3458 return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3459 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
3460 }
3461
3462 /**
3463 * ufshcd_exception_event_handler - handle exceptions raised by device
3464 * @work: pointer to work data
3465 *
3466 * Read bExceptionEventStatus attribute from the device and handle the
3467 * exception event accordingly.
3468 */
3469 static void ufshcd_exception_event_handler(struct work_struct *work)
3470 {
3471 struct ufs_hba *hba;
3472 int err;
3473 u32 status = 0;
3474 hba = container_of(work, struct ufs_hba, eeh_work);
3475
3476 pm_runtime_get_sync(hba->dev);
3477 err = ufshcd_get_ee_status(hba, &status);
3478 if (err) {
3479 dev_err(hba->dev, "%s: failed to get exception status %d\n",
3480 __func__, err);
3481 goto out;
3482 }
3483
3484 status &= hba->ee_ctrl_mask;
3485 if (status & MASK_EE_URGENT_BKOPS) {
3486 err = ufshcd_urgent_bkops(hba);
3487 if (err < 0)
3488 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
3489 __func__, err);
3490 }
3491 out:
3492 pm_runtime_put_sync(hba->dev);
3493 return;
3494 }
3495
3496 /**
3497 * ufshcd_err_handler - handle UFS errors that require s/w attention
3498 * @work: pointer to work structure
3499 */
3500 static void ufshcd_err_handler(struct work_struct *work)
3501 {
3502 struct ufs_hba *hba;
3503 unsigned long flags;
3504 u32 err_xfer = 0;
3505 u32 err_tm = 0;
3506 int err = 0;
3507 int tag;
3508
3509 hba = container_of(work, struct ufs_hba, eh_work);
3510
3511 pm_runtime_get_sync(hba->dev);
3512 ufshcd_hold(hba, false);
3513
3514 spin_lock_irqsave(hba->host->host_lock, flags);
3515 if (hba->ufshcd_state == UFSHCD_STATE_RESET) {
3516 spin_unlock_irqrestore(hba->host->host_lock, flags);
3517 goto out;
3518 }
3519
3520 hba->ufshcd_state = UFSHCD_STATE_RESET;
3521 ufshcd_set_eh_in_progress(hba);
3522
3523 /* Complete requests that have door-bell cleared by h/w */
3524 ufshcd_transfer_req_compl(hba);
3525 ufshcd_tmc_handler(hba);
3526 spin_unlock_irqrestore(hba->host->host_lock, flags);
3527
3528 /* Clear pending transfer requests */
3529 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs)
3530 if (ufshcd_clear_cmd(hba, tag))
3531 err_xfer |= 1 << tag;
3532
3533 /* Clear pending task management requests */
3534 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs)
3535 if (ufshcd_clear_tm_cmd(hba, tag))
3536 err_tm |= 1 << tag;
3537
3538 /* Complete the requests that are cleared by s/w */
3539 spin_lock_irqsave(hba->host->host_lock, flags);
3540 ufshcd_transfer_req_compl(hba);
3541 ufshcd_tmc_handler(hba);
3542 spin_unlock_irqrestore(hba->host->host_lock, flags);
3543
3544 /* Fatal errors need reset */
3545 if (err_xfer || err_tm || (hba->saved_err & INT_FATAL_ERRORS) ||
3546 ((hba->saved_err & UIC_ERROR) &&
3547 (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR))) {
3548 err = ufshcd_reset_and_restore(hba);
3549 if (err) {
3550 dev_err(hba->dev, "%s: reset and restore failed\n",
3551 __func__);
3552 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3553 }
3554 /*
3555 * Inform scsi mid-layer that we did reset and allow to handle
3556 * Unit Attention properly.
3557 */
3558 scsi_report_bus_reset(hba->host, 0);
3559 hba->saved_err = 0;
3560 hba->saved_uic_err = 0;
3561 }
3562 ufshcd_clear_eh_in_progress(hba);
3563
3564 out:
3565 scsi_unblock_requests(hba->host);
3566 ufshcd_release(hba);
3567 pm_runtime_put_sync(hba->dev);
3568 }
3569
3570 /**
3571 * ufshcd_update_uic_error - check and set fatal UIC error flags.
3572 * @hba: per-adapter instance
3573 */
3574 static void ufshcd_update_uic_error(struct ufs_hba *hba)
3575 {
3576 u32 reg;
3577
3578 /* PA_INIT_ERROR is fatal and needs UIC reset */
3579 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
3580 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
3581 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
3582
3583 /* UIC NL/TL/DME errors needs software retry */
3584 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
3585 if (reg)
3586 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
3587
3588 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
3589 if (reg)
3590 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
3591
3592 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
3593 if (reg)
3594 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
3595
3596 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
3597 __func__, hba->uic_error);
3598 }
3599
3600 /**
3601 * ufshcd_check_errors - Check for errors that need s/w attention
3602 * @hba: per-adapter instance
3603 */
3604 static void ufshcd_check_errors(struct ufs_hba *hba)
3605 {
3606 bool queue_eh_work = false;
3607
3608 if (hba->errors & INT_FATAL_ERRORS)
3609 queue_eh_work = true;
3610
3611 if (hba->errors & UIC_ERROR) {
3612 hba->uic_error = 0;
3613 ufshcd_update_uic_error(hba);
3614 if (hba->uic_error)
3615 queue_eh_work = true;
3616 }
3617
3618 if (queue_eh_work) {
3619 /* handle fatal errors only when link is functional */
3620 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
3621 /* block commands from scsi mid-layer */
3622 scsi_block_requests(hba->host);
3623
3624 /* transfer error masks to sticky bits */
3625 hba->saved_err |= hba->errors;
3626 hba->saved_uic_err |= hba->uic_error;
3627
3628 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3629 schedule_work(&hba->eh_work);
3630 }
3631 }
3632 /*
3633 * if (!queue_eh_work) -
3634 * Other errors are either non-fatal where host recovers
3635 * itself without s/w intervention or errors that will be
3636 * handled by the SCSI core layer.
3637 */
3638 }
3639
3640 /**
3641 * ufshcd_tmc_handler - handle task management function completion
3642 * @hba: per adapter instance
3643 */
3644 static void ufshcd_tmc_handler(struct ufs_hba *hba)
3645 {
3646 u32 tm_doorbell;
3647
3648 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
3649 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
3650 wake_up(&hba->tm_wq);
3651 }
3652
3653 /**
3654 * ufshcd_sl_intr - Interrupt service routine
3655 * @hba: per adapter instance
3656 * @intr_status: contains interrupts generated by the controller
3657 */
3658 static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
3659 {
3660 hba->errors = UFSHCD_ERROR_MASK & intr_status;
3661 if (hba->errors)
3662 ufshcd_check_errors(hba);
3663
3664 if (intr_status & UFSHCD_UIC_MASK)
3665 ufshcd_uic_cmd_compl(hba, intr_status);
3666
3667 if (intr_status & UTP_TASK_REQ_COMPL)
3668 ufshcd_tmc_handler(hba);
3669
3670 if (intr_status & UTP_TRANSFER_REQ_COMPL)
3671 ufshcd_transfer_req_compl(hba);
3672 }
3673
3674 /**
3675 * ufshcd_intr - Main interrupt service routine
3676 * @irq: irq number
3677 * @__hba: pointer to adapter instance
3678 *
3679 * Returns IRQ_HANDLED - If interrupt is valid
3680 * IRQ_NONE - If invalid interrupt
3681 */
3682 static irqreturn_t ufshcd_intr(int irq, void *__hba)
3683 {
3684 u32 intr_status;
3685 irqreturn_t retval = IRQ_NONE;
3686 struct ufs_hba *hba = __hba;
3687
3688 spin_lock(hba->host->host_lock);
3689 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
3690
3691 if (intr_status) {
3692 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
3693 ufshcd_sl_intr(hba, intr_status);
3694 retval = IRQ_HANDLED;
3695 }
3696 spin_unlock(hba->host->host_lock);
3697 return retval;
3698 }
3699
3700 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
3701 {
3702 int err = 0;
3703 u32 mask = 1 << tag;
3704 unsigned long flags;
3705
3706 if (!test_bit(tag, &hba->outstanding_tasks))
3707 goto out;
3708
3709 spin_lock_irqsave(hba->host->host_lock, flags);
3710 ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
3711 spin_unlock_irqrestore(hba->host->host_lock, flags);
3712
3713 /* poll for max. 1 sec to clear door bell register by h/w */
3714 err = ufshcd_wait_for_register(hba,
3715 REG_UTP_TASK_REQ_DOOR_BELL,
3716 mask, 0, 1000, 1000);
3717 out:
3718 return err;
3719 }
3720
3721 /**
3722 * ufshcd_issue_tm_cmd - issues task management commands to controller
3723 * @hba: per adapter instance
3724 * @lun_id: LUN ID to which TM command is sent
3725 * @task_id: task ID to which the TM command is applicable
3726 * @tm_function: task management function opcode
3727 * @tm_response: task management service response return value
3728 *
3729 * Returns non-zero value on error, zero on success.
3730 */
3731 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
3732 u8 tm_function, u8 *tm_response)
3733 {
3734 struct utp_task_req_desc *task_req_descp;
3735 struct utp_upiu_task_req *task_req_upiup;
3736 struct Scsi_Host *host;
3737 unsigned long flags;
3738 int free_slot;
3739 int err;
3740 int task_tag;
3741
3742 host = hba->host;
3743
3744 /*
3745 * Get free slot, sleep if slots are unavailable.
3746 * Even though we use wait_event() which sleeps indefinitely,
3747 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
3748 */
3749 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
3750 ufshcd_hold(hba, false);
3751
3752 spin_lock_irqsave(host->host_lock, flags);
3753 task_req_descp = hba->utmrdl_base_addr;
3754 task_req_descp += free_slot;
3755
3756 /* Configure task request descriptor */
3757 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
3758 task_req_descp->header.dword_2 =
3759 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
3760
3761 /* Configure task request UPIU */
3762 task_req_upiup =
3763 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
3764 task_tag = hba->nutrs + free_slot;
3765 task_req_upiup->header.dword_0 =
3766 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
3767 lun_id, task_tag);
3768 task_req_upiup->header.dword_1 =
3769 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
3770 /*
3771 * The host shall provide the same value for LUN field in the basic
3772 * header and for Input Parameter.
3773 */
3774 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
3775 task_req_upiup->input_param2 = cpu_to_be32(task_id);
3776
3777 /* send command to the controller */
3778 __set_bit(free_slot, &hba->outstanding_tasks);
3779 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
3780
3781 spin_unlock_irqrestore(host->host_lock, flags);
3782
3783 /* wait until the task management command is completed */
3784 err = wait_event_timeout(hba->tm_wq,
3785 test_bit(free_slot, &hba->tm_condition),
3786 msecs_to_jiffies(TM_CMD_TIMEOUT));
3787 if (!err) {
3788 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
3789 __func__, tm_function);
3790 if (ufshcd_clear_tm_cmd(hba, free_slot))
3791 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
3792 __func__, free_slot);
3793 err = -ETIMEDOUT;
3794 } else {
3795 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
3796 }
3797
3798 clear_bit(free_slot, &hba->tm_condition);
3799 ufshcd_put_tm_slot(hba, free_slot);
3800 wake_up(&hba->tm_tag_wq);
3801
3802 ufshcd_release(hba);
3803 return err;
3804 }
3805
3806 /**
3807 * ufshcd_eh_device_reset_handler - device reset handler registered to
3808 * scsi layer.
3809 * @cmd: SCSI command pointer
3810 *
3811 * Returns SUCCESS/FAILED
3812 */
3813 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
3814 {
3815 struct Scsi_Host *host;
3816 struct ufs_hba *hba;
3817 unsigned int tag;
3818 u32 pos;
3819 int err;
3820 u8 resp = 0xF;
3821 struct ufshcd_lrb *lrbp;
3822 unsigned long flags;
3823
3824 host = cmd->device->host;
3825 hba = shost_priv(host);
3826 tag = cmd->request->tag;
3827
3828 lrbp = &hba->lrb[tag];
3829 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
3830 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3831 if (!err)
3832 err = resp;
3833 goto out;
3834 }
3835
3836 /* clear the commands that were pending for corresponding LUN */
3837 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
3838 if (hba->lrb[pos].lun == lrbp->lun) {
3839 err = ufshcd_clear_cmd(hba, pos);
3840 if (err)
3841 break;
3842 }
3843 }
3844 spin_lock_irqsave(host->host_lock, flags);
3845 ufshcd_transfer_req_compl(hba);
3846 spin_unlock_irqrestore(host->host_lock, flags);
3847 out:
3848 if (!err) {
3849 err = SUCCESS;
3850 } else {
3851 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
3852 err = FAILED;
3853 }
3854 return err;
3855 }
3856
3857 /**
3858 * ufshcd_abort - abort a specific command
3859 * @cmd: SCSI command pointer
3860 *
3861 * Abort the pending command in device by sending UFS_ABORT_TASK task management
3862 * command, and in host controller by clearing the door-bell register. There can
3863 * be race between controller sending the command to the device while abort is
3864 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
3865 * really issued and then try to abort it.
3866 *
3867 * Returns SUCCESS/FAILED
3868 */
3869 static int ufshcd_abort(struct scsi_cmnd *cmd)
3870 {
3871 struct Scsi_Host *host;
3872 struct ufs_hba *hba;
3873 unsigned long flags;
3874 unsigned int tag;
3875 int err = 0;
3876 int poll_cnt;
3877 u8 resp = 0xF;
3878 struct ufshcd_lrb *lrbp;
3879 u32 reg;
3880
3881 host = cmd->device->host;
3882 hba = shost_priv(host);
3883 tag = cmd->request->tag;
3884
3885 ufshcd_hold(hba, false);
3886 /* If command is already aborted/completed, return SUCCESS */
3887 if (!(test_bit(tag, &hba->outstanding_reqs)))
3888 goto out;
3889
3890 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
3891 if (!(reg & (1 << tag))) {
3892 dev_err(hba->dev,
3893 "%s: cmd was completed, but without a notifying intr, tag = %d",
3894 __func__, tag);
3895 }
3896
3897 lrbp = &hba->lrb[tag];
3898 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
3899 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
3900 UFS_QUERY_TASK, &resp);
3901 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
3902 /* cmd pending in the device */
3903 break;
3904 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3905 /*
3906 * cmd not pending in the device, check if it is
3907 * in transition.
3908 */
3909 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
3910 if (reg & (1 << tag)) {
3911 /* sleep for max. 200us to stabilize */
3912 usleep_range(100, 200);
3913 continue;
3914 }
3915 /* command completed already */
3916 goto out;
3917 } else {
3918 if (!err)
3919 err = resp; /* service response error */
3920 goto out;
3921 }
3922 }
3923
3924 if (!poll_cnt) {
3925 err = -EBUSY;
3926 goto out;
3927 }
3928
3929 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
3930 UFS_ABORT_TASK, &resp);
3931 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3932 if (!err)
3933 err = resp; /* service response error */
3934 goto out;
3935 }
3936
3937 err = ufshcd_clear_cmd(hba, tag);
3938 if (err)
3939 goto out;
3940
3941 scsi_dma_unmap(cmd);
3942
3943 spin_lock_irqsave(host->host_lock, flags);
3944 __clear_bit(tag, &hba->outstanding_reqs);
3945 hba->lrb[tag].cmd = NULL;
3946 spin_unlock_irqrestore(host->host_lock, flags);
3947
3948 clear_bit_unlock(tag, &hba->lrb_in_use);
3949 wake_up(&hba->dev_cmd.tag_wq);
3950
3951 out:
3952 if (!err) {
3953 err = SUCCESS;
3954 } else {
3955 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
3956 err = FAILED;
3957 }
3958
3959 /*
3960 * This ufshcd_release() corresponds to the original scsi cmd that got
3961 * aborted here (as we won't get any IRQ for it).
3962 */
3963 ufshcd_release(hba);
3964 return err;
3965 }
3966
3967 /**
3968 * ufshcd_host_reset_and_restore - reset and restore host controller
3969 * @hba: per-adapter instance
3970 *
3971 * Note that host controller reset may issue DME_RESET to
3972 * local and remote (device) Uni-Pro stack and the attributes
3973 * are reset to default state.
3974 *
3975 * Returns zero on success, non-zero on failure
3976 */
3977 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
3978 {
3979 int err;
3980 unsigned long flags;
3981
3982 /* Reset the host controller */
3983 spin_lock_irqsave(hba->host->host_lock, flags);
3984 ufshcd_hba_stop(hba);
3985 spin_unlock_irqrestore(hba->host->host_lock, flags);
3986
3987 err = ufshcd_hba_enable(hba);
3988 if (err)
3989 goto out;
3990
3991 /* Establish the link again and restore the device */
3992 err = ufshcd_probe_hba(hba);
3993
3994 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3995 err = -EIO;
3996 out:
3997 if (err)
3998 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
3999
4000 return err;
4001 }
4002
4003 /**
4004 * ufshcd_reset_and_restore - reset and re-initialize host/device
4005 * @hba: per-adapter instance
4006 *
4007 * Reset and recover device, host and re-establish link. This
4008 * is helpful to recover the communication in fatal error conditions.
4009 *
4010 * Returns zero on success, non-zero on failure
4011 */
4012 static int ufshcd_reset_and_restore(struct ufs_hba *hba)
4013 {
4014 int err = 0;
4015 unsigned long flags;
4016 int retries = MAX_HOST_RESET_RETRIES;
4017
4018 do {
4019 err = ufshcd_host_reset_and_restore(hba);
4020 } while (err && --retries);
4021
4022 /*
4023 * After reset the door-bell might be cleared, complete
4024 * outstanding requests in s/w here.
4025 */
4026 spin_lock_irqsave(hba->host->host_lock, flags);
4027 ufshcd_transfer_req_compl(hba);
4028 ufshcd_tmc_handler(hba);
4029 spin_unlock_irqrestore(hba->host->host_lock, flags);
4030
4031 return err;
4032 }
4033
4034 /**
4035 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
4036 * @cmd - SCSI command pointer
4037 *
4038 * Returns SUCCESS/FAILED
4039 */
4040 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
4041 {
4042 int err;
4043 unsigned long flags;
4044 struct ufs_hba *hba;
4045
4046 hba = shost_priv(cmd->device->host);
4047
4048 ufshcd_hold(hba, false);
4049 /*
4050 * Check if there is any race with fatal error handling.
4051 * If so, wait for it to complete. Even though fatal error
4052 * handling does reset and restore in some cases, don't assume
4053 * anything out of it. We are just avoiding race here.
4054 */
4055 do {
4056 spin_lock_irqsave(hba->host->host_lock, flags);
4057 if (!(work_pending(&hba->eh_work) ||
4058 hba->ufshcd_state == UFSHCD_STATE_RESET))
4059 break;
4060 spin_unlock_irqrestore(hba->host->host_lock, flags);
4061 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
4062 flush_work(&hba->eh_work);
4063 } while (1);
4064
4065 hba->ufshcd_state = UFSHCD_STATE_RESET;
4066 ufshcd_set_eh_in_progress(hba);
4067 spin_unlock_irqrestore(hba->host->host_lock, flags);
4068
4069 err = ufshcd_reset_and_restore(hba);
4070
4071 spin_lock_irqsave(hba->host->host_lock, flags);
4072 if (!err) {
4073 err = SUCCESS;
4074 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
4075 } else {
4076 err = FAILED;
4077 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4078 }
4079 ufshcd_clear_eh_in_progress(hba);
4080 spin_unlock_irqrestore(hba->host->host_lock, flags);
4081
4082 ufshcd_release(hba);
4083 return err;
4084 }
4085
4086 /**
4087 * ufshcd_get_max_icc_level - calculate the ICC level
4088 * @sup_curr_uA: max. current supported by the regulator
4089 * @start_scan: row at the desc table to start scan from
4090 * @buff: power descriptor buffer
4091 *
4092 * Returns calculated max ICC level for specific regulator
4093 */
4094 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
4095 {
4096 int i;
4097 int curr_uA;
4098 u16 data;
4099 u16 unit;
4100
4101 for (i = start_scan; i >= 0; i--) {
4102 data = be16_to_cpu(*((u16 *)(buff + 2*i)));
4103 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
4104 ATTR_ICC_LVL_UNIT_OFFSET;
4105 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
4106 switch (unit) {
4107 case UFSHCD_NANO_AMP:
4108 curr_uA = curr_uA / 1000;
4109 break;
4110 case UFSHCD_MILI_AMP:
4111 curr_uA = curr_uA * 1000;
4112 break;
4113 case UFSHCD_AMP:
4114 curr_uA = curr_uA * 1000 * 1000;
4115 break;
4116 case UFSHCD_MICRO_AMP:
4117 default:
4118 break;
4119 }
4120 if (sup_curr_uA >= curr_uA)
4121 break;
4122 }
4123 if (i < 0) {
4124 i = 0;
4125 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
4126 }
4127
4128 return (u32)i;
4129 }
4130
4131 /**
4132 * ufshcd_calc_icc_level - calculate the max ICC level
4133 * In case regulators are not initialized we'll return 0
4134 * @hba: per-adapter instance
4135 * @desc_buf: power descriptor buffer to extract ICC levels from.
4136 * @len: length of desc_buff
4137 *
4138 * Returns calculated ICC level
4139 */
4140 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
4141 u8 *desc_buf, int len)
4142 {
4143 u32 icc_level = 0;
4144
4145 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
4146 !hba->vreg_info.vccq2) {
4147 dev_err(hba->dev,
4148 "%s: Regulator capability was not set, actvIccLevel=%d",
4149 __func__, icc_level);
4150 goto out;
4151 }
4152
4153 if (hba->vreg_info.vcc)
4154 icc_level = ufshcd_get_max_icc_level(
4155 hba->vreg_info.vcc->max_uA,
4156 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
4157 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
4158
4159 if (hba->vreg_info.vccq)
4160 icc_level = ufshcd_get_max_icc_level(
4161 hba->vreg_info.vccq->max_uA,
4162 icc_level,
4163 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
4164
4165 if (hba->vreg_info.vccq2)
4166 icc_level = ufshcd_get_max_icc_level(
4167 hba->vreg_info.vccq2->max_uA,
4168 icc_level,
4169 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
4170 out:
4171 return icc_level;
4172 }
4173
4174 static void ufshcd_init_icc_levels(struct ufs_hba *hba)
4175 {
4176 int ret;
4177 int buff_len = QUERY_DESC_POWER_MAX_SIZE;
4178 u8 desc_buf[QUERY_DESC_POWER_MAX_SIZE];
4179
4180 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
4181 if (ret) {
4182 dev_err(hba->dev,
4183 "%s: Failed reading power descriptor.len = %d ret = %d",
4184 __func__, buff_len, ret);
4185 return;
4186 }
4187
4188 hba->init_prefetch_data.icc_level =
4189 ufshcd_find_max_sup_active_icc_level(hba,
4190 desc_buf, buff_len);
4191 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
4192 __func__, hba->init_prefetch_data.icc_level);
4193
4194 ret = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
4195 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
4196 &hba->init_prefetch_data.icc_level);
4197
4198 if (ret)
4199 dev_err(hba->dev,
4200 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
4201 __func__, hba->init_prefetch_data.icc_level , ret);
4202
4203 }
4204
4205 /**
4206 * ufshcd_scsi_add_wlus - Adds required W-LUs
4207 * @hba: per-adapter instance
4208 *
4209 * UFS device specification requires the UFS devices to support 4 well known
4210 * logical units:
4211 * "REPORT_LUNS" (address: 01h)
4212 * "UFS Device" (address: 50h)
4213 * "RPMB" (address: 44h)
4214 * "BOOT" (address: 30h)
4215 * UFS device's power management needs to be controlled by "POWER CONDITION"
4216 * field of SSU (START STOP UNIT) command. But this "power condition" field
4217 * will take effect only when its sent to "UFS device" well known logical unit
4218 * hence we require the scsi_device instance to represent this logical unit in
4219 * order for the UFS host driver to send the SSU command for power management.
4220
4221 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
4222 * Block) LU so user space process can control this LU. User space may also
4223 * want to have access to BOOT LU.
4224
4225 * This function adds scsi device instances for each of all well known LUs
4226 * (except "REPORT LUNS" LU).
4227 *
4228 * Returns zero on success (all required W-LUs are added successfully),
4229 * non-zero error value on failure (if failed to add any of the required W-LU).
4230 */
4231 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
4232 {
4233 int ret = 0;
4234 struct scsi_device *sdev_rpmb;
4235 struct scsi_device *sdev_boot;
4236
4237 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
4238 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
4239 if (IS_ERR(hba->sdev_ufs_device)) {
4240 ret = PTR_ERR(hba->sdev_ufs_device);
4241 hba->sdev_ufs_device = NULL;
4242 goto out;
4243 }
4244 scsi_device_put(hba->sdev_ufs_device);
4245
4246 sdev_boot = __scsi_add_device(hba->host, 0, 0,
4247 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
4248 if (IS_ERR(sdev_boot)) {
4249 ret = PTR_ERR(sdev_boot);
4250 goto remove_sdev_ufs_device;
4251 }
4252 scsi_device_put(sdev_boot);
4253
4254 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
4255 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
4256 if (IS_ERR(sdev_rpmb)) {
4257 ret = PTR_ERR(sdev_rpmb);
4258 goto remove_sdev_boot;
4259 }
4260 scsi_device_put(sdev_rpmb);
4261 goto out;
4262
4263 remove_sdev_boot:
4264 scsi_remove_device(sdev_boot);
4265 remove_sdev_ufs_device:
4266 scsi_remove_device(hba->sdev_ufs_device);
4267 out:
4268 return ret;
4269 }
4270
4271 /**
4272 * ufshcd_probe_hba - probe hba to detect device and initialize
4273 * @hba: per-adapter instance
4274 *
4275 * Execute link-startup and verify device initialization
4276 */
4277 static int ufshcd_probe_hba(struct ufs_hba *hba)
4278 {
4279 int ret;
4280
4281 ret = ufshcd_link_startup(hba);
4282 if (ret)
4283 goto out;
4284
4285 ufshcd_init_pwr_info(hba);
4286
4287 /* UniPro link is active now */
4288 ufshcd_set_link_active(hba);
4289
4290 ret = ufshcd_verify_dev_init(hba);
4291 if (ret)
4292 goto out;
4293
4294 ret = ufshcd_complete_dev_init(hba);
4295 if (ret)
4296 goto out;
4297
4298 /* UFS device is also active now */
4299 ufshcd_set_ufs_dev_active(hba);
4300 ufshcd_force_reset_auto_bkops(hba);
4301 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
4302 hba->wlun_dev_clr_ua = true;
4303
4304 if (ufshcd_get_max_pwr_mode(hba)) {
4305 dev_err(hba->dev,
4306 "%s: Failed getting max supported power mode\n",
4307 __func__);
4308 } else {
4309 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
4310 if (ret)
4311 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
4312 __func__, ret);
4313 }
4314
4315 /*
4316 * If we are in error handling context or in power management callbacks
4317 * context, no need to scan the host
4318 */
4319 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
4320 bool flag;
4321
4322 /* clear any previous UFS device information */
4323 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
4324 if (!ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4325 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
4326 hba->dev_info.f_power_on_wp_en = flag;
4327
4328 if (!hba->is_init_prefetch)
4329 ufshcd_init_icc_levels(hba);
4330
4331 /* Add required well known logical units to scsi mid layer */
4332 if (ufshcd_scsi_add_wlus(hba))
4333 goto out;
4334
4335 scsi_scan_host(hba->host);
4336 pm_runtime_put_sync(hba->dev);
4337 }
4338
4339 if (!hba->is_init_prefetch)
4340 hba->is_init_prefetch = true;
4341
4342 /* Resume devfreq after UFS device is detected */
4343 if (ufshcd_is_clkscaling_enabled(hba))
4344 devfreq_resume_device(hba->devfreq);
4345
4346 out:
4347 /*
4348 * If we failed to initialize the device or the device is not
4349 * present, turn off the power/clocks etc.
4350 */
4351 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
4352 pm_runtime_put_sync(hba->dev);
4353 ufshcd_hba_exit(hba);
4354 }
4355
4356 return ret;
4357 }
4358
4359 /**
4360 * ufshcd_async_scan - asynchronous execution for probing hba
4361 * @data: data pointer to pass to this function
4362 * @cookie: cookie data
4363 */
4364 static void ufshcd_async_scan(void *data, async_cookie_t cookie)
4365 {
4366 struct ufs_hba *hba = (struct ufs_hba *)data;
4367
4368 ufshcd_probe_hba(hba);
4369 }
4370
4371 static struct scsi_host_template ufshcd_driver_template = {
4372 .module = THIS_MODULE,
4373 .name = UFSHCD,
4374 .proc_name = UFSHCD,
4375 .queuecommand = ufshcd_queuecommand,
4376 .slave_alloc = ufshcd_slave_alloc,
4377 .slave_configure = ufshcd_slave_configure,
4378 .slave_destroy = ufshcd_slave_destroy,
4379 .change_queue_depth = ufshcd_change_queue_depth,
4380 .eh_abort_handler = ufshcd_abort,
4381 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
4382 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
4383 .this_id = -1,
4384 .sg_tablesize = SG_ALL,
4385 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
4386 .can_queue = UFSHCD_CAN_QUEUE,
4387 .max_host_blocked = 1,
4388 .track_queue_depth = 1,
4389 };
4390
4391 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
4392 int ua)
4393 {
4394 int ret;
4395
4396 if (!vreg)
4397 return 0;
4398
4399 ret = regulator_set_load(vreg->reg, ua);
4400 if (ret < 0) {
4401 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
4402 __func__, vreg->name, ua, ret);
4403 }
4404
4405 return ret;
4406 }
4407
4408 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
4409 struct ufs_vreg *vreg)
4410 {
4411 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
4412 }
4413
4414 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
4415 struct ufs_vreg *vreg)
4416 {
4417 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
4418 }
4419
4420 static int ufshcd_config_vreg(struct device *dev,
4421 struct ufs_vreg *vreg, bool on)
4422 {
4423 int ret = 0;
4424 struct regulator *reg = vreg->reg;
4425 const char *name = vreg->name;
4426 int min_uV, uA_load;
4427
4428 BUG_ON(!vreg);
4429
4430 if (regulator_count_voltages(reg) > 0) {
4431 min_uV = on ? vreg->min_uV : 0;
4432 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
4433 if (ret) {
4434 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
4435 __func__, name, ret);
4436 goto out;
4437 }
4438
4439 uA_load = on ? vreg->max_uA : 0;
4440 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
4441 if (ret)
4442 goto out;
4443 }
4444 out:
4445 return ret;
4446 }
4447
4448 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
4449 {
4450 int ret = 0;
4451
4452 if (!vreg || vreg->enabled)
4453 goto out;
4454
4455 ret = ufshcd_config_vreg(dev, vreg, true);
4456 if (!ret)
4457 ret = regulator_enable(vreg->reg);
4458
4459 if (!ret)
4460 vreg->enabled = true;
4461 else
4462 dev_err(dev, "%s: %s enable failed, err=%d\n",
4463 __func__, vreg->name, ret);
4464 out:
4465 return ret;
4466 }
4467
4468 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
4469 {
4470 int ret = 0;
4471
4472 if (!vreg || !vreg->enabled)
4473 goto out;
4474
4475 ret = regulator_disable(vreg->reg);
4476
4477 if (!ret) {
4478 /* ignore errors on applying disable config */
4479 ufshcd_config_vreg(dev, vreg, false);
4480 vreg->enabled = false;
4481 } else {
4482 dev_err(dev, "%s: %s disable failed, err=%d\n",
4483 __func__, vreg->name, ret);
4484 }
4485 out:
4486 return ret;
4487 }
4488
4489 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
4490 {
4491 int ret = 0;
4492 struct device *dev = hba->dev;
4493 struct ufs_vreg_info *info = &hba->vreg_info;
4494
4495 if (!info)
4496 goto out;
4497
4498 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
4499 if (ret)
4500 goto out;
4501
4502 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
4503 if (ret)
4504 goto out;
4505
4506 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
4507 if (ret)
4508 goto out;
4509
4510 out:
4511 if (ret) {
4512 ufshcd_toggle_vreg(dev, info->vccq2, false);
4513 ufshcd_toggle_vreg(dev, info->vccq, false);
4514 ufshcd_toggle_vreg(dev, info->vcc, false);
4515 }
4516 return ret;
4517 }
4518
4519 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
4520 {
4521 struct ufs_vreg_info *info = &hba->vreg_info;
4522
4523 if (info)
4524 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
4525
4526 return 0;
4527 }
4528
4529 static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
4530 {
4531 int ret = 0;
4532
4533 if (!vreg)
4534 goto out;
4535
4536 vreg->reg = devm_regulator_get(dev, vreg->name);
4537 if (IS_ERR(vreg->reg)) {
4538 ret = PTR_ERR(vreg->reg);
4539 dev_err(dev, "%s: %s get failed, err=%d\n",
4540 __func__, vreg->name, ret);
4541 }
4542 out:
4543 return ret;
4544 }
4545
4546 static int ufshcd_init_vreg(struct ufs_hba *hba)
4547 {
4548 int ret = 0;
4549 struct device *dev = hba->dev;
4550 struct ufs_vreg_info *info = &hba->vreg_info;
4551
4552 if (!info)
4553 goto out;
4554
4555 ret = ufshcd_get_vreg(dev, info->vcc);
4556 if (ret)
4557 goto out;
4558
4559 ret = ufshcd_get_vreg(dev, info->vccq);
4560 if (ret)
4561 goto out;
4562
4563 ret = ufshcd_get_vreg(dev, info->vccq2);
4564 out:
4565 return ret;
4566 }
4567
4568 static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
4569 {
4570 struct ufs_vreg_info *info = &hba->vreg_info;
4571
4572 if (info)
4573 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
4574
4575 return 0;
4576 }
4577
4578 static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
4579 bool skip_ref_clk)
4580 {
4581 int ret = 0;
4582 struct ufs_clk_info *clki;
4583 struct list_head *head = &hba->clk_list_head;
4584 unsigned long flags;
4585
4586 if (!head || list_empty(head))
4587 goto out;
4588
4589 list_for_each_entry(clki, head, list) {
4590 if (!IS_ERR_OR_NULL(clki->clk)) {
4591 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
4592 continue;
4593
4594 if (on && !clki->enabled) {
4595 ret = clk_prepare_enable(clki->clk);
4596 if (ret) {
4597 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
4598 __func__, clki->name, ret);
4599 goto out;
4600 }
4601 } else if (!on && clki->enabled) {
4602 clk_disable_unprepare(clki->clk);
4603 }
4604 clki->enabled = on;
4605 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
4606 clki->name, on ? "en" : "dis");
4607 }
4608 }
4609
4610 ret = ufshcd_vops_setup_clocks(hba, on);
4611 out:
4612 if (ret) {
4613 list_for_each_entry(clki, head, list) {
4614 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
4615 clk_disable_unprepare(clki->clk);
4616 }
4617 } else if (on) {
4618 spin_lock_irqsave(hba->host->host_lock, flags);
4619 hba->clk_gating.state = CLKS_ON;
4620 spin_unlock_irqrestore(hba->host->host_lock, flags);
4621 }
4622 return ret;
4623 }
4624
4625 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
4626 {
4627 return __ufshcd_setup_clocks(hba, on, false);
4628 }
4629
4630 static int ufshcd_init_clocks(struct ufs_hba *hba)
4631 {
4632 int ret = 0;
4633 struct ufs_clk_info *clki;
4634 struct device *dev = hba->dev;
4635 struct list_head *head = &hba->clk_list_head;
4636
4637 if (!head || list_empty(head))
4638 goto out;
4639
4640 list_for_each_entry(clki, head, list) {
4641 if (!clki->name)
4642 continue;
4643
4644 clki->clk = devm_clk_get(dev, clki->name);
4645 if (IS_ERR(clki->clk)) {
4646 ret = PTR_ERR(clki->clk);
4647 dev_err(dev, "%s: %s clk get failed, %d\n",
4648 __func__, clki->name, ret);
4649 goto out;
4650 }
4651
4652 if (clki->max_freq) {
4653 ret = clk_set_rate(clki->clk, clki->max_freq);
4654 if (ret) {
4655 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
4656 __func__, clki->name,
4657 clki->max_freq, ret);
4658 goto out;
4659 }
4660 clki->curr_freq = clki->max_freq;
4661 }
4662 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
4663 clki->name, clk_get_rate(clki->clk));
4664 }
4665 out:
4666 return ret;
4667 }
4668
4669 static int ufshcd_variant_hba_init(struct ufs_hba *hba)
4670 {
4671 int err = 0;
4672
4673 if (!hba->vops)
4674 goto out;
4675
4676 err = ufshcd_vops_init(hba);
4677 if (err)
4678 goto out;
4679
4680 err = ufshcd_vops_setup_regulators(hba, true);
4681 if (err)
4682 goto out_exit;
4683
4684 goto out;
4685
4686 out_exit:
4687 ufshcd_vops_exit(hba);
4688 out:
4689 if (err)
4690 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
4691 __func__, ufshcd_get_var_name(hba), err);
4692 return err;
4693 }
4694
4695 static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
4696 {
4697 if (!hba->vops)
4698 return;
4699
4700 ufshcd_vops_setup_clocks(hba, false);
4701
4702 ufshcd_vops_setup_regulators(hba, false);
4703
4704 ufshcd_vops_exit(hba);
4705 }
4706
4707 static int ufshcd_hba_init(struct ufs_hba *hba)
4708 {
4709 int err;
4710
4711 /*
4712 * Handle host controller power separately from the UFS device power
4713 * rails as it will help controlling the UFS host controller power
4714 * collapse easily which is different than UFS device power collapse.
4715 * Also, enable the host controller power before we go ahead with rest
4716 * of the initialization here.
4717 */
4718 err = ufshcd_init_hba_vreg(hba);
4719 if (err)
4720 goto out;
4721
4722 err = ufshcd_setup_hba_vreg(hba, true);
4723 if (err)
4724 goto out;
4725
4726 err = ufshcd_init_clocks(hba);
4727 if (err)
4728 goto out_disable_hba_vreg;
4729
4730 err = ufshcd_setup_clocks(hba, true);
4731 if (err)
4732 goto out_disable_hba_vreg;
4733
4734 err = ufshcd_init_vreg(hba);
4735 if (err)
4736 goto out_disable_clks;
4737
4738 err = ufshcd_setup_vreg(hba, true);
4739 if (err)
4740 goto out_disable_clks;
4741
4742 err = ufshcd_variant_hba_init(hba);
4743 if (err)
4744 goto out_disable_vreg;
4745
4746 hba->is_powered = true;
4747 goto out;
4748
4749 out_disable_vreg:
4750 ufshcd_setup_vreg(hba, false);
4751 out_disable_clks:
4752 ufshcd_setup_clocks(hba, false);
4753 out_disable_hba_vreg:
4754 ufshcd_setup_hba_vreg(hba, false);
4755 out:
4756 return err;
4757 }
4758
4759 static void ufshcd_hba_exit(struct ufs_hba *hba)
4760 {
4761 if (hba->is_powered) {
4762 ufshcd_variant_hba_exit(hba);
4763 ufshcd_setup_vreg(hba, false);
4764 ufshcd_setup_clocks(hba, false);
4765 ufshcd_setup_hba_vreg(hba, false);
4766 hba->is_powered = false;
4767 }
4768 }
4769
4770 static int
4771 ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
4772 {
4773 unsigned char cmd[6] = {REQUEST_SENSE,
4774 0,
4775 0,
4776 0,
4777 SCSI_SENSE_BUFFERSIZE,
4778 0};
4779 char *buffer;
4780 int ret;
4781
4782 buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
4783 if (!buffer) {
4784 ret = -ENOMEM;
4785 goto out;
4786 }
4787
4788 ret = scsi_execute_req_flags(sdp, cmd, DMA_FROM_DEVICE, buffer,
4789 SCSI_SENSE_BUFFERSIZE, NULL,
4790 msecs_to_jiffies(1000), 3, NULL, REQ_PM);
4791 if (ret)
4792 pr_err("%s: failed with err %d\n", __func__, ret);
4793
4794 kfree(buffer);
4795 out:
4796 return ret;
4797 }
4798
4799 /**
4800 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
4801 * power mode
4802 * @hba: per adapter instance
4803 * @pwr_mode: device power mode to set
4804 *
4805 * Returns 0 if requested power mode is set successfully
4806 * Returns non-zero if failed to set the requested power mode
4807 */
4808 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
4809 enum ufs_dev_pwr_mode pwr_mode)
4810 {
4811 unsigned char cmd[6] = { START_STOP };
4812 struct scsi_sense_hdr sshdr;
4813 struct scsi_device *sdp;
4814 unsigned long flags;
4815 int ret;
4816
4817 spin_lock_irqsave(hba->host->host_lock, flags);
4818 sdp = hba->sdev_ufs_device;
4819 if (sdp) {
4820 ret = scsi_device_get(sdp);
4821 if (!ret && !scsi_device_online(sdp)) {
4822 ret = -ENODEV;
4823 scsi_device_put(sdp);
4824 }
4825 } else {
4826 ret = -ENODEV;
4827 }
4828 spin_unlock_irqrestore(hba->host->host_lock, flags);
4829
4830 if (ret)
4831 return ret;
4832
4833 /*
4834 * If scsi commands fail, the scsi mid-layer schedules scsi error-
4835 * handling, which would wait for host to be resumed. Since we know
4836 * we are functional while we are here, skip host resume in error
4837 * handling context.
4838 */
4839 hba->host->eh_noresume = 1;
4840 if (hba->wlun_dev_clr_ua) {
4841 ret = ufshcd_send_request_sense(hba, sdp);
4842 if (ret)
4843 goto out;
4844 /* Unit attention condition is cleared now */
4845 hba->wlun_dev_clr_ua = false;
4846 }
4847
4848 cmd[4] = pwr_mode << 4;
4849
4850 /*
4851 * Current function would be generally called from the power management
4852 * callbacks hence set the REQ_PM flag so that it doesn't resume the
4853 * already suspended childs.
4854 */
4855 ret = scsi_execute_req_flags(sdp, cmd, DMA_NONE, NULL, 0, &sshdr,
4856 START_STOP_TIMEOUT, 0, NULL, REQ_PM);
4857 if (ret) {
4858 sdev_printk(KERN_WARNING, sdp,
4859 "START_STOP failed for power mode: %d, result %x\n",
4860 pwr_mode, ret);
4861 if (driver_byte(ret) & DRIVER_SENSE)
4862 scsi_print_sense_hdr(sdp, NULL, &sshdr);
4863 }
4864
4865 if (!ret)
4866 hba->curr_dev_pwr_mode = pwr_mode;
4867 out:
4868 scsi_device_put(sdp);
4869 hba->host->eh_noresume = 0;
4870 return ret;
4871 }
4872
4873 static int ufshcd_link_state_transition(struct ufs_hba *hba,
4874 enum uic_link_state req_link_state,
4875 int check_for_bkops)
4876 {
4877 int ret = 0;
4878
4879 if (req_link_state == hba->uic_link_state)
4880 return 0;
4881
4882 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
4883 ret = ufshcd_uic_hibern8_enter(hba);
4884 if (!ret)
4885 ufshcd_set_link_hibern8(hba);
4886 else
4887 goto out;
4888 }
4889 /*
4890 * If autobkops is enabled, link can't be turned off because
4891 * turning off the link would also turn off the device.
4892 */
4893 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
4894 (!check_for_bkops || (check_for_bkops &&
4895 !hba->auto_bkops_enabled))) {
4896 /*
4897 * Change controller state to "reset state" which
4898 * should also put the link in off/reset state
4899 */
4900 ufshcd_hba_stop(hba);
4901 /*
4902 * TODO: Check if we need any delay to make sure that
4903 * controller is reset
4904 */
4905 ufshcd_set_link_off(hba);
4906 }
4907
4908 out:
4909 return ret;
4910 }
4911
4912 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
4913 {
4914 /*
4915 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
4916 * power.
4917 *
4918 * If UFS device and link is in OFF state, all power supplies (VCC,
4919 * VCCQ, VCCQ2) can be turned off if power on write protect is not
4920 * required. If UFS link is inactive (Hibern8 or OFF state) and device
4921 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
4922 *
4923 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
4924 * in low power state which would save some power.
4925 */
4926 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
4927 !hba->dev_info.is_lu_power_on_wp) {
4928 ufshcd_setup_vreg(hba, false);
4929 } else if (!ufshcd_is_ufs_dev_active(hba)) {
4930 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
4931 if (!ufshcd_is_link_active(hba)) {
4932 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
4933 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
4934 }
4935 }
4936 }
4937
4938 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
4939 {
4940 int ret = 0;
4941
4942 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
4943 !hba->dev_info.is_lu_power_on_wp) {
4944 ret = ufshcd_setup_vreg(hba, true);
4945 } else if (!ufshcd_is_ufs_dev_active(hba)) {
4946 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
4947 if (!ret && !ufshcd_is_link_active(hba)) {
4948 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
4949 if (ret)
4950 goto vcc_disable;
4951 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
4952 if (ret)
4953 goto vccq_lpm;
4954 }
4955 }
4956 goto out;
4957
4958 vccq_lpm:
4959 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
4960 vcc_disable:
4961 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
4962 out:
4963 return ret;
4964 }
4965
4966 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
4967 {
4968 if (ufshcd_is_link_off(hba))
4969 ufshcd_setup_hba_vreg(hba, false);
4970 }
4971
4972 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
4973 {
4974 if (ufshcd_is_link_off(hba))
4975 ufshcd_setup_hba_vreg(hba, true);
4976 }
4977
4978 /**
4979 * ufshcd_suspend - helper function for suspend operations
4980 * @hba: per adapter instance
4981 * @pm_op: desired low power operation type
4982 *
4983 * This function will try to put the UFS device and link into low power
4984 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
4985 * (System PM level).
4986 *
4987 * If this function is called during shutdown, it will make sure that
4988 * both UFS device and UFS link is powered off.
4989 *
4990 * NOTE: UFS device & link must be active before we enter in this function.
4991 *
4992 * Returns 0 for success and non-zero for failure
4993 */
4994 static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
4995 {
4996 int ret = 0;
4997 enum ufs_pm_level pm_lvl;
4998 enum ufs_dev_pwr_mode req_dev_pwr_mode;
4999 enum uic_link_state req_link_state;
5000
5001 hba->pm_op_in_progress = 1;
5002 if (!ufshcd_is_shutdown_pm(pm_op)) {
5003 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
5004 hba->rpm_lvl : hba->spm_lvl;
5005 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
5006 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
5007 } else {
5008 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
5009 req_link_state = UIC_LINK_OFF_STATE;
5010 }
5011
5012 /*
5013 * If we can't transition into any of the low power modes
5014 * just gate the clocks.
5015 */
5016 ufshcd_hold(hba, false);
5017 hba->clk_gating.is_suspended = true;
5018
5019 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
5020 req_link_state == UIC_LINK_ACTIVE_STATE) {
5021 goto disable_clks;
5022 }
5023
5024 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
5025 (req_link_state == hba->uic_link_state))
5026 goto out;
5027
5028 /* UFS device & link must be active before we enter in this function */
5029 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
5030 ret = -EINVAL;
5031 goto out;
5032 }
5033
5034 if (ufshcd_is_runtime_pm(pm_op)) {
5035 if (ufshcd_can_autobkops_during_suspend(hba)) {
5036 /*
5037 * The device is idle with no requests in the queue,
5038 * allow background operations if bkops status shows
5039 * that performance might be impacted.
5040 */
5041 ret = ufshcd_urgent_bkops(hba);
5042 if (ret)
5043 goto enable_gating;
5044 } else {
5045 /* make sure that auto bkops is disabled */
5046 ufshcd_disable_auto_bkops(hba);
5047 }
5048 }
5049
5050 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
5051 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
5052 !ufshcd_is_runtime_pm(pm_op))) {
5053 /* ensure that bkops is disabled */
5054 ufshcd_disable_auto_bkops(hba);
5055 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
5056 if (ret)
5057 goto enable_gating;
5058 }
5059
5060 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
5061 if (ret)
5062 goto set_dev_active;
5063
5064 ufshcd_vreg_set_lpm(hba);
5065
5066 disable_clks:
5067 /*
5068 * The clock scaling needs access to controller registers. Hence, Wait
5069 * for pending clock scaling work to be done before clocks are
5070 * turned off.
5071 */
5072 if (ufshcd_is_clkscaling_enabled(hba)) {
5073 devfreq_suspend_device(hba->devfreq);
5074 hba->clk_scaling.window_start_t = 0;
5075 }
5076 /*
5077 * Call vendor specific suspend callback. As these callbacks may access
5078 * vendor specific host controller register space call them before the
5079 * host clocks are ON.
5080 */
5081 ret = ufshcd_vops_suspend(hba, pm_op);
5082 if (ret)
5083 goto set_link_active;
5084
5085 ret = ufshcd_vops_setup_clocks(hba, false);
5086 if (ret)
5087 goto vops_resume;
5088
5089 if (!ufshcd_is_link_active(hba))
5090 ufshcd_setup_clocks(hba, false);
5091 else
5092 /* If link is active, device ref_clk can't be switched off */
5093 __ufshcd_setup_clocks(hba, false, true);
5094
5095 hba->clk_gating.state = CLKS_OFF;
5096 /*
5097 * Disable the host irq as host controller as there won't be any
5098 * host controller transaction expected till resume.
5099 */
5100 ufshcd_disable_irq(hba);
5101 /* Put the host controller in low power mode if possible */
5102 ufshcd_hba_vreg_set_lpm(hba);
5103 goto out;
5104
5105 vops_resume:
5106 ufshcd_vops_resume(hba, pm_op);
5107 set_link_active:
5108 ufshcd_vreg_set_hpm(hba);
5109 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
5110 ufshcd_set_link_active(hba);
5111 else if (ufshcd_is_link_off(hba))
5112 ufshcd_host_reset_and_restore(hba);
5113 set_dev_active:
5114 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
5115 ufshcd_disable_auto_bkops(hba);
5116 enable_gating:
5117 hba->clk_gating.is_suspended = false;
5118 ufshcd_release(hba);
5119 out:
5120 hba->pm_op_in_progress = 0;
5121 return ret;
5122 }
5123
5124 /**
5125 * ufshcd_resume - helper function for resume operations
5126 * @hba: per adapter instance
5127 * @pm_op: runtime PM or system PM
5128 *
5129 * This function basically brings the UFS device, UniPro link and controller
5130 * to active state.
5131 *
5132 * Returns 0 for success and non-zero for failure
5133 */
5134 static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
5135 {
5136 int ret;
5137 enum uic_link_state old_link_state;
5138
5139 hba->pm_op_in_progress = 1;
5140 old_link_state = hba->uic_link_state;
5141
5142 ufshcd_hba_vreg_set_hpm(hba);
5143 /* Make sure clocks are enabled before accessing controller */
5144 ret = ufshcd_setup_clocks(hba, true);
5145 if (ret)
5146 goto out;
5147
5148 /* enable the host irq as host controller would be active soon */
5149 ret = ufshcd_enable_irq(hba);
5150 if (ret)
5151 goto disable_irq_and_vops_clks;
5152
5153 ret = ufshcd_vreg_set_hpm(hba);
5154 if (ret)
5155 goto disable_irq_and_vops_clks;
5156
5157 /*
5158 * Call vendor specific resume callback. As these callbacks may access
5159 * vendor specific host controller register space call them when the
5160 * host clocks are ON.
5161 */
5162 ret = ufshcd_vops_resume(hba, pm_op);
5163 if (ret)
5164 goto disable_vreg;
5165
5166 if (ufshcd_is_link_hibern8(hba)) {
5167 ret = ufshcd_uic_hibern8_exit(hba);
5168 if (!ret)
5169 ufshcd_set_link_active(hba);
5170 else
5171 goto vendor_suspend;
5172 } else if (ufshcd_is_link_off(hba)) {
5173 ret = ufshcd_host_reset_and_restore(hba);
5174 /*
5175 * ufshcd_host_reset_and_restore() should have already
5176 * set the link state as active
5177 */
5178 if (ret || !ufshcd_is_link_active(hba))
5179 goto vendor_suspend;
5180 }
5181
5182 if (!ufshcd_is_ufs_dev_active(hba)) {
5183 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
5184 if (ret)
5185 goto set_old_link_state;
5186 }
5187
5188 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
5189 ufshcd_enable_auto_bkops(hba);
5190 else
5191 /*
5192 * If BKOPs operations are urgently needed at this moment then
5193 * keep auto-bkops enabled or else disable it.
5194 */
5195 ufshcd_urgent_bkops(hba);
5196
5197 hba->clk_gating.is_suspended = false;
5198
5199 if (ufshcd_is_clkscaling_enabled(hba))
5200 devfreq_resume_device(hba->devfreq);
5201
5202 /* Schedule clock gating in case of no access to UFS device yet */
5203 ufshcd_release(hba);
5204 goto out;
5205
5206 set_old_link_state:
5207 ufshcd_link_state_transition(hba, old_link_state, 0);
5208 vendor_suspend:
5209 ufshcd_vops_suspend(hba, pm_op);
5210 disable_vreg:
5211 ufshcd_vreg_set_lpm(hba);
5212 disable_irq_and_vops_clks:
5213 ufshcd_disable_irq(hba);
5214 ufshcd_setup_clocks(hba, false);
5215 out:
5216 hba->pm_op_in_progress = 0;
5217 return ret;
5218 }
5219
5220 /**
5221 * ufshcd_system_suspend - system suspend routine
5222 * @hba: per adapter instance
5223 * @pm_op: runtime PM or system PM
5224 *
5225 * Check the description of ufshcd_suspend() function for more details.
5226 *
5227 * Returns 0 for success and non-zero for failure
5228 */
5229 int ufshcd_system_suspend(struct ufs_hba *hba)
5230 {
5231 int ret = 0;
5232
5233 if (!hba || !hba->is_powered)
5234 return 0;
5235
5236 if (pm_runtime_suspended(hba->dev)) {
5237 if (hba->rpm_lvl == hba->spm_lvl)
5238 /*
5239 * There is possibility that device may still be in
5240 * active state during the runtime suspend.
5241 */
5242 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
5243 hba->curr_dev_pwr_mode) && !hba->auto_bkops_enabled)
5244 goto out;
5245
5246 /*
5247 * UFS device and/or UFS link low power states during runtime
5248 * suspend seems to be different than what is expected during
5249 * system suspend. Hence runtime resume the devic & link and
5250 * let the system suspend low power states to take effect.
5251 * TODO: If resume takes longer time, we might have optimize
5252 * it in future by not resuming everything if possible.
5253 */
5254 ret = ufshcd_runtime_resume(hba);
5255 if (ret)
5256 goto out;
5257 }
5258
5259 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
5260 out:
5261 if (!ret)
5262 hba->is_sys_suspended = true;
5263 return ret;
5264 }
5265 EXPORT_SYMBOL(ufshcd_system_suspend);
5266
5267 /**
5268 * ufshcd_system_resume - system resume routine
5269 * @hba: per adapter instance
5270 *
5271 * Returns 0 for success and non-zero for failure
5272 */
5273
5274 int ufshcd_system_resume(struct ufs_hba *hba)
5275 {
5276 if (!hba || !hba->is_powered || pm_runtime_suspended(hba->dev))
5277 /*
5278 * Let the runtime resume take care of resuming
5279 * if runtime suspended.
5280 */
5281 return 0;
5282
5283 return ufshcd_resume(hba, UFS_SYSTEM_PM);
5284 }
5285 EXPORT_SYMBOL(ufshcd_system_resume);
5286
5287 /**
5288 * ufshcd_runtime_suspend - runtime suspend routine
5289 * @hba: per adapter instance
5290 *
5291 * Check the description of ufshcd_suspend() function for more details.
5292 *
5293 * Returns 0 for success and non-zero for failure
5294 */
5295 int ufshcd_runtime_suspend(struct ufs_hba *hba)
5296 {
5297 if (!hba || !hba->is_powered)
5298 return 0;
5299
5300 return ufshcd_suspend(hba, UFS_RUNTIME_PM);
5301 }
5302 EXPORT_SYMBOL(ufshcd_runtime_suspend);
5303
5304 /**
5305 * ufshcd_runtime_resume - runtime resume routine
5306 * @hba: per adapter instance
5307 *
5308 * This function basically brings the UFS device, UniPro link and controller
5309 * to active state. Following operations are done in this function:
5310 *
5311 * 1. Turn on all the controller related clocks
5312 * 2. Bring the UniPro link out of Hibernate state
5313 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
5314 * to active state.
5315 * 4. If auto-bkops is enabled on the device, disable it.
5316 *
5317 * So following would be the possible power state after this function return
5318 * successfully:
5319 * S1: UFS device in Active state with VCC rail ON
5320 * UniPro link in Active state
5321 * All the UFS/UniPro controller clocks are ON
5322 *
5323 * Returns 0 for success and non-zero for failure
5324 */
5325 int ufshcd_runtime_resume(struct ufs_hba *hba)
5326 {
5327 if (!hba || !hba->is_powered)
5328 return 0;
5329 else
5330 return ufshcd_resume(hba, UFS_RUNTIME_PM);
5331 }
5332 EXPORT_SYMBOL(ufshcd_runtime_resume);
5333
5334 int ufshcd_runtime_idle(struct ufs_hba *hba)
5335 {
5336 return 0;
5337 }
5338 EXPORT_SYMBOL(ufshcd_runtime_idle);
5339
5340 /**
5341 * ufshcd_shutdown - shutdown routine
5342 * @hba: per adapter instance
5343 *
5344 * This function would power off both UFS device and UFS link.
5345 *
5346 * Returns 0 always to allow force shutdown even in case of errors.
5347 */
5348 int ufshcd_shutdown(struct ufs_hba *hba)
5349 {
5350 int ret = 0;
5351
5352 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
5353 goto out;
5354
5355 if (pm_runtime_suspended(hba->dev)) {
5356 ret = ufshcd_runtime_resume(hba);
5357 if (ret)
5358 goto out;
5359 }
5360
5361 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
5362 out:
5363 if (ret)
5364 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
5365 /* allow force shutdown even in case of errors */
5366 return 0;
5367 }
5368 EXPORT_SYMBOL(ufshcd_shutdown);
5369
5370 /*
5371 * Values permitted 0, 1, 2.
5372 * 0 -> Disable IO latency histograms (default)
5373 * 1 -> Enable IO latency histograms
5374 * 2 -> Zero out IO latency histograms
5375 */
5376 static ssize_t
5377 latency_hist_store(struct device *dev, struct device_attribute *attr,
5378 const char *buf, size_t count)
5379 {
5380 struct ufs_hba *hba = dev_get_drvdata(dev);
5381 long value;
5382
5383 if (kstrtol(buf, 0, &value))
5384 return -EINVAL;
5385 if (value == BLK_IO_LAT_HIST_ZERO)
5386 blk_zero_latency_hist(&hba->io_lat_s);
5387 else if (value == BLK_IO_LAT_HIST_ENABLE ||
5388 value == BLK_IO_LAT_HIST_DISABLE)
5389 hba->latency_hist_enabled = value;
5390 return count;
5391 }
5392
5393 ssize_t
5394 latency_hist_show(struct device *dev, struct device_attribute *attr,
5395 char *buf)
5396 {
5397 struct ufs_hba *hba = dev_get_drvdata(dev);
5398
5399 return blk_latency_hist_show(&hba->io_lat_s, buf);
5400 }
5401
5402 static DEVICE_ATTR(latency_hist, S_IRUGO | S_IWUSR,
5403 latency_hist_show, latency_hist_store);
5404
5405 static void
5406 ufshcd_init_latency_hist(struct ufs_hba *hba)
5407 {
5408 if (device_create_file(hba->dev, &dev_attr_latency_hist))
5409 dev_err(hba->dev, "Failed to create latency_hist sysfs entry\n");
5410 }
5411
5412 static void
5413 ufshcd_exit_latency_hist(struct ufs_hba *hba)
5414 {
5415 device_create_file(hba->dev, &dev_attr_latency_hist);
5416 }
5417
5418 /**
5419 * ufshcd_remove - de-allocate SCSI host and host memory space
5420 * data structure memory
5421 * @hba - per adapter instance
5422 */
5423 void ufshcd_remove(struct ufs_hba *hba)
5424 {
5425 scsi_remove_host(hba->host);
5426 /* disable interrupts */
5427 ufshcd_disable_intr(hba, hba->intr_mask);
5428 ufshcd_hba_stop(hba);
5429
5430 scsi_host_put(hba->host);
5431
5432 ufshcd_exit_clk_gating(hba);
5433 ufshcd_exit_latency_hist(hba);
5434 if (ufshcd_is_clkscaling_enabled(hba))
5435 devfreq_remove_device(hba->devfreq);
5436 ufshcd_hba_exit(hba);
5437 }
5438 EXPORT_SYMBOL_GPL(ufshcd_remove);
5439
5440 /**
5441 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
5442 * @hba: pointer to Host Bus Adapter (HBA)
5443 */
5444 void ufshcd_dealloc_host(struct ufs_hba *hba)
5445 {
5446 scsi_host_put(hba->host);
5447 }
5448 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
5449
5450 /**
5451 * ufshcd_set_dma_mask - Set dma mask based on the controller
5452 * addressing capability
5453 * @hba: per adapter instance
5454 *
5455 * Returns 0 for success, non-zero for failure
5456 */
5457 static int ufshcd_set_dma_mask(struct ufs_hba *hba)
5458 {
5459 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
5460 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
5461 return 0;
5462 }
5463 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
5464 }
5465
5466 /**
5467 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
5468 * @dev: pointer to device handle
5469 * @hba_handle: driver private handle
5470 * Returns 0 on success, non-zero value on failure
5471 */
5472 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
5473 {
5474 struct Scsi_Host *host;
5475 struct ufs_hba *hba;
5476 int err = 0;
5477
5478 if (!dev) {
5479 dev_err(dev,
5480 "Invalid memory reference for dev is NULL\n");
5481 err = -ENODEV;
5482 goto out_error;
5483 }
5484
5485 host = scsi_host_alloc(&ufshcd_driver_template,
5486 sizeof(struct ufs_hba));
5487 if (!host) {
5488 dev_err(dev, "scsi_host_alloc failed\n");
5489 err = -ENOMEM;
5490 goto out_error;
5491 }
5492 hba = shost_priv(host);
5493 hba->host = host;
5494 hba->dev = dev;
5495 *hba_handle = hba;
5496
5497 out_error:
5498 return err;
5499 }
5500 EXPORT_SYMBOL(ufshcd_alloc_host);
5501
5502 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
5503 {
5504 int ret = 0;
5505 struct ufs_clk_info *clki;
5506 struct list_head *head = &hba->clk_list_head;
5507
5508 if (!head || list_empty(head))
5509 goto out;
5510
5511 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
5512 if (ret)
5513 return ret;
5514
5515 list_for_each_entry(clki, head, list) {
5516 if (!IS_ERR_OR_NULL(clki->clk)) {
5517 if (scale_up && clki->max_freq) {
5518 if (clki->curr_freq == clki->max_freq)
5519 continue;
5520 ret = clk_set_rate(clki->clk, clki->max_freq);
5521 if (ret) {
5522 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
5523 __func__, clki->name,
5524 clki->max_freq, ret);
5525 break;
5526 }
5527 clki->curr_freq = clki->max_freq;
5528
5529 } else if (!scale_up && clki->min_freq) {
5530 if (clki->curr_freq == clki->min_freq)
5531 continue;
5532 ret = clk_set_rate(clki->clk, clki->min_freq);
5533 if (ret) {
5534 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
5535 __func__, clki->name,
5536 clki->min_freq, ret);
5537 break;
5538 }
5539 clki->curr_freq = clki->min_freq;
5540 }
5541 }
5542 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
5543 clki->name, clk_get_rate(clki->clk));
5544 }
5545
5546 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
5547
5548 out:
5549 return ret;
5550 }
5551
5552 static int ufshcd_devfreq_target(struct device *dev,
5553 unsigned long *freq, u32 flags)
5554 {
5555 int err = 0;
5556 struct ufs_hba *hba = dev_get_drvdata(dev);
5557
5558 if (!ufshcd_is_clkscaling_enabled(hba))
5559 return -EINVAL;
5560
5561 if (*freq == UINT_MAX)
5562 err = ufshcd_scale_clks(hba, true);
5563 else if (*freq == 0)
5564 err = ufshcd_scale_clks(hba, false);
5565
5566 return err;
5567 }
5568
5569 static int ufshcd_devfreq_get_dev_status(struct device *dev,
5570 struct devfreq_dev_status *stat)
5571 {
5572 struct ufs_hba *hba = dev_get_drvdata(dev);
5573 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
5574 unsigned long flags;
5575
5576 if (!ufshcd_is_clkscaling_enabled(hba))
5577 return -EINVAL;
5578
5579 memset(stat, 0, sizeof(*stat));
5580
5581 spin_lock_irqsave(hba->host->host_lock, flags);
5582 if (!scaling->window_start_t)
5583 goto start_window;
5584
5585 if (scaling->is_busy_started)
5586 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
5587 scaling->busy_start_t));
5588
5589 stat->total_time = jiffies_to_usecs((long)jiffies -
5590 (long)scaling->window_start_t);
5591 stat->busy_time = scaling->tot_busy_t;
5592 start_window:
5593 scaling->window_start_t = jiffies;
5594 scaling->tot_busy_t = 0;
5595
5596 if (hba->outstanding_reqs) {
5597 scaling->busy_start_t = ktime_get();
5598 scaling->is_busy_started = true;
5599 } else {
5600 scaling->busy_start_t = ktime_set(0, 0);
5601 scaling->is_busy_started = false;
5602 }
5603 spin_unlock_irqrestore(hba->host->host_lock, flags);
5604 return 0;
5605 }
5606
5607 static struct devfreq_dev_profile ufs_devfreq_profile = {
5608 .polling_ms = 100,
5609 .target = ufshcd_devfreq_target,
5610 .get_dev_status = ufshcd_devfreq_get_dev_status,
5611 };
5612
5613 /**
5614 * ufshcd_init - Driver initialization routine
5615 * @hba: per-adapter instance
5616 * @mmio_base: base register address
5617 * @irq: Interrupt line of device
5618 * Returns 0 on success, non-zero value on failure
5619 */
5620 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
5621 {
5622 int err;
5623 struct Scsi_Host *host = hba->host;
5624 struct device *dev = hba->dev;
5625
5626 if (!mmio_base) {
5627 dev_err(hba->dev,
5628 "Invalid memory reference for mmio_base is NULL\n");
5629 err = -ENODEV;
5630 goto out_error;
5631 }
5632
5633 hba->mmio_base = mmio_base;
5634 hba->irq = irq;
5635
5636 err = ufshcd_hba_init(hba);
5637 if (err)
5638 goto out_error;
5639
5640 /* Read capabilities registers */
5641 ufshcd_hba_capabilities(hba);
5642
5643 /* Get UFS version supported by the controller */
5644 hba->ufs_version = ufshcd_get_ufs_version(hba);
5645
5646 /* Get Interrupt bit mask per version */
5647 hba->intr_mask = ufshcd_get_intr_mask(hba);
5648
5649 err = ufshcd_set_dma_mask(hba);
5650 if (err) {
5651 dev_err(hba->dev, "set dma mask failed\n");
5652 goto out_disable;
5653 }
5654
5655 /* Allocate memory for host memory space */
5656 err = ufshcd_memory_alloc(hba);
5657 if (err) {
5658 dev_err(hba->dev, "Memory allocation failed\n");
5659 goto out_disable;
5660 }
5661
5662 /* Configure LRB */
5663 ufshcd_host_memory_configure(hba);
5664
5665 host->can_queue = hba->nutrs;
5666 host->cmd_per_lun = hba->nutrs;
5667 host->max_id = UFSHCD_MAX_ID;
5668 host->max_lun = UFS_MAX_LUNS;
5669 host->max_channel = UFSHCD_MAX_CHANNEL;
5670 host->unique_id = host->host_no;
5671 host->max_cmd_len = MAX_CDB_SIZE;
5672
5673 hba->max_pwr_info.is_valid = false;
5674
5675 /* Initailize wait queue for task management */
5676 init_waitqueue_head(&hba->tm_wq);
5677 init_waitqueue_head(&hba->tm_tag_wq);
5678
5679 /* Initialize work queues */
5680 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
5681 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
5682
5683 /* Initialize UIC command mutex */
5684 mutex_init(&hba->uic_cmd_mutex);
5685
5686 /* Initialize mutex for device management commands */
5687 mutex_init(&hba->dev_cmd.lock);
5688
5689 /* Initialize device management tag acquire wait queue */
5690 init_waitqueue_head(&hba->dev_cmd.tag_wq);
5691
5692 ufshcd_init_clk_gating(hba);
5693 /* IRQ registration */
5694 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
5695 if (err) {
5696 dev_err(hba->dev, "request irq failed\n");
5697 goto exit_gating;
5698 } else {
5699 hba->is_irq_enabled = true;
5700 }
5701
5702 err = scsi_add_host(host, hba->dev);
5703 if (err) {
5704 dev_err(hba->dev, "scsi_add_host failed\n");
5705 goto exit_gating;
5706 }
5707
5708 /* Host controller enable */
5709 err = ufshcd_hba_enable(hba);
5710 if (err) {
5711 dev_err(hba->dev, "Host controller enable failed\n");
5712 goto out_remove_scsi_host;
5713 }
5714
5715 if (ufshcd_is_clkscaling_enabled(hba)) {
5716 hba->devfreq = devfreq_add_device(dev, &ufs_devfreq_profile,
5717 "simple_ondemand", NULL);
5718 if (IS_ERR(hba->devfreq)) {
5719 dev_err(hba->dev, "Unable to register with devfreq %ld\n",
5720 PTR_ERR(hba->devfreq));
5721 goto out_remove_scsi_host;
5722 }
5723 /* Suspend devfreq until the UFS device is detected */
5724 devfreq_suspend_device(hba->devfreq);
5725 hba->clk_scaling.window_start_t = 0;
5726 }
5727
5728 /* Hold auto suspend until async scan completes */
5729 pm_runtime_get_sync(dev);
5730
5731 ufshcd_init_latency_hist(hba);
5732
5733 /*
5734 * The device-initialize-sequence hasn't been invoked yet.
5735 * Set the device to power-off state
5736 */
5737 ufshcd_set_ufs_dev_poweroff(hba);
5738
5739 async_schedule(ufshcd_async_scan, hba);
5740
5741 return 0;
5742
5743 out_remove_scsi_host:
5744 scsi_remove_host(hba->host);
5745 exit_gating:
5746 ufshcd_exit_clk_gating(hba);
5747 ufshcd_exit_latency_hist(hba);
5748 out_disable:
5749 hba->is_irq_enabled = false;
5750 scsi_host_put(host);
5751 ufshcd_hba_exit(hba);
5752 out_error:
5753 return err;
5754 }
5755 EXPORT_SYMBOL_GPL(ufshcd_init);
5756
5757 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
5758 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
5759 MODULE_DESCRIPTION("Generic UFS host controller driver Core");
5760 MODULE_LICENSE("GPL");
5761 MODULE_VERSION(UFSHCD_DRIVER_VERSION);