drivers/pci/setup-res.c

   1 /*
   2  *      drivers/pci/setup-res.c
   3  *
   4  * Extruded from code written by
   5  *      Dave Rusling (david.rusling@reo.mts.dec.com)
   6  *      David Mosberger (davidm@cs.arizona.edu)
   7  *      David Miller (davem@redhat.com)
   8  *
   9  * Support routines for initializing a PCI subsystem.
  10  */
  11
  12 /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
  13
  14 /*
  15  * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  16  *           Resource sorting
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/export.h>
  21 #include <linux/pci.h>
  22 #include <linux/errno.h>
  23 #include <linux/ioport.h>
  24 #include <linux/cache.h>
  25 #include <linux/slab.h>
  26 #include "pci.h"
  27
  28 static void pci_std_update_resource(struct pci_dev *dev, int resno)
  29 {
  30         struct pci_bus_region region;
  31         bool disable;
  32         u16 cmd;
  33         u32 new, check, mask;
  34         int reg;
  35         struct resource *res = dev->resource + resno;
  36
  37         if (dev->is_virtfn) {
  38                 dev_warn(&dev->dev, "can't update VF BAR%d\n", resno);
  39                 return;
  40         }
  41
  42         /*
  43          * Ignore resources for unimplemented BARs and unused resource slots
  44          * for 64 bit BARs.
  45          */
  46         if (!res->flags)
  47                 return;
  48
  49         if (res->flags & IORESOURCE_UNSET)
  50                 return;
  51
  52         /*
  53          * Ignore non-moveable resources.  This might be legacy resources for
  54          * which no functional BAR register exists or another important
  55          * system resource we shouldn't move around.
  56          */
  57         if (res->flags & IORESOURCE_PCI_FIXED)
  58                 return;
  59
  60         pcibios_resource_to_bus(dev->bus, &region, res);
  61
  62         new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
  63         if (res->flags & IORESOURCE_IO)
  64                 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
  65         else
  66                 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
  67
  68         if (resno < PCI_ROM_RESOURCE) {
  69                 reg = PCI_BASE_ADDRESS_0 + 4 * resno;
  70         } else if (resno == PCI_ROM_RESOURCE) {
  71
  72                 /*
  73                  * Apparently some Matrox devices have ROM BARs that read
  74                  * as zero when disabled, so don't update ROM BARs unless
  75                  * they're enabled.  See https://lkml.org/lkml/2005/8/30/138.
  76                  */
  77                 if (!(res->flags & IORESOURCE_ROM_ENABLE))
  78                         return;
  79
  80                 reg = dev->rom_base_reg;
  81                 new |= PCI_ROM_ADDRESS_ENABLE;
  82         } else
  83                 return;
  84
  85         /*
  86          * We can't update a 64-bit BAR atomically, so when possible,
  87          * disable decoding so that a half-updated BAR won't conflict
  88          * with another device.
  89          */
  90         disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
  91         if (disable) {
  92                 pci_read_config_word(dev, PCI_COMMAND, &cmd);
  93                 pci_write_config_word(dev, PCI_COMMAND,
  94                                       cmd & ~PCI_COMMAND_MEMORY);
  95         }
  96
  97         pci_write_config_dword(dev, reg, new);
  98         pci_read_config_dword(dev, reg, &check);
  99
 100         if ((new ^ check) & mask) {
 101                 dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
 102                         resno, new, check);
 103         }
 104
 105         if (res->flags & IORESOURCE_MEM_64) {
 106                 new = region.start >> 16 >> 16;
 107                 pci_write_config_dword(dev, reg + 4, new);
 108                 pci_read_config_dword(dev, reg + 4, &check);
 109                 if (check != new) {
 110                         dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n",
 111                                 resno, new, check);
 112                 }
 113         }
 114
 115         if (disable)
 116                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 117 }
 118
 119 void pci_update_resource(struct pci_dev *dev, int resno)
 120 {
 121         if (resno <= PCI_ROM_RESOURCE)
 122                 pci_std_update_resource(dev, resno);
 123 #ifdef CONFIG_PCI_IOV
 124         else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
 125                 pci_iov_update_resource(dev, resno);
 126 #endif
 127 }
 128
 129 int pci_claim_resource(struct pci_dev *dev, int resource)
 130 {
 131         struct resource *res = &dev->resource[resource];
 132         struct resource *root, *conflict;
 133
 134         if (res->flags & IORESOURCE_UNSET) {
 135                 dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n",
 136                          resource, res);
 137                 return -EINVAL;
 138         }
 139
 140         root = pci_find_parent_resource(dev, res);
 141         if (!root) {
 142                 dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
 143                          resource, res);
 144                 res->flags |= IORESOURCE_UNSET;
 145                 return -EINVAL;
 146         }
 147
 148         conflict = request_resource_conflict(root, res);
 149         if (conflict) {
 150                 dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
 151                          resource, res, conflict->name, conflict);
 152                 res->flags |= IORESOURCE_UNSET;
 153                 return -EBUSY;
 154         }
 155
 156         return 0;
 157 }
 158 EXPORT_SYMBOL(pci_claim_resource);
 159
 160 void pci_disable_bridge_window(struct pci_dev *dev)
 161 {
 162         dev_info(&dev->dev, "disabling bridge mem windows\n");
 163
 164         /* MMIO Base/Limit */
 165         pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
 166
 167         /* Prefetchable MMIO Base/Limit */
 168         pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
 169         pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
 170         pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
 171 }
 172
 173 /*
 174  * Generic function that returns a value indicating that the device's
 175  * original BIOS BAR address was not saved and so is not available for
 176  * reinstatement.
 177  *
 178  * Can be over-ridden by architecture specific code that implements
 179  * reinstatement functionality rather than leaving it disabled when
 180  * normal allocation attempts fail.
 181  */
 182 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
 183 {
 184         return 0;
 185 }
 186
 187 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
 188                 int resno, resource_size_t size)
 189 {
 190         struct resource *root, *conflict;
 191         resource_size_t fw_addr, start, end;
 192
 193         fw_addr = pcibios_retrieve_fw_addr(dev, resno);
 194         if (!fw_addr)
 195                 return -ENOMEM;
 196
 197         start = res->start;
 198         end = res->end;
 199         res->start = fw_addr;
 200         res->end = res->start + size - 1;
 201         res->flags &= ~IORESOURCE_UNSET;
 202
 203         root = pci_find_parent_resource(dev, res);
 204         if (!root) {
 205                 if (res->flags & IORESOURCE_IO)
 206                         root = &ioport_resource;
 207                 else
 208                         root = &iomem_resource;
 209         }
 210
 211         dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
 212                  resno, res);
 213         conflict = request_resource_conflict(root, res);
 214         if (conflict) {
 215                 dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n",
 216                          resno, res, conflict->name, conflict);
 217                 res->start = start;
 218                 res->end = end;
 219                 res->flags |= IORESOURCE_UNSET;
 220                 return -EBUSY;
 221         }
 222         return 0;
 223 }
 224
 225 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
 226                 int resno, resource_size_t size, resource_size_t align)
 227 {
 228         struct resource *res = dev->resource + resno;
 229         resource_size_t min;
 230         int ret;
 231
 232         min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
 233
 234         /*
 235          * First, try exact prefetching match.  Even if a 64-bit
 236          * prefetchable bridge window is below 4GB, we can't put a 32-bit
 237          * prefetchable resource in it because pbus_size_mem() assumes a
 238          * 64-bit window will contain no 32-bit resources.  If we assign
 239          * things differently than they were sized, not everything will fit.
 240          */
 241         ret = pci_bus_alloc_resource(bus, res, size, align, min,
 242                                      IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
 243                                      pcibios_align_resource, dev);
 244         if (ret == 0)
 245                 return 0;
 246
 247         /*
 248          * If the prefetchable window is only 32 bits wide, we can put
 249          * 64-bit prefetchable resources in it.
 250          */
 251         if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
 252              (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
 253                 ret = pci_bus_alloc_resource(bus, res, size, align, min,
 254                                              IORESOURCE_PREFETCH,
 255                                              pcibios_align_resource, dev);
 256                 if (ret == 0)
 257                         return 0;
 258         }
 259
 260         /*
 261          * If we didn't find a better match, we can put any memory resource
 262          * in a non-prefetchable window.  If this resource is 32 bits and
 263          * non-prefetchable, the first call already tried the only possibility
 264          * so we don't need to try again.
 265          */
 266         if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
 267                 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
 268                                              pcibios_align_resource, dev);
 269
 270         return ret;
 271 }
 272
 273 static int _pci_assign_resource(struct pci_dev *dev, int resno,
 274                                 resource_size_t size, resource_size_t min_align)
 275 {
 276         struct pci_bus *bus;
 277         int ret;
 278
 279         bus = dev->bus;
 280         while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
 281                 if (!bus->parent || !bus->self->transparent)
 282                         break;
 283                 bus = bus->parent;
 284         }
 285
 286         return ret;
 287 }
 288
 289 int pci_assign_resource(struct pci_dev *dev, int resno)
 290 {
 291         struct resource *res = dev->resource + resno;
 292         resource_size_t align, size;
 293         int ret;
 294
 295         res->flags |= IORESOURCE_UNSET;
 296         align = pci_resource_alignment(dev, res);
 297         if (!align) {
 298                 dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n",
 299                          resno, res);
 300                 return -EINVAL;
 301         }
 302
 303         size = resource_size(res);
 304         ret = _pci_assign_resource(dev, resno, size, align);
 305
 306         /*
 307          * If we failed to assign anything, let's try the address
 308          * where firmware left it.  That at least has a chance of
 309          * working, which is better than just leaving it disabled.
 310          */
 311         if (ret < 0) {
 312                 dev_info(&dev->dev, "BAR %d: no space for %pR\n", resno, res);
 313                 ret = pci_revert_fw_address(res, dev, resno, size);
 314         }
 315
 316         if (ret < 0) {
 317                 dev_info(&dev->dev, "BAR %d: failed to assign %pR\n", resno,
 318                          res);
 319                 return ret;
 320         }
 321
 322         res->flags &= ~IORESOURCE_UNSET;
 323         res->flags &= ~IORESOURCE_STARTALIGN;
 324         dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
 325         if (resno < PCI_BRIDGE_RESOURCES)
 326                 pci_update_resource(dev, resno);
 327
 328         return 0;
 329 }
 330 EXPORT_SYMBOL(pci_assign_resource);
 331
 332 int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
 333                         resource_size_t min_align)
 334 {
 335         struct resource *res = dev->resource + resno;
 336         unsigned long flags;
 337         resource_size_t new_size;
 338         int ret;
 339
 340         flags = res->flags;
 341         res->flags |= IORESOURCE_UNSET;
 342         if (!res->parent) {
 343                 dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n",
 344                          resno, res);
 345                 return -EINVAL;
 346         }
 347
 348         /* already aligned with min_align */
 349         new_size = resource_size(res) + addsize;
 350         ret = _pci_assign_resource(dev, resno, new_size, min_align);
 351         if (ret) {
 352                 res->flags = flags;
 353                 dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n",
 354                          resno, res, (unsigned long long) addsize);
 355                 return ret;
 356         }
 357
 358         res->flags &= ~IORESOURCE_UNSET;
 359         res->flags &= ~IORESOURCE_STARTALIGN;
 360         dev_info(&dev->dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
 361                  resno, res, (unsigned long long) addsize);
 362         if (resno < PCI_BRIDGE_RESOURCES)
 363                 pci_update_resource(dev, resno);
 364
 365         return 0;
 366 }
 367
 368 int pci_enable_resources(struct pci_dev *dev, int mask)
 369 {
 370         u16 cmd, old_cmd;
 371         int i;
 372         struct resource *r;
 373
 374         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 375         old_cmd = cmd;
 376
 377         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 378                 if (!(mask & (1 << i)))
 379                         continue;
 380
 381                 r = &dev->resource[i];
 382
 383                 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
 384                         continue;
 385                 if ((i == PCI_ROM_RESOURCE) &&
 386                                 (!(r->flags & IORESOURCE_ROM_ENABLE)))
 387                         continue;
 388
 389                 if (r->flags & IORESOURCE_UNSET) {
 390                         dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n",
 391                                 i, r);
 392                         return -EINVAL;
 393                 }
 394
 395                 if (!r->parent) {
 396                         dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n",
 397                                 i, r);
 398                         return -EINVAL;
 399                 }
 400
 401                 if (r->flags & IORESOURCE_IO)
 402                         cmd |= PCI_COMMAND_IO;
 403                 if (r->flags & IORESOURCE_MEM)
 404                         cmd |= PCI_COMMAND_MEMORY;
 405         }
 406
 407         if (cmd != old_cmd) {
 408                 dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
 409                          old_cmd, cmd);
 410                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 411         }
 412         return 0;
 413 }