projects / GitHub / exynos8895 / android_kernel_samsung_universal8895.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
PCI: Skip MPS logic for Virtual Functions (VFs)
[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / pci / probe.c
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/of_device.h>
10 #include <linux/of_pci.h>
11 #include <linux/pci_hotplug.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/cpumask.h>
15 #include <linux/pci-aspm.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
18 #include <asm-generic/pci-bridge.h>
19 #include "pci.h"
20
21 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
22 #define CARDBUS_RESERVE_BUSNR 3
23
24 static struct resource busn_resource = {
25 .name = "PCI busn",
26 .start = 0,
27 .end = 255,
28 .flags = IORESOURCE_BUS,
29 };
30
31 /* Ugh. Need to stop exporting this to modules. */
32 LIST_HEAD(pci_root_buses);
33 EXPORT_SYMBOL(pci_root_buses);
34
35 static LIST_HEAD(pci_domain_busn_res_list);
36
37 struct pci_domain_busn_res {
38 struct list_head list;
39 struct resource res;
40 int domain_nr;
41 };
42
43 static struct resource *get_pci_domain_busn_res(int domain_nr)
44 {
45 struct pci_domain_busn_res *r;
46
47 list_for_each_entry(r, &pci_domain_busn_res_list, list)
48 if (r->domain_nr == domain_nr)
49 return &r->res;
50
51 r = kzalloc(sizeof(*r), GFP_KERNEL);
52 if (!r)
53 return NULL;
54
55 r->domain_nr = domain_nr;
56 r->res.start = 0;
57 r->res.end = 0xff;
58 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
59
60 list_add_tail(&r->list, &pci_domain_busn_res_list);
61
62 return &r->res;
63 }
64
65 static int find_anything(struct device *dev, void *data)
66 {
67 return 1;
68 }
69
70 /*
71 * Some device drivers need know if pci is initiated.
72 * Basically, we think pci is not initiated when there
73 * is no device to be found on the pci_bus_type.
74 */
75 int no_pci_devices(void)
76 {
77 struct device *dev;
78 int no_devices;
79
80 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
81 no_devices = (dev == NULL);
82 put_device(dev);
83 return no_devices;
84 }
85 EXPORT_SYMBOL(no_pci_devices);
86
87 /*
88 * PCI Bus Class
89 */
90 static void release_pcibus_dev(struct device *dev)
91 {
92 struct pci_bus *pci_bus = to_pci_bus(dev);
93
94 put_device(pci_bus->bridge);
95 pci_bus_remove_resources(pci_bus);
96 pci_release_bus_of_node(pci_bus);
97 kfree(pci_bus);
98 }
99
100 static struct class pcibus_class = {
101 .name = "pci_bus",
102 .dev_release = &release_pcibus_dev,
103 .dev_groups = pcibus_groups,
104 };
105
106 static int __init pcibus_class_init(void)
107 {
108 return class_register(&pcibus_class);
109 }
110 postcore_initcall(pcibus_class_init);
111
112 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
113 {
114 u64 size = mask & maxbase; /* Find the significant bits */
115 if (!size)
116 return 0;
117
118 /* Get the lowest of them to find the decode size, and
119 from that the extent. */
120 size = (size & ~(size-1)) - 1;
121
122 /* base == maxbase can be valid only if the BAR has
123 already been programmed with all 1s. */
124 if (base == maxbase && ((base | size) & mask) != mask)
125 return 0;
126
127 return size;
128 }
129
130 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
131 {
132 u32 mem_type;
133 unsigned long flags;
134
135 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
136 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
137 flags |= IORESOURCE_IO;
138 return flags;
139 }
140
141 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
142 flags |= IORESOURCE_MEM;
143 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
144 flags |= IORESOURCE_PREFETCH;
145
146 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
147 switch (mem_type) {
148 case PCI_BASE_ADDRESS_MEM_TYPE_32:
149 break;
150 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
151 /* 1M mem BAR treated as 32-bit BAR */
152 break;
153 case PCI_BASE_ADDRESS_MEM_TYPE_64:
154 flags |= IORESOURCE_MEM_64;
155 break;
156 default:
157 /* mem unknown type treated as 32-bit BAR */
158 break;
159 }
160 return flags;
161 }
162
163 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
164
165 /**
166 * pci_read_base - read a PCI BAR
167 * @dev: the PCI device
168 * @type: type of the BAR
169 * @res: resource buffer to be filled in
170 * @pos: BAR position in the config space
171 *
172 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
173 */
174 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
175 struct resource *res, unsigned int pos)
176 {
177 u32 l, sz, mask;
178 u64 l64, sz64, mask64;
179 u16 orig_cmd;
180 struct pci_bus_region region, inverted_region;
181
182 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
183
184 /* No printks while decoding is disabled! */
185 if (!dev->mmio_always_on) {
186 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
187 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
188 pci_write_config_word(dev, PCI_COMMAND,
189 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
190 }
191 }
192
193 res->name = pci_name(dev);
194
195 pci_read_config_dword(dev, pos, &l);
196 pci_write_config_dword(dev, pos, l | mask);
197 pci_read_config_dword(dev, pos, &sz);
198 pci_write_config_dword(dev, pos, l);
199
200 /*
201 * All bits set in sz means the device isn't working properly.
202 * If the BAR isn't implemented, all bits must be 0. If it's a
203 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
204 * 1 must be clear.
205 */
206 if (sz == 0xffffffff)
207 sz = 0;
208
209 /*
210 * I don't know how l can have all bits set. Copied from old code.
211 * Maybe it fixes a bug on some ancient platform.
212 */
213 if (l == 0xffffffff)
214 l = 0;
215
216 if (type == pci_bar_unknown) {
217 res->flags = decode_bar(dev, l);
218 res->flags |= IORESOURCE_SIZEALIGN;
219 if (res->flags & IORESOURCE_IO) {
220 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
221 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
222 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
223 } else {
224 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
225 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
226 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
227 }
228 } else {
229 if (l & PCI_ROM_ADDRESS_ENABLE)
230 res->flags |= IORESOURCE_ROM_ENABLE;
231 l64 = l & PCI_ROM_ADDRESS_MASK;
232 sz64 = sz & PCI_ROM_ADDRESS_MASK;
233 mask64 = PCI_ROM_ADDRESS_MASK;
234 }
235
236 if (res->flags & IORESOURCE_MEM_64) {
237 pci_read_config_dword(dev, pos + 4, &l);
238 pci_write_config_dword(dev, pos + 4, ~0);
239 pci_read_config_dword(dev, pos + 4, &sz);
240 pci_write_config_dword(dev, pos + 4, l);
241
242 l64 |= ((u64)l << 32);
243 sz64 |= ((u64)sz << 32);
244 mask64 |= ((u64)~0 << 32);
245 }
246
247 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
248 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
249
250 if (!sz64)
251 goto fail;
252
253 sz64 = pci_size(l64, sz64, mask64);
254 if (!sz64) {
255 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
256 pos);
257 goto fail;
258 }
259
260 if (res->flags & IORESOURCE_MEM_64) {
261 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
262 && sz64 > 0x100000000ULL) {
263 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
264 res->start = 0;
265 res->end = 0;
266 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
267 pos, (unsigned long long)sz64);
268 goto out;
269 }
270
271 if ((sizeof(pci_bus_addr_t) < 8) && l) {
272 /* Above 32-bit boundary; try to reallocate */
273 res->flags |= IORESOURCE_UNSET;
274 res->start = 0;
275 res->end = sz64;
276 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
277 pos, (unsigned long long)l64);
278 goto out;
279 }
280 }
281
282 region.start = l64;
283 region.end = l64 + sz64;
284
285 pcibios_bus_to_resource(dev->bus, res, &region);
286 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
287
288 /*
289 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
290 * the corresponding resource address (the physical address used by
291 * the CPU. Converting that resource address back to a bus address
292 * should yield the original BAR value:
293 *
294 * resource_to_bus(bus_to_resource(A)) == A
295 *
296 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
297 * be claimed by the device.
298 */
299 if (inverted_region.start != region.start) {
300 res->flags |= IORESOURCE_UNSET;
301 res->start = 0;
302 res->end = region.end - region.start;
303 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
304 pos, (unsigned long long)region.start);
305 }
306
307 goto out;
308
309
310 fail:
311 res->flags = 0;
312 out:
313 if (res->flags)
314 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
315
316 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
317 }
318
319 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
320 {
321 unsigned int pos, reg;
322
323 if (dev->non_compliant_bars)
324 return;
325
326 for (pos = 0; pos < howmany; pos++) {
327 struct resource *res = &dev->resource[pos];
328 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
329 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
330 }
331
332 if (rom) {
333 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
334 dev->rom_base_reg = rom;
335 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
336 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
337 __pci_read_base(dev, pci_bar_mem32, res, rom);
338 }
339 }
340
341 static void pci_read_bridge_io(struct pci_bus *child)
342 {
343 struct pci_dev *dev = child->self;
344 u8 io_base_lo, io_limit_lo;
345 unsigned long io_mask, io_granularity, base, limit;
346 struct pci_bus_region region;
347 struct resource *res;
348
349 io_mask = PCI_IO_RANGE_MASK;
350 io_granularity = 0x1000;
351 if (dev->io_window_1k) {
352 /* Support 1K I/O space granularity */
353 io_mask = PCI_IO_1K_RANGE_MASK;
354 io_granularity = 0x400;
355 }
356
357 res = child->resource[0];
358 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
359 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
360 base = (io_base_lo & io_mask) << 8;
361 limit = (io_limit_lo & io_mask) << 8;
362
363 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
364 u16 io_base_hi, io_limit_hi;
365
366 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
367 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
368 base |= ((unsigned long) io_base_hi << 16);
369 limit |= ((unsigned long) io_limit_hi << 16);
370 }
371
372 if (base <= limit) {
373 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
374 region.start = base;
375 region.end = limit + io_granularity - 1;
376 pcibios_bus_to_resource(dev->bus, res, &region);
377 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
378 }
379 }
380
381 static void pci_read_bridge_mmio(struct pci_bus *child)
382 {
383 struct pci_dev *dev = child->self;
384 u16 mem_base_lo, mem_limit_lo;
385 unsigned long base, limit;
386 struct pci_bus_region region;
387 struct resource *res;
388
389 res = child->resource[1];
390 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
391 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
392 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
393 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
394 if (base <= limit) {
395 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
396 region.start = base;
397 region.end = limit + 0xfffff;
398 pcibios_bus_to_resource(dev->bus, res, &region);
399 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
400 }
401 }
402
403 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
404 {
405 struct pci_dev *dev = child->self;
406 u16 mem_base_lo, mem_limit_lo;
407 u64 base64, limit64;
408 pci_bus_addr_t base, limit;
409 struct pci_bus_region region;
410 struct resource *res;
411
412 res = child->resource[2];
413 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
414 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
415 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
416 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
417
418 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
419 u32 mem_base_hi, mem_limit_hi;
420
421 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
422 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
423
424 /*
425 * Some bridges set the base > limit by default, and some
426 * (broken) BIOSes do not initialize them. If we find
427 * this, just assume they are not being used.
428 */
429 if (mem_base_hi <= mem_limit_hi) {
430 base64 |= (u64) mem_base_hi << 32;
431 limit64 |= (u64) mem_limit_hi << 32;
432 }
433 }
434
435 base = (pci_bus_addr_t) base64;
436 limit = (pci_bus_addr_t) limit64;
437
438 if (base != base64) {
439 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
440 (unsigned long long) base64);
441 return;
442 }
443
444 if (base <= limit) {
445 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
446 IORESOURCE_MEM | IORESOURCE_PREFETCH;
447 if (res->flags & PCI_PREF_RANGE_TYPE_64)
448 res->flags |= IORESOURCE_MEM_64;
449 region.start = base;
450 region.end = limit + 0xfffff;
451 pcibios_bus_to_resource(dev->bus, res, &region);
452 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
453 }
454 }
455
456 void pci_read_bridge_bases(struct pci_bus *child)
457 {
458 struct pci_dev *dev = child->self;
459 struct resource *res;
460 int i;
461
462 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
463 return;
464
465 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
466 &child->busn_res,
467 dev->transparent ? " (subtractive decode)" : "");
468
469 pci_bus_remove_resources(child);
470 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
471 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
472
473 pci_read_bridge_io(child);
474 pci_read_bridge_mmio(child);
475 pci_read_bridge_mmio_pref(child);
476
477 if (dev->transparent) {
478 pci_bus_for_each_resource(child->parent, res, i) {
479 if (res && res->flags) {
480 pci_bus_add_resource(child, res,
481 PCI_SUBTRACTIVE_DECODE);
482 dev_printk(KERN_DEBUG, &dev->dev,
483 " bridge window %pR (subtractive decode)\n",
484 res);
485 }
486 }
487 }
488 }
489
490 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
491 {
492 struct pci_bus *b;
493
494 b = kzalloc(sizeof(*b), GFP_KERNEL);
495 if (!b)
496 return NULL;
497
498 INIT_LIST_HEAD(&b->node);
499 INIT_LIST_HEAD(&b->children);
500 INIT_LIST_HEAD(&b->devices);
501 INIT_LIST_HEAD(&b->slots);
502 INIT_LIST_HEAD(&b->resources);
503 b->max_bus_speed = PCI_SPEED_UNKNOWN;
504 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
505 #ifdef CONFIG_PCI_DOMAINS_GENERIC
506 if (parent)
507 b->domain_nr = parent->domain_nr;
508 #endif
509 return b;
510 }
511
512 static void pci_release_host_bridge_dev(struct device *dev)
513 {
514 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
515
516 if (bridge->release_fn)
517 bridge->release_fn(bridge);
518
519 pci_free_resource_list(&bridge->windows);
520
521 kfree(bridge);
522 }
523
524 static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
525 {
526 struct pci_host_bridge *bridge;
527
528 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
529 if (!bridge)
530 return NULL;
531
532 INIT_LIST_HEAD(&bridge->windows);
533 bridge->bus = b;
534 return bridge;
535 }
536
537 static const unsigned char pcix_bus_speed[] = {
538 PCI_SPEED_UNKNOWN, /* 0 */
539 PCI_SPEED_66MHz_PCIX, /* 1 */
540 PCI_SPEED_100MHz_PCIX, /* 2 */
541 PCI_SPEED_133MHz_PCIX, /* 3 */
542 PCI_SPEED_UNKNOWN, /* 4 */
543 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
544 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
545 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
546 PCI_SPEED_UNKNOWN, /* 8 */
547 PCI_SPEED_66MHz_PCIX_266, /* 9 */
548 PCI_SPEED_100MHz_PCIX_266, /* A */
549 PCI_SPEED_133MHz_PCIX_266, /* B */
550 PCI_SPEED_UNKNOWN, /* C */
551 PCI_SPEED_66MHz_PCIX_533, /* D */
552 PCI_SPEED_100MHz_PCIX_533, /* E */
553 PCI_SPEED_133MHz_PCIX_533 /* F */
554 };
555
556 const unsigned char pcie_link_speed[] = {
557 PCI_SPEED_UNKNOWN, /* 0 */
558 PCIE_SPEED_2_5GT, /* 1 */
559 PCIE_SPEED_5_0GT, /* 2 */
560 PCIE_SPEED_8_0GT, /* 3 */
561 PCI_SPEED_UNKNOWN, /* 4 */
562 PCI_SPEED_UNKNOWN, /* 5 */
563 PCI_SPEED_UNKNOWN, /* 6 */
564 PCI_SPEED_UNKNOWN, /* 7 */
565 PCI_SPEED_UNKNOWN, /* 8 */
566 PCI_SPEED_UNKNOWN, /* 9 */
567 PCI_SPEED_UNKNOWN, /* A */
568 PCI_SPEED_UNKNOWN, /* B */
569 PCI_SPEED_UNKNOWN, /* C */
570 PCI_SPEED_UNKNOWN, /* D */
571 PCI_SPEED_UNKNOWN, /* E */
572 PCI_SPEED_UNKNOWN /* F */
573 };
574
575 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
576 {
577 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
578 }
579 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
580
581 static unsigned char agp_speeds[] = {
582 AGP_UNKNOWN,
583 AGP_1X,
584 AGP_2X,
585 AGP_4X,
586 AGP_8X
587 };
588
589 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
590 {
591 int index = 0;
592
593 if (agpstat & 4)
594 index = 3;
595 else if (agpstat & 2)
596 index = 2;
597 else if (agpstat & 1)
598 index = 1;
599 else
600 goto out;
601
602 if (agp3) {
603 index += 2;
604 if (index == 5)
605 index = 0;
606 }
607
608 out:
609 return agp_speeds[index];
610 }
611
612 static void pci_set_bus_speed(struct pci_bus *bus)
613 {
614 struct pci_dev *bridge = bus->self;
615 int pos;
616
617 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
618 if (!pos)
619 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
620 if (pos) {
621 u32 agpstat, agpcmd;
622
623 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
624 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
625
626 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
627 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
628 }
629
630 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
631 if (pos) {
632 u16 status;
633 enum pci_bus_speed max;
634
635 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
636 &status);
637
638 if (status & PCI_X_SSTATUS_533MHZ) {
639 max = PCI_SPEED_133MHz_PCIX_533;
640 } else if (status & PCI_X_SSTATUS_266MHZ) {
641 max = PCI_SPEED_133MHz_PCIX_266;
642 } else if (status & PCI_X_SSTATUS_133MHZ) {
643 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
644 max = PCI_SPEED_133MHz_PCIX_ECC;
645 else
646 max = PCI_SPEED_133MHz_PCIX;
647 } else {
648 max = PCI_SPEED_66MHz_PCIX;
649 }
650
651 bus->max_bus_speed = max;
652 bus->cur_bus_speed = pcix_bus_speed[
653 (status & PCI_X_SSTATUS_FREQ) >> 6];
654
655 return;
656 }
657
658 if (pci_is_pcie(bridge)) {
659 u32 linkcap;
660 u16 linksta;
661
662 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
663 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
664
665 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
666 pcie_update_link_speed(bus, linksta);
667 }
668 }
669
670 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
671 {
672 struct irq_domain *d;
673
674 /*
675 * Any firmware interface that can resolve the msi_domain
676 * should be called from here.
677 */
678 d = pci_host_bridge_of_msi_domain(bus);
679
680 return d;
681 }
682
683 static void pci_set_bus_msi_domain(struct pci_bus *bus)
684 {
685 struct irq_domain *d;
686 struct pci_bus *b;
687
688 /*
689 * The bus can be a root bus, a subordinate bus, or a virtual bus
690 * created by an SR-IOV device. Walk up to the first bridge device
691 * found or derive the domain from the host bridge.
692 */
693 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
694 if (b->self)
695 d = dev_get_msi_domain(&b->self->dev);
696 }
697
698 if (!d)
699 d = pci_host_bridge_msi_domain(b);
700
701 dev_set_msi_domain(&bus->dev, d);
702 }
703
704 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
705 struct pci_dev *bridge, int busnr)
706 {
707 struct pci_bus *child;
708 int i;
709 int ret;
710
711 /*
712 * Allocate a new bus, and inherit stuff from the parent..
713 */
714 child = pci_alloc_bus(parent);
715 if (!child)
716 return NULL;
717
718 child->parent = parent;
719 child->ops = parent->ops;
720 child->msi = parent->msi;
721 child->sysdata = parent->sysdata;
722 child->bus_flags = parent->bus_flags;
723
724 /* initialize some portions of the bus device, but don't register it
725 * now as the parent is not properly set up yet.
726 */
727 child->dev.class = &pcibus_class;
728 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
729
730 /*
731 * Set up the primary, secondary and subordinate
732 * bus numbers.
733 */
734 child->number = child->busn_res.start = busnr;
735 child->primary = parent->busn_res.start;
736 child->busn_res.end = 0xff;
737
738 if (!bridge) {
739 child->dev.parent = parent->bridge;
740 goto add_dev;
741 }
742
743 child->self = bridge;
744 child->bridge = get_device(&bridge->dev);
745 child->dev.parent = child->bridge;
746 pci_set_bus_of_node(child);
747 pci_set_bus_speed(child);
748
749 /* Set up default resource pointers and names.. */
750 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
751 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
752 child->resource[i]->name = child->name;
753 }
754 bridge->subordinate = child;
755
756 add_dev:
757 pci_set_bus_msi_domain(child);
758 ret = device_register(&child->dev);
759 WARN_ON(ret < 0);
760
761 pcibios_add_bus(child);
762
763 /* Create legacy_io and legacy_mem files for this bus */
764 pci_create_legacy_files(child);
765
766 return child;
767 }
768
769 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
770 int busnr)
771 {
772 struct pci_bus *child;
773
774 child = pci_alloc_child_bus(parent, dev, busnr);
775 if (child) {
776 down_write(&pci_bus_sem);
777 list_add_tail(&child->node, &parent->children);
778 up_write(&pci_bus_sem);
779 }
780 return child;
781 }
782 EXPORT_SYMBOL(pci_add_new_bus);
783
784 static void pci_enable_crs(struct pci_dev *pdev)
785 {
786 u16 root_cap = 0;
787
788 /* Enable CRS Software Visibility if supported */
789 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
790 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
791 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
792 PCI_EXP_RTCTL_CRSSVE);
793 }
794
795 /*
796 * If it's a bridge, configure it and scan the bus behind it.
797 * For CardBus bridges, we don't scan behind as the devices will
798 * be handled by the bridge driver itself.
799 *
800 * We need to process bridges in two passes -- first we scan those
801 * already configured by the BIOS and after we are done with all of
802 * them, we proceed to assigning numbers to the remaining buses in
803 * order to avoid overlaps between old and new bus numbers.
804 */
805 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
806 {
807 struct pci_bus *child;
808 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
809 u32 buses, i, j = 0;
810 u16 bctl;
811 u8 primary, secondary, subordinate;
812 int broken = 0;
813
814 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
815 primary = buses & 0xFF;
816 secondary = (buses >> 8) & 0xFF;
817 subordinate = (buses >> 16) & 0xFF;
818
819 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
820 secondary, subordinate, pass);
821
822 if (!primary && (primary != bus->number) && secondary && subordinate) {
823 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
824 primary = bus->number;
825 }
826
827 /* Check if setup is sensible at all */
828 if (!pass &&
829 (primary != bus->number || secondary <= bus->number ||
830 secondary > subordinate)) {
831 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
832 secondary, subordinate);
833 broken = 1;
834 }
835
836 /* Disable MasterAbortMode during probing to avoid reporting
837 of bus errors (in some architectures) */
838 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
839 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
840 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
841
842 pci_enable_crs(dev);
843
844 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
845 !is_cardbus && !broken) {
846 unsigned int cmax;
847 /*
848 * Bus already configured by firmware, process it in the first
849 * pass and just note the configuration.
850 */
851 if (pass)
852 goto out;
853
854 /*
855 * The bus might already exist for two reasons: Either we are
856 * rescanning the bus or the bus is reachable through more than
857 * one bridge. The second case can happen with the i450NX
858 * chipset.
859 */
860 child = pci_find_bus(pci_domain_nr(bus), secondary);
861 if (!child) {
862 child = pci_add_new_bus(bus, dev, secondary);
863 if (!child)
864 goto out;
865 child->primary = primary;
866 pci_bus_insert_busn_res(child, secondary, subordinate);
867 child->bridge_ctl = bctl;
868 }
869
870 cmax = pci_scan_child_bus(child);
871 if (cmax > subordinate)
872 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
873 subordinate, cmax);
874 /* subordinate should equal child->busn_res.end */
875 if (subordinate > max)
876 max = subordinate;
877 } else {
878 /*
879 * We need to assign a number to this bus which we always
880 * do in the second pass.
881 */
882 if (!pass) {
883 if (pcibios_assign_all_busses() || broken || is_cardbus)
884 /* Temporarily disable forwarding of the
885 configuration cycles on all bridges in
886 this bus segment to avoid possible
887 conflicts in the second pass between two
888 bridges programmed with overlapping
889 bus ranges. */
890 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
891 buses & ~0xffffff);
892 goto out;
893 }
894
895 /* Clear errors */
896 pci_write_config_word(dev, PCI_STATUS, 0xffff);
897
898 /* Prevent assigning a bus number that already exists.
899 * This can happen when a bridge is hot-plugged, so in
900 * this case we only re-scan this bus. */
901 child = pci_find_bus(pci_domain_nr(bus), max+1);
902 if (!child) {
903 child = pci_add_new_bus(bus, dev, max+1);
904 if (!child)
905 goto out;
906 pci_bus_insert_busn_res(child, max+1, 0xff);
907 }
908 max++;
909 buses = (buses & 0xff000000)
910 | ((unsigned int)(child->primary) << 0)
911 | ((unsigned int)(child->busn_res.start) << 8)
912 | ((unsigned int)(child->busn_res.end) << 16);
913
914 /*
915 * yenta.c forces a secondary latency timer of 176.
916 * Copy that behaviour here.
917 */
918 if (is_cardbus) {
919 buses &= ~0xff000000;
920 buses |= CARDBUS_LATENCY_TIMER << 24;
921 }
922
923 /*
924 * We need to blast all three values with a single write.
925 */
926 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
927
928 if (!is_cardbus) {
929 child->bridge_ctl = bctl;
930 max = pci_scan_child_bus(child);
931 } else {
932 /*
933 * For CardBus bridges, we leave 4 bus numbers
934 * as cards with a PCI-to-PCI bridge can be
935 * inserted later.
936 */
937 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
938 struct pci_bus *parent = bus;
939 if (pci_find_bus(pci_domain_nr(bus),
940 max+i+1))
941 break;
942 while (parent->parent) {
943 if ((!pcibios_assign_all_busses()) &&
944 (parent->busn_res.end > max) &&
945 (parent->busn_res.end <= max+i)) {
946 j = 1;
947 }
948 parent = parent->parent;
949 }
950 if (j) {
951 /*
952 * Often, there are two cardbus bridges
953 * -- try to leave one valid bus number
954 * for each one.
955 */
956 i /= 2;
957 break;
958 }
959 }
960 max += i;
961 }
962 /*
963 * Set the subordinate bus number to its real value.
964 */
965 pci_bus_update_busn_res_end(child, max);
966 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
967 }
968
969 sprintf(child->name,
970 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
971 pci_domain_nr(bus), child->number);
972
973 /* Has only triggered on CardBus, fixup is in yenta_socket */
974 while (bus->parent) {
975 if ((child->busn_res.end > bus->busn_res.end) ||
976 (child->number > bus->busn_res.end) ||
977 (child->number < bus->number) ||
978 (child->busn_res.end < bus->number)) {
979 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
980 &child->busn_res,
981 (bus->number > child->busn_res.end &&
982 bus->busn_res.end < child->number) ?
983 "wholly" : "partially",
984 bus->self->transparent ? " transparent" : "",
985 dev_name(&bus->dev),
986 &bus->busn_res);
987 }
988 bus = bus->parent;
989 }
990
991 out:
992 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
993
994 return max;
995 }
996 EXPORT_SYMBOL(pci_scan_bridge);
997
998 /*
999 * Read interrupt line and base address registers.
1000 * The architecture-dependent code can tweak these, of course.
1001 */
1002 static void pci_read_irq(struct pci_dev *dev)
1003 {
1004 unsigned char irq;
1005
1006 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1007 dev->pin = irq;
1008 if (irq)
1009 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1010 dev->irq = irq;
1011 }
1012
1013 void set_pcie_port_type(struct pci_dev *pdev)
1014 {
1015 int pos;
1016 u16 reg16;
1017 int type;
1018 struct pci_dev *parent;
1019
1020 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1021 if (!pos)
1022 return;
1023
1024 pdev->pcie_cap = pos;
1025 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
1026 pdev->pcie_flags_reg = reg16;
1027 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
1028 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1029
1030 /*
1031 * A Root Port or a PCI-to-PCIe bridge is always the upstream end
1032 * of a Link. No PCIe component has two Links. Two Links are
1033 * connected by a Switch that has a Port on each Link and internal
1034 * logic to connect the two Ports.
1035 */
1036 type = pci_pcie_type(pdev);
1037 if (type == PCI_EXP_TYPE_ROOT_PORT ||
1038 type == PCI_EXP_TYPE_PCIE_BRIDGE)
1039 pdev->has_secondary_link = 1;
1040 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1041 type == PCI_EXP_TYPE_DOWNSTREAM) {
1042 parent = pci_upstream_bridge(pdev);
1043
1044 /*
1045 * Usually there's an upstream device (Root Port or Switch
1046 * Downstream Port), but we can't assume one exists.
1047 */
1048 if (parent && !parent->has_secondary_link)
1049 pdev->has_secondary_link = 1;
1050 }
1051 }
1052
1053 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1054 {
1055 u32 reg32;
1056
1057 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
1058 if (reg32 & PCI_EXP_SLTCAP_HPC)
1059 pdev->is_hotplug_bridge = 1;
1060 }
1061
1062 /**
1063 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1064 * @dev: PCI device
1065 *
1066 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1067 * when forwarding a type1 configuration request the bridge must check that
1068 * the extended register address field is zero. The bridge is not permitted
1069 * to forward the transactions and must handle it as an Unsupported Request.
1070 * Some bridges do not follow this rule and simply drop the extended register
1071 * bits, resulting in the standard config space being aliased, every 256
1072 * bytes across the entire configuration space. Test for this condition by
1073 * comparing the first dword of each potential alias to the vendor/device ID.
1074 * Known offenders:
1075 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1076 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1077 */
1078 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1079 {
1080 #ifdef CONFIG_PCI_QUIRKS
1081 int pos;
1082 u32 header, tmp;
1083
1084 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1085
1086 for (pos = PCI_CFG_SPACE_SIZE;
1087 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1088 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1089 || header != tmp)
1090 return false;
1091 }
1092
1093 return true;
1094 #else
1095 return false;
1096 #endif
1097 }
1098
1099 /**
1100 * pci_cfg_space_size - get the configuration space size of the PCI device.
1101 * @dev: PCI device
1102 *
1103 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1104 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1105 * access it. Maybe we don't have a way to generate extended config space
1106 * accesses, or the device is behind a reverse Express bridge. So we try
1107 * reading the dword at 0x100 which must either be 0 or a valid extended
1108 * capability header.
1109 */
1110 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1111 {
1112 u32 status;
1113 int pos = PCI_CFG_SPACE_SIZE;
1114
1115 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1116 goto fail;
1117 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1118 goto fail;
1119
1120 return PCI_CFG_SPACE_EXP_SIZE;
1121
1122 fail:
1123 return PCI_CFG_SPACE_SIZE;
1124 }
1125
1126 int pci_cfg_space_size(struct pci_dev *dev)
1127 {
1128 int pos;
1129 u32 status;
1130 u16 class;
1131
1132 class = dev->class >> 8;
1133 if (class == PCI_CLASS_BRIDGE_HOST)
1134 return pci_cfg_space_size_ext(dev);
1135
1136 if (!pci_is_pcie(dev)) {
1137 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1138 if (!pos)
1139 goto fail;
1140
1141 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1142 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1143 goto fail;
1144 }
1145
1146 return pci_cfg_space_size_ext(dev);
1147
1148 fail:
1149 return PCI_CFG_SPACE_SIZE;
1150 }
1151
1152 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1153
1154 void pci_msi_setup_pci_dev(struct pci_dev *dev)
1155 {
1156 /*
1157 * Disable the MSI hardware to avoid screaming interrupts
1158 * during boot. This is the power on reset default so
1159 * usually this should be a noop.
1160 */
1161 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1162 if (dev->msi_cap)
1163 pci_msi_set_enable(dev, 0);
1164
1165 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1166 if (dev->msix_cap)
1167 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1168 }
1169
1170 /**
1171 * pci_setup_device - fill in class and map information of a device
1172 * @dev: the device structure to fill
1173 *
1174 * Initialize the device structure with information about the device's
1175 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1176 * Called at initialisation of the PCI subsystem and by CardBus services.
1177 * Returns 0 on success and negative if unknown type of device (not normal,
1178 * bridge or CardBus).
1179 */
1180 int pci_setup_device(struct pci_dev *dev)
1181 {
1182 u32 class;
1183 u16 cmd;
1184 u8 hdr_type;
1185 int pos = 0;
1186 struct pci_bus_region region;
1187 struct resource *res;
1188
1189 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1190 return -EIO;
1191
1192 dev->sysdata = dev->bus->sysdata;
1193 dev->dev.parent = dev->bus->bridge;
1194 dev->dev.bus = &pci_bus_type;
1195 dev->hdr_type = hdr_type & 0x7f;
1196 dev->multifunction = !!(hdr_type & 0x80);
1197 dev->error_state = pci_channel_io_normal;
1198 set_pcie_port_type(dev);
1199
1200 pci_dev_assign_slot(dev);
1201 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1202 set this higher, assuming the system even supports it. */
1203 dev->dma_mask = DMA_BIT_MASK(36);
1204
1205 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1206 dev->bus->number, PCI_SLOT(dev->devfn),
1207 PCI_FUNC(dev->devfn));
1208
1209 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1210 dev->revision = class & 0xff;
1211 dev->class = class >> 8; /* upper 3 bytes */
1212
1213 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1214 dev->vendor, dev->device, dev->hdr_type, dev->class);
1215
1216 /* need to have dev->class ready */
1217 dev->cfg_size = pci_cfg_space_size(dev);
1218
1219 /* "Unknown power state" */
1220 dev->current_state = PCI_UNKNOWN;
1221
1222 pci_msi_setup_pci_dev(dev);
1223
1224 /* Early fixups, before probing the BARs */
1225 pci_fixup_device(pci_fixup_early, dev);
1226 /* device class may be changed after fixup */
1227 class = dev->class >> 8;
1228
1229 if (dev->non_compliant_bars) {
1230 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1231 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1232 dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1233 cmd &= ~PCI_COMMAND_IO;
1234 cmd &= ~PCI_COMMAND_MEMORY;
1235 pci_write_config_word(dev, PCI_COMMAND, cmd);
1236 }
1237 }
1238
1239 switch (dev->hdr_type) { /* header type */
1240 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1241 if (class == PCI_CLASS_BRIDGE_PCI)
1242 goto bad;
1243 pci_read_irq(dev);
1244 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1245 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1246 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1247
1248 /*
1249 * Do the ugly legacy mode stuff here rather than broken chip
1250 * quirk code. Legacy mode ATA controllers have fixed
1251 * addresses. These are not always echoed in BAR0-3, and
1252 * BAR0-3 in a few cases contain junk!
1253 */
1254 if (class == PCI_CLASS_STORAGE_IDE) {
1255 u8 progif;
1256 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1257 if ((progif & 1) == 0) {
1258 region.start = 0x1F0;
1259 region.end = 0x1F7;
1260 res = &dev->resource[0];
1261 res->flags = LEGACY_IO_RESOURCE;
1262 pcibios_bus_to_resource(dev->bus, res, &region);
1263 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1264 res);
1265 region.start = 0x3F6;
1266 region.end = 0x3F6;
1267 res = &dev->resource[1];
1268 res->flags = LEGACY_IO_RESOURCE;
1269 pcibios_bus_to_resource(dev->bus, res, &region);
1270 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1271 res);
1272 }
1273 if ((progif & 4) == 0) {
1274 region.start = 0x170;
1275 region.end = 0x177;
1276 res = &dev->resource[2];
1277 res->flags = LEGACY_IO_RESOURCE;
1278 pcibios_bus_to_resource(dev->bus, res, &region);
1279 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1280 res);
1281 region.start = 0x376;
1282 region.end = 0x376;
1283 res = &dev->resource[3];
1284 res->flags = LEGACY_IO_RESOURCE;
1285 pcibios_bus_to_resource(dev->bus, res, &region);
1286 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1287 res);
1288 }
1289 }
1290 break;
1291
1292 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1293 if (class != PCI_CLASS_BRIDGE_PCI)
1294 goto bad;
1295 /* The PCI-to-PCI bridge spec requires that subtractive
1296 decoding (i.e. transparent) bridge must have programming
1297 interface code of 0x01. */
1298 pci_read_irq(dev);
1299 dev->transparent = ((dev->class & 0xff) == 1);
1300 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1301 set_pcie_hotplug_bridge(dev);
1302 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1303 if (pos) {
1304 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1305 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1306 }
1307 break;
1308
1309 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1310 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1311 goto bad;
1312 pci_read_irq(dev);
1313 pci_read_bases(dev, 1, 0);
1314 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1315 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1316 break;
1317
1318 default: /* unknown header */
1319 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1320 dev->hdr_type);
1321 return -EIO;
1322
1323 bad:
1324 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1325 dev->class, dev->hdr_type);
1326 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1327 }
1328
1329 /* We found a fine healthy device, go go go... */
1330 return 0;
1331 }
1332
1333 static void pci_configure_mps(struct pci_dev *dev)
1334 {
1335 struct pci_dev *bridge = pci_upstream_bridge(dev);
1336 int mps, p_mps, rc;
1337
1338 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1339 return;
1340
1341 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
1342 if (dev->is_virtfn)
1343 return;
1344
1345 mps = pcie_get_mps(dev);
1346 p_mps = pcie_get_mps(bridge);
1347
1348 if (mps == p_mps)
1349 return;
1350
1351 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1352 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1353 mps, pci_name(bridge), p_mps);
1354 return;
1355 }
1356
1357 /*
1358 * Fancier MPS configuration is done later by
1359 * pcie_bus_configure_settings()
1360 */
1361 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1362 return;
1363
1364 rc = pcie_set_mps(dev, p_mps);
1365 if (rc) {
1366 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1367 p_mps);
1368 return;
1369 }
1370
1371 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1372 p_mps, mps, 128 << dev->pcie_mpss);
1373 }
1374
1375 static struct hpp_type0 pci_default_type0 = {
1376 .revision = 1,
1377 .cache_line_size = 8,
1378 .latency_timer = 0x40,
1379 .enable_serr = 0,
1380 .enable_perr = 0,
1381 };
1382
1383 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1384 {
1385 u16 pci_cmd, pci_bctl;
1386
1387 if (!hpp)
1388 hpp = &pci_default_type0;
1389
1390 if (hpp->revision > 1) {
1391 dev_warn(&dev->dev,
1392 "PCI settings rev %d not supported; using defaults\n",
1393 hpp->revision);
1394 hpp = &pci_default_type0;
1395 }
1396
1397 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1398 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1399 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1400 if (hpp->enable_serr)
1401 pci_cmd |= PCI_COMMAND_SERR;
1402 if (hpp->enable_perr)
1403 pci_cmd |= PCI_COMMAND_PARITY;
1404 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1405
1406 /* Program bridge control value */
1407 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1408 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1409 hpp->latency_timer);
1410 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1411 if (hpp->enable_serr)
1412 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1413 if (hpp->enable_perr)
1414 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1415 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1416 }
1417 }
1418
1419 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1420 {
1421 int pos;
1422
1423 if (!hpp)
1424 return;
1425
1426 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1427 if (!pos)
1428 return;
1429
1430 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1431 }
1432
1433 static bool pcie_root_rcb_set(struct pci_dev *dev)
1434 {
1435 struct pci_dev *rp = pcie_find_root_port(dev);
1436 u16 lnkctl;
1437
1438 if (!rp)
1439 return false;
1440
1441 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
1442 if (lnkctl & PCI_EXP_LNKCTL_RCB)
1443 return true;
1444
1445 return false;
1446 }
1447
1448 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1449 {
1450 int pos;
1451 u32 reg32;
1452
1453 if (!hpp)
1454 return;
1455
1456 if (!pci_is_pcie(dev))
1457 return;
1458
1459 if (hpp->revision > 1) {
1460 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1461 hpp->revision);
1462 return;
1463 }
1464
1465 /*
1466 * Don't allow _HPX to change MPS or MRRS settings. We manage
1467 * those to make sure they're consistent with the rest of the
1468 * platform.
1469 */
1470 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1471 PCI_EXP_DEVCTL_READRQ;
1472 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1473 PCI_EXP_DEVCTL_READRQ);
1474
1475 /* Initialize Device Control Register */
1476 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1477 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1478
1479 /* Initialize Link Control Register */
1480 if (pcie_cap_has_lnkctl(dev)) {
1481
1482 /*
1483 * If the Root Port supports Read Completion Boundary of
1484 * 128, set RCB to 128. Otherwise, clear it.
1485 */
1486 hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
1487 hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
1488 if (pcie_root_rcb_set(dev))
1489 hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
1490
1491 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1492 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1493 }
1494
1495 /* Find Advanced Error Reporting Enhanced Capability */
1496 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1497 if (!pos)
1498 return;
1499
1500 /* Initialize Uncorrectable Error Mask Register */
1501 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
1502 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1503 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1504
1505 /* Initialize Uncorrectable Error Severity Register */
1506 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
1507 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1508 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1509
1510 /* Initialize Correctable Error Mask Register */
1511 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
1512 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1513 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1514
1515 /* Initialize Advanced Error Capabilities and Control Register */
1516 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
1517 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1518 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1519
1520 /*
1521 * FIXME: The following two registers are not supported yet.
1522 *
1523 * o Secondary Uncorrectable Error Severity Register
1524 * o Secondary Uncorrectable Error Mask Register
1525 */
1526 }
1527
1528 static void pci_configure_device(struct pci_dev *dev)
1529 {
1530 struct hotplug_params hpp;
1531 int ret;
1532
1533 pci_configure_mps(dev);
1534
1535 memset(&hpp, 0, sizeof(hpp));
1536 ret = pci_get_hp_params(dev, &hpp);
1537 if (ret)
1538 return;
1539
1540 program_hpp_type2(dev, hpp.t2);
1541 program_hpp_type1(dev, hpp.t1);
1542 program_hpp_type0(dev, hpp.t0);
1543 }
1544
1545 static void pci_release_capabilities(struct pci_dev *dev)
1546 {
1547 pci_vpd_release(dev);
1548 pci_iov_release(dev);
1549 pci_free_cap_save_buffers(dev);
1550 }
1551
1552 /**
1553 * pci_release_dev - free a pci device structure when all users of it are finished.
1554 * @dev: device that's been disconnected
1555 *
1556 * Will be called only by the device core when all users of this pci device are
1557 * done.
1558 */
1559 static void pci_release_dev(struct device *dev)
1560 {
1561 struct pci_dev *pci_dev;
1562
1563 pci_dev = to_pci_dev(dev);
1564 pci_release_capabilities(pci_dev);
1565 pci_release_of_node(pci_dev);
1566 pcibios_release_device(pci_dev);
1567 pci_bus_put(pci_dev->bus);
1568 kfree(pci_dev->driver_override);
1569 kfree(pci_dev);
1570 }
1571
1572 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1573 {
1574 struct pci_dev *dev;
1575
1576 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1577 if (!dev)
1578 return NULL;
1579
1580 INIT_LIST_HEAD(&dev->bus_list);
1581 dev->dev.type = &pci_dev_type;
1582 dev->bus = pci_bus_get(bus);
1583
1584 return dev;
1585 }
1586 EXPORT_SYMBOL(pci_alloc_dev);
1587
1588 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1589 int crs_timeout)
1590 {
1591 int delay = 1;
1592
1593 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1594 return false;
1595
1596 /* some broken boards return 0 or ~0 if a slot is empty: */
1597 if (*l == 0xffffffff || *l == 0x00000000 ||
1598 *l == 0x0000ffff || *l == 0xffff0000)
1599 return false;
1600
1601 /*
1602 * Configuration Request Retry Status. Some root ports return the
1603 * actual device ID instead of the synthetic ID (0xFFFF) required
1604 * by the PCIe spec. Ignore the device ID and only check for
1605 * (vendor id == 1).
1606 */
1607 while ((*l & 0xffff) == 0x0001) {
1608 if (!crs_timeout)
1609 return false;
1610
1611 msleep(delay);
1612 delay *= 2;
1613 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1614 return false;
1615 /* Card hasn't responded in 60 seconds? Must be stuck. */
1616 if (delay > crs_timeout) {
1617 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1618 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1619 PCI_FUNC(devfn));
1620 return false;
1621 }
1622 }
1623
1624 return true;
1625 }
1626 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1627
1628 /*
1629 * Read the config data for a PCI device, sanity-check it
1630 * and fill in the dev structure...
1631 */
1632 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1633 {
1634 struct pci_dev *dev;
1635 u32 l;
1636
1637 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1638 return NULL;
1639
1640 dev = pci_alloc_dev(bus);
1641 if (!dev)
1642 return NULL;
1643
1644 dev->devfn = devfn;
1645 dev->vendor = l & 0xffff;
1646 dev->device = (l >> 16) & 0xffff;
1647
1648 pci_set_of_node(dev);
1649
1650 if (pci_setup_device(dev)) {
1651 pci_bus_put(dev->bus);
1652 kfree(dev);
1653 return NULL;
1654 }
1655
1656 return dev;
1657 }
1658
1659 static void pci_init_capabilities(struct pci_dev *dev)
1660 {
1661 /* Enhanced Allocation */
1662 pci_ea_init(dev);
1663
1664 /* MSI/MSI-X list */
1665 pci_msi_init_pci_dev(dev);
1666
1667 /* Buffers for saving PCIe and PCI-X capabilities */
1668 pci_allocate_cap_save_buffers(dev);
1669
1670 /* Power Management */
1671 pci_pm_init(dev);
1672
1673 /* Vital Product Data */
1674 pci_vpd_pci22_init(dev);
1675
1676 /* Alternative Routing-ID Forwarding */
1677 pci_configure_ari(dev);
1678
1679 /* Single Root I/O Virtualization */
1680 pci_iov_init(dev);
1681
1682 /* Address Translation Services */
1683 pci_ats_init(dev);
1684
1685 /* Enable ACS P2P upstream forwarding */
1686 pci_enable_acs(dev);
1687
1688 pci_cleanup_aer_error_status_regs(dev);
1689 }
1690
1691 /*
1692 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1693 * devices. Firmware interfaces that can select the MSI domain on a
1694 * per-device basis should be called from here.
1695 */
1696 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
1697 {
1698 struct irq_domain *d;
1699
1700 /*
1701 * If a domain has been set through the pcibios_add_device
1702 * callback, then this is the one (platform code knows best).
1703 */
1704 d = dev_get_msi_domain(&dev->dev);
1705 if (d)
1706 return d;
1707
1708 /*
1709 * Let's see if we have a firmware interface able to provide
1710 * the domain.
1711 */
1712 d = pci_msi_get_device_domain(dev);
1713 if (d)
1714 return d;
1715
1716 return NULL;
1717 }
1718
1719 static void pci_set_msi_domain(struct pci_dev *dev)
1720 {
1721 struct irq_domain *d;
1722
1723 /*
1724 * If the platform or firmware interfaces cannot supply a
1725 * device-specific MSI domain, then inherit the default domain
1726 * from the host bridge itself.
1727 */
1728 d = pci_dev_msi_domain(dev);
1729 if (!d)
1730 d = dev_get_msi_domain(&dev->bus->dev);
1731
1732 dev_set_msi_domain(&dev->dev, d);
1733 }
1734
1735 /**
1736 * pci_dma_configure - Setup DMA configuration
1737 * @dev: ptr to pci_dev struct of the PCI device
1738 *
1739 * Function to update PCI devices's DMA configuration using the same
1740 * info from the OF node or ACPI node of host bridge's parent (if any).
1741 */
1742 static void pci_dma_configure(struct pci_dev *dev)
1743 {
1744 struct device *bridge = pci_get_host_bridge_device(dev);
1745
1746 if (IS_ENABLED(CONFIG_OF) &&
1747 bridge->parent && bridge->parent->of_node) {
1748 of_dma_configure(&dev->dev, bridge->parent->of_node);
1749 } else if (has_acpi_companion(bridge)) {
1750 struct acpi_device *adev = to_acpi_device_node(bridge->fwnode);
1751 enum dev_dma_attr attr = acpi_get_dma_attr(adev);
1752
1753 if (attr == DEV_DMA_NOT_SUPPORTED)
1754 dev_warn(&dev->dev, "DMA not supported.\n");
1755 else
1756 arch_setup_dma_ops(&dev->dev, 0, 0, NULL,
1757 attr == DEV_DMA_COHERENT);
1758 }
1759
1760 pci_put_host_bridge_device(bridge);
1761 }
1762
1763 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1764 {
1765 int ret;
1766
1767 pci_configure_device(dev);
1768
1769 device_initialize(&dev->dev);
1770 dev->dev.release = pci_release_dev;
1771
1772 set_dev_node(&dev->dev, pcibus_to_node(bus));
1773 dev->dev.dma_mask = &dev->dma_mask;
1774 dev->dev.dma_parms = &dev->dma_parms;
1775 dev->dev.coherent_dma_mask = DMA_BIT_MASK(36);
1776 pci_dma_configure(dev);
1777
1778 pci_set_dma_max_seg_size(dev, 65536);
1779 pci_set_dma_seg_boundary(dev, DMA_BIT_MASK(36));
1780
1781 /* Fix up broken headers */
1782 pci_fixup_device(pci_fixup_header, dev);
1783
1784 /* moved out from quirk header fixup code */
1785 pci_reassigndev_resource_alignment(dev);
1786
1787 /* Clear the state_saved flag. */
1788 dev->state_saved = false;
1789
1790 /* Initialize various capabilities */
1791 pci_init_capabilities(dev);
1792
1793 /*
1794 * Add the device to our list of discovered devices
1795 * and the bus list for fixup functions, etc.
1796 */
1797 down_write(&pci_bus_sem);
1798 list_add_tail(&dev->bus_list, &bus->devices);
1799 up_write(&pci_bus_sem);
1800
1801 ret = pcibios_add_device(dev);
1802 WARN_ON(ret < 0);
1803
1804 /* Setup MSI irq domain */
1805 pci_set_msi_domain(dev);
1806
1807 /* Notifier could use PCI capabilities */
1808 dev->match_driver = false;
1809 ret = device_add(&dev->dev);
1810 WARN_ON(ret < 0);
1811 }
1812
1813 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1814 {
1815 struct pci_dev *dev;
1816
1817 dev = pci_get_slot(bus, devfn);
1818 if (dev) {
1819 pci_dev_put(dev);
1820 return dev;
1821 }
1822
1823 dev = pci_scan_device(bus, devfn);
1824 if (!dev)
1825 return NULL;
1826
1827 pci_device_add(dev, bus);
1828
1829 return dev;
1830 }
1831 EXPORT_SYMBOL(pci_scan_single_device);
1832
1833 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1834 {
1835 int pos;
1836 u16 cap = 0;
1837 unsigned next_fn;
1838
1839 if (pci_ari_enabled(bus)) {
1840 if (!dev)
1841 return 0;
1842 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1843 if (!pos)
1844 return 0;
1845
1846 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1847 next_fn = PCI_ARI_CAP_NFN(cap);
1848 if (next_fn <= fn)
1849 return 0; /* protect against malformed list */
1850
1851 return next_fn;
1852 }
1853
1854 /* dev may be NULL for non-contiguous multifunction devices */
1855 if (!dev || dev->multifunction)
1856 return (fn + 1) % 8;
1857
1858 return 0;
1859 }
1860
1861 static int only_one_child(struct pci_bus *bus)
1862 {
1863 struct pci_dev *parent = bus->self;
1864
1865 if (!parent || !pci_is_pcie(parent))
1866 return 0;
1867 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1868 return 1;
1869 if (parent->has_secondary_link &&
1870 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1871 return 1;
1872 return 0;
1873 }
1874
1875 /**
1876 * pci_scan_slot - scan a PCI slot on a bus for devices.
1877 * @bus: PCI bus to scan
1878 * @devfn: slot number to scan (must have zero function.)
1879 *
1880 * Scan a PCI slot on the specified PCI bus for devices, adding
1881 * discovered devices to the @bus->devices list. New devices
1882 * will not have is_added set.
1883 *
1884 * Returns the number of new devices found.
1885 */
1886 int pci_scan_slot(struct pci_bus *bus, int devfn)
1887 {
1888 unsigned fn, nr = 0;
1889 struct pci_dev *dev;
1890
1891 if (only_one_child(bus) && (devfn > 0))
1892 return 0; /* Already scanned the entire slot */
1893
1894 dev = pci_scan_single_device(bus, devfn);
1895 if (!dev)
1896 return 0;
1897 if (!dev->is_added)
1898 nr++;
1899
1900 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1901 dev = pci_scan_single_device(bus, devfn + fn);
1902 if (dev) {
1903 if (!dev->is_added)
1904 nr++;
1905 dev->multifunction = 1;
1906 }
1907 }
1908
1909 /* only one slot has pcie device */
1910 if (bus->self && nr)
1911 pcie_aspm_init_link_state(bus->self);
1912
1913 return nr;
1914 }
1915 EXPORT_SYMBOL(pci_scan_slot);
1916
1917 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1918 {
1919 u8 *smpss = data;
1920
1921 if (!pci_is_pcie(dev))
1922 return 0;
1923
1924 /*
1925 * We don't have a way to change MPS settings on devices that have
1926 * drivers attached. A hot-added device might support only the minimum
1927 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1928 * where devices may be hot-added, we limit the fabric MPS to 128 so
1929 * hot-added devices will work correctly.
1930 *
1931 * However, if we hot-add a device to a slot directly below a Root
1932 * Port, it's impossible for there to be other existing devices below
1933 * the port. We don't limit the MPS in this case because we can
1934 * reconfigure MPS on both the Root Port and the hot-added device,
1935 * and there are no other devices involved.
1936 *
1937 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1938 */
1939 if (dev->is_hotplug_bridge &&
1940 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1941 *smpss = 0;
1942
1943 if (*smpss > dev->pcie_mpss)
1944 *smpss = dev->pcie_mpss;
1945
1946 return 0;
1947 }
1948
1949 static void pcie_write_mps(struct pci_dev *dev, int mps)
1950 {
1951 int rc;
1952
1953 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1954 mps = 128 << dev->pcie_mpss;
1955
1956 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1957 dev->bus->self)
1958 /* For "Performance", the assumption is made that
1959 * downstream communication will never be larger than
1960 * the MRRS. So, the MPS only needs to be configured
1961 * for the upstream communication. This being the case,
1962 * walk from the top down and set the MPS of the child
1963 * to that of the parent bus.
1964 *
1965 * Configure the device MPS with the smaller of the
1966 * device MPSS or the bridge MPS (which is assumed to be
1967 * properly configured at this point to the largest
1968 * allowable MPS based on its parent bus).
1969 */
1970 mps = min(mps, pcie_get_mps(dev->bus->self));
1971 }
1972
1973 rc = pcie_set_mps(dev, mps);
1974 if (rc)
1975 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1976 }
1977
1978 static void pcie_write_mrrs(struct pci_dev *dev)
1979 {
1980 int rc, mrrs;
1981
1982 /* In the "safe" case, do not configure the MRRS. There appear to be
1983 * issues with setting MRRS to 0 on a number of devices.
1984 */
1985 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1986 return;
1987
1988 /* For Max performance, the MRRS must be set to the largest supported
1989 * value. However, it cannot be configured larger than the MPS the
1990 * device or the bus can support. This should already be properly
1991 * configured by a prior call to pcie_write_mps.
1992 */
1993 mrrs = pcie_get_mps(dev);
1994
1995 /* MRRS is a R/W register. Invalid values can be written, but a
1996 * subsequent read will verify if the value is acceptable or not.
1997 * If the MRRS value provided is not acceptable (e.g., too large),
1998 * shrink the value until it is acceptable to the HW.
1999 */
2000 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2001 rc = pcie_set_readrq(dev, mrrs);
2002 if (!rc)
2003 break;
2004
2005 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
2006 mrrs /= 2;
2007 }
2008
2009 if (mrrs < 128)
2010 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2011 }
2012
2013 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2014 {
2015 int mps, orig_mps;
2016
2017 if (!pci_is_pcie(dev))
2018 return 0;
2019
2020 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2021 pcie_bus_config == PCIE_BUS_DEFAULT)
2022 return 0;
2023
2024 mps = 128 << *(u8 *)data;
2025 orig_mps = pcie_get_mps(dev);
2026
2027 pcie_write_mps(dev, mps);
2028 pcie_write_mrrs(dev);
2029
2030 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2031 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2032 orig_mps, pcie_get_readrq(dev));
2033
2034 return 0;
2035 }
2036
2037 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
2038 * parents then children fashion. If this changes, then this code will not
2039 * work as designed.
2040 */
2041 void pcie_bus_configure_settings(struct pci_bus *bus)
2042 {
2043 u8 smpss = 0;
2044
2045 if (!bus->self)
2046 return;
2047
2048 if (!pci_is_pcie(bus->self))
2049 return;
2050
2051 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
2052 * to be aware of the MPS of the destination. To work around this,
2053 * simply force the MPS of the entire system to the smallest possible.
2054 */
2055 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2056 smpss = 0;
2057
2058 if (pcie_bus_config == PCIE_BUS_SAFE) {
2059 smpss = bus->self->pcie_mpss;
2060
2061 pcie_find_smpss(bus->self, &smpss);
2062 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2063 }
2064
2065 pcie_bus_configure_set(bus->self, &smpss);
2066 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2067 }
2068 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2069
2070 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2071 {
2072 unsigned int devfn, pass, max = bus->busn_res.start;
2073 struct pci_dev *dev;
2074
2075 dev_dbg(&bus->dev, "scanning bus\n");
2076
2077 /* Go find them, Rover! */
2078 for (devfn = 0; devfn < 0x100; devfn += 8)
2079 pci_scan_slot(bus, devfn);
2080
2081 /* Reserve buses for SR-IOV capability. */
2082 max += pci_iov_bus_range(bus);
2083
2084 /*
2085 * After performing arch-dependent fixup of the bus, look behind
2086 * all PCI-to-PCI bridges on this bus.
2087 */
2088 if (!bus->is_added) {
2089 dev_dbg(&bus->dev, "fixups for bus\n");
2090 pcibios_fixup_bus(bus);
2091 bus->is_added = 1;
2092 }
2093
2094 for (pass = 0; pass < 2; pass++)
2095 list_for_each_entry(dev, &bus->devices, bus_list) {
2096 if (pci_is_bridge(dev))
2097 max = pci_scan_bridge(bus, dev, max, pass);
2098 }
2099
2100 /*
2101 * We've scanned the bus and so we know all about what's on
2102 * the other side of any bridges that may be on this bus plus
2103 * any devices.
2104 *
2105 * Return how far we've got finding sub-buses.
2106 */
2107 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2108 return max;
2109 }
2110 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2111
2112 /**
2113 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2114 * @bridge: Host bridge to set up.
2115 *
2116 * Default empty implementation. Replace with an architecture-specific setup
2117 * routine, if necessary.
2118 */
2119 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2120 {
2121 return 0;
2122 }
2123
2124 void __weak pcibios_add_bus(struct pci_bus *bus)
2125 {
2126 }
2127
2128 void __weak pcibios_remove_bus(struct pci_bus *bus)
2129 {
2130 }
2131
2132 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2133 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2134 {
2135 int error;
2136 struct pci_host_bridge *bridge;
2137 struct pci_bus *b, *b2;
2138 struct resource_entry *window, *n;
2139 struct resource *res;
2140 resource_size_t offset;
2141 char bus_addr[64];
2142 char *fmt;
2143
2144 b = pci_alloc_bus(NULL);
2145 if (!b)
2146 return NULL;
2147
2148 b->sysdata = sysdata;
2149 b->ops = ops;
2150 b->number = b->busn_res.start = bus;
2151 pci_bus_assign_domain_nr(b, parent);
2152 b2 = pci_find_bus(pci_domain_nr(b), bus);
2153 if (b2) {
2154 /* If we already got to this bus through a different bridge, ignore it */
2155 dev_dbg(&b2->dev, "bus already known\n");
2156 goto err_out;
2157 }
2158
2159 bridge = pci_alloc_host_bridge(b);
2160 if (!bridge)
2161 goto err_out;
2162
2163 bridge->dev.parent = parent;
2164 bridge->dev.release = pci_release_host_bridge_dev;
2165 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
2166 error = pcibios_root_bridge_prepare(bridge);
2167 if (error) {
2168 kfree(bridge);
2169 goto err_out;
2170 }
2171
2172 error = device_register(&bridge->dev);
2173 if (error) {
2174 put_device(&bridge->dev);
2175 goto err_out;
2176 }
2177 b->bridge = get_device(&bridge->dev);
2178 device_enable_async_suspend(b->bridge);
2179 pci_set_bus_of_node(b);
2180 pci_set_bus_msi_domain(b);
2181
2182 if (!parent)
2183 set_dev_node(b->bridge, pcibus_to_node(b));
2184
2185 b->dev.class = &pcibus_class;
2186 b->dev.parent = b->bridge;
2187 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
2188 error = device_register(&b->dev);
2189 if (error)
2190 goto class_dev_reg_err;
2191
2192 pcibios_add_bus(b);
2193
2194 /* Create legacy_io and legacy_mem files for this bus */
2195 pci_create_legacy_files(b);
2196
2197 if (parent)
2198 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
2199 else
2200 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
2201
2202 /* Add initial resources to the bus */
2203 resource_list_for_each_entry_safe(window, n, resources) {
2204 list_move_tail(&window->node, &bridge->windows);
2205 res = window->res;
2206 offset = window->offset;
2207 if (res->flags & IORESOURCE_BUS)
2208 pci_bus_insert_busn_res(b, bus, res->end);
2209 else
2210 pci_bus_add_resource(b, res, 0);
2211 if (offset) {
2212 if (resource_type(res) == IORESOURCE_IO)
2213 fmt = " (bus address [%#06llx-%#06llx])";
2214 else
2215 fmt = " (bus address [%#010llx-%#010llx])";
2216 snprintf(bus_addr, sizeof(bus_addr), fmt,
2217 (unsigned long long) (res->start - offset),
2218 (unsigned long long) (res->end - offset));
2219 } else
2220 bus_addr[0] = '\0';
2221 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
2222 }
2223
2224 down_write(&pci_bus_sem);
2225 list_add_tail(&b->node, &pci_root_buses);
2226 up_write(&pci_bus_sem);
2227
2228 return b;
2229
2230 class_dev_reg_err:
2231 put_device(&bridge->dev);
2232 device_unregister(&bridge->dev);
2233 err_out:
2234 kfree(b);
2235 return NULL;
2236 }
2237 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2238
2239 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2240 {
2241 struct resource *res = &b->busn_res;
2242 struct resource *parent_res, *conflict;
2243
2244 res->start = bus;
2245 res->end = bus_max;
2246 res->flags = IORESOURCE_BUS;
2247
2248 if (!pci_is_root_bus(b))
2249 parent_res = &b->parent->busn_res;
2250 else {
2251 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2252 res->flags |= IORESOURCE_PCI_FIXED;
2253 }
2254
2255 conflict = request_resource_conflict(parent_res, res);
2256
2257 if (conflict)
2258 dev_printk(KERN_DEBUG, &b->dev,
2259 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2260 res, pci_is_root_bus(b) ? "domain " : "",
2261 parent_res, conflict->name, conflict);
2262
2263 return conflict == NULL;
2264 }
2265
2266 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2267 {
2268 struct resource *res = &b->busn_res;
2269 struct resource old_res = *res;
2270 resource_size_t size;
2271 int ret;
2272
2273 if (res->start > bus_max)
2274 return -EINVAL;
2275
2276 size = bus_max - res->start + 1;
2277 ret = adjust_resource(res, res->start, size);
2278 dev_printk(KERN_DEBUG, &b->dev,
2279 "busn_res: %pR end %s updated to %02x\n",
2280 &old_res, ret ? "can not be" : "is", bus_max);
2281
2282 if (!ret && !res->parent)
2283 pci_bus_insert_busn_res(b, res->start, res->end);
2284
2285 return ret;
2286 }
2287
2288 void pci_bus_release_busn_res(struct pci_bus *b)
2289 {
2290 struct resource *res = &b->busn_res;
2291 int ret;
2292
2293 if (!res->flags || !res->parent)
2294 return;
2295
2296 ret = release_resource(res);
2297 dev_printk(KERN_DEBUG, &b->dev,
2298 "busn_res: %pR %s released\n",
2299 res, ret ? "can not be" : "is");
2300 }
2301
2302 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2303 struct pci_ops *ops, void *sysdata,
2304 struct list_head *resources, struct msi_controller *msi)
2305 {
2306 struct resource_entry *window;
2307 bool found = false;
2308 struct pci_bus *b;
2309 int max;
2310
2311 resource_list_for_each_entry(window, resources)
2312 if (window->res->flags & IORESOURCE_BUS) {
2313 found = true;
2314 break;
2315 }
2316
2317 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2318 if (!b)
2319 return NULL;
2320
2321 b->msi = msi;
2322
2323 if (!found) {
2324 dev_info(&b->dev,
2325 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2326 bus);
2327 pci_bus_insert_busn_res(b, bus, 255);
2328 }
2329
2330 max = pci_scan_child_bus(b);
2331
2332 if (!found)
2333 pci_bus_update_busn_res_end(b, max);
2334
2335 return b;
2336 }
2337
2338 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2339 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2340 {
2341 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2342 NULL);
2343 }
2344 EXPORT_SYMBOL(pci_scan_root_bus);
2345
2346 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2347 void *sysdata)
2348 {
2349 LIST_HEAD(resources);
2350 struct pci_bus *b;
2351
2352 pci_add_resource(&resources, &ioport_resource);
2353 pci_add_resource(&resources, &iomem_resource);
2354 pci_add_resource(&resources, &busn_resource);
2355 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2356 if (b) {
2357 pci_scan_child_bus(b);
2358 } else {
2359 pci_free_resource_list(&resources);
2360 }
2361 return b;
2362 }
2363 EXPORT_SYMBOL(pci_scan_bus);
2364
2365 /**
2366 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2367 * @bridge: PCI bridge for the bus to scan
2368 *
2369 * Scan a PCI bus and child buses for new devices, add them,
2370 * and enable them, resizing bridge mmio/io resource if necessary
2371 * and possible. The caller must ensure the child devices are already
2372 * removed for resizing to occur.
2373 *
2374 * Returns the max number of subordinate bus discovered.
2375 */
2376 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2377 {
2378 unsigned int max;
2379 struct pci_bus *bus = bridge->subordinate;
2380
2381 max = pci_scan_child_bus(bus);
2382
2383 pci_assign_unassigned_bridge_resources(bridge);
2384
2385 pci_bus_add_devices(bus);
2386
2387 return max;
2388 }
2389
2390 /**
2391 * pci_rescan_bus - scan a PCI bus for devices.
2392 * @bus: PCI bus to scan
2393 *
2394 * Scan a PCI bus and child buses for new devices, adds them,
2395 * and enables them.
2396 *
2397 * Returns the max number of subordinate bus discovered.
2398 */
2399 unsigned int pci_rescan_bus(struct pci_bus *bus)
2400 {
2401 unsigned int max;
2402
2403 max = pci_scan_child_bus(bus);
2404 pci_assign_unassigned_bus_resources(bus);
2405 pci_bus_add_devices(bus);
2406
2407 return max;
2408 }
2409 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2410
2411 /*
2412 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2413 * routines should always be executed under this mutex.
2414 */
2415 static DEFINE_MUTEX(pci_rescan_remove_lock);
2416
2417 void pci_lock_rescan_remove(void)
2418 {
2419 mutex_lock(&pci_rescan_remove_lock);
2420 }
2421 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2422
2423 void pci_unlock_rescan_remove(void)
2424 {
2425 mutex_unlock(&pci_rescan_remove_lock);
2426 }
2427 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2428
2429 static int __init pci_sort_bf_cmp(const struct device *d_a,
2430 const struct device *d_b)
2431 {
2432 const struct pci_dev *a = to_pci_dev(d_a);
2433 const struct pci_dev *b = to_pci_dev(d_b);
2434
2435 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2436 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2437
2438 if (a->bus->number < b->bus->number) return -1;
2439 else if (a->bus->number > b->bus->number) return 1;
2440
2441 if (a->devfn < b->devfn) return -1;
2442 else if (a->devfn > b->devfn) return 1;
2443
2444 return 0;
2445 }
2446
2447 void __init pci_sort_breadthfirst(void)
2448 {
2449 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
2450 }