drivers/net/wireless/bcmdhd4361/include/bcmpcie.h

   1 /*
   2  * Broadcom PCIE
   3  * Software-specific definitions shared between device and host side
   4  * Explains the shared area between host and dongle
   5  *
   6  * Copyright (C) 1999-2019, Broadcom.
   7  *
   8  *      Unless you and Broadcom execute a separate written software license
   9  * agreement governing use of this software, this software is licensed to you
  10  * under the terms of the GNU General Public License version 2 (the "GPL"),
  11  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
  12  * following added to such license:
  13  *
  14  *      As a special exception, the copyright holders of this software give you
  15  * permission to link this software with independent modules, and to copy and
  16  * distribute the resulting executable under terms of your choice, provided that
  17  * you also meet, for each linked independent module, the terms and conditions of
  18  * the license of that module.  An independent module is a module which is not
  19  * derived from this software.  The special exception does not apply to any
  20  * modifications of the software.
  21  *
  22  *      Notwithstanding the above, under no circumstances may you combine this
  23  * software in any way with any other Broadcom software provided under a license
  24  * other than the GPL, without Broadcom's express prior written consent.
  25  *
  26  *
  27  * <<Broadcom-WL-IPTag/Open:>>
  28  *
  29  * $Id: bcmpcie.h 775339 2018-08-07 02:14:37Z $
  30  */
  31
  32 #ifndef _bcmpcie_h_
  33 #define _bcmpcie_h_
  34
  35 #include <typedefs.h>
  36
  37 #define ADDR_64(x)                      (x.addr)
  38 #define HIGH_ADDR_32(x)     ((uint32) (((sh_addr_t) x).high_addr))
  39 #define LOW_ADDR_32(x)      ((uint32) (((sh_addr_t) x).low_addr))
  40
  41 typedef struct {
  42         uint32 low_addr;
  43         uint32 high_addr;
  44 } sh_addr_t;
  45
  46 /* May be overridden by 43xxxxx-roml.mk */
  47 #if !defined(BCMPCIE_MAX_TX_FLOWS)
  48 #define BCMPCIE_MAX_TX_FLOWS    40
  49 #endif /* ! BCMPCIE_MAX_TX_FLOWS */
  50
  51 #define PCIE_SHARED_VERSION_7           0x00007
  52 #define PCIE_SHARED_VERSION_6           0x00006 /* rev6 is compatible with rev 5 */
  53 #define PCIE_SHARED_VERSION_5           0x00005 /* rev6 is compatible with rev 5 */
  54 /**
  55  * Feature flags enabled in dongle. Advertised by dongle to DHD via the PCIe Shared structure that
  56  * is located in device memory.
  57  */
  58 #define PCIE_SHARED_VERSION_MASK        0x000FF
  59 #define PCIE_SHARED_ASSERT_BUILT        0x00100
  60 #define PCIE_SHARED_ASSERT              0x00200
  61 #define PCIE_SHARED_TRAP                0x00400
  62 #define PCIE_SHARED_IN_BRPT             0x00800
  63 #define PCIE_SHARED_SET_BRPT            0x01000
  64 #define PCIE_SHARED_PENDING_BRPT        0x02000
  65 /* BCMPCIE_SUPPORT_TX_PUSH_RING         0x04000 obsolete */
  66 #define PCIE_SHARED_EVT_SEQNUM          0x08000
  67 #define PCIE_SHARED_DMA_INDEX           0x10000
  68
  69 /**
  70  * There are host types where a device interrupt can 'race ahead' of data written by the device into
  71  * host memory. The dongle can avoid this condition using a variety of techniques (read barrier,
  72  * using PCIe Message Signalled Interrupts, or by using the PCIE_DMA_INDEX feature). Unfortunately
  73  * these techniques have drawbacks on router platforms. For these platforms, it was decided to not
  74  * avoid the condition, but to detect the condition instead and act on it.
  75  * D2H M2M DMA Complete Sync mechanism: Modulo-253-SeqNum or XORCSUM
  76  */
  77 #define PCIE_SHARED_D2H_SYNC_SEQNUM     0x20000
  78 #define PCIE_SHARED_D2H_SYNC_XORCSUM    0x40000
  79 #define PCIE_SHARED_D2H_SYNC_MODE_MASK \
  80         (PCIE_SHARED_D2H_SYNC_SEQNUM | PCIE_SHARED_D2H_SYNC_XORCSUM)
  81 #define PCIE_SHARED_IDLE_FLOW_RING              0x80000
  82 #define PCIE_SHARED_2BYTE_INDICES       0x100000
  83
  84 #define PCIE_SHARED2_EXTENDED_TRAP_DATA 0x00000001      /* using flags2 in shared area */
  85 #define PCIE_SHARED2_TXSTATUS_METADATA  0x00000002
  86 #define PCIE_SHARED2_BT_LOGGING         0x00000004      /* BT logging support */
  87 #define PCIE_SHARED2_SNAPSHOT_UPLOAD    0x00000008      /* BT/WLAN snapshot upload support */
  88 #define PCIE_SHARED2_SUBMIT_COUNT_WAR   0x00000010      /* submission count WAR */
  89 #define PCIE_SHARED2_FW_SMALL_MEMDUMP   0x00000200      /* FW small memdump */
  90 #define PCIE_SHARED2_DEBUG_BUF_DEST     0x00002000      /* debug buf dest support */
  91 #define PCIE_SHARED_FAST_DELETE_RING    0x00000020      /* Fast Delete Ring */
  92 #define PCIE_SHARED_EVENT_BUF_POOL_MAX  0x000000c0      /* event buffer pool max bits */
  93 #define PCIE_SHARED_EVENT_BUF_POOL_MAX_POS     6       /* event buffer pool max bit position */
  94
  95 /* dongle supports fatal buf log collection */
  96 #define PCIE_SHARED_FATAL_LOGBUG_VALID  0x200000
  97
  98 /* Implicit DMA with corerev 19 and after */
  99 #define PCIE_SHARED_IDMA                0x400000
 100
 101 /* MSI support */
 102 #define PCIE_SHARED_D2H_MSI_MULTI_MSG   0x800000
 103
 104 /* IFRM with corerev 19 and after */
 105 #define PCIE_SHARED_IFRM                0x1000000
 106
 107 /**
 108  * From Rev6 and above, suspend/resume can be done using two handshake methods.
 109  * 1. Using ctrl post/ctrl cmpl messages (Default rev6)
 110  * 2. Using Mailbox data (old method as used in rev5)
 111  * This shared flag indicates whether to overide rev6 default method and use mailbox for
 112  * suspend/resume.
 113  */
 114 #define PCIE_SHARED_USE_MAILBOX         0x2000000
 115
 116 /* Firmware compiled for mfgbuild purposes */
 117 #define PCIE_SHARED_MFGBUILD_FW         0x4000000
 118
 119 /* Firmware could use DB0 value as host timestamp */
 120 #define PCIE_SHARED_TIMESTAMP_DB0       0x8000000
 121 /* Firmware could use Hostready (IPC rev7) */
 122 #define PCIE_SHARED_HOSTRDY_SUPPORT     0x10000000
 123
 124 /* When set, Firmwar does not support OOB Device Wake based DS protocol */
 125 #define PCIE_SHARED_NO_OOB_DW           0x20000000
 126
 127 /* When set, Firmwar supports Inband DS protocol */
 128 #define PCIE_SHARED_INBAND_DS           0x40000000
 129
 130 /* use DAR registers */
 131 #define PCIE_SHARED_DAR                 0x80000000
 132
 133 /**
 134  * Following are the shared2 flags. All bits in flags have been used. A flags2
 135  * field got added and the definition for these flags come here:
 136  */
 137 /* WAR: D11 txstatus through unused status field of PCIe completion header */
 138 #define PCIE_SHARED2_D2H_D11_TX_STATUS  0x40000000
 139 #define PCIE_SHARED2_H2D_D11_TX_STATUS  0x80000000
 140
 141 #define PCIE_SHARED2_EXTENDED_TRAP_DATA 0x00000001
 142
 143 #define PCIE_SHARED2_TXSTATUS_METADATA  0x00000002
 144
 145 /* BT logging support */
 146 #define PCIE_SHARED2_BT_LOGGING         0x00000004
 147 /* BT/WLAN snapshot upload support */
 148 #define PCIE_SHARED2_SNAPSHOT_UPLOAD    0x00000008
 149 /* submission count WAR */
 150 #define PCIE_SHARED2_SUBMIT_COUNT_WAR   0x00000010
 151
 152 /* Fast Delete ring support */
 153 #define PCIE_SHARED2_FAST_DELETE_RING   0x00000020
 154
 155 /* Host SCB support */
 156 #define PCIE_SHARED2_HSCB               0x00000800
 157
 158 #define PCIE_SHARED_D2H_MAGIC           0xFEDCBA09
 159 #define PCIE_SHARED_H2D_MAGIC           0x12345678
 160
 161 #define PCIE_SHARED2_PKT_TX_STATUS      0x00000100              /* using flags2 to indicate
 162                                                            firmware support added to reuse
 163                                                            timesync to update PKT txstatus
 164                                                            */
 165 /* Support Enhanced Debug Lane */
 166 #define PCIE_SHARED2_EDL_RING           0x00001000
 167
 168 /* BT producer index reset WAR */
 169 #define PCIE_SHARED2_PCIE_ENUM_RESET_FLR                0x00004000
 170
 171 /**
 172  * Message rings convey messages between host and device. They are unidirectional, and are located
 173  * in host memory.
 174  *
 175  * This is the minimal set of message rings, known as 'common message rings':
 176  */
 177 #define BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT              0
 178 #define BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT               1
 179 #define BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE            2
 180 #define BCMPCIE_D2H_MSGRING_TX_COMPLETE                 3
 181 #define BCMPCIE_D2H_MSGRING_RX_COMPLETE                 4
 182 #define BCMPCIE_COMMON_MSGRING_MAX_ID                   4
 183
 184 #define BCMPCIE_H2D_COMMON_MSGRINGS                     2
 185 #define BCMPCIE_D2H_COMMON_MSGRINGS                     3
 186 #define BCMPCIE_COMMON_MSGRINGS                         5
 187
 188 #define BCMPCIE_H2D_MSGRINGS(max_tx_flows) \
 189         (BCMPCIE_H2D_COMMON_MSGRINGS + (max_tx_flows))
 190
 191 /* different ring types */
 192 #define BCMPCIE_H2D_RING_TYPE_CTRL_SUBMIT               0x1
 193 #define BCMPCIE_H2D_RING_TYPE_TXFLOW_RING               0x2
 194 #define BCMPCIE_H2D_RING_TYPE_RXBUFPOST                 0x3
 195 #define BCMPCIE_H2D_RING_TYPE_TXSUBMIT                  0x4
 196 #define BCMPCIE_H2D_RING_TYPE_DBGBUF_SUBMIT             0x5
 197 #define BCMPCIE_H2D_RING_TYPE_BTLOG_SUBMIT              0x6
 198
 199 #define BCMPCIE_D2H_RING_TYPE_CTRL_CPL                  0x1
 200 #define BCMPCIE_D2H_RING_TYPE_TX_CPL                    0x2
 201 #define BCMPCIE_D2H_RING_TYPE_RX_CPL                    0x3
 202 #define BCMPCIE_D2H_RING_TYPE_DBGBUF_CPL                0x4
 203 #define BCMPCIE_D2H_RING_TYPE_AC_RX_COMPLETE            0x5
 204 #define BCMPCIE_D2H_RING_TYPE_BTLOG_CPL         0x6
 205 #define BCMPCIE_D2H_RING_TYPE_EDL                       0x7
 206
 207 /**
 208  * H2D and D2H, WR and RD index, are maintained in the following arrays:
 209  * - Array of all H2D WR Indices
 210  * - Array of all H2D RD Indices
 211  * - Array of all D2H WR Indices
 212  * - Array of all D2H RD Indices
 213  *
 214  * The offset of the WR or RD indexes (for common rings) in these arrays are
 215  * listed below. Arrays ARE NOT indexed by a ring's id.
 216  *
 217  * D2H common rings WR and RD index start from 0, even though their ringids
 218  * start from BCMPCIE_H2D_COMMON_MSGRINGS
 219  */
 220
 221 #define BCMPCIE_H2D_RING_IDX(h2d_ring_id) (h2d_ring_id)
 222
 223 enum h2dring_idx {
 224         /* H2D common rings */
 225         BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT_IDX =
 226                 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT),
 227         BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT_IDX =
 228                 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT),
 229
 230         /* First TxPost's WR or RD index starts after all H2D common rings */
 231         BCMPCIE_H2D_MSGRING_TXFLOW_IDX_START =
 232                 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_COMMON_MSGRINGS)
 233 };
 234
 235 #define BCMPCIE_D2H_RING_IDX(d2h_ring_id) \
 236         ((d2h_ring_id) - BCMPCIE_H2D_COMMON_MSGRINGS)
 237
 238 enum d2hring_idx {
 239         /* D2H Common Rings */
 240         BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE_IDX =
 241                 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE),
 242         BCMPCIE_D2H_MSGRING_TX_COMPLETE_IDX =
 243                 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_TX_COMPLETE),
 244         BCMPCIE_D2H_MSGRING_RX_COMPLETE_IDX =
 245                 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_RX_COMPLETE)
 246 };
 247
 248 /**
 249  * Macros for managing arrays of RD WR indices:
 250  * rw_index_sz:
 251  *    - in dongle, rw_index_sz is known at compile time
 252  *    - in host/DHD, rw_index_sz is derived from advertized pci_shared flags
 253  *
 254  *  ring_idx: See h2dring_idx and d2hring_idx
 255  */
 256
 257 /** Offset of a RD or WR index in H2D or D2H indices array */
 258 #define BCMPCIE_RW_INDEX_OFFSET(rw_index_sz, ring_idx) \
 259         ((rw_index_sz) * (ring_idx))
 260
 261 /** Fetch the address of RD or WR index in H2D or D2H indices array */
 262 #define BCMPCIE_RW_INDEX_ADDR(indices_array_base, rw_index_sz, ring_idx) \
 263         (void *)((uint32)(indices_array_base) + \
 264         BCMPCIE_RW_INDEX_OFFSET((rw_index_sz), (ring_idx)))
 265
 266 /** H2D DMA Indices array size: given max flow rings */
 267 #define BCMPCIE_H2D_RW_INDEX_ARRAY_SZ(rw_index_sz, max_tx_flows) \
 268         ((rw_index_sz) * BCMPCIE_H2D_MSGRINGS(max_tx_flows))
 269
 270 /** D2H DMA Indices array size */
 271 #define BCMPCIE_D2H_RW_INDEX_ARRAY_SZ(rw_index_sz) \
 272         ((rw_index_sz) * BCMPCIE_D2H_COMMON_MSGRINGS)
 273
 274 /**
 275  * This type is used by a 'message buffer' (which is a FIFO for messages). Message buffers are used
 276  * for host<->device communication and are instantiated on both sides. ring_mem_t is instantiated
 277  * both in host as well as device memory.
 278  */
 279 typedef struct ring_mem {
 280         uint16          idx;       /* ring id */
 281         uint8           type;
 282         uint8           rsvd;
 283         uint16          max_item;  /* Max number of items in flow ring */
 284         uint16          len_items; /* Items are fixed size. Length in bytes of one item */
 285         sh_addr_t       base_addr; /* 64 bits address, either in host or device memory */
 286 } ring_mem_t;
 287
 288 /**
 289  * Per flow ring, information is maintained in device memory, eg at what address the ringmem and
 290  * ringstate are located. The flow ring itself can be instantiated in either host or device memory.
 291  *
 292  * Perhaps this type should be renamed to make clear that it resides in device memory only.
 293  */
 294 typedef struct ring_info {
 295         uint32          ringmem_ptr; /* ring mem location in dongle memory */
 296
 297         /* Following arrays are indexed using h2dring_idx and d2hring_idx, and not
 298          * by a ringid.
 299          */
 300
 301         /* 32bit ptr to arrays of WR or RD indices for all rings in dongle memory */
 302         uint32          h2d_w_idx_ptr; /* Array of all H2D ring's WR indices */
 303         uint32          h2d_r_idx_ptr; /* Array of all H2D ring's RD indices */
 304         uint32          d2h_w_idx_ptr; /* Array of all D2H ring's WR indices */
 305         uint32          d2h_r_idx_ptr; /* Array of all D2H ring's RD indices */
 306
 307         /* PCIE_DMA_INDEX feature: Dongle uses mem2mem DMA to sync arrays in host.
 308          * Host may directly fetch WR and RD indices from these host-side arrays.
 309          *
 310          * 64bit ptr to arrays of WR or RD indices for all rings in host memory.
 311          */
 312         sh_addr_t       h2d_w_idx_hostaddr; /* Array of all H2D ring's WR indices */
 313         sh_addr_t       h2d_r_idx_hostaddr; /* Array of all H2D ring's RD indices */
 314         sh_addr_t       d2h_w_idx_hostaddr; /* Array of all D2H ring's WR indices */
 315         sh_addr_t       d2h_r_idx_hostaddr; /* Array of all D2H ring's RD indices */
 316
 317         uint16          max_tx_flowrings; /* maximum number of H2D rings: common + flow */
 318         uint16          max_submission_queues; /* maximum number of H2D rings: common + flow */
 319         uint16          max_completion_rings; /* maximum number of H2D rings: common + flow */
 320         uint16          max_vdevs; /* max number of virtual interfaces supported */
 321
 322         sh_addr_t       ifrm_w_idx_hostaddr; /* Array of all H2D ring's WR indices for IFRM */
 323 } ring_info_t;
 324
 325 /**
 326  * A structure located in TCM that is shared between host and device, primarily used during
 327  * initialization.
 328  */
 329 typedef struct {
 330         /** shared area version captured at flags 7:0 */
 331         uint32  flags;
 332
 333         uint32  trap_addr;
 334         uint32  assert_exp_addr;
 335         uint32  assert_file_addr;
 336         uint32  assert_line;
 337         uint32  console_addr;           /**< Address of hnd_cons_t */
 338
 339         uint32  msgtrace_addr;
 340
 341         uint32  fwid;
 342
 343         /* Used for debug/flow control */
 344         uint16  total_lfrag_pkt_cnt;
 345         uint16  max_host_rxbufs; /* rsvd in spec */
 346
 347         uint32 dma_rxoffset; /* rsvd in spec */
 348
 349         /** these will be used for sleep request/ack, d3 req/ack */
 350         uint32  h2d_mb_data_ptr;
 351         uint32  d2h_mb_data_ptr;
 352
 353         /* information pertinent to host IPC/msgbuf channels */
 354         /** location in the TCM memory which has the ring_info */
 355         uint32  rings_info_ptr;
 356
 357         /** block of host memory for the scratch buffer */
 358         uint32          host_dma_scratch_buffer_len;
 359         sh_addr_t       host_dma_scratch_buffer;
 360
 361         /* location in host memory for scb host offload structures */
 362         sh_addr_t       host_scb_addr;
 363         uint32          host_scb_size;
 364
 365         /* anonymous union for overloading fields in structure */
 366         union {
 367                 uint32  buzz_dbg_ptr;   /* BUZZZ state format strings and trace buffer */
 368                 struct {
 369                         /* Host provided trap buffer length in words */
 370                         uint16  device_trap_debug_buffer_len;
 371                         uint16  rsvd2;
 372                 };
 373         };
 374
 375         /* rev6 compatible changes */
 376         uint32          flags2;
 377         uint32          host_cap;
 378
 379         /* location in the host address space to write trap indication.
 380         * At this point for the current rev of the spec, firmware will
 381         * support only indications to 32 bit host addresses.
 382         * This essentially is device_trap_debug_buffer_addr
 383         */
 384         sh_addr_t       host_trap_addr;
 385
 386         /* location for host fatal error log buffer start address */
 387         uint32          device_fatal_logbuf_start;
 388
 389         /* location in host memory for offloaded modules */
 390         sh_addr_t       hoffload_addr;
 391 } pciedev_shared_t;
 392
 393 /* Device F/W provides the following access function:
 394  * pciedev_shared_t *hnd_get_pciedev_shared(void);
 395  */
 396
 397 /* host capabilities */
 398 #define HOSTCAP_PCIEAPI_VERSION_MASK            0x000000FF
 399 #define HOSTCAP_H2D_VALID_PHASE                 0x00000100
 400 #define HOSTCAP_H2D_ENABLE_TRAP_ON_BADPHASE     0x00000200
 401 #define HOSTCAP_H2D_ENABLE_HOSTRDY              0x00000400
 402 #define HOSTCAP_DB0_TIMESTAMP                   0x00000800
 403 #define HOSTCAP_DS_NO_OOB_DW                    0x00001000
 404 #define HOSTCAP_DS_INBAND_DW                    0x00002000
 405 #define HOSTCAP_H2D_IDMA                        0x00004000
 406 #define HOSTCAP_H2D_IFRM                        0x00008000
 407 #define HOSTCAP_H2D_DAR                         0x00010000
 408 #define HOSTCAP_EXTENDED_TRAP_DATA              0x00020000
 409 #define HOSTCAP_TXSTATUS_METADATA               0x00040000
 410 #define HOSTCAP_BT_LOGGING                      0x00080000
 411 #define HOSTCAP_SNAPSHOT_UPLOAD                 0x00100000
 412 #define HOSTCAP_FAST_DELETE_RING                0x00200000
 413 #define HOSTCAP_PKT_TXSTATUS                    0x00400000
 414 #define HOSTCAP_UR_FW_NO_TRAP                   0x00800000 /* Don't trap on UR */
 415 #define HOSTCAP_HSCB                            0x02000000
 416 /* Host support for extended device trap debug buffer */
 417 #define HOSTCAP_EXT_TRAP_DBGBUF                 0x04000000
 418 /* Host support for enhanced debug lane */
 419 #define HOSTCAP_EDL_RING                        0x10000000
 420
 421 /* extended trap debug buffer allocation sizes. Note that this buffer can be used for
 422  * other trap related purposes also.
 423  */
 424 #define BCMPCIE_HOST_EXT_TRAP_DBGBUF_LEN_MIN    (64u * 1024u)
 425 #define BCMPCIE_HOST_EXT_TRAP_DBGBUF_LEN_MAX    (256u * 1024u)
 426
 427 /**
 428  * Mailboxes notify a remote party that an event took place, using interrupts. They use hardware
 429  * support.
 430  */
 431
 432 /* H2D mail box Data */
 433 #define H2D_HOST_D3_INFORM              0x00000001
 434 #define H2D_HOST_DS_ACK         0x00000002
 435 #define H2D_HOST_DS_NAK         0x00000004
 436 #define H2D_HOST_D0_INFORM_IN_USE       0x00000008
 437 #define H2D_HOST_D0_INFORM              0x00000010
 438 #define H2DMB_DS_ACTIVE                 0x00000020
 439 #define H2DMB_DS_DEVICE_WAKE    0x00000040
 440 #define H2D_HOST_IDMA_INITED    0x00000080
 441 #define H2D_HOST_ACK_NOINT              0x00010000 /* d2h_ack interrupt ignore */
 442 #define H2D_HOST_CONS_INT       0x80000000      /**< h2d int for console cmds  */
 443 #define H2D_FW_TRAP             0x20000000      /**< h2d force TRAP */
 444 #define H2DMB_DS_HOST_SLEEP_INFORM H2D_HOST_D3_INFORM
 445 #define H2DMB_DS_DEVICE_SLEEP_ACK  H2D_HOST_DS_ACK
 446 #define H2DMB_DS_DEVICE_SLEEP_NAK  H2D_HOST_DS_NAK
 447 #define H2DMB_D0_INFORM_IN_USE     H2D_HOST_D0_INFORM_IN_USE
 448 #define H2DMB_D0_INFORM            H2D_HOST_D0_INFORM
 449 #define H2DMB_FW_TRAP              H2D_FW_TRAP
 450 #define H2DMB_HOST_CONS_INT        H2D_HOST_CONS_INT
 451 #define H2DMB_DS_DEVICE_WAKE_ASSERT             H2DMB_DS_DEVICE_WAKE
 452 #define H2DMB_DS_DEVICE_WAKE_DEASSERT   H2DMB_DS_ACTIVE
 453
 454 /* D2H mail box Data */
 455 #define D2H_DEV_D3_ACK                                  0x00000001
 456 #define D2H_DEV_DS_ENTER_REQ                    0x00000002
 457 #define D2H_DEV_DS_EXIT_NOTE                    0x00000004
 458 #define D2HMB_DS_HOST_SLEEP_EXIT_ACK    0x00000008
 459 #define D2H_DEV_IDMA_INITED                             0x00000010
 460 #define D2H_DEV_FWHALT                                  0x10000000
 461 #define D2H_DEV_TRAP_PING_HOST_FAILURE  0x08000000
 462 #define D2H_DEV_EXT_TRAP_DATA                   0x20000000
 463 #define D2H_DEV_TRAP_IN_TRAP                    0x40000000
 464 #define D2H_DEV_TRAP_DUE_TO_BT                  0x01000000
 465 /* Indicates trap due to HMAP violation */
 466 #define D2H_DEV_TRAP_DUE_TO_HMAP                0x02000000
 467 /* Indicates whether HMAP violation was Write */
 468 #define D2H_DEV_TRAP_HMAP_WRITE                 0x04000000
 469
 470 #define D2HMB_DS_HOST_SLEEP_ACK         D2H_DEV_D3_ACK
 471 #define D2HMB_DS_DEVICE_SLEEP_ENTER_REQ D2H_DEV_DS_ENTER_REQ
 472 #define D2HMB_DS_DEVICE_SLEEP_EXIT      D2H_DEV_DS_EXIT_NOTE
 473 #define D2HMB_FWHALT                    D2H_DEV_FWHALT
 474 #define D2HMB_TRAP_IN_TRAP              D2H_DEV_TRAP_IN_TRAP
 475 #define D2HMB_EXT_TRAP_DATA             D2H_DEV_EXT_TRAP_DATA
 476 #define D2H_FWTRAP_MASK         0x0000001F      /* Adding maskbits for TRAP information */
 477 #define D2H_DEV_MB_MASK         (D2H_DEV_D3_ACK | D2H_DEV_DS_ENTER_REQ | \
 478                                 D2H_DEV_DS_EXIT_NOTE | D2H_DEV_IDMA_INITED | D2H_DEV_FWHALT | \
 479                                 D2H_FWTRAP_MASK | D2H_DEV_EXT_TRAP_DATA | D2H_DEV_TRAP_IN_TRAP)
 480 #define D2H_DEV_MB_INVALIDATED(x)       ((!x) || (x & ~D2H_DEV_MB_MASK))
 481
 482 /* Size of Extended Trap data Buffer */
 483 #define BCMPCIE_EXT_TRAP_DATA_MAXLEN  4096
 484
 485 /** These macro's operate on type 'inuse_lclbuf_pool_t' and are used by firmware only */
 486 #define PREVTXP(i, d)           (((i) == 0) ? ((d) - 1) : ((i) - 1))
 487 #define NEXTTXP(i, d)           ((((i)+1) >= (d)) ? 0 : ((i)+1))
 488 #define NEXTNTXP(i, n, d)       ((((i)+(n)) >= (d)) ? 0 : ((i)+(n)))
 489 #define NTXPACTIVE(r, w, d)     (((r) <= (w)) ? ((w)-(r)) : ((d)-(r)+(w)))
 490 #define NTXPAVAIL(r, w, d)      (((d) - NTXPACTIVE((r), (w), (d))) > 1)
 491
 492 /* Function can be used to notify host of FW halt */
 493 #define READ_AVAIL_SPACE(w, r, d) ((w >= r) ? (uint32)(w - r) : (uint32)(d - r))
 494 #define WRITE_SPACE_AVAIL_CONTINUOUS(r, w, d) ((w >= r) ? (d - w) : (r - w))
 495 #define WRITE_SPACE_AVAIL(r, w, d) (d - (NTXPACTIVE(r, w, d)) - 1)
 496 #define CHECK_WRITE_SPACE(r, w, d) ((r) > (w)) ? \
 497         (uint32)((r) - (w) - 1) : ((r) == 0 || (w) == 0) ? \
 498         (uint32)((d) - (w) - 1) : (uint32)((d) - (w))
 499
 500 #define CHECK_NOWRITE_SPACE(r, w, d) \
 501         (((uint32)(r) == (uint32)((w) + 1)) || (((r) == 0) && ((w) == ((d) - 1))))
 502
 503 #define WRT_PEND(x)     ((x)->wr_pending)
 504 #define DNGL_RING_WPTR(msgbuf)          (*((msgbuf)->tcm_rs_w_ptr)) /**< advanced by producer */
 505 #define BCMMSGBUF_RING_SET_W_PTR(msgbuf, a)     (DNGL_RING_WPTR(msgbuf) = (a))
 506
 507 #define DNGL_RING_RPTR(msgbuf)          (*((msgbuf)->tcm_rs_r_ptr)) /**< advanced by consumer */
 508 #define BCMMSGBUF_RING_SET_R_PTR(msgbuf, a)     (DNGL_RING_RPTR(msgbuf) = (a))
 509
 510 #define MODULO_RING_IDX(x, y)   ((x) % (y)->bitmap_size)
 511
 512 #define  RING_READ_PTR(x)       ((x)->ringstate->r_offset)
 513 #define  RING_WRITE_PTR(x)      ((x)->ringstate->w_offset)
 514 #define  RING_START_PTR(x)      ((x)->ringmem->base_addr.low_addr)
 515 #define  RING_MAX_ITEM(x)       ((x)->ringmem->max_item)
 516 #define  RING_LEN_ITEMS(x)      ((x)->ringmem->len_items)
 517 #define  HOST_RING_BASE(x)      ((x)->dma_buf.va)
 518 #define  HOST_RING_END(x)       ((uint8 *)HOST_RING_BASE((x)) + \
 519                                         ((RING_MAX_ITEM((x))-1)*RING_LEN_ITEMS((x))))
 520
 521 /* Trap types copied in the pciedev_shared.trap_addr */
 522 #define FW_INITIATED_TRAP_TYPE  (0x1 << 7)
 523 #define HEALTHCHECK_NODS_TRAP_TYPE      (0x1 << 6)
 524
 525 #endif  /* _bcmpcie_h_ */