2 * MSGBUF network driver ioctl/indication encoding
3 * Broadcom 802.11abg Networking Device Driver
5 * Definitions subject to change without notice.
7 * Copyright (C) 1999-2019, Broadcom.
9 * Unless you and Broadcom execute a separate written software license
10 * agreement governing use of this software, this software is licensed to you
11 * under the terms of the GNU General Public License version 2 (the "GPL"),
12 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
13 * following added to such license:
15 * As a special exception, the copyright holders of this software give you
16 * permission to link this software with independent modules, and to copy and
17 * distribute the resulting executable under terms of your choice, provided that
18 * you also meet, for each linked independent module, the terms and conditions of
19 * the license of that module. An independent module is a module which is not
20 * derived from this software. The special exception does not apply to any
21 * modifications of the software.
23 * Notwithstanding the above, under no circumstances may you combine this
24 * software in any way with any other Broadcom software provided under a license
25 * other than the GPL, without Broadcom's express prior written consent.
28 * <<Broadcom-WL-IPTag/Open:>>
30 * $Id: bcmmsgbuf.h 777047 2018-08-17 01:01:33Z $
39 #define MSGBUF_MAX_MSG_SIZE ETHER_MAX_LEN
41 #define D2H_EPOCH_MODULO 253 /* sequence number wrap */
42 #define D2H_EPOCH_INIT_VAL (D2H_EPOCH_MODULO + 1)
44 #define H2D_EPOCH_MODULO 253 /* sequence number wrap */
45 #define H2D_EPOCH_INIT_VAL (H2D_EPOCH_MODULO + 1)
47 #define H2DRING_TXPOST_ITEMSIZE 48
48 #define H2DRING_RXPOST_ITEMSIZE 32
49 #define H2DRING_CTRL_SUB_ITEMSIZE 40
51 #define D2HRING_TXCMPLT_ITEMSIZE 24
52 #define D2HRING_RXCMPLT_ITEMSIZE 40
54 #define D2HRING_TXCMPLT_ITEMSIZE_PREREV7 16
55 #define D2HRING_RXCMPLT_ITEMSIZE_PREREV7 32
57 #define D2HRING_CTRL_CMPLT_ITEMSIZE 24
58 #define H2DRING_INFO_BUFPOST_ITEMSIZE H2DRING_CTRL_SUB_ITEMSIZE
59 #define D2HRING_INFO_BUFCMPLT_ITEMSIZE D2HRING_CTRL_CMPLT_ITEMSIZE
61 #define D2HRING_SNAPSHOT_CMPLT_ITEMSIZE 20
63 #define H2DRING_TXPOST_MAX_ITEM 512
64 #define H2DRING_RXPOST_MAX_ITEM 512
65 #define H2DRING_CTRL_SUB_MAX_ITEM 64
66 #define D2HRING_TXCMPLT_MAX_ITEM 1024
67 #define D2HRING_RXCMPLT_MAX_ITEM 512
69 #define H2DRING_DYNAMIC_INFO_MAX_ITEM 32
70 #define D2HRING_DYNAMIC_INFO_MAX_ITEM 32
72 #define D2HRING_EDL_ITEMSIZE 2048u
73 #define D2HRING_EDL_MAX_ITEM 256u
74 #define D2HRING_EDL_WATERMARK (D2HRING_EDL_MAX_ITEM >> 5u)
76 #define D2HRING_CTRL_CMPLT_MAX_ITEM 64
84 HOST_TO_DNGL_TXP_DATA
,
85 HOST_TO_DNGL_RXP_DATA
,
91 #define MESSAGE_PAYLOAD(a) (a & MSG_TYPE_INTERNAL_USE_START) ? TRUE : FALSE
92 #define PCIEDEV_FIRMWARE_TSINFO 0x1
93 #define PCIEDEV_FIRMWARE_TSINFO_FIRST 0x1
94 #define PCIEDEV_FIRMWARE_TSINFO_MIDDLE 0x2
95 #define PCIEDEV_BTLOG_POST 0x3
96 #define PCIEDEV_BT_SNAPSHOT_POST 0x4
100 #define BCMMSGBUF_DUMMY_REF(a, b) do {BCM_REFERENCE((a));BCM_REFERENCE((b));} while (0)
102 #define BCMMSGBUF_API_IFIDX(a) 0
103 #define BCMMSGBUF_API_SEQNUM(a) 0
104 #define BCMMSGBUF_IOCTL_XTID(a) 0
105 #define BCMMSGBUF_IOCTL_PKTID(a) ((a)->cmd_id)
107 #define BCMMSGBUF_SET_API_IFIDX(a, b) BCMMSGBUF_DUMMY_REF(a, b)
108 #define BCMMSGBUF_SET_API_SEQNUM(a, b) BCMMSGBUF_DUMMY_REF(a, b)
109 #define BCMMSGBUF_IOCTL_SET_PKTID(a, b) (BCMMSGBUF_IOCTL_PKTID(a) = (b))
110 #define BCMMSGBUF_IOCTL_SET_XTID(a, b) BCMMSGBUF_DUMMY_REF(a, b)
112 #else /* PCIE_API_REV1 */
114 #define BCMMSGBUF_API_IFIDX(a) ((a)->if_id)
115 #define BCMMSGBUF_IOCTL_PKTID(a) ((a)->pkt_id)
116 #define BCMMSGBUF_API_SEQNUM(a) ((a)->u.seq.seq_no)
117 #define BCMMSGBUF_IOCTL_XTID(a) ((a)->xt_id)
119 #define BCMMSGBUF_SET_API_IFIDX(a, b) (BCMMSGBUF_API_IFIDX((a)) = (b))
120 #define BCMMSGBUF_SET_API_SEQNUM(a, b) (BCMMSGBUF_API_SEQNUM((a)) = (b))
121 #define BCMMSGBUF_IOCTL_SET_PKTID(a, b) (BCMMSGBUF_IOCTL_PKTID((a)) = (b))
122 #define BCMMSGBUF_IOCTL_SET_XTID(a, b) (BCMMSGBUF_IOCTL_XTID((a)) = (b))
124 #endif /* PCIE_API_REV1 */
126 /* utility data structures */
140 typedef union addr64 bcm_addr64_t
;
144 typedef struct cmn_msg_hdr
{
147 /** interface index this is valid for */
151 /** sequence number */
153 /** packet Identifier for the associated host buffer */
158 typedef enum bcmpcie_msgtype
{
159 MSG_TYPE_GEN_STATUS
= 0x1,
160 MSG_TYPE_RING_STATUS
= 0x2,
161 MSG_TYPE_FLOW_RING_CREATE
= 0x3,
162 MSG_TYPE_FLOW_RING_CREATE_CMPLT
= 0x4,
163 /* Enum value as copied from BISON 7.15: new generic message */
164 MSG_TYPE_RING_CREATE_CMPLT
= 0x4,
165 MSG_TYPE_FLOW_RING_DELETE
= 0x5,
166 MSG_TYPE_FLOW_RING_DELETE_CMPLT
= 0x6,
167 /* Enum value as copied from BISON 7.15: new generic message */
168 MSG_TYPE_RING_DELETE_CMPLT
= 0x6,
169 MSG_TYPE_FLOW_RING_FLUSH
= 0x7,
170 MSG_TYPE_FLOW_RING_FLUSH_CMPLT
= 0x8,
171 MSG_TYPE_IOCTLPTR_REQ
= 0x9,
172 MSG_TYPE_IOCTLPTR_REQ_ACK
= 0xA,
173 MSG_TYPE_IOCTLRESP_BUF_POST
= 0xB,
174 MSG_TYPE_IOCTL_CMPLT
= 0xC,
175 MSG_TYPE_EVENT_BUF_POST
= 0xD,
176 MSG_TYPE_WL_EVENT
= 0xE,
177 MSG_TYPE_TX_POST
= 0xF,
178 MSG_TYPE_TX_STATUS
= 0x10,
179 MSG_TYPE_RXBUF_POST
= 0x11,
180 MSG_TYPE_RX_CMPLT
= 0x12,
181 MSG_TYPE_LPBK_DMAXFER
= 0x13,
182 MSG_TYPE_LPBK_DMAXFER_CMPLT
= 0x14,
183 MSG_TYPE_FLOW_RING_RESUME
= 0x15,
184 MSG_TYPE_FLOW_RING_RESUME_CMPLT
= 0x16,
185 MSG_TYPE_FLOW_RING_SUSPEND
= 0x17,
186 MSG_TYPE_FLOW_RING_SUSPEND_CMPLT
= 0x18,
187 MSG_TYPE_INFO_BUF_POST
= 0x19,
188 MSG_TYPE_INFO_BUF_CMPLT
= 0x1A,
189 MSG_TYPE_H2D_RING_CREATE
= 0x1B,
190 MSG_TYPE_D2H_RING_CREATE
= 0x1C,
191 MSG_TYPE_H2D_RING_CREATE_CMPLT
= 0x1D,
192 MSG_TYPE_D2H_RING_CREATE_CMPLT
= 0x1E,
193 MSG_TYPE_H2D_RING_CONFIG
= 0x1F,
194 MSG_TYPE_D2H_RING_CONFIG
= 0x20,
195 MSG_TYPE_H2D_RING_CONFIG_CMPLT
= 0x21,
196 MSG_TYPE_D2H_RING_CONFIG_CMPLT
= 0x22,
197 MSG_TYPE_H2D_MAILBOX_DATA
= 0x23,
198 MSG_TYPE_D2H_MAILBOX_DATA
= 0x24,
199 MSG_TYPE_TIMSTAMP_BUFPOST
= 0x25,
200 MSG_TYPE_HOSTTIMSTAMP
= 0x26,
201 MSG_TYPE_HOSTTIMSTAMP_CMPLT
= 0x27,
202 MSG_TYPE_FIRMWARE_TIMESTAMP
= 0x28,
203 MSG_TYPE_SNAPSHOT_UPLOAD
= 0x29,
204 MSG_TYPE_SNAPSHOT_CMPLT
= 0x2A,
205 MSG_TYPE_H2D_RING_DELETE
= 0x2B,
206 MSG_TYPE_D2H_RING_DELETE
= 0x2C,
207 MSG_TYPE_H2D_RING_DELETE_CMPLT
= 0x2D,
208 MSG_TYPE_D2H_RING_DELETE_CMPLT
= 0x2E,
209 MSG_TYPE_API_MAX_RSVD
= 0x3F
210 } bcmpcie_msg_type_t
;
212 typedef enum bcmpcie_msgtype_int
{
213 MSG_TYPE_INTERNAL_USE_START
= 0x40,
214 MSG_TYPE_EVENT_PYLD
= 0x41,
215 MSG_TYPE_IOCT_PYLD
= 0x42,
216 MSG_TYPE_RX_PYLD
= 0x43,
217 MSG_TYPE_HOST_FETCH
= 0x44,
218 MSG_TYPE_LPBK_DMAXFER_PYLD
= 0x45,
219 MSG_TYPE_TXMETADATA_PYLD
= 0x46,
220 MSG_TYPE_INDX_UPDATE
= 0x47,
221 MSG_TYPE_INFO_PYLD
= 0x48,
222 MSG_TYPE_TS_EVENT_PYLD
= 0x49,
223 MSG_TYPE_PVT_BTLOG_CMPLT
= 0x4A,
224 MSG_TYPE_BTLOG_PYLD
= 0x4B,
225 MSG_TYPE_HMAPTEST_PYLD
= 0x4C,
226 MSG_TYPE_PVT_BT_SNAPSHOT_CMPLT
= 0x4D,
227 MSG_TYPE_BT_SNAPSHOT_PYLD
= 0x4E
228 } bcmpcie_msgtype_int_t
;
230 typedef enum bcmpcie_msgtype_u
{
231 MSG_TYPE_TX_BATCH_POST
= 0x80,
232 MSG_TYPE_IOCTL_REQ
= 0x81,
233 MSG_TYPE_HOST_EVNT
= 0x82, /* console related */
234 MSG_TYPE_LOOPBACK
= 0x83
235 } bcmpcie_msgtype_u_t
;
238 * D2H ring host wakeup soft doorbell, override the PCIE doorbell.
239 * Host configures an <32bit address,value> tuple, and dongle uses SBTOPCIE
240 * Transl0 to write specified value to host address.
242 * Use case: 32bit Address mapped to HW Accelerator Core/Thread Wakeup Register
243 * and value is Core/Thread context. Host will ensure routing the 32bit address
244 * offerred to PCIE to the mapped register.
246 * D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL
248 typedef struct bcmpcie_soft_doorbell
{
249 uint32 value
; /* host defined value to be written, eg HW threadid */
250 bcm_addr64_t haddr
; /* host address, eg thread wakeup register address */
251 uint16 items
; /* interrupt coalescing: item count before wakeup */
252 uint16 msecs
; /* interrupt coalescing: timeout in millisecs */
253 } bcmpcie_soft_doorbell_t
;
256 * D2H interrupt using MSI instead of INTX
257 * Host configures MSI vector offset for each D2H interrupt
259 * D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL
261 typedef enum bcmpcie_msi_intr_idx
{
262 MSI_INTR_IDX_CTRL_CMPL_RING
= 0,
263 MSI_INTR_IDX_TXP_CMPL_RING
= 1,
264 MSI_INTR_IDX_RXP_CMPL_RING
= 2,
265 MSI_INTR_IDX_INFO_CMPL_RING
= 3,
266 MSI_INTR_IDX_MAILBOX
= 4,
268 } bcmpcie_msi_intr_idx_t
;
270 #define BCMPCIE_D2H_MSI_OFFSET_SINGLE 0
271 typedef enum bcmpcie_msi_offset_type
{
272 BCMPCIE_D2H_MSI_OFFSET_MB0
= 2,
273 BCMPCIE_D2H_MSI_OFFSET_MB1
= 3,
274 BCMPCIE_D2H_MSI_OFFSET_DB0
= 4,
275 BCMPCIE_D2H_MSI_OFFSET_DB1
= 5,
276 BCMPCIE_D2H_MSI_OFFSET_H1_DB0
= 6,
277 BCMPCIE_D2H_MSI_OFFSET_MAX
= 7
278 } bcmpcie_msi_offset_type_t
;
280 typedef struct bcmpcie_msi_offset
{
281 uint16 intr_idx
; /* interrupt index */
282 uint16 msi_offset
; /* msi vector offset */
283 } bcmpcie_msi_offset_t
;
285 typedef struct bcmpcie_msi_offset_config
{
287 bcmpcie_msi_offset_t bcmpcie_msi_offset
[MSI_INTR_IDX_MAX
];
288 } bcmpcie_msi_offset_config_t
;
290 #define BCMPCIE_D2H_MSI_OFFSET_DEFAULT BCMPCIE_D2H_MSI_OFFSET_DB1
292 #define BCMPCIE_D2H_MSI_SINGLE 0xFFFE
295 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT 5
296 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX 0x7
297 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_MASK \
298 (BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX << BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT)
299 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_SHFT 0
300 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_MAX 0x1F
301 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_MASK \
302 (BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX << BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT)
305 #define BCMPCIE_CMNHDR_FLAGS_DMA_R_IDX 0x1
306 #define BCMPCIE_CMNHDR_FLAGS_DMA_R_IDX_INTR 0x2
307 #define BCMPCIE_CMNHDR_FLAGS_TS_SEQNUM_INIT 0x4
308 #define BCMPCIE_CMNHDR_FLAGS_PHASE_BIT 0x80
309 #define BCMPCIE_CMNHDR_PHASE_BIT_INIT 0x80
311 /* IOCTL request message */
312 typedef struct ioctl_req_msg
{
313 /** common message header */
314 cmn_msg_hdr_t cmn_hdr
;
315 /** ioctl command type */
317 /** ioctl transaction ID, to pair with a ioctl response */
319 /** input arguments buffer len */
320 uint16 input_buf_len
;
321 /** expected output len */
322 uint16 output_buf_len
;
323 /** to align the host address on 8 byte boundary */
325 /** always align on 8 byte boundary */
326 bcm_addr64_t host_input_buf_addr
;
331 /** buffer post messages for device to use to return IOCTL responses, Events */
332 typedef struct ioctl_resp_evt_buf_post_msg
{
333 /** common message header */
334 cmn_msg_hdr_t cmn_hdr
;
335 /** length of the host buffer supplied */
337 /** to align the host address on 8 byte boundary */
339 /** always align on 8 byte boundary */
340 bcm_addr64_t host_buf_addr
;
342 } ioctl_resp_evt_buf_post_msg_t
;
344 /* buffer post messages for device to use to return dbg buffers */
345 typedef ioctl_resp_evt_buf_post_msg_t info_buf_post_msg_t
;
347 #define DHD_INFOBUF_RX_BUFPOST_PKTSZ (2 * 1024)
349 #define DHD_BTLOG_RX_BUFPOST_PKTSZ (2 * 1024)
351 /* An infobuf host buffer starts with a 32 bit (LE) version. */
352 #define PCIE_INFOBUF_V1 1
353 /* Infobuf v1 type MSGTRACE's data is exactly the same as the MSGTRACE data that
354 * is wrapped previously/also in a WLC_E_TRACE event. See structure
355 * msgrace_hdr_t in msgtrace.h.
357 #define PCIE_INFOBUF_V1_TYPE_MSGTRACE 1
359 /* Infobuf v1 type LOGTRACE data is exactly the same as the LOGTRACE data that
360 * is wrapped previously/also in a WLC_E_TRACE event. See structure
361 * msgrace_hdr_t in msgtrace.h. (The only difference between a MSGTRACE
362 * and a LOGTRACE is the "trace type" field.)
364 #define PCIE_INFOBUF_V1_TYPE_LOGTRACE 2
366 /* An infobuf version 1 host buffer has a single TLV. The information on the
367 * version 1 types follow this structure definition. (int's LE)
369 typedef struct info_buf_payload_hdr_s
{
372 } info_buf_payload_hdr_t
;
374 /* BT logs/memory to DMA directly from BT memory to host */
375 typedef struct info_buf_btlog_s
{
376 void (*status_cb
)(void *ctx
, void *p
, int error
); /* obsolete - to be removed */
378 dma64addr_t src_addr
;
380 bool (*pcie_status_cb
)(osl_t
*osh
, void *p
, int error
);
385 /** snapshot upload request message */
386 typedef struct snapshot_upload_request_msg
{
387 /** common message header */
388 cmn_msg_hdr_t cmn_hdr
;
389 /** length of the snaphost buffer supplied */
390 uint32 snapshot_buf_len
;
391 /** type of snapshot */
393 /** snapshot param */
394 uint8 snapshot_param
;
395 /** to align the host address on 8 byte boundary */
397 /** always align on 8 byte boundary */
398 bcm_addr64_t host_buf_addr
;
400 } snapshot_upload_request_msg_t
;
402 /** snapshot types */
403 typedef enum bcmpcie_snapshot_type
{
404 SNAPSHOT_TYPE_BT
= 0, /* Bluetooth SRAM and patch RAM */
405 SNAPSHOT_TYPE_WLAN_SOCRAM
= 1, /* WLAN SOCRAM */
406 SNAPSHOT_TYPE_WLAN_HEAP
= 2, /* WLAN HEAP */
407 SNAPSHOT_TYPE_WLAN_REGISTER
= 3 /* WLAN registers */
408 } bcmpcie_snapshot_type_t
;
410 #define PCIE_DMA_XFER_FLG_D11_LPBK_MASK 0xF
411 #define PCIE_DMA_XFER_FLG_D11_LPBK_SHIFT 2
412 #define PCIE_DMA_XFER_FLG_CORE_NUMBER_MASK 3
413 #define PCIE_DMA_XFER_FLG_CORE_NUMBER_SHIFT 0
415 typedef struct pcie_dma_xfer_params
{
416 /** common message header */
417 cmn_msg_hdr_t cmn_hdr
;
419 /** always align on 8 byte boundary */
420 bcm_addr64_t host_input_buf_addr
;
422 /** always align on 8 byte boundary */
423 bcm_addr64_t host_ouput_buf_addr
;
425 /** length of transfer */
427 /** delay before doing the src txfer */
429 /** delay before doing the dest txfer */
432 /* bit0: D11 DMA loopback flag */
434 } pcie_dma_xfer_params_t
;
436 /** Complete msgbuf hdr for flow ring update from host to dongle */
437 typedef struct tx_flowring_create_request
{
439 uint8 da
[ETHER_ADDR_LEN
];
440 uint8 sa
[ETHER_ADDR_LEN
];
445 /* priority_ifrmmask is to define core mask in ifrm mode.
446 * currently it is not used for priority. so uses solely for ifrm mask
448 uint8 priority_ifrmmask
;
452 bcm_addr64_t flow_ring_ptr
;
453 } tx_flowring_create_request_t
;
455 typedef struct tx_flowring_delete_request
{
460 } tx_flowring_delete_request_t
;
462 typedef tx_flowring_delete_request_t d2h_ring_delete_req_t
;
463 typedef tx_flowring_delete_request_t h2d_ring_delete_req_t
;
465 typedef struct tx_flowring_flush_request
{
470 } tx_flowring_flush_request_t
;
472 /** Subtypes for ring_config_req control message */
473 typedef enum ring_config_subtype
{
474 /** Default D2H PCIE doorbell override using ring_config_req msg */
475 D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL
= 1, /* Software doorbell */
476 D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL
= 2 /* MSI configuration */
477 } ring_config_subtype_t
;
479 typedef struct ring_config_req
{
486 /** D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL */
487 bcmpcie_soft_doorbell_t soft_doorbell
;
488 /** D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL */
489 bcmpcie_msi_offset_config_t msi_offset
;
493 /* data structure to use to create on the fly d2h rings */
494 typedef struct d2h_ring_create_req
{
499 bcm_addr64_t ring_ptr
;
503 } d2h_ring_create_req_t
;
505 /* data structure to use to create on the fly h2d rings */
506 #define MAX_COMPLETION_RING_IDS_ASSOCIATED 4
507 typedef struct h2d_ring_create_req
{
511 uint8 n_completion_ids
;
513 bcm_addr64_t ring_ptr
;
516 uint16 completion_ring_ids
[MAX_COMPLETION_RING_IDS_ASSOCIATED
];
518 } h2d_ring_create_req_t
;
520 typedef struct d2h_ring_config_req
{
522 uint16 d2h_ring_config_subtype
;
524 uint32 d2h_ring_config_data
[4];
526 } d2h_ring_config_req_t
;
528 typedef struct h2d_ring_config_req
{
530 uint16 h2d_ring_config_subtype
;
532 uint32 h2d_ring_config_data
;
534 } h2d_ring_config_req_t
;
536 typedef struct h2d_mailbox_data
{
538 uint32 mail_box_data
;
540 } h2d_mailbox_data_t
;
541 typedef struct host_timestamp_msg
{
543 uint16 xt_id
; /* transaction ID */
544 uint16 input_data_len
; /* data len at the host_buf_addr, data in TLVs */
545 uint16 seqnum
; /* number of times host captured the timestamp */
547 /* always align on 8 byte boundary */
548 bcm_addr64_t host_buf_addr
;
551 } host_timestamp_msg_t
;
553 /* buffer post message for timestamp events MSG_TYPE_TIMSTAMP_BUFPOST */
554 typedef ioctl_resp_evt_buf_post_msg_t ts_buf_post_msg_t
;
556 typedef union ctrl_submit_item
{
557 ioctl_req_msg_t ioctl_req
;
558 ioctl_resp_evt_buf_post_msg_t resp_buf_post
;
559 pcie_dma_xfer_params_t dma_xfer
;
560 tx_flowring_create_request_t flow_create
;
561 tx_flowring_delete_request_t flow_delete
;
562 tx_flowring_flush_request_t flow_flush
;
563 ring_config_req_t ring_config_req
;
564 d2h_ring_create_req_t d2h_create
;
565 h2d_ring_create_req_t h2d_create
;
566 d2h_ring_config_req_t d2h_config
;
567 h2d_ring_config_req_t h2d_config
;
568 h2d_mailbox_data_t h2d_mailbox_data
;
569 host_timestamp_msg_t host_ts
;
570 ts_buf_post_msg_t ts_buf_post
;
571 d2h_ring_delete_req_t d2h_delete
;
572 h2d_ring_delete_req_t h2d_delete
;
573 unsigned char check
[H2DRING_CTRL_SUB_ITEMSIZE
];
574 } ctrl_submit_item_t
;
576 typedef struct info_ring_submit_item
{
577 info_buf_post_msg_t info_buf_post
;
578 unsigned char check
[H2DRING_INFO_BUFPOST_ITEMSIZE
];
579 } info_sumbit_item_t
;
581 /** Control Completion messages (20 bytes) */
582 typedef struct compl_msg_hdr
{
584 /** status for the completion */
587 /* mutually exclusive with pkt fate debug feature */
588 struct pktts_compl_hdr
{
589 uint16 d_t4
; /* Delta TimeStamp 3: T4-tref */
592 /** submisison flow ring id which generated this status */
599 /** XOR checksum or a magic number to audit DMA done */
600 typedef uint32 dma_done_t
;
602 #define MAX_CLKSRC_ID 0xF
603 #define TX_PKT_RETRY_CNT_0_MASK 0x000000FF
604 #define TX_PKT_RETRY_CNT_0_SHIFT 0
605 #define TX_PKT_RETRY_CNT_1_MASK 0x0000FF00
606 #define TX_PKT_RETRY_CNT_1_SHIFT 8
607 #define TX_PKT_RETRY_CNT_2_MASK 0x00FF0000
608 #define TX_PKT_RETRY_CNT_2_SHIFT 16
609 #define TX_PKT_BAND_INFO 0x0F000000
610 #define TX_PKT_BAND_INFO_SHIFT 24
611 #define TX_PKT_VALID_INFO 0xF0000000
612 #define TX_PKT_VALID_INFO_SHIFT 28
614 typedef struct ts_timestamp_srcid
{
616 uint32 ts_low
; /* time stamp low 32 bits */
617 uint32 rate_spec
; /* use ratespec */
620 uint32 ts_high
; /* time stamp high 28 bits */
622 uint32 ts_high_ext
:28; /* time stamp high 28 bits */
623 uint32 clk_id_ext
:3; /* clock ID source */
624 uint32 phase
:1; /* Phase bit */
625 dma_done_t marker_ext
;
627 uint32 tx_pkt_band_retry_info
;
629 } ts_timestamp_srcid_t
;
631 typedef ts_timestamp_srcid_t ipc_timestamp_t
;
633 typedef struct ts_timestamp
{
638 typedef ts_timestamp_t tick_count_64_t
;
639 typedef ts_timestamp_t ts_timestamp_ns_64_t
;
640 typedef ts_timestamp_t ts_correction_m_t
;
641 typedef ts_timestamp_t ts_correction_b_t
;
643 typedef struct _pktts
{
644 uint32 tref
; /* Ref Clk in uSec (currently, tsf) */
645 uint16 d_t2
; /* Delta TimeStamp 1: T2-tref */
646 uint16 d_t3
; /* Delta TimeStamp 2: T3-tref */
649 /* completion header status codes */
650 #define BCMPCIE_SUCCESS 0
651 #define BCMPCIE_NOTFOUND 1
652 #define BCMPCIE_NOMEM 2
653 #define BCMPCIE_BADOPTION 3
654 #define BCMPCIE_RING_IN_USE 4
655 #define BCMPCIE_RING_ID_INVALID 5
656 #define BCMPCIE_PKT_FLUSH 6
657 #define BCMPCIE_NO_EVENT_BUF 7
658 #define BCMPCIE_NO_RX_BUF 8
659 #define BCMPCIE_NO_IOCTLRESP_BUF 9
660 #define BCMPCIE_MAX_IOCTLRESP_BUF 10
661 #define BCMPCIE_MAX_EVENT_BUF 11
662 #define BCMPCIE_BAD_PHASE 12
663 #define BCMPCIE_INVALID_CPL_RINGID 13
664 #define BCMPCIE_RING_TYPE_INVALID 14
665 #define BCMPCIE_NO_TS_EVENT_BUF 15
666 #define BCMPCIE_MAX_TS_EVENT_BUF 16
667 #define BCMPCIE_PCIE_NO_BTLOG_BUF 17
668 #define BCMPCIE_BT_DMA_ERR 18
669 #define BCMPCIE_BT_DMA_DESCR_FETCH_ERR 19
670 #define BCMPCIE_SNAPSHOT_ERR 20
671 #define BCMPCIE_NOT_READY 21
672 #define BCMPCIE_INVALID_DATA 22
673 #define BCMPCIE_NO_RESPONSE 23
674 #define BCMPCIE_NO_CLOCK 24
676 /** IOCTL completion response */
677 typedef struct ioctl_compl_resp_msg
{
678 /** common message header */
679 cmn_msg_hdr_t cmn_hdr
;
680 /** completion message header */
681 compl_msg_hdr_t compl_hdr
;
682 /** response buffer len where a host buffer is involved */
684 /** transaction id to pair with a request */
688 /** XOR checksum or a magic number to audit DMA done */
690 } ioctl_comp_resp_msg_t
;
692 /** IOCTL request acknowledgement */
693 typedef struct ioctl_req_ack_msg
{
694 /** common message header */
695 cmn_msg_hdr_t cmn_hdr
;
696 /** completion message header */
697 compl_msg_hdr_t compl_hdr
;
701 /** XOR checksum or a magic number to audit DMA done */
703 } ioctl_req_ack_msg_t
;
705 /** WL event message: send from device to host */
706 typedef struct wlevent_req_msg
{
707 /** common message header */
708 cmn_msg_hdr_t cmn_hdr
;
709 /** completion message header */
710 compl_msg_hdr_t compl_hdr
;
711 /** event data len valid with the event buffer */
712 uint16 event_data_len
;
713 /** sequence number */
717 /** XOR checksum or a magic number to audit DMA done */
721 /** dma xfer complete message */
722 typedef struct pcie_dmaxfer_cmplt
{
723 /** common message header */
724 cmn_msg_hdr_t cmn_hdr
;
725 /** completion message header */
726 compl_msg_hdr_t compl_hdr
;
728 /** XOR checksum or a magic number to audit DMA done */
730 } pcie_dmaxfer_cmplt_t
;
732 /** general status message */
733 typedef struct pcie_gen_status
{
734 /** common message header */
735 cmn_msg_hdr_t cmn_hdr
;
736 /** completion message header */
737 compl_msg_hdr_t compl_hdr
;
739 /** XOR checksum or a magic number to audit DMA done */
743 /** ring status message */
744 typedef struct pcie_ring_status
{
745 /** common message header */
746 cmn_msg_hdr_t cmn_hdr
;
747 /** completion message header */
748 compl_msg_hdr_t compl_hdr
;
749 /** message which firmware couldn't decode */
752 /** XOR checksum or a magic number to audit DMA done */
754 } pcie_ring_status_t
;
756 typedef struct ring_create_response
{
757 cmn_msg_hdr_t cmn_hdr
;
758 compl_msg_hdr_t cmplt
;
760 /** XOR checksum or a magic number to audit DMA done */
762 } ring_create_response_t
;
764 typedef ring_create_response_t tx_flowring_create_response_t
;
765 typedef ring_create_response_t h2d_ring_create_response_t
;
766 typedef ring_create_response_t d2h_ring_create_response_t
;
768 typedef struct tx_flowring_delete_response
{
770 compl_msg_hdr_t cmplt
;
773 /** XOR checksum or a magic number to audit DMA done */
775 } tx_flowring_delete_response_t
;
777 typedef tx_flowring_delete_response_t h2d_ring_delete_response_t
;
778 typedef tx_flowring_delete_response_t d2h_ring_delete_response_t
;
780 typedef struct tx_flowring_flush_response
{
782 compl_msg_hdr_t cmplt
;
784 /** XOR checksum or a magic number to audit DMA done */
786 } tx_flowring_flush_response_t
;
788 /** Common layout of all d2h control messages */
789 typedef struct ctrl_compl_msg
{
790 /** common message header */
791 cmn_msg_hdr_t cmn_hdr
;
792 /** completion message header */
793 compl_msg_hdr_t compl_hdr
;
795 /** XOR checksum or a magic number to audit DMA done */
799 typedef struct ring_config_resp
{
800 /** common message header */
801 cmn_msg_hdr_t cmn_hdr
;
802 /** completion message header */
803 compl_msg_hdr_t compl_hdr
;
806 /** XOR checksum or a magic number to audit DMA done */
808 } ring_config_resp_t
;
810 typedef struct d2h_mailbox_data
{
812 compl_msg_hdr_t cmplt
;
813 uint32 d2h_mailbox_data
;
815 /* XOR checksum or a magic number to audit DMA done */
817 } d2h_mailbox_data_t
;
819 /* dbg buf completion msg: send from device to host */
820 typedef struct info_buf_resp
{
821 /* common message header */
822 cmn_msg_hdr_t cmn_hdr
;
823 /* completion message header */
824 compl_msg_hdr_t compl_hdr
;
825 /* event data len valid with the event buffer */
826 uint16 info_data_len
;
827 /* sequence number */
833 /* XOR checksum or a magic number to audit DMA done */
837 /* snapshot completion msg: send from device to host */
838 typedef struct snapshot_resp
{
839 /* common message header */
840 cmn_msg_hdr_t cmn_hdr
;
841 /* completion message header */
842 compl_msg_hdr_t compl_hdr
;
843 /* snapshot length uploaded */
849 /* XOR checksum or a magic number to audit DMA done */
853 typedef struct info_ring_cpl_item
{
854 info_buf_resp_t info_buf_post
;
855 unsigned char check
[D2HRING_INFO_BUFCMPLT_ITEMSIZE
];
858 typedef struct host_timestamp_msg_cpl
{
860 compl_msg_hdr_t cmplt
;
861 uint16 xt_id
; /* transaction ID */
864 /* XOR checksum or a magic number to audit DMA done */
866 } host_timestamp_msg_cpl_t
;
868 typedef struct fw_timestamp_event_msg
{
870 compl_msg_hdr_t cmplt
;
871 /* fw captures time stamp info and passed that to host in TLVs */
872 uint16 buf_len
; /* length of the time stamp data copied in host buf */
873 uint16 seqnum
; /* number of times fw captured time stamp */
875 /* XOR checksum or a magic number to audit DMA done */
877 } fw_timestamp_event_msg_t
;
879 typedef union ctrl_completion_item
{
880 ioctl_comp_resp_msg_t ioctl_resp
;
881 wlevent_req_msg_t event
;
882 ioctl_req_ack_msg_t ioct_ack
;
883 pcie_dmaxfer_cmplt_t pcie_xfer_cmplt
;
884 pcie_gen_status_t pcie_gen_status
;
885 pcie_ring_status_t pcie_ring_status
;
886 tx_flowring_create_response_t txfl_create_resp
;
887 tx_flowring_delete_response_t txfl_delete_resp
;
888 tx_flowring_flush_response_t txfl_flush_resp
;
889 ctrl_compl_msg_t ctrl_compl
;
890 ring_config_resp_t ring_config_resp
;
891 d2h_mailbox_data_t d2h_mailbox_data
;
892 info_buf_resp_t dbg_resp
;
893 h2d_ring_create_response_t h2d_ring_create_resp
;
894 d2h_ring_create_response_t d2h_ring_create_resp
;
895 host_timestamp_msg_cpl_t host_ts_cpl
;
896 fw_timestamp_event_msg_t fw_ts_event
;
897 h2d_ring_delete_response_t h2d_ring_delete_resp
;
898 d2h_ring_delete_response_t d2h_ring_delete_resp
;
899 unsigned char ctrl_response
[D2HRING_CTRL_CMPLT_ITEMSIZE
];
900 } ctrl_completion_item_t
;
902 /** H2D Rxpost ring work items */
903 typedef struct host_rxbuf_post
{
904 /** common message header */
905 cmn_msg_hdr_t cmn_hdr
;
906 /** provided meta data buffer len */
907 uint16 metadata_buf_len
;
908 /** provided data buffer len to receive data */
910 /** alignment to make the host buffers start on 8 byte boundary */
912 /** provided meta data buffer */
913 bcm_addr64_t metadata_buf_addr
;
914 /** provided data buffer to receive data */
915 bcm_addr64_t data_buf_addr
;
918 typedef union rxbuf_submit_item
{
919 host_rxbuf_post_t rxpost
;
920 unsigned char check
[H2DRING_RXPOST_ITEMSIZE
];
921 } rxbuf_submit_item_t
;
923 /* D2H Rxcompletion ring work items for IPC rev7 */
924 typedef struct host_rxbuf_cmpl
{
925 /** common message header */
926 cmn_msg_hdr_t cmn_hdr
;
927 /** completion message header */
928 compl_msg_hdr_t compl_hdr
;
929 /** filled up meta data len */
931 /** filled up buffer len to receive data */
933 /** offset in the host rx buffer where the data starts */
935 /** offset in the host rx buffer where the data starts */
941 union { /* size per IPC = (3 x uint32) bytes */
943 /* used by Monitor mode */
949 /* LatTS_With_XORCSUM */
951 /* latency timestamp */
953 /* XOR checksum or a magic number to audit DMA done */
954 dma_done_t marker_ext
;
959 typedef union rxbuf_complete_item
{
960 host_rxbuf_cmpl_t rxcmpl
;
961 unsigned char check
[D2HRING_RXCMPLT_ITEMSIZE
];
962 } rxbuf_complete_item_t
;
964 typedef struct host_txbuf_post
{
965 /** common message header */
966 cmn_msg_hdr_t cmn_hdr
;
968 uint8 txhdr
[ETHER_HDR_LEN
];
971 /** number of segments */
974 /** provided meta data buffer for txstatus */
975 bcm_addr64_t metadata_buf_addr
;
976 /** provided data buffer to receive data */
977 bcm_addr64_t data_buf_addr
;
978 /** provided meta data buffer len */
979 uint16 metadata_buf_len
;
980 /** provided data buffer len to receive data */
984 /** extended transmit flags */
988 /** user defined rate */
992 /** XOR checksum or a magic number to audit DMA done */
997 #define BCMPCIE_PKT_FLAGS_FRAME_802_3 0x01
998 #define BCMPCIE_PKT_FLAGS_FRAME_802_11 0x02
1000 #define BCMPCIE_PKT_FLAGS_FRAME_NORETRY 0x01 /* Disable retry on this frame */
1001 #define BCMPCIE_PKT_FLAGS_FRAME_NOAGGR 0x02 /* Disable aggregation for this frame */
1002 #define BCMPCIE_PKT_FLAGS_FRAME_UDR 0x04 /* User defined rate for this frame */
1003 #define BCMPCIE_PKT_FLAGS_FRAME_ATTR_MASK 0x07 /* Attribute mask */
1005 #define BCMPCIE_PKT_FLAGS_FRAME_EXEMPT_MASK 0x03 /* Exempt uses 2 bits */
1006 #define BCMPCIE_PKT_FLAGS_FRAME_EXEMPT_SHIFT 0x02 /* needs to be shifted past other bits */
1008 #define BCMPCIE_PKT_FLAGS_PRIO_SHIFT 5
1009 #define BCMPCIE_PKT_FLAGS_PRIO_MASK (7 << BCMPCIE_PKT_FLAGS_PRIO_SHIFT)
1010 #define BCMPCIE_PKT_FLAGS_MONITOR_NO_AMSDU 0x00
1011 #define BCMPCIE_PKT_FLAGS_MONITOR_FIRST_PKT 0x01
1012 #define BCMPCIE_PKT_FLAGS_MONITOR_INTER_PKT 0x02
1013 #define BCMPCIE_PKT_FLAGS_MONITOR_LAST_PKT 0x03
1014 #define BCMPCIE_PKT_FLAGS_MONITOR_SHIFT 8
1015 #define BCMPCIE_PKT_FLAGS_MONITOR_MASK (3 << BCMPCIE_PKT_FLAGS_MONITOR_SHIFT)
1017 /* These are added to fix up compile issues */
1018 #define BCMPCIE_TXPOST_FLAGS_FRAME_802_3 BCMPCIE_PKT_FLAGS_FRAME_802_3
1019 #define BCMPCIE_TXPOST_FLAGS_FRAME_802_11 BCMPCIE_PKT_FLAGS_FRAME_802_11
1020 #define BCMPCIE_TXPOST_FLAGS_PRIO_SHIFT BCMPCIE_PKT_FLAGS_PRIO_SHIFT
1021 #define BCMPCIE_TXPOST_FLAGS_PRIO_MASK BCMPCIE_PKT_FLAGS_PRIO_MASK
1023 /* H2D Txpost ring work items */
1024 typedef union txbuf_submit_item
{
1025 host_txbuf_post_t txpost
;
1026 unsigned char check
[H2DRING_TXPOST_ITEMSIZE
];
1027 } txbuf_submit_item_t
;
1029 /* D2H Txcompletion ring work items - extended for IOC rev7 */
1030 typedef struct host_txbuf_cmpl
{
1031 /** common message header */
1032 cmn_msg_hdr_t cmn_hdr
;
1033 /** completion message header */
1034 compl_msg_hdr_t compl_hdr
;
1036 union { /* size per IPC = (3 x uint32) bytes */
1037 /* Usage 1: TxS_With_TimeSync */
1041 /** provided meta data len */
1042 uint16 metadata_len
;
1043 /** provided extended TX status */
1044 uint16 tx_status_ext
;
1045 }; /*Ext_TxStatus */
1047 /** WLAN side txstatus */
1052 }; /* TxS_with_TS */
1054 /* Usage 2: LatTS_With_XORCSUM */
1056 /* latency timestamp */
1058 /* XOR checksum or a magic number to audit DMA done */
1059 dma_done_t marker_ext
;
1063 } host_txbuf_cmpl_t
;
1065 typedef union txbuf_complete_item
{
1066 host_txbuf_cmpl_t txcmpl
;
1067 unsigned char check
[D2HRING_TXCMPLT_ITEMSIZE
];
1068 } txbuf_complete_item_t
;
1070 #define BCMPCIE_D2H_METADATA_HDRLEN 4
1071 #define BCMPCIE_D2H_METADATA_MINLEN (BCMPCIE_D2H_METADATA_HDRLEN + 4)
1073 /** ret buf struct */
1074 typedef struct ret_buf_ptr
{
1079 #ifdef PCIE_API_REV1
1081 /* ioctl specific hdr */
1082 typedef struct ioctl_hdr
{
1088 typedef struct ioctlptr_hdr
{
1096 #else /* PCIE_API_REV1 */
1098 typedef struct ioctl_req_hdr
{
1099 uint32 pkt_id
; /**< Packet ID */
1100 uint32 cmd
; /**< IOCTL ID */
1103 uint16 xt_id
; /**< transaction ID */
1107 #endif /* PCIE_API_REV1 */
1109 /** Complete msgbuf hdr for ioctl from host to dongle */
1110 typedef struct ioct_reqst_hdr
{
1112 #ifdef PCIE_API_REV1
1113 ioctl_hdr_t ioct_hdr
;
1115 ioctl_req_hdr_t ioct_hdr
;
1120 typedef struct ioctptr_reqst_hdr
{
1122 #ifdef PCIE_API_REV1
1123 ioctlptr_hdr_t ioct_hdr
;
1125 ioctl_req_hdr_t ioct_hdr
;
1129 } ioctptr_reqst_hdr_t
;
1131 /** ioctl response header */
1132 typedef struct ioct_resp_hdr
{
1134 #ifdef PCIE_API_REV1
1142 #ifdef PCIE_API_REV1
1144 uint16 xt_id
; /**< transaction ID */
1149 /* ioct resp header used in dongle */
1150 /* ret buf hdr will be stripped off inside dongle itself */
1151 typedef struct msgbuf_ioctl_resp
{
1152 ioct_resp_hdr_t ioct_hdr
;
1153 ret_buf_t ret_buf
; /**< ret buf pointers */
1154 } msgbuf_ioct_resp_t
;
1156 /** WL event hdr info */
1157 typedef struct wl_event_hdr
{
1167 #define TXDESCR_FLOWID_PCIELPBK_1 0xFF
1168 #define TXDESCR_FLOWID_PCIELPBK_2 0xFE
1170 typedef struct txbatch_lenptr_tup
{
1174 ret_buf_t ret_buf
; /**< ret buf pointers */
1175 } txbatch_lenptr_tup_t
;
1177 typedef struct txbatch_cmn_msghdr
{
1183 uint8 txhdr
[ETHER_HDR_LEN
];
1185 } txbatch_cmn_msghdr_t
;
1187 typedef struct txbatch_msghdr
{
1188 txbatch_cmn_msghdr_t txcmn
;
1189 txbatch_lenptr_tup_t tx_tup
[0]; /**< Based on packet count */
1192 /* TX desc posting header */
1193 typedef struct tx_lenptr_tup
{
1196 ret_buf_t ret_buf
; /**< ret buf pointers */
1199 typedef struct txdescr_cmn_msghdr
{
1206 } txdescr_cmn_msghdr_t
;
1208 typedef struct txdescr_msghdr
{
1209 txdescr_cmn_msghdr_t txcmn
;
1210 uint8 txhdr
[ETHER_HDR_LEN
];
1212 tx_lenptr_tup_t tx_tup
[0]; /**< Based on descriptor count */
1215 /** Tx status header info */
1216 typedef struct txstatus_hdr
{
1221 /** RX bufid-len-ptr tuple */
1222 typedef struct rx_lenptr_tup
{
1226 ret_buf_t ret_buf
; /**< ret buf pointers */
1229 /** Rx descr Post hdr info */
1230 typedef struct rxdesc_msghdr
{
1235 rx_lenptr_tup_t rx_tup
[0];
1238 /** RX complete tuples */
1239 typedef struct rxcmplt_tup
{
1247 /** RX complete messge hdr */
1248 typedef struct rxcmplt_hdr
{
1252 rxcmplt_tup_t rx_tup
[0];
1255 typedef struct hostevent_hdr
{
1260 typedef struct dma_xfer_params
{
1261 uint32 src_physaddr_hi
;
1262 uint32 src_physaddr_lo
;
1263 uint32 dest_physaddr_hi
;
1264 uint32 dest_physaddr_lo
;
1268 } dma_xfer_params_t
;
1271 HOST_EVENT_CONS_CMD
= 1
1274 /* defines for flags */
1275 #define MSGBUF_IOC_ACTION_MASK 0x1
1277 #define MAX_SUSPEND_REQ 15
1279 typedef struct tx_idle_flowring_suspend_request
{
1281 uint16 ring_id
[MAX_SUSPEND_REQ
]; /* ring Id's */
1282 uint16 num
; /* number of flowid's to suspend */
1283 } tx_idle_flowring_suspend_request_t
;
1285 typedef struct tx_idle_flowring_suspend_response
{
1287 compl_msg_hdr_t cmplt
;
1290 } tx_idle_flowring_suspend_response_t
;
1292 typedef struct tx_idle_flowring_resume_request
{
1294 uint16 flow_ring_id
;
1297 } tx_idle_flowring_resume_request_t
;
1299 typedef struct tx_idle_flowring_resume_response
{
1301 compl_msg_hdr_t cmplt
;
1304 } tx_idle_flowring_resume_response_t
;
1306 /* timesync related additions */
1308 typedef struct _bcm_xtlv
{
1309 uint16 id
; /* TLV idenitifier */
1310 uint16 len
; /* TLV length in bytes */
1313 #define BCMMSGBUF_FW_CLOCK_INFO_TAG 0
1314 #define BCMMSGBUF_HOST_CLOCK_INFO_TAG 1
1315 #define BCMMSGBUF_HOST_CLOCK_SELECT_TAG 2
1316 #define BCMMSGBUF_D2H_CLOCK_CORRECTION_TAG 3
1317 #define BCMMSGBUF_HOST_TIMESTAMPING_CONFIG_TAG 4
1318 #define BCMMSGBUF_MAX_TSYNC_TAG 5
1320 /* Flags in fw clock info TLV */
1321 #define CAP_DEVICE_TS (1 << 0)
1322 #define CAP_CORRECTED_TS (1 << 1)
1323 #define TS_CLK_ACTIVE (1 << 2)
1325 typedef struct ts_fw_clock_info
{
1326 _bcm_xtlv_t xtlv
; /* BCMMSGBUF_FW_CLOCK_INFO_TAG */
1327 ts_timestamp_srcid_t ts
; /* tick count */
1328 uchar clk_src
[4]; /* clock source acronym ILP/AVB/TSF */
1329 uint32 nominal_clock_freq
;
1333 } ts_fw_clock_info_t
;
1335 typedef struct ts_host_clock_info
{
1336 _bcm_xtlv_t xtlv
; /* BCMMSGBUF_HOST_CLOCK_INFO_TAG */
1337 tick_count_64_t ticks
; /* 64 bit host tick counter */
1338 ts_timestamp_ns_64_t ns
; /* 64 bit host time in nano seconds */
1339 } ts_host_clock_info_t
;
1341 typedef struct ts_host_clock_sel
{
1342 _bcm_xtlv_t xtlv
; /* BCMMSGBUF_HOST_CLOCK_SELECT_TAG */
1343 uint32 seqnum
; /* number of times GPIO time sync toggled */
1344 uint8 min_clk_idx
; /* clock idenitifer configured for packet tiem stamping */
1345 uint8 max_clk_idx
; /* clock idenitifer configured for packet tiem stamping */
1347 } ts_host_clock_sel_t
;
1349 typedef struct ts_d2h_clock_correction
{
1350 _bcm_xtlv_t xtlv
; /* BCMMSGBUF_HOST_CLOCK_INFO_TAG */
1351 uint8 clk_id
; /* clock source in the device */
1353 ts_correction_m_t m
; /* y = 'm' x + b */
1354 ts_correction_b_t b
; /* y = 'm' x + 'c' */
1355 } ts_d2h_clock_correction_t
;
1357 typedef struct ts_host_timestamping_config
{
1358 _bcm_xtlv_t xtlv
; /* BCMMSGBUF_HOST_TIMESTAMPING_CONFIG_TAG */
1359 /* time period to capture the device time stamp and toggle WLAN_TIME_SYNC_GPIO */
1364 } ts_host_timestamping_config_t
;
1366 /* Flags in host timestamping config TLV */
1367 #define FLAG_HOST_RESET (1 << 0)
1368 #define IS_HOST_RESET(x) ((x) & FLAG_HOST_RESET)
1369 #define CLEAR_HOST_RESET(x) ((x) & ~FLAG_HOST_RESET)
1371 #define FLAG_CONFIG_NODROP (1 << 1)
1372 #define IS_CONFIG_NODROP(x) ((x) & FLAG_CONFIG_NODROP)
1373 #define CLEAR_CONFIG_NODROP(x) ((x) & ~FLAG_CONFIG_NODROP)
1375 #endif /* _bcmmsgbuf_h_ */