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[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / net / wireless / bcmdhd4361 / include / bcmmsgbuf.h
1 /*
2 * MSGBUF network driver ioctl/indication encoding
3 * Broadcom 802.11abg Networking Device Driver
4 *
5 * Definitions subject to change without notice.
6 *
7 * Copyright (C) 1999-2019, Broadcom.
8 *
9 * Unless you and Broadcom execute a separate written software license
10 * agreement governing use of this software, this software is licensed to you
11 * under the terms of the GNU General Public License version 2 (the "GPL"),
12 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
13 * following added to such license:
14 *
15 * As a special exception, the copyright holders of this software give you
16 * permission to link this software with independent modules, and to copy and
17 * distribute the resulting executable under terms of your choice, provided that
18 * you also meet, for each linked independent module, the terms and conditions of
19 * the license of that module. An independent module is a module which is not
20 * derived from this software. The special exception does not apply to any
21 * modifications of the software.
22 *
23 * Notwithstanding the above, under no circumstances may you combine this
24 * software in any way with any other Broadcom software provided under a license
25 * other than the GPL, without Broadcom's express prior written consent.
26 *
27 *
28 * <<Broadcom-WL-IPTag/Open:>>
29 *
30 * $Id: bcmmsgbuf.h 739442 2018-01-08 17:45:01Z $
31 */
32 #ifndef _bcmmsgbuf_h_
33 #define _bcmmsgbuf_h_
34
35 #include <ethernet.h>
36 #include <wlioctl.h>
37 #include <bcmpcie.h>
38
39 #define MSGBUF_MAX_MSG_SIZE ETHER_MAX_LEN
40
41 #define D2H_EPOCH_MODULO 253 /* sequence number wrap */
42 #define D2H_EPOCH_INIT_VAL (D2H_EPOCH_MODULO + 1)
43
44 #define H2D_EPOCH_MODULO 253 /* sequence number wrap */
45 #define H2D_EPOCH_INIT_VAL (H2D_EPOCH_MODULO + 1)
46
47 #define H2DRING_TXPOST_ITEMSIZE 48
48 #define H2DRING_RXPOST_ITEMSIZE 32
49 #define H2DRING_CTRL_SUB_ITEMSIZE 40
50
51 #define D2HRING_TXCMPLT_ITEMSIZE 24
52 #define D2HRING_RXCMPLT_ITEMSIZE 40
53
54 #define D2HRING_TXCMPLT_ITEMSIZE_PREREV7 16
55 #define D2HRING_RXCMPLT_ITEMSIZE_PREREV7 32
56
57 #define D2HRING_CTRL_CMPLT_ITEMSIZE 24
58 #define H2DRING_INFO_BUFPOST_ITEMSIZE H2DRING_CTRL_SUB_ITEMSIZE
59 #define D2HRING_INFO_BUFCMPLT_ITEMSIZE D2HRING_CTRL_CMPLT_ITEMSIZE
60
61 #define D2HRING_SNAPSHOT_CMPLT_ITEMSIZE 20
62
63 #define H2DRING_TXPOST_MAX_ITEM 512
64 #define H2DRING_RXPOST_MAX_ITEM 512
65 #define H2DRING_CTRL_SUB_MAX_ITEM 64
66 #define D2HRING_TXCMPLT_MAX_ITEM 1024
67 #define D2HRING_RXCMPLT_MAX_ITEM 512
68
69 #define H2DRING_DYNAMIC_INFO_MAX_ITEM 32
70 #define D2HRING_DYNAMIC_INFO_MAX_ITEM 32
71
72 #define D2HRING_CTRL_CMPLT_MAX_ITEM 64
73
74 enum {
75 DNGL_TO_HOST_MSGBUF,
76 HOST_TO_DNGL_MSGBUF
77 };
78
79 enum {
80 HOST_TO_DNGL_TXP_DATA,
81 HOST_TO_DNGL_RXP_DATA,
82 HOST_TO_DNGL_CTRL,
83 DNGL_TO_HOST_DATA,
84 DNGL_TO_HOST_CTRL
85 };
86
87 #define MESSAGE_PAYLOAD(a) (a & MSG_TYPE_INTERNAL_USE_START) ? TRUE : FALSE
88 #define PCIEDEV_FIRMWARE_TSINFO 0x1
89 #define PCIEDEV_FIRMWARE_TSINFO_FIRST 0x1
90 #define PCIEDEV_FIRMWARE_TSINFO_MIDDLE 0x2
91 #define PCIEDEV_BTLOG_POST 0x3
92 #define PCIEDEV_BT_SNAPSHOT_POST 0x4
93
94 #ifdef PCIE_API_REV1
95
96 #define BCMMSGBUF_DUMMY_REF(a, b) do {BCM_REFERENCE((a));BCM_REFERENCE((b));} while (0)
97
98 #define BCMMSGBUF_API_IFIDX(a) 0
99 #define BCMMSGBUF_API_SEQNUM(a) 0
100 #define BCMMSGBUF_IOCTL_XTID(a) 0
101 #define BCMMSGBUF_IOCTL_PKTID(a) ((a)->cmd_id)
102
103 #define BCMMSGBUF_SET_API_IFIDX(a, b) BCMMSGBUF_DUMMY_REF(a, b)
104 #define BCMMSGBUF_SET_API_SEQNUM(a, b) BCMMSGBUF_DUMMY_REF(a, b)
105 #define BCMMSGBUF_IOCTL_SET_PKTID(a, b) (BCMMSGBUF_IOCTL_PKTID(a) = (b))
106 #define BCMMSGBUF_IOCTL_SET_XTID(a, b) BCMMSGBUF_DUMMY_REF(a, b)
107
108 #else /* PCIE_API_REV1 */
109
110 #define BCMMSGBUF_API_IFIDX(a) ((a)->if_id)
111 #define BCMMSGBUF_IOCTL_PKTID(a) ((a)->pkt_id)
112 #define BCMMSGBUF_API_SEQNUM(a) ((a)->u.seq.seq_no)
113 #define BCMMSGBUF_IOCTL_XTID(a) ((a)->xt_id)
114
115 #define BCMMSGBUF_SET_API_IFIDX(a, b) (BCMMSGBUF_API_IFIDX((a)) = (b))
116 #define BCMMSGBUF_SET_API_SEQNUM(a, b) (BCMMSGBUF_API_SEQNUM((a)) = (b))
117 #define BCMMSGBUF_IOCTL_SET_PKTID(a, b) (BCMMSGBUF_IOCTL_PKTID((a)) = (b))
118 #define BCMMSGBUF_IOCTL_SET_XTID(a, b) (BCMMSGBUF_IOCTL_XTID((a)) = (b))
119
120 #endif /* PCIE_API_REV1 */
121
122 /* utility data structures */
123
124 union addr64 {
125 struct {
126 uint32 low;
127 uint32 high;
128 };
129 struct {
130 uint32 low_addr;
131 uint32 high_addr;
132 };
133 uint64 u64;
134 } DECLSPEC_ALIGN(8);
135
136 typedef union addr64 bcm_addr64_t;
137
138 /* IOCTL req Hdr */
139 /* cmn Msg Hdr */
140 typedef struct cmn_msg_hdr {
141 /** message type */
142 uint8 msg_type;
143 /** interface index this is valid for */
144 uint8 if_id;
145 /* flags */
146 uint8 flags;
147 /** sequence number */
148 uint8 epoch;
149 /** packet Identifier for the associated host buffer */
150 uint32 request_id;
151 } cmn_msg_hdr_t;
152
153 /** message type */
154 typedef enum bcmpcie_msgtype {
155 MSG_TYPE_GEN_STATUS = 0x1,
156 MSG_TYPE_RING_STATUS = 0x2,
157 MSG_TYPE_FLOW_RING_CREATE = 0x3,
158 MSG_TYPE_FLOW_RING_CREATE_CMPLT = 0x4,
159 /* Enum value as copied from BISON 7.15: new generic message */
160 MSG_TYPE_RING_CREATE_CMPLT = 0x4,
161 MSG_TYPE_FLOW_RING_DELETE = 0x5,
162 MSG_TYPE_FLOW_RING_DELETE_CMPLT = 0x6,
163 /* Enum value as copied from BISON 7.15: new generic message */
164 MSG_TYPE_RING_DELETE_CMPLT = 0x6,
165 MSG_TYPE_FLOW_RING_FLUSH = 0x7,
166 MSG_TYPE_FLOW_RING_FLUSH_CMPLT = 0x8,
167 MSG_TYPE_IOCTLPTR_REQ = 0x9,
168 MSG_TYPE_IOCTLPTR_REQ_ACK = 0xA,
169 MSG_TYPE_IOCTLRESP_BUF_POST = 0xB,
170 MSG_TYPE_IOCTL_CMPLT = 0xC,
171 MSG_TYPE_EVENT_BUF_POST = 0xD,
172 MSG_TYPE_WL_EVENT = 0xE,
173 MSG_TYPE_TX_POST = 0xF,
174 MSG_TYPE_TX_STATUS = 0x10,
175 MSG_TYPE_RXBUF_POST = 0x11,
176 MSG_TYPE_RX_CMPLT = 0x12,
177 MSG_TYPE_LPBK_DMAXFER = 0x13,
178 MSG_TYPE_LPBK_DMAXFER_CMPLT = 0x14,
179 MSG_TYPE_FLOW_RING_RESUME = 0x15,
180 MSG_TYPE_FLOW_RING_RESUME_CMPLT = 0x16,
181 MSG_TYPE_FLOW_RING_SUSPEND = 0x17,
182 MSG_TYPE_FLOW_RING_SUSPEND_CMPLT = 0x18,
183 MSG_TYPE_INFO_BUF_POST = 0x19,
184 MSG_TYPE_INFO_BUF_CMPLT = 0x1A,
185 MSG_TYPE_H2D_RING_CREATE = 0x1B,
186 MSG_TYPE_D2H_RING_CREATE = 0x1C,
187 MSG_TYPE_H2D_RING_CREATE_CMPLT = 0x1D,
188 MSG_TYPE_D2H_RING_CREATE_CMPLT = 0x1E,
189 MSG_TYPE_H2D_RING_CONFIG = 0x1F,
190 MSG_TYPE_D2H_RING_CONFIG = 0x20,
191 MSG_TYPE_H2D_RING_CONFIG_CMPLT = 0x21,
192 MSG_TYPE_D2H_RING_CONFIG_CMPLT = 0x22,
193 MSG_TYPE_H2D_MAILBOX_DATA = 0x23,
194 MSG_TYPE_D2H_MAILBOX_DATA = 0x24,
195 MSG_TYPE_TIMSTAMP_BUFPOST = 0x25,
196 MSG_TYPE_HOSTTIMSTAMP = 0x26,
197 MSG_TYPE_HOSTTIMSTAMP_CMPLT = 0x27,
198 MSG_TYPE_FIRMWARE_TIMESTAMP = 0x28,
199 MSG_TYPE_SNAPSHOT_UPLOAD = 0x29,
200 MSG_TYPE_SNAPSHOT_CMPLT = 0x2A,
201 MSG_TYPE_H2D_RING_DELETE = 0x2B,
202 MSG_TYPE_D2H_RING_DELETE = 0x2C,
203 MSG_TYPE_H2D_RING_DELETE_CMPLT = 0x2D,
204 MSG_TYPE_D2H_RING_DELETE_CMPLT = 0x2E,
205 MSG_TYPE_API_MAX_RSVD = 0x3F
206 } bcmpcie_msg_type_t;
207
208 typedef enum bcmpcie_msgtype_int {
209 MSG_TYPE_INTERNAL_USE_START = 0x40,
210 MSG_TYPE_EVENT_PYLD = 0x41,
211 MSG_TYPE_IOCT_PYLD = 0x42,
212 MSG_TYPE_RX_PYLD = 0x43,
213 MSG_TYPE_HOST_FETCH = 0x44,
214 MSG_TYPE_LPBK_DMAXFER_PYLD = 0x45,
215 MSG_TYPE_TXMETADATA_PYLD = 0x46,
216 MSG_TYPE_INDX_UPDATE = 0x47,
217 MSG_TYPE_INFO_PYLD = 0x48,
218 MSG_TYPE_TS_EVENT_PYLD = 0x49,
219 MSG_TYPE_PVT_BTLOG_CMPLT = 0x4A,
220 MSG_TYPE_BTLOG_PYLD = 0x4B,
221 MSG_TYPE_HMAPTEST_PYLD = 0x4C,
222 MSG_TYPE_PVT_BT_SNAPSHOT_CMPLT = 0x4D,
223 MSG_TYPE_BT_SNAPSHOT_PYLD = 0x4E
224 } bcmpcie_msgtype_int_t;
225
226 typedef enum bcmpcie_msgtype_u {
227 MSG_TYPE_TX_BATCH_POST = 0x80,
228 MSG_TYPE_IOCTL_REQ = 0x81,
229 MSG_TYPE_HOST_EVNT = 0x82, /* console related */
230 MSG_TYPE_LOOPBACK = 0x83
231 } bcmpcie_msgtype_u_t;
232
233 /**
234 * D2H ring host wakeup soft doorbell, override the PCIE doorbell.
235 * Host configures an <32bit address,value> tuple, and dongle uses SBTOPCIE
236 * Transl0 to write specified value to host address.
237 *
238 * Use case: 32bit Address mapped to HW Accelerator Core/Thread Wakeup Register
239 * and value is Core/Thread context. Host will ensure routing the 32bit address
240 * offerred to PCIE to the mapped register.
241 *
242 * D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL
243 */
244 typedef struct bcmpcie_soft_doorbell {
245 uint32 value; /* host defined value to be written, eg HW threadid */
246 bcm_addr64_t haddr; /* host address, eg thread wakeup register address */
247 uint16 items; /* interrupt coalescing: item count before wakeup */
248 uint16 msecs; /* interrupt coalescing: timeout in millisecs */
249 } bcmpcie_soft_doorbell_t;
250
251 /**
252 * D2H interrupt using MSI instead of INTX
253 * Host configures MSI vector offset for each D2H interrupt
254 *
255 * D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL
256 */
257 typedef enum bcmpcie_msi_intr_idx {
258 MSI_INTR_IDX_CTRL_CMPL_RING = 0,
259 MSI_INTR_IDX_TXP_CMPL_RING = 1,
260 MSI_INTR_IDX_RXP_CMPL_RING = 2,
261 MSI_INTR_IDX_INFO_CMPL_RING = 3,
262 MSI_INTR_IDX_MAILBOX = 4,
263 MSI_INTR_IDX_MAX = 5
264 } bcmpcie_msi_intr_idx_t;
265
266 #define BCMPCIE_D2H_MSI_OFFSET_SINGLE 0
267 typedef enum bcmpcie_msi_offset_type {
268 BCMPCIE_D2H_MSI_OFFSET_MB0 = 2,
269 BCMPCIE_D2H_MSI_OFFSET_MB1 = 3,
270 BCMPCIE_D2H_MSI_OFFSET_DB0 = 4,
271 BCMPCIE_D2H_MSI_OFFSET_DB1 = 5,
272 BCMPCIE_D2H_MSI_OFFSET_H1_DB0 = 6,
273 BCMPCIE_D2H_MSI_OFFSET_MAX = 7
274 } bcmpcie_msi_offset_type_t;
275
276 typedef struct bcmpcie_msi_offset {
277 uint16 intr_idx; /* interrupt index */
278 uint16 msi_offset; /* msi vector offset */
279 } bcmpcie_msi_offset_t;
280
281 typedef struct bcmpcie_msi_offset_config {
282 uint32 len;
283 bcmpcie_msi_offset_t bcmpcie_msi_offset[MSI_INTR_IDX_MAX];
284 } bcmpcie_msi_offset_config_t;
285
286 #define BCMPCIE_D2H_MSI_OFFSET_DEFAULT BCMPCIE_D2H_MSI_OFFSET_DB1
287
288 #define BCMPCIE_D2H_MSI_SINGLE 0xFFFE
289
290 /* if_id */
291 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT 5
292 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX 0x7
293 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_MASK \
294 (BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX << BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT)
295 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_SHFT 0
296 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_MAX 0x1F
297 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_MASK \
298 (BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX << BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT)
299
300 /* flags */
301 #define BCMPCIE_CMNHDR_FLAGS_DMA_R_IDX 0x1
302 #define BCMPCIE_CMNHDR_FLAGS_DMA_R_IDX_INTR 0x2
303 #define BCMPCIE_CMNHDR_FLAGS_TS_SEQNUM_INIT 0x4
304 #define BCMPCIE_CMNHDR_FLAGS_PHASE_BIT 0x80
305 #define BCMPCIE_CMNHDR_PHASE_BIT_INIT 0x80
306
307 /* IOCTL request message */
308 typedef struct ioctl_req_msg {
309 /** common message header */
310 cmn_msg_hdr_t cmn_hdr;
311 /** ioctl command type */
312 uint32 cmd;
313 /** ioctl transaction ID, to pair with a ioctl response */
314 uint16 trans_id;
315 /** input arguments buffer len */
316 uint16 input_buf_len;
317 /** expected output len */
318 uint16 output_buf_len;
319 /** to align the host address on 8 byte boundary */
320 uint16 rsvd[3];
321 /** always align on 8 byte boundary */
322 bcm_addr64_t host_input_buf_addr;
323 /* rsvd */
324 uint32 rsvd1[2];
325 } ioctl_req_msg_t;
326
327 /** buffer post messages for device to use to return IOCTL responses, Events */
328 typedef struct ioctl_resp_evt_buf_post_msg {
329 /** common message header */
330 cmn_msg_hdr_t cmn_hdr;
331 /** length of the host buffer supplied */
332 uint16 host_buf_len;
333 /** to align the host address on 8 byte boundary */
334 uint16 reserved[3];
335 /** always align on 8 byte boundary */
336 bcm_addr64_t host_buf_addr;
337 uint32 rsvd[4];
338 } ioctl_resp_evt_buf_post_msg_t;
339
340 /* buffer post messages for device to use to return dbg buffers */
341 typedef ioctl_resp_evt_buf_post_msg_t info_buf_post_msg_t;
342
343 #define DHD_INFOBUF_RX_BUFPOST_PKTSZ (2 * 1024)
344
345 #define DHD_BTLOG_RX_BUFPOST_PKTSZ (2 * 1024)
346
347 /* An infobuf host buffer starts with a 32 bit (LE) version. */
348 #define PCIE_INFOBUF_V1 1
349 /* Infobuf v1 type MSGTRACE's data is exactly the same as the MSGTRACE data that
350 * is wrapped previously/also in a WLC_E_TRACE event. See structure
351 * msgrace_hdr_t in msgtrace.h.
352 */
353 #define PCIE_INFOBUF_V1_TYPE_MSGTRACE 1
354
355 /* Infobuf v1 type LOGTRACE data is exactly the same as the LOGTRACE data that
356 * is wrapped previously/also in a WLC_E_TRACE event. See structure
357 * msgrace_hdr_t in msgtrace.h. (The only difference between a MSGTRACE
358 * and a LOGTRACE is the "trace type" field.)
359 */
360 #define PCIE_INFOBUF_V1_TYPE_LOGTRACE 2
361
362 /* An infobuf version 1 host buffer has a single TLV. The information on the
363 * version 1 types follow this structure definition. (int's LE)
364 */
365 typedef struct info_buf_payload_hdr_s {
366 uint16 type;
367 uint16 length;
368 } info_buf_payload_hdr_t;
369
370 /* BT logs/memory to DMA directly from BT memory to host */
371 typedef struct info_buf_btlog_s {
372 void (*status_cb)(void *ctx, void *p, int error); /* obsolete - to be removed */
373 void *ctx;
374 dma64addr_t src_addr;
375 uint32 length;
376 bool (*pcie_status_cb)(osl_t *osh, void *p, int error);
377 uint32 bt_intstatus;
378 int error;
379 } info_buf_btlog_t;
380
381 /** snapshot upload request message */
382 typedef struct snapshot_upload_request_msg {
383 /** common message header */
384 cmn_msg_hdr_t cmn_hdr;
385 /** length of the snaphost buffer supplied */
386 uint32 snapshot_buf_len;
387 /** type of snapshot */
388 uint8 snapshot_type;
389 /** snapshot param */
390 uint8 snapshot_param;
391 /** to align the host address on 8 byte boundary */
392 uint8 reserved[2];
393 /** always align on 8 byte boundary */
394 bcm_addr64_t host_buf_addr;
395 uint32 rsvd[4];
396 } snapshot_upload_request_msg_t;
397
398 /** snapshot types */
399 typedef enum bcmpcie_snapshot_type {
400 SNAPSHOT_TYPE_BT = 0, /* Bluetooth SRAM and patch RAM */
401 SNAPSHOT_TYPE_WLAN_SOCRAM = 1, /* WLAN SOCRAM */
402 SNAPSHOT_TYPE_WLAN_HEAP = 2, /* WLAN HEAP */
403 SNAPSHOT_TYPE_WLAN_REGISTER = 3 /* WLAN registers */
404 } bcmpcie_snapshot_type_t;
405
406 #define PCIE_DMA_XFER_FLG_D11_LPBK_MASK 0xF
407 #define PCIE_DMA_XFER_FLG_D11_LPBK_SHIFT 2
408 #define PCIE_DMA_XFER_FLG_CORE_NUMBER_MASK 3
409 #define PCIE_DMA_XFER_FLG_CORE_NUMBER_SHIFT 0
410
411 typedef struct pcie_dma_xfer_params {
412 /** common message header */
413 cmn_msg_hdr_t cmn_hdr;
414
415 /** always align on 8 byte boundary */
416 bcm_addr64_t host_input_buf_addr;
417
418 /** always align on 8 byte boundary */
419 bcm_addr64_t host_ouput_buf_addr;
420
421 /** length of transfer */
422 uint32 xfer_len;
423 /** delay before doing the src txfer */
424 uint32 srcdelay;
425 /** delay before doing the dest txfer */
426 uint32 destdelay;
427 uint8 rsvd[3];
428 /* bit0: D11 DMA loopback flag */
429 uint8 flags;
430 } pcie_dma_xfer_params_t;
431
432 /** Complete msgbuf hdr for flow ring update from host to dongle */
433 typedef struct tx_flowring_create_request {
434 cmn_msg_hdr_t msg;
435 uint8 da[ETHER_ADDR_LEN];
436 uint8 sa[ETHER_ADDR_LEN];
437 uint8 tid;
438 uint8 if_flags;
439 uint16 flow_ring_id;
440 uint8 tc;
441 /* priority_ifrmmask is to define core mask in ifrm mode.
442 * currently it is not used for priority. so uses solely for ifrm mask
443 */
444 uint8 priority_ifrmmask;
445 uint16 int_vector;
446 uint16 max_items;
447 uint16 len_item;
448 bcm_addr64_t flow_ring_ptr;
449 } tx_flowring_create_request_t;
450
451 typedef struct tx_flowring_delete_request {
452 cmn_msg_hdr_t msg;
453 uint16 flow_ring_id;
454 uint16 reason;
455 uint32 rsvd[7];
456 } tx_flowring_delete_request_t;
457
458 typedef tx_flowring_delete_request_t d2h_ring_delete_req_t;
459 typedef tx_flowring_delete_request_t h2d_ring_delete_req_t;
460
461 typedef struct tx_flowring_flush_request {
462 cmn_msg_hdr_t msg;
463 uint16 flow_ring_id;
464 uint16 reason;
465 uint32 rsvd[7];
466 } tx_flowring_flush_request_t;
467
468 /** Subtypes for ring_config_req control message */
469 typedef enum ring_config_subtype {
470 /** Default D2H PCIE doorbell override using ring_config_req msg */
471 D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL = 1, /* Software doorbell */
472 D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL = 2 /* MSI configuration */
473 } ring_config_subtype_t;
474
475 typedef struct ring_config_req {
476 cmn_msg_hdr_t msg;
477 uint16 subtype;
478 uint16 ring_id;
479 uint32 rsvd;
480 union {
481 uint32 data[6];
482 /** D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL */
483 bcmpcie_soft_doorbell_t soft_doorbell;
484 /** D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL */
485 bcmpcie_msi_offset_config_t msi_offset;
486 };
487 } ring_config_req_t;
488
489 /* data structure to use to create on the fly d2h rings */
490 typedef struct d2h_ring_create_req {
491 cmn_msg_hdr_t msg;
492 uint16 ring_id;
493 uint16 ring_type;
494 uint32 flags;
495 bcm_addr64_t ring_ptr;
496 uint16 max_items;
497 uint16 len_item;
498 uint32 rsvd[3];
499 } d2h_ring_create_req_t;
500
501 /* data structure to use to create on the fly h2d rings */
502 #define MAX_COMPLETION_RING_IDS_ASSOCIATED 4
503 typedef struct h2d_ring_create_req {
504 cmn_msg_hdr_t msg;
505 uint16 ring_id;
506 uint8 ring_type;
507 uint8 n_completion_ids;
508 uint32 flags;
509 bcm_addr64_t ring_ptr;
510 uint16 max_items;
511 uint16 len_item;
512 uint16 completion_ring_ids[MAX_COMPLETION_RING_IDS_ASSOCIATED];
513 uint32 rsvd;
514 } h2d_ring_create_req_t;
515
516 typedef struct d2h_ring_config_req {
517 cmn_msg_hdr_t msg;
518 uint16 d2h_ring_config_subtype;
519 uint16 d2h_ring_id;
520 uint32 d2h_ring_config_data[4];
521 uint32 rsvd[3];
522 } d2h_ring_config_req_t;
523
524 typedef struct h2d_ring_config_req {
525 cmn_msg_hdr_t msg;
526 uint16 h2d_ring_config_subtype;
527 uint16 h2d_ring_id;
528 uint32 h2d_ring_config_data;
529 uint32 rsvd[6];
530 } h2d_ring_config_req_t;
531
532 typedef struct h2d_mailbox_data {
533 cmn_msg_hdr_t msg;
534 uint32 mail_box_data;
535 uint32 rsvd[7];
536 } h2d_mailbox_data_t;
537 typedef struct host_timestamp_msg {
538 cmn_msg_hdr_t msg;
539 uint16 xt_id; /* transaction ID */
540 uint16 input_data_len; /* data len at the host_buf_addr, data in TLVs */
541 uint16 seqnum; /* number of times host captured the timestamp */
542 uint16 rsvd;
543 /* always align on 8 byte boundary */
544 bcm_addr64_t host_buf_addr;
545 /* rsvd */
546 uint32 rsvd1[4];
547 } host_timestamp_msg_t;
548
549 /* buffer post message for timestamp events MSG_TYPE_TIMSTAMP_BUFPOST */
550 typedef ioctl_resp_evt_buf_post_msg_t ts_buf_post_msg_t;
551
552 typedef union ctrl_submit_item {
553 ioctl_req_msg_t ioctl_req;
554 ioctl_resp_evt_buf_post_msg_t resp_buf_post;
555 pcie_dma_xfer_params_t dma_xfer;
556 tx_flowring_create_request_t flow_create;
557 tx_flowring_delete_request_t flow_delete;
558 tx_flowring_flush_request_t flow_flush;
559 ring_config_req_t ring_config_req;
560 d2h_ring_create_req_t d2h_create;
561 h2d_ring_create_req_t h2d_create;
562 d2h_ring_config_req_t d2h_config;
563 h2d_ring_config_req_t h2d_config;
564 h2d_mailbox_data_t h2d_mailbox_data;
565 host_timestamp_msg_t host_ts;
566 ts_buf_post_msg_t ts_buf_post;
567 d2h_ring_delete_req_t d2h_delete;
568 h2d_ring_delete_req_t h2d_delete;
569 unsigned char check[H2DRING_CTRL_SUB_ITEMSIZE];
570 } ctrl_submit_item_t;
571
572 typedef struct info_ring_submit_item {
573 info_buf_post_msg_t info_buf_post;
574 unsigned char check[H2DRING_INFO_BUFPOST_ITEMSIZE];
575 } info_sumbit_item_t;
576
577 /** Control Completion messages (20 bytes) */
578 typedef struct compl_msg_hdr {
579 /** status for the completion */
580 int16 status;
581 /** submisison flow ring id which generated this status */
582 union {
583 uint16 ring_id;
584 uint16 flow_ring_id;
585 };
586 } compl_msg_hdr_t;
587
588 /** XOR checksum or a magic number to audit DMA done */
589 typedef uint32 dma_done_t;
590
591 #define MAX_CLKSRC_ID 0xF
592 #define TX_PKT_RETRY_CNT_0_MASK 0x000000FF
593 #define TX_PKT_RETRY_CNT_0_SHIFT 0
594 #define TX_PKT_RETRY_CNT_1_MASK 0x0000FF00
595 #define TX_PKT_RETRY_CNT_1_SHIFT 8
596 #define TX_PKT_RETRY_CNT_2_MASK 0x00FF0000
597 #define TX_PKT_RETRY_CNT_2_SHIFT 16
598 #define TX_PKT_BAND_INFO 0x0F000000
599 #define TX_PKT_BAND_INFO_SHIFT 24
600 #define TX_PKT_VALID_INFO 0xF0000000
601 #define TX_PKT_VALID_INFO_SHIFT 28
602
603 typedef struct ts_timestamp_srcid {
604 union {
605 uint32 ts_low; /* time stamp low 32 bits */
606 uint32 rate_spec; /* use ratespec */
607 };
608 union {
609 uint32 ts_high; /* time stamp high 28 bits */
610 union {
611 uint32 ts_high_ext :28; /* time stamp high 28 bits */
612 uint32 clk_id_ext :3; /* clock ID source */
613 uint32 phase :1; /* Phase bit */
614 dma_done_t marker_ext;
615 };
616 uint32 tx_pkt_band_retry_info;
617 };
618 } ts_timestamp_srcid_t;
619
620 typedef ts_timestamp_srcid_t ipc_timestamp_t;
621
622 typedef struct ts_timestamp {
623 uint32 low;
624 uint32 high;
625 } ts_timestamp_t;
626
627 typedef ts_timestamp_t tick_count_64_t;
628 typedef ts_timestamp_t ts_timestamp_ns_64_t;
629 typedef ts_timestamp_t ts_correction_m_t;
630 typedef ts_timestamp_t ts_correction_b_t;
631
632 /* completion header status codes */
633 #define BCMPCIE_SUCCESS 0
634 #define BCMPCIE_NOTFOUND 1
635 #define BCMPCIE_NOMEM 2
636 #define BCMPCIE_BADOPTION 3
637 #define BCMPCIE_RING_IN_USE 4
638 #define BCMPCIE_RING_ID_INVALID 5
639 #define BCMPCIE_PKT_FLUSH 6
640 #define BCMPCIE_NO_EVENT_BUF 7
641 #define BCMPCIE_NO_RX_BUF 8
642 #define BCMPCIE_NO_IOCTLRESP_BUF 9
643 #define BCMPCIE_MAX_IOCTLRESP_BUF 10
644 #define BCMPCIE_MAX_EVENT_BUF 11
645 #define BCMPCIE_BAD_PHASE 12
646 #define BCMPCIE_INVALID_CPL_RINGID 13
647 #define BCMPCIE_RING_TYPE_INVALID 14
648 #define BCMPCIE_NO_TS_EVENT_BUF 15
649 #define BCMPCIE_MAX_TS_EVENT_BUF 16
650 #define BCMPCIE_PCIE_NO_BTLOG_BUF 17
651 #define BCMPCIE_BT_DMA_ERR 18
652 #define BCMPCIE_BT_DMA_DESCR_FETCH_ERR 19
653 #define BCMPCIE_SNAPSHOT_ERR 20
654 #define BCMPCIE_NOT_READY 21
655 #define BCMPCIE_INVALID_DATA 22
656 #define BCMPCIE_NO_RESPONSE 23
657 #define BCMPCIE_NO_CLOCK 24
658
659 /** IOCTL completion response */
660 typedef struct ioctl_compl_resp_msg {
661 /** common message header */
662 cmn_msg_hdr_t cmn_hdr;
663 /** completion message header */
664 compl_msg_hdr_t compl_hdr;
665 /** response buffer len where a host buffer is involved */
666 uint16 resp_len;
667 /** transaction id to pair with a request */
668 uint16 trans_id;
669 /** cmd id */
670 uint32 cmd;
671 /** XOR checksum or a magic number to audit DMA done */
672 dma_done_t marker;
673 } ioctl_comp_resp_msg_t;
674
675 /** IOCTL request acknowledgement */
676 typedef struct ioctl_req_ack_msg {
677 /** common message header */
678 cmn_msg_hdr_t cmn_hdr;
679 /** completion message header */
680 compl_msg_hdr_t compl_hdr;
681 /** cmd id */
682 uint32 cmd;
683 uint32 rsvd;
684 /** XOR checksum or a magic number to audit DMA done */
685 dma_done_t marker;
686 } ioctl_req_ack_msg_t;
687
688 /** WL event message: send from device to host */
689 typedef struct wlevent_req_msg {
690 /** common message header */
691 cmn_msg_hdr_t cmn_hdr;
692 /** completion message header */
693 compl_msg_hdr_t compl_hdr;
694 /** event data len valid with the event buffer */
695 uint16 event_data_len;
696 /** sequence number */
697 uint16 seqnum;
698 /** rsvd */
699 uint32 rsvd;
700 /** XOR checksum or a magic number to audit DMA done */
701 dma_done_t marker;
702 } wlevent_req_msg_t;
703
704 /** dma xfer complete message */
705 typedef struct pcie_dmaxfer_cmplt {
706 /** common message header */
707 cmn_msg_hdr_t cmn_hdr;
708 /** completion message header */
709 compl_msg_hdr_t compl_hdr;
710 uint32 rsvd[2];
711 /** XOR checksum or a magic number to audit DMA done */
712 dma_done_t marker;
713 } pcie_dmaxfer_cmplt_t;
714
715 /** general status message */
716 typedef struct pcie_gen_status {
717 /** common message header */
718 cmn_msg_hdr_t cmn_hdr;
719 /** completion message header */
720 compl_msg_hdr_t compl_hdr;
721 uint32 rsvd[2];
722 /** XOR checksum or a magic number to audit DMA done */
723 dma_done_t marker;
724 } pcie_gen_status_t;
725
726 /** ring status message */
727 typedef struct pcie_ring_status {
728 /** common message header */
729 cmn_msg_hdr_t cmn_hdr;
730 /** completion message header */
731 compl_msg_hdr_t compl_hdr;
732 /** message which firmware couldn't decode */
733 uint16 write_idx;
734 uint16 rsvd[3];
735 /** XOR checksum or a magic number to audit DMA done */
736 dma_done_t marker;
737 } pcie_ring_status_t;
738
739 typedef struct ring_create_response {
740 cmn_msg_hdr_t cmn_hdr;
741 compl_msg_hdr_t cmplt;
742 uint32 rsvd[2];
743 /** XOR checksum or a magic number to audit DMA done */
744 dma_done_t marker;
745 } ring_create_response_t;
746
747 typedef ring_create_response_t tx_flowring_create_response_t;
748 typedef ring_create_response_t h2d_ring_create_response_t;
749 typedef ring_create_response_t d2h_ring_create_response_t;
750
751 typedef struct tx_flowring_delete_response {
752 cmn_msg_hdr_t msg;
753 compl_msg_hdr_t cmplt;
754 uint16 read_idx;
755 uint16 rsvd[3];
756 /** XOR checksum or a magic number to audit DMA done */
757 dma_done_t marker;
758 } tx_flowring_delete_response_t;
759
760 typedef tx_flowring_delete_response_t h2d_ring_delete_response_t;
761 typedef tx_flowring_delete_response_t d2h_ring_delete_response_t;
762
763 typedef struct tx_flowring_flush_response {
764 cmn_msg_hdr_t msg;
765 compl_msg_hdr_t cmplt;
766 uint32 rsvd[2];
767 /** XOR checksum or a magic number to audit DMA done */
768 dma_done_t marker;
769 } tx_flowring_flush_response_t;
770
771 /** Common layout of all d2h control messages */
772 typedef struct ctrl_compl_msg {
773 /** common message header */
774 cmn_msg_hdr_t cmn_hdr;
775 /** completion message header */
776 compl_msg_hdr_t compl_hdr;
777 uint32 rsvd[2];
778 /** XOR checksum or a magic number to audit DMA done */
779 dma_done_t marker;
780 } ctrl_compl_msg_t;
781
782 typedef struct ring_config_resp {
783 /** common message header */
784 cmn_msg_hdr_t cmn_hdr;
785 /** completion message header */
786 compl_msg_hdr_t compl_hdr;
787 uint16 subtype;
788 uint16 rsvd[3];
789 /** XOR checksum or a magic number to audit DMA done */
790 dma_done_t marker;
791 } ring_config_resp_t;
792
793 typedef struct d2h_mailbox_data {
794 cmn_msg_hdr_t msg;
795 compl_msg_hdr_t cmplt;
796 uint32 d2h_mailbox_data;
797 uint32 rsvd[1];
798 /* XOR checksum or a magic number to audit DMA done */
799 dma_done_t marker;
800 } d2h_mailbox_data_t;
801
802 /* dbg buf completion msg: send from device to host */
803 typedef struct info_buf_resp {
804 /* common message header */
805 cmn_msg_hdr_t cmn_hdr;
806 /* completion message header */
807 compl_msg_hdr_t compl_hdr;
808 /* event data len valid with the event buffer */
809 uint16 info_data_len;
810 /* sequence number */
811 uint16 seqnum;
812 /* rsvd */
813 uint32 rsvd;
814 /* XOR checksum or a magic number to audit DMA done */
815 dma_done_t marker;
816 } info_buf_resp_t;
817
818 /* snapshot completion msg: send from device to host */
819 typedef struct snapshot_resp {
820 /* common message header */
821 cmn_msg_hdr_t cmn_hdr;
822 /* completion message header */
823 compl_msg_hdr_t compl_hdr;
824 /* snapshot length uploaded */
825 uint32 resp_len;
826 /* snapshot type */
827 uint8 type;
828 /* rsvd */
829 uint8 rsvd[3];
830 /* XOR checksum or a magic number to audit DMA done */
831 dma_done_t marker;
832 } snapshot_resp_t;
833
834 typedef struct info_ring_cpl_item {
835 info_buf_resp_t info_buf_post;
836 unsigned char check[D2HRING_INFO_BUFCMPLT_ITEMSIZE];
837 } info_cpl_item_t;
838
839 typedef struct host_timestamp_msg_cpl {
840 cmn_msg_hdr_t msg;
841 compl_msg_hdr_t cmplt;
842 uint16 xt_id; /* transaction ID */
843 uint16 rsvd;
844 uint32 rsvd1;
845 /* XOR checksum or a magic number to audit DMA done */
846 dma_done_t marker;
847 } host_timestamp_msg_cpl_t;
848
849 typedef struct fw_timestamp_event_msg {
850 cmn_msg_hdr_t msg;
851 compl_msg_hdr_t cmplt;
852 /* fw captures time stamp info and passed that to host in TLVs */
853 uint16 buf_len; /* length of the time stamp data copied in host buf */
854 uint16 seqnum; /* number of times fw captured time stamp */
855 uint32 rsvd;
856 /* XOR checksum or a magic number to audit DMA done */
857 dma_done_t marker;
858 } fw_timestamp_event_msg_t;
859
860 typedef union ctrl_completion_item {
861 ioctl_comp_resp_msg_t ioctl_resp;
862 wlevent_req_msg_t event;
863 ioctl_req_ack_msg_t ioct_ack;
864 pcie_dmaxfer_cmplt_t pcie_xfer_cmplt;
865 pcie_gen_status_t pcie_gen_status;
866 pcie_ring_status_t pcie_ring_status;
867 tx_flowring_create_response_t txfl_create_resp;
868 tx_flowring_delete_response_t txfl_delete_resp;
869 tx_flowring_flush_response_t txfl_flush_resp;
870 ctrl_compl_msg_t ctrl_compl;
871 ring_config_resp_t ring_config_resp;
872 d2h_mailbox_data_t d2h_mailbox_data;
873 info_buf_resp_t dbg_resp;
874 h2d_ring_create_response_t h2d_ring_create_resp;
875 d2h_ring_create_response_t d2h_ring_create_resp;
876 host_timestamp_msg_cpl_t host_ts_cpl;
877 fw_timestamp_event_msg_t fw_ts_event;
878 h2d_ring_delete_response_t h2d_ring_delete_resp;
879 d2h_ring_delete_response_t d2h_ring_delete_resp;
880 unsigned char ctrl_response[D2HRING_CTRL_CMPLT_ITEMSIZE];
881 } ctrl_completion_item_t;
882
883 /** H2D Rxpost ring work items */
884 typedef struct host_rxbuf_post {
885 /** common message header */
886 cmn_msg_hdr_t cmn_hdr;
887 /** provided meta data buffer len */
888 uint16 metadata_buf_len;
889 /** provided data buffer len to receive data */
890 uint16 data_buf_len;
891 /** alignment to make the host buffers start on 8 byte boundary */
892 uint32 rsvd;
893 /** provided meta data buffer */
894 bcm_addr64_t metadata_buf_addr;
895 /** provided data buffer to receive data */
896 bcm_addr64_t data_buf_addr;
897 } host_rxbuf_post_t;
898
899 typedef union rxbuf_submit_item {
900 host_rxbuf_post_t rxpost;
901 unsigned char check[H2DRING_RXPOST_ITEMSIZE];
902 } rxbuf_submit_item_t;
903
904 /* D2H Rxcompletion ring work items for IPC rev7 */
905 typedef struct host_rxbuf_cmpl {
906 /** common message header */
907 cmn_msg_hdr_t cmn_hdr;
908 /** completion message header */
909 compl_msg_hdr_t compl_hdr;
910 /** filled up meta data len */
911 uint16 metadata_len;
912 /** filled up buffer len to receive data */
913 uint16 data_len;
914 /** offset in the host rx buffer where the data starts */
915 uint16 data_offset;
916 /** offset in the host rx buffer where the data starts */
917 uint16 flags;
918 /** rx status */
919 uint32 rx_status_0;
920 uint32 rx_status_1;
921 /** XOR checksum or a magic number to audit DMA done */
922 /* This is for rev6 only. For IPC rev7, this is a reserved field */
923 dma_done_t marker;
924 /* timestamp */
925 ipc_timestamp_t ts;
926 } host_rxbuf_cmpl_t;
927
928 typedef union rxbuf_complete_item {
929 host_rxbuf_cmpl_t rxcmpl;
930 unsigned char check[D2HRING_RXCMPLT_ITEMSIZE];
931 } rxbuf_complete_item_t;
932
933 typedef struct host_txbuf_post {
934 /** common message header */
935 cmn_msg_hdr_t cmn_hdr;
936 /** eth header */
937 uint8 txhdr[ETHER_HDR_LEN];
938 /** flags */
939 uint8 flags;
940 /** number of segments */
941 uint8 seg_cnt;
942
943 /** provided meta data buffer for txstatus */
944 bcm_addr64_t metadata_buf_addr;
945 /** provided data buffer to receive data */
946 bcm_addr64_t data_buf_addr;
947 /** provided meta data buffer len */
948 uint16 metadata_buf_len;
949 /** provided data buffer len to receive data */
950 uint16 data_len;
951 union {
952 struct {
953 /** extended transmit flags */
954 uint8 ext_flags;
955 uint8 rsvd1;
956
957 /** user defined rate */
958 uint8 rate;
959 uint8 rsvd2;
960 };
961 /** XOR checksum or a magic number to audit DMA done */
962 dma_done_t marker;
963 };
964 } host_txbuf_post_t;
965
966 #define BCMPCIE_PKT_FLAGS_FRAME_802_3 0x01
967 #define BCMPCIE_PKT_FLAGS_FRAME_802_11 0x02
968
969 #define BCMPCIE_PKT_FLAGS_FRAME_NORETRY 0x01 /* Disable retry on this frame */
970 #define BCMPCIE_PKT_FLAGS_FRAME_NOAGGR 0x02 /* Disable aggregation for this frame */
971 #define BCMPCIE_PKT_FLAGS_FRAME_UDR 0x04 /* User defined rate for this frame */
972 #define BCMPCIE_PKT_FLAGS_FRAME_ATTR_MASK 0x07 /* Attribute mask */
973
974 #define BCMPCIE_PKT_FLAGS_FRAME_EXEMPT_MASK 0x03 /* Exempt uses 2 bits */
975 #define BCMPCIE_PKT_FLAGS_FRAME_EXEMPT_SHIFT 0x02 /* needs to be shifted past other bits */
976
977 #define BCMPCIE_PKT_FLAGS_PRIO_SHIFT 5
978 #define BCMPCIE_PKT_FLAGS_PRIO_MASK (7 << BCMPCIE_PKT_FLAGS_PRIO_SHIFT)
979 #define BCMPCIE_PKT_FLAGS_MONITOR_NO_AMSDU 0x00
980 #define BCMPCIE_PKT_FLAGS_MONITOR_FIRST_PKT 0x01
981 #define BCMPCIE_PKT_FLAGS_MONITOR_INTER_PKT 0x02
982 #define BCMPCIE_PKT_FLAGS_MONITOR_LAST_PKT 0x03
983 #define BCMPCIE_PKT_FLAGS_MONITOR_SHIFT 8
984 #define BCMPCIE_PKT_FLAGS_MONITOR_MASK (3 << BCMPCIE_PKT_FLAGS_MONITOR_SHIFT)
985
986 /* These are added to fix up compile issues */
987 #define BCMPCIE_TXPOST_FLAGS_FRAME_802_3 BCMPCIE_PKT_FLAGS_FRAME_802_3
988 #define BCMPCIE_TXPOST_FLAGS_FRAME_802_11 BCMPCIE_PKT_FLAGS_FRAME_802_11
989 #define BCMPCIE_TXPOST_FLAGS_PRIO_SHIFT BCMPCIE_PKT_FLAGS_PRIO_SHIFT
990 #define BCMPCIE_TXPOST_FLAGS_PRIO_MASK BCMPCIE_PKT_FLAGS_PRIO_MASK
991
992 /* H2D Txpost ring work items */
993 typedef union txbuf_submit_item {
994 host_txbuf_post_t txpost;
995 unsigned char check[H2DRING_TXPOST_ITEMSIZE];
996 } txbuf_submit_item_t;
997
998 /* D2H Txcompletion ring work items - extended for IOC rev7 */
999 typedef struct host_txbuf_cmpl {
1000 /** common message header */
1001 cmn_msg_hdr_t cmn_hdr;
1002 /** completion message header */
1003 compl_msg_hdr_t compl_hdr;
1004 union {
1005 struct {
1006 union {
1007 /** provided meta data len */
1008 uint16 metadata_len;
1009 /** provided extended TX status */
1010 uint16 tx_status_ext;
1011 };
1012 /** WLAN side txstatus */
1013 uint16 tx_status;
1014 };
1015 /** XOR checksum or a magic number to audit DMA done */
1016 /* This is for rev6 only. For IPC rev7, this is not used */
1017 dma_done_t marker;
1018 };
1019 /* timestamp */
1020 ipc_timestamp_t ts;
1021
1022 } host_txbuf_cmpl_t;
1023
1024 typedef union txbuf_complete_item {
1025 host_txbuf_cmpl_t txcmpl;
1026 unsigned char check[D2HRING_TXCMPLT_ITEMSIZE];
1027 } txbuf_complete_item_t;
1028
1029 #define BCMPCIE_D2H_METADATA_HDRLEN 4
1030 #define BCMPCIE_D2H_METADATA_MINLEN (BCMPCIE_D2H_METADATA_HDRLEN + 4)
1031
1032 /** ret buf struct */
1033 typedef struct ret_buf_ptr {
1034 uint32 low_addr;
1035 uint32 high_addr;
1036 } ret_buf_t;
1037
1038 #ifdef PCIE_API_REV1
1039
1040 /* ioctl specific hdr */
1041 typedef struct ioctl_hdr {
1042 uint16 cmd;
1043 uint16 retbuf_len;
1044 uint32 cmd_id;
1045 } ioctl_hdr_t;
1046
1047 typedef struct ioctlptr_hdr {
1048 uint16 cmd;
1049 uint16 retbuf_len;
1050 uint16 buflen;
1051 uint16 rsvd;
1052 uint32 cmd_id;
1053 } ioctlptr_hdr_t;
1054
1055 #else /* PCIE_API_REV1 */
1056
1057 typedef struct ioctl_req_hdr {
1058 uint32 pkt_id; /**< Packet ID */
1059 uint32 cmd; /**< IOCTL ID */
1060 uint16 retbuf_len;
1061 uint16 buflen;
1062 uint16 xt_id; /**< transaction ID */
1063 uint16 rsvd[1];
1064 } ioctl_req_hdr_t;
1065
1066 #endif /* PCIE_API_REV1 */
1067
1068 /** Complete msgbuf hdr for ioctl from host to dongle */
1069 typedef struct ioct_reqst_hdr {
1070 cmn_msg_hdr_t msg;
1071 #ifdef PCIE_API_REV1
1072 ioctl_hdr_t ioct_hdr;
1073 #else
1074 ioctl_req_hdr_t ioct_hdr;
1075 #endif // endif
1076 ret_buf_t ret_buf;
1077 } ioct_reqst_hdr_t;
1078
1079 typedef struct ioctptr_reqst_hdr {
1080 cmn_msg_hdr_t msg;
1081 #ifdef PCIE_API_REV1
1082 ioctlptr_hdr_t ioct_hdr;
1083 #else
1084 ioctl_req_hdr_t ioct_hdr;
1085 #endif // endif
1086 ret_buf_t ret_buf;
1087 ret_buf_t ioct_buf;
1088 } ioctptr_reqst_hdr_t;
1089
1090 /** ioctl response header */
1091 typedef struct ioct_resp_hdr {
1092 cmn_msg_hdr_t msg;
1093 #ifdef PCIE_API_REV1
1094 uint32 cmd_id;
1095 #else
1096 uint32 pkt_id;
1097 #endif // endif
1098 uint32 status;
1099 uint32 ret_len;
1100 uint32 inline_data;
1101 #ifdef PCIE_API_REV1
1102 #else
1103 uint16 xt_id; /**< transaction ID */
1104 uint16 rsvd[1];
1105 #endif // endif
1106 } ioct_resp_hdr_t;
1107
1108 /* ioct resp header used in dongle */
1109 /* ret buf hdr will be stripped off inside dongle itself */
1110 typedef struct msgbuf_ioctl_resp {
1111 ioct_resp_hdr_t ioct_hdr;
1112 ret_buf_t ret_buf; /**< ret buf pointers */
1113 } msgbuf_ioct_resp_t;
1114
1115 /** WL event hdr info */
1116 typedef struct wl_event_hdr {
1117 cmn_msg_hdr_t msg;
1118 uint16 event;
1119 uint8 flags;
1120 uint8 rsvd;
1121 uint16 retbuf_len;
1122 uint16 rsvd1;
1123 uint32 rxbufid;
1124 } wl_event_hdr_t;
1125
1126 #define TXDESCR_FLOWID_PCIELPBK_1 0xFF
1127 #define TXDESCR_FLOWID_PCIELPBK_2 0xFE
1128
1129 typedef struct txbatch_lenptr_tup {
1130 uint32 pktid;
1131 uint16 pktlen;
1132 uint16 rsvd;
1133 ret_buf_t ret_buf; /**< ret buf pointers */
1134 } txbatch_lenptr_tup_t;
1135
1136 typedef struct txbatch_cmn_msghdr {
1137 cmn_msg_hdr_t msg;
1138 uint8 priority;
1139 uint8 hdrlen;
1140 uint8 pktcnt;
1141 uint8 flowid;
1142 uint8 txhdr[ETHER_HDR_LEN];
1143 uint16 rsvd;
1144 } txbatch_cmn_msghdr_t;
1145
1146 typedef struct txbatch_msghdr {
1147 txbatch_cmn_msghdr_t txcmn;
1148 txbatch_lenptr_tup_t tx_tup[0]; /**< Based on packet count */
1149 } txbatch_msghdr_t;
1150
1151 /* TX desc posting header */
1152 typedef struct tx_lenptr_tup {
1153 uint16 pktlen;
1154 uint16 rsvd;
1155 ret_buf_t ret_buf; /**< ret buf pointers */
1156 } tx_lenptr_tup_t;
1157
1158 typedef struct txdescr_cmn_msghdr {
1159 cmn_msg_hdr_t msg;
1160 uint8 priority;
1161 uint8 hdrlen;
1162 uint8 descrcnt;
1163 uint8 flowid;
1164 uint32 pktid;
1165 } txdescr_cmn_msghdr_t;
1166
1167 typedef struct txdescr_msghdr {
1168 txdescr_cmn_msghdr_t txcmn;
1169 uint8 txhdr[ETHER_HDR_LEN];
1170 uint16 rsvd;
1171 tx_lenptr_tup_t tx_tup[0]; /**< Based on descriptor count */
1172 } txdescr_msghdr_t;
1173
1174 /** Tx status header info */
1175 typedef struct txstatus_hdr {
1176 cmn_msg_hdr_t msg;
1177 uint32 pktid;
1178 } txstatus_hdr_t;
1179
1180 /** RX bufid-len-ptr tuple */
1181 typedef struct rx_lenptr_tup {
1182 uint32 rxbufid;
1183 uint16 len;
1184 uint16 rsvd2;
1185 ret_buf_t ret_buf; /**< ret buf pointers */
1186 } rx_lenptr_tup_t;
1187
1188 /** Rx descr Post hdr info */
1189 typedef struct rxdesc_msghdr {
1190 cmn_msg_hdr_t msg;
1191 uint16 rsvd0;
1192 uint8 rsvd1;
1193 uint8 descnt;
1194 rx_lenptr_tup_t rx_tup[0];
1195 } rxdesc_msghdr_t;
1196
1197 /** RX complete tuples */
1198 typedef struct rxcmplt_tup {
1199 uint16 retbuf_len;
1200 uint16 data_offset;
1201 uint32 rxstatus0;
1202 uint32 rxstatus1;
1203 uint32 rxbufid;
1204 } rxcmplt_tup_t;
1205
1206 /** RX complete messge hdr */
1207 typedef struct rxcmplt_hdr {
1208 cmn_msg_hdr_t msg;
1209 uint16 rsvd0;
1210 uint16 rxcmpltcnt;
1211 rxcmplt_tup_t rx_tup[0];
1212 } rxcmplt_hdr_t;
1213
1214 typedef struct hostevent_hdr {
1215 cmn_msg_hdr_t msg;
1216 uint32 evnt_pyld;
1217 } hostevent_hdr_t;
1218
1219 typedef struct dma_xfer_params {
1220 uint32 src_physaddr_hi;
1221 uint32 src_physaddr_lo;
1222 uint32 dest_physaddr_hi;
1223 uint32 dest_physaddr_lo;
1224 uint32 len;
1225 uint32 srcdelay;
1226 uint32 destdelay;
1227 } dma_xfer_params_t;
1228
1229 enum {
1230 HOST_EVENT_CONS_CMD = 1
1231 };
1232
1233 /* defines for flags */
1234 #define MSGBUF_IOC_ACTION_MASK 0x1
1235
1236 #define MAX_SUSPEND_REQ 15
1237
1238 typedef struct tx_idle_flowring_suspend_request {
1239 cmn_msg_hdr_t msg;
1240 uint16 ring_id[MAX_SUSPEND_REQ]; /* ring Id's */
1241 uint16 num; /* number of flowid's to suspend */
1242 } tx_idle_flowring_suspend_request_t;
1243
1244 typedef struct tx_idle_flowring_suspend_response {
1245 cmn_msg_hdr_t msg;
1246 compl_msg_hdr_t cmplt;
1247 uint32 rsvd[2];
1248 dma_done_t marker;
1249 } tx_idle_flowring_suspend_response_t;
1250
1251 typedef struct tx_idle_flowring_resume_request {
1252 cmn_msg_hdr_t msg;
1253 uint16 flow_ring_id;
1254 uint16 reason;
1255 uint32 rsvd[7];
1256 } tx_idle_flowring_resume_request_t;
1257
1258 typedef struct tx_idle_flowring_resume_response {
1259 cmn_msg_hdr_t msg;
1260 compl_msg_hdr_t cmplt;
1261 uint32 rsvd[2];
1262 dma_done_t marker;
1263 } tx_idle_flowring_resume_response_t;
1264
1265 /* timesync related additions */
1266
1267 typedef struct _bcm_xtlv {
1268 uint16 id; /* TLV idenitifier */
1269 uint16 len; /* TLV length in bytes */
1270 } _bcm_xtlv_t;
1271
1272 #define BCMMSGBUF_FW_CLOCK_INFO_TAG 0
1273 #define BCMMSGBUF_HOST_CLOCK_INFO_TAG 1
1274 #define BCMMSGBUF_HOST_CLOCK_SELECT_TAG 2
1275 #define BCMMSGBUF_D2H_CLOCK_CORRECTION_TAG 3
1276 #define BCMMSGBUF_HOST_TIMESTAMPING_CONFIG_TAG 4
1277 #define BCMMSGBUF_MAX_TSYNC_TAG 5
1278
1279 /* Flags in fw clock info TLV */
1280 #define CAP_DEVICE_TS (1 << 0)
1281 #define CAP_CORRECTED_TS (1 << 1)
1282 #define TS_CLK_ACTIVE (1 << 2)
1283
1284 typedef struct ts_fw_clock_info {
1285 _bcm_xtlv_t xtlv; /* BCMMSGBUF_FW_CLOCK_INFO_TAG */
1286 ts_timestamp_srcid_t ts; /* tick count */
1287 uchar clk_src[4]; /* clock source acronym ILP/AVB/TSF */
1288 uint32 nominal_clock_freq;
1289 uint32 reset_cnt;
1290 uint8 flags;
1291 uint8 rsvd[3];
1292 } ts_fw_clock_info_t;
1293
1294 typedef struct ts_host_clock_info {
1295 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_CLOCK_INFO_TAG */
1296 tick_count_64_t ticks; /* 64 bit host tick counter */
1297 ts_timestamp_ns_64_t ns; /* 64 bit host time in nano seconds */
1298 } ts_host_clock_info_t;
1299
1300 typedef struct ts_host_clock_sel {
1301 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_CLOCK_SELECT_TAG */
1302 uint32 seqnum; /* number of times GPIO time sync toggled */
1303 uint8 min_clk_idx; /* clock idenitifer configured for packet tiem stamping */
1304 uint8 max_clk_idx; /* clock idenitifer configured for packet tiem stamping */
1305 uint16 rsvd[1];
1306 } ts_host_clock_sel_t;
1307
1308 typedef struct ts_d2h_clock_correction {
1309 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_CLOCK_INFO_TAG */
1310 uint8 clk_id; /* clock source in the device */
1311 uint8 rsvd[3];
1312 ts_correction_m_t m; /* y = 'm' x + b */
1313 ts_correction_b_t b; /* y = 'm' x + 'c' */
1314 } ts_d2h_clock_correction_t;
1315
1316 typedef struct ts_host_timestamping_config {
1317 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_TIMESTAMPING_CONFIG_TAG */
1318 /* time period to capture the device time stamp and toggle WLAN_TIME_SYNC_GPIO */
1319 uint16 period_ms;
1320 uint8 flags;
1321 uint8 post_delay;
1322 uint32 reset_cnt;
1323 } ts_host_timestamping_config_t;
1324
1325 /* Flags in host timestamping config TLV */
1326 #define FLAG_HOST_RESET (1 << 0)
1327 #define IS_HOST_RESET(x) ((x) & FLAG_HOST_RESET)
1328 #define CLEAR_HOST_RESET(x) ((x) & ~FLAG_HOST_RESET)
1329
1330 #define FLAG_CONFIG_NODROP (1 << 1)
1331 #define IS_CONFIG_NODROP(x) ((x) & FLAG_CONFIG_NODROP)
1332 #define CLEAR_CONFIG_NODROP(x) ((x) & ~FLAG_CONFIG_NODROP)
1333
1334 #endif /* _bcmmsgbuf_h_ */