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[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / net / wireless / bcmdhd4361 / dhd_pcie_linux.c
1 /*
2 * Linux DHD Bus Module for PCIE
3 *
4 * Copyright (C) 1999-2019, Broadcom.
5 *
6 * Unless you and Broadcom execute a separate written software license
7 * agreement governing use of this software, this software is licensed to you
8 * under the terms of the GNU General Public License version 2 (the "GPL"),
9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
10 * following added to such license:
11 *
12 * As a special exception, the copyright holders of this software give you
13 * permission to link this software with independent modules, and to copy and
14 * distribute the resulting executable under terms of your choice, provided that
15 * you also meet, for each linked independent module, the terms and conditions of
16 * the license of that module. An independent module is a module which is not
17 * derived from this software. The special exception does not apply to any
18 * modifications of the software.
19 *
20 * Notwithstanding the above, under no circumstances may you combine this
21 * software in any way with any other Broadcom software provided under a license
22 * other than the GPL, without Broadcom's express prior written consent.
23 *
24 *
25 * <<Broadcom-WL-IPTag/Open:>>
26 *
27 * $Id: dhd_pcie_linux.c 797197 2018-12-29 03:31:21Z $
28 */
29
30 /* include files */
31 #include <typedefs.h>
32 #include <bcmutils.h>
33 #include <bcmdevs.h>
34 #include <siutils.h>
35 #include <hndsoc.h>
36 #include <hndpmu.h>
37 #include <sbchipc.h>
38 #if defined(DHD_DEBUG)
39 #include <hnd_armtrap.h>
40 #include <hnd_cons.h>
41 #endif /* defined(DHD_DEBUG) */
42 #include <dngl_stats.h>
43 #include <pcie_core.h>
44 #include <dhd.h>
45 #include <dhd_bus.h>
46 #include <dhd_proto.h>
47 #include <dhd_dbg.h>
48 #include <dhdioctl.h>
49 #include <bcmmsgbuf.h>
50 #include <pcicfg.h>
51 #include <dhd_pcie.h>
52 #include <dhd_linux.h>
53 #ifdef CONFIG_ARCH_MSM
54 #if defined(CONFIG_PCI_MSM) || defined(CONFIG_ARCH_MSM8996)
55 #include <linux/msm_pcie.h>
56 #else
57 #include <mach/msm_pcie.h>
58 #endif /* CONFIG_PCI_MSM */
59 #endif /* CONFIG_ARCH_MSM */
60
61 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
62 #include <linux/pm_runtime.h>
63 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
64
65 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
66 #ifndef AUTO_SUSPEND_TIMEOUT
67 #define AUTO_SUSPEND_TIMEOUT 1000
68 #endif /* AUTO_SUSPEND_TIMEOUT */
69 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
70
71 #include <linux/irq.h>
72 #ifdef USE_SMMU_ARCH_MSM
73 #include <asm/dma-iommu.h>
74 #include <linux/iommu.h>
75 #include <linux/of.h>
76 #include <linux/platform_device.h>
77 #endif /* USE_SMMU_ARCH_MSM */
78
79 #define PCI_CFG_RETRY 10
80 #define OS_HANDLE_MAGIC 0x1234abcd /* Magic # to recognize osh */
81 #define BCM_MEM_FILENAME_LEN 24 /* Mem. filename length */
82
83 #define OSL_PKTTAG_CLEAR(p) \
84 do { \
85 struct sk_buff *s = (struct sk_buff *)(p); \
86 ASSERT(OSL_PKTTAG_SZ == 32); \
87 *(uint32 *)(&s->cb[0]) = 0; *(uint32 *)(&s->cb[4]) = 0; \
88 *(uint32 *)(&s->cb[8]) = 0; *(uint32 *)(&s->cb[12]) = 0; \
89 *(uint32 *)(&s->cb[16]) = 0; *(uint32 *)(&s->cb[20]) = 0; \
90 *(uint32 *)(&s->cb[24]) = 0; *(uint32 *)(&s->cb[28]) = 0; \
91 } while (0)
92
93 /* user defined data structures */
94
95 typedef struct dhd_pc_res {
96 uint32 bar0_size;
97 void* bar0_addr;
98 uint32 bar1_size;
99 void* bar1_addr;
100 } pci_config_res, *pPci_config_res;
101
102 typedef bool (*dhdpcie_cb_fn_t)(void *);
103
104 typedef struct dhdpcie_info
105 {
106 dhd_bus_t *bus;
107 osl_t *osh;
108 struct pci_dev *dev; /* pci device handle */
109 volatile char *regs; /* pci device memory va */
110 volatile char *tcm; /* pci device memory va */
111 uint32 tcm_size; /* pci device memory size */
112 struct pcos_info *pcos_info;
113 uint16 last_intrstatus; /* to cache intrstatus */
114 int irq;
115 char pciname[32];
116 struct pci_saved_state* default_state;
117 struct pci_saved_state* state;
118 #ifdef BCMPCIE_OOB_HOST_WAKE
119 void *os_cxt; /* Pointer to per-OS private data */
120 #endif /* BCMPCIE_OOB_HOST_WAKE */
121 #ifdef DHD_WAKE_STATUS
122 spinlock_t pcie_lock;
123 unsigned int total_wake_count;
124 int pkt_wake;
125 int wake_irq;
126 #endif /* DHD_WAKE_STATUS */
127 #ifdef USE_SMMU_ARCH_MSM
128 void *smmu_cxt;
129 #endif /* USE_SMMU_ARCH_MSM */
130 } dhdpcie_info_t;
131
132 struct pcos_info {
133 dhdpcie_info_t *pc;
134 spinlock_t lock;
135 wait_queue_head_t intr_wait_queue;
136 struct timer_list tuning_timer;
137 int tuning_timer_exp;
138 atomic_t timer_enab;
139 struct tasklet_struct tuning_tasklet;
140 };
141
142 #ifdef BCMPCIE_OOB_HOST_WAKE
143 typedef struct dhdpcie_os_info {
144 int oob_irq_num; /* valid when hardware or software oob in use */
145 unsigned long oob_irq_flags; /* valid when hardware or software oob in use */
146 bool oob_irq_registered;
147 bool oob_irq_enabled;
148 bool oob_irq_wake_enabled;
149 spinlock_t oob_irq_spinlock;
150 void *dev; /* handle to the underlying device */
151 } dhdpcie_os_info_t;
152 static irqreturn_t wlan_oob_irq(int irq, void *data);
153 #endif /* BCMPCIE_OOB_HOST_WAKE */
154
155 #ifdef USE_SMMU_ARCH_MSM
156 typedef struct dhdpcie_smmu_info {
157 struct dma_iommu_mapping *smmu_mapping;
158 dma_addr_t smmu_iova_start;
159 size_t smmu_iova_len;
160 } dhdpcie_smmu_info_t;
161 #endif /* USE_SMMU_ARCH_MSM */
162
163 /* function declarations */
164 static int __devinit
165 dhdpcie_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
166 static void __devexit
167 dhdpcie_pci_remove(struct pci_dev *pdev);
168 static int dhdpcie_init(struct pci_dev *pdev);
169 static irqreturn_t dhdpcie_isr(int irq, void *arg);
170 /* OS Routine functions for PCI suspend/resume */
171
172 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
173 static int dhdpcie_set_suspend_resume(struct pci_dev *dev, bool state, bool byint);
174 #else
175 static int dhdpcie_set_suspend_resume(dhd_bus_t *bus, bool state);
176 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
177 static int dhdpcie_resume_host_dev(dhd_bus_t *bus);
178 static int dhdpcie_suspend_host_dev(dhd_bus_t *bus);
179 static int dhdpcie_resume_dev(struct pci_dev *dev);
180 static int dhdpcie_suspend_dev(struct pci_dev *dev);
181 #ifdef DHD_PCIE_RUNTIMEPM
182 static int dhdpcie_pm_suspend(struct device *dev);
183 static int dhdpcie_pm_prepare(struct device *dev);
184 static int dhdpcie_pm_resume(struct device *dev);
185 static void dhdpcie_pm_complete(struct device *dev);
186 #else
187 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
188 static int dhdpcie_pm_system_suspend_noirq(struct device * dev);
189 static int dhdpcie_pm_system_resume_noirq(struct device * dev);
190 #else
191 static int dhdpcie_pci_suspend(struct pci_dev *dev, pm_message_t state);
192 static int dhdpcie_pci_resume(struct pci_dev *dev);
193 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
194 #endif /* DHD_PCIE_RUNTIMEPM */
195
196 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
197 static int dhdpcie_pm_runtime_suspend(struct device * dev);
198 static int dhdpcie_pm_runtime_resume(struct device * dev);
199 static int dhdpcie_pm_system_suspend_noirq(struct device * dev);
200 static int dhdpcie_pm_system_resume_noirq(struct device * dev);
201 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
202
203 static struct pci_device_id dhdpcie_pci_devid[] __devinitdata = {
204 { vendor: 0x14e4,
205 device: PCI_ANY_ID,
206 subvendor: PCI_ANY_ID,
207 subdevice: PCI_ANY_ID,
208 class: PCI_CLASS_NETWORK_OTHER << 8,
209 class_mask: 0xffff00,
210 driver_data: 0,
211 },
212 { 0, 0, 0, 0, 0, 0, 0}
213 };
214 MODULE_DEVICE_TABLE(pci, dhdpcie_pci_devid);
215
216 /* Power Management Hooks */
217 #ifdef DHD_PCIE_RUNTIMEPM
218 static const struct dev_pm_ops dhd_pcie_pm_ops = {
219 .prepare = dhdpcie_pm_prepare,
220 .suspend = dhdpcie_pm_suspend,
221 .resume = dhdpcie_pm_resume,
222 .complete = dhdpcie_pm_complete,
223 };
224 #endif /* DHD_PCIE_RUNTIMEPM */
225 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
226 static const struct dev_pm_ops dhdpcie_pm_ops = {
227 SET_RUNTIME_PM_OPS(dhdpcie_pm_runtime_suspend, dhdpcie_pm_runtime_resume, NULL)
228 .suspend_noirq = dhdpcie_pm_system_suspend_noirq,
229 .resume_noirq = dhdpcie_pm_system_resume_noirq
230 };
231 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
232
233 static struct pci_driver dhdpcie_driver = {
234 node: {&dhdpcie_driver.node, &dhdpcie_driver.node},
235 name: "pcieh",
236 id_table: dhdpcie_pci_devid,
237 probe: dhdpcie_pci_probe,
238 remove: dhdpcie_pci_remove,
239 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
240 save_state: NULL,
241 #endif // endif
242 #if defined(DHD_PCIE_RUNTIMEPM) || defined(DHD_PCIE_NATIVE_RUNTIMEPM)
243 .driver.pm = &dhd_pcie_pm_ops,
244 #else
245 suspend: dhdpcie_pci_suspend,
246 resume: dhdpcie_pci_resume,
247 #endif /* DHD_PCIE_RUNTIMEPM || DHD_PCIE_NATIVE_RUNTIMEPM */
248 };
249
250 int dhdpcie_init_succeeded = FALSE;
251
252 #ifdef USE_SMMU_ARCH_MSM
253 static int dhdpcie_smmu_init(struct pci_dev *pdev, void *smmu_cxt)
254 {
255 struct dma_iommu_mapping *mapping;
256 struct device_node *root_node = NULL;
257 dhdpcie_smmu_info_t *smmu_info = (dhdpcie_smmu_info_t *)smmu_cxt;
258 int smmu_iova_address[2];
259 char *wlan_node = "android,bcmdhd_wlan";
260 char *wlan_smmu_node = "wlan-smmu-iova-address";
261 int atomic_ctx = 1;
262 int s1_bypass = 1;
263 int ret = 0;
264
265 DHD_ERROR(("%s: SMMU initialize\n", __FUNCTION__));
266
267 root_node = of_find_compatible_node(NULL, NULL, wlan_node);
268 if (!root_node) {
269 WARN(1, "failed to get device node of BRCM WLAN\n");
270 return -ENODEV;
271 }
272
273 if (of_property_read_u32_array(root_node, wlan_smmu_node,
274 smmu_iova_address, 2) == 0) {
275 DHD_ERROR(("%s : get SMMU start address 0x%x, size 0x%x\n",
276 __FUNCTION__, smmu_iova_address[0], smmu_iova_address[1]));
277 smmu_info->smmu_iova_start = smmu_iova_address[0];
278 smmu_info->smmu_iova_len = smmu_iova_address[1];
279 } else {
280 printf("%s : can't get smmu iova address property\n",
281 __FUNCTION__);
282 return -ENODEV;
283 }
284
285 if (smmu_info->smmu_iova_len <= 0) {
286 DHD_ERROR(("%s: Invalid smmu iova len %d\n",
287 __FUNCTION__, (int)smmu_info->smmu_iova_len));
288 return -EINVAL;
289 }
290
291 DHD_ERROR(("%s : SMMU init start\n", __FUNCTION__));
292
293 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) ||
294 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
295 DHD_ERROR(("%s: DMA set 64bit mask failed.\n", __FUNCTION__));
296 return -EINVAL;
297 }
298
299 mapping = arm_iommu_create_mapping(&platform_bus_type,
300 smmu_info->smmu_iova_start, smmu_info->smmu_iova_len);
301 if (IS_ERR(mapping)) {
302 DHD_ERROR(("%s: create mapping failed, err = %d\n",
303 __FUNCTION__, ret));
304 ret = PTR_ERR(mapping);
305 goto map_fail;
306 }
307
308 ret = iommu_domain_set_attr(mapping->domain,
309 DOMAIN_ATTR_ATOMIC, &atomic_ctx);
310 if (ret) {
311 DHD_ERROR(("%s: set atomic_ctx attribute failed, err = %d\n",
312 __FUNCTION__, ret));
313 goto set_attr_fail;
314 }
315
316 ret = iommu_domain_set_attr(mapping->domain,
317 DOMAIN_ATTR_S1_BYPASS, &s1_bypass);
318 if (ret < 0) {
319 DHD_ERROR(("%s: set s1_bypass attribute failed, err = %d\n",
320 __FUNCTION__, ret));
321 goto set_attr_fail;
322 }
323
324 ret = arm_iommu_attach_device(&pdev->dev, mapping);
325 if (ret) {
326 DHD_ERROR(("%s: attach device failed, err = %d\n",
327 __FUNCTION__, ret));
328 goto attach_fail;
329 }
330
331 smmu_info->smmu_mapping = mapping;
332
333 return ret;
334
335 attach_fail:
336 set_attr_fail:
337 arm_iommu_release_mapping(mapping);
338 map_fail:
339 return ret;
340 }
341
342 static void dhdpcie_smmu_remove(struct pci_dev *pdev, void *smmu_cxt)
343 {
344 dhdpcie_smmu_info_t *smmu_info;
345
346 if (!smmu_cxt) {
347 return;
348 }
349
350 smmu_info = (dhdpcie_smmu_info_t *)smmu_cxt;
351 if (smmu_info->smmu_mapping) {
352 arm_iommu_detach_device(&pdev->dev);
353 arm_iommu_release_mapping(smmu_info->smmu_mapping);
354 smmu_info->smmu_mapping = NULL;
355 }
356 }
357 #endif /* USE_SMMU_ARCH_MSM */
358
359 void
360 dhd_bus_aer_config(dhd_bus_t *bus)
361 {
362 uint32 val;
363
364 DHD_ERROR(("%s: Configure AER registers for EP\n", __FUNCTION__));
365 val = dhdpcie_ep_access_cap(bus, PCIE_ADVERRREP_CAPID,
366 PCIE_ADV_CORR_ERR_MASK_OFFSET, TRUE, FALSE, 0);
367 if (val != (uint32)-1) {
368 val &= ~CORR_ERR_AE;
369 dhdpcie_ep_access_cap(bus, PCIE_ADVERRREP_CAPID,
370 PCIE_ADV_CORR_ERR_MASK_OFFSET, TRUE, TRUE, val);
371 } else {
372 DHD_ERROR(("%s: Invalid EP's PCIE_ADV_CORR_ERR_MASK: 0x%x\n",
373 __FUNCTION__, val));
374 }
375
376 DHD_ERROR(("%s: Configure AER registers for RC\n", __FUNCTION__));
377 val = dhdpcie_rc_access_cap(bus, PCIE_ADVERRREP_CAPID,
378 PCIE_ADV_CORR_ERR_MASK_OFFSET, TRUE, FALSE, 0);
379 if (val != (uint32)-1) {
380 val &= ~CORR_ERR_AE;
381 dhdpcie_rc_access_cap(bus, PCIE_ADVERRREP_CAPID,
382 PCIE_ADV_CORR_ERR_MASK_OFFSET, TRUE, TRUE, val);
383 } else {
384 DHD_ERROR(("%s: Invalid RC's PCIE_ADV_CORR_ERR_MASK: 0x%x\n",
385 __FUNCTION__, val));
386 }
387 }
388
389 #ifdef DHD_PCIE_RUNTIMEPM
390 static int dhdpcie_pm_suspend(struct device *dev)
391 {
392 int ret = 0;
393 struct pci_dev *pdev = to_pci_dev(dev);
394 dhdpcie_info_t *pch = pci_get_drvdata(pdev);
395 dhd_bus_t *bus = NULL;
396 unsigned long flags;
397
398 if (pch) {
399 bus = pch->bus;
400 }
401 if (!bus) {
402 return ret;
403 }
404
405 DHD_GENERAL_LOCK(bus->dhd, flags);
406 if (!DHD_BUS_BUSY_CHECK_IDLE(bus->dhd)) {
407 DHD_ERROR(("%s: Bus not IDLE!! dhd_bus_busy_state = 0x%x\n",
408 __FUNCTION__, bus->dhd->dhd_bus_busy_state));
409 DHD_GENERAL_UNLOCK(bus->dhd, flags);
410 return -EBUSY;
411 }
412 DHD_BUS_BUSY_SET_SUSPEND_IN_PROGRESS(bus->dhd);
413 DHD_GENERAL_UNLOCK(bus->dhd, flags);
414
415 if (!bus->dhd->dongle_reset)
416 ret = dhdpcie_set_suspend_resume(bus, TRUE);
417
418 DHD_GENERAL_LOCK(bus->dhd, flags);
419 DHD_BUS_BUSY_CLEAR_SUSPEND_IN_PROGRESS(bus->dhd);
420 dhd_os_busbusy_wake(bus->dhd);
421 DHD_GENERAL_UNLOCK(bus->dhd, flags);
422
423 return ret;
424
425 }
426
427 static int dhdpcie_pm_prepare(struct device *dev)
428 {
429 struct pci_dev *pdev = to_pci_dev(dev);
430 dhdpcie_info_t *pch = pci_get_drvdata(pdev);
431 dhd_bus_t *bus = NULL;
432
433 if (!pch || !pch->bus) {
434 return 0;
435 }
436
437 bus = pch->bus;
438 DHD_DISABLE_RUNTIME_PM(bus->dhd);
439 bus->chk_pm = TRUE;
440
441 return 0;
442 }
443
444 static int dhdpcie_pm_resume(struct device *dev)
445 {
446 int ret = 0;
447 struct pci_dev *pdev = to_pci_dev(dev);
448 dhdpcie_info_t *pch = pci_get_drvdata(pdev);
449 dhd_bus_t *bus = NULL;
450 unsigned long flags;
451
452 if (pch) {
453 bus = pch->bus;
454 }
455 if (!bus) {
456 return ret;
457 }
458
459 DHD_GENERAL_LOCK(bus->dhd, flags);
460 DHD_BUS_BUSY_SET_RESUME_IN_PROGRESS(bus->dhd);
461 DHD_GENERAL_UNLOCK(bus->dhd, flags);
462
463 if (!bus->dhd->dongle_reset)
464 ret = dhdpcie_set_suspend_resume(bus, FALSE);
465
466 DHD_GENERAL_LOCK(bus->dhd, flags);
467 DHD_BUS_BUSY_CLEAR_RESUME_IN_PROGRESS(bus->dhd);
468 dhd_os_busbusy_wake(bus->dhd);
469 DHD_GENERAL_UNLOCK(bus->dhd, flags);
470
471 return ret;
472 }
473
474 static void dhdpcie_pm_complete(struct device *dev)
475 {
476 struct pci_dev *pdev = to_pci_dev(dev);
477 dhdpcie_info_t *pch = pci_get_drvdata(pdev);
478 dhd_bus_t *bus = NULL;
479
480 if (!pch || !pch->bus) {
481 return;
482 }
483
484 bus = pch->bus;
485 DHD_ENABLE_RUNTIME_PM(bus->dhd);
486 bus->chk_pm = FALSE;
487
488 return;
489 }
490 #else
491 static int dhdpcie_pci_suspend(struct pci_dev * pdev, pm_message_t state)
492 {
493 int ret = 0;
494 dhdpcie_info_t *pch = pci_get_drvdata(pdev);
495 dhd_bus_t *bus = NULL;
496 unsigned long flags;
497
498 if (pch) {
499 bus = pch->bus;
500 }
501 if (!bus) {
502 return ret;
503 }
504
505 BCM_REFERENCE(state);
506
507 DHD_GENERAL_LOCK(bus->dhd, flags);
508 if (!DHD_BUS_BUSY_CHECK_IDLE(bus->dhd)) {
509 DHD_ERROR(("%s: Bus not IDLE!! dhd_bus_busy_state = 0x%x\n",
510 __FUNCTION__, bus->dhd->dhd_bus_busy_state));
511 DHD_GENERAL_UNLOCK(bus->dhd, flags);
512 return -EBUSY;
513 }
514 DHD_BUS_BUSY_SET_SUSPEND_IN_PROGRESS(bus->dhd);
515 DHD_GENERAL_UNLOCK(bus->dhd, flags);
516
517 if (!bus->dhd->dongle_reset)
518 ret = dhdpcie_set_suspend_resume(bus, TRUE);
519
520 DHD_GENERAL_LOCK(bus->dhd, flags);
521 DHD_BUS_BUSY_CLEAR_SUSPEND_IN_PROGRESS(bus->dhd);
522 dhd_os_busbusy_wake(bus->dhd);
523 DHD_GENERAL_UNLOCK(bus->dhd, flags);
524
525 return ret;
526 }
527
528 static int dhdpcie_pci_resume(struct pci_dev *pdev)
529 {
530 int ret = 0;
531 dhdpcie_info_t *pch = pci_get_drvdata(pdev);
532 dhd_bus_t *bus = NULL;
533 unsigned long flags;
534
535 if (pch) {
536 bus = pch->bus;
537 }
538 if (!bus) {
539 return ret;
540 }
541
542 DHD_GENERAL_LOCK(bus->dhd, flags);
543 DHD_BUS_BUSY_SET_RESUME_IN_PROGRESS(bus->dhd);
544 DHD_GENERAL_UNLOCK(bus->dhd, flags);
545
546 if (!bus->dhd->dongle_reset)
547 ret = dhdpcie_set_suspend_resume(bus, FALSE);
548
549 DHD_GENERAL_LOCK(bus->dhd, flags);
550 DHD_BUS_BUSY_CLEAR_RESUME_IN_PROGRESS(bus->dhd);
551 dhd_os_busbusy_wake(bus->dhd);
552 DHD_GENERAL_UNLOCK(bus->dhd, flags);
553
554 return ret;
555 }
556
557 #endif /* DHD_PCIE_RUNTIMEPM */
558 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
559 static int dhdpcie_set_suspend_resume(dhd_bus_t *bus, bool state, bool byint)
560 #else
561 static int dhdpcie_set_suspend_resume(dhd_bus_t *bus, bool state)
562 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
563 {
564 int ret = 0;
565
566 ASSERT(bus && !bus->dhd->dongle_reset);
567
568 #ifdef DHD_PCIE_RUNTIMEPM
569 /* if wakelock is held during suspend, return failed */
570 if (state == TRUE && dhd_os_check_wakelock_all(bus->dhd)) {
571 return -EBUSY;
572 }
573 mutex_lock(&bus->pm_lock);
574 #endif /* DHD_PCIE_RUNTIMEPM */
575
576 /* When firmware is not loaded do the PCI bus */
577 /* suspend/resume only */
578 if (bus->dhd->busstate == DHD_BUS_DOWN) {
579 ret = dhdpcie_pci_suspend_resume(bus, state);
580 #ifdef DHD_PCIE_RUNTIMEPM
581 mutex_unlock(&bus->pm_lock);
582 #endif /* DHD_PCIE_RUNTIMEPM */
583 return ret;
584 }
585 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
586 ret = dhdpcie_bus_suspend(bus, state, byint);
587 #else
588 ret = dhdpcie_bus_suspend(bus, state);
589 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
590
591 #ifdef DHD_PCIE_RUNTIMEPM
592 mutex_unlock(&bus->pm_lock);
593 #endif /* DHD_PCIE_RUNTIMEPM */
594
595 return ret;
596 }
597
598 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
599 static int dhdpcie_pm_runtime_suspend(struct device * dev)
600 {
601 struct pci_dev *pdev = to_pci_dev(dev);
602 dhdpcie_info_t *pch = pci_get_drvdata(pdev);
603 dhd_bus_t *bus = NULL;
604 int ret = 0;
605
606 if (!pch)
607 return -EBUSY;
608
609 bus = pch->bus;
610
611 DHD_RPM(("%s Enter\n", __FUNCTION__));
612
613 if (atomic_read(&bus->dhd->block_bus))
614 return -EHOSTDOWN;
615
616 dhd_netif_stop_queue(bus);
617 atomic_set(&bus->dhd->block_bus, TRUE);
618
619 if (dhdpcie_set_suspend_resume(pdev, TRUE, TRUE)) {
620 pm_runtime_mark_last_busy(dev);
621 ret = -EAGAIN;
622 }
623
624 atomic_set(&bus->dhd->block_bus, FALSE);
625 dhd_bus_start_queue(bus);
626
627 return ret;
628 }
629
630 static int dhdpcie_pm_runtime_resume(struct device * dev)
631 {
632 struct pci_dev *pdev = to_pci_dev(dev);
633 dhdpcie_info_t *pch = pci_get_drvdata(pdev);
634 dhd_bus_t *bus = pch->bus;
635
636 DHD_RPM(("%s Enter\n", __FUNCTION__));
637
638 if (atomic_read(&bus->dhd->block_bus))
639 return -EHOSTDOWN;
640
641 if (dhdpcie_set_suspend_resume(pdev, FALSE, TRUE))
642 return -EAGAIN;
643
644 return 0;
645 }
646
647 static int dhdpcie_pm_system_suspend_noirq(struct device * dev)
648 {
649 struct pci_dev *pdev = to_pci_dev(dev);
650 dhdpcie_info_t *pch = pci_get_drvdata(pdev);
651 dhd_bus_t *bus = NULL;
652 int ret;
653
654 DHD_RPM(("%s Enter\n", __FUNCTION__));
655
656 if (!pch)
657 return -EBUSY;
658
659 bus = pch->bus;
660
661 if (atomic_read(&bus->dhd->block_bus))
662 return -EHOSTDOWN;
663
664 dhd_netif_stop_queue(bus);
665 atomic_set(&bus->dhd->block_bus, TRUE);
666
667 ret = dhdpcie_set_suspend_resume(pdev, TRUE, FALSE);
668
669 if (ret) {
670 dhd_bus_start_queue(bus);
671 atomic_set(&bus->dhd->block_bus, FALSE);
672 }
673
674 return ret;
675 }
676
677 static int dhdpcie_pm_system_resume_noirq(struct device * dev)
678 {
679 struct pci_dev *pdev = to_pci_dev(dev);
680 dhdpcie_info_t *pch = pci_get_drvdata(pdev);
681 dhd_bus_t *bus = NULL;
682 int ret;
683
684 if (!pch)
685 return -EBUSY;
686
687 bus = pch->bus;
688
689 DHD_RPM(("%s Enter\n", __FUNCTION__));
690
691 ret = dhdpcie_set_suspend_resume(pdev, FALSE, FALSE);
692
693 atomic_set(&bus->dhd->block_bus, FALSE);
694 dhd_bus_start_queue(bus);
695 pm_runtime_mark_last_busy(dhd_bus_to_dev(bus));
696
697 return ret;
698 }
699 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
700
701 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
702 extern void dhd_dpc_tasklet_kill(dhd_pub_t *dhdp);
703 #endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
704
705 static int dhdpcie_suspend_dev(struct pci_dev *dev)
706 {
707 int ret;
708 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
709 dhdpcie_info_t *pch = pci_get_drvdata(dev);
710 dhd_bus_t *bus = pch->bus;
711
712 if (bus->is_linkdown) {
713 DHD_ERROR(("%s: PCIe link is down\n", __FUNCTION__));
714 return BCME_ERROR;
715 }
716 #endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
717 DHD_TRACE_HW4(("%s: Enter\n", __FUNCTION__));
718 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
719 dhd_dpc_tasklet_kill(bus->dhd);
720 #endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
721 pci_save_state(dev);
722 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
723 pch->state = pci_store_saved_state(dev);
724 #endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
725 pci_enable_wake(dev, PCI_D0, TRUE);
726 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
727 if (pci_is_enabled(dev))
728 #endif // endif
729 pci_disable_device(dev);
730
731 ret = pci_set_power_state(dev, PCI_D3hot);
732 if (ret) {
733 DHD_ERROR(("%s: pci_set_power_state error %d\n",
734 __FUNCTION__, ret));
735 }
736 dev->state_saved = FALSE;
737 return ret;
738 }
739
740 #ifdef DHD_WAKE_STATUS
741 int bcmpcie_get_total_wake(struct dhd_bus *bus)
742 {
743 dhdpcie_info_t *pch = pci_get_drvdata(bus->dev);
744
745 return pch->total_wake_count;
746 }
747
748 int bcmpcie_set_get_wake(struct dhd_bus *bus, int flag)
749 {
750 dhdpcie_info_t *pch = pci_get_drvdata(bus->dev);
751 unsigned long flags;
752 int ret;
753
754 spin_lock_irqsave(&pch->pcie_lock, flags);
755
756 ret = pch->pkt_wake;
757 pch->total_wake_count += flag;
758 pch->pkt_wake = flag;
759
760 spin_unlock_irqrestore(&pch->pcie_lock, flags);
761 return ret;
762 }
763 #endif /* DHD_WAKE_STATUS */
764
765 static int dhdpcie_resume_dev(struct pci_dev *dev)
766 {
767 int err = 0;
768 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
769 dhdpcie_info_t *pch = pci_get_drvdata(dev);
770 pci_load_and_free_saved_state(dev, &pch->state);
771 #endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
772 DHD_TRACE_HW4(("%s: Enter\n", __FUNCTION__));
773 dev->state_saved = TRUE;
774 pci_restore_state(dev);
775 err = pci_enable_device(dev);
776 if (err) {
777 printf("%s:pci_enable_device error %d \n", __FUNCTION__, err);
778 goto out;
779 }
780 pci_set_master(dev);
781 err = pci_set_power_state(dev, PCI_D0);
782 if (err) {
783 printf("%s:pci_set_power_state error %d \n", __FUNCTION__, err);
784 goto out;
785 }
786
787 out:
788 return err;
789 }
790
791 static int dhdpcie_resume_host_dev(dhd_bus_t *bus)
792 {
793 int bcmerror = 0;
794 #ifdef USE_EXYNOS_PCIE_RC_PMPATCH
795 bcmerror = exynos_pcie_pm_resume(SAMSUNG_PCIE_CH_NUM);
796 #endif /* USE_EXYNOS_PCIE_RC_PMPATCH */
797 #ifdef CONFIG_ARCH_MSM
798 bcmerror = dhdpcie_start_host_pcieclock(bus);
799 #endif /* CONFIG_ARCH_MSM */
800 #ifdef CONFIG_ARCH_TEGRA
801 bcmerror = tegra_pcie_pm_resume();
802 #endif /* CONFIG_ARCH_TEGRA */
803 if (bcmerror < 0) {
804 DHD_ERROR(("%s: PCIe RC resume failed!!! (%d)\n",
805 __FUNCTION__, bcmerror));
806 bus->is_linkdown = 1;
807 #ifdef SUPPORT_LINKDOWN_RECOVERY
808 #ifdef CONFIG_ARCH_MSM
809 bus->no_cfg_restore = 1;
810 #endif /* CONFIG_ARCH_MSM */
811 #endif /* SUPPORT_LINKDOWN_RECOVERY */
812 }
813
814 return bcmerror;
815 }
816
817 static int dhdpcie_suspend_host_dev(dhd_bus_t *bus)
818 {
819 int bcmerror = 0;
820 #ifdef USE_EXYNOS_PCIE_RC_PMPATCH
821 if (bus->rc_dev) {
822 pci_save_state(bus->rc_dev);
823 } else {
824 DHD_ERROR(("%s: RC %x:%x handle is NULL\n",
825 __FUNCTION__, PCIE_RC_VENDOR_ID, PCIE_RC_DEVICE_ID));
826 }
827 exynos_pcie_pm_suspend(SAMSUNG_PCIE_CH_NUM);
828 #endif /* USE_EXYNOS_PCIE_RC_PMPATCH */
829 #ifdef CONFIG_ARCH_MSM
830 bcmerror = dhdpcie_stop_host_pcieclock(bus);
831 #endif /* CONFIG_ARCH_MSM */
832 #ifdef CONFIG_ARCH_TEGRA
833 bcmerror = tegra_pcie_pm_suspend();
834 #endif /* CONFIG_ARCH_TEGRA */
835 return bcmerror;
836 }
837
838 uint32
839 dhdpcie_rc_config_read(dhd_bus_t *bus, uint offset)
840 {
841 uint val = -1; /* Initialise to 0xfffffff */
842 if (bus->rc_dev) {
843 pci_read_config_dword(bus->rc_dev, offset, &val);
844 OSL_DELAY(100);
845 } else {
846 DHD_ERROR(("%s: RC %x:%x handle is NULL\n",
847 __FUNCTION__, PCIE_RC_VENDOR_ID, PCIE_RC_DEVICE_ID));
848 }
849 DHD_ERROR(("%s: RC %x:%x offset 0x%x val 0x%x\n",
850 __FUNCTION__, PCIE_RC_VENDOR_ID, PCIE_RC_DEVICE_ID, offset, val));
851 return (val);
852 }
853
854 /*
855 * Reads/ Writes the value of capability register
856 * from the given CAP_ID section of PCI Root Port
857 *
858 * Arguements
859 * @bus current dhd_bus_t pointer
860 * @cap Capability or Extended Capability ID to get
861 * @offset offset of Register to Read
862 * @is_ext TRUE if @cap is given for Extended Capability
863 * @is_write is set to TRUE to indicate write
864 * @val value to write
865 *
866 * Return Value
867 * Returns 0xffffffff on error
868 * on write success returns BCME_OK (0)
869 * on Read Success returns the value of register requested
870 * Note: caller shoud ensure valid capability ID and Ext. Capability ID.
871 */
872
873 uint32
874 dhdpcie_access_cap(struct pci_dev *pdev, int cap, uint offset, bool is_ext, bool is_write,
875 uint32 writeval)
876 {
877 int cap_ptr = 0;
878 uint32 ret = -1;
879 uint32 readval;
880
881 if (!(pdev)) {
882 DHD_ERROR(("%s: pdev is NULL\n", __FUNCTION__));
883 return ret;
884 }
885
886 /* Find Capability offset */
887 if (is_ext) {
888 /* removing max EXT_CAP_ID check as
889 * linux kernel definition's max value is not upadted yet as per spec
890 */
891 cap_ptr = pci_find_ext_capability(pdev, cap);
892
893 } else {
894 /* removing max PCI_CAP_ID_MAX check as
895 * pervious kernel versions dont have this definition
896 */
897 cap_ptr = pci_find_capability(pdev, cap);
898 }
899
900 /* Return if capability with given ID not found */
901 if (cap_ptr == 0) {
902 DHD_ERROR(("%s: PCI Cap(0x%02x) not supported.\n",
903 __FUNCTION__, cap));
904 return BCME_ERROR;
905 }
906
907 if (is_write) {
908 pci_write_config_dword(pdev, (cap_ptr + offset), writeval);
909 ret = BCME_OK;
910
911 } else {
912
913 pci_read_config_dword(pdev, (cap_ptr + offset), &readval);
914 ret = readval;
915 }
916
917 return ret;
918 }
919
920 uint32
921 dhdpcie_rc_access_cap(dhd_bus_t *bus, int cap, uint offset, bool is_ext, bool is_write,
922 uint32 writeval)
923 {
924 if (!(bus->rc_dev)) {
925 DHD_ERROR(("%s: RC %x:%x handle is NULL\n",
926 __FUNCTION__, PCIE_RC_VENDOR_ID, PCIE_RC_DEVICE_ID));
927 return BCME_ERROR;
928 }
929
930 return dhdpcie_access_cap(bus->rc_dev, cap, offset, is_ext, is_write, writeval);
931 }
932
933 uint32
934 dhdpcie_ep_access_cap(dhd_bus_t *bus, int cap, uint offset, bool is_ext, bool is_write,
935 uint32 writeval)
936 {
937 if (!(bus->dev)) {
938 DHD_ERROR(("%s: EP handle is NULL\n", __FUNCTION__));
939 return BCME_ERROR;
940 }
941
942 return dhdpcie_access_cap(bus->dev, cap, offset, is_ext, is_write, writeval);
943 }
944
945 /* API wrapper to read Root Port link capability
946 * Returns 2 = GEN2 1 = GEN1 BCME_ERR on linkcap not found
947 */
948
949 uint32 dhd_debug_get_rc_linkcap(dhd_bus_t *bus)
950 {
951 uint32 linkcap = -1;
952 linkcap = dhdpcie_rc_access_cap(bus, PCIE_CAP_ID_EXP,
953 PCIE_CAP_LINKCAP_OFFSET, FALSE, FALSE, 0);
954 linkcap &= PCIE_CAP_LINKCAP_LNKSPEED_MASK;
955 return linkcap;
956 }
957
958 int dhdpcie_pci_suspend_resume(dhd_bus_t *bus, bool state)
959 {
960 int rc;
961
962 struct pci_dev *dev = bus->dev;
963
964 if (state) {
965 #if !defined(BCMPCIE_OOB_HOST_WAKE)
966 dhdpcie_pme_active(bus->osh, state);
967 #endif // endif
968 rc = dhdpcie_suspend_dev(dev);
969 if (!rc) {
970 dhdpcie_suspend_host_dev(bus);
971 }
972 } else {
973 rc = dhdpcie_resume_host_dev(bus);
974 if (!rc) {
975 rc = dhdpcie_resume_dev(dev);
976 if (MULTIBP_ENAB(bus->sih) && (bus->sih->buscorerev >= 66)) {
977 /* reinit CTO configuration
978 * because cfg space got reset at D3 (PERST)
979 */
980 dhdpcie_cto_init(bus, bus->cto_enable);
981 }
982 if (bus->sih->buscorerev == 66) {
983 dhdpcie_ssreset_dis_enum_rst(bus);
984 }
985 #if !defined(BCMPCIE_OOB_HOST_WAKE)
986 dhdpcie_pme_active(bus->osh, state);
987 #endif // endif
988 }
989 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
990 #if defined(DHD_HANG_SEND_UP_TEST)
991 if (bus->is_linkdown ||
992 bus->dhd->req_hang_type == HANG_REASON_PCIE_RC_LINK_UP_FAIL) {
993 #else /* DHD_HANG_SEND_UP_TEST */
994 if (bus->is_linkdown) {
995 #endif /* DHD_HANG_SEND_UP_TEST */
996 bus->dhd->hang_reason = HANG_REASON_PCIE_RC_LINK_UP_FAIL;
997 dhd_os_send_hang_message(bus->dhd);
998 }
999 #endif // endif
1000 }
1001 return rc;
1002 }
1003
1004 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
1005 static int dhdpcie_device_scan(struct device *dev, void *data)
1006 {
1007 struct pci_dev *pcidev;
1008 int *cnt = data;
1009
1010 #if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
1011 #pragma GCC diagnostic push
1012 #pragma GCC diagnostic ignored "-Wcast-qual"
1013 #endif // endif
1014 pcidev = container_of(dev, struct pci_dev, dev);
1015 #if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
1016 #pragma GCC diagnostic pop
1017 #endif // endif
1018 if (pcidev->vendor != 0x14e4)
1019 return 0;
1020
1021 DHD_INFO(("Found Broadcom PCI device 0x%04x\n", pcidev->device));
1022 *cnt += 1;
1023 if (pcidev->driver && strcmp(pcidev->driver->name, dhdpcie_driver.name))
1024 DHD_ERROR(("Broadcom PCI Device 0x%04x has allocated with driver %s\n",
1025 pcidev->device, pcidev->driver->name));
1026
1027 return 0;
1028 }
1029 #endif /* LINUX_VERSION >= 2.6.0 */
1030
1031 int
1032 dhdpcie_bus_register(void)
1033 {
1034 int error = 0;
1035
1036 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
1037 if (!(error = pci_module_init(&dhdpcie_driver)))
1038 return 0;
1039
1040 DHD_ERROR(("%s: pci_module_init failed 0x%x\n", __FUNCTION__, error));
1041 #else
1042 if (!(error = pci_register_driver(&dhdpcie_driver))) {
1043 bus_for_each_dev(dhdpcie_driver.driver.bus, NULL, &error, dhdpcie_device_scan);
1044 if (!error) {
1045 DHD_ERROR(("No Broadcom PCI device enumerated!\n"));
1046 } else if (!dhdpcie_init_succeeded) {
1047 DHD_ERROR(("%s: dhdpcie initialize failed.\n", __FUNCTION__));
1048 } else {
1049 return 0;
1050 }
1051
1052 pci_unregister_driver(&dhdpcie_driver);
1053 error = BCME_ERROR;
1054 }
1055 #endif /* LINUX_VERSION < 2.6.0 */
1056
1057 return error;
1058 }
1059
1060 void
1061 dhdpcie_bus_unregister(void)
1062 {
1063 pci_unregister_driver(&dhdpcie_driver);
1064 }
1065
1066 int __devinit
1067 dhdpcie_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1068 {
1069
1070 if (dhdpcie_chipmatch (pdev->vendor, pdev->device)) {
1071 DHD_ERROR(("%s: chipmatch failed!!\n", __FUNCTION__));
1072 return -ENODEV;
1073 }
1074 printf("PCI_PROBE: bus %X, slot %X,vendor %X, device %X"
1075 "(good PCI location)\n", pdev->bus->number,
1076 PCI_SLOT(pdev->devfn), pdev->vendor, pdev->device);
1077
1078 if (dhdpcie_init (pdev)) {
1079 DHD_ERROR(("%s: PCIe Enumeration failed\n", __FUNCTION__));
1080 return -ENODEV;
1081 }
1082
1083 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
1084 /*
1085 Since MSM PCIe RC dev usage conunt already incremented +2 even
1086 before dhdpcie_pci_probe() called, then we inevitably to call
1087 pm_runtime_put_noidle() two times to make the count start with zero.
1088 */
1089
1090 pm_runtime_put_noidle(&pdev->dev);
1091 pm_runtime_put_noidle(&pdev->dev);
1092 pm_runtime_set_suspended(&pdev->dev);
1093 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
1094
1095 #ifdef BCMPCIE_DISABLE_ASYNC_SUSPEND
1096 /* disable async suspend */
1097 device_disable_async_suspend(&pdev->dev);
1098 #endif /* BCMPCIE_DISABLE_ASYNC_SUSPEND */
1099
1100 DHD_TRACE(("%s: PCIe Enumeration done!!\n", __FUNCTION__));
1101 return 0;
1102 }
1103
1104 int
1105 dhdpcie_detach(dhdpcie_info_t *pch)
1106 {
1107 if (pch) {
1108 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
1109 if (!dhd_download_fw_on_driverload) {
1110 pci_load_and_free_saved_state(pch->dev, &pch->default_state);
1111 }
1112 #endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
1113 MFREE(pch->osh, pch, sizeof(dhdpcie_info_t));
1114 }
1115 return 0;
1116 }
1117
1118 void __devexit
1119 dhdpcie_pci_remove(struct pci_dev *pdev)
1120 {
1121 osl_t *osh = NULL;
1122 dhdpcie_info_t *pch = NULL;
1123 dhd_bus_t *bus = NULL;
1124
1125 DHD_TRACE(("%s Enter\n", __FUNCTION__));
1126 pch = pci_get_drvdata(pdev);
1127 bus = pch->bus;
1128 osh = pch->osh;
1129
1130 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
1131 pm_runtime_get_noresume(&pdev->dev);
1132 pm_runtime_get_noresume(&pdev->dev);
1133 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
1134
1135 if (bus) {
1136 #ifdef SUPPORT_LINKDOWN_RECOVERY
1137 #ifdef CONFIG_ARCH_MSM
1138 msm_pcie_deregister_event(&bus->pcie_event);
1139 #endif /* CONFIG_ARCH_MSM */
1140 #ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY
1141 #if defined(CONFIG_SOC_EXYNOS8890) || defined(CONFIG_SOC_EXYNOS8895) || \
1142 defined(CONFIG_SOC_EXYNOS9810)
1143 exynos_pcie_deregister_event(&bus->pcie_event);
1144 #endif /* CONFIG_SOC_EXYNOS8890 || CONFIG_SOC_EXYNOS8895 ||
1145 * CONFIG_SOC_EXYNOS9810
1146 */
1147 #endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */
1148 #endif /* SUPPORT_LINKDOWN_RECOVERY */
1149
1150 bus->rc_dev = NULL;
1151
1152 dhdpcie_bus_release(bus);
1153 }
1154 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
1155 if (pci_is_enabled(pdev))
1156 #endif // endif
1157 pci_disable_device(pdev);
1158 #ifdef BCMPCIE_OOB_HOST_WAKE
1159 /* pcie os info detach */
1160 MFREE(osh, pch->os_cxt, sizeof(dhdpcie_os_info_t));
1161 #endif /* BCMPCIE_OOB_HOST_WAKE */
1162 #ifdef USE_SMMU_ARCH_MSM
1163 /* smmu info detach */
1164 dhdpcie_smmu_remove(pdev, pch->smmu_cxt);
1165 MFREE(osh, pch->smmu_cxt, sizeof(dhdpcie_smmu_info_t));
1166 #endif /* USE_SMMU_ARCH_MSM */
1167 /* pcie info detach */
1168 dhdpcie_detach(pch);
1169 /* osl detach */
1170 osl_detach(osh);
1171
1172 dhdpcie_init_succeeded = FALSE;
1173
1174 DHD_TRACE(("%s Exit\n", __FUNCTION__));
1175
1176 return;
1177 }
1178
1179 /* Enable Linux Msi */
1180 int
1181 dhdpcie_enable_msi(struct pci_dev *pdev, unsigned int min_vecs, unsigned int max_vecs)
1182 {
1183 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
1184 return pci_alloc_irq_vectors(pdev, min_vecs, max_vecs, PCI_IRQ_MSI);
1185 #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
1186 return pci_enable_msi_range(pdev, min_vecs, max_vecs);
1187 #else
1188 return pci_enable_msi_block(pdev, max_vecs);
1189 #endif // endif
1190 }
1191
1192 /* Disable Linux Msi */
1193 void
1194 dhdpcie_disable_msi(struct pci_dev *pdev)
1195 {
1196 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
1197 pci_free_irq_vectors(pdev);
1198 #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))
1199 pci_disable_msi(pdev);
1200 #else
1201 pci_disable_msi(pdev);
1202 #endif // endif
1203 return;
1204 }
1205
1206 /* Request Linux irq */
1207 int
1208 dhdpcie_request_irq(dhdpcie_info_t *dhdpcie_info)
1209 {
1210 dhd_bus_t *bus = dhdpcie_info->bus;
1211 struct pci_dev *pdev = dhdpcie_info->bus->dev;
1212 int host_irq_disabled;
1213
1214 if (!bus->irq_registered) {
1215 snprintf(dhdpcie_info->pciname, sizeof(dhdpcie_info->pciname),
1216 "dhdpcie:%s", pci_name(pdev));
1217
1218 if (bus->d2h_intr_method == PCIE_MSI) {
1219 if (dhdpcie_enable_msi(pdev, 1, 1) < 0) {
1220 DHD_ERROR(("%s: dhdpcie_enable_msi() failed\n", __FUNCTION__));
1221 dhdpcie_disable_msi(pdev);
1222 bus->d2h_intr_method = PCIE_INTX;
1223 }
1224 }
1225
1226 if (request_irq(pdev->irq, dhdpcie_isr, IRQF_SHARED,
1227 dhdpcie_info->pciname, bus) < 0) {
1228 DHD_ERROR(("%s: request_irq() failed\n", __FUNCTION__));
1229 if (bus->d2h_intr_method == PCIE_MSI) {
1230 dhdpcie_disable_msi(pdev);
1231 }
1232 return -1;
1233 }
1234 else {
1235 bus->irq_registered = TRUE;
1236 }
1237 } else {
1238 DHD_ERROR(("%s: PCI IRQ is already registered\n", __FUNCTION__));
1239 }
1240
1241 host_irq_disabled = dhdpcie_irq_disabled(bus);
1242 if (host_irq_disabled) {
1243 DHD_ERROR(("%s: PCIe IRQ was disabled(%d), so, enabled it again\n",
1244 __FUNCTION__, host_irq_disabled));
1245 dhdpcie_enable_irq(bus);
1246 }
1247
1248 DHD_TRACE(("%s %s\n", __FUNCTION__, dhdpcie_info->pciname));
1249
1250 return 0; /* SUCCESS */
1251 }
1252
1253 /**
1254 * dhdpcie_get_pcieirq - return pcie irq number to linux-dhd
1255 */
1256 int
1257 dhdpcie_get_pcieirq(struct dhd_bus *bus, unsigned int *irq)
1258 {
1259 struct pci_dev *pdev = bus->dev;
1260
1261 if (!pdev) {
1262 DHD_ERROR(("%s : bus->dev is NULL\n", __FUNCTION__));
1263 return -ENODEV;
1264 }
1265
1266 *irq = pdev->irq;
1267
1268 return 0; /* SUCCESS */
1269 }
1270
1271 #ifdef CONFIG_PHYS_ADDR_T_64BIT
1272 #define PRINTF_RESOURCE "0x%016llx"
1273 #else
1274 #define PRINTF_RESOURCE "0x%08x"
1275 #endif // endif
1276
1277 #ifdef EXYNOS_PCIE_MODULE_PATCH
1278 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
1279 extern struct pci_saved_state *bcm_pcie_default_state;
1280 #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
1281 #endif /* EXYNOS_MODULE_PATCH */
1282
1283 /*
1284
1285 Name: osl_pci_get_resource
1286
1287 Parametrs:
1288
1289 1: struct pci_dev *pdev -- pci device structure
1290 2: pci_res -- structure containing pci configuration space values
1291
1292 Return value:
1293
1294 int - Status (TRUE or FALSE)
1295
1296 Description:
1297 Access PCI configuration space, retrieve PCI allocated resources , updates in resource structure.
1298
1299 */
1300 int dhdpcie_get_resource(dhdpcie_info_t *dhdpcie_info)
1301 {
1302 phys_addr_t bar0_addr, bar1_addr;
1303 ulong bar1_size;
1304 struct pci_dev *pdev = NULL;
1305 pdev = dhdpcie_info->dev;
1306 #ifdef EXYNOS_PCIE_MODULE_PATCH
1307 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
1308 if (bcm_pcie_default_state) {
1309 pci_load_saved_state(pdev, bcm_pcie_default_state);
1310 pci_restore_state(pdev);
1311 }
1312 #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
1313 #endif /* EXYNOS_MODULE_PATCH */
1314 do {
1315 if (pci_enable_device(pdev)) {
1316 printf("%s: Cannot enable PCI device\n", __FUNCTION__);
1317 break;
1318 }
1319 pci_set_master(pdev);
1320 bar0_addr = pci_resource_start(pdev, 0); /* Bar-0 mapped address */
1321 bar1_addr = pci_resource_start(pdev, 2); /* Bar-1 mapped address */
1322
1323 /* read Bar-1 mapped memory range */
1324 bar1_size = pci_resource_len(pdev, 2);
1325
1326 if ((bar1_size == 0) || (bar1_addr == 0)) {
1327 printf("%s: BAR1 Not enabled for this device size(%ld),"
1328 " addr(0x"PRINTF_RESOURCE")\n",
1329 __FUNCTION__, bar1_size, bar1_addr);
1330 goto err;
1331 }
1332
1333 dhdpcie_info->regs = (volatile char *) REG_MAP(bar0_addr, DONGLE_REG_MAP_SIZE);
1334 dhdpcie_info->tcm_size =
1335 (bar1_size > DONGLE_TCM_MAP_SIZE) ? bar1_size : DONGLE_TCM_MAP_SIZE;
1336 dhdpcie_info->tcm = (volatile char *) REG_MAP(bar1_addr, dhdpcie_info->tcm_size);
1337
1338 if (!dhdpcie_info->regs || !dhdpcie_info->tcm) {
1339 DHD_ERROR(("%s:ioremap() failed\n", __FUNCTION__));
1340 break;
1341 }
1342 #ifdef EXYNOS_PCIE_MODULE_PATCH
1343 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
1344 if (bcm_pcie_default_state == NULL) {
1345 pci_save_state(pdev);
1346 bcm_pcie_default_state = pci_store_saved_state(pdev);
1347 }
1348 #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
1349 #endif /* EXYNOS_MODULE_PATCH */
1350
1351 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
1352 /* Backup PCIe configuration so as to use Wi-Fi on/off process
1353 * in case of built in driver
1354 */
1355 pci_save_state(pdev);
1356 dhdpcie_info->default_state = pci_store_saved_state(pdev);
1357
1358 if (dhdpcie_info->default_state == NULL) {
1359 DHD_ERROR(("%s pci_store_saved_state returns NULL\n",
1360 __FUNCTION__));
1361 REG_UNMAP(dhdpcie_info->regs);
1362 REG_UNMAP(dhdpcie_info->tcm);
1363 pci_disable_device(pdev);
1364 break;
1365 }
1366 #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
1367
1368 DHD_TRACE(("%s:Phys addr : reg space = %p base addr 0x"PRINTF_RESOURCE" \n",
1369 __FUNCTION__, dhdpcie_info->regs, bar0_addr));
1370 DHD_TRACE(("%s:Phys addr : tcm_space = %p base addr 0x"PRINTF_RESOURCE" \n",
1371 __FUNCTION__, dhdpcie_info->tcm, bar1_addr));
1372
1373 return 0; /* SUCCESS */
1374 } while (0);
1375 err:
1376 return -1; /* FAILURE */
1377 }
1378
1379 int dhdpcie_scan_resource(dhdpcie_info_t *dhdpcie_info)
1380 {
1381
1382 DHD_TRACE(("%s: ENTER\n", __FUNCTION__));
1383
1384 do {
1385 /* define it here only!! */
1386 if (dhdpcie_get_resource (dhdpcie_info)) {
1387 DHD_ERROR(("%s: Failed to get PCI resources\n", __FUNCTION__));
1388 break;
1389 }
1390 DHD_TRACE(("%s:Exit - SUCCESS \n",
1391 __FUNCTION__));
1392
1393 return 0; /* SUCCESS */
1394
1395 } while (0);
1396
1397 DHD_TRACE(("%s:Exit - FAILURE \n", __FUNCTION__));
1398
1399 return -1; /* FAILURE */
1400
1401 }
1402
1403 void dhdpcie_dump_resource(dhd_bus_t *bus)
1404 {
1405 dhdpcie_info_t *pch;
1406
1407 if (bus == NULL) {
1408 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
1409 return;
1410 }
1411
1412 if (bus->dev == NULL) {
1413 DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
1414 return;
1415 }
1416
1417 pch = pci_get_drvdata(bus->dev);
1418 if (pch == NULL) {
1419 DHD_ERROR(("%s: pch is NULL\n", __FUNCTION__));
1420 return;
1421 }
1422
1423 /* BAR0 */
1424 DHD_ERROR(("%s: BAR0(VA): 0x%pK, BAR0(PA): "PRINTF_RESOURCE", SIZE: %d\n",
1425 __FUNCTION__, pch->regs, pci_resource_start(bus->dev, 0),
1426 DONGLE_REG_MAP_SIZE));
1427
1428 /* BAR1 */
1429 DHD_ERROR(("%s: BAR1(VA): 0x%pK, BAR1(PA): "PRINTF_RESOURCE", SIZE: %d\n",
1430 __FUNCTION__, pch->tcm, pci_resource_start(bus->dev, 2),
1431 pch->tcm_size));
1432 }
1433
1434 #ifdef SUPPORT_LINKDOWN_RECOVERY
1435 #if defined(CONFIG_ARCH_MSM) || (defined(EXYNOS_PCIE_LINKDOWN_RECOVERY) && \
1436 (defined(CONFIG_SOC_EXYNOS8890) || defined(CONFIG_SOC_EXYNOS8895) || \
1437 defined(CONFIG_SOC_EXYNOS9810)))
1438 void dhdpcie_linkdown_cb(struct_pcie_notify *noti)
1439 {
1440 struct pci_dev *pdev = (struct pci_dev *)noti->user;
1441 dhdpcie_info_t *pch = NULL;
1442
1443 if (pdev) {
1444 pch = pci_get_drvdata(pdev);
1445 if (pch) {
1446 dhd_bus_t *bus = pch->bus;
1447 if (bus) {
1448 dhd_pub_t *dhd = bus->dhd;
1449 if (dhd) {
1450 DHD_ERROR(("%s: Event HANG send up "
1451 "due to PCIe linkdown\n",
1452 __FUNCTION__));
1453 #ifdef CONFIG_ARCH_MSM
1454 bus->no_cfg_restore = 1;
1455 #endif /* CONFIG_ARCH_MSM */
1456 bus->is_linkdown = 1;
1457 DHD_OS_WAKE_LOCK(dhd);
1458 dhd->hang_reason = HANG_REASON_PCIE_LINK_DOWN;
1459 dhd_os_send_hang_message(dhd);
1460 }
1461 }
1462 }
1463 }
1464
1465 }
1466 #endif /* CONFIG_ARCH_MSM || (EXYNOS_PCIE_LINKDOWN_RECOVERY &&
1467 * (CONFIG_SOC_EXYNOS8890 || CONFIG_SOC_EXYNOS8895 || CONFIG_SOC_EXYNOS9810))
1468 */
1469 #endif /* SUPPORT_LINKDOWN_RECOVERY */
1470
1471 int dhdpcie_init(struct pci_dev *pdev)
1472 {
1473
1474 osl_t *osh = NULL;
1475 dhd_bus_t *bus = NULL;
1476 dhdpcie_info_t *dhdpcie_info = NULL;
1477 wifi_adapter_info_t *adapter = NULL;
1478 #ifdef BCMPCIE_OOB_HOST_WAKE
1479 dhdpcie_os_info_t *dhdpcie_osinfo = NULL;
1480 #endif /* BCMPCIE_OOB_HOST_WAKE */
1481 #ifdef USE_SMMU_ARCH_MSM
1482 dhdpcie_smmu_info_t *dhdpcie_smmu_info = NULL;
1483 #endif /* USE_SMMU_ARCH_MSM */
1484 int ret = 0;
1485
1486 do {
1487 /* osl attach */
1488 if (!(osh = osl_attach(pdev, PCI_BUS, FALSE))) {
1489 DHD_ERROR(("%s: osl_attach failed\n", __FUNCTION__));
1490 break;
1491 }
1492
1493 /* initialize static buffer */
1494 adapter = dhd_wifi_platform_get_adapter(PCI_BUS, pdev->bus->number,
1495 PCI_SLOT(pdev->devfn));
1496 if (adapter != NULL)
1497 DHD_ERROR(("%s: found adapter info '%s'\n", __FUNCTION__, adapter->name));
1498 else
1499 DHD_ERROR(("%s: can't find adapter info for this chip\n", __FUNCTION__));
1500 osl_static_mem_init(osh, adapter);
1501
1502 /* Set ACP coherence flag */
1503 if (OSL_ACP_WAR_ENAB() || OSL_ARCH_IS_COHERENT())
1504 osl_flag_set(osh, OSL_ACP_COHERENCE);
1505
1506 /* allocate linux spcific pcie structure here */
1507 if (!(dhdpcie_info = MALLOC(osh, sizeof(dhdpcie_info_t)))) {
1508 DHD_ERROR(("%s: MALLOC of dhd_bus_t failed\n", __FUNCTION__));
1509 break;
1510 }
1511 bzero(dhdpcie_info, sizeof(dhdpcie_info_t));
1512 dhdpcie_info->osh = osh;
1513 dhdpcie_info->dev = pdev;
1514
1515 #ifdef BCMPCIE_OOB_HOST_WAKE
1516 /* allocate OS speicific structure */
1517 dhdpcie_osinfo = MALLOC(osh, sizeof(dhdpcie_os_info_t));
1518 if (dhdpcie_osinfo == NULL) {
1519 DHD_ERROR(("%s: MALLOC of dhdpcie_os_info_t failed\n",
1520 __FUNCTION__));
1521 break;
1522 }
1523 bzero(dhdpcie_osinfo, sizeof(dhdpcie_os_info_t));
1524 dhdpcie_info->os_cxt = (void *)dhdpcie_osinfo;
1525
1526 /* Initialize host wake IRQ */
1527 spin_lock_init(&dhdpcie_osinfo->oob_irq_spinlock);
1528 /* Get customer specific host wake IRQ parametres: IRQ number as IRQ type */
1529 dhdpcie_osinfo->oob_irq_num = wifi_platform_get_irq_number(adapter,
1530 &dhdpcie_osinfo->oob_irq_flags);
1531 if (dhdpcie_osinfo->oob_irq_num < 0) {
1532 DHD_ERROR(("%s: Host OOB irq is not defined\n", __FUNCTION__));
1533 }
1534 #endif /* BCMPCIE_OOB_HOST_WAKE */
1535
1536 #ifdef USE_SMMU_ARCH_MSM
1537 /* allocate private structure for using SMMU */
1538 dhdpcie_smmu_info = MALLOC(osh, sizeof(dhdpcie_smmu_info_t));
1539 if (dhdpcie_smmu_info == NULL) {
1540 DHD_ERROR(("%s: MALLOC of dhdpcie_smmu_info_t failed\n",
1541 __FUNCTION__));
1542 break;
1543 }
1544 bzero(dhdpcie_smmu_info, sizeof(dhdpcie_smmu_info_t));
1545 dhdpcie_info->smmu_cxt = (void *)dhdpcie_smmu_info;
1546
1547 /* Initialize smmu structure */
1548 if (dhdpcie_smmu_init(pdev, dhdpcie_info->smmu_cxt) < 0) {
1549 DHD_ERROR(("%s: Failed to initialize SMMU\n",
1550 __FUNCTION__));
1551 break;
1552 }
1553 #endif /* USE_SMMU_ARCH_MSM */
1554
1555 #ifdef DHD_WAKE_STATUS
1556 /* Initialize pcie_lock */
1557 spin_lock_init(&dhdpcie_info->pcie_lock);
1558 #endif /* DHD_WAKE_STATUS */
1559
1560 /* Find the PCI resources, verify the */
1561 /* vendor and device ID, map BAR regions and irq, update in structures */
1562 if (dhdpcie_scan_resource(dhdpcie_info)) {
1563 DHD_ERROR(("%s: dhd_Scan_PCI_Res failed\n", __FUNCTION__));
1564
1565 break;
1566 }
1567
1568 /* Bus initialization */
1569 ret = dhdpcie_bus_attach(osh, &bus, dhdpcie_info->regs, dhdpcie_info->tcm, pdev);
1570 if (ret != BCME_OK) {
1571 DHD_ERROR(("%s:dhdpcie_bus_attach() failed\n", __FUNCTION__));
1572 break;
1573 }
1574
1575 dhdpcie_info->bus = bus;
1576 bus->is_linkdown = 0;
1577 bus->no_bus_init = FALSE;
1578
1579 /* Get RC Device Handle */
1580 bus->rc_dev = pci_get_device(PCIE_RC_VENDOR_ID, PCIE_RC_DEVICE_ID, NULL);
1581
1582 #ifdef DONGLE_ENABLE_ISOLATION
1583 bus->dhd->dongle_isolation = TRUE;
1584 #endif /* DONGLE_ENABLE_ISOLATION */
1585 #ifdef SUPPORT_LINKDOWN_RECOVERY
1586 #ifdef CONFIG_ARCH_MSM
1587 bus->pcie_event.events = MSM_PCIE_EVENT_LINKDOWN;
1588 bus->pcie_event.user = pdev;
1589 bus->pcie_event.mode = MSM_PCIE_TRIGGER_CALLBACK;
1590 bus->pcie_event.callback = dhdpcie_linkdown_cb;
1591 bus->pcie_event.options = MSM_PCIE_CONFIG_NO_RECOVERY;
1592 msm_pcie_register_event(&bus->pcie_event);
1593 bus->no_cfg_restore = FALSE;
1594 #endif /* CONFIG_ARCH_MSM */
1595 #ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY
1596 #if defined(CONFIG_SOC_EXYNOS8890) || defined(CONFIG_SOC_EXYNOS8895) || \
1597 defined(CONFIG_SOC_EXYNOS9810)
1598 bus->pcie_event.events = EXYNOS_PCIE_EVENT_LINKDOWN;
1599 bus->pcie_event.user = pdev;
1600 bus->pcie_event.mode = EXYNOS_PCIE_TRIGGER_CALLBACK;
1601 bus->pcie_event.callback = dhdpcie_linkdown_cb;
1602 exynos_pcie_register_event(&bus->pcie_event);
1603 #endif /* CONFIG_SOC_EXYNOS8890 || CONFIG_SOC_EXYNOS8895 ||
1604 * CONFIG_SOC_EXYNOS9810
1605 */
1606 #endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */
1607 bus->read_shm_fail = FALSE;
1608 #endif /* SUPPORT_LINKDOWN_RECOVERY */
1609
1610 if (bus->intr) {
1611 /* Register interrupt callback, but mask it (not operational yet). */
1612 DHD_INTR(("%s: Registering and masking interrupts\n", __FUNCTION__));
1613 dhdpcie_bus_intr_disable(bus);
1614
1615 if (dhdpcie_request_irq(dhdpcie_info)) {
1616 DHD_ERROR(("%s: request_irq() failed\n", __FUNCTION__));
1617 break;
1618 }
1619 } else {
1620 bus->pollrate = 1;
1621 DHD_INFO(("%s: PCIe interrupt function is NOT registered "
1622 "due to polling mode\n", __FUNCTION__));
1623 }
1624
1625 #if defined(BCM_REQUEST_FW)
1626 if (dhd_bus_download_firmware(bus, osh, NULL, NULL) < 0) {
1627 DHD_ERROR(("%s: failed to download firmware\n", __FUNCTION__));
1628 }
1629 bus->nv_path = NULL;
1630 bus->fw_path = NULL;
1631 #endif /* BCM_REQUEST_FW */
1632
1633 /* set private data for pci_dev */
1634 pci_set_drvdata(pdev, dhdpcie_info);
1635
1636 if (dhd_download_fw_on_driverload) {
1637 if (dhd_bus_start(bus->dhd)) {
1638 DHD_ERROR(("%s: dhd_bud_start() failed\n", __FUNCTION__));
1639 if (!allow_delay_fwdl)
1640 break;
1641 }
1642 } else {
1643 /* Set ramdom MAC address during boot time */
1644 get_random_bytes(&bus->dhd->mac.octet[3], 3);
1645 /* Adding BRCM OUI */
1646 bus->dhd->mac.octet[0] = 0;
1647 bus->dhd->mac.octet[1] = 0x90;
1648 bus->dhd->mac.octet[2] = 0x4C;
1649 }
1650
1651 /* Attach to the OS network interface */
1652 DHD_TRACE(("%s(): Calling dhd_register_if() \n", __FUNCTION__));
1653 if (dhd_attach_net(bus->dhd, TRUE)) {
1654 DHD_ERROR(("%s(): ERROR.. dhd_register_if() failed\n", __FUNCTION__));
1655 break;
1656 }
1657
1658 dhdpcie_init_succeeded = TRUE;
1659
1660 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
1661 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTO_SUSPEND_TIMEOUT);
1662 pm_runtime_use_autosuspend(&pdev->dev);
1663 atomic_set(&bus->dhd->block_bus, FALSE);
1664 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
1665
1666 DHD_TRACE(("%s:Exit - SUCCESS \n", __FUNCTION__));
1667 return 0; /* return SUCCESS */
1668
1669 } while (0);
1670 /* reverse the initialization in order in case of error */
1671
1672 if (bus)
1673 dhdpcie_bus_release(bus);
1674
1675 #ifdef BCMPCIE_OOB_HOST_WAKE
1676 if (dhdpcie_osinfo) {
1677 MFREE(osh, dhdpcie_osinfo, sizeof(dhdpcie_os_info_t));
1678 }
1679 #endif /* BCMPCIE_OOB_HOST_WAKE */
1680
1681 #ifdef USE_SMMU_ARCH_MSM
1682 if (dhdpcie_smmu_info) {
1683 MFREE(osh, dhdpcie_smmu_info, sizeof(dhdpcie_smmu_info_t));
1684 dhdpcie_info->smmu_cxt = NULL;
1685 }
1686 #endif /* USE_SMMU_ARCH_MSM */
1687
1688 if (dhdpcie_info)
1689 dhdpcie_detach(dhdpcie_info);
1690 pci_disable_device(pdev);
1691 if (osh)
1692 osl_detach(osh);
1693
1694 dhdpcie_init_succeeded = FALSE;
1695
1696 DHD_TRACE(("%s:Exit - FAILURE \n", __FUNCTION__));
1697
1698 return -1; /* return FAILURE */
1699 }
1700
1701 /* Free Linux irq */
1702 void
1703 dhdpcie_free_irq(dhd_bus_t *bus)
1704 {
1705 struct pci_dev *pdev = NULL;
1706
1707 DHD_TRACE(("%s: freeing up the IRQ\n", __FUNCTION__));
1708 if (bus) {
1709 pdev = bus->dev;
1710 if (bus->irq_registered) {
1711 free_irq(pdev->irq, bus);
1712 bus->irq_registered = FALSE;
1713 if (bus->d2h_intr_method == PCIE_MSI) {
1714 dhdpcie_disable_msi(pdev);
1715 }
1716 } else {
1717 DHD_ERROR(("%s: PCIe IRQ is not registered\n", __FUNCTION__));
1718 }
1719 }
1720 DHD_TRACE(("%s: Exit\n", __FUNCTION__));
1721 return;
1722 }
1723
1724 /*
1725
1726 Name: dhdpcie_isr
1727
1728 Parametrs:
1729
1730 1: IN int irq -- interrupt vector
1731 2: IN void *arg -- handle to private data structure
1732
1733 Return value:
1734
1735 Status (TRUE or FALSE)
1736
1737 Description:
1738 Interrupt Service routine checks for the status register,
1739 disable interrupt and queue DPC if mail box interrupts are raised.
1740 */
1741
1742 irqreturn_t
1743 dhdpcie_isr(int irq, void *arg)
1744 {
1745 dhd_bus_t *bus = (dhd_bus_t*)arg;
1746 bus->isr_entry_time = OSL_LOCALTIME_NS();
1747 if (!dhdpcie_bus_isr(bus)) {
1748 DHD_LOG_MEM(("%s: dhdpcie_bus_isr returns with FALSE\n", __FUNCTION__));
1749 }
1750 bus->isr_exit_time = OSL_LOCALTIME_NS();
1751 return IRQ_HANDLED;
1752 }
1753
1754 int
1755 dhdpcie_disable_irq_nosync(dhd_bus_t *bus)
1756 {
1757 struct pci_dev *dev;
1758 if ((bus == NULL) || (bus->dev == NULL)) {
1759 DHD_ERROR(("%s: bus or bus->dev is NULL\n", __FUNCTION__));
1760 return BCME_ERROR;
1761 }
1762
1763 dev = bus->dev;
1764 disable_irq_nosync(dev->irq);
1765 return BCME_OK;
1766 }
1767
1768 int
1769 dhdpcie_disable_irq(dhd_bus_t *bus)
1770 {
1771 struct pci_dev *dev;
1772 if ((bus == NULL) || (bus->dev == NULL)) {
1773 DHD_ERROR(("%s: bus or bus->dev is NULL\n", __FUNCTION__));
1774 return BCME_ERROR;
1775 }
1776
1777 dev = bus->dev;
1778 disable_irq(dev->irq);
1779 return BCME_OK;
1780 }
1781
1782 int
1783 dhdpcie_enable_irq(dhd_bus_t *bus)
1784 {
1785 struct pci_dev *dev;
1786 if ((bus == NULL) || (bus->dev == NULL)) {
1787 DHD_ERROR(("%s: bus or bus->dev is NULL\n", __FUNCTION__));
1788 return BCME_ERROR;
1789 }
1790
1791 dev = bus->dev;
1792 enable_irq(dev->irq);
1793 return BCME_OK;
1794 }
1795
1796 int
1797 dhdpcie_irq_disabled(dhd_bus_t *bus)
1798 {
1799 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28))
1800 struct irq_desc *desc = irq_to_desc(bus->dev->irq);
1801 /* depth will be zero, if enabled */
1802 return desc->depth;
1803 #else
1804 /* return ERROR by default as there is no support for lower versions */
1805 return BCME_ERROR;
1806 #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
1807 }
1808
1809 int
1810 dhdpcie_start_host_pcieclock(dhd_bus_t *bus)
1811 {
1812 int ret = 0;
1813 #ifdef CONFIG_ARCH_MSM
1814 #ifdef SUPPORT_LINKDOWN_RECOVERY
1815 int options = 0;
1816 #endif /* SUPPORT_LINKDOWN_RECOVERY */
1817 #endif /* CONFIG_ARCH_MSM */
1818 DHD_TRACE(("%s Enter:\n", __FUNCTION__));
1819
1820 if (bus == NULL) {
1821 return BCME_ERROR;
1822 }
1823
1824 if (bus->dev == NULL) {
1825 return BCME_ERROR;
1826 }
1827
1828 #ifdef CONFIG_ARCH_MSM
1829 #ifdef SUPPORT_LINKDOWN_RECOVERY
1830 if (bus->no_cfg_restore) {
1831 options = MSM_PCIE_CONFIG_NO_CFG_RESTORE;
1832 }
1833 ret = msm_pcie_pm_control(MSM_PCIE_RESUME, bus->dev->bus->number,
1834 bus->dev, NULL, options);
1835 if (bus->no_cfg_restore && !ret) {
1836 msm_pcie_recover_config(bus->dev);
1837 bus->no_cfg_restore = 0;
1838 }
1839 #else
1840 ret = msm_pcie_pm_control(MSM_PCIE_RESUME, bus->dev->bus->number,
1841 bus->dev, NULL, 0);
1842 #endif /* SUPPORT_LINKDOWN_RECOVERY */
1843 if (ret) {
1844 DHD_ERROR(("%s Failed to bring up PCIe link\n", __FUNCTION__));
1845 goto done;
1846 }
1847
1848 done:
1849 #endif /* CONFIG_ARCH_MSM */
1850 DHD_TRACE(("%s Exit:\n", __FUNCTION__));
1851 return ret;
1852 }
1853
1854 int
1855 dhdpcie_stop_host_pcieclock(dhd_bus_t *bus)
1856 {
1857 int ret = 0;
1858 #ifdef CONFIG_ARCH_MSM
1859 #ifdef SUPPORT_LINKDOWN_RECOVERY
1860 int options = 0;
1861 #endif /* SUPPORT_LINKDOWN_RECOVERY */
1862 #endif /* CONFIG_ARCH_MSM */
1863
1864 DHD_TRACE(("%s Enter:\n", __FUNCTION__));
1865
1866 if (bus == NULL) {
1867 return BCME_ERROR;
1868 }
1869
1870 if (bus->dev == NULL) {
1871 return BCME_ERROR;
1872 }
1873
1874 #ifdef CONFIG_ARCH_MSM
1875 #ifdef SUPPORT_LINKDOWN_RECOVERY
1876 if (bus->no_cfg_restore) {
1877 options = MSM_PCIE_CONFIG_NO_CFG_RESTORE | MSM_PCIE_CONFIG_LINKDOWN;
1878 }
1879
1880 ret = msm_pcie_pm_control(MSM_PCIE_SUSPEND, bus->dev->bus->number,
1881 bus->dev, NULL, options);
1882 #else
1883 ret = msm_pcie_pm_control(MSM_PCIE_SUSPEND, bus->dev->bus->number,
1884 bus->dev, NULL, 0);
1885 #endif /* SUPPORT_LINKDOWN_RECOVERY */
1886 if (ret) {
1887 DHD_ERROR(("Failed to stop PCIe link\n"));
1888 goto done;
1889 }
1890 done:
1891 #endif /* CONFIG_ARCH_MSM */
1892 DHD_TRACE(("%s Exit:\n", __FUNCTION__));
1893 return ret;
1894 }
1895
1896 int
1897 dhdpcie_disable_device(dhd_bus_t *bus)
1898 {
1899 DHD_TRACE(("%s Enter:\n", __FUNCTION__));
1900
1901 if (bus == NULL) {
1902 return BCME_ERROR;
1903 }
1904
1905 if (bus->dev == NULL) {
1906 return BCME_ERROR;
1907 }
1908
1909 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
1910 if (pci_is_enabled(bus->dev))
1911 #endif // endif
1912 pci_disable_device(bus->dev);
1913
1914 return 0;
1915 }
1916
1917 int
1918 dhdpcie_enable_device(dhd_bus_t *bus)
1919 {
1920 int ret = BCME_ERROR;
1921 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
1922 dhdpcie_info_t *pch;
1923 #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
1924
1925 DHD_TRACE(("%s Enter:\n", __FUNCTION__));
1926
1927 if (bus == NULL) {
1928 return BCME_ERROR;
1929 }
1930
1931 if (bus->dev == NULL) {
1932 return BCME_ERROR;
1933 }
1934
1935 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
1936 pch = pci_get_drvdata(bus->dev);
1937 if (pch == NULL) {
1938 return BCME_ERROR;
1939 }
1940
1941 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) && (LINUX_VERSION_CODE < \
1942 KERNEL_VERSION(3, 19, 0)) && !defined(CONFIG_SOC_EXYNOS8890)
1943 /* Updated with pci_load_and_free_saved_state to compatible
1944 * with Kernel version 3.14.0 to 3.18.41.
1945 */
1946 pci_load_and_free_saved_state(bus->dev, &pch->default_state);
1947 pch->default_state = pci_store_saved_state(bus->dev);
1948 #else
1949 pci_load_saved_state(bus->dev, pch->default_state);
1950 #endif /* LINUX_VERSION >= 3.14.0 && LINUX_VERSION < 3.19.0 && !CONFIG_SOC_EXYNOS8890 */
1951
1952 /* Check if Device ID is valid */
1953 if (bus->dev->state_saved) {
1954 uint32 vid, saved_vid;
1955 pci_read_config_dword(bus->dev, PCI_CFG_VID, &vid);
1956 saved_vid = bus->dev->saved_config_space[PCI_CFG_VID];
1957 if (vid != saved_vid) {
1958 DHD_ERROR(("%s: VID(0x%x) is different from saved VID(0x%x) "
1959 "Skip the bus init\n", __FUNCTION__, vid, saved_vid));
1960 bus->no_bus_init = TRUE;
1961 /* Check if the PCIe link is down */
1962 if (vid == (uint32)-1) {
1963 bus->is_linkdown = 1;
1964 #ifdef SUPPORT_LINKDOWN_RECOVERY
1965 #ifdef CONFIG_ARCH_MSM
1966 bus->no_cfg_restore = TRUE;
1967 #endif /* CONFIG_ARCH_MSM */
1968 #endif /* SUPPORT_LINKDOWN_RECOVERY */
1969 }
1970 return BCME_ERROR;
1971 }
1972 }
1973
1974 pci_restore_state(bus->dev);
1975 #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) */
1976
1977 ret = pci_enable_device(bus->dev);
1978 if (ret) {
1979 pci_disable_device(bus->dev);
1980 } else {
1981 pci_set_master(bus->dev);
1982 }
1983
1984 return ret;
1985 }
1986
1987 int
1988 dhdpcie_alloc_resource(dhd_bus_t *bus)
1989 {
1990 dhdpcie_info_t *dhdpcie_info;
1991 phys_addr_t bar0_addr, bar1_addr;
1992 ulong bar1_size;
1993
1994 do {
1995 if (bus == NULL) {
1996 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
1997 break;
1998 }
1999
2000 if (bus->dev == NULL) {
2001 DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
2002 break;
2003 }
2004
2005 dhdpcie_info = pci_get_drvdata(bus->dev);
2006 if (dhdpcie_info == NULL) {
2007 DHD_ERROR(("%s: dhdpcie_info is NULL\n", __FUNCTION__));
2008 break;
2009 }
2010
2011 bar0_addr = pci_resource_start(bus->dev, 0); /* Bar-0 mapped address */
2012 bar1_addr = pci_resource_start(bus->dev, 2); /* Bar-1 mapped address */
2013
2014 /* read Bar-1 mapped memory range */
2015 bar1_size = pci_resource_len(bus->dev, 2);
2016
2017 if ((bar1_size == 0) || (bar1_addr == 0)) {
2018 printf("%s: BAR1 Not enabled for this device size(%ld),"
2019 " addr(0x"PRINTF_RESOURCE")\n",
2020 __FUNCTION__, bar1_size, bar1_addr);
2021 break;
2022 }
2023
2024 dhdpcie_info->regs = (volatile char *) REG_MAP(bar0_addr, DONGLE_REG_MAP_SIZE);
2025 if (!dhdpcie_info->regs) {
2026 DHD_ERROR(("%s: ioremap() for regs is failed\n", __FUNCTION__));
2027 break;
2028 }
2029
2030 bus->regs = dhdpcie_info->regs;
2031 dhdpcie_info->tcm_size =
2032 (bar1_size > DONGLE_TCM_MAP_SIZE) ? bar1_size : DONGLE_TCM_MAP_SIZE;
2033 dhdpcie_info->tcm = (volatile char *) REG_MAP(bar1_addr, dhdpcie_info->tcm_size);
2034 if (!dhdpcie_info->tcm) {
2035 DHD_ERROR(("%s: ioremap() for regs is failed\n", __FUNCTION__));
2036 REG_UNMAP(dhdpcie_info->regs);
2037 bus->regs = NULL;
2038 break;
2039 }
2040
2041 bus->tcm = dhdpcie_info->tcm;
2042
2043 DHD_TRACE(("%s:Phys addr : reg space = %p base addr 0x"PRINTF_RESOURCE" \n",
2044 __FUNCTION__, dhdpcie_info->regs, bar0_addr));
2045 DHD_TRACE(("%s:Phys addr : tcm_space = %p base addr 0x"PRINTF_RESOURCE" \n",
2046 __FUNCTION__, dhdpcie_info->tcm, bar1_addr));
2047
2048 return 0;
2049 } while (0);
2050
2051 return BCME_ERROR;
2052 }
2053
2054 void
2055 dhdpcie_free_resource(dhd_bus_t *bus)
2056 {
2057 dhdpcie_info_t *dhdpcie_info;
2058
2059 if (bus == NULL) {
2060 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
2061 return;
2062 }
2063
2064 if (bus->dev == NULL) {
2065 DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
2066 return;
2067 }
2068
2069 dhdpcie_info = pci_get_drvdata(bus->dev);
2070 if (dhdpcie_info == NULL) {
2071 DHD_ERROR(("%s: dhdpcie_info is NULL\n", __FUNCTION__));
2072 return;
2073 }
2074
2075 if (bus->regs) {
2076 REG_UNMAP(dhdpcie_info->regs);
2077 bus->regs = NULL;
2078 }
2079
2080 if (bus->tcm) {
2081 REG_UNMAP(dhdpcie_info->tcm);
2082 bus->tcm = NULL;
2083 }
2084 }
2085
2086 int
2087 dhdpcie_bus_request_irq(struct dhd_bus *bus)
2088 {
2089 dhdpcie_info_t *dhdpcie_info;
2090 int ret = 0;
2091
2092 if (bus == NULL) {
2093 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
2094 return BCME_ERROR;
2095 }
2096
2097 if (bus->dev == NULL) {
2098 DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
2099 return BCME_ERROR;
2100 }
2101
2102 dhdpcie_info = pci_get_drvdata(bus->dev);
2103 if (dhdpcie_info == NULL) {
2104 DHD_ERROR(("%s: dhdpcie_info is NULL\n", __FUNCTION__));
2105 return BCME_ERROR;
2106 }
2107
2108 if (bus->intr) {
2109 /* Register interrupt callback, but mask it (not operational yet). */
2110 DHD_INTR(("%s: Registering and masking interrupts\n", __FUNCTION__));
2111 dhdpcie_bus_intr_disable(bus);
2112 ret = dhdpcie_request_irq(dhdpcie_info);
2113 if (ret) {
2114 DHD_ERROR(("%s: request_irq() failed, ret=%d\n",
2115 __FUNCTION__, ret));
2116 return ret;
2117 }
2118 }
2119
2120 return ret;
2121 }
2122
2123 #ifdef BCMPCIE_OOB_HOST_WAKE
2124 int dhdpcie_get_oob_irq_num(dhd_bus_t *bus)
2125 {
2126 dhdpcie_info_t *pch;
2127 dhdpcie_os_info_t *dhdpcie_osinfo;
2128
2129 if (bus == NULL) {
2130 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
2131 return 0;
2132 }
2133
2134 if (bus->dev == NULL) {
2135 DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
2136 return 0;
2137 }
2138
2139 pch = pci_get_drvdata(bus->dev);
2140 if (pch == NULL) {
2141 DHD_ERROR(("%s: pch is NULL\n", __FUNCTION__));
2142 return 0;
2143 }
2144
2145 dhdpcie_osinfo = (dhdpcie_os_info_t *)pch->os_cxt;
2146
2147 return dhdpcie_osinfo ? dhdpcie_osinfo->oob_irq_num : 0;
2148 }
2149
2150 void dhdpcie_oob_intr_set(dhd_bus_t *bus, bool enable)
2151 {
2152 unsigned long flags;
2153 dhdpcie_info_t *pch;
2154 dhdpcie_os_info_t *dhdpcie_osinfo;
2155
2156 if (bus == NULL) {
2157 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
2158 return;
2159 }
2160
2161 if (bus->dev == NULL) {
2162 DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
2163 return;
2164 }
2165
2166 pch = pci_get_drvdata(bus->dev);
2167 if (pch == NULL) {
2168 DHD_ERROR(("%s: pch is NULL\n", __FUNCTION__));
2169 return;
2170 }
2171
2172 dhdpcie_osinfo = (dhdpcie_os_info_t *)pch->os_cxt;
2173 spin_lock_irqsave(&dhdpcie_osinfo->oob_irq_spinlock, flags);
2174 if ((dhdpcie_osinfo->oob_irq_enabled != enable) &&
2175 (dhdpcie_osinfo->oob_irq_num > 0)) {
2176 if (enable) {
2177 enable_irq(dhdpcie_osinfo->oob_irq_num);
2178 bus->oob_intr_enable_count++;
2179 } else {
2180 disable_irq_nosync(dhdpcie_osinfo->oob_irq_num);
2181 bus->oob_intr_disable_count++;
2182 }
2183 dhdpcie_osinfo->oob_irq_enabled = enable;
2184 }
2185 spin_unlock_irqrestore(&dhdpcie_osinfo->oob_irq_spinlock, flags);
2186 }
2187
2188 static irqreturn_t wlan_oob_irq(int irq, void *data)
2189 {
2190 dhd_bus_t *bus;
2191 unsigned long flags_bus;
2192 DHD_TRACE(("%s: IRQ Triggered\n", __FUNCTION__));
2193 bus = (dhd_bus_t *)data;
2194 dhdpcie_oob_intr_set(bus, FALSE);
2195 bus->last_oob_irq_time = OSL_LOCALTIME_NS();
2196 bus->oob_intr_count++;
2197 #ifdef DHD_WAKE_STATUS
2198 #ifdef DHD_PCIE_RUNTIMEPM
2199 /* This condition is for avoiding counting of wake up from Runtime PM */
2200 if (bus->chk_pm)
2201 #endif /* DHD_PCIE_RUNTIMPM */
2202 {
2203 bcmpcie_set_get_wake(bus, 1);
2204 }
2205 #endif /* DHD_WAKE_STATUS */
2206 #ifdef DHD_PCIE_RUNTIMEPM
2207 dhdpcie_runtime_bus_wake(bus->dhd, FALSE, wlan_oob_irq);
2208 #endif /* DHD_PCIE_RUNTIMPM */
2209 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
2210 dhd_bus_wakeup_work(bus->dhd);
2211 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
2212 DHD_BUS_LOCK(bus->bus_lock, flags_bus);
2213 /* Hold wakelock if bus_low_power_state is
2214 * DHD_BUS_D3_INFORM_SENT OR DHD_BUS_D3_ACK_RECIEVED
2215 */
2216 if (bus->dhd->up && bus->bus_low_power_state != DHD_BUS_NO_LOW_POWER_STATE) {
2217 DHD_OS_OOB_IRQ_WAKE_LOCK_TIMEOUT(bus->dhd, OOB_WAKE_LOCK_TIMEOUT);
2218 }
2219 DHD_BUS_UNLOCK(bus->bus_lock, flags_bus);
2220 return IRQ_HANDLED;
2221 }
2222
2223 int dhdpcie_oob_intr_register(dhd_bus_t *bus)
2224 {
2225 int err = 0;
2226 dhdpcie_info_t *pch;
2227 dhdpcie_os_info_t *dhdpcie_osinfo;
2228
2229 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
2230 if (bus == NULL) {
2231 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
2232 return -EINVAL;
2233 }
2234
2235 if (bus->dev == NULL) {
2236 DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
2237 return -EINVAL;
2238 }
2239
2240 pch = pci_get_drvdata(bus->dev);
2241 if (pch == NULL) {
2242 DHD_ERROR(("%s: pch is NULL\n", __FUNCTION__));
2243 return -EINVAL;
2244 }
2245
2246 dhdpcie_osinfo = (dhdpcie_os_info_t *)pch->os_cxt;
2247 if (dhdpcie_osinfo->oob_irq_registered) {
2248 DHD_ERROR(("%s: irq is already registered\n", __FUNCTION__));
2249 return -EBUSY;
2250 }
2251
2252 if (dhdpcie_osinfo->oob_irq_num > 0) {
2253 DHD_INFO_HW4(("%s OOB irq=%d flags=%X \n", __FUNCTION__,
2254 (int)dhdpcie_osinfo->oob_irq_num,
2255 (int)dhdpcie_osinfo->oob_irq_flags));
2256 err = request_irq(dhdpcie_osinfo->oob_irq_num, wlan_oob_irq,
2257 dhdpcie_osinfo->oob_irq_flags, "dhdpcie_host_wake",
2258 bus);
2259 if (err) {
2260 DHD_ERROR(("%s: request_irq failed with %d\n",
2261 __FUNCTION__, err));
2262 return err;
2263 }
2264 err = enable_irq_wake(dhdpcie_osinfo->oob_irq_num);
2265 if (!err) {
2266 dhdpcie_osinfo->oob_irq_wake_enabled = TRUE;
2267 } else {
2268 /* On Hikey platform enable_irq_wake() is failing with error
2269 * ENXIO (No such device or address). This is because the callback function
2270 * irq_set_wake() is not registered in kernel, hence returning BCME_OK.
2271 */
2272 }
2273 dhdpcie_osinfo->oob_irq_enabled = TRUE;
2274 }
2275
2276 dhdpcie_osinfo->oob_irq_registered = TRUE;
2277
2278 return err;
2279 }
2280
2281 void dhdpcie_oob_intr_unregister(dhd_bus_t *bus)
2282 {
2283 int err = 0;
2284 dhdpcie_info_t *pch;
2285 dhdpcie_os_info_t *dhdpcie_osinfo;
2286
2287 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
2288 if (bus == NULL) {
2289 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
2290 return;
2291 }
2292
2293 if (bus->dev == NULL) {
2294 DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
2295 return;
2296 }
2297
2298 pch = pci_get_drvdata(bus->dev);
2299 if (pch == NULL) {
2300 DHD_ERROR(("%s: pch is NULL\n", __FUNCTION__));
2301 return;
2302 }
2303
2304 dhdpcie_osinfo = (dhdpcie_os_info_t *)pch->os_cxt;
2305 if (!dhdpcie_osinfo->oob_irq_registered) {
2306 DHD_ERROR(("%s: irq is not registered\n", __FUNCTION__));
2307 return;
2308 }
2309 if (dhdpcie_osinfo->oob_irq_num > 0) {
2310 if (dhdpcie_osinfo->oob_irq_wake_enabled) {
2311 err = disable_irq_wake(dhdpcie_osinfo->oob_irq_num);
2312 if (!err) {
2313 dhdpcie_osinfo->oob_irq_wake_enabled = FALSE;
2314 }
2315 }
2316 if (dhdpcie_osinfo->oob_irq_enabled) {
2317 disable_irq(dhdpcie_osinfo->oob_irq_num);
2318 dhdpcie_osinfo->oob_irq_enabled = FALSE;
2319 }
2320 free_irq(dhdpcie_osinfo->oob_irq_num, bus);
2321 }
2322 dhdpcie_osinfo->oob_irq_registered = FALSE;
2323 }
2324 #endif /* BCMPCIE_OOB_HOST_WAKE */
2325
2326 #ifdef DHD_FW_COREDUMP
2327 int
2328 dhd_dongle_mem_dump(void)
2329 {
2330 if (!g_dhd_bus) {
2331 DHD_ERROR(("%s: Bus is NULL\n", __FUNCTION__));
2332 return -ENODEV;
2333 }
2334
2335 dhd_bus_dump_console_buffer(g_dhd_bus);
2336 dhd_prot_debug_info_print(g_dhd_bus->dhd);
2337
2338 g_dhd_bus->dhd->memdump_enabled = DUMP_MEMFILE_BUGON;
2339 g_dhd_bus->dhd->memdump_type = DUMP_TYPE_AP_ABNORMAL_ACCESS;
2340
2341 #ifdef DHD_PCIE_RUNTIMEPM
2342 dhdpcie_runtime_bus_wake(g_dhd_bus->dhd, TRUE, __builtin_return_address(0));
2343 #endif /* DHD_PCIE_RUNTIMEPM */
2344
2345 dhd_bus_mem_dump(g_dhd_bus->dhd);
2346 return 0;
2347 }
2348 EXPORT_SYMBOL(dhd_dongle_mem_dump);
2349 #endif /* DHD_FW_COREDUMP */
2350
2351 bool
2352 dhd_bus_check_driver_up(void)
2353 {
2354 dhd_bus_t *bus;
2355 dhd_pub_t *dhdp;
2356 bool isup = FALSE;
2357
2358 bus = (dhd_bus_t *)g_dhd_bus;
2359 if (!bus) {
2360 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
2361 return isup;
2362 }
2363
2364 dhdp = bus->dhd;
2365 if (dhdp) {
2366 isup = dhdp->up;
2367 }
2368
2369 return isup;
2370 }
2371 EXPORT_SYMBOL(dhd_bus_check_driver_up);
2372
2373 #ifdef DHD_PCIE_RUNTIMEPM
2374 bool dhd_runtimepm_state(dhd_pub_t *dhd)
2375 {
2376 dhd_bus_t *bus;
2377 unsigned long flags;
2378 bus = dhd->bus;
2379
2380 DHD_GENERAL_LOCK(dhd, flags);
2381 bus->idlecount++;
2382
2383 DHD_TRACE(("%s : Enter \n", __FUNCTION__));
2384 if ((bus->idletime > 0) && (bus->idlecount >= bus->idletime)) {
2385 bus->idlecount = 0;
2386 if (DHD_BUS_BUSY_CHECK_IDLE(dhd) && !DHD_BUS_CHECK_DOWN_OR_DOWN_IN_PROGRESS(dhd)) {
2387 bus->bus_wake = 0;
2388 DHD_BUS_BUSY_SET_RPM_SUSPEND_IN_PROGRESS(dhd);
2389 bus->runtime_resume_done = FALSE;
2390 /* stop all interface network queue. */
2391 dhd_bus_stop_queue(bus);
2392 DHD_GENERAL_UNLOCK(dhd, flags);
2393 DHD_ERROR(("%s: DHD Idle state!! - idletime :%d, wdtick :%d \n",
2394 __FUNCTION__, bus->idletime, dhd_runtimepm_ms));
2395 /* RPM suspend is failed, return FALSE then re-trying */
2396 if (dhdpcie_set_suspend_resume(bus, TRUE)) {
2397 DHD_ERROR(("%s: exit with wakelock \n", __FUNCTION__));
2398 DHD_GENERAL_LOCK(dhd, flags);
2399 DHD_BUS_BUSY_CLEAR_RPM_SUSPEND_IN_PROGRESS(dhd);
2400 dhd_os_busbusy_wake(bus->dhd);
2401 bus->runtime_resume_done = TRUE;
2402 /* It can make stuck NET TX Queue without below */
2403 dhd_bus_start_queue(bus);
2404 DHD_GENERAL_UNLOCK(dhd, flags);
2405 smp_wmb();
2406 wake_up_interruptible(&bus->rpm_queue);
2407 return FALSE;
2408 }
2409
2410 DHD_GENERAL_LOCK(dhd, flags);
2411 DHD_BUS_BUSY_CLEAR_RPM_SUSPEND_IN_PROGRESS(dhd);
2412 DHD_BUS_BUSY_SET_RPM_SUSPEND_DONE(dhd);
2413 /* For making sure NET TX Queue active */
2414 dhd_bus_start_queue(bus);
2415 DHD_GENERAL_UNLOCK(dhd, flags);
2416
2417 wait_event_interruptible(bus->rpm_queue, bus->bus_wake);
2418
2419 DHD_GENERAL_LOCK(dhd, flags);
2420 DHD_BUS_BUSY_CLEAR_RPM_SUSPEND_DONE(dhd);
2421 DHD_BUS_BUSY_SET_RPM_RESUME_IN_PROGRESS(dhd);
2422 DHD_GENERAL_UNLOCK(dhd, flags);
2423
2424 dhdpcie_set_suspend_resume(bus, FALSE);
2425
2426 DHD_GENERAL_LOCK(dhd, flags);
2427 DHD_BUS_BUSY_CLEAR_RPM_RESUME_IN_PROGRESS(dhd);
2428 dhd_os_busbusy_wake(bus->dhd);
2429 /* Inform the wake up context that Resume is over */
2430 bus->runtime_resume_done = TRUE;
2431 /* For making sure NET TX Queue active */
2432 dhd_bus_start_queue(bus);
2433 DHD_GENERAL_UNLOCK(dhd, flags);
2434
2435 smp_wmb();
2436 wake_up_interruptible(&bus->rpm_queue);
2437 DHD_ERROR(("%s : runtime resume ended \n", __FUNCTION__));
2438 return TRUE;
2439 } else {
2440 DHD_GENERAL_UNLOCK(dhd, flags);
2441 /* Since one of the contexts are busy (TX, IOVAR or RX)
2442 * we should not suspend
2443 */
2444 DHD_ERROR(("%s : bus is active with dhd_bus_busy_state = 0x%x\n",
2445 __FUNCTION__, dhd->dhd_bus_busy_state));
2446 return FALSE;
2447 }
2448 }
2449
2450 DHD_GENERAL_UNLOCK(dhd, flags);
2451 return FALSE;
2452 } /* dhd_runtimepm_state */
2453
2454 /*
2455 * dhd_runtime_bus_wake
2456 * TRUE - related with runtime pm context
2457 * FALSE - It isn't invloved in runtime pm context
2458 */
2459 bool dhd_runtime_bus_wake(dhd_bus_t *bus, bool wait, void *func_addr)
2460 {
2461 unsigned long flags;
2462 bus->idlecount = 0;
2463 DHD_TRACE(("%s : enter\n", __FUNCTION__));
2464 if (bus->dhd->up == FALSE) {
2465 DHD_INFO(("%s : dhd is not up\n", __FUNCTION__));
2466 return FALSE;
2467 }
2468
2469 DHD_GENERAL_LOCK(bus->dhd, flags);
2470 if (DHD_BUS_BUSY_CHECK_RPM_ALL(bus->dhd)) {
2471 /* Wake up RPM state thread if it is suspend in progress or suspended */
2472 if (DHD_BUS_BUSY_CHECK_RPM_SUSPEND_IN_PROGRESS(bus->dhd) ||
2473 DHD_BUS_BUSY_CHECK_RPM_SUSPEND_DONE(bus->dhd)) {
2474 bus->bus_wake = 1;
2475
2476 DHD_GENERAL_UNLOCK(bus->dhd, flags);
2477
2478 DHD_ERROR(("Runtime Resume is called in %pf\n", func_addr));
2479 smp_wmb();
2480 wake_up_interruptible(&bus->rpm_queue);
2481 /* No need to wake up the RPM state thread */
2482 } else if (DHD_BUS_BUSY_CHECK_RPM_RESUME_IN_PROGRESS(bus->dhd)) {
2483 DHD_GENERAL_UNLOCK(bus->dhd, flags);
2484 }
2485
2486 /* If wait is TRUE, function with wait = TRUE will be wait in here */
2487 if (wait) {
2488 wait_event_interruptible(bus->rpm_queue, bus->runtime_resume_done);
2489 } else {
2490 DHD_INFO(("%s: bus wakeup but no wait until resume done\n", __FUNCTION__));
2491 }
2492 /* If it is called from RPM context, it returns TRUE */
2493 return TRUE;
2494 }
2495
2496 DHD_GENERAL_UNLOCK(bus->dhd, flags);
2497
2498 return FALSE;
2499 }
2500
2501 bool dhdpcie_runtime_bus_wake(dhd_pub_t *dhdp, bool wait, void* func_addr)
2502 {
2503 dhd_bus_t *bus = dhdp->bus;
2504 return dhd_runtime_bus_wake(bus, wait, func_addr);
2505 }
2506
2507 void dhdpcie_block_runtime_pm(dhd_pub_t *dhdp)
2508 {
2509 dhd_bus_t *bus = dhdp->bus;
2510 bus->idletime = 0;
2511 }
2512
2513 bool dhdpcie_is_resume_done(dhd_pub_t *dhdp)
2514 {
2515 dhd_bus_t *bus = dhdp->bus;
2516 return bus->runtime_resume_done;
2517 }
2518 #endif /* DHD_PCIE_RUNTIMEPM */
2519
2520 struct device * dhd_bus_to_dev(dhd_bus_t *bus)
2521 {
2522 struct pci_dev *pdev;
2523 pdev = bus->dev;
2524
2525 if (pdev)
2526 return &pdev->dev;
2527 else
2528 return NULL;
2529 }