projects / GitHub / exynos8895 / android_kernel_samsung_universal8895.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
dts: early mount efs
[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / arch / arm64 / boot / dts / exynos / exynos8895.dtsi
1 /*
2 * SAMSUNG EXYNOS8895 SoC device tree source
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS8895 SoC device nodes are listed in this file.
8 * EXYNOS8895 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16 #include <dt-bindings/clock/exynos8895.h>
17 #include <dt-bindings/ufs/ufs.h>
18 #include <dt-bindings/soc/samsung/exynos8895.h>
19 #include <dt-bindings/sysmmu/sysmmu.h>
20 #include <dt-bindings/thermal/thermal.h>
21 #include "exynos8895-pinctrl.dtsi"
22 #include "exynos8895-pm-domains.dtsi"
23 #include "exynos8895-ess.dtsi"
24
25 / {
26 compatible = "samsung,armv8", "samsung,exynos8895";
27 interrupt-parent = <&gic>;
28 #address-cells = <2>;
29 #size-cells = <1>;
30
31 firmware: firmware {
32 android {
33 compatible = "android,firmware";
34 fstab {
35 compatible = "android,fstab";
36 system {
37 compatible = "android,system";
38 dev = "/dev/block/platform/11120000.ufs/by-name/SYSTEM";
39 type = "ext4";
40 mnt_flags = "ro,noatime";
41 fsmgr_flags = "wait";
42 status = "ok";
43 };
44 efs {
45 compatible = "android,efs";
46 dev = "/dev/block/platform/11120000.ufs/by-name/EFS";
47 type = "ext4";
48 mnt_flags = "noatime,nosuid,nodev,noauto_da_alloc,discard,journal_checksum,data=ordered,errors=panic";
49 fsmgr_flags = "wait,check";
50 status = "ok";
51 };
52 };
53 };
54 };
55
56 arm-pmu {
57 compatible = "arm,armv8-pmuv3";
58 interrupts = <0 24 4>,
59 <0 25 4>,
60 <0 26 4>,
61 <0 27 4>,
62 <0 40 4>,
63 <0 41 4>,
64 <0 42 4>,
65 <0 43 4>;
66 };
67
68 aliases {
69 pinctrl0 = &pinctrl_0;
70 pinctrl1 = &pinctrl_1;
71 pinctrl2 = &pinctrl_2;
72 pinctrl3 = &pinctrl_3;
73 pinctrl4 = &pinctrl_4;
74 pinctrl5 = &pinctrl_5;
75 pinctrl6 = &pinctrl_6;
76 pinctrl7 = &pinctrl_7;
77 usi0 = &usi_0;
78 usi1 = &usi_1;
79 usi2 = &usi_2;
80 usi3 = &usi_3;
81 usi4 = &usi_4;
82 usi5 = &usi_5;
83 usi6 = &usi_6;
84 usi7 = &usi_7;
85 usi8 = &usi_8;
86 usi9 = &usi_9;
87 usi10 = &usi_10;
88 usi11 = &usi_11;
89 usi12 = &usi_12;
90 usi13 = &usi_13;
91 uart0 = &serial_0;
92 uart1 = &serial_1;
93 uart2 = &serial_2;
94 uart3 = &serial_3;
95 uart4 = &serial_4;
96 uart5 = &serial_5;
97 uart6 = &serial_6;
98 uart7 = &serial_7;
99 uart8 = &serial_8;
100 uart9 = &serial_9;
101 uart10 = &serial_10;
102 uart11 = &serial_11;
103 uart12 = &serial_12;
104 uart13 = &serial_13;
105 uart14 = &serial_14;
106 uart15 = &serial_15;
107 hsi2c0 = &hsi2c_0;
108 hsi2c1 = &hsi2c_1;
109 hsi2c2 = &hsi2c_2;
110 hsi2c3 = &hsi2c_3;
111 hsi2c4 = &hsi2c_4;
112 hsi2c5 = &hsi2c_5;
113 hsi2c6 = &hsi2c_6;
114 hsi2c7 = &hsi2c_7;
115 hsi2c8 = &hsi2c_8;
116 hsi2c9 = &hsi2c_9;
117 hsi2c10 = &hsi2c_10;
118 hsi2c11 = &hsi2c_11;
119 hsi2c12 = &hsi2c_12;
120 hsi2c13 = &hsi2c_13;
121 hsi2c14 = &hsi2c_14;
122 hsi2c15 = &hsi2c_15;
123 hsi2c16 = &hsi2c_16;
124 hsi2c17 = &hsi2c_17;
125 hsi2c18 = &hsi2c_18;
126 hsi2c19 = &hsi2c_19;
127 hsi2c20 = &hsi2c_20;
128 hsi2c21 = &hsi2c_21;
129 hsi2c22 = &hsi2c_22;
130 hsi2c23 = &hsi2c_23;
131 hsi2c24 = &hsi2c_24;
132 hsi2c25 = &hsi2c_25;
133 hsi2c26 = &hsi2c_26;
134 hsi2c27 = &hsi2c_27;
135 hsi2c28 = &hsi2c_28;
136 hsi2c29 = &hsi2c_29;
137 hsi2c30 = &hsi2c_30;
138 hsi2c31 = &hsi2c_31;
139 hsi2c32 = &hsi2c_32;
140 spi0 = &spi_0;
141 spi1 = &spi_1;
142 spi2 = &spi_2;
143 spi3 = &spi_3;
144 spi4 = &spi_4;
145 spi5 = &spi_5;
146 spi6 = &spi_6;
147 spi7 = &spi_7;
148 spi8 = &spi_8;
149 spi9 = &spi_9;
150 spi10 = &spi_10;
151 spi11 = &spi_11;
152 spi12 = &spi_12;
153 spi13 = &spi_13;
154 spi14 = &spi_14;
155 spi15 = &spi_15;
156 dpp0 = &idma_g0;
157 dpp1 = &idma_g1;
158 dpp2 = &idma_vg0;
159 dpp3 = &idma_vg1;
160 dpp4 = &idma_vgf0;
161 dpp5 = &idma_vgf1;
162 dpp6 = &odma_wb;
163 dsim0 = &dsim_0;
164 displayport = &displayport;
165 decon0 = &decon_f;
166 decon1 = &decon_s;
167 decon2 = &decon_t;
168 mshc2 = &dwmmc_2;
169 scaler0 = &scaler_0;
170 mfc0 = &mfc_0;
171 };
172
173 chipid@10000000 {
174 compatible = "samsung,exynos8895-chipid";
175 reg = <0x0 0x10000000 0x100>;
176 };
177
178 reboot {
179 compatible = "exynos,reboot";
180 pmu_base = <0x16480000>;
181 };
182
183 cpus {
184 #address-cells = <2>;
185 #size-cells = <0>;
186
187 hmp {
188 up_threshold = <524>;
189 down_threshold = <214>;
190 semiboost_up_threshold = <254>;
191 semiboost_down_threshold = <163>;
192 bootboost-duration-us = <40000000>;
193 down_compensation_timeout = <30>; /* ms */
194 down_compensation_high_freq = <1248000>; /* min qos lock for little cpu */
195 down_compensation_mid_freq = <1053000>; /* min qos lock for little cpu */
196 down_compensation_low_freq = <832000>; /* min qos lock for little cpu */
197 hmp_up_compst_ratio = <512>;
198 hmp_down_compst_ratio = <2048>;
199 little-id = <1>;
200 };
201
202 auto_cpu_mapping {
203 enabled = <1>;
204 };
205
206 cpu0: cpu@100 {
207 device_type = "cpu";
208 compatible = "arm,cortex-a53", "arm,armv8";
209 reg = <0x0 0x100>;
210 logical-id = <0>;
211 enable-method = "psci";
212 cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
213 #cooling-cells = <2>; /* min followed by max */
214 current = <60240 40410 27260 20180 16850 13710 10710 8290 6060>;
215 };
216 cpu@101 {
217 device_type = "cpu";
218 compatible = "arm,cortex-a53", "arm,armv8";
219 reg = <0x0 0x101>;
220 logical-id = <1>;
221 enable-method = "psci";
222 cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
223 current = <60240 40410 27260 20180 16850 13710 10710 8290 6060>;
224 };
225 cpu@102 {
226 device_type = "cpu";
227 compatible = "arm,cortex-a53", "arm,armv8";
228 reg = <0x0 0x102>;
229 logical-id = <2>;
230 enable-method = "psci";
231 cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
232 current = <60240 40410 27260 20180 16850 13710 10710 8290 6060>;
233 };
234 cpu@103 {
235 device_type = "cpu";
236 compatible = "arm,cortex-a53", "arm,armv8";
237 reg = <0x0 0x103>;
238 logical-id = <3>;
239 enable-method = "psci";
240 cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
241 current = <60240 40410 27260 20180 16850 13710 10710 8290 6060>;
242 };
243 cpu4: cpu@0 {
244 device_type = "cpu";
245 compatible = "arm,mongoose", "arm,armv8";
246 reg = <0x0 0x0>;
247 logical-id = <4>;
248 enable-method = "psci";
249 cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
250 #cooling-cells = <2>; /* min followed by max */
251 current = <355850 295970 251060 233620 201350 177320 137850 111850 100000 88090 78470 69380 58880>;
252 };
253 cpu@1 {
254 device_type = "cpu";
255 compatible = "arm,mongoose", "arm,armv8";
256 reg = <0x0 0x1>;
257 logical-id = <5>;
258 enable-method = "psci";
259 cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
260 current = <355850 295970 251060 233620 201350 177320 137850 111850 100000 88090 78470 69380 58880>;
261 };
262 cpu@2 {
263 device_type = "cpu";
264 compatible = "arm,mongoose", "arm,armv8";
265 reg = <0x0 0x2>;
266 logical-id = <6>;
267 enable-method = "psci";
268 cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
269 current = <355850 295970 251060 233620 201350 177320 137850 111850 100000 88090 78470 69380 58880>;
270 };
271 cpu@3 {
272 device_type = "cpu";
273 compatible = "arm,mongoose", "arm,armv8";
274 reg = <0x0 0x3>;
275 logical-id = <7>;
276 enable-method = "psci";
277 cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
278 current = <355850 295970 251060 233620 201350 177320 137850 111850 100000 88090 78470 69380 58880>;
279 };
280
281 idle-states {
282 entry-method = "arm,psci";
283
284 BOOTCL_CPU_SLEEP: bootcl-cpu-sleep {
285 idle-state-name = "c2";
286 compatible = "exynos,idle-state";
287 arm,psci-suspend-param = <0x0010000>;
288 entry-latency-us = <35>;
289 exit-latency-us = <90>;
290 min-residency-us = <750>;
291 status = "okay";
292 };
293
294 NONBOOTCL_CPU_SLEEP: nobootcl-cpu-sleep {
295 idle-state-name = "c2";
296 compatible = "exynos,idle-state";
297 arm,psci-suspend-param = <0x0010000>;
298 entry-latency-us = <30>;
299 exit-latency-us = <75>;
300 min-residency-us = <2000>;
301 status = "okay";
302 };
303 };
304 };
305
306 psci {
307 compatible = "arm,psci";
308 method = "smc";
309 cpu_suspend = <0xC4000001>;
310 cpu_off = <0x84000002>;
311 cpu_on = <0xC4000003>;
312 };
313
314 cpu_hotplug {
315 compatible = "exynos,cpu_hotplug";
316 boot_lock_time = <40>;
317 };
318
319 exynos-pmu {
320 compatible = "samsung,exynos-pmu";
321 samsung,syscon-phandle = <&pmu_system_controller>;
322 };
323
324 pmu_system_controller: system-controller@16480000 {
325 compatible = "samsung,exynos8895-pmu", "syscon";
326 reg = <0x0 0x16480000 0x10000>;
327 };
328
329 exynos-pm {
330 compatible = "samsung,exynos-pm";
331 reg = <0x0 0x164B0000 0x1000>,
332 <0x0 0x10201200 0x100>;
333 reg-names = "gpio_alive_base",
334 "gicd_ispendrn_base";
335 num-eint = <32>;
336 num-gic = <16>;
337 suspend_mode_idx = <8>; /* SYS_SLEEP */
338 suspend_psci_idx = <133>; /* PSCI_SYSTEM_SLEEP */
339 cp_call_mode_idx = <10>; /* SYS_SLEEP_AUD_ON */
340 cp_call_psci_idx = <133>; /* PSCI_SYSTEM_SLEEP */
341 extra_wakeup_stat = <0x640>;
342 };
343
344 exynos-powermode {
345 cpd_residency = <3000>;
346 sicd_residency = <3000>;
347 cpd_enabled = <1>;
348 sicd_enabled = <1>;
349
350 idle-ip = "104c0000.pwm", /* [ 0] pwm */
351 "15b70000.adc", /* [ 1] adc */
352 "15bc0000.hsi2c", /* [ 2] hsi2c_0 */
353 "10990000.hsi2c", /* [ 3] hsi2c_1 */
354 "109a0000.hsi2c", /* [ 4] hsi2c_2 */
355 "109b0000.hsi2c", /* [ 5] hsi2c_3 */
356 "109c0000.hsi2c", /* [ 6] hsi2c_4 */
357 "10440000.hsi2c", /* [ 7] hsi2c_5 */
358 "10450000.hsi2c", /* [ 8] hsi2c_6 */
359 "10460000.hsi2c", /* [ 9] hsi2c_7 */
360 "10470000.hsi2c", /* [10] hsi2c_8 */
361 "10480000.hsi2c", /* [11] hsi2c_9 */
362 "10490000.hsi2c", /* [12] hsi2c_10 */
363 "104a0000.hsi2c", /* [13] hsi2c_11 */
364 "104b0000.hsi2c", /* [14] hsi2c_12 */
365 "10840000.hsi2c", /* [15] hsi2c_13 */
366 "10850000.hsi2c", /* [16] hsi2c_14 */
367 "10860000.hsi2c", /* [17] hsi2c_15 */
368 "10870000.hsi2c", /* [18] hsi2c_16 */
369 "10880000.hsi2c", /* [19] hsi2c_17 */
370 "10890000.hsi2c", /* [20] hsi2c_18 */
371 "108a0000.hsi2c", /* [21] hsi2c_19 */
372 "108b0000.hsi2c", /* [22] hsi2c_20 */
373 "108c0000.hsi2c", /* [23] hsi2c_21 */
374 "108d0000.hsi2c", /* [24] hsi2c_22 */
375 "108e0000.hsi2c", /* [25] hsi2c_23 */
376 "108f0000.hsi2c", /* [26] hsi2c_24 */
377 "10900000.hsi2c", /* [27] hsi2c_25 */
378 "10910000.hsi2c", /* [28] hsi2c_26 */
379 "10920000.hsi2c", /* [29] hsi2c_27 */
380 "10930000.hsi2c", /* [30] hsi2c_28 */
381 "10940000.hsi2c", /* [31] hsi2c_29 */
382 "10950000.hsi2c", /* [32] hsi2c_30 */
383 "10960000.hsi2c", /* [33] hsi2c_31 */
384 "10970000.hsi2c", /* [34] hsi2c_32 */
385 "109e0000.spi", /* [35] spi_0 */
386 "109e0000.spi", /* [36] spi_1 */
387 "10440000.spi", /* [37] spi_2 */
388 "10460000.spi", /* [38] spi_3 */
389 "10480000.spi", /* [39] spi_4 */
390 "104a0000.spi", /* [40] spi_5 */
391 "10840000.spi", /* [41] spi_6 */
392 "10860000.spi", /* [42] spi_7 */
393 "10880000.spi", /* [43] spi_8 */
394 "108a0000.spi", /* [44] spi_9 */
395 "108c0000.spi", /* [45] spi_10 */
396 "108e0000.spi", /* [46] spi_11 */
397 "10900000.spi", /* [47] spi_12 */
398 "10920000.spi", /* [48] spi_13 */
399 "10940000.spi", /* [49] spi_14 */
400 "10960000.spi", /* [50] spi_15 */
401 "11120000.ufs", /* [51] ufs */
402 "11500000.dwmmc2", /* [52] dwmmc2 */
403 "10c00000.usb", /* [53] usb */
404 "14040000.mailbox", /* [54] mailbox */
405 "116a0000.pcie0", /* [55] pcie0 */
406 "116b0000.pcie1", /* [56] pcie1 */
407 "pd-abox", /* [57] pd-abox */
408 "pd-cam", /* [58] pd-cam */
409 "pd-dbg", /* [59] pd-dbg */
410 "pd-dcam", /* [60] pd-dcam */
411 "pd-dpu0", /* [61] pd-dpu0 */
412 "pd-dpu1", /* [62] pd-dpu1 */
413 "pd-dsp", /* [63] pd-dsp */
414 "pd-g2d", /* [64] pd-g2d */
415 "pd-g3d", /* [65] pd-g3d */
416 "pd-isphq", /* [66] pd-isphq */
417 "pd-isplp", /* [67] pd-isplp */
418 "pd-iva", /* [68] pd-iva */
419 "pd-mfc", /* [69] pd-mfc */
420 "pd-srdz", /* [70] pd-srdz */
421 "pd-vpu", /* [71] pd-vpu */
422 "pd-vts", /* [72] pd-vts */
423 "bluetooth"; /* [73] bluetooth */
424
425 fix-idle-ip = "acpm_dvfs";
426 fix-idle-ip-index = <96>;
427
428 idle_ip_mask {
429 sicd: SYS_SICD {
430 mode-index = <0>;
431 ref-idle-ip = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>,
432 <10>, <11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>,
433 <20>, <21>, <22>, <23>, <24>, <25>, <26>, <27>, <28>, <29>,
434 <30>, <31>, <32>, <33>, <34>, <35>, <36>, <37>, <38>, <39>,
435 <40>, <41>, <42>, <43>, <44>, <45>, <46>, <47>, <48>, <49>,
436 <50>, <51>, <52>, <53>, <54>, <55>, <56>, <58>,
437 <60>, <61>, <62>, <63>, <64>, <65>, <66>, <67>, <68>, <69>,
438 <70>, <71>, <73>, <96>;
439 };
440 };
441
442 wakeup-masks {
443 /*
444 * wakeup_mask configuration
445 * SICD SICD_CPD AFTR STOP
446 * LPD LPA ALPA DSTOP
447 * SLEEP SLEEP_VTS_ON SLEEP_AUD_ON FAPO
448 */
449 wakeup-mask {
450 mask = <0x400001E0>, <0x0>, <0x0>, <0x0>,
451 <0x0>, <0x0>, <0x0>, <0x0>,
452 <0x500F7E7E>, <0x500F7E7E>, <0x500F7E7E>, <0x0>;
453 reg-offset = <0x610>;
454 };
455 wakeup-mask2 {
456 mask = <0x0>, <0x0>, <0x0>, <0x0>,
457 <0x0>, <0x0>, <0x0>, <0x0>,
458 <0xFFFF00FF>, <0xFFFF00FF>, <0xFFFF00FF>, <0x0>;
459 reg-offset = <0x614>;
460 };
461 wakeup-mask3 {
462 mask = <0x0>, <0x0>, <0x0>, <0x0>,
463 <0x0>, <0x0>, <0x0>, <0x0>,
464 <0xFFFF00FF>, <0xFFFF00FF>, <0xFFFF00FF>, <0x0>;
465 reg-offset = <0x618>;
466 };
467 wakeup-mask4 {
468 mask = <0x0>, <0x0>, <0x0>, <0x0>,
469 <0x0>, <0x0>, <0x0>, <0x0>,
470 <0x0>, <0x0>, <0x0>, <0x0>;
471 reg-offset = <0x644>;
472 };
473 };
474 };
475
476 schedtune {
477 domain@0 {
478 device_type = "schedtune-freqvar";
479 shared-cpus = "0-3";
480 /* this table works like target_load of interactive parameter */
481 table = < 100 598000 60 715000 30 832000 20 949000 10 1053000 0 >;
482 };
483 domain@1 {
484 device_type = "schedtune-freqvar";
485 shared-cpus = "4-7";
486 /* this table works like target_load of interactive parameter */
487 table = < 20 858000 15 962000 5 1261000 0 >;
488 };
489 };
490
491 cpufreq {
492 domain@0 {
493 device_type = "cpufreq-domain";
494 sibling-cpus = "0-3";
495 cal-id = <ACPM_DVFS_CPUCL1>;
496 dm-type = <DM_CPU_CL0>;
497
498 min-freq = <455000>;
499
500 /* PM QoS Class ID*/
501 pm_qos-min-class = <3>;
502 pm_qos-max-class = <4>;
503
504 user-default-qos = <715000>;
505
506 /* auto calibration value */
507 auto-cal-freq = <1053000>;
508 auto-cal-duration = <400>; /* ms */
509
510 dm-constraints {
511 mif-perf {
512 const-type = <CONSTRAINT_MIN>;
513 dm-type = <DM_MIF>;
514 /* cpu mif */
515 table = < 2002000 1014000
516 1898000 1014000
517 1794000 1014000
518 1690000 1014000
519 1456000 845000
520 1248000 845000
521 1053000 845000
522 949000 845000
523 832000 676000
524 715000 676000
525 598000 421000
526 455000 0
527 >;
528 };
529 mif-skew {
530 guidance;
531 const-type = <CONSTRAINT_MIN>;
532 dm-type = <DM_MIF>;
533 ect-name = "dvfs_cpucl1";
534 };
535 };
536 };
537 domain@1 {
538 device_type = "cpufreq-domain";
539 sibling-cpus = "4-7";
540 cal-id = <ACPM_DVFS_CPUCL0>;
541 dm-type = <DM_CPU_CL1>;
542
543 min-freq = <741000>;
544
545 /* PM QoS Class ID*/
546 pm_qos-min-class = <5>;
547 pm_qos-max-class = <6>;
548 pm_qos-jigbooting = <1469000>;
549
550 /* auto calibration value */
551 auto-cal-freq = <1703000>;
552 auto-cal-duration = <400>; /* ms */
553
554 dm-constraints {
555 mif-perf {
556 const-type = <CONSTRAINT_MIN>;
557 dm-type = <DM_MIF>;
558 /* cpu mif */
559 table = < 2808000 1794000
560 2704000 1794000
561 2652000 1794000
562 2574000 1794000
563 2496000 1794000
564 2314000 1794000
565 2158000 1540000
566 2002000 1540000
567 1937000 1352000
568 1807000 1352000
569 1703000 1014000
570 1469000 845000
571 1261000 676000
572 1170000 546000
573 1066000 546000
574 962000 421000
575 858000 421000
576 741000 421000 >;
577 };
578 mif-skew {
579 guidance;
580 const-type = <CONSTRAINT_MIN>;
581 dm-type = <DM_MIF>;
582 ect-name = "dvfs_cpucl0";
583 };
584 };
585 };
586 };
587
588 gic:interrupt-controller@10200000 {
589 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
590 #interrupt-cells = <3>;
591 #address-cells = <0>;
592 interrupt-controller;
593 reg = <0x0 0x10201000 0x1000>,
594 <0x0 0x10202000 0x1000>,
595 <0x0 0x10204000 0x2000>,
596 <0x0 0x10206000 0x2000>;
597 interrupts = <1 9 0xf04>;
598 };
599
600 timer {
601 compatible = "arm,armv8-timer";
602 interrupts = <1 13 0xff01>,
603 <1 14 0xff01>,
604 <1 11 0xff01>,
605 <1 10 0xff01>;
606 clock-frequency = <26000000>;
607 use-clocksource-only;
608 use-physical-timer;
609 };
610
611 clock: clock-controller@0x15a80000 {
612 compatible = "samsung,exynos8895-clock";
613 reg = <0x0 0x15a80000 0x8000>;
614 #clock-cells = <1>;
615 acpm-ipc-channel = <0>;
616 };
617
618 sysreg_fsys0_controller: sysreg-controller@11020000 {
619 compatible = "samsung,exynos8895-sysreg", "syscon";
620 reg = <0x0 0x11020000 0x1200>;
621 };
622
623 sysreg_fsys1_controller: sysreg-controller@11420000 {
624 compatible = "samsung,exynos8895-sysreg", "syscon";
625 reg = <0x0 0x11420000 0x1200>;
626 };
627
628 mct@10040000 {
629 compatible = "samsung,exynos4210-mct";
630 reg = <0x0 0x10040000 0x800>;
631 interrupt-controller;
632 #interrupt-cells = <1>;
633 interrupt-parent = <&mct_map>;
634 interrupts = <0>, <1>, <2>, <3>,
635 <4>, <5>, <6>, <7>,
636 <8>, <9>, <10>, <11>;
637 clocks = <&clock OSCCLK>, <&clock GATE_MCT>;
638 clock-names = "fin_pll", "mct";
639 use-clockevent-only;
640
641 mct_map: mct-map {
642 #interrupt-cells = <1>;
643 #address-cells = <0>;
644 #size-cells = <0>;
645 interrupt-map = <0 &gic 0 455 0>,
646 <1 &gic 0 456 0>,
647 <2 &gic 0 457 0>,
648 <3 &gic 0 458 0>,
649 <4 &gic 0 459 0>,
650 <5 &gic 0 460 0>,
651 <6 &gic 0 461 0>,
652 <7 &gic 0 462 0>,
653 <8 &gic 0 463 0>,
654 <9 &gic 0 464 0>,
655 <10 &gic 0 465 0>,
656 <11 &gic 0 466 0>;
657 };
658 };
659
660 /* DMA */
661 amba {
662 #address-cells = <2>;
663 #size-cells = <1>;
664 compatible = "arm,amba-bus";
665 interrupt-parent = <&gic>;
666 ranges;
667
668 pdma0: pdma0@15A40000 {
669 compatible = "arm,pl330", "arm,primecell";
670 reg = <0x0 0x15A40000 0x1000>;
671 interrupts = <0 107 0>;
672 clocks = <&clock GATE_PDMA0>;
673 clock-names = "apb_pclk";
674 #dma-cells = <2>;
675 #dma-channels = <8>;
676 #dma-requests = <32>;
677 #dma_mcode_addr = <0x13F2C000>;
678 #dma-multi-irq = <1>;
679 dma-arwrapper = <0x15A44400>,
680 <0x15A44420>,
681 <0x15A44440>,
682 <0x15A44460>,
683 <0x15A44480>,
684 <0x15A444A0>,
685 <0x15A444C0>,
686 <0x15A444E0>;
687 dma-awwrapper = <0x15A44404>,
688 <0x15A44424>,
689 <0x15A44444>,
690 <0x15A44464>,
691 <0x15A44484>,
692 <0x15A444A4>,
693 <0x15A444C4>,
694 <0x15A444E4>;
695 dma-instwrapper = <0x15A44500>;
696 dma-selchan = <0x15A22200>;
697 dma-mask-bit = <36>;
698 coherent-mask-bit = <36>;
699 };
700 };
701
702
703 ITMON@0 {
704 compatible = "samsung,exynos-itmon";
705 interrupts = <0 72 0>, /* DATA_BUS_1 */
706 <0 311 0>, /* DATA_CORE */
707 <0 92 0>, /* DATA_BUS_C */
708 <0 315 0>, /* PERI_CORE_0 */
709 <0 316 0>, /* PERI_CORE_1 */
710 <0 93 0>, /* PERI_BUS_C */
711 <0 77 0>; /* PERI_BUS_1 */
712 };
713
714 /* ALIVE */
715 pinctrl_0: pinctrl@164B0000 {
716 compatible = "samsung,exynos8895-pinctrl";
717 reg = <0x0 0x164B0000 0x1000>;
718 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
719 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
720 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
721 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
722 wakeup-interrupt-controller {
723 compatible = "samsung,exynos7-wakeup-eint";
724 interrupt-parent = <&gic>;
725 interrupts = <0 16 0>;
726 };
727 };
728
729 /* A-BOX */
730 pinctrl_1: pinctrl@13E60000{
731 compatible = "samsung,exynos8895-pinctrl";
732 reg = <0x0 0x13E60000 0x1000>;
733 };
734
735 /* VTS */
736 pinctrl_2: pinctrl@14080000 {
737 compatible = "samsung,exynos8895-pinctrl";
738 reg = <0x0 0x14080000 0x1000>;
739 };
740
741 /* FSYS0 */
742 pinctrl_3: pinctrl@11050000 {
743 compatible = "samsung,exynos8895-pinctrl";
744 reg = <0x0 0x11050000 0x1000>;
745 interrupts = <0 335 0>;
746 };
747
748 /* FSYS1 */
749 pinctrl_4: pinctrl@11430000 {
750 compatible = "samsung,exynos8895-pinctrl";
751 reg = <0x0 0x11430000 0x1000>;
752 interrupts = <0 342 0>;
753 };
754
755 /* BUSC */
756 pinctrl_5: pinctrl@15A30000 {
757 compatible = "samsung,exynos8895-pinctrl";
758 reg = <0x0 0x15A30000 0x1000>;
759 interrupts = <0 103 0>;
760 };
761
762 /* PERIC0 */
763 pinctrl_6: pinctrl@104D0000 {
764 compatible = "samsung,exynos8895-pinctrl";
765 reg = <0x0 0x104D0000 0x1000>;
766 interrupts = <0 386 0>;
767 pinctrl-names = "default";
768 };
769
770 /* PERIC1 */
771 pinctrl_7: pinctrl@10980000 {
772 compatible = "samsung,exynos8895-pinctrl";
773 reg = <0x0 0x10980000 0x1000>;
774 interrupts = <0 430 0>;
775 };
776
777 mali: mali@13900000 {
778 compatible = "arm,mali";
779 reg = <0x0 0x13900000 0x5000>;
780 interrupts = <0 60 0>,
781 <0 61 0>,
782 <0 59 0>;
783 interrupt-names = "JOB", "MMU", "GPU";
784 g3d_cmu_cal_id = <ACPM_DVFS_G3D>;
785 samsung,power-domain = <&pd_g3d>;
786 g3d_genpd_name = "pd-g3d"; /*KC: pg-g3d, LT,MK: pd-embedded_g3d*/
787 #cooling-cells = <2>; /* min followed by max */
788 governor = "interactive";
789 interactive_info = <455000 95 0>;
790 gpu_dvfs_table_size = <9 7>; /*<row col>*/
791 gpu_dvfs_table = < 839000 98 100 1 1794000 1690000 0
792 764000 98 100 1 1794000 1690000 0
793 683000 98 100 1 1794000 1690000 0
794 572000 78 99 1 1794000 1690000 0
795 546000 78 99 1 1794000 1690000 2002000
796 455000 78 85 1 1540000 1456000 2002000
797 385000 78 85 1 1352000 1248000 0
798 338000 78 85 1 1014000 949000 0
799 260000 78 85 1 421000 0 0 >;
800 gpu_sustainable_info = <0 0 0 0 0>; /* Not used */
801 gpu_pmqos_cpu_cluster_num = <2>;
802 gpu_pmu_status_reg_offset = <0x40E4>;
803 gpu_pmu_status_local_pwr_mask = <0xF>; /*0xF << 0*/
804 gpu_max_clock = <546000>;
805 gpu_max_clock_limit = <546000>;
806 gpu_min_clock = <260000>;
807 gpu_dvfs_start_clock = <260000>;
808 gpu_dvfs_bl_config_clock = <260000>;
809 gpu_default_voltage = <800000>;
810 gpu_cold_minimum_vol = <0>;
811 gpu_voltage_offset_margin = <37500>;
812 gpu_tmu_control = <1>;
813 gpu_temp_throttling_level_num = <6>;
814 gpu_temp_throttling = <546000 455000 385000 338000 260000 260000>;
815 gpu_power_coeff = <625>;
816 gpu_dvfs_time_interval = <5>; /*1 tick : 10ms*/
817 gpu_default_wakeup_lock = <1>;
818 gpu_dynamic_abb = <0>;
819 gpu_early_clk_gating = <0>;
820 gpu_dvs = <0>;
821 gpu_inter_frame_pm = <1>;
822 gpu_perf_gathering = <0>;
823 gpu_runtime_pm_delay_time = <50>;
824 gpu_dvfs_polling_time = <30>;
825 gpu_pmqos_int_disable = <1>;
826 gpu_pmqos_mif_max_clock = <1794000>;
827 gpu_pmqos_mif_max_clock_base = <546000>;
828 gpu_cl_dvfs_start_base = <455000>;
829 gpu_debug_level = <3>; /*DEBUG(1) INFO(2) WARNING(3) ERROR(4)*/
830 gpu_trace_level = <8>; /*TRACE_ALL*/
831 gpu_mo_min_clock = <455000>;
832 gpu_boost_gpu_min_lock = <0>;
833 gpu_boost_egl_min_lock = <1872000>;
834 gpu_vk_boost_max_lock = <338000>;
835 gpu_vk_boost_mif_min_lock = <1794000>;
836 gpu_bts_support = <1>;
837 gpu_asv_cali_lock_val = <546000>; /*Should check this value when MALI_ASV_CALIBRATION_SUPPORT is enabled*/
838 gpu_set_pmu_duration_reg = <0x40F0>; /* only for KC for now*/
839 gpu_set_pmu_duration_val = <0xfffff363>; /* only for KC for now*/
840 };
841
842 ufs@0x11120000 {
843 /* ----------------------- */
844 /* 1. SYSTEM CONFIGURATION */
845 /* ----------------------- */
846 compatible ="samsung,exynos-ufs";
847 #address-cells = <2>;
848 #size-cells = <1>;
849 ranges;
850
851 reg =
852 <0x0 0x11120000 0x200>, /* 0: HCI standard */
853 <0x0 0x11121100 0x200>, /* 1: Vendor specificed */
854 <0x0 0x11110000 0x8000>, /* 2: UNIPRO */
855 <0x0 0x11130000 0x100>; /* 3: UFS protector */
856 interrupts = <0 334 0>;
857 pinctrl-names = "default";
858 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
859 clocks =
860 /* aclk clock */
861 <&clock GATE_UFS_EMBD>,
862 /* unipro clocks */
863 <&clock UFS_EMBD>;
864
865 clock-names =
866 /* aclk clocks */
867 "GATE_UFS_EMBD",
868 /* unipro clocks */
869 "UFS_EMBD";
870
871 /* PM QoS for INT power domain */
872 ufs-pm-qos-int = <400000>;
873
874 /* DMA coherent callback, should be coupled with 'ufs-sys' */
875 dma-coherent;
876
877 /* Alive block sfr for TCXO control */
878 samsung,pmu-phandle = <&pmu_system_controller>;
879
880 /* ----------------------- */
881 /* 2. UFS COMMON */
882 /* ----------------------- */
883 freq-table-hz = <0 0>, <0 0>;
884 pclk-freq-avail-range = <70000000 166000000>;
885
886 ufs,pmd-local-l2-timer = <8000 28000 20000>;
887 ufs,pmd-remote-l2-timer = <12000 32000 16000>;
888
889 vcc-supply = <&ufs_fixed_vcc>;
890 vcc-fixed-regulator;
891
892
893 /* ----------------------- */
894 /* 3. UFS EXYNOS */
895 /* ----------------------- */
896 hw-rev = <UFS_VER_0004>;
897
898 /* power mode change */
899 ufs,pmd-attr-mode = "FAST";
900 ufs,pmd-attr-lane = /bits/ 8 <2>;
901 ufs,pmd-attr-gear = /bits/ 8 <3>;
902 ufs,pmd-attr-hs-series = "HS_rate_b";
903
904 /* hiberantion */
905 ufs-rx-adv-fine-gran-sup_en = <0>;
906 ufs-rx-min-activate-time-cap = <3>;
907 ufs-rx-hibern8-time-cap = <2>;
908 ufs-tx-hibern8-time-cap = <2>;
909
910 /* misc table */
911 phy-init =
912 <0x9514 0x00 PMD_ALL UNIPRO_DBG_PRD>, //Unipro Clock Period
913 <0x200 0x40 PMD_ALL PHY_PCS_COMN>, //OV_TM On
914 <0x12 0x00 PMD_ALL PHY_PCS_RX_PRD>, //PCS RX Clock Period
915 <0xAA 0x00 PMD_ALL PHY_PCS_TX_PRD>, //PCS TX Clock Period
916 <0x5C 0x38 PMD_ALL PHY_PCS_RX>,
917 <0x0F 0x0 PMD_ALL PHY_PCS_RX>,
918 <0x65 0x01 PMD_ALL PHY_PCS_RX>, //PCS RX INT_H8_COUNT_CAP_ENABLE[0] = 1b'1(THIBERN8 CAPABILITY(200us))
919 <0x69 0x01 PMD_ALL PHY_PCS_RX>,
920 <0x21 0x00 PMD_ALL PHY_PCS_RX>,
921 <0x22 0x00 PMD_ALL PHY_PCS_RX>,
922 <0x84 0x01 PMD_ALL PHY_PCS_RX>,
923 <0x04 0x01 PMD_ALL PHY_PCS_TX>,
924 <0x200 0x0 PMD_ALL PHY_PCS_COMN>, //OV_TM Off
925 <0x9536 0x4E20 PMD_ALL UNIPRO_DBG_MIB>,
926 <0x9564 0x2e820183 PMD_ALL UNIPRO_DBG_MIB>, //DBG_PA_OPTION_SUITE
927 <0x155E 0x0 PMD_ALL UNIPRO_STD_MIB>, //LCC disable
928
929 <0x3000 0x0 PMD_ALL UNIPRO_STD_MIB>, //N_DeviceID
930 <0x3001 0x1 PMD_ALL UNIPRO_STD_MIB>, //N_DeviceID_valid
931 <0x4021 0x1 PMD_ALL UNIPRO_STD_MIB>, //T_PeerDeviceID
932
933 <0x4020 0x1 PMD_ALL UNIPRO_STD_MIB>, //T_ConnectionState
934
935 <0x8C 0x80 PMD_ALL PHY_PMA_COMN>,
936 <0x74 0x10 PMD_ALL PHY_PMA_COMN>, //CMN_1D(0x74), PWM clock generation selection: CMN_REG1D(0x10 = Refclk, 0x20 = int OSC)
937 <0x110 0xB5 PMD_ALL PHY_PMA_TRSV>, //TRSVx_14(0x110/0x250), TRSVx_REG14(RXAFE_DIFN_SQ_PULSE_REJ_EN = 1b'0)
938 <0x134 0x43 PMD_ALL PHY_PMA_TRSV>, //TRSVx_1D(0x134/0x274),
939 <0x16C 0x20 PMD_ALL PHY_PMA_TRSV>, //TRSVx_2B(0x16C/0x2AC),
940 <0x178 0xC0 PMD_ALL PHY_PMA_TRSV>, //TRSVx_2E(0x178/0x2B8),
941 <0xE0 0x12 PMD_ALL PHY_PMA_TRSV>,
942 <0x164 0x58 PMD_ALL PHY_PMA_TRSV>,
943 <0x8C 0xC0 PMD_ALL PHY_PMA_COMN>,
944 <0x8C 0x00 PMD_ALL PHY_PMA_COMN>,
945 <0x00 0xC8 PMD_ALL COMMON_WAIT>,
946 <0 0 0 0>;
947
948 post-phy-init =
949 <0x9529 0x1 PMD_ALL UNIPRO_DBG_MIB>, //Unipro Debug Mode On
950 <0x15A4 0xFA PMD_ALL UNIPRO_STD_MIB>, //PA_SaveConfigTime
951 <0x9529 0x0 PMD_ALL UNIPRO_DBG_MIB>, //Unipro Debug Mode Off
952 <0x200 0x40 PMD_ALL PHY_PCS_COMN>,
953 <0x35 0x05 PMD_ALL PHY_PCS_RX>,
954 <0x73 0x01 PMD_ALL PHY_PCS_RX>,
955 <0x41 0x02 PMD_ALL PHY_PCS_RX>,
956 <0x42 0xAC PMD_ALL PHY_PCS_RX>,
957 <0x200 0x0 PMD_ALL PHY_PCS_COMN>,
958 <0 0 0 0>;
959
960 calib-of-pwm =
961 <0x1569 0x0 PMD_PWM UNIPRO_STD_MIB>,
962 <0x1584 0x0 PMD_PWM UNIPRO_STD_MIB>,
963 <0x2041 8064 PMD_PWM UNIPRO_STD_MIB>,
964 <0x2042 28224 PMD_PWM UNIPRO_STD_MIB>,
965 <0x2043 20160 PMD_PWM UNIPRO_STD_MIB>,
966 <0x15B0 12000 PMD_PWM UNIPRO_STD_MIB>,
967 <0x15B1 32000 PMD_PWM UNIPRO_STD_MIB>,
968 <0x15B2 16000 PMD_PWM UNIPRO_STD_MIB>,
969 <0x7888 8064 PMD_PWM UNIPRO_DBG_APB>,
970 <0x788C 28224 PMD_PWM UNIPRO_DBG_APB>,
971 <0x7890 20160 PMD_PWM UNIPRO_DBG_APB>,
972 <0x78B8 12000 PMD_PWM UNIPRO_DBG_APB>,
973 <0x78BC 32000 PMD_PWM UNIPRO_DBG_APB>,
974 <0x78C0 16000 PMD_PWM UNIPRO_DBG_APB>,
975 /*MPHY tuning value*/
976 <0xC8 0x40 PMD_PWM PHY_PMA_TRSV>, //TRSVx_02(0xC8/0x208),
977 <0xF0 0x77 PMD_PWM PHY_PMA_TRSV>, //TRSVx_0c(0xF0/0x230), TX_SLEW_PREEMP_EN_CTRL_EN(bit3) = 1b'0
978 <0x120 0x80 PMD_PWM PHY_PMA_TRSV>, //TRSVx_18(0x120/0x260), TX_AMPL_CNTR_EN(bit6) = 1b'0
979 <0x128 0x00 PMD_PWM PHY_PMA_TRSV>, //TRSVx_1a(0x128/0x268), TX_AMPL_CTRL(bit[4:0], Amplitude) = 5b'00000(PWM)
980 <0x12C 0x00 PMD_PWM PHY_PMA_TRSV>, //TRSVx_1b(0x12C/0x26C), TX_PREEMP_CTRL(bit[5:4]) = 2b'00(0dB)
981 <0x134 0x43 PMD_PWM PHY_PMA_TRSV>, //TRSVx_1d(0x134/0x274), TX_AUX_CAP_INV_SEL(bit7) = 1b'0, TX_AUX_CAP_CTRL(bit[6:4]) = 3b'100
982 <0 0 0 0>;
983
984 calib-of-hs-rate-a =
985 <0x1569 0x1 PMD_HS UNIPRO_STD_MIB>,
986 <0x1584 0x1 PMD_HS UNIPRO_STD_MIB>,
987
988 <0x2041 8064 PMD_HS UNIPRO_STD_MIB>,
989 <0x2042 28224 PMD_HS UNIPRO_STD_MIB>,
990 <0x2043 20160 PMD_HS UNIPRO_STD_MIB>,
991 <0x15B0 12000 PMD_HS UNIPRO_STD_MIB>,
992 <0x15B1 32000 PMD_HS UNIPRO_STD_MIB>,
993 <0x15B2 16000 PMD_HS UNIPRO_STD_MIB>,
994
995 <0x7888 8064 PMD_HS UNIPRO_DBG_APB>,
996 <0x788C 28224 PMD_HS UNIPRO_DBG_APB>,
997 <0x7890 20160 PMD_HS UNIPRO_DBG_APB>,
998 <0x78B8 12000 PMD_HS UNIPRO_DBG_APB>,
999 <0x78BC 32000 PMD_HS UNIPRO_DBG_APB>,
1000 <0x78C0 16000 PMD_HS UNIPRO_DBG_APB>,
1001 /*MPHY tuning value*/
1002 <0xC8 0xBC PMD_HS PHY_PMA_TRSV>, //TRSVx_02(0xC8/0x208),
1003 <0xF0 0x7F PMD_HS PHY_PMA_TRSV>, //TRSVx_0c(0xF0/0x230), TX_SLEW_PREEMP_EN_CTRL_EN(bit3) = 1b'1
1004 <0x120 0xC0 PMD_HS PHY_PMA_TRSV>, //TRSVx_18(0x120/0x260), TX_AMPL_CNTR_EN(bit6) = 1b'1
1005 <0x128 0x08 PMD_HS_G1_L2 PHY_PMA_TRSV>, //TRSVx_1a(0x128/0x268), TX_AMPL_CTRL(bit[4:0], Amplitude) = 5b'01000(G1A/B)
1006 <0x128 0x02 PMD_HS_G2_L2 PHY_PMA_TRSV>, // TX_AMPL_CTRL(bit[4:0], Amplitude) = 5b'00010(G2A/B)
1007 <0x128 0x00 PMD_HS_G3_L2 PHY_PMA_TRSV>, // TX_AMPL_CTRL(bit[4:0], Amplitude) = 5b'00000(G3A/B)
1008 <0x12C 0x00 (PMD_HS_G1_L2|PMD_HS_G3_L2) PHY_PMA_TRSV>, // TX_PREEMP_CTRL(bit[5:4]) = 2b'00(0dB)
1009 <0x12C 0x00 PMD_HS_G2_L2 PHY_PMA_TRSV>, // TX_PREEMP_CTRL(bit[5:4]) = 2b'00(0dB, G2A/B))
1010 <0x134 0xd3 PMD_HS_G1_L2 PHY_PMA_TRSV>, //TRSVx_1d(0x134/0x274), TX_AUX_CAP_INV_SEL(bit7) = 1b'1, TX_AUX_CAP_CTRL(bit[6:4]) = 3b'101
1011 <0x134 0x73 PMD_HS_G2_L2 PHY_PMA_TRSV>, // TX_AUX_CAP_CTRL(bit[6:4]) = 3b'111
1012 <0x134 0x63 PMD_HS_G3_L2 PHY_PMA_TRSV>, // TX_AUX_CAP_CTRL(bit[6:4]) = 3b'110
1013
1014 <0x108 0x5D PMD_HS PHY_PMA_TRSV>, //
1015 <0x10C 0x90 PMD_HS PHY_PMA_TRSV>, //
1016 <0 0 0 0>;
1017
1018 calib-of-hs-rate-b =
1019 <0x1569 0x1 PMD_HS UNIPRO_STD_MIB>,
1020 <0x1584 0x1 PMD_HS UNIPRO_STD_MIB>,
1021
1022 <0x2041 8064 PMD_HS UNIPRO_STD_MIB>,
1023 <0x2042 28224 PMD_HS UNIPRO_STD_MIB>,
1024 <0x2043 20160 PMD_HS UNIPRO_STD_MIB>,
1025 <0x15B0 12000 PMD_HS UNIPRO_STD_MIB>,
1026 <0x15B1 32000 PMD_HS UNIPRO_STD_MIB>,
1027 <0x15B2 16000 PMD_HS UNIPRO_STD_MIB>,
1028
1029 <0x7888 8064 PMD_HS UNIPRO_DBG_APB>,
1030 <0x788C 28224 PMD_HS UNIPRO_DBG_APB>,
1031 <0x7890 20160 PMD_HS UNIPRO_DBG_APB>,
1032 <0x78B8 12000 PMD_HS UNIPRO_DBG_APB>,
1033 <0x78BC 32000 PMD_HS UNIPRO_DBG_APB>,
1034 <0x78C0 16000 PMD_HS UNIPRO_DBG_APB>,
1035 /*MPHY tuning value*/
1036 <0xC8 0xBC PMD_HS PHY_PMA_TRSV>, //TRSVx_02(0xC8/0x208),
1037 <0xF0 0x7F PMD_HS PHY_PMA_TRSV>, //TRSVx_0c(0xF0/0x230), TX_SLEW_PREEMP_EN_CTRL_EN(bit3) = 1b'1
1038 <0x120 0xC0 PMD_HS PHY_PMA_TRSV>, //TRSVx_18(0x120/0x260), TX_AMPL_CNTR_EN(bit6) = 1b'1
1039 <0x128 0x08 PMD_HS_G1_L2 PHY_PMA_TRSV>, //TRSVx_1a(0x128/0x268), TX_AMPL_CTRL(bit[4:0], Amplitude) = 5b'01000(G1A/B)
1040 <0x128 0x02 PMD_HS_G2_L2 PHY_PMA_TRSV>, // TX_AMPL_CTRL(bit[4:0], Amplitude) = 5b'00010(G2A/B)
1041 <0x128 0x00 PMD_HS_G3_L2 PHY_PMA_TRSV>, // TX_AMPL_CTRL(bit[4:0], Amplitude) = 5b'00000(G3A/B)
1042 <0x12C 0x00 (PMD_HS_G1_L2|PMD_HS_G3_L2) PHY_PMA_TRSV>, // TX_PREEMP_CTRL(bit[5:4]) = 2b'00(0dB)
1043 <0x12C 0x00 PMD_HS_G2_L2 PHY_PMA_TRSV>, // TX_PREEMP_CTRL(bit[5:4]) = 2b'00(0dB, G2A/B))
1044 <0x134 0xd3 PMD_HS_G1_L2 PHY_PMA_TRSV>, //TRSVx_1d(0x134/0x274), TX_AUX_CAP_INV_SEL(bit7) = 1b'1, TX_AUX_CAP_CTRL(bit[6:4]) = 3b'101
1045 <0x134 0x73 PMD_HS_G2_L2 PHY_PMA_TRSV>, // TX_AUX_CAP_CTRL(bit[6:4]) = 3b'111
1046 <0x134 0x63 PMD_HS_G3_L2 PHY_PMA_TRSV>, //
1047
1048 <0x108 0x5D PMD_HS PHY_PMA_TRSV>, //
1049 <0x10C 0x90 PMD_HS PHY_PMA_TRSV>, //
1050 <0 0 0 0>;
1051
1052 post-calib-of-pwm =
1053 <0 0 0 0>;
1054
1055 post-calib-of-hs-rate-a =
1056 <0x1fc 0x01 PMD_HS PHY_CDR_WAIT>,
1057 <0 0 0 0>;
1058
1059 post-calib-of-hs-rate-b =
1060 <0x1fc 0x01 PMD_HS PHY_CDR_WAIT>,
1061 <0 0 0 0>;
1062
1063 lpa-restore =
1064 <0 0 0 0>;
1065
1066 pre-clk-off =
1067 /* SQ off */
1068 <0x0C4 0x99 PMD_ALL PHY_PMA_TRSV>,
1069 <0x0E8 0x7F PMD_ALL PHY_PMA_TRSV>,
1070 <0x004 0x02 PMD_ALL PHY_PMA_COMN>,
1071 <0 0 0 0>;
1072
1073 post-clk-on =
1074 /* SQ on */
1075 <0x004 0x00 PMD_ALL PHY_PMA_COMN>,
1076 <0x0C4 0xD9 PMD_ALL PHY_PMA_TRSV>,
1077 <0x0E8 0x77 PMD_ALL PHY_PMA_TRSV>,
1078 <0 0 0 0>;
1079
1080 lane1-sq-off =
1081 /* SQ off only for 1lane */
1082 <0x0C4 0x19 PMD_ALL PHY_PMA_TRSV_LANE1_SQ_OFF>,
1083 <0x0E8 0xFF PMD_ALL PHY_PMA_TRSV_LANE1_SQ_OFF>,
1084 <0 0 0 0>;
1085
1086 /* ----------------------- */
1087 /* 4. ADDITIONAL NODES */
1088 /* ----------------------- */
1089 /* PHY isolation */
1090 ufs-phy {
1091 #address-cells = <2>;
1092 #size-cells = <1>;
1093 ranges;
1094 reg = <0x0 0x11124000 0x800>;
1095
1096 ufs-phy-sys {
1097 reg = <0x0 0x16480724 0x4>;
1098 };
1099 };
1100
1101 /* SYSREG */
1102 ufs-io-coherency {
1103 #address-cells = <2>;
1104 #size-cells = <1>;
1105 ranges;
1106
1107 reg =
1108 <0x0 0x11020700 0x4>;
1109
1110 mask = <(BIT_8 | BIT_9)>;
1111 bits = <(BIT_8 | BIT_9)>;
1112 };
1113
1114 ufs-tcxo-sel {
1115 #address-cells = <2>;
1116 #size-cells = <1>;
1117 ranges;
1118
1119 reg =
1120 <0x0 0x11021150 0x4>;
1121
1122 mask = <BIT_0>;
1123 bits = <BIT_0>; // use alternative
1124 };
1125 };
1126
1127 ufs_fixed_vcc: fixedregulator@0 {
1128 compatible = "regulator-fixed";
1129 regulator-name = "ufs-vcc";
1130 gpio = <&gpg0 0 0>;
1131 regulator-boot-on;
1132 enable-active-high;
1133 };
1134
1135 /* UART_DBG */
1136 serial_0: uart@10430000 {
1137 compatible = "samsung,exynos-uart";
1138 samsung,separate-uart-clk;
1139 reg = <0x0 0x10430000 0x100>;
1140 samsung,fifo-size = <256>;
1141 interrupts = <0 385 0>;
1142 pinctrl-names = "default";
1143 pinctrl-0 = <&uart0_bus>;
1144 clocks = <&clock GATE_UART_DBG>, <&clock UART_DBG>;
1145 clock-names = "gate_pclk0", "gate_uart0";
1146 status = "disabled";
1147 };
1148
1149 /* UART_BT */
1150 serial_1: uart@10830000 {
1151 compatible = "samsung,exynos-uart";
1152 samsung,separate-uart-clk;
1153 reg = <0x0 0x10830000 0x100>;
1154 samsung,fifo-size = <256>;
1155 interrupts = <0 389 0>;
1156 pinctrl-names = "btdefault", "btsleep";
1157 pinctrl-0 = <&uart1_default>;
1158 pinctrl-1 = <&uart1_btsleep>;
1159 clocks = <&clock GATE_UART_BT>, <&clock UART_BT>;
1160 clock-names = "gate_pclk1", "gate_uart1";
1161 status = "okay";
1162 };
1163
1164 /* USI0_UART */
1165 serial_2: uart@10440000 {
1166 compatible = "samsung,exynos-uart";
1167 samsung,separate-uart-clk;
1168 reg = <0x0 0x10440000 0x100>;
1169 samsung,fifo-size = <64>;
1170 interrupts = <0 366 0>;
1171 pinctrl-names = "default";
1172 pinctrl-0 = <&uart2_bus_single>; /* or <&uart2_bus_dual> */
1173 clocks = <&clock GATE_USI00>, <&clock USI00>;
1174 clock-names = "gate_pclk2", "gate_uart2";
1175 status = "disabled";
1176 };
1177
1178 /* USI1_UART */
1179 serial_3: uart@10460000 {
1180 compatible = "samsung,exynos-uart";
1181 samsung,separate-uart-clk;
1182 reg = <0x0 0x10460000 0x100>;
1183 samsung,fifo-size = <64>;
1184 interrupts = <0 370 0>;
1185 pinctrl-names = "default";
1186 pinctrl-0 = <&uart3_bus_single>; /* or <&uart3_bus_dual> */
1187 clocks = <&clock GATE_USI01>, <&clock USI01>;
1188 clock-names = "gate_pclk3", "gate_uart3";
1189 status = "disabled";
1190 };
1191
1192 /* USI2_UART */
1193 serial_4: uart@10480000 {
1194 compatible = "samsung,exynos-uart";
1195 samsung,separate-uart-clk;
1196 reg = <0x0 0x10480000 0x100>;
1197 samsung,fifo-size = <64>;
1198 interrupts = <0 374 0>;
1199 pinctrl-names = "default";
1200 pinctrl-0 = <&uart4_bus_single>; /* or <&uart4_bus_dual> */
1201 clocks = <&clock GATE_USI02>, <&clock USI02>;
1202 clock-names = "gate_pclk4", "gate_uart4";
1203 status = "disabled";
1204 };
1205
1206 /* USI3_UART */
1207 serial_5: uart@104A0000 {
1208 compatible = "samsung,exynos-uart";
1209 samsung,separate-uart-clk;
1210 reg = <0x0 0x104A0000 0x100>;
1211 samsung,fifo-size = <64>;
1212 interrupts = <0 378 0>;
1213 pinctrl-names = "default";
1214 pinctrl-0 = <&uart5_bus_single>; /* or <&uart5_bus_dual> */
1215 clocks = <&clock GATE_USI03>, <&clock USI03>;
1216 clock-names = "gate_pclk5", "gate_uart5";
1217 status = "disabled";
1218 };
1219
1220 /* USI4_UART */
1221 serial_6: uart@10840000 {
1222 compatible = "samsung,exynos-uart";
1223 samsung,separate-uart-clk;
1224 reg = <0x0 0x10840000 0x100>;
1225 samsung,fifo-size = <64>;
1226 interrupts = <0 392 0>;
1227 pinctrl-names = "default";
1228 pinctrl-0 = <&uart6_bus_single>; /* or <&uart6_bus_dual> */
1229 clocks = <&clock GATE_USI04>, <&clock USI04>;
1230 clock-names = "gate_pclk6", "gate_uart6";
1231 status = "disabled";
1232 };
1233
1234 /* USI5_UART */
1235 serial_7: uart@10860000 {
1236 compatible = "samsung,exynos-uart";
1237 samsung,separate-uart-clk;
1238 reg = <0x0 0x10860000 0x100>;
1239 samsung,fifo-size = <64>;
1240 interrupts = <0 396 0>;
1241 pinctrl-names = "default";
1242 pinctrl-0 = <&uart7_bus_single>; /* or <&uart7_bus_dual> */
1243 clocks = <&clock GATE_USI05>, <&clock USI05>;
1244 clock-names = "gate_pclk7", "gate_uart7";
1245 status = "disabled";
1246 };
1247
1248 /* USI6_UART */
1249 serial_8: uart@10880000 {
1250 compatible = "samsung,exynos-uart";
1251 samsung,separate-uart-clk;
1252 reg = <0x0 0x10880000 0x100>;
1253 samsung,fifo-size = <64>;
1254 interrupts = <0 400 0>;
1255 pinctrl-names = "default";
1256 pinctrl-0 = <&uart8_bus_single>; /* or <&uart8_bus_dual> */
1257 clocks = <&clock GATE_USI06>, <&clock USI06>;
1258 clock-names = "gate_pclk8", "gate_uart8";
1259 status = "disabled";
1260 };
1261
1262 /* USI7_UART */
1263 serial_9: uart@108A0000 {
1264 compatible = "samsung,exynos-uart";
1265 samsung,separate-uart-clk;
1266 reg = <0x0 0x108A0000 0x100>;
1267 samsung,fifo-size = <64>;
1268 interrupts = <0 404 0>;
1269 pinctrl-names = "default";
1270 pinctrl-0 = <&uart9_bus_single>; /* or <&uart9_bus_dual> */
1271 clocks = <&clock GATE_USI07>, <&clock USI07>;
1272 clock-names = "gate_pclk9", "gate_uart9";
1273 status = "disabled";
1274 };
1275
1276 /* USI8_UART */
1277 serial_10: uart@108C0000 {
1278 compatible = "samsung,exynos-uart";
1279 samsung,separate-uart-clk;
1280 reg = <0x0 0x108C0000 0x100>;
1281 samsung,fifo-size = <64>;
1282 interrupts = <0 408 0>;
1283 pinctrl-names = "default";
1284 pinctrl-0 = <&uart10_bus_single>; /* or <&uart10_bus_dual> */
1285 clocks = <&clock GATE_USI08>, <&clock USI08>;
1286 clock-names = "gate_pclk10", "gate_uart10";
1287 status = "disabled";
1288 };
1289
1290 /* USI9_UART */
1291 serial_11: uart@108E0000 {
1292 compatible = "samsung,exynos-uart";
1293 samsung,separate-uart-clk;
1294 reg = <0x0 0x108E0000 0x100>;
1295 samsung,fifo-size = <64>;
1296 interrupts = <0 412 0>;
1297 pinctrl-names = "default";
1298 pinctrl-0 = <&uart11_bus_single>; /* or <&uart11_bus_dual> */
1299 clocks = <&clock GATE_USI09>, <&clock USI09>;
1300 clock-names = "gate_pclk11", "gate_uart11";
1301 status = "disabled";
1302 };
1303
1304 /* USI10_UART */
1305 serial_12: uart@10900000 {
1306 compatible = "samsung,exynos-uart";
1307 samsung,separate-uart-clk;
1308 reg = <0x0 0x10900000 0x100>;
1309 samsung,fifo-size = <64>;
1310 interrupts = <0 416 0>;
1311 pinctrl-names = "default";
1312 pinctrl-0 = <&uart12_bus_single>; /* or <&uart12_bus_dual> */
1313 clocks = <&clock GATE_USI10>, <&clock USI10>;
1314 clock-names = "gate_pclk12", "gate_uart12";
1315 status = "disabled";
1316 };
1317
1318 /* USI11_UART */
1319 serial_13: uart@10920000 {
1320 compatible = "samsung,exynos-uart";
1321 samsung,separate-uart-clk;
1322 reg = <0x0 0x10920000 0x100>;
1323 samsung,fifo-size = <64>;
1324 interrupts = <0 420 0>;
1325 pinctrl-names = "default";
1326 pinctrl-0 = <&uart13_bus_single>; /* or <&uart13_bus_dual> */
1327 clocks = <&clock GATE_USI11>, <&clock USI11>;
1328 clock-names = "gate_pclk13", "gate_uart13";
1329 status = "disabled";
1330 };
1331
1332 /* USI12_UART */
1333 serial_14: uart@10940000 {
1334 compatible = "samsung,exynos-uart";
1335 samsung,separate-uart-clk;
1336 reg = <0x0 0x10940000 0x100>;
1337 samsung,fifo-size = <64>;
1338 interrupts = <0 424 0>;
1339 pinctrl-names = "default";
1340 pinctrl-0 = <&uart14_bus_single>; /* or <&uart14_bus_dual> */
1341 clocks = <&clock GATE_USI12>, <&clock USI12>;
1342 clock-names = "gate_pclk14", "gate_uart14";
1343 status = "disabled";
1344 };
1345
1346
1347 /* USI13_UART */
1348 serial_15: uart@10960000 {
1349 compatible = "samsung,exynos-uart";
1350 samsung,separate-uart-clk;
1351 reg = <0x0 0x10960000 0x100>;
1352 samsung,fifo-size = <64>;
1353 interrupts = <0 428 0>;
1354 pinctrl-names = "default";
1355 pinctrl-0 = <&uart15_bus_single>; /* or <&uart15_bus_dual> */
1356 clocks = <&clock GATE_USI13>, <&clock USI13>;
1357 clock-names = "gate_pclk15", "gate_uart15";
1358 status = "disabled";
1359 };
1360
1361 /* USI_0 */
1362 usi_0: usi@10421000 {
1363 compatible = "samsung,exynos-usi";
1364 reg = <0x0 0x10421000 0x4>;
1365 /* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
1366 or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
1367 status = "disabled";
1368 };
1369
1370 /* USI_1 */
1371 usi_1: usi@10421004 {
1372 compatible = "samsung,exynos-usi";
1373 reg = <0x0 0x10421004 0x4>;
1374 /* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
1375 or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
1376 status = "disabled";
1377 };
1378
1379 /* USI_2 */
1380 usi_2: usi@10421008 {
1381 compatible = "samsung,exynos-usi";
1382 reg = <0x0 0x10421008 0x4>;
1383 /* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
1384 or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
1385 status = "disabled";
1386 };
1387
1388 /* USI_3 */
1389 usi_3: usi@1042100C {
1390 compatible = "samsung,exynos-usi";
1391 reg = <0x0 0x1042100C 0x4>;
1392 /* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
1393 or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
1394 status = "disabled";
1395 };
1396
1397 /* USI_4 */
1398 usi_4: usi@10821008 {
1399 compatible = "samsung,exynos-usi";
1400 reg = <0x0 0x10821008 0x4>;
1401 /* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
1402 or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
1403 status = "disabled";
1404 };
1405
1406 /* USI_5 */
1407 usi_5: usi@1082100C {
1408 compatible = "samsung,exynos-usi";
1409 reg = <0x0 0x1082100C 0x4>;
1410 /* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
1411 or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
1412 status = "disabled";
1413 };
1414
1415 /* USI_6 */
1416 usi_6: usi@10821010 {
1417 compatible = "samsung,exynos-usi";
1418 reg = <0x0 0x10821010 0x4>;
1419 /* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
1420 or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
1421 status = "disabled";
1422 };
1423
1424 /* USI_7 */
1425 usi_7: usi@10821014 {
1426 compatible = "samsung,exynos-usi";
1427 reg = <0x0 0x10821014 0x4>;
1428 /* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
1429 or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
1430 status = "disabled";
1431 };
1432
1433 /* USI_8 */
1434 usi_8: usi@10821018 {
1435 compatible = "samsung,exynos-usi";
1436 reg = <0x0 0x10821018 0x4>;
1437 /* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
1438 or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
1439 status = "disabled";
1440 };
1441
1442 /* USI_9 */
1443 usi_9: usi@1082101C {
1444 compatible = "samsung,exynos-usi";
1445 reg = <0x0 0x1082101C 0x4>;
1446 /* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
1447 or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
1448 status = "disabled";
1449 };
1450
1451 /* USI_10 */
1452 usi_10: usi@10821020 {
1453 compatible = "samsung,exynos-usi";
1454 reg = <0x0 0x10821020 0x4>;
1455 /* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
1456 or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
1457 status = "disabled";
1458 };
1459
1460 /* USI_11 */
1461 usi_11: usi@10821024 {
1462 compatible = "samsung,exynos-usi";
1463 reg = <0x0 0x10821024 0x4>;
1464 /* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
1465 or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
1466 status = "disabled";
1467 };
1468
1469 /* USI_12 */
1470 usi_12: usi@10821028 {
1471 compatible = "samsung,exynos-usi";
1472 reg = <0x0 0x10821028 0x4>;
1473 /* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
1474 or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
1475 status = "disabled";
1476 };
1477
1478 /* USI_13 */
1479 usi_13: usi@1082102C {
1480 compatible = "samsung,exynos-usi";
1481 reg = <0x0 0x1082102C 0x4>;
1482 /* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
1483 or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
1484 status = "disabled";
1485 };
1486
1487 /* HSI2C_PMIC */
1488 hsi2c_0: hsi2c@15BC0000 {
1489 compatible = "samsung,exynos5-hsi2c";
1490 samsung,check-transdone-int;
1491 reg = <0x0 0x15BC0000 0x1000>;
1492 interrupts = <0 113 0>;
1493 #address-cells = <1>;
1494 #size-cells = <0>;
1495 pinctrl-names = "default";
1496 pinctrl-0 = <&hsi2c0_bus>;
1497 clocks = <&clock UMUX_CLKCMU_BUSC_BUSPHSI2C>, <&clock GATE_HSI2CDF>;
1498 clock-names = "rate_hsi2c", "gate_hsi2c";
1499 samsung,scl-clk-stretching;
1500 gpio_sda= <&gpb2 0 0x1>;
1501 gpio_scl= <&gpb2 1 0x1>;
1502 status = "disabled";
1503 };
1504
1505 /* HSI2C_CAM0 */
1506 hsi2c_1: hsi2c@10990000 {
1507 compatible = "samsung,exynos5-hsi2c";
1508 samsung,check-transdone-int;
1509 reg = <0x0 0x10990000 0x1000>;
1510 interrupts = <0 431 0>;
1511 #address-cells = <1>;
1512 #size-cells = <0>;
1513 pinctrl-names = "default";
1514 pinctrl-0 = <&hsi2c1_bus>;
1515 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_HSI2C_CAM0>;
1516 clock-names = "rate_hsi2c", "gate_hsi2c";
1517 samsung,scl-clk-stretching;
1518 gpio_sda= <&gpc2 0 0x1>;
1519 gpio_scl= <&gpc2 1 0x1>;
1520 status = "disabled";
1521 };
1522
1523 /* HSI2C_CAM1 */
1524 hsi2c_2: hsi2c@109A0000 {
1525 compatible = "samsung,exynos5-hsi2c";
1526 samsung,check-transdone-int;
1527 reg = <0x0 0x109A0000 0x1000>;
1528 interrupts = <0 432 0>;
1529 #address-cells = <1>;
1530 #size-cells = <0>;
1531 pinctrl-names = "default";
1532 pinctrl-0 = <&hsi2c2_bus>;
1533 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_HSI2C_CAM1>;
1534 clock-names = "rate_hsi2c", "gate_hsi2c";
1535 samsung,scl-clk-stretching;
1536 gpio_sda= <&gpc2 2 0x1>;
1537 gpio_scl= <&gpc2 3 0x1>;
1538 status = "disabled";
1539 };
1540
1541 /* HSI2C_CAM2 */
1542 hsi2c_3: hsi2c@109B0000 {
1543 compatible = "samsung,exynos5-hsi2c";
1544 samsung,check-transdone-int;
1545 reg = <0x0 0x109B0000 0x1000>;
1546 interrupts = <0 433 0>;
1547 #address-cells = <1>;
1548 #size-cells = <0>;
1549 pinctrl-names = "default";
1550 pinctrl-0 = <&hsi2c3_bus>;
1551 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_HSI2C_CAM2>;
1552 clock-names = "rate_hsi2c", "gate_hsi2c";
1553 samsung,scl-clk-stretching;
1554 gpio_sda= <&gpc2 4 0x1>;
1555 gpio_scl= <&gpc2 5 0x1>;
1556 status = "disabled";
1557 };
1558
1559 /* HSI2C_CAM3 */
1560 hsi2c_4: hsi2c@109C0000 {
1561 compatible = "samsung,exynos5-hsi2c";
1562 samsung,check-transdone-int;
1563 reg = <0x0 0x109C0000 0x1000>;
1564 interrupts = <0 434 0>;
1565 #address-cells = <1>;
1566 #size-cells = <0>;
1567 pinctrl-names = "default";
1568 pinctrl-0 = <&hsi2c4_bus>;
1569 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_HSI2C_CAM3>;
1570 clock-names = "rate_hsi2c", "gate_hsi2c";
1571 samsung,scl-clk-stretching;
1572 gpio_sda= <&gpc2 6 0x1>;
1573 gpio_scl= <&gpc2 7 0x1>;
1574 status = "disabled";
1575 };
1576
1577 /* HSI2C_USI0_0 */
1578 hsi2c_5: hsi2c@10440000 {
1579 compatible = "samsung,exynos5-hsi2c";
1580 samsung,check-transdone-int;
1581 reg = <0x0 0x10440000 0x1000>;
1582 interrupts = <0 364 0>;
1583 #address-cells = <1>;
1584 #size-cells = <0>;
1585 pinctrl-names = "default";
1586 pinctrl-0 = <&hsi2c5_bus>;
1587 clocks = <&clock UMUX_CLKCMU_PERIC0_BUS>, <&clock GATE_USI00>;
1588 clock-names = "rate_hsi2c", "gate_hsi2c";
1589 samsung,scl-clk-stretching;
1590 gpio_sda= <&gpd1 0 0x1>;
1591 gpio_scl= <&gpd1 1 0x1>;
1592 status = "disabled";
1593 };
1594
1595 /* HSI2C_USI0_1 */
1596 hsi2c_6: hsi2c@10450000 {
1597 compatible = "samsung,exynos5-hsi2c";
1598 samsung,check-transdone-int;
1599 reg = <0x0 0x10450000 0x1000>;
1600 interrupts = <0 365 0>;
1601 #address-cells = <1>;
1602 #size-cells = <0>;
1603 pinctrl-names = "default";
1604 pinctrl-0 = <&hsi2c6_bus>;
1605 clocks = <&clock UMUX_CLKCMU_PERIC0_BUS>, <&clock GATE_USI00>;
1606 clock-names = "rate_hsi2c", "gate_hsi2c";
1607 samsung,scl-clk-stretching;
1608 gpio_sda= <&gpd1 2 0x1>;
1609 gpio_scl= <&gpd1 3 0x1>;
1610 status = "disabled";
1611 };
1612
1613 /* HSI2C_USI1_0 */
1614 hsi2c_7: hsi2c@10460000 {
1615 compatible = "samsung,exynos5-hsi2c";
1616 samsung,check-transdone-int;
1617 reg = <0x0 0x10460000 0x1000>;
1618 interrupts = <0 368 0>;
1619 #address-cells = <1>;
1620 #size-cells = <0>;
1621 pinctrl-names = "default";
1622 pinctrl-0 = <&hsi2c7_bus>;
1623 clocks = <&clock UMUX_CLKCMU_PERIC0_BUS>, <&clock GATE_USI01>;
1624 clock-names = "rate_hsi2c", "gate_hsi2c";
1625 samsung,scl-clk-stretching;
1626 gpio_sda= <&gpd1 4 0x1>;
1627 gpio_scl= <&gpd1 5 0x1>;
1628 status = "disabled";
1629 };
1630
1631 /* HSI2C_USI1_1 */
1632 hsi2c_8: hsi2c@10470000 {
1633 compatible = "samsung,exynos5-hsi2c";
1634 samsung,check-transdone-int;
1635 reg = <0x0 0x10470000 0x1000>;
1636 interrupts = <0 369 0>;
1637 #address-cells = <1>;
1638 #size-cells = <0>;
1639 pinctrl-names = "default";
1640 pinctrl-0 = <&hsi2c8_bus>;
1641 clocks = <&clock UMUX_CLKCMU_PERIC0_BUS>, <&clock GATE_USI01>;
1642 clock-names = "rate_hsi2c", "gate_hsi2c";
1643 samsung,scl-clk-stretching;
1644 gpio_sda= <&gpd1 6 0x1>;
1645 gpio_scl= <&gpd1 7 0x1>;
1646 status = "disabled";
1647 };
1648
1649 /* HSI2C_USI2_0 */
1650 hsi2c_9: hsi2c@10480000 {
1651 compatible = "samsung,exynos5-hsi2c";
1652 samsung,check-transdone-int;
1653 reg = <0x0 0x10480000 0x1000>;
1654 interrupts = <0 372 0>;
1655 #address-cells = <1>;
1656 #size-cells = <0>;
1657 pinctrl-names = "default";
1658 pinctrl-0 = <&hsi2c9_bus>;
1659 clocks = <&clock UMUX_CLKCMU_PERIC0_BUS>, <&clock GATE_USI02>;
1660 clock-names = "rate_hsi2c", "gate_hsi2c";
1661 samsung,scl-clk-stretching;
1662 gpio_sda= <&gpd2 0 0x1>;
1663 gpio_scl= <&gpd2 1 0x1>;
1664 status = "disabled";
1665 };
1666
1667 /* HSI2C_USI2_1 */
1668 hsi2c_10: hsi2c@10490000 {
1669 compatible = "samsung,exynos5-hsi2c";
1670 samsung,check-transdone-int;
1671 reg = <0x0 0x10490000 0x1000>;
1672 interrupts = <0 373 0>;
1673 #address-cells = <1>;
1674 #size-cells = <0>;
1675 pinctrl-names = "default";
1676 pinctrl-0 = <&hsi2c10_bus>;
1677 clocks = <&clock UMUX_CLKCMU_PERIC0_BUS>, <&clock GATE_USI02>;
1678 clock-names = "rate_hsi2c", "gate_hsi2c";
1679 samsung,scl-clk-stretching;
1680 gpio_sda= <&gpd2 2 0x1>;
1681 gpio_scl= <&gpd2 3 0x1>;
1682 status = "disabled";
1683 };
1684
1685 /* HSI2C_USI3_0 */
1686 hsi2c_11: hsi2c@104A0000 {
1687 compatible = "samsung,exynos5-hsi2c";
1688 samsung,check-transdone-int;
1689 reg = <0x0 0x104A0000 0x1000>;
1690 interrupts = <0 376 0>;
1691 #address-cells = <1>;
1692 #size-cells = <0>;
1693 pinctrl-names = "default";
1694 pinctrl-0 = <&hsi2c11_bus>;
1695 clocks = <&clock UMUX_CLKCMU_PERIC0_BUS>, <&clock GATE_USI03>;
1696 clock-names = "rate_hsi2c", "gate_hsi2c";
1697 samsung,scl-clk-stretching;
1698 gpio_sda= <&gpd3 0 0x1>;
1699 gpio_scl= <&gpd3 1 0x1>;
1700 status = "disabled";
1701 };
1702
1703 /* HSI2C_USI3_1 */
1704 hsi2c_12: hsi2c@104B0000 {
1705 compatible = "samsung,exynos5-hsi2c";
1706 samsung,check-transdone-int;
1707 reg = <0x0 0x104B0000 0x1000>;
1708 interrupts = <0 377 0>;
1709 #address-cells = <1>;
1710 #size-cells = <0>;
1711 pinctrl-names = "default";
1712 pinctrl-0 = <&hsi2c12_bus>;
1713 clocks = <&clock UMUX_CLKCMU_PERIC0_BUS>, <&clock GATE_USI03>;
1714 clock-names = "rate_hsi2c", "gate_hsi2c";
1715 samsung,scl-clk-stretching;
1716 gpio_sda= <&gpd3 2 0x1>;
1717 gpio_scl= <&gpd3 3 0x1>;
1718 status = "disabled";
1719 };
1720
1721 /* HSI2C_USI4_0 */
1722 hsi2c_13: hsi2c@10840000 {
1723 compatible = "samsung,exynos5-hsi2c";
1724 samsung,check-transdone-int;
1725 reg = <0x0 0x10840000 0x1000>;
1726 interrupts = <0 390 0>;
1727 #address-cells = <1>;
1728 #size-cells = <0>;
1729 pinctrl-names = "default";
1730 pinctrl-0 = <&hsi2c13_bus>;
1731 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI04>;
1732 clock-names = "rate_hsi2c", "gate_hsi2c";
1733 samsung,scl-clk-stretching;
1734 gpio_sda= <&gpe5 0 0x1>;
1735 gpio_scl= <&gpe5 1 0x1>;
1736 status = "disabled";
1737 };
1738
1739 /* HSI2C_USI4_1 */
1740 hsi2c_14: hsi2c@10850000 {
1741 compatible = "samsung,exynos5-hsi2c";
1742 samsung,check-transdone-int;
1743 reg = <0x0 0x10850000 0x1000>;
1744 interrupts = <0 391 0>;
1745 #address-cells = <1>;
1746 #size-cells = <0>;
1747 pinctrl-names = "default";
1748 pinctrl-0 = <&hsi2c14_bus>;
1749 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI04>;
1750 clock-names = "rate_hsi2c", "gate_hsi2c";
1751 samsung,scl-clk-stretching;
1752 gpio_sda= <&gpe5 2 0x1>;
1753 gpio_scl= <&gpe5 3 0x1>;
1754 status = "disabled";
1755 };
1756
1757 /* HSI2C_USI5_0 */
1758 hsi2c_15: hsi2c@10860000 {
1759 compatible = "samsung,exynos5-hsi2c";
1760 samsung,check-transdone-int;
1761 reg = <0x0 0x10860000 0x1000>;
1762 interrupts = <0 394 0>;
1763 #address-cells = <1>;
1764 #size-cells = <0>;
1765 pinctrl-names = "default";
1766 pinctrl-0 = <&hsi2c15_bus>;
1767 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI05>;
1768 clock-names = "rate_hsi2c", "gate_hsi2c";
1769 samsung,scl-clk-stretching;
1770 gpio_sda= <&gpe1 0 0x1>;
1771 gpio_scl= <&gpe1 1 0x1>;
1772 status = "disabled";
1773 };
1774
1775 /* HSI2C_USI5_1 */
1776 hsi2c_16: hsi2c@10870000 {
1777 compatible = "samsung,exynos5-hsi2c";
1778 samsung,check-transdone-int;
1779 reg = <0x0 0x10870000 0x1000>;
1780 interrupts = <0 395 0>;
1781 #address-cells = <1>;
1782 #size-cells = <0>;
1783 pinctrl-names = "default";
1784 pinctrl-0 = <&hsi2c16_bus>;
1785 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI05>;
1786 clock-names = "rate_hsi2c", "gate_hsi2c";
1787 samsung,scl-clk-stretching;
1788 gpio_sda= <&gpe1 2 0x1>;
1789 gpio_scl= <&gpe1 3 0x1>;
1790 status = "disabled";
1791 };
1792
1793 /* HSI2C_USI6_0 */
1794 hsi2c_17: hsi2c@10880000 {
1795 compatible = "samsung,exynos5-hsi2c";
1796 samsung,check-transdone-int;
1797 reg = <0x0 0x10880000 0x1000>;
1798 interrupts = <0 398 0>;
1799 #address-cells = <1>;
1800 #size-cells = <0>;
1801 pinctrl-names = "default";
1802 pinctrl-0 = <&hsi2c17_bus>;
1803 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI06>;
1804 clock-names = "rate_hsi2c", "gate_hsi2c";
1805 samsung,scl-clk-stretching;
1806 gpio_sda= <&gpe1 4 0x1>;
1807 gpio_scl= <&gpe1 5 0x1>;
1808 status = "disabled";
1809 };
1810
1811 /* HSI2C_USI6_1 */
1812 hsi2c_18: hsi2c@10890000 {
1813 compatible = "samsung,exynos5-hsi2c";
1814 samsung,check-transdone-int;
1815 reg = <0x0 0x10890000 0x1000>;
1816 interrupts = <0 399 0>;
1817 #address-cells = <1>;
1818 #size-cells = <0>;
1819 pinctrl-names = "default";
1820 pinctrl-0 = <&hsi2c18_bus>;
1821 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI06>;
1822 clock-names = "rate_hsi2c", "gate_hsi2c";
1823 samsung,scl-clk-stretching;
1824 gpio_sda= <&gpe1 6 0x1>;
1825 gpio_scl= <&gpe1 7 0x1>;
1826 status = "disabled";
1827 };
1828
1829 /* HSI2C_USI7_0 */
1830 hsi2c_19: hsi2c@108A0000 {
1831 compatible = "samsung,exynos5-hsi2c";
1832 samsung,check-transdone-int;
1833 reg = <0x0 0x108A0000 0x1000>;
1834 interrupts = <0 402 0>;
1835 #address-cells = <1>;
1836 #size-cells = <0>;
1837 pinctrl-names = "default";
1838 pinctrl-0 = <&hsi2c19_bus>;
1839 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI07>;
1840 clock-names = "rate_hsi2c", "gate_hsi2c";
1841 samsung,scl-clk-stretching;
1842 gpio_sda= <&gpe2 0 0x1>;
1843 gpio_scl= <&gpe2 1 0x1>;
1844 status = "disabled";
1845 };
1846
1847 /* HSI2C_USI7_1 */
1848 hsi2c_20: hsi2c@108B0000 {
1849 compatible = "samsung,exynos5-hsi2c";
1850 samsung,check-transdone-int;
1851 reg = <0x0 0x108B0000 0x1000>;
1852 interrupts = <0 403 0>;
1853 #address-cells = <1>;
1854 #size-cells = <0>;
1855 pinctrl-names = "default";
1856 pinctrl-0 = <&hsi2c20_bus>;
1857 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI07>;
1858 clock-names = "rate_hsi2c", "gate_hsi2c";
1859 samsung,scl-clk-stretching;
1860 gpio_sda= <&gpe2 2 0x1>;
1861 gpio_scl= <&gpe2 3 0x1>;
1862 status = "disabled";
1863 };
1864
1865 /* HSI2C_USI8_0 */
1866 hsi2c_21: hsi2c@108C0000 {
1867 compatible = "samsung,exynos5-hsi2c";
1868 samsung,check-transdone-int;
1869 reg = <0x0 0x108C0000 0x1000>;
1870 interrupts = <0 406 0>;
1871 #address-cells = <1>;
1872 #size-cells = <0>;
1873 pinctrl-names = "default";
1874 pinctrl-0 = <&hsi2c21_bus>;
1875 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI08>;
1876 clock-names = "rate_hsi2c", "gate_hsi2c";
1877 samsung,scl-clk-stretching;
1878 gpio_sda= <&gpe2 4 0x1>;
1879 gpio_scl= <&gpe2 5 0x1>;
1880 status = "disabled";
1881 };
1882
1883 /* HSI2C_USI8_1 */
1884 hsi2c_22: hsi2c@108D0000 {
1885 compatible = "samsung,exynos5-hsi2c";
1886 samsung,check-transdone-int;
1887 reg = <0x0 0x108D0000 0x1000>;
1888 interrupts = <0 407 0>;
1889 #address-cells = <1>;
1890 #size-cells = <0>;
1891 pinctrl-names = "default";
1892 pinctrl-0 = <&hsi2c22_bus>;
1893 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI08>;
1894 clock-names = "rate_hsi2c", "gate_hsi2c";
1895 samsung,scl-clk-stretching;
1896 gpio_sda= <&gpe2 6 0x1>;
1897 gpio_scl= <&gpe2 7 0x1>;
1898 status = "disabled";
1899 };
1900
1901 /* HSI2C_USI9_0 */
1902 hsi2c_23: hsi2c@108E0000 {
1903 compatible = "samsung,exynos5-hsi2c";
1904 samsung,check-transdone-int;
1905 reg = <0x0 0x108E0000 0x1000>;
1906 interrupts = <0 410 0>;
1907 #address-cells = <1>;
1908 #size-cells = <0>;
1909 pinctrl-names = "default";
1910 pinctrl-0 = <&hsi2c23_bus>;
1911 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI09>;
1912 clock-names = "rate_hsi2c", "gate_hsi2c";
1913 samsung,scl-clk-stretching;
1914 gpio_sda= <&gpe3 0 0x1>;
1915 gpio_scl= <&gpe3 1 0x1>;
1916 status = "disabled";
1917 };
1918
1919 /* HSI2C_USI9_1 */
1920 hsi2c_24: hsi2c@108F0000 {
1921 compatible = "samsung,exynos5-hsi2c";
1922 samsung,check-transdone-int;
1923 reg = <0x0 0x108F0000 0x1000>;
1924 interrupts = <0 411 0>;
1925 #address-cells = <1>;
1926 #size-cells = <0>;
1927 pinctrl-names = "default";
1928 pinctrl-0 = <&hsi2c24_bus>;
1929 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI09>;
1930 clock-names = "rate_hsi2c", "gate_hsi2c";
1931 samsung,scl-clk-stretching;
1932 gpio_sda= <&gpe3 2 0x1>;
1933 gpio_scl= <&gpe3 3 0x1>;
1934 status = "disabled";
1935 };
1936
1937 /* HSI2C_USI10_0 */
1938 hsi2c_25: hsi2c@10900000 {
1939 compatible = "samsung,exynos5-hsi2c";
1940 samsung,check-transdone-int;
1941 reg = <0x0 0x10900000 0x1000>;
1942 interrupts = <0 414 0>;
1943 #address-cells = <1>;
1944 #size-cells = <0>;
1945 pinctrl-names = "default";
1946 pinctrl-0 = <&hsi2c25_bus>;
1947 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI10>;
1948 clock-names = "rate_hsi2c", "gate_hsi2c";
1949 samsung,scl-clk-stretching;
1950 gpio_sda= <&gpe3 4 0x1>;
1951 gpio_scl= <&gpe3 5 0x1>;
1952 status = "disabled";
1953 };
1954
1955 /* HSI2C_USI10_1 */
1956 hsi2c_26: hsi2c@10910000 {
1957 compatible = "samsung,exynos5-hsi2c";
1958 samsung,check-transdone-int;
1959 reg = <0x0 0x10910000 0x1000>;
1960 interrupts = <0 415 0>;
1961 #address-cells = <1>;
1962 #size-cells = <0>;
1963 pinctrl-names = "default";
1964 pinctrl-0 = <&hsi2c26_bus>;
1965 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI10>;
1966 clock-names = "rate_hsi2c", "gate_hsi2c";
1967 samsung,scl-clk-stretching;
1968 gpio_sda= <&gpe3 6 0x1>;
1969 gpio_scl= <&gpe3 7 0x1>;
1970 status = "disabled";
1971 };
1972
1973 /* HSI2C_USI11_0 */
1974 hsi2c_27: hsi2c@10920000 {
1975 compatible = "samsung,exynos5-hsi2c";
1976 samsung,check-transdone-int;
1977 reg = <0x0 0x10920000 0x1000>;
1978 interrupts = <0 418 0>;
1979 #address-cells = <1>;
1980 #size-cells = <0>;
1981 pinctrl-names = "default";
1982 pinctrl-0 = <&hsi2c27_bus>;
1983 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI11>;
1984 clock-names = "rate_hsi2c", "gate_hsi2c";
1985 samsung,scl-clk-stretching;
1986 gpio_sda= <&gpe4 0 0x1>;
1987 gpio_scl= <&gpe4 1 0x1>;
1988 status = "disabled";
1989 };
1990
1991 /* HSI2C_USI11_1 */
1992 hsi2c_28: hsi2c@10930000 {
1993 compatible = "samsung,exynos5-hsi2c";
1994 samsung,check-transdone-int;
1995 reg = <0x0 0x10930000 0x1000>;
1996 interrupts = <0 419 0>;
1997 #address-cells = <1>;
1998 #size-cells = <0>;
1999 pinctrl-names = "default";
2000 pinctrl-0 = <&hsi2c28_bus>;
2001 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI11>;
2002 clock-names = "rate_hsi2c", "gate_hsi2c";
2003 samsung,scl-clk-stretching;
2004 gpio_sda= <&gpe4 2 0x1>;
2005 gpio_scl= <&gpe4 3 0x1>;
2006 status = "disabled";
2007 };
2008
2009 /* HSI2C_USI12_0 */
2010 hsi2c_29: hsi2c@10940000 {
2011 compatible = "samsung,exynos5-hsi2c";
2012 samsung,check-transdone-int;
2013 reg = <0x0 0x10940000 0x1000>;
2014 interrupts = <0 422 0>;
2015 #address-cells = <1>;
2016 #size-cells = <0>;
2017 pinctrl-names = "default";
2018 pinctrl-0 = <&hsi2c29_bus>;
2019 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI12>;
2020 clock-names = "rate_hsi2c", "gate_hsi2c";
2021 samsung,scl-clk-stretching;
2022 gpio_sda= <&gpe4 4 0x1>;
2023 gpio_scl= <&gpe4 5 0x1>;
2024 status = "disabled";
2025 };
2026
2027 /* HSI2C_USI12_1 */
2028 hsi2c_30: hsi2c@10950000 {
2029 compatible = "samsung,exynos5-hsi2c";
2030 samsung,check-transdone-int;
2031 reg = <0x0 0x10950000 0x1000>;
2032 interrupts = <0 423 0>;
2033 #address-cells = <1>;
2034 #size-cells = <0>;
2035 pinctrl-names = "default";
2036 pinctrl-0 = <&hsi2c30_bus>;
2037 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI12>;
2038 clock-names = "rate_hsi2c", "gate_hsi2c";
2039 samsung,scl-clk-stretching;
2040 gpio_sda= <&gpe4 6 0x1>;
2041 gpio_scl= <&gpe4 7 0x1>;
2042 status = "disabled";
2043 };
2044
2045 /* HSI2C_USI13_0 */
2046 hsi2c_31: hsi2c@10960000 {
2047 compatible = "samsung,exynos5-hsi2c";
2048 samsung,check-transdone-int;
2049 reg = <0x0 0x10960000 0x1000>;
2050 interrupts = <0 426 0>;
2051 #address-cells = <1>;
2052 #size-cells = <0>;
2053 pinctrl-names = "default";
2054 pinctrl-0 = <&hsi2c31_bus>;
2055 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI13>;
2056 clock-names = "rate_hsi2c", "gate_hsi2c";
2057 samsung,scl-clk-stretching;
2058 gpio_sda= <&gpe5 4 0x1>;
2059 gpio_scl= <&gpe5 5 0x1>;
2060 status = "disabled";
2061 };
2062
2063 /* HSI2C_USI13_1 */
2064 hsi2c_32: hsi2c@10970000 {
2065 compatible = "samsung,exynos5-hsi2c";
2066 samsung,check-transdone-int;
2067 reg = <0x0 0x10970000 0x1000>;
2068 interrupts = <0 427 0>;
2069 #address-cells = <1>;
2070 #size-cells = <0>;
2071 pinctrl-names = "default";
2072 pinctrl-0 = <&hsi2c32_bus>;
2073 clocks = <&clock UMUX_CLKCMU_PERIC1_BUS>, <&clock GATE_USI13>;
2074 clock-names = "rate_hsi2c", "gate_hsi2c";
2075 samsung,scl-clk-stretching;
2076 gpio_sda= <&gpe5 6 0x1>;
2077 gpio_scl= <&gpe5 7 0x1>;
2078 status = "disabled";
2079 };
2080
2081 /* SPI CAM_0 */
2082 spi_0: spi@109D0000 {
2083 compatible = "samsung,exynos-spi";
2084 reg = <0x0 0x109D0000 0x100>;
2085 samsung,spi-fifosize = <64>;
2086 interrupts = <0 435 0>;
2087 /*
2088 To use DMA in SPI CAM_0, do not use DMA in SPI USI_13.
2089
2090 dma-mode;
2091 dmas = <&pdma0 31 1
2092 &pdma0 30 1>;
2093 */
2094 dma-names = "tx", "rx";
2095 swap-mode;
2096 #address-cells = <1>;
2097 #size-cells = <0>;
2098 clocks = <&clock GATE_SPI_CAM0>, <&clock DOUT_CLKCMU_PERIC1_SPI_CAM0>;
2099 clock-names = "spi", "spi_busclk0";
2100 pinctrl-names = "default";
2101 pinctrl-0 = <&spi0_bus>;
2102 status = "disabled";
2103 };
2104
2105 /* SPI CAM_1 */
2106 spi_1: spi@109E0000 {
2107 compatible = "samsung,exynos-spi";
2108 reg = <0x0 0x109E0000 0x100>;
2109 samsung,spi-fifosize = <64>;
2110 interrupts = <0 436 0>;
2111 dma-names = "tx", "rx";
2112 swap-mode;
2113 #address-cells = <1>;
2114 #size-cells = <0>;
2115 clocks = <&clock GATE_SPI_CAM1>, <&clock DOUT_CLKCMU_PERIC1_SPI_CAM1>;
2116 clock-names = "spi", "spi_busclk0";
2117 pinctrl-names = "default";
2118 pinctrl-0 = <&spi1_bus>;
2119 status = "disabled";
2120 };
2121
2122 /* SPI USI_0 */
2123 spi_2: spi@10440000 {
2124 compatible = "samsung,exynos-spi";
2125 reg = <0x0 0x10440000 0x100>;
2126 samsung,spi-fifosize = <64>;
2127 interrupts = <0 367 0>;
2128 /*
2129 dma-mode;
2130 dmas = <&pdma0 1 0
2131 &pdma0 0 0>;
2132 */
2133 dma-names = "tx", "rx";
2134 swap-mode;
2135 #address-cells = <1>;
2136 #size-cells = <0>;
2137 clocks = <&clock GATE_USI00>, <&clock USI00>;
2138 clock-names = "spi", "spi_busclk0";
2139 pinctrl-names = "default";
2140 pinctrl-0 = <&spi2_bus>;
2141 status = "disabled";
2142 };
2143
2144 /* SPI USI_1 */
2145 spi_3: spi@10460000 {
2146 compatible = "samsung,exynos-spi";
2147 reg = <0x0 0x10460000 0x100>;
2148 samsung,spi-fifosize = <64>;
2149 interrupts = <0 371 0>;
2150 /*
2151 dma-mode;
2152 dmas = <&pdma0 3 0
2153 &pdma0 2 0>;
2154 */
2155 dma-names = "tx", "rx";
2156 swap-mode;
2157 #address-cells = <1>;
2158 #size-cells = <0>;
2159 clocks = <&clock GATE_USI01>, <&clock USI01>;
2160 clock-names = "spi", "spi_busclk0";
2161 pinctrl-names = "default";
2162 pinctrl-0 = <&spi3_bus>;
2163 status = "disabled";
2164 };
2165
2166 /* SPI USI_2 */
2167 spi_4: spi@10480000 {
2168 compatible = "samsung,exynos-spi";
2169 reg = <0x0 0x10480000 0x100>;
2170 samsung,spi-fifosize = <64>;
2171 interrupts = <0 375 0>;
2172 /*
2173 dma-mode;
2174 dmas = <&pdma0 5 0
2175 &pdma0 4 0>;
2176 */
2177 dma-names = "tx", "rx";
2178 swap-mode;
2179 #address-cells = <1>;
2180 #size-cells = <0>;
2181 clocks = <&clock GATE_USI02>, <&clock USI02>;
2182 clock-names = "spi", "spi_busclk0";
2183 pinctrl-names = "default";
2184 pinctrl-0 = <&spi4_bus>;
2185 status = "disabled";
2186 };
2187
2188 /* SPI USI_3 */
2189 spi_5: spi@104A0000 {
2190 compatible = "samsung,exynos-spi";
2191 reg = <0x0 0x104A0000 0x100>;
2192 samsung,spi-fifosize = <64>;
2193 interrupts = <0 379 0>;
2194 /*
2195 dma-mode;
2196 dmas = <&pdma0 7 0
2197 &pdma0 6 0>;
2198 */
2199 dma-names = "tx", "rx";
2200 swap-mode;
2201 #address-cells = <1>;
2202 #size-cells = <0>;
2203 clocks = <&clock GATE_USI03>, <&clock USI03>;
2204 clock-names = "spi", "spi_busclk0";
2205 pinctrl-names = "default";
2206 pinctrl-0 = <&spi5_bus>;
2207 status = "disabled";
2208 };
2209
2210 /* SPI USI_4 */
2211 spi_6: spi@10840000 {
2212 compatible = "samsung,exynos-spi";
2213 reg = <0x0 0x10840000 0x100>;
2214 samsung,spi-fifosize = <64>;
2215 interrupts = <0 393 0>;
2216 /*
2217 dma-mode;
2218 dmas = <&pdma0 13 0
2219 &pdma0 12 0>;
2220 */
2221 dma-names = "tx", "rx";
2222 swap-mode;
2223 #address-cells = <1>;
2224 #size-cells = <0>;
2225 clocks = <&clock GATE_USI04>, <&clock USI04>;
2226 clock-names = "spi", "spi_busclk0";
2227 pinctrl-names = "default";
2228 pinctrl-0 = <&spi6_bus>;
2229 status = "disabled";
2230 };
2231
2232 /* SPI USI_5 */
2233 spi_7: spi@10860000 {
2234 compatible = "samsung,exynos-spi";
2235 reg = <0x0 0x10860000 0x100>;
2236 samsung,spi-fifosize = <64>;
2237 interrupts = <0 397 0>;
2238 /*
2239 dma-mode;
2240 dmas = <&pdma0 15 0
2241 &pdma0 14 0>;
2242 */
2243 dma-names = "tx", "rx";
2244 swap-mode;
2245 #address-cells = <1>;
2246 #size-cells = <0>;
2247 clocks = <&clock GATE_USI05>, <&clock USI05>;
2248 clock-names = "spi", "spi_busclk0";
2249 pinctrl-names = "default";
2250 pinctrl-0 = <&spi7_bus>;
2251 status = "disabled";
2252 };
2253
2254 /* SPI USI_6 */
2255 spi_8: spi@10880000 {
2256 compatible = "samsung,exynos-spi";
2257 reg = <0x0 0x10880000 0x100>;
2258 samsung,spi-fifosize = <64>;
2259 interrupts = <0 401 0>;
2260 /*
2261 dma-mode;
2262 dmas = <&pdma0 17 0
2263 &pdma0 16 0>;
2264 */
2265 dma-names = "tx", "rx";
2266 swap-mode;
2267 #address-cells = <1>;
2268 #size-cells = <0>;
2269 clocks = <&clock GATE_USI06>, <&clock USI06>;
2270 clock-names = "spi", "spi_busclk0";
2271 pinctrl-names = "default";
2272 pinctrl-0 = <&spi8_bus>;
2273 status = "disabled";
2274 };
2275
2276 /* SPI USI_7 */
2277 spi_9: spi@108A0000 {
2278 compatible = "samsung,exynos-spi";
2279 reg = <0x0 0x108A0000 0x100>;
2280 samsung,spi-fifosize = <64>;
2281 interrupts = <0 405 0>;
2282 /*
2283 dma-mode;
2284 dmas = <&pdma0 19 0
2285 &pdma0 18 0>;
2286 */
2287 dma-names = "tx", "rx";
2288 swap-mode;
2289 #address-cells = <1>;
2290 #size-cells = <0>;
2291 clocks = <&clock GATE_USI07>, <&clock USI07>;
2292 clock-names = "spi", "spi_busclk0";
2293 pinctrl-names = "default";
2294 pinctrl-0 = <&spi9_bus>;
2295 status = "disabled";
2296 };
2297
2298 /* SPI USI_8 */
2299 spi_10: spi@108C0000 {
2300 compatible = "samsung,exynos-spi";
2301 reg = <0x0 0x108C0000 0x100>;
2302 samsung,spi-fifosize = <64>;
2303 interrupts = <0 409 0>;
2304 /*
2305 dma-mode;
2306 dmas = <&pdma0 21 0
2307 &pdma0 20 0>;
2308 */
2309 dma-names = "tx", "rx";
2310 swap-mode;
2311 #address-cells = <1>;
2312 #size-cells = <0>;
2313 clocks = <&clock GATE_USI08>, <&clock USI08>;
2314 clock-names = "spi", "spi_busclk0";
2315 pinctrl-names = "default";
2316 pinctrl-0 = <&spi10_bus>;
2317 status = "disabled";
2318 };
2319
2320 /* SPI USI_9 */
2321 spi_11: spi@108E0000 {
2322 compatible = "samsung,exynos-spi";
2323 reg = <0x0 0x108E0000 0x100>;
2324 samsung,spi-fifosize = <64>;
2325 interrupts = <0 413 0>;
2326 /*
2327 dma-mode;
2328 dmas = <&pdma0 23 0
2329 &pdma0 22 0>;
2330 */
2331 dma-names = "tx", "rx";
2332 swap-mode;
2333 #address-cells = <1>;
2334 #size-cells = <0>;
2335 clocks = <&clock GATE_USI09>, <&clock USI09>;
2336 clock-names = "spi", "spi_busclk0";
2337 pinctrl-names = "default";
2338 pinctrl-0 = <&spi11_bus>;
2339 status = "disabled";
2340 };
2341
2342 /* SPI USI_10 */
2343 spi_12: spi@10900000 {
2344 compatible = "samsung,exynos-spi";
2345 reg = <0x0 0x10900000 0x100>;
2346 samsung,spi-fifosize = <64>;
2347 interrupts = <0 417 0>;
2348 /*
2349 dma-mode;
2350 dmas = <&pdma0 25 0
2351 &pdma0 24 0>;
2352 */
2353 dma-names = "tx", "rx";
2354 swap-mode;
2355 #address-cells = <1>;
2356 #size-cells = <0>;
2357 clocks = <&clock GATE_USI10>, <&clock USI10>;
2358 clock-names = "spi", "spi_busclk0";
2359 pinctrl-names = "default";
2360 pinctrl-0 = <&spi12_bus>;
2361 status = "disabled";
2362 };
2363
2364 /* SPI USI_11 */
2365 spi_13: spi@10920000 {
2366 compatible = "samsung,exynos-spi";
2367 reg = <0x0 0x10920000 0x100>;
2368 samsung,spi-fifosize = <64>;
2369 interrupts = <0 421 0>;
2370 /*
2371 dma-mode;
2372 dmas = <&pdma0 27 0
2373 &pdma0 26 0>;
2374 */
2375 dma-names = "tx", "rx";
2376 swap-mode;
2377 #address-cells = <1>;
2378 #size-cells = <0>;
2379 clocks = <&clock GATE_USI11>, <&clock USI11>;
2380 clock-names = "spi", "spi_busclk0";
2381 pinctrl-names = "default";
2382 pinctrl-0 = <&spi13_bus>;
2383 status = "disabled";
2384 };
2385
2386 /* SPI USI_12 */
2387 spi_14: spi@10940000 {
2388 compatible = "samsung,exynos-spi";
2389 reg = <0x0 0x10940000 0x100>;
2390 samsung,spi-fifosize = <64>;
2391 interrupts = <0 425 0>;
2392 /*
2393 dma-mode;
2394 dmas = <&pdma0 29 0
2395 &pdma0 28 0>;
2396 */
2397 dma-names = "tx", "rx";
2398 swap-mode;
2399 #address-cells = <1>;
2400 #size-cells = <0>;
2401 clocks = <&clock GATE_USI12>, <&clock USI12>;
2402 clock-names = "spi", "spi_busclk0";
2403 pinctrl-names = "default";
2404 pinctrl-0 = <&spi14_bus>;
2405 status = "disabled";
2406 };
2407
2408 /* SPI USI_13 */
2409 spi_15: spi@10960000 {
2410 compatible = "samsung,exynos-spi";
2411 reg = <0x0 0x10960000 0x100>;
2412 samsung,spi-fifosize = <64>;
2413 interrupts = <0 429 0>;
2414 /*
2415 To use DMA in SPI USI_13, do not use DMA in SPI CAM_0.
2416
2417 dma-mode;
2418 dmas = <&pdma0 31 0
2419 &pdma0 30 0>;
2420 */
2421 dma-names = "tx", "rx";
2422 swap-mode;
2423 #address-cells = <1>;
2424 #size-cells = <0>;
2425 clocks = <&clock GATE_USI13>, <&clock USI13>;
2426 clock-names = "spi", "spi_busclk0";
2427 pinctrl-names = "default";
2428 pinctrl-0 = <&spi15_bus>;
2429 status = "disabled";
2430 };
2431
2432 acpm {
2433 compatible = "samsung,exynos-acpm";
2434 #address-cells = <2>;
2435 #size-cells = <1>;
2436 reg = <0x0 0x16488000 0x1000>; /* PMU_ALIVE */
2437 acpm-ipc-channel = <4>;
2438 };
2439
2440 acpm_ipc {
2441 compatible = "samsung,exynos-acpm-ipc";
2442 #address-cells = <2>;
2443 #size-cells = <1>;
2444 interrupts = <0 39 0>;
2445 reg = <0x0 0x16440000 0x1000>, /* AP2APM MAILBOX */
2446 <0x0 0x16500000 0xB400>; /* APM SRAM */
2447 initdata-base = <0x2850>;
2448 num-timestamps = <32>;
2449 debug-log-level = <0>;
2450 logging-period = <500>;
2451 dump-base = <0x16500000>;
2452 dump-size = <0xB400>;
2453 };
2454
2455 acpm_dvfs {
2456 compatible = "samsung,exynos-acpm-dvfs";
2457 acpm-ipc-channel = <5>;
2458
2459 cpu_cold_temp_list = <ACPM_DVFS_MIF>, <ACPM_DVFS_INT>,
2460 <ACPM_DVFS_CPUCL0>, <ACPM_DVFS_CPUCL1>,
2461 <ACPM_DVFS_INTCAM>, <ACPM_DVFS_CAM>,
2462 <ACPM_DVFS_DISP>;
2463 gpu_cold_temp_list = <ACPM_DVFS_G3D>;
2464 };
2465
2466 smc_info: mcinfo@160300000 {
2467 compatible = "samsung,exynos-mcinfo";
2468 reg = <0x0 0x1603004C 0x4>,
2469 <0x0 0x1613004C 0x4>,
2470 <0x0 0x1623004C 0x4>,
2471 <0x0 0x1633004C 0x4>;
2472 bit_field = <20 4>;
2473 /* start bit, width */
2474 basecnt = <4>;
2475 irqcnt = <4>;
2476
2477 interrupts = <0 115 0>, <0 122 0>, <0 129 0>, <0 136 0>;
2478 };
2479
2480 devfreq_0: devfreq_mif@17000010 {
2481 compatible = "samsung,exynos-devfreq";
2482 reg = <0x0 0x17000010 0x0>;
2483 devfreq_type = "mif";
2484 devfreq_domain_name = "dvfs_mif";
2485
2486 /* Delay time */
2487 use_delay_time = "true";
2488 delay_time_list = "20";
2489
2490 freq_info = <2093000 208000 1014000 208000 2093000 421000>;
2491 /* initial_freq, default_qos, suspend_freq, min_freq, max_freq reboot_freq */
2492
2493 /* Booting value */
2494 boot_info = <40 1794000>;
2495 /* boot_qos_timeout, boot_freq */
2496
2497 use_get_dev = "false";
2498 polling_ms = <0>;
2499
2500 /* governor data */
2501 gov_name = "interactive";
2502 use_reg = "false";
2503
2504 use_tmu = "true";
2505 use_cl_dvfs = "false";
2506 use_sw_clk = "false";
2507 dfs_id = <ACPM_DVFS_MIF>;
2508 acpm-ipc-channel = <1>;
2509 use_acpm = "true";
2510 };
2511
2512 devfreq_1: devfreq_int@17000020 {
2513 compatible = "samsung,exynos-devfreq";
2514 reg = <0x0 0x17000020 0x0>;
2515 devfreq_type = "int";
2516 devfreq_domain_name = "dvfs_int";
2517
2518 /* Delay time */
2519 use_delay_time = "false";
2520
2521 freq_info = <667000 178000 107000 107000 667000 667000>;
2522 /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
2523
2524 /* Booting value */
2525 boot_info = <40 667000>;
2526 /* boot_qos_timeout, boot_freq */
2527
2528 /* default_dev_profile */
2529 use_get_dev = "false";
2530 polling_ms = <0>;
2531
2532 /* governor data */
2533 gov_name = "interactive";
2534 use_reg = "false";
2535
2536 use_tmu = "true";
2537 use_cl_dvfs = "false";
2538 use_sw_clk = "false";
2539 dfs_id = <ACPM_DVFS_INT>;
2540 acpm-ipc-channel = <1>;
2541 use_acpm = "true";
2542 };
2543
2544 devfreq_2: devfreq_intcam@17000030 {
2545 compatible = "samsung,exynos-devfreq";
2546 reg = <0x0 0x17000030 0x0>;
2547 devfreq_type = "intcam";
2548 devfreq_domain_name = "dvfs_intcam";
2549
2550 /* Delay time */
2551 use_delay_time = "false";
2552
2553 freq_info = <690000 640000 690000 640000 690000 690000>;
2554 /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
2555
2556 /* Booting value */
2557 boot_info = <40 640000>;
2558 /* boot_qos_timeout, boot_freq */
2559
2560 /* default_dev_profile */
2561 use_get_dev = "false";
2562 polling_ms = <0>;
2563
2564 /* governor data */
2565 gov_name = "interactive";
2566 use_reg = "false";
2567
2568 use_tmu = "true";
2569 use_cl_dvfs = "false";
2570 use_sw_clk = "false";
2571 dfs_id = <ACPM_DVFS_INTCAM>;
2572 };
2573
2574 devfreq_3: devfreq_disp@17000040 {
2575 compatible = "samsung,exynos-devfreq";
2576 reg = <0x0 0x17000040 0x0>;
2577 devfreq_type = "disp";
2578 devfreq_domain_name = "dvfs_disp";
2579
2580 /* Delay time */
2581 use_delay_time = "false";
2582
2583 freq_info = <630000 134000 630000 134000 630000 630000>;
2584 /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
2585
2586 /* Booting value */
2587 boot_info = <40 630000>;
2588 /* boot_qos_timeout, boot_freq */
2589
2590 /* default dev profile */
2591 use_get_dev = "false";
2592 polling_ms = <0>;
2593
2594 /* governor data */
2595 gov_name = "interactive";
2596 use_reg = "false";
2597
2598 use_tmu = "true";
2599 use_cl_dvfs = "false";
2600 use_sw_clk = "false";
2601 dfs_id = <ACPM_DVFS_DISP>;
2602 };
2603
2604 devfreq_4: devfreq_cam@17000050 {
2605 compatible = "samsung,exynos-devfreq";
2606 reg = <0x0 0x17000050 0x0>;
2607 devfreq_type = "cam";
2608 devfreq_domain_name = "dvfs_cam";
2609
2610 /* Delay time */
2611 use_delay_time = "false";
2612
2613 freq_info = <690000 630000 690000 630000 690000 690000>;
2614 /* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
2615
2616 /* Booting value */
2617 boot_info = <40 630000>;
2618 /* boot_qos_timeout, boot_freq */
2619
2620 /* default dev profile */
2621 use_get_dev = "false";
2622 polling_ms = <0>;
2623
2624 /* governor data */
2625 gov_name = "interactive";
2626 use_reg = "false";
2627
2628 use_tmu = "true";
2629 use_cl_dvfs = "false";
2630 use_sw_clk = "false";
2631 dfs_id = <ACPM_DVFS_CAM>;
2632 };
2633
2634 exynos_dm: exynos-dm@17000000 {
2635 compatible = "samsung,exynos-dvfs-manager";
2636 reg = <0x0 0x17000000 0x0>;
2637 acpm-ipc-channel = <1>;
2638 cpufreq_cl0 {
2639 dm-index = <DM_CPU_CL0>;
2640 available = "true";
2641 cal_id = <ACPM_DVFS_CPUCL0>;
2642 };
2643 cpufreq_cl1 {
2644 dm-index = <DM_CPU_CL1>;
2645 available = "true";
2646 cal_id = <ACPM_DVFS_CPUCL1>;
2647 };
2648 devfreq_mif {
2649 dm-index = <DM_MIF>;
2650 available = "true";
2651 policy_use = "true";
2652 cal_id = <ACPM_DVFS_MIF>;
2653 };
2654 devfreq_int {
2655 dm-index = <DM_INT>;
2656 available = "true";
2657 policy_use = "true";
2658 cal_id = <ACPM_DVFS_INT>;
2659 };
2660 devfreq_intcam {
2661 dm-index = <DM_INTCAM>;
2662 available = "true";
2663 cal_id = <ACPM_DVFS_INTCAM>;
2664 };
2665 devfreq_disp {
2666 dm-index = <DM_DISP>;
2667 available = "true";
2668 cal_id = <ACPM_DVFS_DISP>;
2669 };
2670 devfreq_cam {
2671 dm-index = <DM_CAM>;
2672 available = "true";
2673 cal_id = <ACPM_DVFS_CAM>;
2674 };
2675 dvfs_gpu {
2676 dm-index = <DM_GPU>;
2677 available = "false";
2678 cal_id = <ACPM_DVFS_G3D>;
2679 };
2680 };
2681
2682 fimg2d_0: fimg2d@15100000 {
2683 compatible = "samsung,s5p-fimg2d";
2684 reg = <0x0 0x13A30000 0x1000>;
2685 interrupts = <0 224 0>;
2686 clocks = <&clock GATE_G2D>;
2687 clock-names="gate";
2688 samsung,power-domain = <&pd_g2d>;
2689 iommus = <&sysmmu_g2d_0>, <&sysmmu_g2d_1>;
2690 hw_ppc = <2800>, <2400>, <3800>;
2691 /* cluster1 cluster0 mif */
2692 skia_qos_table = <0 0 1014000
2693 0 0 1014000
2694 0 0 845000
2695 0 0 845000
2696 0 0 676000
2697 0 0 0
2698 >;
2699 };
2700
2701 sysmmu_g2d_0: sysmmu@13A60000 {
2702 compatible = "samsung,exynos-sysmmu";
2703 reg = <0x0 0x13A60000 0x3000>;
2704 interrupts = <0 215 0>, <0 216 0>;
2705 clock-names = "aclk";
2706 clocks = <&clock GATE_SMMU_G2DD0>;
2707 port-name = "G2D0";
2708 sysmmu,secure-irq;
2709 sysmmu,secure_base = <0x13A80000>;
2710 #iommu-cells = <0>;
2711 };
2712 sysmmu_g2d_1: sysmmu@13A70000 {
2713 compatible = "samsung,exynos-sysmmu";
2714 reg = <0x0 0x13A70000 0x3000>;
2715 interrupts = <0 218 0>, <0 219 0>;
2716 clock-names = "aclk";
2717 clocks = <&clock GATE_SMMU_G2DD1>;
2718 port-name = "G2D1";
2719 sysmmu,secure-irq;
2720 sysmmu,secure_base = <0x13A90000>;
2721 #iommu-cells = <0>;
2722 };
2723
2724 /* SPEEDY IP_BATCHER_AP */
2725 speedy@15B50000 {
2726 compatible = "samsung,exynos-speedy";
2727 reg = <0x0 0x15B50000 0x2000>;
2728 interrupts = <0 109 0>;
2729 #address-cells = <1>;
2730 #size-cells = <0>;
2731 pinctrl-names = "default";
2732 pinctrl-0 = <&speedy_bus>;
2733 clocks = <&clock GATE_SPEEDY_BATCHER_WRAP_BATCHER_AP>;
2734 clock-names = "gate_speedy";
2735 status = "disabled";
2736 };
2737
2738 vpu: vpu@13300000 {
2739 compatible = "samsung,exynos-vpu";
2740 #pb-id-cells = <4>;
2741 reg = <0x0 0x133C0000 0x20000>, /* RAM0 */
2742 <0x0 0x133E0000 0x20000>, /* RAM1 */
2743 <0x0 0x13380000 0x20000>, /* CODE */
2744 <0x0 0x13300000 0x50000>; /* APB */
2745 interrupts = <0 190 0>, <0 191 0>;
2746 samsung,power-domain = <&pd_vpu>;
2747
2748 clocks = <&clock GATE_VPU>;
2749 clock-names = "vpu";
2750 iommus = <&sysmmu_vpu>;
2751 };
2752
2753 iommu-domain_vpu {
2754 compatible = "samsung,exynos-iommu-bus";
2755 #dma-address-cells = <1>;
2756 #dma-size-cells = <1>;
2757 /* start address, size */
2758 dma-window = <0x30000000 0xA0000000>;
2759
2760 domain-clients = <&vpu>;
2761 };
2762
2763 sysmmu_vpu: sysmmu@13250000 {
2764 compatible = "samsung,exynos-sysmmu";
2765 reg = <0x0 0x13250000 0x3000>;
2766 interrupts = <0 194 0>, <0 195 0>;
2767 qos = <15>;
2768 clock-names = "aclk";
2769 clocks = <&clock GATE_SMMU_VPU>;
2770 port-name = "VPU";
2771 sysmmu,secure-irq;
2772 sysmmu,secure_base = <0x13240000>;
2773 sysmmu,tlb_property =
2774 <(SYSMMU_PUBLIC_NO_PREFETCH | SYSMMU_BL8) SYSMMU_NOID>;
2775 #iommu-cells = <0>;
2776 };
2777
2778 iommu-domain_disp {
2779 compatible = "samsung,exynos-iommu-bus";
2780 #address-cells = <2>;
2781 #size-cells = <1>;
2782 ranges;
2783
2784 domain-clients = <&idma_g0>, <&idma_g1>, <&idma_vg0>, <&idma_vg1>,
2785 <&idma_vgf0>, <&idma_vgf1>, <&odma_wb>;
2786 };
2787
2788 sysmmu_dpu0: sysmmu@12900000 {
2789 compatible = "samsung,exynos-sysmmu";
2790 reg = <0x0 0x12900000 0x3000>;
2791 interrupts = <0 152 0>, <0 153 0>;
2792 qos = <15>;
2793 clock-names = "aclk";
2794 clocks = <&clock GATE_SYSMMU_DPUD0>;
2795 port-name = "DPU0 (VGR, VGF)";
2796 sysmmu,secure-irq;
2797 sysmmu,secure_base = <0x12930000>;
2798 sysmmu,tlb_property =
2799 /* 0~1 : VGR */
2800 <(SYSMMU_PRIV_ID_NO_PREFETCH_READ | SYSMMU_BL16) SYSMMU_ID_MASK(0x100, 0x180)>,
2801 <(SYSMMU_PRIV_ID_NO_PREFETCH_READ | SYSMMU_BL16) SYSMMU_ID_MASK(0x180, 0x180)>,
2802 /* 2~3 : VGF */
2803 <(SYSMMU_PRIV_ID_PREFETCH_PREDICTION_READ | SYSMMU_BL8) SYSMMU_ID_MASK(0x0, 0x180)>,
2804 <(SYSMMU_PRIV_ID_PREFETCH_PREDICTION_READ | SYSMMU_BL8) SYSMMU_ID_MASK(0x80, 0x180)>;
2805 #iommu-cells = <0>;
2806 };
2807 sysmmu_dpu1: sysmmu@12910000 {
2808 compatible = "samsung,exynos-sysmmu";
2809 reg = <0x0 0x12910000 0x3000>;
2810 interrupts = <0 155 0>, <0 156 0>;
2811 qos = <15>;
2812 clock-names = "aclk";
2813 clocks = <&clock GATE_SYSMMU_DPUD1>;
2814 port-name = "DPU1 (G0, VG0)";
2815 sysmmu,secure-irq;
2816 sysmmu,secure_base = <0x12940000>;
2817 sysmmu,tlb_property =
2818 /* 0 : G0 */
2819 <(SYSMMU_PRIV_ID_PREFETCH_PREDICTION_READ | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0x600)>,
2820 /* 1~2 : VG0 */
2821 <(SYSMMU_PRIV_ID_PREFETCH_PREDICTION_READ | SYSMMU_BL1) SYSMMU_ID_MASK(0x400, 0x600)>,
2822 <(SYSMMU_PRIV_ID_PREFETCH_PREDICTION_READ | SYSMMU_BL1) SYSMMU_ID_MASK(0x600, 0x600)>;
2823 #iommu-cells = <0>;
2824 };
2825 sysmmu_dpu2: sysmmu@12920000 {
2826 compatible = "samsung,exynos-sysmmu";
2827 reg = <0x0 0x12920000 0x3000>;
2828 interrupts = <0 158 0>, <0 159 0>;
2829 qos = <15>;
2830 clock-names = "aclk";
2831 clocks = <&clock GATE_SYSMMU_DPUD2>;
2832 port-name = "DPU2 (G1, VG1, WB)";
2833 sysmmu,secure-irq;
2834 sysmmu,secure_base = <0x12950000>;
2835 sysmmu,tlb_property =
2836 /* 0 : G1 */
2837 <(SYSMMU_PRIV_ID_PREFETCH_PREDICTION_READ | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0x600)>,
2838 /* 1~2 : VG1 */
2839 <(SYSMMU_PRIV_ID_PREFETCH_PREDICTION_READ | SYSMMU_BL1) SYSMMU_ID_MASK(0x400, 0x600)>,
2840 <(SYSMMU_PRIV_ID_PREFETCH_PREDICTION_READ | SYSMMU_BL1) SYSMMU_ID_MASK(0x600, 0x600)>,
2841 /* 3~4 : WB */
2842 <(SYSMMU_PRIV_ID_PREFETCH_PREDICTION_WRITE | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0x100)>,
2843 <(SYSMMU_PRIV_ID_PREFETCH_PREDICTION_WRITE | SYSMMU_BL1) SYSMMU_ID_MASK(0x100, 0x100)>;
2844 #iommu-cells = <0>;
2845 };
2846
2847 idma_g0: dpp@0x12851000{
2848 compatible = "samsung,exynos8-dpp";
2849 #pb-id-cells = <3>;
2850 reg = <0x0 0x12851000 0x1000>, <0x0 0x128B1000 0x1000>, <0x0 0x128B0000 0x100>;
2851 interrupts = <0 183 0>, <0 179 0>;
2852 iommus = <&sysmmu_dpu1>;
2853
2854 /* power domain */
2855 samsung,power-domain = <&pd_dpu0>;
2856 };
2857
2858 idma_g1: dpp@0x12852000{
2859 compatible = "samsung,exynos8-dpp";
2860 #pb-id-cells = <6>;
2861 reg = <0x0 0x12852000 0x1000>, <0x0 0x128B2000 0x1000>, <0x0 0x128B0000 0x100>;
2862 interrupts = <0 184 0>, <0 181 0>;
2863 iommus = <&sysmmu_dpu2>;
2864
2865 /* power domain */
2866 samsung,power-domain = <&pd_dpu0>;
2867 };
2868
2869 idma_vg0: dpp@0x12853000{
2870 compatible = "samsung,exynos8-dpp";
2871 #pb-id-cells = <3>;
2872 reg = <0x0 0x12853000 0x1000>, <0x0 0x128B3000 0x1000>, <0x0 0x128B0000 0x100>;
2873 interrupts = <0 185 0>, <0 180 0>;
2874 iommus = <&sysmmu_dpu1>;
2875
2876 /* power domain */
2877 samsung,power-domain = <&pd_dpu0>;
2878 };
2879
2880 idma_vg1: dpp@0x12854000{
2881 compatible = "samsung,exynos8-dpp";
2882 #pb-id-cells = <3>;
2883 reg = <0x0 0x12854000 0x1000>, <0x0 0x128B4000 0x1000>, <0x0 0x128B0000 0x100>;
2884 interrupts = <0 186 0>, <0 182 0>;
2885 iommus = <&sysmmu_dpu2>;
2886
2887 /* power domain */
2888 samsung,power-domain = <&pd_dpu0>;
2889 };
2890
2891 idma_vgf0: dpp@0x12855000{
2892 compatible = "samsung,exynos8-dpp";
2893 #pb-id-cells = <3>;
2894 reg = <0x0 0x12855000 0x1000>, <0x0 0x128B5000 0x1000>, <0x0 0x128B0000 0x100>;
2895 interrupts = <0 188 0>, <0 177 0>;
2896 iommus = <&sysmmu_dpu0>;
2897
2898 /* power domain */
2899 samsung,power-domain = <&pd_dpu0>;
2900 };
2901
2902 idma_vgf1: dpp@0x12856000{
2903 compatible = "samsung,exynos8-dpp";
2904 #pb-id-cells = <3>;
2905 reg = <0x0 0x12856000 0x1000>, <0x0 0x128B6000 0x1000>, <0x0 0x128B0000 0x100>;
2906 interrupts = <0 187 0>, <0 178 0>;
2907 iommus = <&sysmmu_dpu0>;
2908
2909 /* power domain */
2910 samsung,power-domain = <&pd_dpu0>;
2911 };
2912
2913 odma_wb: dpp@0x12890000{
2914 compatible = "samsung,exynos8-dpp";
2915 #pb-id-cells = <3>;
2916 reg = <0x0 0x12890000 0x1000>, <0x0 0x128B7000 0x1000>, <0x0 0x128B0000 0x100>;
2917 interrupts = <0 189 0>;
2918 iommus = <&sysmmu_dpu2>;
2919
2920 /* power domain */
2921 samsung,power-domain = <&pd_dpu0>;
2922 };
2923
2924 ion {
2925 compatible = "samsung,exynos5430-ion";
2926 };
2927
2928 disp_ss: disp_ss@0x12820000 {
2929 compatible = "samsung,exynos8-disp_ss";
2930 reg = <0x0 0x12821000 0x10>;
2931 };
2932
2933 disp_ver: disp_ver@0x10000010 {
2934 compatible = "samsung,exynos8-disp-ver";
2935 reg = <0x0 0x10000010 0x4>;
2936 };
2937
2938 mipi_phy_dsim: phy_m4s4_dsi@0x12821008 {
2939 compatible = "samsung,mipi-phy-m4s4-mod";
2940 samsung,pmu-syscon = <&pmu_system_controller>;
2941 isolation = <0x710>;
2942 /* PHY reset be controlled from DSIM */
2943 /* reg = <0x0 0x12821008 0x4>; */
2944 /* reset = <0 1>; */
2945 /* init = <4 5>; */ /* PHY reset control path bit of SYSREG */
2946 owner = <0>; /* 0: DSI, 1: CSI */
2947 #phy-cells = <1>;
2948 };
2949
2950 dsim_0: dsim@0x12870000 {
2951 compatible = "samsung,exynos8-dsim";
2952 reg = <0x0 0x12870000 0x100>;
2953 interrupts = <0 150 0>;
2954
2955 phys = <&mipi_phy_dsim 0>;
2956 phy-names = "dsim_dphy";
2957
2958 /* power domain */
2959 samsung,power-domain = <&pd_dpu1>;
2960 };
2961
2962 displayport_phy: displayport_phy@11090904 {
2963 compatible = "samsung,displayport-phy";
2964 samsung,pmu-syscon = <&pmu_system_controller>;
2965 isolation = <0x072C>;
2966 #phy-cells = <1>;
2967 };
2968
2969 displayport: displayport@0x11090000 {
2970 compatible = "samsung,exynos-displayport";
2971 reg = <0x0 0x11090000 0xFFFF>;
2972 interrupts = <0 340 0>;
2973
2974 phys = <&displayport_phy 0>;
2975 phy-names = "displayport_phy";
2976 };
2977
2978 displayport_adma: displayport_adma@0x15A40000 {
2979 compatible = "samsung,displayport-adma";
2980 reg = <0x0 0x15A40000 0x1000>;
2981 interrupt = <0 107 0>;
2982 clocks = <&clock GATE_PDMA0>;
2983 clock-names = "apb_pclk";
2984
2985 /* dma-mode; */
2986 dmas = <&pdma0 9 0>;
2987 dma-names = "tx";
2988 };
2989
2990 decon_f: decon_f@0x12860000 {
2991 compatible = "samsung,exynos8-decon";
2992 #pb-id-cells = <4>;
2993 reg = <0x0 0x12860000 0x10000>;
2994
2995 /* interrupt num */
2996 interrupts = <0 142 0>, <0 143 0>, <0 144 0>, <0 149 0>, <0 430 0>,
2997 <0 145 0>, <0 146 0>, <0 147 0>, <0 148 0>;
2998
2999 /* clock */
3000 clock-names = "aclk";
3001 clocks = <&clock GATE_DECON0>;
3002
3003 /* pinctrl */
3004 pinctrl-names = "hw_te_on", "hw_te_off";
3005 pinctrl-0 = <&decon_f_te_on>;
3006 pinctrl-1 = <&decon_f_te_off>;
3007
3008 /* power domain */
3009 samsung,power-domain = <&pd_dpu0>;
3010
3011 max_win = <6>;
3012 default_win = <5>;
3013 default_idma = <0>;
3014 psr_mode = <2>; /* 0: video mode, 1: DP command mode, 2: MIPI command mode */
3015 trig_mode = <0>; /* 0: hw trigger, 1: sw trigger */
3016 dsi_mode = <0>; /* 0: single dsi, 1: dual dsi */
3017
3018 /* 0: DSI, 1: eDP, 2:HDMI, 3: WB */
3019 out_type = <0>;
3020 /* 0: DSI0, 1: DSI1, 2: DSI2 */
3021 out_idx = <0>;
3022
3023 #address-cells = <2>;
3024 #size-cells = <1>;
3025 ranges;
3026
3027 /* EINT for TE */
3028 gpios = <&gpb0 1 0xf>;
3029 /* sw te pending register */
3030 te_eint {
3031 /* NWEINT_GPB0_PEND (GPB0_0:TE_T, GPB0_1:TE_F, GPB0_2:TE_S) */
3032 reg = <0x0 0x10980a00 0x4>;
3033 };
3034
3035 cam-stat {
3036 reg = <0x0 0x16484024 0x4>;
3037 };
3038 };
3039
3040 decon_s: decon_s@0x12A30000 {
3041 compatible = "samsung,exynos8-decon";
3042 #pb-id-cells = <4>;
3043 reg = <0x0 0x12A30000 0x8000>;
3044
3045 /* interrupt num */
3046 interrupts = <0 167 0>, <0 168 0>, <0 169 0>, <0 170 0>;
3047
3048 /* clock */
3049 clock-names = "aclk", "busd", "busp";
3050 clocks = <&clock GATE_DECON0>, <&clock UMUX_CLKCMU_DPU1_BUSD>,
3051 <&clock UMUX_CLKCMU_DPU1_BUSP>;
3052
3053 /* power domain */
3054 samsung,power-domain = <&pd_dpu1>;
3055
3056 max_win = <5>;
3057 default_win = <3>;
3058 default_idma = <2>;
3059 psr_mode = <2>; /* 0: video mode, 1: DP command mode, 2: MIPI command mode */
3060 trig_mode = <1>; /* 0: hw trigger, 1: sw trigger */
3061 dsi_mode = <0>; /* 0: single dsi, 1: dual dsi */
3062
3063 /* 0: DSI, 1: eDP, 2:DP, 3: WB */
3064 out_type = <3>;
3065 /* 0: DSI0, 1: DSI1, 2: DSI2 */
3066 out_idx = <0>;
3067
3068 #address-cells = <2>;
3069 #size-cells = <1>;
3070 ranges;
3071 };
3072
3073 decon_t: decon_t@0x12A40000 {
3074 compatible = "samsung,exynos8-decon";
3075 #pb-id-cells = <4>;
3076 reg = <0x0 0x12A40000 0x8000>;
3077
3078 /* interrupt num */
3079 interrupts = <0 171 0>, <0 172 0>, <0 173 0>, <0 174 0>, <0 175 0>;
3080
3081 /* clock */
3082 clock-names = "aclk", "busd", "busp", "busc", "core";
3083 clocks = <&clock GATE_DECON0>, <&clock UMUX_CLKCMU_DPU1_BUSD>,
3084 <&clock UMUX_CLKCMU_DPU1_BUSP>, <&clock GATE_TREX_BUSC>, <&clock GATE_TREX_CORE>;
3085
3086 /* power domain */
3087 samsung,power-domain = <&pd_dpu1>;
3088
3089 max_win = <5>;
3090 default_win = <3>;
3091 default_idma = <2>;
3092 psr_mode = <0>; /* 0: video mode, 1: DP command mode, 2: MIPI command mode */
3093 trig_mode = <1>; /* 0: hw trigger, 1: sw trigger */
3094 dsi_mode = <0>; /* 0: single dsi, 1: dual dsi */
3095
3096 /* 0: DSI, 1: eDP, 2:DP, 3: WB */
3097 out_type = <2>;
3098 /* 0: DSI0, 1: DSI1, 2: DSI2 */
3099 out_idx = <0>;
3100
3101 #address-cells = <2>;
3102 #size-cells = <1>;
3103 ranges;
3104 };
3105
3106 smfc: smfc@13B00000 {
3107 compatible = "samsung,exynos8890-jpeg";
3108 dma-coherent;
3109 reg = <0x0 0x13B00000 0x1000>;
3110 interrupts = <0 225 0>;
3111 clocks = <&clock GATE_JPEG>;
3112 clock-names = "gate";
3113 iommus = <&sysmmu_g2d_2>;
3114 samsung,power-domain = <&pd_g2d>;
3115 };
3116
3117 exynos_adc: adc@15B70000 {
3118 compatible = "samsung,exynos-adc-v3";
3119 reg = <0x0 0x15B70000 0x100>;
3120 interrupts = <0 104 0>;
3121 #io-channel-cells = <1>;
3122 io-channel-ranges;
3123 clocks = <&clock GATE_ADCIF_BUSC_S0>;
3124 clock-names = "gate_adcif";
3125 };
3126
3127 scaler_0: scaler@0x13B10000 {
3128 compatible = "samsung,exynos5-scaler";
3129 dma-coherent;
3130 reg = <0x0 0x13B10000 0x1300>;
3131 interrupts = <0 226 0>;
3132 clocks = <&clock GATE_M2MSCALER>;
3133 clock-names = "gate";
3134 iommus = <&sysmmu_g2d_2>;
3135 samsung,power-domain = <&pd_g2d>;
3136 };
3137
3138 ima: ima@0x1C000000 {
3139 compatible = "samsung,exynos-ima";
3140 reg = <0x0 0x13780000 0x80000>, /* CPU path */
3141 <0x0 0x1C000000 0x80000>, /* DMA path */
3142 <0x0 0x13520000 0x2000>, /* Sysreg */
3143 <0x0 0x136D0000 0x1000>; /* Pre-register */
3144 clocks = <&clock GATE_IVA_INTMEM>;
3145 clock-names = "gate";
3146 samsung,power-domain = <&pd_iva>;
3147 };
3148
3149 iommu-domain_g2d {
3150 compatible = "samsung,exynos-iommu-bus";
3151 #address-cells = <2>;
3152 #size-cells = <1>;
3153 ranges;
3154
3155 domain-clients = <&fimg2d_0>;
3156 };
3157
3158 iommu-domain_smfc_scaler {
3159 compatible = "samsung,exynos-iommu-bus";
3160 #address-cells = <2>;
3161 #size-cells = <1>;
3162 ranges;
3163
3164 domain-clients = <&smfc>, <&scaler_0>;
3165 };
3166
3167 sysmmu_g2d_2: sysmmu@13B50000 {
3168 compatible = "samsung,exynos-sysmmu";
3169 reg = <0x0 0x13B50000 0x3000>;
3170 interrupts = <0 221 0>, <0 222 0>;
3171 clock-names = "aclk";
3172 clocks = <&clock GATE_SMMU_G2DD2>;
3173 port-name = "Scaler, SMFC";
3174 sysmmu,secure-irq;
3175 sysmmu,secure_base = <0x13B60000>;
3176 sysmmu,tlb_property =
3177 /* 0~5 : M2MScaler */
3178 <(SYSMMU_PRIV_ID_NO_PREFETCH_READ | SYSMMU_BL32) SYSMMU_ID(0x1)>,
3179 <(SYSMMU_PRIV_ID_NO_PREFETCH_READ | SYSMMU_BL32) SYSMMU_ID(0x3)>,
3180 <(SYSMMU_PRIV_ID_NO_PREFETCH_READ | SYSMMU_BL32) SYSMMU_ID(0x5)>,
3181 <(SYSMMU_PRIV_ID_NO_PREFETCH_WRITE | SYSMMU_BL32) SYSMMU_ID(0x11)>,
3182 <(SYSMMU_PRIV_ID_NO_PREFETCH_WRITE | SYSMMU_BL32) SYSMMU_ID(0x13)>,
3183 <(SYSMMU_PRIV_ID_NO_PREFETCH_WRITE | SYSMMU_BL32) SYSMMU_ID(0x15)>,
3184 /* 6~9 : SMFC */
3185 <(SYSMMU_PRIV_ADDR_NO_PREFETCH_READWRITE | SYSMMU_BL32) SYSMMU_NOID>,
3186 <(SYSMMU_PRIV_ADDR_NO_PREFETCH_READWRITE | SYSMMU_BL32) SYSMMU_NOID>,
3187 <(SYSMMU_PRIV_ADDR_NO_PREFETCH_READWRITE | SYSMMU_BL32) SYSMMU_NOID>,
3188 <(SYSMMU_PRIV_ADDR_NO_PREFETCH_WRITE | SYSMMU_BL32) SYSMMU_NOID>;
3189 #iommu-cells = <0>;
3190 };
3191
3192 watchdog@10060000 {
3193 compatible = "samsung,exynos8-wdt";
3194 reg = <0x0 0x10060000 0x100>;
3195 interrupts = <0 454 0>;
3196 clocks = <&clock OSCCLK>, <&clock UMUX_CLKCMU_PERIS_BUS>;
3197 clock-names = "rate_watchdog", "gate_watchdog";
3198 timeout-sec = <30>;
3199 samsung,syscon-phandle = <&pmu_system_controller>;
3200 };
3201
3202 dwmmc_2: dwmmc2@11500000 {
3203 compatible = "samsung,exynos-dw-mshc";
3204 reg = <0x0 0x11500000 0x2000>;
3205 interrupts = <0 341 0>;
3206 #address-cells = <1>;
3207 #size-cells = <0>;
3208 clocks = <&clock MMC_CARD>, <&clock GATE_MMC_CARD>;
3209 clock-names = "ciu", "ciu_gate";
3210 status = "disabled";
3211 };
3212
3213 sec_pwm: pwm@104c0000 {
3214 compatible = "samsung,s3c6400-pwm";
3215 reg = <0x0 0x104c0000 0x1000>;
3216 samsung,pwm-outputs = <0>, <1>, <2>, <3>, <4>;
3217 #pwm-cells = <3>;
3218 clocks = <&clock UMUX_CLKCMU_PERIC0_BUS>,
3219 <&clock_pwm 1>, <&clock_pwm 2>,
3220 <&clock_pwm 5>, <&clock_pwm 6>,
3221 <&clock_pwm 7>, <&clock_pwm 8>,
3222 <&clock_pwm 10>, <&clock_pwm 11>,
3223 <&clock_pwm 12>, <&clock_pwm 13>;
3224 clock-names = "gate_timers",
3225 "pwm-scaler0", "pwm-scaler1",
3226 "pwm-tdiv0", "pwm-tdiv1",
3227 "pwm-tdiv2", "pwm-tdiv3",
3228 "pwm-tin0", "pwm-tin1",
3229 "pwm-tin2", "pwm-tin3";
3230 status = "ok";
3231 };
3232
3233 clock_pwm: pwm-clock-controller@104c0000 {
3234 compatible = "samsung,exynos-pwm-clock";
3235 reg = <0x0 0x104c0000 0x50>;
3236 #clock-cells = <1>;
3237 };
3238
3239 coresight@17000000 {
3240 compatible = "exynos,coresight";
3241 base = <0x17000000>;
3242 sj-offset = <0x6000>;
3243 /* coresight component count */
3244 funnel-num = <3>;
3245 etf-num = <2>;
3246
3247 cl0_cpu0@400000 {
3248 device_type = "cs";
3249 dbg-offset = <0x410000>;
3250 etm-offset = <0x440000>;
3251 funnel-port = <0 0>;
3252 };
3253 cl0_cpu1@500000 {
3254 device_type = "cs";
3255 dbg-offset = <0x510000>;
3256 etm-offset = <0x540000>;
3257 funnel-port = <0 1>;
3258 };
3259 cl0_cpu2@600000 {
3260 device_type = "cs";
3261 dbg-offset = <0x610000>;
3262 etm-offset = <0x640000>;
3263 funnel-port = <0 2>;
3264 };
3265 cl0_cpu3@700000 {
3266 device_type = "cs";
3267 dbg-offset = <0x710000>;
3268 etm-offset = <0x740000>;
3269 funnel-port = <0 3>;
3270 };
3271 cl1_cpu0@800000 {
3272 device_type = "cs";
3273 dbg-offset = <0x810000>;
3274 etm-offset = <0x840000>;
3275 funnel-port = <1 0>;
3276 };
3277 cl1_cpu1@900000 {
3278 device_type = "cs";
3279 dbg-offset = <0x910000>;
3280 etm-offset = <0x940000>;
3281 funnel-port = <1 1>;
3282 };
3283 cl1_cpu2@A00000 {
3284 device_type = "cs";
3285 dbg-offset = <0xA10000>;
3286 etm-offset = <0xA40000>;
3287 funnel-port = <1 2>;
3288 };
3289 cl1_cpu3@B00000 {
3290 device_type = "cs";
3291 dbg-offset = <0xB10000>;
3292 etm-offset = <0xB40000>;
3293 funnel-port = <1 3>;
3294 };
3295
3296 cs_etf0: cs_etf0@C000 {
3297 device_type = "etf";
3298 offset = <0x4000>;
3299 funnel-port = <2 0>;
3300 };
3301 cs_etf1: cs_etf1@5000 {
3302 device_type = "etf";
3303 offset = <0x5000>;
3304 funnel-port = <2 1>;
3305 };
3306 cs_funnel0@4000 {
3307 device_type = "funnel";
3308 offset = <0x7000>;
3309 };
3310 cs_funnel1@9000 {
3311 device_type = "funnel";
3312 offset = <0x8000>;
3313 };
3314 cs_funnelm2@9000 {
3315 device_type = "funnel";
3316 offset = <0x9000>;
3317 };
3318 cs_etr@B000 {
3319 device_type = "etr";
3320 offset = <0xA000>;
3321 };
3322 };
3323
3324 udc: usb@10C00000 {
3325 compatible = "samsung,exynos8895-dwusb3";
3326 clocks = <&clock GATE_USBTV_USB30DRD_LINK>, <&clock USBDRD30>;
3327 clock-names = "aclk", "sclk";
3328 reg = <0x0 0x10C00000 0x10000>;
3329 #address-cells = <2>;
3330 #size-cells = <1>;
3331 ranges;
3332 status = "disabled";
3333
3334 usbdrd_dwc3: dwc3 {
3335 compatible = "synopsys,dwc3";
3336 reg = <0x0 0x10C00000 0x10000>;
3337 interrupts = <0 337 0>;
3338 is_not_vbus_pad;
3339 suspend_clk_freq = <66000000>;
3340 enable_sprs_transfer;
3341 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
3342 phy-names = "usb2-phy", "usb3-phy";
3343 };
3344 };
3345
3346 usbdrd_phy0: phy@10E00000 {
3347 compatible = "samsung,exynos8895-usbdrd-phy";
3348 reg = <0x0 0x10E00000 0x100>,
3349 <0x0 0x10E10000 0x100>;
3350 clocks = <&clock OSCCLK>, <&clock GATE_USBTV_USB30DRD_LINK>;
3351 clock-names = "ext_xtal", "aclk";
3352 samsung,pmu-syscon = <&pmu_system_controller>;
3353 is_not_vbus_pad;
3354 status = "disabled";
3355 #phy-cells = <1>;
3356 #address-cells = <2>;
3357 #size-cells = <1>;
3358 ranges;
3359 change_refclk = <1>;
3360
3361 usbphy-refclk {
3362 reg = <0x0 0x10E50070 0x10>;
3363 offset = <0xC>;
3364 mask = <0x1000000>;
3365 value = <0x1000000>;
3366 };
3367 };
3368
3369 iommu-domain_aud {
3370 compatible = "samsung,exynos-iommu-bus";
3371 #address-cells = <2>;
3372 #size-cells = <1>;
3373 ranges;
3374 domain-clients = <&abox>;
3375 };
3376
3377 sysmmu_aud0: sysmmu@13E30000 {
3378 compatible = "samsung,exynos-sysmmu";
3379 reg = <0x0 0x13E30000 0x3000>;
3380 interrupts = <0 445 0>;
3381 qos = <15>;
3382 clock-names = "aclk";
3383 clocks = <&clock GATE_SMMU_ABOX>;
3384 port-name = "Abox";
3385 sysmmu,no-suspend;
3386 sysmmu,tlb_property =
3387 <(SYSMMU_PUBLIC_NO_PREFETCH | SYSMMU_BL1) SYSMMU_NOID>;
3388 #iommu-cells = <0>;
3389 };
3390
3391 abox_gic: abox_gic@0x13EF0000 {
3392 compatible = "samsung,abox_gic";
3393 reg = <0x0 0x13EF1000 0x1000>, <0x0 0x13EF2000 0x1004>;
3394 reg-names = "gicd", "gicc";
3395 interrupts = <0 442 0>;
3396 };
3397
3398 abox: abox@0x13E50000 {
3399 compatible = "samsung,abox";
3400 reg = <0x0 0x13E50000 0x10000>, <0x0 0x13E20000 0x10000>, <0x0 0x13F00000 0x31000>;
3401 reg-names = "sfr", "sysreg", "sram";
3402 #address-cells = <2>;
3403 #size-cells = <1>;
3404 ranges;
3405 pinctrl-names = "default", "idle";
3406 pinctrl-0 = <&aud_codec_mclk &aud_codec_bus &aud_spk_bus
3407 &aud_fm_bus &aud_bt_bus &aud_cdma_bus>;
3408 pinctrl-1 = <&aud_codec_mclk_idle &aud_codec_bus_idle &aud_spk_bus_idle
3409 &aud_fm_bus_idle &aud_bt_bus_idle &aud_cdma_bus_idle>;
3410 samsung,power-domain = <&pd_abox>;
3411 ipc_tx_offset = <0x30000>;
3412 ipc_rx_offset = <0x30300>;
3413 ipc_tx_ack_offset = <0x302FC>;
3414 ipc_rx_ack_offset = <0x305FC>;
3415 mailbox_offset = <0x30600>;
3416 abox_gic = <&abox_gic>;
3417 vts = <&vts>;
3418 clocks = <&clock PLL_OUT_AUD>, <&clock DFS_ABOX>, <&clock DOUT_CLK_ABOX_AUDIF>,
3419 <&clock DOUT_CLK_ABOX_UAIF0>, <&clock DOUT_CLK_ABOX_UAIF1>,
3420 <&clock DOUT_CLK_ABOX_UAIF2>, <&clock DOUT_CLK_ABOX_UAIF3>,
3421 <&clock DOUT_CLK_ABOX_UAIF4>, <&clock DOUT_CLK_ABOX_DSIF>,
3422 <&clock DOUT_CLK_ABOX_DMIC>, <&clock GATE_UAIF0>,
3423 <&clock GATE_UAIF1>, <&clock GATE_UAIF2>,
3424 <&clock GATE_UAIF3>, <&clock GATE_UAIF4>,
3425 <&clock GATE_DSIF>;
3426 clock-names = "pll", "ca7", "audif",
3427 "bclk0", "bclk1",
3428 "bclk2", "bclk3",
3429 "bclk4", "bclk5",
3430 "dmic", "bclk0_gate",
3431 "bclk1_gate", "bclk2_gate",
3432 "bclk3_gate", "bclk4_gate",
3433 "bclk5_gate";
3434 iommus = <&sysmmu_aud0>;
3435 pm_qos_int = <533000 400000 0 0 0>;
3436
3437 abox_rdma_0: abox_rdma@0x13E51000 {
3438 compatible = "samsung,abox-rdma";
3439 reg = <0x0 0x13E51000 0x100>;
3440 abox = <&abox>;
3441 id = <0>;
3442 type = "normal";
3443 pm_qos_lit = <715000 715000 0>; /* SUHQA UHQA NORMAL */
3444 pm_qos_big = <1170000 1170000 0>; /* SUHQA UHQA NORMAL */
3445 pm_qos_hmp = <1 1 0>; /* SUHQA UHQA NORMAL */
3446 };
3447
3448 abox_rdma_1: abox_rdma@0x13E51100 {
3449 compatible = "samsung,abox-rdma";
3450 reg = <0x0 0x13E51100 0x100>;
3451 abox = <&abox>;
3452 id = <1>;
3453 type = "normal";
3454 pm_qos_lit = <715000 715000 0>; /* SUHQA UHQA NORMAL */
3455 pm_qos_big = <1170000 1170000 0>; /* SUHQA UHQA NORMAL */
3456 pm_qos_hmp = <1 1 0>; /* SUHQA UHQA NORMAL */
3457 };
3458
3459 abox_rdma_2: abox_rdma@0x13E51200 {
3460 compatible = "samsung,abox-rdma";
3461 reg = <0x0 0x13E51200 0x100>;
3462 abox = <&abox>;
3463 id = <2>;
3464 type = "normal";
3465 pm_qos_lit = <715000 715000 0>; /* SUHQA UHQA NORMAL */
3466 pm_qos_big = <1170000 1170000 0>; /* SUHQA UHQA NORMAL */
3467 pm_qos_hmp = <1 1 0>; /* SUHQA UHQA NORMAL */
3468 };
3469
3470 abox_rdma_3: abox_rdma@0x13E51300 {
3471 compatible = "samsung,abox-rdma";
3472 reg = <0x0 0x13E51300 0x100>;
3473 abox = <&abox>;
3474 id = <3>;
3475 type = "sync";
3476 };
3477
3478 abox_rdma_4: abox_rdma@0x13E51400 {
3479 compatible = "samsung,abox-rdma";
3480 reg = <0x0 0x13E51400 0x100>;
3481 abox = <&abox>;
3482 id = <4>;
3483 type = "call";
3484 };
3485
3486 abox_rdma_5: abox_rdma@0x13E51500 {
3487 compatible = "samsung,abox-rdma";
3488 reg = <0x0 0x13E51500 0x100>;
3489 abox = <&abox>;
3490 id = <5>;
3491 type = "compress";
3492 };
3493
3494 abox_rdma_6: abox_rdma@0x13E51600 {
3495 compatible = "samsung,abox-rdma";
3496 reg = <0x0 0x13E51600 0x100>;
3497 abox = <&abox>;
3498 id = <6>;
3499 type = "realtime";
3500 };
3501
3502 abox_rdma_7: abox_rdma@0x13E51700 {
3503 compatible = "samsung,abox-rdma";
3504 reg = <0x0 0x13E51700 0x100>;
3505 abox = <&abox>;
3506 id = <7>;
3507 type = "realtime";
3508 };
3509
3510 abox_wdma_0: abox_wdma@0x13E52000 {
3511 compatible = "samsung,abox-wdma";
3512 reg = <0x0 0x13E52000 0x100>;
3513 abox = <&abox>;
3514 id = <0>;
3515 type = "normal";
3516 };
3517
3518 abox_wdma_1: abox_wdma@0x13E52100 {
3519 compatible = "samsung,abox-wdma";
3520 reg = <0x0 0x13E52100 0x100>;
3521 abox = <&abox>;
3522 id = <1>;
3523 type = "normal";
3524 };
3525
3526 abox_wdma_2: abox_wdma@0x13E52200 {
3527 compatible = "samsung,abox-wdma";
3528 reg = <0x0 0x13E52200 0x100>;
3529 abox = <&abox>;
3530 id = <2>;
3531 type = "call";
3532 };
3533
3534 abox_wdma_3: abox_wdma@0x13E52300 {
3535 compatible = "samsung,abox-wdma";
3536 reg = <0x0 0x13E52300 0x100>;
3537 abox = <&abox>;
3538 id = <3>;
3539 type = "realtime";
3540 };
3541
3542 abox_wdma_4: abox_wdma@0x13E52400 {
3543 compatible = "samsung,abox-wdma";
3544 reg = <0x0 0x13E52400 0x100>;
3545 abox = <&abox>;
3546 id = <4>;
3547 type = "vi-sensing";
3548 };
3549
3550 abox_effect: abox_effect@0x13F2E000 {
3551 compatible = "samsung,abox-effect";
3552 reg = <0x0 0x13F2E000 0x1000>;
3553 reg-names = "reg";
3554 abox = <&abox>;
3555 };
3556
3557 abox_debug: abox_debug@0 {
3558 compatible = "samsung,abox-debug";
3559 memory-region = <&abox_rmem>;
3560 };
3561
3562 abox_vss: abox_vss@0 {
3563 compatible = "samsung,abox-vss";
3564 };
3565
3566 ext_bin_0: ext_bin@0 {
3567 status = "okay";
3568 samsung,name = "dsm.bin";
3569 samsung,area = <1>; /* 0:SRAM, 1:DRAM, 2:VSS */
3570 samsung,offset = <0x502000>;
3571 };
3572 ext_bin_1: ext_bin@1 {
3573 status = "okay";
3574 samsung,name = "AP_AUDIO_SLSI.bin";
3575 samsung,area = <1>;
3576 samsung,offset = <0x7F0000>;
3577 };
3578 ext_bin_2: ext_bin@2 {
3579 status = "okay";
3580 samsung,name = "APBargeIn_AUDIO_SLSI.bin";
3581 samsung,area = <1>;
3582 samsung,offset = <0x7EC000>;
3583 };
3584 ext_bin_3: ext_bin@3 {
3585 status = "okay";
3586 samsung,name = "SoundBoosterParam.bin";
3587 samsung,area = <1>;
3588 samsung,offset = <0x4FC000>;
3589 };
3590 ext_bin_4: ext_bin@4 {
3591 status = "okay";
3592 samsung,name = "APBiBF_AUDIO_SLSI.bin";
3593 samsung,area = <1>;
3594 samsung,offset = <0x7EF000>;
3595 };
3596 ext_bin_5: ext_bin@5 {
3597 status = "okay";
3598 samsung,name = "dsm_tune.bin";
3599 samsung,area = <1>;
3600 samsung,offset = <0x601000>;
3601 };
3602 ext_bin_6: ext_bin@6 {
3603 status = "disabled";
3604 samsung,name = "dummy.bin";
3605 samsung,area = <1>;
3606 samsung,offset = <0x800000>;
3607 };
3608 ext_bin_7: ext_bin@7 {
3609 status = "disabled";
3610 samsung,name = "dummy.bin";
3611 samsung,area = <1>;
3612 samsung,offset = <0x800000>;
3613 };
3614 };
3615
3616 mailbox_vts: mailbox@0x14040000 {
3617 compatible = "samsung,mailbox-asoc";
3618 reg = <0x0 0x14040000 0x10000>;
3619 reg-names = "sfr";
3620 interrupts = <0 23 0>;
3621 interrupt-controller;
3622 #interrupt-cells = <1>;
3623 };
3624
3625 vts: vts@0x14020000 {
3626 compatible = "samsung,vts";
3627 reg = <0x0 0x14020000 0x10000>, <0x0 0x14100000 0x59800>,
3628 <0x0 0x14070000 0x8>, <0x0 0x141F0000 0x50>;
3629 reg-names = "sfr", "sram", "dmic", "gpr";
3630 #address-cells = <2>;
3631 #size-cells = <1>;
3632 ranges;
3633 pinctrl-names = "dmic_default", "amic_default", "idle";
3634 pinctrl-0 = <&dmic_bus_clk &dmic_pdm>;
3635 pinctrl-1 = <&amic_bus_clk &amic_pdm>;
3636 pinctrl-2 = <&mic_bus_clk_idle &dmic_pdm_idle &amic_pdm_idle>;
3637 samsung,power-domain = <&pd_vts>;
3638 clocks = <&clock GATE_OSC_VTS>, <&clock DOUT_CLK_VTS_DMIC>,
3639 <&clock DOUT_CLK_VTS_DMICIF>, <&clock DOUT_CLK_VTS_DMIC_DIV2>;
3640 clock-names = "rco", "dmic", "dmic_if", "dmic_sync";
3641 mailbox = <&mailbox_vts>;
3642 interrupt-parent = <&mailbox_vts>;
3643 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
3644 interrupt-names = "error", "boot_completed", "ipc_received", "voice_triggered", "trigger_period_elapsed", "record_period_elapsed";
3645 vts_dma0: vts_dma@0x0 {
3646 compatible = "samsung,vts-dma";
3647 reg = <0x0 0x0 0x0>;
3648 vts = <&vts>;
3649 id = <0>;
3650 type = "vts-trigger";
3651 };
3652
3653 vts_dma1: vts_dma@0x1 {
3654 compatible = "samsung,vts-dma";
3655 reg = <0x0 0x1 0x0>;
3656 vts = <&vts>;
3657 id = <1>;
3658 type = "vts-record";
3659 };
3660 };
3661
3662 pcie0@116A0000 {
3663 compatible = "samsung,exynos-pcie";
3664 gpios = <&gpj1 2 0x1 /* PERST */>;
3665 reg = <0x0 0x116A0000 0x1000 /* elbi base */
3666 0x0 0x116D0000 0x1000 /* phy base */
3667 0x0 0x11421044 0x30 /* sysreg base */
3668 0x0 0x11700000 0x1000 /* DBI base */
3669 0x0 0x116C0000 0x1FC /* phy pcs base */
3670 0x0 0x11BFF000 0x1000>; /* configuration space */
3671 reg-names = "elbi", "phy", "sysreg", "dbi", "pcs", "config";
3672 interrupts = <0 345 0>; /* IRQ_PULSE */
3673 samsung,syscon-phandle = <&pmu_system_controller>;
3674 samsung,sysreg-phandle = <&sysreg_fsys1_controller>;
3675 pinctrl-names = "default", "clkreq_output";
3676 pinctrl-0 = <&pcie0_clkreq &pcie0_perst &pcie_wake &cfg_wlanen &wlan_host_wake>;
3677 pinctrl-1 = <&pcie0_perst &pcie_wake &cfg_wlanen &wlan_host_wake>;
3678 #address-cells = <3>;
3679 #size-cells = <2>;
3680 device_type = "pci";
3681 ranges = <0x82000000 0 0x11800000 0 0x11800000 0 0x400000>; /* non-prefetchable memory */
3682 #interrupt-cells = <1>;
3683 interrupt-map-mask = <0 0 0 0>;
3684 interrupt-map = <0 0 0 0 &gic 0 345 0x4>;
3685 ip-ver = <0x889500>;
3686 num-lanes = <1>;
3687 msi-base = <200>;
3688 ch-num = <0>;
3689 pcie-clk-num = <0>;
3690 phy-clk-num = <0>;
3691 pcie-irq-toe-enable = <0>;
3692 pcie-irq-toe-num = <10>;
3693 pcie-irq-msi-cp-enable = <0>;
3694 pcie-irq-msi-cp-base-bit = <16>;
3695 pcie-irq-msi-cp-num = <4>;
3696 pcie-pm-qos-int = <0>;
3697 use-cache-coherency = "true";
3698 use-msi = "false";
3699 use-sicd = "true";
3700 status = "disabled";
3701 };
3702
3703 pcie1@116B0000 {
3704 compatible = "samsung,exynos8895-pcie";
3705 gpios = <&gpj1 6 0x1 /* PERST */>;
3706 reg = <0x0 0x116B0000 0x1000 /* elbi base */
3707 0x0 0x116D0000 0x1000 /* phy base */
3708 0x0 0x15601044 0x30 /* sysreg base */
3709 0x0 0x11710000 0x1000 /* DBI base */
3710 0x0 0x116C0000 0x1FC /* phy pcs base */
3711 0x0 0x11C00000 0x1000>; /* configuration space */
3712 reg-names = "elbi", "phy", "sysreg", "dbi", "pcs", "config";
3713 interrupts = <0 346 0>; /* IRQ_PULSE */
3714 clocks = <&clock 770>;
3715 clock-names = "gate_pciewifi1";
3716 samsung,syscon-phandle = <&pmu_system_controller>;
3717 pinctrl-names = "default", "clkreq_output";
3718 pinctrl-0 = <&pcie1_clkreq &pcie1_perst>;
3719 pinctrl-1 = <&pcie1_clkreq_output &pcie1_perst>;
3720 #address-cells = <3>;
3721 #size-cells = <2>;
3722 device_type = "pci";
3723 ranges = <0x81000000 0 0 0 0x11C01000 0 0x00010000 /* downstream I/O */
3724 0x82000000 0 0x11C11000 0 0x11C11000 0 0x3EEFFF>; /* non-prefetchable memory */
3725 #interrupt-cells = <1>;
3726 interrupt-map-mask = <0 0 0 0>;
3727 interrupt-map = <0 0 0 0 &gic 0 346 0x4>;
3728 ip-ver = <0x889500>;
3729 num-lanes = <1>;
3730 msi-base = <200>;
3731 ch-num = <1>;
3732 pcie-clk-num = <1>;
3733 phy-clk-num = <0>;
3734 pcie-pm-qos-int = <0>;
3735 use-cache-coherency = "true";
3736 use-msi = "false";
3737 use-sicd = "true";
3738 status = "disabled";
3739 };
3740
3741 /* Secure log */
3742 seclog {
3743 compatible = "samsung,exynos-seclog";
3744 interrupts = <0 68 0>;
3745 };
3746
3747 /* Secure RPMB */
3748 ufs-srpmb {
3749 compatible = "samsung,ufs-srpmb";
3750 interrupts = <0 69 0>;
3751 };
3752
3753 /* tbase */
3754 tee {
3755 compatible = "samsung,exynos-tee";
3756 interrupts = <0 233 0>;
3757 };
3758
3759 fips-fmp {
3760 compatible = "samsung,exynos-fips-fmp";
3761 };
3762
3763 mfc_0: mfc0@13CE0000 {
3764 compatible = "samsung,mfc-v6";
3765 reg = <0x0 0x13CE0000 0x10000>;
3766 interrupts = <0 208 0>;
3767 clock-names = "aclk_mfc";
3768 clocks = <&clock GATE_MFC>;
3769 iommus = <&sysmmu_mfc0_0>, <&sysmmu_mfc0_1>;
3770 samsung,power-domain = <&pd_mfc>;
3771 status = "ok";
3772 ip_ver = <15>;
3773 clock_rate = <400000000>;
3774 min_rate = <100000>;
3775 num_qos_steps = <8>;
3776 max_mb = <4757298>;
3777 mfc_qos_table {
3778 mfc_qos_variant_0 {
3779 thrd_mb = <0>;
3780 freq_mfc = <89000>;
3781 freq_int = <107000>;
3782 freq_mif = <286000>;
3783 freq_cpu = <0>;
3784 freq_kfc = <0>;
3785 mo_value = <0>;
3786 mo_10bit_value = <0>;
3787 time_fw = <923>;
3788 };
3789 mfc_qos_variant_1 {
3790 thrd_mb = <259787>;
3791 freq_mfc = <267000>;
3792 freq_int = <267000>;
3793 freq_mif = <421000>;
3794 freq_cpu = <0>;
3795 freq_kfc = <0>;
3796 mo_value = <0>;
3797 mo_10bit_value = <0>;
3798 time_fw = <431>;
3799 };
3800 mfc_qos_variant_2 {
3801 thrd_mb = <535550>;
3802 freq_mfc = <400000>;
3803 freq_int = <400000>;
3804 freq_mif = <845000>;
3805 freq_cpu = <0>;
3806 freq_kfc = <0>;
3807 mo_value = <0>;
3808 mo_10bit_value = <0>;
3809 time_fw = <261>;
3810 };
3811 mfc_qos_variant_3 {
3812 thrd_mb = <1153791>;
3813 freq_mfc = <400000>;
3814 freq_int = <400000>;
3815 freq_mif = <1352000>;
3816 freq_cpu = <0>;
3817 freq_kfc = <0>;
3818 mo_value = <0>;
3819 mo_10bit_value = <0>;
3820 time_fw = <226>;
3821 };
3822 mfc_qos_variant_4 {
3823 thrd_mb = <1884284>;
3824 freq_mfc = <667000>;
3825 freq_int = <533000>;
3826 freq_mif = <1794000>;
3827 freq_cpu = <0>;
3828 freq_kfc = <0>;
3829 mo_value = <0>;
3830 mo_10bit_value = <0>;
3831 time_fw = <161>;
3832 };
3833 mfc_qos_variant_5 {
3834 thrd_mb = <2713968>;
3835 freq_mfc = <667000>;
3836 freq_int = <533000>;
3837 freq_mif = <1014000>;
3838 freq_cpu = <0>;
3839 freq_kfc = <0>;
3840 mo_value = <1>;
3841 mo_10bit_value = <0>;
3842 time_fw = <196>;
3843 };
3844 mfc_qos_variant_6 {
3845 thrd_mb = <3267739>;
3846 freq_mfc = <667000>;
3847 freq_int = <533000>;
3848 freq_mif = <1794000>;
3849 freq_cpu = <0>;
3850 freq_kfc = <0>;
3851 mo_value = <1>;
3852 mo_10bit_value = <0>;
3853 time_fw = <161>;
3854 };
3855 mfc_qos_variant_7 {
3856 thrd_mb = <4517358>;
3857 freq_mfc = <667000>;
3858 freq_int = <533000>;
3859 freq_mif = <1794000>;
3860 freq_cpu = <0>;
3861 freq_kfc = <0>;
3862 mo_value = <0>;
3863 mo_10bit_value = <1>;
3864 time_fw = <161>;
3865 };
3866 };
3867 };
3868
3869 iommu-domain_mfc {
3870 compatible = "samsung,exynos-iommu-bus";
3871 #address-cells = <2>;
3872 #size-cells = <1>;
3873 domain-clients = <&mfc_0>;
3874 };
3875
3876 sysmmu_mfc0_0: sysmmu@0x13c80000 {
3877 compatible = "samsung,exynos-sysmmu";
3878 reg = <0x0 0x13c80000 0x3000>;
3879 interrupts = <0 198 0>, <0 199 0>;
3880 clock-names = "aclk";
3881 clocks = <&clock GATE_SMMU_MFCD0>;
3882 port-name = "MFC0";
3883 sysmmu,secure-irq;
3884 sysmmu,secure_base = <0x13C90000>;
3885 sysmmu,tlb_property =
3886 <(SYSMMU_PUBLIC_NO_PREFETCH | SYSMMU_BL4) SYSMMU_NOID>;
3887 #iommu-cells = <0>;
3888 };
3889
3890 sysmmu_mfc0_1: sysmmu@0x13ca0000 {
3891 compatible = "samsung,exynos-sysmmu";
3892 reg = <0x0 0x13ca0000 0x3000>;
3893 interrupts = <0 201 0>, <0 202 0>;
3894 clock-names = "aclk";
3895 clocks = <&clock GATE_SMMU_MFCD1>;
3896 port-name = "MFC1";
3897 sysmmu,secure-irq;
3898 sysmmu,secure_base = <0x13CB0000>;
3899 sysmmu,tlb_property =
3900 <(SYSMMU_PUBLIC_NO_PREFETCH | SYSMMU_BL4) SYSMMU_NOID>;
3901 #iommu-cells = <0>;
3902 };
3903
3904 iva: iva@0x13600000 {
3905 compatible = "samsung,iva";
3906 reg = <0x0 0x13600000 0x200000>;
3907
3908 iommus = <&sysmmu_iva>;
3909
3910 interrupt-names = "iva_mbox_irq";
3911 interrupts = <0 236 0>;
3912
3913 clocks = <&clock GATE_IVA>;
3914 clock-names = "clk_iva";
3915 samsung,power-domain = <&pd_iva>;
3916
3917 mcu-info {
3918 mem_size = <0x20000>;
3919 shmem_size = <0x1000>;
3920 print_delay = <0>; /* us */
3921 };
3922 };
3923
3924 sysmmu_iva: sysmmu@13530000 {
3925 compatible = "samsung,exynos-sysmmu";
3926 reg = <0x0 0x13530000 0x3000>;
3927 interrupts = <0 240 0>;
3928 clock-names = "aclk";
3929 clocks = <&clock GATE_SMMU_IVA>;
3930 #iommu-cells = <0>;
3931 };
3932
3933 score: score@134C0000 {
3934 compatible = "samsung,score";
3935 dma-coherent;
3936 reg = <0x0 0x134C0000 0x20000>;
3937 interrupts = <0 227 0>;
3938
3939 clocks = <&clock GATE_SCORE>;
3940 clock-names = "dsp";
3941 samsung,power-domain = <&pd_dsp>;
3942
3943 iommus = <&sysmmu_score0>;
3944 };
3945 #if 0
3946 iommu-domain_score {
3947 compatible = "samsung,exynos-iommu-bus";
3948 #address-cells = <2>;
3949 #size-cells = <1>;
3950 ranges;
3951
3952 domain-clients = <&score>;
3953 };
3954 #endif
3955 iommu-domain_iva_score {
3956 compatible = "samsung,exynos-iommu-bus";
3957 #dma-address-cells = <1>;
3958 #dma-size-cells = <1>;
3959
3960 /* start address, size : 0x80000000 - bug*/
3961 dma-window = <0x80000000 0x70000000>;
3962
3963 domain-clients = <&iva>, <&score>;
3964 };
3965
3966 sysmmu_score0: sysmmu@13430000 {
3967 compatible = "samsung,exynos-sysmmu";
3968 reg = <0x0 0x13430000 0x3000>;
3969 interrupts = <0 230 0>, <0 231 0>;
3970 qos = <15>;
3971 clock-names = "aclk";
3972 clocks = <&clock GATE_SMMU_SCORE>;
3973 port-name = "Score";
3974 sysmmu,secure-irq;
3975 sysmmu,secure_base = <0x13450000>;
3976 sysmmu,tlb_property =
3977 <(SYSMMU_PRIV_ID_NO_PREFETCH_READ | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0x1)>,
3978 <(SYSMMU_PUBLIC_NO_PREFETCH | SYSMMU_BL8) SYSMMU_NOID>;
3979 #iommu-cells = <0>;
3980 };
3981
3982 fimc_is: fimc_is@13140000 {
3983 compatible = "samsung,exynos5-fimc-is";
3984 #pb-id-cells = <6>;
3985 reg = <0x0 0x12CE0000 0x10000>, /* CSIS-DMA */
3986 <0x0 0x13030000 0x10000>, /* FIMC-3AAW */
3987 <0x0 0x13130000 0x10000>, /* FIMC-3AA */
3988 <0x0 0x13040000 0x10000>, /* FIMC_ISPLP */
3989 <0x0 0x13140000 0x10000>, /* FIMC_ISPHQ */
3990 <0x0 0x12C40000 0x10000>, /* FIMC_TPU0 */
3991 <0x0 0x12C90000 0x10000>, /* FIMC_TPU1 */
3992 <0x0 0x12C50000 0x10000>, /* MC_SCALER */
3993 <0x0 0x12C60000 0x10000>, /* FIMC-VRA (Set A) */
3994 <0x0 0x12C70000 0x10000>, /* FIMC-VRA (Set B) */
3995 <0x0 0x12F00000 0x10000>, /* DCP */
3996 <0x0 0x14300000 0x10000>; /* SRDZ */
3997 interrupts = <0 294 0>, /* 3AAW_0 */
3998 <0 295 0>, /* 3AAW_1 */
3999 <0 301 0>, /* 3AA_0 */
4000 <0 302 0>, /* 3AA_1 */
4001 <0 296 0>, /* ISPLP_0 */
4002 <0 297 0>, /* ISPLP_1 */
4003 <0 303 0>, /* ISPHQ_0 */
4004 <0 304 0>, /* ISPHQ_1 */
4005 <0 272 0>, /* TPU0_0 */
4006 <0 273 0>, /* TPU0_1 */
4007 <0 284 0>, /* TPU1_0 */
4008 <0 285 0>, /* TPU1_1 */
4009 <0 274 0>, /* MC_SC_0 */
4010 <0 275 0>, /* MC_SC_1 */
4011 <0 276 0>, /* VRA_0 */
4012 <0 277 0>, /* VRA_1 */
4013 <0 242 0>, /* DCP_0 */
4014 <0 243 0>, /* DCP_1 */
4015 <0 85 0>; /* SRDZ */
4016 samsung,power-domain = <&pd_dcam>;
4017 clocks = <&clock GATE_ISP_EWGEN_ISPHQ>,
4018 <&clock GATE_IS_ISPHQ_3AA>,
4019 <&clock GATE_IS_ISPHQ_ISPHQ>,
4020 <&clock GATE_IS_ISPHQ_QE_3AA>,
4021 <&clock GATE_IS_ISPHQ_QE_ISPHQ>,
4022 <&clock GATE_ISPHQ_CMU_ISPHQ>,
4023 <&clock GATE_PMU_ISPHQ>,
4024 <&clock GATE_SYSREG_ISPHQ>,
4025 <&clock UMUX_CLKCMU_ISPHQ_BUS>,
4026
4027 <&clock GATE_ISP_EWGEN_ISPLP>,
4028 <&clock GATE_IS_ISPLP_3AAW>,
4029 <&clock GATE_IS_ISPLP_ISPLP>,
4030 <&clock GATE_IS_ISPLP_QE_3AAW>,
4031 <&clock GATE_IS_ISPLP_QE_ISPLP>,
4032 <&clock GATE_IS_ISPLP_SMMU_ISPLP>,
4033 <&clock GATE_IS_ISPLP_BCM_ISPLP>,
4034 <&clock GATE_BTM_ISPLP>,
4035 <&clock GATE_ISPLP_CMU_ISPLP>,
4036 <&clock GATE_PMU_ISPLP>,
4037 <&clock GATE_SYSREG_ISPLP>,
4038 <&clock UMUX_CLKCMU_ISPLP_BUS>,
4039
4040 <&clock GATE_ISP_EWGEN_CAM>,
4041 <&clock GATE_IS_CAM_CSIS0>,
4042 <&clock GATE_IS_CAM_CSIS1>,
4043 <&clock GATE_IS_CAM_CSIS2>,
4044 <&clock GATE_IS_CAM_CSIS3>,
4045 <&clock GATE_IS_CAM_MC_SCALER>,
4046 <&clock GATE_IS_CAM_CSISX4_DMA>,
4047 <&clock GATE_IS_CAM_SYSMMU_CAM0>,
4048 <&clock GATE_IS_CAM_SYSMMU_CAM1>,
4049 <&clock GATE_IS_CAM_BCM_CAM0>,
4050 <&clock GATE_IS_CAM_BCM_CAM1>,
4051 <&clock GATE_IS_CAM_TPU0>,
4052 <&clock GATE_IS_CAM_VRA>,
4053 <&clock GATE_IS_CAM_QE_TPU0>,
4054 <&clock GATE_IS_CAM_QE_VRA>,
4055 <&clock GATE_IS_CAM_BNS>,
4056 <&clock GATE_IS_CAM_QE_CSISX4>,
4057 <&clock GATE_IS_CAM_QE_TPU1>,
4058 <&clock GATE_IS_CAM_TPU1>,
4059 <&clock GATE_BTM_CAMD0>,
4060 <&clock GATE_BTM_CAMD1>,
4061 <&clock GATE_CAM_CMU_CAM>,
4062 <&clock GATE_PMU_CAM>,
4063 <&clock GATE_SYSREG_CAM>,
4064 <&clock UMUX_CLKCMU_CAM_BUS>,
4065 <&clock UMUX_CLKCMU_CAM_TPU0>,
4066 <&clock UMUX_CLKCMU_CAM_VRA>,
4067 <&clock UMUX_CLKCMU_CAM_TPU1>,
4068
4069 <&clock GATE_DCP>,
4070 <&clock GATE_BTM_DCAM>,
4071 <&clock GATE_DCAM_CMU_DCAM>,
4072 <&clock GATE_PMU_DCAM>,
4073 <&clock GATE_BCM_DCAM>,
4074 <&clock GATE_SYSREG_DCAM>,
4075 <&clock UMUX_CLKCMU_DCAM_BUS>,
4076 <&clock UMUX_CLKCMU_DCAM_IMGD>,
4077
4078 <&clock GATE_SRDZ>,
4079 <&clock GATE_BTM_SRDZ>,
4080 <&clock GATE_PMU_SRDZ>,
4081 <&clock GATE_BCM_SRDZ>,
4082 <&clock GATE_SMMU_SRDZ>,
4083 <&clock GATE_SRDZ_CMU_SRDZ>,
4084 <&clock GATE_SYSREG_SRDZ>,
4085 <&clock UMUX_CLKCMU_SRDZ_BUS>,
4086 <&clock UMUX_CLKCMU_SRDZ_IMGD>,
4087
4088 <&clock CIS_CLK0>,
4089 <&clock CIS_CLK1>,
4090 <&clock CIS_CLK2>,
4091 <&clock CIS_CLK3>,
4092
4093 <&clock GATE_DFTMUX_TOP_CIS_CLK0>,
4094 <&clock GATE_DFTMUX_TOP_CIS_CLK1>,
4095 <&clock GATE_DFTMUX_TOP_CIS_CLK2>,
4096 <&clock GATE_DFTMUX_TOP_CIS_CLK3>;
4097 clock-names = "GATE_ISP_EWGEN_ISPHQ",
4098 "GATE_IS_ISPHQ_3AA",
4099 "GATE_IS_ISPHQ_ISPHQ",
4100 "GATE_IS_ISPHQ_QE_3AA",
4101 "GATE_IS_ISPHQ_QE_ISPHQ",
4102 "GATE_ISPHQ_CMU_ISPHQ",
4103 "GATE_PMU_ISPHQ",
4104 "GATE_SYSREG_ISPHQ",
4105 "UMUX_CLKCMU_ISPHQ_BUS",
4106
4107 "GATE_ISP_EWGEN_ISPLP",
4108 "GATE_IS_ISPLP_3AAW",
4109 "GATE_IS_ISPLP_ISPLP",
4110 "GATE_IS_ISPLP_QE_3AAW",
4111 "GATE_IS_ISPLP_QE_ISPLP",
4112 "GATE_IS_ISPLP_SMMU_ISPLP",
4113 "GATE_IS_ISPLP_BCM_ISPLP",
4114 "GATE_BTM_ISPLP",
4115 "GATE_ISPLP_CMU_ISPLP",
4116 "GATE_PMU_ISPLP",
4117 "GATE_SYSREG_ISPLP",
4118 "UMUX_CLKCMU_ISPLP_BUS",
4119
4120 "GATE_ISP_EWGEN_CAM",
4121 "GATE_IS_CAM_CSIS0",
4122 "GATE_IS_CAM_CSIS1",
4123 "GATE_IS_CAM_CSIS2",
4124 "GATE_IS_CAM_CSIS3",
4125 "GATE_IS_CAM_MC_SCALER",
4126 "GATE_IS_CAM_CSISX4_DMA",
4127 "GATE_IS_CAM_SYSMMU_CAM0",
4128 "GATE_IS_CAM_SYSMMU_CAM1",
4129 "GATE_IS_CAM_BCM_CAM0",
4130 "GATE_IS_CAM_BCM_CAM1",
4131 "GATE_IS_CAM_TPU0",
4132 "GATE_IS_CAM_VRA",
4133 "GATE_IS_CAM_QE_TPU0",
4134 "GATE_IS_CAM_QE_VRA",
4135 "GATE_IS_CAM_BNS",
4136 "GATE_IS_CAM_QE_CSISX4",
4137 "GATE_IS_CAM_QE_TPU1",
4138 "GATE_IS_CAM_TPU1",
4139 "GATE_BTM_CAMD0",
4140 "GATE_BTM_CAMD1",
4141 "GATE_CAM_CMU_CAM",
4142 "GATE_PMU_CAM",
4143 "GATE_SYSREG_CAM",
4144 "UMUX_CLKCMU_CAM_BUS",
4145 "UMUX_CLKCMU_CAM_TPU0",
4146 "UMUX_CLKCMU_CAM_VRA",
4147 "UMUX_CLKCMU_CAM_TPU1",
4148
4149 "GATE_DCP",
4150 "GATE_BTM_DCAM",
4151 "GATE_DCAM_CMU_DCAM",
4152 "GATE_PMU_DCAM",
4153 "GATE_BCM_DCAM",
4154 "GATE_SYSREG_DCAM",
4155 "UMUX_CLKCMU_DCAM_BUS",
4156 "UMUX_CLKCMU_DCAM_IMGD",
4157
4158 "GATE_SRDZ",
4159 "GATE_BTM_SRDZ",
4160 "GATE_PMU_SRDZ",
4161 "GATE_BCM_SRDZ",
4162 "GATE_SMMU_SRDZ",
4163 "GATE_SRDZ_CMU_SRDZ",
4164 "GATE_SYSREG_SRDZ",
4165 "UMUX_CLKCMU_SRDZ_BUS",
4166 "UMUX_CLKCMU_SRDZ_IMGD",
4167
4168 "CIS_CLK0",
4169 "CIS_CLK1",
4170 "CIS_CLK2",
4171 "CIS_CLK3",
4172
4173 "MUX_CIS_CLK0",
4174 "MUX_CIS_CLK1",
4175 "MUX_CIS_CLK2",
4176 "MUX_CIS_CLK3";
4177 status = "ok";
4178 iommus = <&sysmmu_cam0>, <&sysmmu_cam1>, <&sysmmu_isp>, <&sysmmu_dcam>;
4179 #cooling-cells = <2>; /* min followed by max */
4180 };
4181
4182 mipi_phy_csis0_m4s4_top: dphy_m4s4_csis0@0x12C21050 {
4183 compatible = "samsung,mipi-phy-m4s4-top";
4184 samsung,pmu-syscon = <&pmu_system_controller>;
4185 isolation = <0x70C>; /* PMU address offset */
4186 reg = <0x0 0x12C21050 0x4>; /* SYSREG address for reset */
4187 reset = <0>; /* reset bit */
4188 owner = <1>; /* 0: DSI, 1: CSI */
4189 #phy-cells = <1>;
4190 };
4191
4192 mipi_phy_csis2_m4s4_mod: dphy_m4s4_csis2@0x12C21050 {
4193 compatible = "samsung,mipi-phy-m4s4-mod";
4194 samsung,pmu-syscon = <&pmu_system_controller>;
4195 isolation = <0x710>; /* PMU address offset */
4196 reset = <1>; /* reset bit */
4197 owner = <1>; /* 0: DSI, 1: CSI */
4198 #phy-cells = <1>;
4199 };
4200
4201 mipi_phy_csis1_m1s2s2: dphy_m1s2s2_csis1@0x12C21050 {
4202 compatible = "samsung,mipi-phy-m1s2s2";
4203 samsung,pmu-syscon = <&pmu_system_controller>;
4204 isolation = <0x730>; /* PMU address offset */
4205 reset = <2>; /* reset bit */
4206 owner = <1>; /* 0: DSI, 1: CSI */
4207 #phy-cells = <1>;
4208 };
4209
4210 mipi_phy_csis3_m1s2s2: dphy_m1s2s2_csis3@0x12C21050 {
4211 compatible = "samsung,mipi-phy-m1s2s2";
4212 samsung,pmu-syscon = <&pmu_system_controller>;
4213 isolation = <0x730>; /* PMU address offset */
4214 reset = <3>; /* reset bit */
4215 owner = <1>; /* 0: DSI, 1: CSI */
4216 #phy-cells = <1>;
4217 };
4218
4219 fimc_is_sensor0: fimc_is_sensor@12CA0000 {
4220 /* BACK/CSIS0 */
4221 compatible = "samsung,exynos5-fimc-is-sensor";
4222 #pb-id-cells = <4>;
4223 reg = <0x0 0x12CA0000 0x10000>, /* MIPI-CSI0 */
4224 <0x0 0x12C80000 0x10000>; /* FIMC-BNS */
4225 interrupts = <0 264 0>, /* MIPI-CSI0 */
4226 <0 291 0>; /* FIMC-BNS */
4227 samsung,power-domain = <&pd_cam>;
4228 phys = <&mipi_phy_csis0_m4s4_top 0>;
4229 phy-names = "csis_dphy";
4230 clocks = <&clock CIS_CLK0>,
4231 <&clock CIS_CLK1>,
4232 <&clock CIS_CLK2>,
4233 <&clock CIS_CLK3>,
4234
4235 <&clock GATE_DFTMUX_TOP_CIS_CLK0>,
4236 <&clock GATE_DFTMUX_TOP_CIS_CLK1>,
4237 <&clock GATE_DFTMUX_TOP_CIS_CLK2>,
4238 <&clock GATE_DFTMUX_TOP_CIS_CLK3>,
4239
4240 <&clock GATE_IS_CAM_CSIS0>,
4241 <&clock GATE_IS_CAM_CSIS1>,
4242 <&clock GATE_IS_CAM_CSIS2>,
4243 <&clock GATE_IS_CAM_CSIS3>;
4244 clock-names = "CIS_CLK0",
4245 "CIS_CLK1",
4246 "CIS_CLK2",
4247 "CIS_CLK3",
4248
4249 "MUX_CIS_CLK0",
4250 "MUX_CIS_CLK1",
4251 "MUX_CIS_CLK2",
4252 "MUX_CIS_CLK3",
4253
4254 "GATE_IS_CAM_CSIS0",
4255 "GATE_IS_CAM_CSIS1",
4256 "GATE_IS_CAM_CSIS2",
4257 "GATE_IS_CAM_CSIS3";
4258 iommus = <&sysmmu_cam0>;
4259 };
4260
4261 fimc_is_sensor1: fimc_is_sensor@12CB0000 {
4262 compatible = "samsung,exynos5-fimc-is-sensor";
4263 #pb-id-cells = <4>;
4264 reg = <0x0 0x12CB0000 0x10000>, /* MIPI-CSI1 */
4265 <0x0 0x12C80000 0x10000>; /* FIMC-BNS */
4266 interrupts = <0 266 0>, /* MIPI-CSI1 */
4267 <0 291 0>; /* FIMC-BNS */
4268 samsung,power-domain = <&pd_cam>;
4269 phys = <&mipi_phy_csis1_m1s2s2 0>;
4270 phy-names = "csis_dphy";
4271 clocks = <&clock CIS_CLK0>,
4272 <&clock CIS_CLK1>,
4273 <&clock CIS_CLK2>,
4274 <&clock CIS_CLK3>,
4275
4276 <&clock GATE_DFTMUX_TOP_CIS_CLK0>,
4277 <&clock GATE_DFTMUX_TOP_CIS_CLK1>,
4278 <&clock GATE_DFTMUX_TOP_CIS_CLK2>,
4279 <&clock GATE_DFTMUX_TOP_CIS_CLK3>,
4280
4281 <&clock GATE_IS_CAM_CSIS0>,
4282 <&clock GATE_IS_CAM_CSIS1>,
4283 <&clock GATE_IS_CAM_CSIS2>,
4284 <&clock GATE_IS_CAM_CSIS3>;
4285 clock-names = "CIS_CLK0",
4286 "CIS_CLK1",
4287 "CIS_CLK2",
4288 "CIS_CLK3",
4289
4290 "MUX_CIS_CLK0",
4291 "MUX_CIS_CLK1",
4292 "MUX_CIS_CLK2",
4293 "MUX_CIS_CLK3",
4294
4295 "GATE_IS_CAM_CSIS0",
4296 "GATE_IS_CAM_CSIS1",
4297 "GATE_IS_CAM_CSIS2",
4298 "GATE_IS_CAM_CSIS3";
4299 iommus = <&sysmmu_cam0>;
4300 };
4301
4302 fimc_is_sensor2: fimc_is_sensor@12CC0000 {
4303 /* DEPTH/CSIS2 */
4304 compatible = "samsung,exynos5-fimc-is-sensor";
4305 #pb-id-cells = <4>;
4306 reg = <0x0 0x12CC0000 0x10000>, /* MIPI-CSI2 */
4307 <0x0 0x12C80000 0x10000>; /* FIMC-BNS */
4308 interrupts = <0 268 0>, /* MIPI-CSI2 */
4309 <0 291 0>; /* FIMC-BNS */
4310 samsung,power-domain = <&pd_cam>;
4311 phys = <&mipi_phy_csis2_m4s4_mod 0>;
4312 phy-names = "csis_dphy";
4313 clocks = <&clock CIS_CLK0>,
4314 <&clock CIS_CLK1>,
4315 <&clock CIS_CLK2>,
4316 <&clock CIS_CLK3>,
4317
4318 <&clock GATE_DFTMUX_TOP_CIS_CLK0>,
4319 <&clock GATE_DFTMUX_TOP_CIS_CLK1>,
4320 <&clock GATE_DFTMUX_TOP_CIS_CLK2>,
4321 <&clock GATE_DFTMUX_TOP_CIS_CLK3>,
4322
4323 <&clock GATE_IS_CAM_CSIS0>,
4324 <&clock GATE_IS_CAM_CSIS1>,
4325 <&clock GATE_IS_CAM_CSIS2>,
4326 <&clock GATE_IS_CAM_CSIS3>;
4327 clock-names = "CIS_CLK0",
4328 "CIS_CLK1",
4329 "CIS_CLK2",
4330 "CIS_CLK3",
4331
4332 "MUX_CIS_CLK0",
4333 "MUX_CIS_CLK1",
4334 "MUX_CIS_CLK2",
4335 "MUX_CIS_CLK3",
4336
4337 "GATE_IS_CAM_CSIS0",
4338 "GATE_IS_CAM_CSIS1",
4339 "GATE_IS_CAM_CSIS2",
4340 "GATE_IS_CAM_CSIS3";
4341 iommus = <&sysmmu_cam0>;
4342 };
4343
4344 fimc_is_sensor3: fimc_is_sensor@112CD000 {
4345 /* IRIS/CSIS3 */
4346 compatible = "samsung,exynos5-fimc-is-sensor";
4347 #pb-id-cells = <4>;
4348 reg = <0x0 0x12CD0000 0x10000>, /* MIPI-CSI3 */
4349 <0x0 0x12C80000 0x10000>; /* FIMC-BNS */
4350 interrupts = <0 270 0>, /* MIPI-CSI3 */
4351 <0 291 0>; /* FIMC-BNS */
4352 samsung,power-domain = <&pd_cam>;
4353 phys = <&mipi_phy_csis3_m1s2s2 0>, <&mipi_phy_csis1_m1s2s2 0>;
4354 phy-names = "csis_dphy", "extra_csis_dphy";
4355 clocks = <&clock CIS_CLK0>,
4356 <&clock CIS_CLK1>,
4357 <&clock CIS_CLK2>,
4358 <&clock CIS_CLK3>,
4359
4360 <&clock GATE_DFTMUX_TOP_CIS_CLK0>,
4361 <&clock GATE_DFTMUX_TOP_CIS_CLK1>,
4362 <&clock GATE_DFTMUX_TOP_CIS_CLK2>,
4363 <&clock GATE_DFTMUX_TOP_CIS_CLK3>,
4364
4365 <&clock GATE_IS_CAM_CSIS0>,
4366 <&clock GATE_IS_CAM_CSIS1>,
4367 <&clock GATE_IS_CAM_CSIS2>,
4368 <&clock GATE_IS_CAM_CSIS3>;
4369 clock-names = "CIS_CLK0",
4370 "CIS_CLK1",
4371 "CIS_CLK2",
4372 "CIS_CLK3",
4373
4374 "MUX_CIS_CLK0",
4375 "MUX_CIS_CLK1",
4376 "MUX_CIS_CLK2",
4377 "MUX_CIS_CLK3",
4378
4379 "GATE_IS_CAM_CSIS0",
4380 "GATE_IS_CAM_CSIS1",
4381 "GATE_IS_CAM_CSIS2",
4382 "GATE_IS_CAM_CSIS3";
4383 iommus = <&sysmmu_cam0>;
4384 };
4385
4386 iommu-domain_cam {
4387 compatible = "samsung,exynos-iommu-bus";
4388 #address-cells = <2>;
4389 #size-cells = <1>;
4390 ranges;
4391 domain-clients = <&fimc_is>, <&fimc_is_sensor0>, <&fimc_is_sensor1>,
4392 <&fimc_is_sensor2>, <&fimc_is_sensor3>;
4393 };
4394
4395 sysmmu_cam0: sysmmu@12D10000 {
4396 compatible = "samsung,exynos-sysmmu";
4397 reg = <0x0 0x12D10000 0x3000>;
4398 interrupts = <0 279 0>, <0 280 0>;
4399 qos = <15>;
4400 clock-names = "aclk";
4401 clocks = <&clock GATE_IS_CAM_SYSMMU_CAM0>;
4402 port-name = "CAM0";
4403 sysmmu,secure-irq;
4404 sysmmu,secure_base = <0x12D00000>;
4405 /* Dual CAM scenario */
4406 sysmmu,tlb_property =
4407 /* 0~9 : CSIS0~3 */
4408 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID_MASK(0x0, 0x3F)>,
4409 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID_MASK(0x4, 0x3F)>,
4410 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID_MASK(0x8, 0x3F)>,
4411 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID_MASK(0x10, 0x3F)>,
4412 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID_MASK(0x14, 0x3F)>,
4413 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID_MASK(0x18, 0x3F)>,
4414 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID_MASK(0x20, 0x3F)>,
4415 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID_MASK(0x24, 0x3F)>,
4416 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID_MASK(0x28, 0x3F)>,
4417 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID_MASK(0x30, 0x3F)>,
4418 /* 10~13 : TPU1_ID */
4419 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL4) SYSMMU_ID(0x7)>,
4420 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID(0x3)>,
4421 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID(0x7)>,
4422 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID(0xB)>,
4423 /* 14~17 : TPU0_ID */
4424 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL4) SYSMMU_ID(0x5)>,
4425 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID(0x1)>,
4426 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID(0x5)>,
4427 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID(0x9)>,
4428 /* 18~19 : VRA Ch0 */
4429 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL4) SYSMMU_ID(0x6)>,
4430 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL4) SYSMMU_ID(0x6)>,
4431 /* 20~21 : TPU1_ADDR */
4432 <(SYSMMU_PRIV_ADDR_PREFETCH_ASCENDING_READ | SYSMMU_BL4) SYSMMU_NOID>,
4433 <(SYSMMU_PRIV_ADDR_PREFETCH_ASCENDING_READ | SYSMMU_BL4) SYSMMU_NOID>,
4434 /* 22~23 : TPU0_ADDR */
4435 <(SYSMMU_PRIV_ADDR_PREFETCH_ASCENDING_READ | SYSMMU_BL4) SYSMMU_NOID>,
4436 <(SYSMMU_PRIV_ADDR_PREFETCH_ASCENDING_READ | SYSMMU_BL4) SYSMMU_NOID>,
4437 /* 24~27 : VRA Ch1 */
4438 <(SYSMMU_PUBLIC_PREFETCH_ASCENDING | SYSMMU_BL1) SYSMMU_NOID>;
4439 #iommu-cells = <0>;
4440 };
4441
4442 sysmmu_cam1: sysmmu@12D20000 {
4443 compatible = "samsung,exynos-sysmmu";
4444 reg = <0x0 0x12D20000 0x3000>;
4445 interrupts = <0 282 0>;
4446 qos = <15>;
4447 clock-names = "aclk";
4448 clocks = <&clock GATE_IS_CAM_SYSMMU_CAM1>;
4449 port-name = "CAM1";
4450 sysmmu,tlb_property =
4451 /* 0~17 : MCScaler */
4452 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL1) SYSMMU_ID(0x0)>,
4453 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL1) SYSMMU_ID(0x1)>,
4454 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL1) SYSMMU_ID(0x2)>,
4455 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x0)>,
4456 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x1)>,
4457 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x2)>,
4458 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x3)>,
4459 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x4)>,
4460 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x5)>,
4461 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x6)>,
4462 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x7)>,
4463 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x8)>,
4464 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x9)>,
4465 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0xA)>,
4466 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0xB)>,
4467 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0xC)>,
4468 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0xD)>,
4469 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0xE)>,
4470 /* 18~19 : SBB */
4471 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL1) SYSMMU_ID(0x3)>,
4472 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0xF)>;
4473 #iommu-cells = <0>;
4474 };
4475
4476 sysmmu_isp: sysmmu@13050000 {
4477 compatible = "samsung,exynos-sysmmu";
4478 reg = <0x0 0x13050000 0x3000>;
4479 interrupts = <0 298 0>, <0 299 0>;
4480 qos = <15>;
4481 clock-names = "aclk";
4482 clocks = <&clock GATE_IS_ISPLP_SMMU_ISPLP>;
4483 port-name = "ISP";
4484 sysmmu,secure-irq;
4485 sysmmu,secure_base = <0x13060000>;
4486 sysmmu,tlb_property =
4487 /* 0~11 : 3AAW */
4488 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL1) SYSMMU_ID(0x0)>,
4489 <(SYSMMU_PRIV_ID_NO_PREFETCH_WRITE | SYSMMU_BL2) SYSMMU_ID(0x0)>,
4490 <(SYSMMU_PRIV_ID_NO_PREFETCH_WRITE | SYSMMU_BL2) SYSMMU_ID(0x4)>,
4491 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x24)>,
4492 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0xC)>,
4493 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x20)>,
4494 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x8)>,
4495 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x18)>,
4496 <(SYSMMU_PRIV_ID_NO_PREFETCH_READ | SYSMMU_BL2) SYSMMU_ID(0x4)>,
4497 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x14)>,
4498 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x1C)>,
4499 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x10)>,
4500 /* 12~14 : ISPLP */
4501 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL1) SYSMMU_ID(0x2)>,
4502 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x1)>,
4503 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x5)>,
4504 /* 15~20 : 3AA */
4505 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL1) SYSMMU_ID(0x2)>,
4506 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x2)>,
4507 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0xA)>,
4508 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x22)>,
4509 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x12)>,
4510 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x1A)>,
4511 /* 21~28 : ISPHQ */
4512 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL1) SYSMMU_ID(0x6)>,
4513 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL1) SYSMMU_ID(0x1E)>,
4514 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL1) SYSMMU_ID(0x26)>,
4515 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x26)>,
4516 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x16)>,
4517 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x2E)>,
4518 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0x6)>,
4519 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL1) SYSMMU_ID(0xE)>,
4520 /* 29 : 3AAW/ISPLP/ISPHQ */
4521 <(SYSMMU_PUBLIC_NO_PREFETCH | SYSMMU_BL2) SYSMMU_NOID>;
4522 #iommu-cells = <0>;
4523 };
4524
4525 sysmmu_dcam: sysmmu@14230000 {
4526 compatible = "samsung,exynos-sysmmu";
4527 reg = <0x0 0x14230000 0x3000>;
4528 interrupts = <0 248 0>, <0 249 0>;
4529 qos = <15>;
4530 clock-names = "aclk";
4531 clocks = <&clock GATE_SMMU_SRDZ>;
4532 port-name = "DCP, SRDZ";
4533 sysmmu,secure-irq;
4534 sysmmu,secure_base = <0x14250000>;
4535 sysmmu,tlb_property =
4536 /* 0~10 : DCP */
4537 <(SYSMMU_PRIV_ID_NO_PREFETCH_READ | SYSMMU_BL16) SYSMMU_ID(0x1)>,
4538 <(SYSMMU_PRIV_ID_NO_PREFETCH_READ | SYSMMU_BL16) SYSMMU_ID(0x3)>,
4539 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL8) SYSMMU_ID(0x5)>,
4540 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL8) SYSMMU_ID(0x7)>,
4541 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL8) SYSMMU_ID(0x9)>,
4542 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL8) SYSMMU_ID(0x1)>,
4543 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL8) SYSMMU_ID(0x3)>,
4544 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL8) SYSMMU_ID(0x5)>,
4545 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL8) SYSMMU_ID(0x7)>,
4546 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL8) SYSMMU_ID(0x9)>,
4547 <(SYSMMU_PRIV_ID_NO_PREFETCH_WRITE | SYSMMU_BL16) SYSMMU_ID(0xB)>,
4548 /* 11~15 : SRDZ */
4549 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL8) SYSMMU_ID(0x0)>,
4550 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL16) SYSMMU_ID(0x2)>,
4551 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_READ | SYSMMU_BL16) SYSMMU_ID(0x6)>,
4552 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL16) SYSMMU_ID(0x0)>,
4553 <(SYSMMU_PRIV_ID_PREFETCH_ASCENDING_WRITE | SYSMMU_BL16) SYSMMU_ID(0x2)>;
4554 #iommu-cells = <0>;
4555 };
4556
4557 earlytmu: earlytmu@10080000 {
4558 compatible = "samsung,exynos8895-earlytmu";
4559 reg = <0x0 0x10080000 0x400>;
4560 };
4561
4562 tmuctrl_0: MNGS@10080000 {
4563 compatible = "samsung,exynos8895-tmu";
4564 reg = <0x0 0x10080000 0x400>;
4565 interrupts = <0 451 0>;
4566 tmu_name = "MNGS";
4567 id = <0>;
4568 sensors = <61>;
4569 sensing_mode = "balance";
4570 hotplug_enable = <1>;
4571 hotplug_in_threshold = <91>;
4572 hotplug_out_threshold = <96>;
4573 #include "exynos8895-tmu-sensor-conf.dtsi"
4574 };
4575
4576 tmuctrl_1: APOLLO@10080000 {
4577 compatible = "samsung,exynos8895-tmu";
4578 reg = <0x0 0x10080000 0x400>;
4579 interrupts = <0 451 0>;
4580 tmu_name = "APOLLO";
4581 id = <1>;
4582 sensors = <2>;
4583 sensing_mode = "max";
4584 #include "exynos8895-tmu-sensor-conf.dtsi"
4585 };
4586
4587 tmuctrl_2: GPU@10084000 {
4588 compatible = "samsung,exynos8895-tmu";
4589 reg = <0x0 0x10084000 0x400>;
4590 interrupts = <0 452 0>;
4591 tmu_name = "GPU";
4592 id = <2>;
4593 sensors = <1>;
4594 sensing_mode = "max";
4595 /* gpu cooling related table */
4596 /* flags, driver_data(index), frequency */
4597 gpu_idx_num = <6>;
4598 gpu_cooling_table = < 0 0 546000
4599 0 1 455000
4600 0 2 385000
4601 0 3 338000
4602 0 4 260000
4603 0 5 TABLE_END>;
4604 #include "exynos8895-tmu-sensor-conf.dtsi"
4605 };
4606
4607 tmuctrl_3: ISP@10084000 {
4608 compatible = "samsung,exynos8895-tmu";
4609 reg = <0x0 0x10084000 0x400>;
4610 interrupts = <0 452 0>;
4611 tmu_name = "ISP";
4612 id = <3>;
4613 sensors = <6>;
4614 sensing_mode = "max";
4615 #include "exynos8895-tmu-sensor-conf.dtsi"
4616 };
4617
4618 thermal-zones {
4619 mngs_thermal: mngs-thermal {
4620 zone_name = "MNGS_THERMAL";
4621 polling-delay-passive = <50>;
4622 polling-delay = <1000>;
4623 thermal-sensors = <&tmuctrl_0>;
4624 governor = "power_allocator";
4625 sustainable-power = <2000>;
4626 k_po = <100>;
4627 k_pu = <85>;
4628 k_i = <100>;
4629 i_max = <1500>;
4630 integral_cutoff = <28>;
4631
4632 trips {
4633 mngs_cold: mngs-cold {
4634 temperature = <20000>;
4635 hysteresis = <5000>; /* millicelsius */
4636 type = "active";
4637 };
4638 mngs_alert0: mngs-alert0 {
4639 temperature = <55000>; /* millicelsius */
4640 hysteresis = <2000>; /* millicelsius */
4641 type = "active";
4642 };
4643 mngs_alert1: mngs-alert1 {
4644 temperature = <83000>; /* millicelsius */
4645 hysteresis = <5000>; /* millicelsius */
4646 type = "passive";
4647 };
4648 mngs_hot: mngs-hot {
4649 temperature = <115000>; /* millicelsius */
4650 hysteresis = <5000>; /* millicelsius */
4651 type = "hot";
4652 };
4653 };
4654
4655 cooling-maps {
4656 map0 {
4657 trip = <&mngs_alert0>;
4658 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4659 };
4660 map1 {
4661 trip = <&mngs_alert1>;
4662 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4663 };
4664 };
4665 };
4666
4667 apo_thermal: APOLLO {
4668 zone_name = "APO_THERMAL";
4669 polling-delay-passive = <0>;
4670 polling-delay = <0>;
4671 thermal-sensors = <&tmuctrl_1>;
4672
4673 trips {
4674 apo_alert0: apo-alert0 {
4675 temperature = <20000>; /* millicelsius */
4676 hysteresis = <5000>; /* millicelsius */
4677 type = "active";
4678 };
4679 apo_alert1: apo-alert1 {
4680 temperature = <76000>; /* millicelsius */
4681 hysteresis = <5000>; /* millicelsius */
4682 type = "active";
4683 };
4684 apo_alert2: apo-alert2 {
4685 temperature = <81000>; /* millicelsius */
4686 hysteresis = <5000>; /* millicelsius */
4687 type = "active";
4688 };
4689 apo_alert3: apo-alert3 {
4690 temperature = <86000>; /* millicelsius */
4691 hysteresis = <5000>; /* millicelsius */
4692 type = "active";
4693 };
4694 apo_alert4: apo-alert4 {
4695 temperature = <91000>; /* millicelsius */
4696 hysteresis = <5000>; /* millicelsius */
4697 type = "active";
4698 };
4699 apo_alert5: apo-alert5 {
4700 temperature = <96000>; /* millicelsius */
4701 hysteresis = <5000>; /* millicelsius */
4702 type = "active";
4703 };
4704 apo_alert6: apo-alert6 {
4705 temperature = <101000>; /* millicelsius */
4706 hysteresis = <5000>; /* millicelsius */
4707 type = "active";
4708 };
4709 apo_hot: apo-hot {
4710 temperature = <115000>; /* millicelsius */
4711 hysteresis = <5000>; /* millicelsius */
4712 type = "hot";
4713 };
4714 };
4715
4716 cooling-maps {
4717 map0 {
4718 trip = <&apo_alert0>;
4719 /* Corresponds to 1586MHz at freq_table */
4720 cooling-device = <&cpu0 0 0>;
4721 };
4722 map1 {
4723 trip = <&apo_alert1>;
4724 /* Corresponds to 1482MHz at freq_table */
4725 cooling-device = <&cpu0 0 0>;
4726 };
4727 map2 {
4728 trip = <&apo_alert2>;
4729 /* Corresponds to 1378MHz at freq_table */
4730 cooling-device = <&cpu0 0 0>;
4731 };
4732 map3 {
4733 trip = <&apo_alert3>;
4734 /* Corresponds to 1170MHz at freq_table */
4735 cooling-device = <&cpu0 0 0>;
4736 };
4737 map4 {
4738 trip = <&apo_alert4>;
4739 /* Corresponds to 1066MHz at freq_table */
4740 cooling-device = <&cpu0 0 0>;
4741 };
4742 map5 {
4743 trip = <&apo_alert5>;
4744 /* Corresponds to 442MHz at freq_table */
4745 cooling-device = <&cpu0 0 0>;
4746 };
4747 map6 {
4748 trip = <&apo_alert6>;
4749 /* Corresponds to 442MHz at freq_table */
4750 cooling-device = <&cpu0 0 0>;
4751 };
4752 map7 {
4753 trip = <&apo_hot>;
4754 /* Corresponds to 442MHz at freq_table */
4755 cooling-device = <&cpu0 0 0>;
4756 };
4757 };
4758 };
4759
4760 gpu_thermal: GPU {
4761 zone_name = "GPU_THERMAL";
4762 polling-delay-passive = <100>;
4763 polling-delay = <0>;
4764 thermal-sensors = <&tmuctrl_2>;
4765 governor = "power_allocator";
4766 sustainable-power = <2000>;
4767 k_po = <60>;
4768 k_pu = <100>;
4769 k_i = <50>;
4770 i_max = <500>;
4771 integral_cutoff = <10>;
4772
4773 trips {
4774 gpu_cold: gpu-cold {
4775 temperature = <20000>;
4776 hysteresis = <5000>; /* millicelsius */
4777 type = "active";
4778 };
4779 gpu_alert0: gpu-alert0 {
4780 temperature = <78000>; /* millicelsius */
4781 hysteresis = <2000>; /* millicelsius */
4782 type = "active";
4783 };
4784 gpu_alert1: gpu-alert1 {
4785 temperature = <88000>; /* millicelsius */
4786 hysteresis = <5000>; /* millicelsius */
4787 type = "passive";
4788 };
4789 gpu_hot: gpu-hot {
4790 temperature = <115000>; /* millicelsius */
4791 hysteresis = <5000>; /* millicelsius */
4792 type = "hot";
4793 };
4794 };
4795
4796 cooling-maps {
4797 map0 {
4798 trip = <&gpu_alert0>;
4799 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4800 };
4801 map1 {
4802 trip = <&gpu_alert1>;
4803 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4804 };
4805 };
4806 };
4807
4808 isp_thermal: ISP {
4809 zone_name = "ISP_THERMAL";
4810 polling-delay-passive = <0>;
4811 polling-delay = <0>;
4812 thermal-sensors = <&tmuctrl_3>;
4813
4814 trips {
4815 isp_alert0: isp-alert0 {
4816 temperature = <20000>; /* millicelsius */
4817 hysteresis = <5000>; /* millicelsius */
4818 type = "active";
4819 };
4820 isp_alert1: isp-alert1 {
4821 temperature = <91000>; /* millicelsius */
4822 hysteresis = <5000>; /* millicelsius */
4823 type = "active";
4824 };
4825 isp_alert2: isp-alert2 {
4826 temperature = <96000>; /* millicelsius */
4827 hysteresis = <5000>; /* millicelsius */
4828 type = "active";
4829 };
4830 isp_alert3: isp-alert3 {
4831 temperature = <101000>; /* millicelsius */
4832 hysteresis = <5000>; /* millicelsius */
4833 type = "active";
4834 };
4835 isp_hot: isp-hot {
4836 temperature = <115000>; /* millicelsius */
4837 hysteresis = <5000>; /* millicelsius */
4838 type = "hot";
4839 };
4840 };
4841
4842 cooling-maps {
4843 map0 {
4844 trip = <&isp_alert0>;
4845 /* Corresponds to No limit */
4846 cooling-device = <&fimc_is 0 0>;
4847 };
4848 map1 {
4849 trip = <&isp_alert1>;
4850 /* Corresponds to No limit */
4851 cooling-device = <&fimc_is 0 0>;
4852 };
4853 map2 {
4854 trip = <&isp_alert2>;
4855 /* Corresponds to 15fps at freq_table */
4856 cooling-device = <&fimc_is 0 0>;
4857 };
4858 map3 {
4859 trip = <&isp_alert3>;
4860 /* Corresponds to 5fps at freq_table */
4861 cooling-device = <&fimc_is 0 0>;
4862 };
4863 map4 {
4864 trip = <&isp_hot>;
4865 /* Corresponds to HW trip */
4866 cooling-device = <&fimc_is 0 0>;
4867 };
4868 };
4869 };
4870
4871 };
4872
4873 input_booster {
4874 status = "okay";
4875 compatible = "input_booster";
4876 #address-cells = <1>;
4877 #size-cells = <0>;
4878
4879 booster_key@1 {
4880 input_booster,label = "KEY";
4881 input_booster,type = <0>; /* BOOSTER_DEVICE_KEY */
4882
4883 input_booster,levels = <1>;
4884
4885 /* Frequency table */
4886 /* for level : 1_Head */
4887 input_booster,cpu_freqs = <1066000>;
4888 input_booster,hmp_boost = <1>;
4889 input_booster,kfc_freqs = <0>;
4890 input_booster,mif_freqs = <0>;
4891 input_booster,int_freqs = <0>;
4892
4893 /* Time table */
4894 input_booster,head_times = <500>;
4895 input_booster,tail_times = <500>;
4896 input_booster,phase_times = <0>;
4897 };
4898 booster_key@2 {
4899 input_booster,label = "TOUCHKEY";
4900 input_booster,type = <1>; /* BOOSTER_DEVICE_TOUCHKEY */
4901
4902 input_booster,levels = <1>;
4903
4904 /* Frequency table */
4905 /* for level : 1_Head */
4906 input_booster,cpu_freqs = <1066000>;
4907 input_booster,hmp_boost = <1>;
4908 input_booster,kfc_freqs = <0>;
4909 input_booster,mif_freqs = <0>;
4910 input_booster,int_freqs = <0>;
4911
4912 /* Time table */
4913 input_booster,head_times = <0>;
4914 input_booster,tail_times = <200>;
4915 input_booster,phase_times = <0>;
4916 };
4917 booster_key@3 {
4918 input_booster,label = "TOUCH";
4919 input_booster,type = <2>; /* BOOSTER_DEVICE_TOUCH */
4920
4921 input_booster,levels = <1 2 3>;
4922
4923 /* Frequency table */
4924 /* for level : 1_Head, 2_Head, 2_Tail */
4925 input_booster,cpu_freqs = <1066000 1066000 858000>;
4926 input_booster,hmp_boost = <1 1 1>;
4927 input_booster,kfc_freqs = <832000 832000 832000>;
4928 input_booster,mif_freqs = <0 0 0>;
4929 input_booster,int_freqs = <0 0 0>;
4930
4931 /* Time table */
4932 input_booster,head_times = <130 130 0>;
4933 input_booster,tail_times = <0 0 500>;
4934 input_booster,phase_times = <0 0 0>;
4935 };
4936 booster_key@4 { // Input Booster +
4937 input_booster,label = "MULTITOUCH";
4938 input_booster,type = <3>; /* BOOSTER_DEVICE_MULTITOUCH */
4939
4940 input_booster,levels = <1 2>;
4941
4942 /* Frequency table */
4943 /* for level : 1_Head 2_Tail*/
4944 input_booster,cpu_freqs = <1066000 858000>;
4945 input_booster,hmp_boost = <1 1>;
4946 input_booster,kfc_freqs = <832000 832000>;
4947 input_booster,mif_freqs = <0 0>;
4948 input_booster,int_freqs = <0 0>;
4949
4950 /* Time table */
4951 input_booster,head_times = <1000 0>;
4952 input_booster,tail_times = <0 500>;
4953 input_booster,phase_times = <0 0>;
4954 };
4955 booster_key@5 {
4956 input_booster,label = "KEYBOARD";
4957 input_booster,type = <4>; /* BOOSTER_DEVICE_KEYBOARD */
4958
4959 input_booster,levels = <1 2>;
4960
4961 /* Frequency table */
4962 /* for level : 1_Head 2_Tail*/
4963 input_booster,cpu_freqs = <1066000 1066000>;
4964 input_booster,hmp_boost = <1 1>;
4965 input_booster,kfc_freqs = <832000 832000>;
4966 input_booster,mif_freqs = <0 0>;
4967 input_booster,int_freqs = <0 0>;
4968
4969 /* Time table */
4970 input_booster,head_times = <130 130>;
4971 input_booster,tail_times = <0 0>;
4972 input_booster,phase_times = <0 0>;
4973 };
4974 booster_key@6 {
4975 input_booster,label = "MOUSE";
4976 input_booster,type = <5>; /* BOOSTER_DEVICE_MOUSE */
4977
4978 input_booster,levels = <1 2>;
4979
4980 /* Frequency table */
4981 /* for level : 1_Head 2_Tail*/
4982 input_booster,cpu_freqs = <1066000 858000>;
4983 input_booster,hmp_boost = <1 1>;
4984 input_booster,kfc_freqs = <832000 832000>;
4985 input_booster,mif_freqs = <0 0>;
4986 input_booster,int_freqs = <0 0>;
4987
4988 /* Time table */
4989 input_booster,head_times = <130 0>;
4990 input_booster,tail_times = <0 500>;
4991 input_booster,phase_times = <0 0>;
4992 };
4993 booster_key@7 {
4994 input_booster,label = "MOUSE WHEEL";
4995 input_booster,type = <6>; /* BOOSTER_DEVICE_MOUSE */
4996
4997 input_booster,levels = <1 2>;
4998
4999 /* Frequency table */
5000 /* for level : 1_Head 2_Tail*/
5001 input_booster,cpu_freqs = <1066000 0>;
5002 input_booster,hmp_boost = <1 0>;
5003 input_booster,kfc_freqs = <832000 0>;
5004 input_booster,mif_freqs = <0 0>;
5005 input_booster,int_freqs = <0 0>;
5006
5007 /* Time table */
5008 input_booster,head_times = <130 0>;
5009 input_booster,tail_times = <0 0>;
5010 input_booster,phase_times = <0 0>;
5011 };
5012 booster_key@8 {
5013 input_booster,label = "PEN HOVER";
5014 input_booster,type = <7>; /* BOOSTER_DEVICE_MOUSE */
5015
5016 input_booster,levels = <1 2>;
5017
5018 /* Frequency table */
5019 /* for level : 1_Head 2_Tail*/
5020 input_booster,cpu_freqs = <1066000 858000>;
5021 input_booster,hmp_boost = <1 1>;
5022 input_booster,kfc_freqs = <832000 832000>;
5023 input_booster,mif_freqs = <0 0>;
5024 input_booster,int_freqs = <0 0>;
5025
5026 /* Time table */
5027 input_booster,head_times = <130 0>;
5028 input_booster,tail_times = <0 500>;
5029 input_booster,phase_times = <0 0>;
5030 };
5031 booster_key@9 {
5032 input_booster,label = "PEN";
5033 input_booster,type = <8>; /* BOOSTER_DEVICE_MOUSE */
5034
5035 input_booster,levels = <1 2>;
5036
5037 /* Frequency table */
5038 /* for level : 1_Head 2_Tail*/
5039 input_booster,cpu_freqs = <1469000 858000>;
5040 input_booster,hmp_boost = <1 1>;
5041 input_booster,kfc_freqs = <832000 832000>;
5042 input_booster,bimc_freqs = <0 0>;
5043
5044 /* Time table */
5045 input_booster,head_times = <200 0>;
5046 input_booster,tail_times = <0 600>;
5047 };
5048 booster_key@10 {
5049 input_booster,label = "KEY_TWO";
5050 input_booster,type = <9>; /* BOOSTER_DEVICE_KEY */
5051
5052 input_booster,levels = <1>;
5053
5054 /* Frequency table */
5055 /* for level : 1_Head */
5056 input_booster,cpu_freqs = <1469000>;
5057 input_booster,hmp_boost = <1>;
5058 input_booster,kfc_freqs = <0>;
5059 input_booster,mif_freqs = <0>;
5060 input_booster,int_freqs = <0>;
5061
5062 /* Time table */
5063 input_booster,head_times = <700>;
5064 input_booster,tail_times = <700>;
5065 input_booster,phase_times = <0>;
5066 }; // Input Booster -
5067 /* If you need to add new key type, add it this position */
5068 };
5069
5070 rtc@16490000 {
5071 compatible = "samsung,exynos8-rtc";
5072 reg = <0x0 0x16490000 0x100>;
5073 interrupts = <0 79 0>, <0 78 0>;
5074 };
5075
5076 cpufreq-ufc {
5077 /* Ctrl Type */
5078 #define PM_QOS_MIN_LIMIT 0
5079 #define PM_QOS_MIN_WO_BOOST_LIMIT 1
5080 #define PM_QOS_MAX_LIMIT 2
5081 /* Execution Mode */
5082 #define AARCH64_MODE 0
5083 #define AARCH32_MODE 1
5084
5085 domain@0 {
5086 device_type = "cpufreq-userctrl";
5087 shared-cpus = "0-3";
5088
5089 user-default-qos = <715000>;
5090 };
5091
5092 domain@1 {
5093 device_type = "cpufreq-userctrl";
5094 shared-cpus = "4-7";
5095
5096 user-default-qos = <962000>;
5097
5098 min-limit {
5099 ctrl-type = <PM_QOS_MIN_LIMIT>;
5100 execution-mode = <AARCH64_MODE>;
5101 /* big lit */
5102 table = < 2314000 1690000
5103 2158000 715000
5104 2002000 715000
5105 1937000 715000
5106 1807000 715000
5107 1703000 715000
5108 1469000 715000
5109 1261000 715000
5110 1170000 715000
5111 1066000 715000
5112 962000 715000
5113 858000 715000
5114 741000 715000>;
5115 };
5116
5117 max-limit {
5118 ctrl-type = <PM_QOS_MAX_LIMIT>;
5119 execution-mode = <AARCH64_MODE>;
5120 /* big lit */
5121 table = < 2314000 1690000
5122 2158000 1690000
5123 2002000 1690000
5124 1937000 1690000
5125 1807000 1690000
5126 1703000 1690000
5127 1469000 1690000
5128 1261000 1690000
5129 1170000 1690000
5130 1066000 1690000
5131 962000 1690000
5132 858000 1690000
5133 741000 1690000 >;
5134 };
5135
5136 };
5137 };
5138 };