include/scsc/api/bsmhcp.h

   1 /****************************************************************************
   2  *
   3  * Copyright (c) 2014 - 2016 Samsung Electronics Co., Ltd. All rights reserved
   4  *
   5  ****************************************************************************/
   6
   7 /****************************************************************************
   8  * FILE
   9  *      bsmhcp.h  -  Bluetooth Shared Memory Host Controller Protocol
  10  *
  11  * DESCRIPTION
  12  *      This file specifies the layout of the Bluetooth Shared Memory
  13  *      Host Controller Protocol as described in SC-505753-DD
  14  */
  15
  16 #ifndef __BSMHCP_H__
  17 #define __BSMHCP_H__
  18
  19 #define BSMHCP_TRANSFER_RING_CMD_SIZE           (8)
  20 #define BSMHCP_TRANSFER_RING_EVT_SIZE           (32)
  21 #define BSMHCP_TRANSFER_RING_ACL_SIZE           (32)
  22 #define BSMHCP_TRANSFER_RING_AVDTP_SIZE         (16)
  23 #define BSMHCP_TRANSFER_RING_IQ_REPORT_SIZE     (8)
  24
  25 /* Of the buffers in BSMHCP_TRANSFER_RING_ACL_SIZE, reserve a number for ULP
  26  * operation. */
  27 #define BSMHCP_TRANSFER_RING_ACL_ULP_RESERVED   (4)
  28 #define BSMHCP_TRANSFER_RING_SCO_SIZE           (0)
  29 #define BSMHCP_TRANSFER_RING_ACL_COUNT          (36)
  30 #define BSMHCP_TRANSFER_RING_TIMING_COUNT       (64)
  31
  32 #define BSMHCP_CMD_EVT_BUFFER_SIZE              (258)
  33 #define BSMHCP_ACL_BUFFER_SIZE                  (1024)
  34 #define BSMHCP_IQ_REPORT_BUFFER_SIZE            (164)
  35
  36 #define BSMHCP_ACL_PACKET_SIZE                  (1021)
  37 #define BSMHCP_ULP_PACKET_SIZE                  BSMHCP_ACL_PACKET_SIZE
  38 #define BSMHCP_SCO_PACKET_SIZE                  (0)
  39
  40 #define BSMHCP_DATA_BUFFER_CMD_SIZE \
  41                 BSMHCP_TRANSFER_RING_CMD_SIZE
  42 #define BSMHCP_DATA_BUFFER_EVT_SIZE \
  43                 BSMHCP_TRANSFER_RING_EVT_SIZE
  44 #define BSMHCP_DATA_BUFFER_TX_ACL_SIZE \
  45                 (BSMHCP_TRANSFER_RING_ACL_SIZE - 2)
  46 #define BSMHCP_DATA_BUFFER_RX_ACL_SIZE \
  47                 BSMHCP_TRANSFER_RING_ACL_SIZE
  48
  49 #define BSMHCP_EVENT_TYPE_NONE                  (0x00)
  50 #define BSMHCP_EVENT_TYPE_CONNECTED             (0x01)
  51 #define BSMHCP_EVENT_TYPE_DISCONNECTED          (0x02)
  52 #define BSMHCP_EVENT_TYPE_IQ_REPORT_ENABLED     (0x03)
  53 #define BSMHCP_EVENT_TYPE_IQ_REPORT_DISABLED    (0x04)
  54
  55 #define BSMHCP_ACL_BC_FLAG_BCAST_NON            (0x00)
  56 #define BSMHCP_ACL_BC_FLAG_BCAST_ACTIVE         (0x40)
  57 #define BSMHCP_ACL_BC_FLAG_BCAST_ALL            (0x80)
  58 #define BSMHCP_ACL_BC_FLAG_BCAST_RSVD           (0xC0)
  59 #define BSMHCP_ACL_BC_FLAG_BCAST_MASK           (0xC0)
  60
  61 #define BSMHCP_ACL_PB_FLAG_START_NONFLUSH       (0x00)
  62 #define BSMHCP_ACL_PB_FLAG_CONT                 (0x10)
  63 #define BSMHCP_ACL_PB_FLAG_START_FLUSH          (0x20)
  64 #define BSMHCP_ACL_PB_FLAG_RSVD_3               (0x30)
  65 #define BSMHCP_ACL_PB_FLAG_MASK                 (0x30)
  66
  67 #define BSMHCP_ACL_L2CAP_FLAG_NON               (0x00)
  68 #define BSMHCP_ACL_L2CAP_FLAG_END               (0x01)
  69 #define BSMHCP_ACL_L2CAP_FLAG_MASK              (0x01)
  70
  71 #define BSMHCP_SERVICE_BT_STATE_INACTIVE        (0x00)
  72 #define BSMHCP_SERVICE_BT_STATE_ACTIVE          (0x01)
  73
  74 #define BSMHCP_CONTROLLER_STATE_ACTIVE          (0x00000001)
  75
  76 #define BSMHCP_HCI_CONNECTION_HANDLE_LOOPBACK   (0x4000)
  77
  78 #define BSMHCP_ALIGNMENT                        (32)
  79
  80 #define BSMHCP_FEATURE_LPA2DP                   (0x00000001)
  81 #define BSMHCP_FEATURE_M4_INTERRUPTS            (0x00000002)
  82 #define BSMHCP_FEATURE_FW_INFORMATION           (0x00000004)
  83 #define BSMHCP_FEATURE_AVDTP_TRANSFER_RING      (0x00000008)
  84
  85 #define BSMHCP_CONTROL_START_PANIC              (0x10DEAD01)
  86 #define BSMHCP_CONTROL_STOP_PANIC               (0x0201DEAD)
  87 #define BSMHCP_CONTROL_CONNECTION_PANIC         (0xDEAD2002)
  88
  89 #define BSMHCP_FW_INFO_USER_DEFINED_COUNT       (96)
  90
  91 #define BSMHCP_TIMING_SOURCE_ITIME              (0)
  92 #define BSMHCP_TIMING_SOURCE_ITIME_L1           (1)
  93 #define BSMHCP_TIMING_SOURCE_RADIO_TX           (2)
  94 #define BSMHCP_TIMING_SOURCE_RADIO_RX           (3)
  95 #define BSMHCP_TIMING_SOURCE_RADIO_LC           (4)
  96 #define BSMHCP_TIMING_SOURCE_COUNT              (5)
  97
  98 #define BSMHCP_INCREASE_INDEX(index, limit) \
  99                 ((index) = ((index) + 1) % (limit))
 100
 101 #define BSMHCP_HAS_ROOM(write, read, limit) \
 102                 ((((write) + 1) % (limit)) != (read))
 103
 104 struct BSMHCP_TD_CONTROL {
 105         uint16_t length;
 106         uint8_t  data[BSMHCP_CMD_EVT_BUFFER_SIZE];
 107 };
 108
 109 struct BSMHCP_TD_HCI_EVT {
 110         uint16_t length;
 111         uint16_t hci_connection_handle;
 112         uint16_t event_type;
 113         uint8_t  data[BSMHCP_CMD_EVT_BUFFER_SIZE];
 114 };
 115
 116 struct BSMHCP_TD_ACL_RX {
 117         uint16_t hci_connection_handle;
 118         uint16_t length;
 119         uint8_t  broadcast_flag;
 120         uint8_t  packet_boundary;
 121         uint8_t  disconnected;
 122         uint8_t  reserved;
 123         uint8_t  data[BSMHCP_ACL_BUFFER_SIZE];
 124 };
 125
 126 struct BSMHCP_TD_ACL_TX_DATA {
 127         uint16_t length;
 128         uint8_t  buffer_index;
 129         uint8_t  flags;
 130         uint16_t hci_connection_handle;
 131         uint16_t l2cap_cid;
 132 };
 133
 134 struct BSMHCP_TD_ACL_TX_FREE {
 135         uint8_t  buffer_index;
 136         uint8_t  reserved;
 137         uint16_t hci_connection_handle;
 138 };
 139
 140 struct BSMHCP_TD_AVDTP {
 141         uint32_t flags;
 142         uint16_t l2cap_cid;
 143         uint16_t hci_connection_handle;
 144         uint32_t reserved;
 145 };
 146
 147 struct BSMHCP_ACL_TR_DRV_INDEX {
 148         uint32_t read_free;
 149         uint32_t write_data;
 150 };
 151
 152 struct BSMHCP_ACL_TR_CTRL_INDEX {
 153         uint32_t read_data;
 154         uint32_t write_free;
 155 };
 156
 157 struct BSMHCP_INDEX {
 158         uint32_t read;
 159         uint32_t write;
 160 };
 161
 162 struct BSMHCP_TIMING_PACKET {
 163         uint16_t source;
 164         uint16_t sequence_number;
 165         uint32_t interrupt_enter;
 166         uint32_t critical_section_enter;
 167         uint32_t time[4];
 168         uint32_t critical_section_leave;
 169         uint32_t interrupt_leave;
 170 };
 171
 172 struct BSMHCP_FW_INFO {
 173         uint32_t r4_from_ap_interrupt_count;
 174         uint32_t m4_from_ap_interrupt_count;
 175         uint32_t r4_to_ap_interrupt_count;
 176         uint32_t m4_to_ap_interrupt_count;
 177         uint32_t bt_deep_sleep_time_total;
 178         uint32_t bt_deep_sleep_wakeup_duration;
 179         uint32_t sched_n_messages;
 180         uint32_t user_defined_count;
 181         uint32_t user_defined[BSMHCP_FW_INFO_USER_DEFINED_COUNT];
 182 };
 183
 184 struct BSMHCP_TD_IQ_REPORTING_EVT {
 185         uint8_t  subevent_code;
 186         uint8_t  packet_status;
 187         uint16_t connection_handle;
 188         uint16_t sync_handle;
 189         uint8_t  rx_phy;
 190         uint8_t  channel_index;
 191         int16_t  rssi;
 192         uint8_t  rssi_antenna_id;
 193         uint8_t  cte_type;
 194         uint8_t  slot_durations;
 195         uint8_t  sample_count;
 196         uint16_t event_count;
 197         uint8_t  data[BSMHCP_IQ_REPORT_BUFFER_SIZE];
 198 };
 199
 200 struct BSMHCP_HEADER {
 201         /* AP RW - M4/R4 RO - 64 octets */
 202         uint32_t                        magic_value;                /* 0x00 */
 203         uint16_t                        ap_to_fg_m4_int_src;        /* 0x04 */
 204         uint8_t                         service_request;            /* 0x06 */
 205         uint8_t                         reserved1;                  /* 0x07 */
 206         uint32_t                        acl_buffer_size;            /* 0x08 */
 207         uint32_t                        cmd_evt_buffer_size;        /* 0x0C */
 208         uint32_t                        acl_tx_buffers;             /* 0x10 */
 209         uint16_t                        ap_to_bg_int_src;           /* 0x14 */
 210         uint16_t                        ap_to_fg_int_src;           /* 0x16 */
 211         uint16_t                        bg_to_ap_int_src;           /* 0x18 */
 212         uint16_t                        fg_to_ap_int_src;           /* 0x1A */
 213         uint32_t                        mailbox_offset;             /* 0x1C */
 214         uint32_t                        reserved1_u32;              /* 0x20 */
 215         uint32_t                        mailbox_hci_cmd_write;      /* 0x24 */
 216         uint32_t                        mailbox_hci_evt_read;       /* 0x28 */
 217         uint32_t                        mailbox_acl_tx_write;       /* 0x2C */
 218         uint32_t                        mailbox_acl_free_read;      /* 0x30 */
 219         uint32_t                        mailbox_acl_rx_read;        /* 0x34 */
 220         uint32_t                        abox_offset;                /* 0x38 */
 221         uint32_t                        abox_length;                /* 0x3C */
 222
 223         /* AP RO - R4 RW - M4 NA - 32 octets */
 224         uint16_t                        panic_deathbed_confession;  /* 0x40 */
 225         uint16_t                        panic_diatribe_value;       /* 0x42 */
 226         uint32_t                        mailbox_hci_cmd_read;       /* 0x44 */
 227         uint32_t                        mailbox_hci_evt_write;      /* 0x48 */
 228         uint32_t                        controller_flags;           /* 0x4C */
 229         uint32_t                        firmware_features;          /* 0x50 */
 230         uint16_t                        reserved_u16;               /* 0x54 */
 231         uint8_t                         service_state;              /* 0x56 */
 232         uint8_t                         reserved_u8;                /* 0x57 */
 233         uint32_t                        reserved4_u32;              /* 0x58 */
 234         uint32_t                        mailbox_avdtp_read;         /* 0x5C */
 235
 236         /* AP RO - R4 NA - M4 RW - 32 octets */
 237         uint32_t                        mailbox_acl_tx_read;        /* 0x60 */
 238         uint32_t                        mailbox_acl_free_write;     /* 0x64 */
 239         uint32_t                        mailbox_acl_rx_write;       /* 0x68 */
 240         uint32_t                        mailbox_timing_write;       /* 0x6C */
 241         uint32_t                        mailbox_iq_report_write;    /* 0x70 */
 242         uint8_t                         reserved4[0x0C];            /* 0x74 */
 243
 244
 245         /* AP RO - R4/M4 RW - 32 octets */
 246         uint32_t                        reserved6_u32;              /* 0x80 */
 247         uint8_t                         reserved5[0x1C];            /* 0x84 */
 248
 249         /* AP RW - M4/R4 RO */
 250         uint32_t                        mailbox_timing_read;        /* 0xA0 */
 251         uint32_t                        mailbox_avdtp_write;        /* 0xA4 */
 252         uint32_t                        mailbox_iq_report_read;     /* 0xA8 */
 253         uint32_t                        reserved9_u32;              /* 0xAC */
 254         uint32_t                        reserved10_u32;             /* 0xB0 */
 255         uint32_t                        reserved11_u32;             /* 0xB4 */
 256         uint32_t                        reserved12_u32;             /* 0xB8 */
 257         uint16_t                        info_ap_to_bg_int_src;      /* 0xBC */
 258         uint16_t                        info_bg_to_ap_int_src;      /* 0xBE */
 259         uint32_t                        mxlog_filter;               /* 0xC0 */
 260         uint32_t                        firmware_control;           /* 0xC4 */
 261         uint8_t                         reserved6[0x24];            /* 0xC8 */
 262
 263         /* Obsolete region - not used */
 264         uint32_t                        smm_debug_read;             /* 0xEC */
 265         uint32_t                        smm_debug_write;            /* 0xF0 */
 266         uint32_t                        smm_exception;              /* 0xF4 */
 267         uint32_t                        avdtp_detect_stream_id;     /* 0xF8 */
 268         uint32_t                        smm_int_ready;              /* 0xFE */
 269 };
 270
 271 struct BSMHCP_PROTOCOL {
 272         /* header offset: 0x00000000 */
 273         volatile struct BSMHCP_HEADER header;
 274
 275         /* from AP */
 276         struct BSMHCP_TD_CONTROL /* offset: 0x00000100 */
 277                 hci_cmd_transfer_ring[BSMHCP_TRANSFER_RING_CMD_SIZE];
 278
 279         /* AVDTP detection */
 280         struct BSMHCP_TD_AVDTP /* offset: 0x00000920 */
 281                 avdtp_transfer_ring[BSMHCP_TRANSFER_RING_AVDTP_SIZE];
 282
 283         uint8_t /* offset: 0x000009E0 */
 284                 to_air_reserved[0x1FC0];
 285
 286         struct BSMHCP_TD_ACL_TX_DATA /* offset: 0x000029A0 */
 287                 acl_tx_data_transfer_ring[BSMHCP_TRANSFER_RING_ACL_SIZE];
 288
 289         uint8_t /* offset: 0x00002AA0 */
 290                 acl_tx_buffer[BSMHCP_DATA_BUFFER_TX_ACL_SIZE]
 291                              [BSMHCP_ACL_BUFFER_SIZE];
 292
 293         /* Padding used to ensure minimum 32 octets between sections */
 294         uint8_t reserved[0x20]; /* offset: 0x0000A2A0 */
 295
 296         /* to AP */
 297         struct BSMHCP_TD_HCI_EVT /* offset: 0x0000A2C0 */
 298                 hci_evt_transfer_ring[BSMHCP_TRANSFER_RING_EVT_SIZE];
 299
 300         struct BSMHCP_TIMING_PACKET /* offset: 0x0000C3C0 */
 301                 timing_transfer_ring[BSMHCP_TRANSFER_RING_TIMING_COUNT];
 302
 303         struct BSMHCP_FW_INFO /* offset: 0x0000CCC0 */
 304                 information;
 305
 306         uint8_t /* offset: 0x0000CCC0 + sizoef(struct BSMHCP_FW_INFO) */
 307                 from_air_reserved[0x11E0 - sizeof(struct BSMHCP_FW_INFO)];
 308
 309         struct BSMHCP_TD_IQ_REPORTING_EVT /* offset: 0x0000DEA0 */
 310                 iq_reporting_transfer_ring[BSMHCP_TRANSFER_RING_IQ_REPORT_SIZE];
 311
 312         struct BSMHCP_TD_ACL_RX /* offset: 0x0000E440 */
 313                 acl_rx_transfer_ring[BSMHCP_TRANSFER_RING_ACL_SIZE];
 314
 315         struct BSMHCP_TD_ACL_TX_FREE /* offset: 0x00016540 */
 316                 acl_tx_free_transfer_ring[BSMHCP_TRANSFER_RING_ACL_SIZE];
 317 };
 318
 319 #define BSMHCP_TD_ACL_RX_CONTROL_SIZE  \
 320                 (sizeof(struct BSMHCP_TD_ACL_RX) - BSMHCP_ACL_BUFFER_SIZE)
 321
 322 #define BSMHCP_PROTOCOL_MAGICVALUE \
 323                 ((BSMHCP_ACL_BUFFER_SIZE | BSMHCP_CMD_EVT_BUFFER_SIZE | \
 324                 (offsetof(struct BSMHCP_PROTOCOL, acl_tx_buffer) << 15)) ^ \
 325                 sizeof(struct BSMHCP_PROTOCOL))
 326
 327 #endif /* __BSMHCP_H__ */