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[9610] wlbt: SCSC Driver version 10.9.1.0
[GitHub/MotorolaMobilityLLC/kernel-slsi.git] / drivers / misc / samsung / scsc / platform_mif_3830.c
1 /****************************************************************************
2 *
3 * Copyright (c) 2014 - 2019 Samsung Electronics Co., Ltd. All rights reserved
4 *
5 ****************************************************************************/
6
7 /* Implements interface */
8
9 #include "platform_mif.h"
10
11 /* Interfaces it Uses */
12
13 #include <linux/version.h>
14 #include <linux/module.h>
15 #include <linux/interrupt.h>
16 #include <linux/pm_qos.h>
17 #include <linux/platform_device.h>
18 #include <linux/moduleparam.h>
19 #include <linux/iommu.h>
20 #include <linux/slab.h>
21 #include <linux/io.h>
22 #include <linux/smc.h>
23 #ifdef CONFIG_OF
24 #include <linux/of.h>
25 #include <linux/of_address.h>
26 #include <linux/of_platform.h>
27 #endif
28 #include <linux/mfd/syscon.h>
29 #include <linux/regmap.h>
30 #include <linux/delay.h>
31 #include <scsc/scsc_logring.h>
32 #include "mif_reg_S5E3830.h"
33 #include "platform_mif_module.h"
34 #ifdef CONFIG_ARCH_EXYNOS
35 #include <linux/soc/samsung/exynos-soc.h>
36 #endif
37 #ifdef CONFIG_SOC_EXYNOS3830
38 #include <linux/mfd/samsung/s2mpu12-regulator.h>
39 #endif
40
41 #ifdef CONFIG_SCSC_SMAPPER
42 #include <linux/dma-mapping.h>
43 #include "mif_reg_smapper.h"
44 #endif
45 #ifdef CONFIG_SCSC_QOS
46 #include <linux/pm_qos.h>
47 #endif
48
49 #if !defined(CONFIG_SOC_EXYNOS3830)
50 #error Target processor CONFIG_SOC_EXYNOS3830 not selected
51 #endif
52
53 #ifdef CONFIG_SCSC_LOG_COLLECTION
54 #include <scsc/scsc_log_collector.h>
55 #endif
56 /* Time to wait for CFG_REQ IRQ on 3830 */
57 #define WLBT_BOOT_TIMEOUT (HZ)
58
59 #ifdef CONFIG_OF_RESERVED_MEM
60 #include <linux/of_reserved_mem.h>
61 #endif
62 static unsigned long sharedmem_base;
63 static size_t sharedmem_size;
64
65 #ifdef CONFIG_SCSC_CHV_SUPPORT
66 static bool chv_disable_irq;
67 module_param(chv_disable_irq, bool, S_IRUGO | S_IWUSR);
68 MODULE_PARM_DESC(chv_disable_irq, "Do not register for irq");
69 #endif
70
71 static bool enable_platform_mif_arm_reset = true;
72 module_param(enable_platform_mif_arm_reset, bool, S_IRUGO | S_IWUSR);
73 MODULE_PARM_DESC(enable_platform_mif_arm_reset, "Enables WIFIBT ARM cores reset");
74
75 #ifdef CONFIG_SCSC_QOS
76 struct qos_table {
77 unsigned int freq_mif;
78 unsigned int freq_int;
79 unsigned int freq_cl0;
80 unsigned int freq_cl1;
81 };
82 #endif
83
84 struct platform_mif {
85 struct scsc_mif_abs interface;
86 struct scsc_mbox_s *mbox;
87 struct platform_device *pdev;
88
89 struct device *dev;
90
91 struct {
92 int irq_num;
93 int flags;
94 atomic_t irq_disabled_cnt;
95 } wlbt_irq[PLATFORM_MIF_NUM_IRQS];
96
97 /* MIF registers preserved during suspend */
98 struct {
99 u32 irq_bit_mask;
100 } mif_preserve;
101
102 /* register MBOX memory space */
103 size_t reg_start;
104 size_t reg_size;
105 void __iomem *base;
106
107 /* register CMU memory space */
108 struct regmap *cmu_base;
109
110 void __iomem *con0_base;
111
112 /* pmu syscon regmap */
113 struct regmap *pmureg;
114 #if defined(CONFIG_SOC_EXYNOS3830)
115 struct regmap *i3c_apm_pmic;
116 struct regmap *dbus_baaw;
117 struct regmap *pbus_baaw;
118 struct regmap *wlbt_remap;
119 struct regmap *boot_cfg;
120
121 /* Signalled when CFG_REQ IRQ handled */
122 struct completion cfg_ack;
123
124 /* State of CFG_REQ handler */
125 enum wlbt_boot_state {
126 WLBT_BOOT_IN_RESET = 0,
127 WLBT_BOOT_WAIT_CFG_REQ,
128 WLBT_BOOT_CFG_DONE,
129 WLBT_BOOT_CFG_ERROR
130 } boot_state;
131
132 #endif
133 #ifdef CONFIG_SCSC_SMAPPER
134 /* SMAPPER */
135 void __iomem *smapper_base;
136 u8 smapper_banks;
137 struct {
138 u8 bank;
139 u32 ws;
140 bool large;
141 struct scsc_mif_smapper_info bank_info;
142 } *smapper;
143 #endif
144 /* Shared memory space - reserved memory */
145 unsigned long mem_start;
146 size_t mem_size;
147 void __iomem *mem;
148
149 /* Callback function and dev pointer mif_intr manager handler */
150 void (*r4_handler)(int irq, void *data);
151 void *irq_dev;
152 /* spinlock to serialize driver access */
153 spinlock_t mif_spinlock;
154 void (*reset_request_handler)(int irq, void *data);
155 void *irq_reset_request_dev;
156
157 #ifdef CONFIG_SCSC_QOS
158 /* QoS table */
159 struct qos_table *qos;
160 bool qos_enabled;
161 #endif
162 /* Suspend/resume handlers */
163 int (*suspend_handler)(struct scsc_mif_abs *abs, void *data);
164 void (*resume_handler)(struct scsc_mif_abs *abs, void *data);
165 void *suspendresume_data;
166 };
167
168 static void power_supplies_on(struct platform_mif *platform);
169
170 extern int mx140_log_dump(void);
171
172 #define platform_mif_from_mif_abs(MIF_ABS_PTR) container_of(MIF_ABS_PTR, struct platform_mif, interface)
173
174 inline void platform_mif_reg_write(struct platform_mif *platform, u16 offset, u32 value)
175 {
176 writel(value, platform->base + offset);
177 }
178
179 inline u32 platform_mif_reg_read(struct platform_mif *platform, u16 offset)
180 {
181 return readl(platform->base + offset);
182 }
183
184 #ifdef CONFIG_SCSC_SMAPPER
185 inline void platform_mif_reg_write_smapper(struct platform_mif *platform, u16 offset, u32 value)
186 {
187 writel(value, platform->smapper_base + offset);
188 }
189
190 inline u32 platform_mif_reg_read_smapper(struct platform_mif *platform, u16 offset)
191 {
192 return readl(platform->smapper_base + offset);
193 }
194
195 #define PLATFORM_MIF_SHIFT_SMAPPER_ADDR 11 /* From 36 bits addres to 25 bits */
196 #define PLATFORM_MIF_SHIFT_SMAPPER_END 4 /* End address aligment */
197
198 /* Platform is responsible to give the phys mapping of the SMAPPER maps */
199 static int platform_mif_smapper_get_mapping(struct scsc_mif_abs *interface, u8 *phy_map, u16 *align)
200 {
201 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
202 u8 i;
203
204 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "Mapping %d banks\n", platform->smapper_banks);
205
206 if (!platform->smapper_banks)
207 return -EINVAL;
208
209 for (i = 0; i < platform->smapper_banks; i++) {
210 if (platform->smapper[i].large)
211 phy_map[i] = SCSC_MIF_ABS_LARGE_BANK;
212 else
213 phy_map[i] = SCSC_MIF_ABS_SMALL_BANK;
214 }
215
216 if (align)
217 *align = 1 << PLATFORM_MIF_SHIFT_SMAPPER_ADDR;
218
219 return 0;
220 }
221
222 static int platform_mif_smapper_get_bank_info(struct scsc_mif_abs *interface, u8 bank, struct scsc_mif_smapper_info *bank_info)
223 {
224 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
225
226 if (!platform->smapper_banks)
227 return -EINVAL;
228
229 bank_info->num_entries = platform->smapper[bank].bank_info.num_entries;
230 bank_info->mem_range_bytes = platform->smapper[bank].bank_info.mem_range_bytes;
231
232 return 0;
233 }
234
235 static u8 platform_mif_smapper_granularity_to_bits(u32 granularity)
236 {
237 if (granularity <= 2 * 1024)
238 return 0;
239 if (granularity <= 4 * 1024)
240 return 1;
241 if (granularity <= 8 * 1024)
242 return 2;
243 if (granularity <= 16 * 1024)
244 return 3;
245 if (granularity <= 32 * 1024)
246 return 4;
247 if (granularity <= 64 * 1024)
248 return 5;
249 if (granularity <= 128 * 1024)
250 return 6;
251 return 7;
252 }
253
254 static u32 platform_mif_smapper_get_bank_base_address(struct scsc_mif_abs *interface, u8 bank)
255 {
256 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
257
258 if (!platform->smapper)
259 return 0;
260
261 return platform->smapper[bank].ws;
262 }
263
264 /* Configure smapper according the memory map and range */
265 static void platform_mif_smapper_configure(struct scsc_mif_abs *interface, u32 granularity)
266 {
267 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
268 u8 i;
269 u8 gran;
270 u8 nb = platform->smapper_banks;
271
272 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "Configure SMAPPER with granularity %d\n", granularity);
273
274 gran = platform_mif_smapper_granularity_to_bits(granularity);
275
276 platform_mif_reg_write_smapper(platform, SMAPPER_QCH_DISABLE, 1);
277 platform_mif_reg_write_smapper(platform, ORIGIN_ADDR_AR, 0);
278 platform_mif_reg_write_smapper(platform, ORIGIN_ADDR_AW, 0);
279 /* Program SMAPPER memmap */
280 for (i = 0; i < nb; i++) {
281 /* Set ADDR_MAP_EN to 1'b0*/
282 platform_mif_reg_write_smapper(platform, ADDR_MAP_EN(i), 0);
283 /* Set START_ADDR */
284 platform_mif_reg_write_smapper(platform, START_ADDR(i), platform->smapper[i].ws);
285 /* Set ADDR_GRANULARITY - FIXED AT 4KB */
286 platform_mif_reg_write_smapper(platform, ADDR_GRANULARITY(i), gran);
287 /* WLAN_ADDR_MAP operation is started */
288 }
289 /* Set access window control (MSB 32bits Start/End address) */
290 /* Remapped address should be ranged from AW_START_ADDR to AW_EN_ADDR */
291 platform_mif_reg_write_smapper(platform, AW_START_ADDR, 0);
292 platform_mif_reg_write_smapper(platform, AW_END_ADDR, dma_get_mask(platform->dev) >> PLATFORM_MIF_SHIFT_SMAPPER_END);
293 smp_mb();
294 }
295
296 /* Caller is responsible of validating the phys address (alignment) */
297 static int platform_mif_smapper_write_sram(struct scsc_mif_abs *interface, u8 bank, u8 num_entries, u8 first_entry, dma_addr_t *addr)
298 {
299 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
300 u8 i;
301 u32 rb;
302
303 if (!platform->smapper_banks)
304 return -EINVAL;
305
306 if (!platform->smapper_base) {
307 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev, "SMAPPER not enabled\n");
308 return -EINVAL;
309 }
310
311 /* Set ADDR_MAP_EN to 1'b0*/
312 platform_mif_reg_write_smapper(platform, ADDR_MAP_EN(bank), 0);
313 /* Write mapping table to SRAM. Each entry consists of 25 bits MSB address to remap */
314 for (i = 0; i < num_entries; i++) {
315 if (!addr[i]) {
316 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev, "ADDR IS NULL at bank %d entry %d/%d\n", bank, first_entry + i, num_entries);
317 return -EINVAL;
318 }
319 /* Set SRAM_WRITE_CTRL to 1'b1*/
320 platform_mif_reg_write_smapper(platform, SRAM_WRITE_CTRL(bank), 1);
321 platform_mif_reg_write_smapper(platform, SRAM_BANK_INDEX(bank, first_entry + i), addr[i] >> PLATFORM_MIF_SHIFT_SMAPPER_ADDR);
322 /* check incorrect writings */
323 platform_mif_reg_write_smapper(platform, SRAM_WRITE_CTRL(bank), 0);
324 rb = platform_mif_reg_read_smapper(platform, SRAM_BANK_INDEX(bank, first_entry + i));
325 if (rb != addr[i] >> PLATFORM_MIF_SHIFT_SMAPPER_ADDR) {
326 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev, "incorrect mapping detected rb 0x%x, addr 0x%x\n", rb, (u32)addr[i] >> PLATFORM_MIF_SHIFT_SMAPPER_ADDR);
327 return -EFAULT;
328 }
329 }
330 platform_mif_reg_write_smapper(platform, ADDR_MAP_EN(bank), 1);
331 smp_mb();
332 return 0;
333 }
334
335 static int platform_mif_parse_smapper(struct platform_mif *platform, struct device_node *np, u8 num_banks)
336 {
337 /* SMAPPER parsing */
338 struct device_node *np_banks;
339 char node_name[50];
340 u32 val[2];
341 u8 i;
342 u32 bank = 0, ws = 0, wsz = 0, ent = 0, large = 0;
343
344 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "banks found: %d szof %zu\n", num_banks, sizeof(*platform->smapper));
345
346 platform->smapper = kmalloc_array(num_banks, sizeof(*platform->smapper), GFP_KERNEL);
347
348 if (!platform->smapper)
349 return -ENOMEM;
350
351 for (i = 0; i < num_banks; i++) {
352 snprintf(node_name, sizeof(node_name), "smapper_bank_%d", i);
353 np_banks = of_find_node_by_name(np, node_name);
354 if (!np_banks) {
355 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev, "%s: could not find smapper_bank\n",
356 node_name);
357 kfree(platform->smapper);
358 platform->smapper = NULL;
359 return -ENOENT;
360 }
361 of_property_read_u32(np_banks, "bank_num", &bank);
362 of_property_read_u32(np_banks, "fw_window_start", &ws);
363 of_property_read_u32(np_banks, "fw_window_size", &wsz);
364 of_property_read_u32(np_banks, "num_entries", &ent);
365 of_property_read_u32(np_banks, "is_large", &large);
366 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
367 "bank %d fw_w_start 0x%x fw_w_sz 0x%x entries %d is_large %d\n",
368 bank, ws, wsz, ent, large);
369
370 platform->smapper[i].bank = (u8)bank;
371 platform->smapper[i].ws = ws;
372 platform->smapper[i].large = (bool)large;
373 platform->smapper[i].bank_info.num_entries = ent;
374 platform->smapper[i].bank_info.mem_range_bytes = wsz;
375 }
376
377 /* Update the number of banks before returning */
378 platform->smapper_banks = num_banks;
379
380 of_property_read_u32_array(np, "smapper_reg", val, 2);
381 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
382 "smapper reg address 0x%x size 0x%x\n", val[0], val[1]);
383 platform->smapper_base =
384 devm_ioremap_nocache(platform->dev, val[0], val[1]);
385
386 if (!platform->smapper_base) {
387 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
388 "Error mapping smapper register region\n");
389 kfree(platform->smapper);
390 platform->smapper = NULL;
391 return -ENOENT;
392 }
393
394 return 0;
395 }
396 #endif
397 #ifdef CONFIG_SCSC_QOS
398 static int platform_mif_parse_qos(struct platform_mif *platform, struct device_node *np)
399 {
400 int len, i;
401
402 platform->qos_enabled = false;
403
404 len = of_property_count_u32_elems(np, "qos_table");
405 if (!(len == 12)) {
406 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
407 "No qos table for wlbt, or incorrect size\n");
408 return -ENOENT;
409 }
410
411 platform->qos = devm_kzalloc(platform->dev, sizeof(struct qos_table) * len / 4, GFP_KERNEL);
412 if (!platform->qos)
413 return -ENOMEM;
414
415 of_property_read_u32_array(np, "qos_table", (unsigned int *)platform->qos, len);
416
417 for (i = 0; i < len / 4; i++) {
418 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "QoS Table[%d] mif : %u int : %u cl0 : %u cl1: %u\n", i,
419 platform->qos[i].freq_mif,
420 platform->qos[i].freq_int,
421 platform->qos[i].freq_cl0,
422 platform->qos[i].freq_cl1);
423 }
424
425 platform->qos_enabled = true;
426 return 0;
427 }
428
429 struct qos_table platform_mif_pm_qos_get_table(struct platform_mif *platform, enum scsc_qos_config config)
430 {
431 struct qos_table table;
432
433 switch (config) {
434 case SCSC_QOS_MIN:
435 table.freq_mif = platform->qos[0].freq_mif;
436 table.freq_int = platform->qos[0].freq_int;
437 table.freq_cl0 = platform->qos[0].freq_cl0;
438 table.freq_cl1 = platform->qos[0].freq_cl1;
439 break;
440
441 case SCSC_QOS_MED:
442 table.freq_mif = platform->qos[1].freq_mif;
443 table.freq_int = platform->qos[1].freq_int;
444 table.freq_cl0 = platform->qos[1].freq_cl0;
445 table.freq_cl1 = platform->qos[1].freq_cl1;
446 break;
447
448 case SCSC_QOS_MAX:
449 table.freq_mif = platform->qos[2].freq_mif;
450 table.freq_int = platform->qos[2].freq_int;
451 table.freq_cl0 = platform->qos[2].freq_cl0;
452 table.freq_cl1 = platform->qos[2].freq_cl1;
453 break;
454
455 default:
456 table.freq_mif = 0;
457 table.freq_int = 0;
458 table.freq_cl0 = 0;
459 table.freq_cl1 = 0;
460 }
461
462 return table;
463 }
464
465 static int platform_mif_pm_qos_add_request(struct scsc_mif_abs *interface, struct scsc_mifqos_request *qos_req, enum scsc_qos_config config)
466 {
467 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
468 struct qos_table table;
469
470 if (!platform)
471 return -ENODEV;
472
473 if (!platform->qos_enabled) {
474 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "PM QoS not configured\n");
475 return -EOPNOTSUPP;
476 }
477
478 table = platform_mif_pm_qos_get_table(platform, config);
479
480 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
481 "PM QoS add request: %u. MIF %u INT %u CL0 %u CL1 %u\n", config, table.freq_mif, table.freq_int, table.freq_cl0, table.freq_cl1);
482
483 pm_qos_add_request(&qos_req->pm_qos_req_mif, PM_QOS_BUS_THROUGHPUT, table.freq_mif);
484 pm_qos_add_request(&qos_req->pm_qos_req_int, PM_QOS_DEVICE_THROUGHPUT, table.freq_int);
485 pm_qos_add_request(&qos_req->pm_qos_req_cl0, PM_QOS_CLUSTER0_FREQ_MIN, table.freq_cl0);
486 pm_qos_add_request(&qos_req->pm_qos_req_cl1, PM_QOS_CLUSTER1_FREQ_MIN, table.freq_cl1);
487
488 return 0;
489 }
490
491 static int platform_mif_pm_qos_update_request(struct scsc_mif_abs *interface, struct scsc_mifqos_request *qos_req, enum scsc_qos_config config)
492 {
493 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
494 struct qos_table table;
495
496 if (!platform)
497 return -ENODEV;
498
499 if (!platform->qos_enabled) {
500 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "PM QoS not configured\n");
501 return -EOPNOTSUPP;
502 }
503
504 table = platform_mif_pm_qos_get_table(platform, config);
505
506 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
507 "PM QoS update request: %u. MIF %u INT %u CL0 %u CL1 %u\n", config, table.freq_mif, table.freq_int, table.freq_cl0, table.freq_cl1);
508
509 pm_qos_update_request(&qos_req->pm_qos_req_mif, table.freq_mif);
510 pm_qos_update_request(&qos_req->pm_qos_req_int, table.freq_int);
511 pm_qos_update_request(&qos_req->pm_qos_req_cl0, table.freq_cl0);
512 pm_qos_update_request(&qos_req->pm_qos_req_cl1, table.freq_cl1);
513
514 return 0;
515 }
516
517 static int platform_mif_pm_qos_remove_request(struct scsc_mif_abs *interface, struct scsc_mifqos_request *qos_req)
518 {
519 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
520
521 if (!platform)
522 return -ENODEV;
523
524
525 if (!platform->qos_enabled) {
526 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "PM QoS not configured\n");
527 return -EOPNOTSUPP;
528 }
529
530 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "PM QoS remove request\n");
531 pm_qos_remove_request(&qos_req->pm_qos_req_mif);
532 pm_qos_remove_request(&qos_req->pm_qos_req_int);
533 pm_qos_remove_request(&qos_req->pm_qos_req_cl0);
534 pm_qos_remove_request(&qos_req->pm_qos_req_cl1);
535
536 return 0;
537 }
538 #endif
539
540 static void platform_mif_irq_default_handler(int irq, void *data)
541 {
542 /* Avoid unused parameter error */
543 (void)irq;
544 (void)data;
545
546 /* int handler not registered */
547 SCSC_TAG_INFO_DEV(PLAT_MIF, NULL, "INT handler not registered\n");
548 }
549
550 static void platform_mif_irq_reset_request_default_handler(int irq, void *data)
551 {
552 /* Avoid unused parameter error */
553 (void)irq;
554 (void)data;
555
556 /* int handler not registered */
557 SCSC_TAG_INFO_DEV(PLAT_MIF, NULL, "INT reset_request handler not registered\n");
558 }
559
560 irqreturn_t platform_mif_isr(int irq, void *data)
561 {
562 struct platform_mif *platform = (struct platform_mif *)data;
563
564 SCSC_TAG_DEBUG_DEV(PLAT_MIF, platform->dev, "INT %pS\n", platform->r4_handler);
565 if (platform->r4_handler != platform_mif_irq_default_handler)
566 platform->r4_handler(irq, platform->irq_dev);
567 else
568 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "MIF Interrupt Handler not registered\n");
569
570 return IRQ_HANDLED;
571 }
572
573 #ifdef CONFIG_SCSC_ENABLE_ALIVE_IRQ
574 irqreturn_t platform_alive_isr(int irq, void *data)
575 {
576 struct platform_mif *platform = (struct platform_mif *)data;
577
578 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "INT received\n");
579
580 return IRQ_HANDLED;
581 }
582 #endif
583
584 irqreturn_t platform_wdog_isr(int irq, void *data)
585 {
586 int ret = 0;
587 struct platform_mif *platform = (struct platform_mif *)data;
588
589 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "INT received\n");
590 if (platform->reset_request_handler != platform_mif_irq_reset_request_default_handler) {
591 disable_irq_nosync(platform->wlbt_irq[PLATFORM_MIF_WDOG].irq_num);
592 platform->reset_request_handler(irq, platform->irq_reset_request_dev);
593 } else {
594 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "WDOG Interrupt reset_request_handler not registered\n");
595 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "Disabling unhandled WDOG IRQ.\n");
596 disable_irq_nosync(platform->wlbt_irq[PLATFORM_MIF_WDOG].irq_num);
597 atomic_inc(&platform->wlbt_irq[PLATFORM_MIF_WDOG].irq_disabled_cnt);
598 }
599
600 /* The wakeup source isn't cleared until WLBT is reset, so change the interrupt type to suppress this */
601 if (mxman_recovery_disabled()) {
602 ret = regmap_update_bits(platform->pmureg, WAKEUP_INT_TYPE,
603 RESETREQ_WLBT, 0);
604 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "Set RESETREQ_WLBT wakeup interrput type to EDGE.\n");
605 if (ret < 0)
606 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev, "Failed to Set WAKEUP_INT_TYPE[RESETREQ_WLBT]: %d\n", ret);
607 }
608
609 return IRQ_HANDLED;
610 }
611
612 /*
613 * Attached array contains the replacement PMU boot code which should
614 * be programmed using the CBUS during the config phase.
615 */
616 uint32_t ka_patch[] = {
617 // Maxwell142 PMU+PROC combined boot ROM
618 // IP Version: 0xFF
619 // Major Version: 0xF, Minor Version: 0xF
620 // PMU ROM version: 0x2
621 // PROC ROM version: 0x0
622 // received initial version on 030719
623 0x90750002,
624 0x11a4c218,
625 0x755a118a,
626 0x9075e090,
627 0x30b3e5e7,
628 0xa230f8e0,
629 0xf5077411,
630 0xfdb2b5b1,
631 0x7400b153,
632 0xb5acf507,
633 0xb475fdad,
634 0x20b3e501,
635 0xb475fbe0,
636 0x75a3d200,
637 0xd2801890,
638 0x7907a075,
639 0xe6b07837,
640 0x07b40754,
641 0xd90b8002,
642 0xf5c404f6,
643 0x00af7590,
644 0x90750380,
645 0xf7532290,
646 0xeff753f7,
647 0x53dff753,
648 0x0479fece,
649 0xce53fed9,
650 0xd90c79fd,
651 0xfbce53fe,
652 0x53159275,
653 0xce53fd91,
654 0x02f943f7,
655 0x22fef953,
656 0xd8fed9f9,
657 0x9e7522fb,
658 0xcfc17501,
659 0x75a4c275,
660 0xc4754ac3,
661 0xa4c57547,
662 0x7561c675,
663 0xd27540c7,
664 0x80d37503,
665 0x7500c975,
666 0xcb75d0ca,
667 0x00cc7500,
668 0x75009a75,
669 0x9c75c09b,
670 0x009d7500,
671 0x82740278,
672 0x43848012,
673 0x057802c6,
674 0x8012d074,
675 0x20c34384,
676 0x75d09075,
677 0x93750291,
678 0x029e7501,
679 0x00000022,
680 };
681
682 irqreturn_t platform_cfg_req_isr(int irq, void *data)
683 {
684 struct platform_mif *platform = (struct platform_mif *)data;
685 u64 ret64 = 0;
686 const u64 EXYNOS_WLBT = 0x1;
687 /*s32 ret = 0;*/
688 unsigned int ka_addr = 0x1000;
689 uint32_t *ka_patch_addr = ka_patch;
690 //unsigned int id;
691
692 #define CHECK(x) do { \
693 int retval = (x); \
694 if (retval < 0) {\
695 pr_err("%s failed at L%d", __FUNCTION__, __LINE__); \
696 goto cfg_error; \
697 } \
698 } while (0)
699
700 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "INT received\n");
701 SCSC_TAG_DEBUG_DEV(PLAT_MIF, platform->dev, "disable_irq\n");
702
703 /* mask the irq */
704 disable_irq_nosync(platform->wlbt_irq[PLATFORM_MIF_CFG_REQ].irq_num);
705
706 /* Was the CFG_REQ irq received from WLBT before we expected it?
707 * Typically this indicates an issue returning WLBT HW to reset.
708 */
709 if (platform->boot_state != WLBT_BOOT_WAIT_CFG_REQ) {
710 u32 val;
711 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
712 "Spurious CFG_REQ IRQ from WLBT!\n");
713
714 regmap_read(platform->pmureg, WLBT_CTRL_NS, &val);
715 SCSC_TAG_INFO(PLAT_MIF, "WLBT_CTRL_NS 0x%x\n", val);
716
717 regmap_read(platform->pmureg, WLBT_CTRL_S, &val);
718 SCSC_TAG_INFO(PLAT_MIF, "WLBT_CTRL_S 0x%x\n", val);
719
720 regmap_read(platform->pmureg, WLBT_DEBUG, &val);
721 SCSC_TAG_INFO(PLAT_MIF, "WLBT_DEBUG 0x%x\n", val);
722
723 return IRQ_HANDLED;
724 }
725
726 /* Set TZPC to non-secure mode */
727 ret64 = exynos_smc(SMC_CMD_CONN_IF, (EXYNOS_WLBT << 32) | EXYNOS_SET_CONN_TZPC, 0, 0);
728 if (ret64)
729 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
730 "Failed to set TZPC to non-secure mode: %llu\n", ret64);
731 else
732 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
733 "SMC_CMD_CONN_IF run successfully : %llu\n", ret64);
734
735 /* WLBT_REMAP PMU_REMAP */
736 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "WLBT_REMAP begin\n");
737 CHECK(regmap_write(platform->wlbt_remap, 0x400, WLBT_DBUS_BAAW_0_START >> 12));
738 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "WLBT_REMAP end\n");
739
740 /* DBUS_BAAW regions */
741 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "DBUS_BAAW begin\n"); // PMU_DBUS_BAAW
742
743 /* Shared DRAM mapping. The destination address is the location reserved
744 * by the kernel.
745 */
746 CHECK(regmap_write(platform->dbus_baaw, 0x0, WLBT_DBUS_BAAW_0_START >> 12));
747 CHECK(regmap_write(platform->dbus_baaw, 0x4, WLBT_DBUS_BAAW_0_END >> 12));
748 CHECK(regmap_write(platform->dbus_baaw, 0x8, platform->mem_start >> 12)); // FW AP base addr >> 12
749 CHECK(regmap_write(platform->dbus_baaw, 0xC, WLBT_BAAW_ACCESS_CTRL));
750 #if 0
751 /* Additional DRAM mappings for future use */
752 CHECK(regmap_write(platform->dbus_baaw, 0x10, 0x000C0000));
753 CHECK(regmap_write(platform->dbus_baaw, 0x14, 0x000D0000));
754 CHECK(regmap_write(platform->dbus_baaw, 0x18, 0x000D0000));
755 CHECK(regmap_write(platform->dbus_baaw, 0x1C, WLBT_BAAW_ACCESS_CTRL));
756
757 CHECK(regmap_write(platform->dbus_baaw, 0x20, 0x000D0000));
758 CHECK(regmap_write(platform->dbus_baaw, 0x24, 0x000E0000));
759 CHECK(regmap_write(platform->dbus_baaw, 0x28, 0x000E0000));
760 CHECK(regmap_write(platform->dbus_baaw, 0x2C, WLBT_BAAW_ACCESS_CTRL));
761
762 CHECK(regmap_write(platform->dbus_baaw, 0x30, 0x000E0000));
763 CHECK(regmap_write(platform->dbus_baaw, 0x34, 0x000F0000));
764 CHECK(regmap_write(platform->dbus_baaw, 0x38, 0x000F0000));
765 CHECK(regmap_write(platform->dbus_baaw, 0x3C, WLBT_BAAW_ACCESS_CTRL));
766 #endif
767 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "DBUS_BAAW end\n");
768
769 /* PBUS_BAAW regions */
770 /* ref wlbt_if_S5E3830.c, updated for MX152 memory map */
771 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "PBUS_BAAW begin\n");
772
773 /* Range for CP2WLBT mailbox */
774 CHECK(regmap_write(platform->pbus_baaw, 0x0, WLBT_CBUS_BAAW_0_START >> 12));
775 CHECK(regmap_write(platform->pbus_baaw, 0x4, WLBT_CBUS_BAAW_0_END >> 12));
776 CHECK(regmap_write(platform->pbus_baaw, 0x8, WLBT_PBUS_MBOX_CP2WLBT_BASE >> 12));
777 CHECK(regmap_write(platform->pbus_baaw, 0xC, WLBT_BAAW_ACCESS_CTRL));
778
779 /* Range includes AP2WLBT,APM2WLBT,GNSS2WLBT mailboxes */
780 CHECK(regmap_write(platform->pbus_baaw, 0x10, WLBT_CBUS_BAAW_1_START >> 12));
781 CHECK(regmap_write(platform->pbus_baaw, 0x14, WLBT_CBUS_BAAW_1_END >> 12));
782 CHECK(regmap_write(platform->pbus_baaw, 0x18, WLBT_PBUS_MBOX_GNSS2WLBT_BASE >> 12));
783 CHECK(regmap_write(platform->pbus_baaw, 0x1C, WLBT_BAAW_ACCESS_CTRL));
784 #if 0
785 /* These mappings are not yet used by WLBT FW */
786 CHECK(regmap_write(platform->pbus_baaw, 0x20, WLBT_CBUS_BAAW_2_START >> 12));
787 CHECK(regmap_write(platform->pbus_baaw, 0x24, WLBT_CBUS_BAAW_2_END >> 12));
788 CHECK(regmap_write(platform->pbus_baaw, 0x28, WLBT_PBUS_MBOX_APM2WLBT_BASE >> 12));
789 CHECK(regmap_write(platform->pbus_baaw, 0x2C, WLBT_BAAW_ACCESS_CTRL));
790
791 CHECK(regmap_write(platform->pbus_baaw, 0x30, WLBT_CBUS_BAAW_3_START >>12));
792 CHECK(regmap_write(platform->pbus_baaw, 0x34, WLBT_CBUS_BAAW_3_END >> 12));
793 CHECK(regmap_write(platform->pbus_baaw, 0x38, WLBT_PBUS_MBOX_AP2WLBT_BASE >> 12));
794 CHECK(regmap_write(platform->pbus_baaw, 0x3C, WLBT_BAAW_ACCESS_CTRL));
795
796 CHECK(regmap_write(platform->pbus_baaw, 0x40, WLBT_CBUS_BAAW_4_START >> 12));
797 CHECK(regmap_write(platform->pbus_baaw, 0x44, WLBT_CBUS_BAAW_4_END >> 12));
798 CHECK(regmap_write(platform->pbus_baaw, 0x48, WLBT_PBUS_MBOX_WLBT2ABOX_BASE >> 12));
799 CHECK(regmap_write(platform->pbus_baaw, 0x4C, WLBT_BAAW_ACCESS_CTRL));
800
801 CHECK(regmap_write(platform->pbus_baaw, 0x50, WLBT_CBUS_BAAW_5_START >> 12));
802 CHECK(regmap_write(platform->pbus_baaw, 0x54, WLBT_CBUS_BAAW_5_END >> 12));
803 CHECK(regmap_write(platform->pbus_baaw, 0x58, WLBT_PBUS_MBOX_WLBT2CHUB_BASE >> 12));
804 CHECK(regmap_write(platform->pbus_baaw, 0x5C, WLBT_BAAW_ACCESS_CTRL));
805
806 CHECK(regmap_write(platform->pbus_baaw, 0x60, WLBT_CBUS_BAAW_6_START >> 12));
807 CHECK(regmap_write(platform->pbus_baaw, 0x64, WLBT_CBUS_BAAW_6_START >> 12));
808 CHECK(regmap_write(platform->pbus_baaw, 0x68, WLBT_PBUS_CHUB_BASE >> 12));
809 CHECK(regmap_write(platform->pbus_baaw, 0x6C, WLBT_BAAW_ACCESS_CTRL));
810 #endif
811 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "PBUS_BAAW end\n");
812
813 /* PMU boot patch
814 * BOOT_SOURCE_CFG 0x0001 KA RAM access granted to CFG longhop. Any 8051 accesses are waited if this setting is used.
815 */
816 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "BOOT_WLBT begin\n");
817 CHECK(regmap_write(platform->boot_cfg, 0x0, 0x1));
818 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "BOOT_WLBT done\n");
819
820 while (ka_patch_addr < (ka_patch + ARRAY_SIZE(ka_patch))) {
821 CHECK(regmap_write(platform->boot_cfg, ka_addr, *ka_patch_addr));
822 ka_addr += (unsigned int)sizeof(ka_patch[0]);
823 ka_patch_addr++;
824 }
825 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "KA patch done\n");
826
827 /* Notify PMU of configuration done
828 * BOOT_SOURCE_ROM 0x0000 KA RAM access granted to 8051. CBUS accesses are ignored if this setting is used.
829 */
830 CHECK(regmap_write(platform->boot_cfg, 0x0, 0x0));
831 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "BOOT config done\n");
832
833 /* BOOT_CFG_ACK is 1-bit wide */
834 CHECK(regmap_write(platform->boot_cfg, 0x4, 0x1));
835 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "BOOT_CFG_ACK done\n");
836
837 /* Mark as CFQ_REQ handled, so boot may continue */
838 platform->boot_state = WLBT_BOOT_CFG_DONE;
839
840 /* Signal triggering function that the IRQ arrived and CFG was done */
841 complete(&platform->cfg_ack);
842
843 /* as per wlbt_if_S5E3830.c - end */
844
845 return IRQ_HANDLED;
846 cfg_error:
847 platform->boot_state = WLBT_BOOT_CFG_ERROR;
848 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev, "ERROR: WLBT Config failed. WLBT will not work\n");
849 complete(&platform->cfg_ack);
850 return IRQ_HANDLED;
851 }
852
853 static void platform_mif_unregister_irq(struct platform_mif *platform)
854 {
855 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "Unregistering IRQs\n");
856
857 devm_free_irq(platform->dev, platform->wlbt_irq[PLATFORM_MIF_MBOX].irq_num, platform);
858 devm_free_irq(platform->dev, platform->wlbt_irq[PLATFORM_MIF_WDOG].irq_num, platform);
859 /* Reset irq_disabled_cnt for WDOG IRQ since the IRQ itself is here unregistered and disabled */
860 atomic_set(&platform->wlbt_irq[PLATFORM_MIF_WDOG].irq_disabled_cnt, 0);
861 #ifdef CONFIG_SCSC_ENABLE_ALIVE_IRQ
862 /* if ALIVE irq is required */
863 devm_free_irq(platform->dev, platform->wlbt_irq[PLATFORM_MIF_ALIVE].irq_num, platform);
864 #endif
865 devm_free_irq(platform->dev, platform->wlbt_irq[PLATFORM_MIF_CFG_REQ].irq_num, platform);
866 }
867
868 static int platform_mif_register_irq(struct platform_mif *platform)
869 {
870 int err;
871
872 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "Registering IRQs\n");
873
874 /* Register MBOX irq */
875 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "Registering MBOX irq: %d flag 0x%x\n",
876 platform->wlbt_irq[PLATFORM_MIF_MBOX].irq_num, platform->wlbt_irq[PLATFORM_MIF_MBOX].flags);
877
878 err = devm_request_irq(platform->dev, platform->wlbt_irq[PLATFORM_MIF_MBOX].irq_num, platform_mif_isr,
879 platform->wlbt_irq[PLATFORM_MIF_MBOX].flags, DRV_NAME, platform);
880 if (IS_ERR_VALUE((unsigned long)err)) {
881 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
882 "Failed to register MBOX handler: %d. Aborting.\n", err);
883 err = -ENODEV;
884 return err;
885 }
886
887 /* Register WDOG irq */
888 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "Registering WDOG irq: %d flag 0x%x\n",
889 platform->wlbt_irq[PLATFORM_MIF_WDOG].irq_num, platform->wlbt_irq[PLATFORM_MIF_WDOG].flags);
890
891 err = devm_request_irq(platform->dev, platform->wlbt_irq[PLATFORM_MIF_WDOG].irq_num, platform_wdog_isr,
892 platform->wlbt_irq[PLATFORM_MIF_WDOG].flags, DRV_NAME, platform);
893 if (IS_ERR_VALUE((unsigned long)err)) {
894 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
895 "Failed to register WDOG handler: %d. Aborting.\n", err);
896 err = -ENODEV;
897 return err;
898 }
899
900 #ifdef CONFIG_SCSC_ENABLE_ALIVE_IRQ
901 /* Register ALIVE irq */
902 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "Registering ALIVE irq: %d flag 0x%x\n",
903 platform->wlbt_irq[PLATFORM_MIF_ALIVE].irq_num, platform->wlbt_irq[PLATFORM_MIF_ALIVE].flags);
904
905 err = devm_request_irq(platform->dev, platform->wlbt_irq[PLATFORM_MIF_ALIVE].irq_num, platform_alive_isr,
906 platform->wlbt_irq[PLATFORM_MIF_ALIVE].flags, DRV_NAME, platform);
907 if (IS_ERR_VALUE(err)) {
908 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
909 "Failed to register ALIVE handler: %d. Aborting.\n", err);
910 err = -ENODEV;
911 return err;
912 }
913 #endif
914
915 /* Mark as WLBT in reset before enabling IRQ to guard against spurious IRQ */
916 platform->boot_state = WLBT_BOOT_IN_RESET;
917 smp_wmb(); /* commit before irq */
918
919 /* Register WB2AP_CFG_REQ irq */
920 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "Registering CFG_REQ irq: %d flag 0x%x\n",
921 platform->wlbt_irq[PLATFORM_MIF_CFG_REQ].irq_num, platform->wlbt_irq[PLATFORM_MIF_CFG_REQ].flags);
922
923 err = devm_request_irq(platform->dev, platform->wlbt_irq[PLATFORM_MIF_CFG_REQ].irq_num, platform_cfg_req_isr,
924 platform->wlbt_irq[PLATFORM_MIF_CFG_REQ].flags, DRV_NAME, platform);
925 if (IS_ERR_VALUE((unsigned long)err)) {
926 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
927 "Failed to register CFG_REQ handler: %d. Aborting.\n", err);
928 err = -ENODEV;
929 return err;
930 }
931
932 /* Leave disabled until ready to handle */
933 disable_irq_nosync(platform->wlbt_irq[PLATFORM_MIF_CFG_REQ].irq_num);
934
935 return 0;
936 }
937
938 static void platform_mif_destroy(struct scsc_mif_abs *interface)
939 {
940 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
941
942 platform_mif_unregister_irq(platform);
943 }
944
945 static char *platform_mif_get_uid(struct scsc_mif_abs *interface)
946 {
947 /* Avoid unused parameter error */
948 (void)interface;
949 return "0";
950 }
951
952 static void wlbt_regdump(struct platform_mif *platform)
953 {
954 u32 val = 0;
955
956 regmap_read(platform->pmureg, WLBT_CTRL_S, &val);
957 SCSC_TAG_INFO(PLAT_MIF, "WLBT_CTRL_S 0x%x\n", val);
958
959 regmap_read(platform->pmureg, WLBT_CONFIGURATION, &val);
960 SCSC_TAG_INFO(PLAT_MIF, "WLBT_CONFIGURATION 0x%x\n", val);
961
962 regmap_read(platform->pmureg, WLBT_CTRL_NS, &val);
963 SCSC_TAG_INFO(PLAT_MIF, "WLBT_CTRL_NS 0x%x\n", val);
964
965 regmap_read(platform->pmureg, WLBT_IN, &val);
966 SCSC_TAG_INFO(PLAT_MIF, "WLBT_IN 0x%x\n", val);
967
968 regmap_read(platform->pmureg, WLBT_OUT, &val);
969 SCSC_TAG_INFO(PLAT_MIF, "WLBT_OUT 0x%x\n", val);
970
971 regmap_read(platform->pmureg, WLBT_STATUS, &val);
972 SCSC_TAG_INFO(PLAT_MIF, "WLBT_STATUS 0x%x\n", val);
973
974 regmap_read(platform->pmureg, WLBT_STATES, &val);
975 SCSC_TAG_INFO(PLAT_MIF, "WLBT_STATES 0x%x\n", val);
976
977 regmap_read(platform->pmureg, WLBT_DEBUG, &val);
978 SCSC_TAG_INFO(PLAT_MIF, "WLBT_DEBUG 0x%x\n", val);
979 }
980
981 /* WLBT START */
982 static int platform_mif_start(struct scsc_mif_abs *interface, bool start)
983 {
984 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
985
986 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "start %d\n", start);
987 /* At this point WLBT should assert the CFG_REQ IRQ, so wait for it */
988 if (start &&
989 wait_for_completion_timeout(&platform->cfg_ack, WLBT_BOOT_TIMEOUT) == 0) {
990 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev, "Timeout waiting for CFG_REQ IRQ\n");
991 wlbt_regdump(platform);
992 return -ETIMEDOUT;
993 }
994
995 wlbt_regdump(platform);
996
997 /* only continue if CFG_REQ IRQ configured WLBT/PMU correctly */
998 if (platform->boot_state == WLBT_BOOT_CFG_ERROR) {
999 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev, "CFG_REQ failed to configure WLBT.\n");
1000 return -EIO;
1001 }
1002 return 0;
1003 }
1004
1005 static int platform_mif_pmu_reset_release(struct scsc_mif_abs *interface)
1006 {
1007 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1008 int ret = 0;
1009 u32 val = 0;
1010 unsigned long timeout;
1011 static bool init_done;
1012
1013 /* We're now ready for the IRQ */
1014 platform->boot_state = WLBT_BOOT_WAIT_CFG_REQ;
1015 smp_wmb(); /* commit before irq */
1016
1017 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "on boot_state = WLBT_BOOT_WAIT_CFG_REQ\n");
1018
1019 /* INIT SEQUENCE - First WLBT boot only
1020 * Cold reset wrt. AP power sequencer, cold reset for WLBT
1021 */
1022 if (!init_done) {
1023 /* init sequence from excite/email - PMUCAL v2
1024 *
1025 * access type SFR Name Address Field value
1026 * write WLBT_CTRL_S 0x####_3114 [3] 0x1
1027 * write WLBT_OPTION 0x####_310C [3] 0x1
1028 * delay delay 　 　 0x3
1029 * write TOP_OUT 0x####_3920 [1] 0x1
1030 * read-till VGPIO_TX_MONITOR 0x####_1700 [29] 0x1
1031 * delay delay 　 　 0x3E8
1032 * write WLBT_CONFIGURATION 0x####_3100 [0] 0x1
1033 * read-till WLBT_STATUS 0x####_3104 [0] 0x1
1034 * write WLBT_CTRL_NS 0x####_3110 [6] 0x0
1035 * write WLBT_CTRL_NS 0x####_3110 [5] 0x1
1036 *
1037 */
1038 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "init\n");
1039
1040 /* WLBT_CTRL_S[WLBT_START] = 1 enable */
1041 ret = regmap_update_bits(platform->pmureg, WLBT_CTRL_S,
1042 BIT(3), BIT(3)); /* WLBT_START */
1043 if (ret < 0) {
1044 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
1045 "Failed to update WLBT_CTRL_S[WLBT_START]: %d\n", ret);
1046 return ret;
1047 }
1048 regmap_read(platform->pmureg, WLBT_CTRL_S, &val);
1049 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
1050 "updated successfully WLBT_CTRL_S[WLBT_START]: 0x%x\n", val);
1051
1052 /* WLBT_OPTION[WLBT_OPTION_DATA] = 1 Power On */
1053 ret = regmap_update_bits(platform->pmureg, WLBT_OPTION,
1054 BIT(3), BIT(3)); /* WLBT_OPTION_DATA */
1055 if (ret < 0) {
1056 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
1057 "Failed to update WLBT_OPTION[WLBT_OPTION_DATA]: %d\n", ret);
1058 return ret;
1059 }
1060 regmap_read(platform->pmureg, WLBT_OPTION, &val);
1061 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
1062 "updated successfully WLBT_OPTION[WLBT_OPTION_DATA]: 0x%x\n", val);
1063
1064 /* TOP_OUT[PWRRGTON_CP] = 1 Power On */
1065 ret = regmap_update_bits(platform->pmureg, TOP_OUT,
1066 BIT(1), BIT(1)); /* PWRRGTON_CP */
1067 if (ret < 0) {
1068 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
1069 "Failed to update TOP_OUT[PWRRGTON_CP]: %d\n", ret);
1070 return ret;
1071 }
1072 regmap_read(platform->pmureg, TOP_OUT, &val);
1073 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
1074 "updated successfully TOP_OUT[PWRRGTON_CP]: 0x%x\n", val);
1075
1076 /* VGPIO_TX_MONITOR = 0x1 */
1077 timeout = jiffies + msecs_to_jiffies(500);
1078 do {
1079 regmap_read(platform->i3c_apm_pmic, VGPIO_TX_MONITOR, &val);
1080 val &= (u32)BIT(29); /* VGPIO_TX_MON_BIT29 */
1081 if (val) {
1082 SCSC_TAG_INFO(PLAT_MIF, "VGPIO_TX_MONITOR 0x%x\n", val);
1083 break;
1084 }
1085 } while (time_before(jiffies, timeout));
1086
1087 if (!val) {
1088 regmap_read(platform->i3c_apm_pmic, VGPIO_TX_MONITOR, &val);
1089 SCSC_TAG_INFO(PLAT_MIF, "timeout waiting for VGPIO_TX_MONITOR time-out: "
1090 "VGPIO_TX_MONITOR 0x%x\n", val);
1091 }
1092
1093 /* WLBT_CONFIGURATION[LOCAL_PWR_CFG] = 1 Power On */
1094 ret = regmap_update_bits(platform->pmureg, WLBT_CONFIGURATION,
1095 BIT(0), BIT(0)); /* LOCAL_PWR_CFG */
1096 if (ret < 0) {
1097 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
1098 "Failed to update WLBT_CONFIGURATION[LOCAL_PWR_CFG]: %d\n", ret);
1099 return ret;
1100 }
1101 regmap_read(platform->pmureg, WLBT_CONFIGURATION, &val);
1102 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
1103 "updated successfully WLBT_CONFIGURATION[LOCAL_PWR_CFG]: 0x%x\n", val);
1104
1105 /* wait for power up complete WLBT_STATUS[WLBT_STATUS_BIT0] = 1 for Power On */
1106 timeout = jiffies + msecs_to_jiffies(500);
1107 do {
1108 regmap_read(platform->pmureg, WLBT_STATUS, &val);
1109 val &= (u32)BIT(0); /* WLBT_STATUS_BIT0 */
1110 if (val) {
1111 /* Power On complete */
1112 SCSC_TAG_INFO(PLAT_MIF, "Power On complete: WLBT_STATUS 0x%x\n", val);
1113 break;
1114 }
1115 } while (time_before(jiffies, timeout));
1116
1117 if (!val) {
1118 regmap_read(platform->pmureg, WLBT_STATUS, &val);
1119 SCSC_TAG_INFO(PLAT_MIF, "timeout waiting for power on time-out: "
1120 "WLBT_STATUS 0x%x\n", val);
1121 }
1122
1123 /* WLBT_CTRL_NS[WLBT_ACTIVE_CLR] = 0 Active interrupt clear */
1124 ret = regmap_update_bits(platform->pmureg, WLBT_CTRL_NS,
1125 BIT(6), 0x0); /* WLBT_ACTIVE_CLR */
1126 if (ret < 0) {
1127 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
1128 "Failed to update WLBT_CTRL_NS[WLBT_ACTIVE_CLR]: %d\n", ret);
1129 return ret;
1130 }
1131 regmap_read(platform->pmureg, WLBT_CTRL_NS, &val);
1132 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
1133 "updated successfully WLBT_CTRL_NS[WLBT_ACTIVE_CLR]: 0x%x\n", val);
1134
1135 /* WLBT_CTRL_NS[WLBT_ACTIVE_EN] = 1 Active interrupt enable */
1136 ret = regmap_update_bits(platform->pmureg, WLBT_CTRL_NS,
1137 BIT(5), BIT(5)); /* WLBT_ACTIVE_EN */
1138 if (ret < 0) {
1139 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
1140 "Failed to update WLBT_CTRL_NS[WLBT_ACTIVE_EN]: %d\n", ret);
1141 return ret;
1142 }
1143 regmap_read(platform->pmureg, WLBT_CTRL_NS, &val);
1144 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
1145 "updated successfully WLBT_CTRL_NS[WLBT_ACTIVE_EN]: 0x%x\n", val);
1146
1147 init_done = true;
1148
1149 goto init_code_done;
1150 }
1151
1152 /* RESET RELEASE - Subsequent WLBT reboots */
1153 /* wlbt_if_reset_release - from excite/email code PMUCAL v2
1154 * access type SFR Name Address Field value
1155 *
1156 * write WLBT_OPTION 0x####_310C [3] 0x1
1157 * write MIF_CTRL 0x####_3810 [0] 0x1
1158 * write TCXO_BUF_CTRL 0x####_3b78 [0] 0x1
1159 * write TOP_OUT 0x####_3920 [1] 0x1
1160 * read-till VGPIO_TX_MONITOR 0x####_1700 [29] 0x1
1161 * delay delay 　 　 0x3e8
1162 * write WLBT_CONFIGURATION 0x####_3100 [0] 0x1
1163 * read-till WLBT_STATUS 0x####_3104 [0] 0x1
1164 * write WLBT_INT_EN 0x####_3144 [3] 0x1
1165 * write WLBT_INT_EN 0x####_3144 [5] 0x1
1166 * write WLBT_CTRL_NS 0x####_3110 [6] 0x0
1167 * write WLBT_CTRL_NS 0x####_3110 [5] 0x1
1168 *
1169 * */
1170
1171 /* Warm reset wrt. AP power sequencer, but cold reset for WLBT */
1172 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "release\n");
1173
1174 ret = regmap_update_bits(platform->pmureg, WLBT_OPTION,
1175 BIT(3), BIT(3)); /* WLBT_OPTION_DATA */
1176 if (ret < 0) {
1177 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
1178 "Failed to update WLBT_OPTION[WLBT_OPTION_DATA]: %d\n", ret);
1179 return ret;
1180 }
1181 regmap_read(platform->pmureg, WLBT_OPTION, &val);
1182 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
1183 "updated successfully WLBT_OPTION[WLBT_OPTION_DATA]: 0x%x\n", val);
1184
1185 ret = regmap_update_bits(platform->pmureg, MIF_CTRL,
1186 BIT(0), BIT(0)); /* TCXO_EN */
1187 if (ret < 0) {
1188 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
1189 "Failed to update MIF_CTRL[TCXO_EN]: %d\n", ret);
1190 return ret;
1191 }
1192 regmap_read(platform->pmureg, MIF_CTRL, &val);
1193 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
1194 "updated successfully MIF_CTRL[TCXO_EN]: 0x%x\n", val & TCXO_EN);
1195
1196 ret = regmap_update_bits(platform->pmureg, TCXO_BUF_CTRL,
1197 BIT(0), BIT(0)); /* TCXO_BUF_BIAS_EN_WLBT */
1198 if (ret < 0) {
1199 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
1200 "Failed to update TCXO_BUF_CTRL[TCXO_BUF_BIAS_EN_WLBT]: %d\n", ret);
1201 return ret;
1202 }
1203 regmap_read(platform->pmureg, TCXO_BUF_CTRL, &val);
1204 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
1205 "updated successfully TCXO_BUF_CTRL[TCXO_BUF_BIAS_EN_WLBT]: 0x%x\n", val & TCXO_BUF_BIAS_EN_WLBT);
1206
1207 ret = regmap_update_bits(platform->pmureg, TOP_OUT,
1208 BIT(1), BIT(1)); /* PWRRGTON_CP */
1209
1210 if (ret < 0) {
1211 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
1212 "Failed to update TOP_OUT[PWRRGTON_CP]: %d\n", ret);
1213 return ret;
1214 }
1215 /* VGPIO_TX_MONITOR = 0x1 */
1216 timeout = jiffies + msecs_to_jiffies(500);
1217 do {
1218 regmap_read(platform->i3c_apm_pmic, VGPIO_TX_MONITOR, &val);
1219 val &= (u32)BIT(29); /* VGPIO_TX_MON_BIT29 */
1220 if (val) {
1221 SCSC_TAG_INFO(PLAT_MIF, "VGPIO_TX_MONITOR 0x%x\n", val);
1222 break;
1223 }
1224 } while (time_before(jiffies, timeout));
1225
1226 if (!val) {
1227 regmap_read(platform->i3c_apm_pmic, VGPIO_TX_MONITOR, &val);
1228 SCSC_TAG_INFO(PLAT_MIF, "timeout waiting for VGPIO_TX_MONITOR time-out: "
1229 "VGPIO_TX_MONITOR 0x%x\n", val);
1230 }
1231
1232 /* Power Up */
1233 ret = regmap_update_bits(platform->pmureg, WLBT_CONFIGURATION,
1234 BIT(0), BIT(0)); /* LOCAL_PWR_CFG */
1235 if (ret < 0) {
1236 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
1237 "Failed to update WLBT_CONFIGURATION[LOCAL_PWR_CFG]: %d\n", ret);
1238 return ret;
1239 }
1240 regmap_read(platform->pmureg, WLBT_CONFIGURATION, &val);
1241 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
1242 "updated successfully WLBT_CONFIGURATION[LOCAL_PWR_CFG]: 0x%x\n", val);
1243
1244 /* wait for power up complete WLBT_STATUS[0] = 0 for power down */
1245 timeout = jiffies + msecs_to_jiffies(500);
1246 do {
1247 regmap_read(platform->pmureg, WLBT_STATUS, &val);
1248 val &= (u32)BIT(0); /* WLBT_STATUS_BIT0 */
1249 if (val) {
1250 /* Power up complete */
1251 SCSC_TAG_INFO(PLAT_MIF, "Power up complete: WLBT_STATUS 0x%x\n", val);
1252 break;
1253 }
1254 } while (time_before(jiffies, timeout));
1255
1256 if (!val) {
1257 regmap_read(platform->pmureg, WLBT_STATUS, &val);
1258 SCSC_TAG_INFO(PLAT_MIF, "Timeout waiting for Power up complete: "
1259 "WLBT_STATUS 0x%x\n", val);
1260 }
1261
1262 /* enable PWR_REQ_F and TCXO_REQ_F interrupts */
1263 ret = regmap_update_bits(platform->pmureg, WLBT_INT_EN,
1264 BIT(3), BIT(3)); /* PWR_REQ_F */
1265 if (ret < 0) {
1266 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
1267 "Failed to update WLBT_INT_EN[PWR_REQ_F]: %d\n", ret);
1268 return ret;
1269 }
1270 regmap_read(platform->pmureg, WLBT_INT_EN, &val);
1271 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
1272 "updated successfully WLBT_INT_EN[PWR_REQ_F]: 0x%x\n", val);
1273
1274 ret = regmap_update_bits(platform->pmureg, WLBT_INT_EN,
1275 BIT(5), BIT(5)); /* TCXO_REQ_F */
1276 if (ret < 0) {
1277 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
1278 "Failed to update WLBT_INT_EN[TCXO_REQ_F]: %d\n", ret);
1279 return ret;
1280 }
1281 regmap_read(platform->pmureg, WLBT_INT_EN, &val);
1282 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
1283 "updated successfully WLBT_INT_EN[TCXO_REQ_F]: 0x%x\n", val);
1284
1285 /* WLBT_CTRL_NS[WLBT_ACTIVE_CLR] = 0 Active interrupt clear */
1286 ret = regmap_update_bits(platform->pmureg, WLBT_CTRL_NS,
1287 BIT(6), 0x0);
1288 if (ret < 0) {
1289 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
1290 "Failed to update WLBT_CTRL_NS[WLBT_ACTIVE_CLR]: %d\n", ret);
1291 return ret;
1292 }
1293 regmap_read(platform->pmureg, WLBT_CTRL_NS, &val);
1294 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
1295 "updated successfully WLBT_CTRL_NS[WLBT_ACTIVE_CLR]: 0x%x\n", val);
1296
1297 /* WLBT_CTRL_NS[WLBT_ACTIVE_EN] = 1 Active interrupt enable */
1298 ret = regmap_update_bits(platform->pmureg, WLBT_CTRL_NS,
1299 BIT(5), BIT(5)); /* WLBT_ACTIVE_EN */
1300 if (ret < 0) {
1301 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
1302 "Failed to update WLBT_CTRL_NS[WLBT_ACTIVE_EN]: %d\n", ret);
1303 return ret;
1304 }
1305 regmap_read(platform->pmureg, WLBT_CTRL_NS, &val);
1306 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
1307 "updated successfully WLBT_CTRL_NS[WLBT_ACTIVE_EN]: 0x%x\n", val);
1308
1309 init_code_done:
1310 /* Now handle the CFG_REQ IRQ */
1311 enable_irq(platform->wlbt_irq[PLATFORM_MIF_CFG_REQ].irq_num);
1312
1313 ret = platform_mif_start(interface, true);
1314 if (ret)
1315 return ret;
1316
1317 return ret;
1318 }
1319
1320 static int platform_mif_pmu_reset_assert(struct scsc_mif_abs *interface)
1321 {
1322 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1323 unsigned long timeout;
1324 int ret;
1325 u32 val;
1326
1327 /* wlbt_if_reset_assertion - from excite/email PMUCAL v2
1328 *
1329 * access type SFR Name Address Field value
1330 * write WLBT_CTRL_NS 0x####_3110 [5] 0x0
1331 * write WLBT_CONFIGURATION 0x####_3100 [0] 0x0
1332 * read-till WLBT_STATUS 0x####_3104 [0] 0x0
1333 *
1334 */
1335
1336 /* Active interrupt disable */
1337 ret = regmap_update_bits(platform->pmureg, WLBT_CTRL_NS,
1338 BIT(5), 0x0); /* WLBT_ACTIVE_EN */
1339 if (ret < 0) {
1340 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
1341 "Failed to update WLBT_CTRL_NS[WLBT_ACTIVE_EN]: %d\n", ret);
1342 return ret;
1343 }
1344 regmap_read(platform->pmureg, WLBT_CTRL_NS, &val);
1345 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
1346 "updated successfully WLBT_CTRL_NS[WLBT_ACTIVE_EN]: 0x%x\n", val);
1347
1348 /* Power Down */
1349 ret = regmap_update_bits(platform->pmureg, WLBT_CONFIGURATION,
1350 BIT(0), 0x0); /* LOCAL_PWR_CFG */
1351 if (ret < 0) {
1352 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
1353 "Failed to update WLBT_CONFIGURATION[LOCAL_PWR_CFG]: %d\n", ret);
1354 return ret;
1355 }
1356 regmap_read(platform->pmureg, WLBT_CONFIGURATION, &val);
1357 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
1358 "updated successfully WLBT_CONFIGURATION[LOCAL_PWR_CFG]: 0x%x\n", val);
1359
1360 /* Wait for power Off WLBT_STATUS[WLBT_STATUS_BIT0] = 0 */
1361 timeout = jiffies + msecs_to_jiffies(500);
1362 do {
1363 regmap_read(platform->pmureg, WLBT_STATUS, &val);
1364 val &= (u32)BIT(0); /* WLBT_STATUS_BIT0 */
1365 if (val == 0) {
1366 SCSC_TAG_INFO(PLAT_MIF, "WLBT_STATUS 0x%x\n", val);
1367 return 0; /* OK - return */
1368 }
1369 } while (time_before(jiffies, timeout));
1370
1371 /* Timed out */
1372 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev, "Timeout waiting for WLBT_STATUS status\n");
1373
1374 regmap_read(platform->pmureg, WLBT_STATUS, &val);
1375 SCSC_TAG_INFO(PLAT_MIF, "WLBT_STATUS 0x%x\n", val);
1376 regmap_read(platform->pmureg, WLBT_DEBUG, &val);
1377 SCSC_TAG_INFO(PLAT_MIF, "WLBT_DEBUG 0x%x\n", val);
1378 regmap_read(platform->pmureg, WLBT_STATES, &val);
1379 SCSC_TAG_INFO(PLAT_MIF, "WLBT_STATES 0x%x\n", val);
1380 return -ETIME;
1381 }
1382
1383 /* reset=0 - release from reset */
1384 /* reset=1 - hold reset */
1385 static int platform_mif_reset(struct scsc_mif_abs *interface, bool reset)
1386 {
1387 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1388 u32 ret = 0;
1389
1390 SCSC_TAG_DEBUG_DEV(PLAT_MIF, platform->dev, "\n");
1391
1392 if (enable_platform_mif_arm_reset || !reset) {
1393 if (!reset) { /* Release from reset */
1394 #ifdef CONFIG_ARCH_EXYNOS
1395 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
1396 "SOC_VERSION: product_id 0x%x, rev 0x%x\n",
1397 exynos_soc_info.product_id, exynos_soc_info.revision);
1398 #endif
1399 power_supplies_on(platform);
1400
1401 ret = platform_mif_pmu_reset_release(interface);
1402 } else {
1403 /* Put back into reset */
1404 ret = platform_mif_pmu_reset_assert(interface);
1405 }
1406 } else
1407 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "Not resetting ARM Cores - enable_platform_mif_arm_reset: %d\n",
1408 enable_platform_mif_arm_reset);
1409 return ret;
1410 }
1411
1412 static void __iomem *platform_mif_map_region(unsigned long phys_addr, size_t size)
1413 {
1414 size_t i;
1415 struct page **pages;
1416 void *vmem;
1417
1418 size = PAGE_ALIGN(size);
1419
1420 pages = kmalloc((size >> PAGE_SHIFT) * sizeof(*pages), GFP_KERNEL);
1421 if (!pages)
1422 return NULL;
1423
1424 /* Map NORMAL_NC pages with kernel virtual space */
1425 for (i = 0; i < (size >> PAGE_SHIFT); i++) {
1426 pages[i] = phys_to_page(phys_addr);
1427 phys_addr += PAGE_SIZE;
1428 }
1429
1430 vmem = vmap(pages, size >> PAGE_SHIFT, VM_MAP, pgprot_writecombine(PAGE_KERNEL));
1431
1432 kfree(pages);
1433 return (void __iomem *)vmem;
1434 }
1435
1436 static void platform_mif_unmap_region(void *vmem)
1437 {
1438 vunmap(vmem);
1439 }
1440
1441 static void *platform_mif_map(struct scsc_mif_abs *interface, size_t *allocated)
1442 {
1443 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1444 u8 i;
1445
1446 if (allocated)
1447 *allocated = 0;
1448
1449 platform->mem =
1450 platform_mif_map_region(platform->mem_start, platform->mem_size);
1451
1452 if (!platform->mem) {
1453 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev, "Error remaping shared memory\n");
1454 return NULL;
1455 }
1456
1457 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "Map: virt %p phys %lx\n", platform->mem, (uintptr_t)platform->mem_start);
1458
1459 /* Initialise MIF registers with documented defaults */
1460 /* MBOXes */
1461 for (i = 0; i < NUM_MBOX_PLAT; i++)
1462 platform_mif_reg_write(platform, MAILBOX_WLBT_REG(ISSR(i)), 0x00000000);
1463
1464 /* MRs */ /*1's - set all as Masked */
1465 platform_mif_reg_write(platform, MAILBOX_WLBT_REG(INTMR0), 0xffff0000);
1466 platform_mif_reg_write(platform, MAILBOX_WLBT_REG(INTMR1), 0x0000ffff);
1467 /* CRs */ /* 1's - clear all the interrupts */
1468 platform_mif_reg_write(platform, MAILBOX_WLBT_REG(INTCR0), 0xffff0000);
1469 platform_mif_reg_write(platform, MAILBOX_WLBT_REG(INTCR1), 0x0000ffff);
1470
1471 #ifdef CONFIG_SCSC_CHV_SUPPORT
1472 if (chv_disable_irq == true) {
1473 if (allocated)
1474 *allocated = platform->mem_size;
1475 return platform->mem;
1476 }
1477 #endif
1478 /* register interrupts */
1479 if (platform_mif_register_irq(platform)) {
1480 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "Unmap: virt %p phys %lx\n", platform->mem, (uintptr_t)platform->mem_start);
1481 platform_mif_unmap_region(platform->mem);
1482 return NULL;
1483 }
1484
1485 if (allocated)
1486 *allocated = platform->mem_size;
1487 /* Set the CR4 base address in Mailbox??*/
1488 return platform->mem;
1489 }
1490
1491 /* HERE: Not sure why mem is passed in - its stored in platform - as it should be */
1492 static void platform_mif_unmap(struct scsc_mif_abs *interface, void *mem)
1493 {
1494 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1495
1496 /* Avoid unused parameter error */
1497 (void)mem;
1498
1499 /* MRs */ /*1's - set all as Masked */
1500 platform_mif_reg_write(platform, MAILBOX_WLBT_REG(INTMR0), 0xffff0000);
1501 platform_mif_reg_write(platform, MAILBOX_WLBT_REG(INTMR1), 0x0000ffff);
1502
1503 #ifdef CONFIG_SCSC_CHV_SUPPORT
1504 /* Restore PIO changed by Maxwell subsystem */
1505 if (chv_disable_irq == false)
1506 /* Unregister IRQs */
1507 platform_mif_unregister_irq(platform);
1508 #else
1509 platform_mif_unregister_irq(platform);
1510 #endif
1511 /* CRs */ /* 1's - clear all the interrupts */
1512 platform_mif_reg_write(platform, MAILBOX_WLBT_REG(INTCR0), 0xffff0000);
1513 platform_mif_reg_write(platform, MAILBOX_WLBT_REG(INTCR1), 0x0000ffff);
1514 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "Unmap: virt %p phys %lx\n", platform->mem, (uintptr_t)platform->mem_start);
1515 platform_mif_unmap_region(platform->mem);
1516 platform->mem = NULL;
1517 }
1518
1519 static u32 platform_mif_irq_bit_mask_status_get(struct scsc_mif_abs *interface)
1520 {
1521 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1522 u32 val;
1523
1524 val = platform_mif_reg_read(platform, MAILBOX_WLBT_REG(INTMR0)) >> 16;
1525 SCSC_TAG_DEBUG_DEV(PLAT_MIF, platform->dev, "Getting INTMR0: 0x%x\n", val);
1526 return val;
1527 }
1528
1529 static u32 platform_mif_irq_get(struct scsc_mif_abs *interface)
1530 {
1531 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1532 u32 val;
1533
1534 /* Function has to return the interrupts that are enabled *AND* not masked */
1535 val = platform_mif_reg_read(platform, MAILBOX_WLBT_REG(INTMSR0)) >> 16;
1536 SCSC_TAG_DEBUG_DEV(PLAT_MIF, platform->dev, "Getting INT-INTMSR0: 0x%x\n", val);
1537
1538 return val;
1539 }
1540
1541 static void platform_mif_irq_bit_set(struct scsc_mif_abs *interface, int bit_num, enum scsc_mif_abs_target target)
1542 {
1543 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1544 u32 reg;
1545
1546 if (bit_num >= 16) {
1547 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev, "Incorrect INT number: %d\n", bit_num);
1548 return;
1549 }
1550
1551 reg = INTGR1;
1552 platform_mif_reg_write(platform, MAILBOX_WLBT_REG(reg), (1 << bit_num));
1553 SCSC_TAG_DEBUG_DEV(PLAT_MIF, platform->dev, "Setting INTGR1: bit %d on target %d\n", bit_num, target);
1554 }
1555
1556 static void platform_mif_irq_bit_clear(struct scsc_mif_abs *interface, int bit_num)
1557 {
1558 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1559
1560 if (bit_num >= 16) {
1561 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev, "Incorrect INT number: %d\n", bit_num);
1562 return;
1563 }
1564 /* WRITE : 1 = Clears Interrupt */
1565 platform_mif_reg_write(platform, MAILBOX_WLBT_REG(INTCR0), ((1 << bit_num) << 16));
1566 SCSC_TAG_DEBUG_DEV(PLAT_MIF, platform->dev, "Setting INTCR0: bit %d\n", bit_num);
1567 }
1568
1569 static void platform_mif_irq_bit_mask(struct scsc_mif_abs *interface, int bit_num)
1570 {
1571 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1572 u32 val;
1573 unsigned long flags;
1574
1575 if (bit_num >= 16) {
1576 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev, "Incorrect INT number: %d\n", bit_num);
1577 return;
1578 }
1579 spin_lock_irqsave(&platform->mif_spinlock, flags);
1580 val = platform_mif_reg_read(platform, MAILBOX_WLBT_REG(INTMR0));
1581 /* WRITE : 1 = Mask Interrupt */
1582 platform_mif_reg_write(platform, MAILBOX_WLBT_REG(INTMR0), val | ((1 << bit_num) << 16));
1583 spin_unlock_irqrestore(&platform->mif_spinlock, flags);
1584 SCSC_TAG_DEBUG_DEV(PLAT_MIF, platform->dev, "Setting INTMR0: 0x%x bit %d\n", val | (1 << bit_num), bit_num);
1585 }
1586
1587 static void platform_mif_irq_bit_unmask(struct scsc_mif_abs *interface, int bit_num)
1588 {
1589 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1590 u32 val;
1591 unsigned long flags;
1592
1593 if (bit_num >= 16) {
1594 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev, "Incorrect INT number: %d\n", bit_num);
1595 return;
1596 }
1597 spin_lock_irqsave(&platform->mif_spinlock, flags);
1598 val = platform_mif_reg_read(platform, MAILBOX_WLBT_REG(INTMR0));
1599 /* WRITE : 0 = Unmask Interrupt */
1600 platform_mif_reg_write(platform, MAILBOX_WLBT_REG(INTMR0), val & ~((1 << bit_num) << 16));
1601 spin_unlock_irqrestore(&platform->mif_spinlock, flags);
1602 SCSC_TAG_DEBUG_DEV(PLAT_MIF, platform->dev, "UNMASK Setting INTMR0: 0x%x bit %d\n", val & ~((1 << bit_num) << 16), bit_num);
1603 }
1604
1605 /* Return the contents of the mask register */
1606 static u32 __platform_mif_irq_bit_mask_read(struct platform_mif *platform)
1607 {
1608 u32 val;
1609 unsigned long flags;
1610
1611 spin_lock_irqsave(&platform->mif_spinlock, flags);
1612 val = platform_mif_reg_read(platform, MAILBOX_WLBT_REG(INTMR0));
1613 spin_unlock_irqrestore(&platform->mif_spinlock, flags);
1614 SCSC_TAG_DEBUG_DEV(PLAT_MIF, platform->dev, "Read INTMR0: 0x%x\n", val);
1615
1616 return val;
1617 }
1618
1619 /* Write the mask register, destroying previous contents */
1620 static void __platform_mif_irq_bit_mask_write(struct platform_mif *platform, u32 val)
1621 {
1622 unsigned long flags;
1623
1624 spin_lock_irqsave(&platform->mif_spinlock, flags);
1625 platform_mif_reg_write(platform, MAILBOX_WLBT_REG(INTMR0), val);
1626 spin_unlock_irqrestore(&platform->mif_spinlock, flags);
1627 SCSC_TAG_DEBUG_DEV(PLAT_MIF, platform->dev, "Write INTMR0: 0x%x\n", val);
1628 }
1629
1630 static void platform_mif_irq_reg_handler(struct scsc_mif_abs *interface, void (*handler)(int irq, void *data), void *dev)
1631 {
1632 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1633 unsigned long flags;
1634
1635 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "Registering mif int handler %pS in %p %p\n", handler, platform, interface);
1636 spin_lock_irqsave(&platform->mif_spinlock, flags);
1637 platform->r4_handler = handler;
1638 platform->irq_dev = dev;
1639 spin_unlock_irqrestore(&platform->mif_spinlock, flags);
1640 }
1641
1642 static void platform_mif_irq_unreg_handler(struct scsc_mif_abs *interface)
1643 {
1644 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1645 unsigned long flags;
1646
1647 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "Unregistering mif int handler %pS\n", interface);
1648 spin_lock_irqsave(&platform->mif_spinlock, flags);
1649 platform->r4_handler = platform_mif_irq_default_handler;
1650 platform->irq_dev = NULL;
1651 spin_unlock_irqrestore(&platform->mif_spinlock, flags);
1652 }
1653
1654 static void platform_mif_irq_reg_reset_request_handler(struct scsc_mif_abs *interface, void (*handler)(int irq, void *data), void *dev)
1655 {
1656 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1657
1658 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "Registering mif reset_request int handler %pS in %p %p\n", handler, platform, interface);
1659 platform->reset_request_handler = handler;
1660 platform->irq_reset_request_dev = dev;
1661 if (atomic_read(&platform->wlbt_irq[PLATFORM_MIF_WDOG].irq_disabled_cnt)) {
1662 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev,
1663 "Default WDOG handler disabled by spurios IRQ...re-enabling.\n");
1664 enable_irq(platform->wlbt_irq[PLATFORM_MIF_WDOG].irq_num);
1665 atomic_set(&platform->wlbt_irq[PLATFORM_MIF_WDOG].irq_disabled_cnt, 0);
1666 }
1667 }
1668
1669 static void platform_mif_irq_unreg_reset_request_handler(struct scsc_mif_abs *interface)
1670 {
1671 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1672
1673 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "UnRegistering mif reset_request int handler %pS\n", interface);
1674 platform->reset_request_handler = platform_mif_irq_reset_request_default_handler;
1675 platform->irq_reset_request_dev = NULL;
1676 }
1677
1678 static void platform_mif_suspend_reg_handler(struct scsc_mif_abs *interface,
1679 int (*suspend)(struct scsc_mif_abs *abs, void *data),
1680 void (*resume)(struct scsc_mif_abs *abs, void *data),
1681 void *data)
1682 {
1683 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1684
1685 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "Registering mif suspend/resume handlers in %p %p\n", platform, interface);
1686 platform->suspend_handler = suspend;
1687 platform->resume_handler = resume;
1688 platform->suspendresume_data = data;
1689 }
1690
1691 static void platform_mif_suspend_unreg_handler(struct scsc_mif_abs *interface)
1692 {
1693 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1694
1695 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "Unregistering mif suspend/resume handlers in %p %p\n", platform, interface);
1696 platform->suspend_handler = NULL;
1697 platform->resume_handler = NULL;
1698 platform->suspendresume_data = NULL;
1699 }
1700
1701 static u32 *platform_mif_get_mbox_ptr(struct scsc_mif_abs *interface, u32 mbox_index)
1702 {
1703 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1704 u32 *addr;
1705
1706 SCSC_TAG_DEBUG_DEV(PLAT_MIF, platform->dev, "mbox_index 0x%x\n", mbox_index);
1707 addr = platform->base + MAILBOX_WLBT_REG(ISSR(mbox_index));
1708 return addr;
1709 }
1710
1711 static int platform_mif_get_mifram_ref(struct scsc_mif_abs *interface, void *ptr, scsc_mifram_ref *ref)
1712 {
1713 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1714
1715 SCSC_TAG_DEBUG_DEV(PLAT_MIF, platform->dev, "\n");
1716
1717 if (!platform->mem) {
1718 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev, "Memory unmmaped\n");
1719 return -ENOMEM;
1720 }
1721
1722 /* Check limits! */
1723 if (ptr >= (platform->mem + platform->mem_size)) {
1724 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev, "Unable to get pointer reference\n");
1725 return -ENOMEM;
1726 }
1727
1728 *ref = (scsc_mifram_ref)((uintptr_t)ptr - (uintptr_t)platform->mem);
1729
1730 return 0;
1731 }
1732
1733 static void *platform_mif_get_mifram_ptr(struct scsc_mif_abs *interface, scsc_mifram_ref ref)
1734 {
1735 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1736
1737 SCSC_TAG_DEBUG_DEV(PLAT_MIF, platform->dev, "\n");
1738
1739 if (!platform->mem) {
1740 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev, "Memory unmmaped\n");
1741 return NULL;
1742 }
1743
1744 /* Check limits */
1745 if (ref >= 0 && ref < platform->mem_size)
1746 return (void *)((uintptr_t)platform->mem + (uintptr_t)ref);
1747 else
1748 return NULL;
1749 }
1750
1751 static void *platform_mif_get_mifram_phy_ptr(struct scsc_mif_abs *interface, scsc_mifram_ref ref)
1752 {
1753 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1754
1755 SCSC_TAG_DEBUG_DEV(PLAT_MIF, platform->dev, "\n");
1756
1757 if (!platform->mem_start) {
1758 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev, "Memory unmmaped\n");
1759 return NULL;
1760 }
1761
1762 return (void *)((uintptr_t)platform->mem_start + (uintptr_t)ref);
1763 }
1764
1765 static uintptr_t platform_mif_get_mif_pfn(struct scsc_mif_abs *interface)
1766 {
1767 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1768
1769 return vmalloc_to_pfn(platform->mem);
1770 }
1771
1772 static struct device *platform_mif_get_mif_device(struct scsc_mif_abs *interface)
1773 {
1774 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1775
1776 SCSC_TAG_DEBUG_DEV(PLAT_MIF, platform->dev, "\n");
1777
1778 return platform->dev;
1779 }
1780
1781 static void platform_mif_irq_clear(void)
1782 {
1783 /* Implement if required */
1784 }
1785
1786 static int platform_mif_read_register(struct scsc_mif_abs *interface, u64 id, u32 *val)
1787 {
1788 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1789
1790 if (id == SCSC_REG_READ_WLBT_STAT) {
1791 regmap_read(platform->pmureg, WLBT_STAT, val);
1792 return 0;
1793 }
1794
1795 return -EIO;
1796 }
1797
1798 static void platform_mif_dump_register(struct scsc_mif_abs *interface)
1799 {
1800 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
1801 unsigned long flags;
1802
1803 spin_lock_irqsave(&platform->mif_spinlock, flags);
1804
1805 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "INTGR0 0x%08x\n", platform_mif_reg_read(platform, MAILBOX_WLBT_REG(INTGR0)));
1806 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "INTGR1 0x%08x\n", platform_mif_reg_read(platform, MAILBOX_WLBT_REG(INTGR1)));
1807 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "INTCR0 0x%08x\n", platform_mif_reg_read(platform, MAILBOX_WLBT_REG(INTCR0)));
1808 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "INTCR1 0x%08x\n", platform_mif_reg_read(platform, MAILBOX_WLBT_REG(INTCR1)));
1809 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "INTMR0 0x%08x\n", platform_mif_reg_read(platform, MAILBOX_WLBT_REG(INTMR0)));
1810 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "INTMR1 0x%08x\n", platform_mif_reg_read(platform, MAILBOX_WLBT_REG(INTMR1)));
1811 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "INTSR0 0x%08x\n", platform_mif_reg_read(platform, MAILBOX_WLBT_REG(INTSR0)));
1812 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "INTSR1 0x%08x\n", platform_mif_reg_read(platform, MAILBOX_WLBT_REG(INTSR1)));
1813 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "INTMSR0 0x%08x\n", platform_mif_reg_read(platform, MAILBOX_WLBT_REG(INTMSR0)));
1814 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "INTMSR1 0x%08x\n", platform_mif_reg_read(platform, MAILBOX_WLBT_REG(INTMSR1)));
1815
1816 spin_unlock_irqrestore(&platform->mif_spinlock, flags);
1817 }
1818
1819 static void platform_mif_cleanup(struct scsc_mif_abs *interface)
1820 {
1821 }
1822
1823 static void platform_mif_restart(struct scsc_mif_abs *interface)
1824 {
1825 }
1826
1827 #ifdef CONFIG_OF_RESERVED_MEM
1828 static int __init platform_mif_wifibt_if_reserved_mem_setup(struct reserved_mem *remem)
1829 {
1830 SCSC_TAG_DEBUG(PLAT_MIF, "memory reserved: mem_base=%#lx, mem_size=%zd\n",
1831 (unsigned long)remem->base, (size_t)remem->size);
1832
1833 sharedmem_base = remem->base;
1834 sharedmem_size = remem->size;
1835 return 0;
1836 }
1837 RESERVEDMEM_OF_DECLARE(wifibt_if, "exynos,wifibt_if", platform_mif_wifibt_if_reserved_mem_setup);
1838 #endif
1839
1840 struct scsc_mif_abs *platform_mif_create(struct platform_device *pdev)
1841 {
1842 struct scsc_mif_abs *platform_if;
1843 struct platform_mif *platform =
1844 (struct platform_mif *)devm_kzalloc(&pdev->dev, sizeof(struct platform_mif), GFP_KERNEL);
1845 int err = 0;
1846 u8 i = 0;
1847 struct resource *reg_res;
1848
1849 #ifdef CONFIG_SCSC_SMAPPER
1850 u32 smapper_banks = 0;
1851 #endif
1852
1853 if (!platform)
1854 return NULL;
1855
1856 SCSC_TAG_INFO_DEV(PLAT_MIF, &pdev->dev, "Creating MIF platform device\n");
1857
1858 platform_if = &platform->interface;
1859
1860 /* initialise interface structure */
1861 platform_if->destroy = platform_mif_destroy;
1862 platform_if->get_uid = platform_mif_get_uid;
1863 platform_if->reset = platform_mif_reset;
1864 platform_if->map = platform_mif_map;
1865 platform_if->unmap = platform_mif_unmap;
1866 platform_if->irq_bit_set = platform_mif_irq_bit_set;
1867 platform_if->irq_get = platform_mif_irq_get;
1868 platform_if->irq_bit_mask_status_get = platform_mif_irq_bit_mask_status_get;
1869 platform_if->irq_bit_clear = platform_mif_irq_bit_clear;
1870 platform_if->irq_bit_mask = platform_mif_irq_bit_mask;
1871 platform_if->irq_bit_unmask = platform_mif_irq_bit_unmask;
1872 platform_if->irq_reg_handler = platform_mif_irq_reg_handler;
1873 platform_if->irq_unreg_handler = platform_mif_irq_unreg_handler;
1874 platform_if->irq_reg_reset_request_handler = platform_mif_irq_reg_reset_request_handler;
1875 platform_if->irq_unreg_reset_request_handler = platform_mif_irq_unreg_reset_request_handler;
1876 platform_if->suspend_reg_handler = platform_mif_suspend_reg_handler;
1877 platform_if->suspend_unreg_handler = platform_mif_suspend_unreg_handler;
1878 platform_if->get_mbox_ptr = platform_mif_get_mbox_ptr;
1879 platform_if->get_mifram_ptr = platform_mif_get_mifram_ptr;
1880 platform_if->get_mifram_ref = platform_mif_get_mifram_ref;
1881 platform_if->get_mifram_pfn = platform_mif_get_mif_pfn;
1882 platform_if->get_mifram_phy_ptr = platform_mif_get_mifram_phy_ptr;
1883 platform_if->get_mif_device = platform_mif_get_mif_device;
1884 platform_if->irq_clear = platform_mif_irq_clear;
1885 platform_if->mif_dump_registers = platform_mif_dump_register;
1886 platform_if->mif_read_register = platform_mif_read_register;
1887 platform_if->mif_cleanup = platform_mif_cleanup;
1888 platform_if->mif_restart = platform_mif_restart;
1889 #ifdef CONFIG_SCSC_SMAPPER
1890 platform_if->mif_smapper_get_mapping = platform_mif_smapper_get_mapping;
1891 platform_if->mif_smapper_get_bank_info = platform_mif_smapper_get_bank_info;
1892 platform_if->mif_smapper_write_sram = platform_mif_smapper_write_sram;
1893 platform_if->mif_smapper_configure = platform_mif_smapper_configure;
1894 platform_if->mif_smapper_get_bank_base_address = platform_mif_smapper_get_bank_base_address;
1895 #endif
1896 #ifdef CONFIG_SCSC_QOS
1897 platform_if->mif_pm_qos_add_request = platform_mif_pm_qos_add_request;
1898 platform_if->mif_pm_qos_update_request = platform_mif_pm_qos_update_request;
1899 platform_if->mif_pm_qos_remove_request = platform_mif_pm_qos_remove_request;
1900 #endif
1901 /* Update state */
1902 platform->pdev = pdev;
1903 platform->dev = &pdev->dev;
1904
1905 platform->r4_handler = platform_mif_irq_default_handler;
1906 platform->irq_dev = NULL;
1907 platform->reset_request_handler = platform_mif_irq_reset_request_default_handler;
1908 platform->irq_reset_request_dev = NULL;
1909 platform->suspend_handler = NULL;
1910 platform->resume_handler = NULL;
1911 platform->suspendresume_data = NULL;
1912
1913 #ifdef CONFIG_OF_RESERVED_MEM
1914 platform->mem_start = sharedmem_base;
1915 platform->mem_size = sharedmem_size;
1916 #else
1917 /* If CONFIG_OF_RESERVED_MEM is not defined, sharedmem values should be
1918 * parsed from the scsc_wifibt binding
1919 */
1920 if (of_property_read_u32(pdev->dev.of_node, "sharedmem-base", &sharedmem_base)) {
1921 err = -EINVAL;
1922 goto error_exit;
1923 }
1924 platform->mem_start = sharedmem_base;
1925
1926 if (of_property_read_u32(pdev->dev.of_node, "sharedmem-size", &sharedmem_size)) {
1927 err = -EINVAL;
1928 goto error_exit;
1929 }
1930 platform->mem_size = sharedmem_size;
1931 #endif
1932 #ifdef CONFIG_SCSC_SMAPPER
1933 platform->smapper = NULL;
1934 #endif
1935
1936 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "platform->mem_start 0x%x platform->mem_size 0x%x\n",
1937 (u32)platform->mem_start, (u32)platform->mem_size);
1938 if (platform->mem_start == 0)
1939 SCSC_TAG_WARNING_DEV(PLAT_MIF, platform->dev, "platform->mem_start is 0");
1940
1941 if (platform->mem_size == 0) {
1942 /* We return return if mem_size is 0 as it does not make any sense.
1943 * This may be an indication of an incorrect platform device binding.
1944 */
1945 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev, "platform->mem_size is 0");
1946 err = -EINVAL;
1947 goto error_exit;
1948 }
1949
1950 /* Memory resource - Phys Address of MAILBOX_WLBT register map */
1951 reg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1952 if (!reg_res) {
1953 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
1954 "Error getting mem resource for MAILBOX_WLBT\n");
1955 err = -ENOENT;
1956 goto error_exit;
1957 }
1958
1959 platform->reg_start = reg_res->start;
1960 platform->reg_size = resource_size(reg_res);
1961
1962 platform->base =
1963 devm_ioremap_nocache(platform->dev, reg_res->start, resource_size(reg_res));
1964
1965 if (!platform->base) {
1966 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
1967 "Error mapping register region\n");
1968 err = -EBUSY;
1969 goto error_exit;
1970 }
1971 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "platform->reg_start %lx size %x base %p\n",
1972 (uintptr_t)platform->reg_start, (u32)platform->reg_size, platform->base);
1973
1974 /* Get the 4 IRQ resources */
1975 for (i = 0; i < 4; i++) {
1976 struct resource *irq_res;
1977 int irqtag;
1978
1979 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1980 if (!irq_res) {
1981 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
1982 "No IRQ resource at index %d\n", i);
1983 err = -ENOENT;
1984 goto error_exit;
1985 }
1986
1987 if (!strcmp(irq_res->name, "MBOX")) {
1988 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "MBOX irq %d flag 0x%x\n",
1989 (u32)irq_res->start, (u32)irq_res->flags);
1990 irqtag = PLATFORM_MIF_MBOX;
1991 } else if (!strcmp(irq_res->name, "ALIVE")) {
1992 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "ALIVE irq %d flag 0x%x\n",
1993 (u32)irq_res->start, (u32)irq_res->flags);
1994 irqtag = PLATFORM_MIF_ALIVE;
1995 } else if (!strcmp(irq_res->name, "WDOG")) {
1996 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "WDOG irq %d flag 0x%x\n",
1997 (u32)irq_res->start, (u32)irq_res->flags);
1998 irqtag = PLATFORM_MIF_WDOG;
1999 } else if (!strcmp(irq_res->name, "CFG_REQ")) {
2000 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "CFG_REQ irq %d flag 0x%x\n",
2001 (u32)irq_res->start, (u32)irq_res->flags);
2002 irqtag = PLATFORM_MIF_CFG_REQ;
2003 } else {
2004 SCSC_TAG_ERR_DEV(PLAT_MIF, &pdev->dev, "Invalid irq res name: %s\n",
2005 irq_res->name);
2006 err = -EINVAL;
2007 goto error_exit;
2008 }
2009 platform->wlbt_irq[irqtag].irq_num = irq_res->start;
2010 platform->wlbt_irq[irqtag].flags = (irq_res->flags & IRQF_TRIGGER_MASK);
2011 atomic_set(&platform->wlbt_irq[irqtag].irq_disabled_cnt, 0);
2012 }
2013
2014 /* PMU reg map - syscon */
2015 platform->pmureg = syscon_regmap_lookup_by_phandle(platform->dev->of_node,
2016 "samsung,syscon-phandle");
2017 if (IS_ERR(platform->pmureg)) {
2018 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
2019 "syscon regmap lookup failed. Aborting. %ld\n",
2020 PTR_ERR(platform->pmureg));
2021 err = -EINVAL;
2022 goto error_exit;
2023 }
2024
2025 /* Completion event and state used to indicate CFG_REQ IRQ occurred */
2026 init_completion(&platform->cfg_ack);
2027 platform->boot_state = WLBT_BOOT_IN_RESET;
2028
2029 /* I3C_APM_PMIC */
2030 platform->i3c_apm_pmic = syscon_regmap_lookup_by_phandle(platform->dev->of_node,
2031 "samsung,i3c_apm_pmic-syscon-phandle");
2032 if (IS_ERR(platform->i3c_apm_pmic)) {
2033 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
2034 "i3c_apm_pmic regmap lookup failed. Aborting. %ld\n",
2035 PTR_ERR(platform->i3c_apm_pmic));
2036 err = -EINVAL;
2037 goto error_exit;
2038 }
2039
2040 /* DBUS_BAAW */
2041 platform->dbus_baaw = syscon_regmap_lookup_by_phandle(platform->dev->of_node,
2042 "samsung,dbus_baaw-syscon-phandle");
2043 if (IS_ERR(platform->dbus_baaw)) {
2044 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
2045 "dbus_baaw regmap lookup failed. Aborting. %ld\n",
2046 PTR_ERR(platform->dbus_baaw));
2047 err = -EINVAL;
2048 goto error_exit;
2049 }
2050
2051 /* PBUS_BAAW */
2052 platform->pbus_baaw = syscon_regmap_lookup_by_phandle(platform->dev->of_node,
2053 "samsung,pbus_baaw-syscon-phandle");
2054 if (IS_ERR(platform->pbus_baaw)) {
2055 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
2056 "pbus_baaw regmap lookup failed. Aborting. %ld\n",
2057 PTR_ERR(platform->pbus_baaw));
2058 err = -EINVAL;
2059 goto error_exit;
2060 }
2061
2062 /* WLBT_REMAP */
2063 platform->wlbt_remap = syscon_regmap_lookup_by_phandle(platform->dev->of_node,
2064 "samsung,wlbt_remap-syscon-phandle");
2065 if (IS_ERR(platform->wlbt_remap)) {
2066 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
2067 "wlbt_remap regmap lookup failed. Aborting. %ld\n",
2068 PTR_ERR(platform->wlbt_remap));
2069 err = -EINVAL;
2070 goto error_exit;
2071 }
2072
2073 /* BOOT_CFG */
2074 platform->boot_cfg = syscon_regmap_lookup_by_phandle(platform->dev->of_node,
2075 "samsung,boot_cfg-syscon-phandle");
2076 if (IS_ERR(platform->boot_cfg)) {
2077 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
2078 "boot_cfg regmap lookup failed. Aborting. %ld\n",
2079 PTR_ERR(platform->boot_cfg));
2080 err = -EINVAL;
2081 goto error_exit;
2082 }
2083
2084 #ifdef CONFIG_SCSC_SMAPPER
2085 /* SMAPPER parsing */
2086 if (!of_property_read_u32(pdev->dev.of_node, "smapper_num_banks", &smapper_banks))
2087 platform_mif_parse_smapper(platform, platform->dev->of_node, smapper_banks);
2088
2089 #endif
2090 #ifdef CONFIG_SCSC_QOS
2091 platform_mif_parse_qos(platform, platform->dev->of_node);
2092 #endif
2093 /* Initialize spinlock */
2094 spin_lock_init(&platform->mif_spinlock);
2095
2096 return platform_if;
2097
2098 error_exit:
2099 devm_kfree(&pdev->dev, platform);
2100 return NULL;
2101 }
2102
2103 void platform_mif_destroy_platform(struct platform_device *pdev, struct scsc_mif_abs *interface)
2104 {
2105 }
2106
2107 struct platform_device *platform_mif_get_platform_dev(struct scsc_mif_abs *interface)
2108 {
2109 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
2110
2111 BUG_ON(!interface || !platform);
2112
2113 return platform->pdev;
2114 }
2115
2116 struct device *platform_mif_get_dev(struct scsc_mif_abs *interface)
2117 {
2118 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
2119
2120 BUG_ON(!interface || !platform);
2121
2122 return platform->dev;
2123 }
2124
2125 /* Preserve MIF registers during suspend.
2126 * If all users of the MIF (AP, mx140, CP, etc) release it, the registers
2127 * will lose their values. Save the useful subset here.
2128 *
2129 * Assumption: the AP will not change the register values between the suspend
2130 * and resume handlers being called!
2131 */
2132 static void platform_mif_reg_save(struct platform_mif *platform)
2133 {
2134 platform->mif_preserve.irq_bit_mask = __platform_mif_irq_bit_mask_read(platform);
2135 }
2136
2137 /* Restore MIF registers that may have been lost during suspend */
2138 static void platform_mif_reg_restore(struct platform_mif *platform)
2139 {
2140 __platform_mif_irq_bit_mask_write(platform, platform->mif_preserve.irq_bit_mask);
2141 }
2142
2143 int platform_mif_suspend(struct scsc_mif_abs *interface)
2144 {
2145 int r = 0;
2146 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
2147
2148 if (platform->suspend_handler)
2149 r = platform->suspend_handler(interface, platform->suspendresume_data);
2150
2151 /* Save the MIF registers.
2152 * This must be done last as the suspend_handler may use the MIF
2153 */
2154 platform_mif_reg_save(platform);
2155
2156 return r;
2157 }
2158
2159 void platform_mif_resume(struct scsc_mif_abs *interface)
2160 {
2161 struct platform_mif *platform = platform_mif_from_mif_abs(interface);
2162 s32 ret;
2163
2164 /* Restore the MIF registers.
2165 * This must be done first as the resume_handler may use the MIF.
2166 */
2167 platform_mif_reg_restore(platform);
2168
2169 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "Clear WLBT_ACTIVE_CLR flag\n");
2170 /* Clear WLBT_ACTIVE_CLR flag in WLBT_CTRL_NS */
2171 ret = regmap_update_bits(platform->pmureg, WLBT_CTRL_NS,
2172 BIT(6), BIT(6)); /* WLBT_ACTIVE_CLR*/
2173 if (ret < 0) {
2174 SCSC_TAG_ERR_DEV(PLAT_MIF, platform->dev,
2175 "Failed to Set WLBT_CTRL_NS[WLBT_ACTIVE_CLR]: %d\n", ret);
2176 }
2177
2178 if (platform->resume_handler)
2179 platform->resume_handler(interface, platform->suspendresume_data);
2180 }
2181
2182 /* Temporary workaround to power up slave PMIC LDOs before FW APM/WLBT signalling
2183 * is complete
2184 */
2185 static void power_supplies_on(struct platform_mif *platform)
2186 {
2187 struct i2c_client i2c;
2188
2189 /* HACK: Note only addr field is needed by s2mpu11_write_reg() */
2190 i2c.addr = 0x1;
2191
2192 SCSC_TAG_INFO_DEV(PLAT_MIF, platform->dev, "WLBT LDOs on (PMIC i2c_addr = 0x%x)\n", i2c.addr);
2193 /* SLAVE PMIC
2194 * adb shell "echo 0x3C > sys/class/pmic/s2mpu12/s2mpu12_read"
2195 * adb shell "echo 0x3C 0xE0 > sys/class/pmic/s2mpu12/s2mpu12_write"
2196 * adb shell "echo 0x3D > /sys/class/pmic/s2mpu12/s2mpu12_read"
2197 * adb shell "echo 0x3D 0xE0 > /sys/class/pmic/s2mpu12/s2mpu12_write"
2198 * adb shell "echo 0x3E > /sys/class/pmic/s2mpu12/s2mpu12_read"
2199 * adb shell "echo 0x3E 0xEC > /sys/class/pmic/s2mpu12/s2mpu12_write"
2200 * adb shell "echo 0x40 > /sys/class/pmic/s2mpu12/s2mpu12_read"
2201 * adb shell "echo 0x40 0xFC > /sys/class/pmic/s2mpu12/s2mpu12_write"
2202 */
2203
2204 s2mpu12_write_reg(&i2c, 0x3C, 0xE0); /* LDO 18 */
2205 s2mpu12_write_reg(&i2c, 0x3D, 0xE0); /* LDO 19 */
2206 s2mpu12_write_reg(&i2c, 0x3E, 0xEC); /* LDO 20 */
2207 s2mpu12_write_reg(&i2c, 0x40, 0xFC); /* LDO 22 */
2208 }
Motorola kernel-slsi