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[RAMEN9610-9865][9609] driver: gpu: Update Robusta2 Mali-GPU DDK from r10p0 to r16p0
[GitHub/MotorolaMobilityLLC/kernel-slsi.git] / arch / arm64 / boot / dts / exynos / exynos9610.dtsi
1 /*
2 * SAMSUNG EXYNOS9610 SoC device tree source
3 *
4 * Copyright (c) 2017 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS9610 SoC device nodes are listed in this file.
8 * EXYNOS9610 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16 #include <dt-bindings/clock/exynos9610.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include "exynos9610-pinctrl.dtsi"
19 #include "exynos9610-rmem.dtsi"
20 #include "exynos9610-debug.dtsi"
21 #include <dt-bindings/thermal/thermal.h>
22 #include <dt-bindings/ufs/ufs.h>
23 #include "exynos9610-sysmmu.dtsi"
24 #include <dt-bindings/soc/samsung/exynos9610-dm.h>
25 #include "exynos9610-pm-domains.dtsi"
26 #include <dt-bindings/soc/samsung/exynos9610-devfreq.h>
27 #include "exynos9610-mfc.dtsi"
28 #include "exynos9610-camera.dtsi"
29 #include <dt-bindings/soc/samsung/exynos-bcm_dbg.h>
30
31 / {
32 compatible = "samsung,armv8", "samsung,exynos9610";
33 interrupt-parent = <&gic>;
34 #address-cells = <2>;
35 #size-cells = <1>;
36
37 aliases {
38 pinctrl0 = &pinctrl_0;
39 pinctrl1 = &pinctrl_1;
40 pinctrl2 = &pinctrl_2;
41 pinctrl3 = &pinctrl_3;
42 pinctrl4 = &pinctrl_4;
43 pinctrl5 = &pinctrl_5;
44 usi0 = &usi_0_shub;
45 usi1 = &usi_0_shub_i2c;
46 usi2 = &usi_0_cmgp;
47 usi3 = &usi_0_cmgp_i2c;
48 usi4 = &usi_1_cmgp;
49 usi5 = &usi_1_cmgp_i2c;
50 usi6 = &usi_2_cmgp;
51 usi7 = &usi_2_cmgp_i2c;
52 usi8 = &usi_3_cmgp;
53 usi9 = &usi_3_cmgp_i2c;
54 usi10 = &usi_4_cmgp;
55 usi11 = &usi_4_cmgp_i2c;
56 usi12 = &usi_peri_uart;
57 usi13 = &usi_peri_cami2c_0;
58 usi14 = &usi_peri_cami2c_1;
59 usi15 = &usi_peri_cami2c_2;
60 usi16 = &usi_peri_cami2c_3;
61 usi17 = &usi_peri_spi_0;
62 usi18 = &usi_peri_spi_1;
63 usi19 = &usi_peri_usi_0;
64 usi20 = &usi_peri_usi_0_i2c;
65 usi21 = &usi_peri_spi_2;
66 hsi2c0 = &hsi2c_0;
67 hsi2c1 = &hsi2c_1;
68 hsi2c2 = &hsi2c_2;
69 hsi2c3 = &hsi2c_3;
70 hsi2c4 = &hsi2c_4;
71 hsi2c5 = &hsi2c_5;
72 hsi2c6 = &hsi2c_6;
73 hsi2c7 = &hsi2c_7;
74 hsi2c8 = &hsi2c_8;
75 hsi2c9 = &hsi2c_9;
76 hsi2c10 = &hsi2c_10;
77 hsi2c11 = &hsi2c_11;
78 hsi2c12 = &hsi2c_12;
79 hsi2c13 = &hsi2c_13;
80 hsi2c14 = &hsi2c_14;
81 hsi2c15 = &hsi2c_15;
82 hsi2c16 = &hsi2c_16;
83 hsi2c17 = &hsi2c_17;
84 spi0 = &spi_0;
85 spi1 = &spi_1;
86 spi2 = &spi_2;
87 spi3 = &spi_3;
88 spi4 = &spi_4;
89 spi5 = &spi_5;
90 spi6 = &spi_6;
91 spi7 = &spi_7;
92 spi8 = &spi_8;
93 spi9 = &spi_9;
94 uart0 = &serial_0;
95 uart1 = &serial_1;
96 uart2 = &serial_2;
97 uart3 = &serial_3;
98 uart4 = &serial_4;
99 uart5 = &serial_5;
100 uart6 = &serial_6;
101 uart7 = &serial_7;
102 fmp0 = &fmp_0;
103 contexthub0 = &contexthub_0;
104 dpp0 = &dpp_0;
105 dpp1 = &dpp_1;
106 dpp2 = &dpp_2;
107 dpp3 = &dpp_3;
108 dsim0 = &dsim_0;
109 decon0 = &decon_f;
110 scaler0 = &scaler_0;
111 mfc0 = &mfc_0;
112 mshc2 = &dwmmc_2;
113 };
114
115 ect {
116 parameter_address = <0x90000000>;
117 parameter_size = <0x19000>;
118 };
119
120 chosen {
121 bootargs = "console=ram androidboot.dtbo_idx=0 skip_initramfs rootwait ro init=/init clk_ignore_unused bcm_setup=0xffffff80f8e00000 androidboot.hardware=exynos9610 androidboot.selinux=permissive androidboot.debug_level=0x4948 firmware_class.path=/vendor/firmware ecd_setup=disable reserve-fimc=0xffffff80f9fe0000 pmic_info=0x3 ccic_info=0x1 epx_activate=true";
122 linux,initrd-start = <0x84000000>;
123 linux,initrd-end = <0x841FFFFF>;
124 };
125
126 chipid@10000000 {
127 compatible = "samsung,exynos9-chipid";
128 reg = <0x0 0x10000000 0x100>, <0x0 0x2038848 0x10>;
129 };
130
131 arm-pmu {
132 compatible = "arm,armv8-pmuv3";
133 interrupts = <0 82 4>,
134 <0 83 4>,
135 <0 84 4>,
136 <0 85 4>,
137 <0 96 4>,
138 <0 97 4>,
139 <0 98 4>,
140 <0 99 4>;
141 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>,
142 <&cpu3>, <&cpu4>, <&cpu5>,
143 <&cpu6>, <&cpu7>;
144 };
145
146 cpus {
147 #address-cells = <2>;
148 #size-cells = <0>;
149
150 cpu-map {
151 cluster0 {
152 coregroup0 {
153 core0 {
154 cpu = <&cpu0>;
155 };
156 core1 {
157 cpu = <&cpu1>;
158 };
159 core2 {
160 cpu = <&cpu2>;
161 };
162 core3 {
163 cpu = <&cpu3>;
164 };
165 };
166 };
167
168 cluster1 {
169 coregroup0 {
170 core0 {
171 cpu = <&cpu4>;
172 };
173 core1 {
174 cpu = <&cpu5>;
175 };
176 core2 {
177 cpu = <&cpu6>;
178 };
179 core3 {
180 cpu = <&cpu7>;
181 };
182 };
183 };
184
185 };
186
187 cpu0: cpu@100 {
188 device_type = "cpu";
189 compatible = "arm,cortex-a53", "arm,armv8";
190 reg = <0x0 0x0>;
191 enable-method = "psci";
192 cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
193 sched-energy-data = <&A53_ENERGY>;
194 };
195 cpu1: cpu@101 {
196 device_type = "cpu";
197 compatible = "arm,cortex-a53", "arm,armv8";
198 reg = <0x0 0x1>;
199 enable-method = "psci";
200 cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
201 sched-energy-data = <&A53_ENERGY>;
202 };
203 cpu2: cpu@102 {
204 device_type = "cpu";
205 compatible = "arm,cortex-a53", "arm,armv8";
206 reg = <0x0 0x2>;
207 enable-method = "psci";
208 cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
209 sched-energy-data = <&A53_ENERGY>;
210 };
211 cpu3: cpu@103 {
212 device_type = "cpu";
213 compatible = "arm,cortex-a53", "arm,armv8";
214 reg = <0x0 0x3>;
215 enable-method = "psci";
216 cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
217 sched-energy-data = <&A53_ENERGY>;
218 };
219 cpu4: cpu@0 {
220 device_type = "cpu";
221 compatible = "arm,cortex-a73", "arm,armv8";
222 reg = <0x0 0x100>;
223 enable-method = "psci";
224 cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
225 sched-energy-data = <&A73_ENERGY>;
226 };
227 cpu5: cpu@1 {
228 device_type = "cpu";
229 compatible = "arm,cortex-a73", "arm,armv8";
230 reg = <0x0 0x101>;
231 enable-method = "psci";
232 cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
233 sched-energy-data = <&A73_ENERGY>;
234 };
235 cpu6: cpu@2 {
236 device_type = "cpu";
237 compatible = "arm,cortex-a73", "arm,armv8";
238 reg = <0x0 0x102>;
239 enable-method = "psci";
240 cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
241 sched-energy-data = <&A73_ENERGY>;
242 };
243 cpu7: cpu@3 {
244 device_type = "cpu";
245 compatible = "arm,cortex-a73", "arm,armv8";
246 reg = <0x0 0x103>;
247 enable-method = "psci";
248 cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
249 sched-energy-data = <&A73_ENERGY>;
250 };
251
252 idle-states {
253 entry-method = "arm,psci";
254
255 BOOTCL_CPU_SLEEP: bootcl-cpu-sleep {
256 idle-state-name = "c2";
257 compatible = "exynos,idle-state";
258 arm,psci-suspend-param = <0x0010000>;
259 entry-latency-us = <35>;
260 exit-latency-us = <90>;
261 min-residency-us = <750>;
262 status = "okay";
263 };
264
265 NONBOOTCL_CPU_SLEEP: nobootcl-cpu-sleep {
266 idle-state-name = "c2";
267 compatible = "exynos,idle-state";
268 arm,psci-suspend-param = <0x0010000>;
269 entry-latency-us = <30>;
270 exit-latency-us = <75>;
271 min-residency-us = <2000>;
272 status = "okay";
273 };
274 };
275
276 energy-data {
277 A53_ENERGY: a53-energy {
278 capacity-mips = <230>;
279 power-coefficient = <450>;
280 };
281 A73_ENERGY: a73-energy {
282 capacity-mips = <480>;
283 power-coefficient = <870>;
284 };
285 };
286
287 ems {
288 /* Ontime Migration */
289 ontime {
290 /* little cores */
291 coregroup0 {
292 lower-boundary = <0>;
293 upper-boundary = <68>;
294 coverage-ratio = <100>;
295 };
296 /* big cores */
297 coregroup1 {
298 lower-boundary = <17>;
299 upper-boundary = <100>;
300 coverage-ratio = <75>;
301 };
302 };
303
304 /* Load Balance Trigger */
305 #define DEFAULT_RATIO 80
306 lbt {
307 overutil-level0 {
308 cpus = "0-3",
309 "4-7";
310 ratio = <30>,
311 <40>;
312 };
313 overutil-level1 {
314 cpus = "0-7";
315 ratio = <DEFAULT_RATIO>;
316 };
317 };
318
319 /* FRT Migration */
320 frt {
321 /* little cores */
322 coregroup0 {
323 coverage-ratio = <30>;
324 active-ratio = <25>;
325 };
326 /* big cores */
327 coregroup1 {
328 coverage-ratio = <15>;
329 active-ratio = <5>;
330 };
331 };
332
333 prefer-perf-service {
334 prefer-perf0 {
335 boost = <1>;
336 light-task-threshold = <0>;
337 prefer-cpus = "4-7", "0-3";
338 };
339 };
340 };
341 };
342
343 psci {
344 compatible = "arm,psci";
345 method = "smc";
346 cpu_suspend = <0xC4000001>;
347 cpu_off = <0x84000002>;
348 cpu_on = <0xC4000003>;
349 };
350
351 cpupm {
352 #define POWERMODE_TYPE_CLUSTER 0
353 #define POWERMODE_TYPE_SYSTEM 1
354
355 cpd_cl0 {
356 device_type = "cpupm";
357 target-residency = <10000>;
358 psci-index = <128>;
359 type = <POWERMODE_TYPE_CLUSTER>;
360 siblings = "0-3";
361 };
362
363 cpd_cl1 {
364 device_type = "cpupm";
365 target-residency = <3000>;
366 psci-index = <128>;
367 type = <POWERMODE_TYPE_CLUSTER>;
368 siblings = "4-7";
369 entry-allowed = "4-7";
370 };
371
372 sicd {
373 device_type = "cpupm";
374 target-residency = <3000>; /* us */
375 psci-index = <256>;
376 type = <POWERMODE_TYPE_SYSTEM>;
377 siblings = "0-7";
378 entry-allowed = "0-3";
379 system-idle;
380 };
381
382 idle-ip {
383 idle-ip-list =
384 "13970000.pwm", /* [ 0] pwm */
385 "11c30000.adc", /* [ 1] adc */
386 "110c0000.hsi2c", /* [ 2] hsi2c_0 */
387 "110d0000.hsi2c", /* [ 3] hsi2c_1 */
388 "11d00000.hsi2c", /* [ 4] hsi2c_2 */
389 "11d10000.hsi2c", /* [ 5] hsi2c_3 */
390 "11d20000.hsi2c", /* [ 6] hsi2c_4 */
391 "11d30000.hsi2c", /* [ 7] hsi2c_5 */
392 "11d40000.hsi2c", /* [ 8] hsi2c_6 */
393 "11d50000.hsi2c", /* [ 9] hsi2c_7 */
394 "11d60000.hsi2c", /* [10] hsi2c_8 */
395 "11d70000.hsi2c", /* [11] hsi2c_9 */
396 "11d80000.hsi2c", /* [12] hsi2c_10 */
397 "11d90000.hsi2c", /* [13] hsi2c_11 */
398 "138a0000.hsi2c", /* [14] hsi2c_12 */
399 "138b0000.hsi2c", /* [15] hsi2c_13 */
400 "138c0000.hsi2c", /* [16] hsi2c_14 */
401 "138d0000.hsi2c", /* [17] hsi2c_15 */
402 "13920000.hsi2c", /* [18] hsi2c_16 */
403 "13930000.hsi2c", /* [19] hsi2c_17 */
404 "13830000.i2c", /* [20] i2c_0 */
405 "13840000.i2c", /* [21] i2c_1 */
406 "13850000.i2c", /* [22] i2c_2 */
407 "13860000.i2c", /* [23] i2c_3 */
408 "13870000.i2c", /* [24] i2c_4 */
409 "13880000.i2c", /* [25] i2c_5 */
410 "13890000.i2c", /* [26] i2c_6 */
411 "110c0000.spi", /* [27] spi_0 */
412 "11d00000.spi", /* [28] spi_1 */
413 "11d20000.spi", /* [29] spi_2 */
414 "11d40000.spi", /* [30] spi_3 */
415 "11d60000.spi", /* [31] spi_4 */
416 "11d80000.spi", /* [32] spi_5 */
417 "13900000.spi", /* [33] spi_6 */
418 "13910000.spi", /* [34] spi_7 */
419 "13920000.spi", /* [35] spi_8 */
420 "13940000.spi", /* [36] spi_9 */
421 "13520000.ufs", /* [37] ufs */
422 "13500000.dwmmc0", /* [38] dwmmc0 */
423 "13550000.dwmmc2", /* [39] dwmmc2 */
424 "13200000.usb", /* [40] usb */
425 "pd-cam", /* [41] pd-cam */
426 "pd-isp", /* [42] pd-isp */
427 "pd-vipx1", /* [43] pd-vipx1 */
428 "pd-vipx2", /* [44] pd-vipx2 */
429 "pd-g2d", /* [45] pd-g2d */
430 "pd-g3d", /* [46] pd-g3d */
431 "pd-dispaud", /* [47] pd-dispaud */
432 "pd-mfc", /* [48] pd-mfc */
433 "148e0000.dsim"; /* [49] dsim_0 */
434
435 fix-idle-ip = "acpm_dvfs";
436 fix-idle-ip-index = <96>;
437
438 idle-ip-mask =
439 <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>,
440 <10>, <11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>,
441 <20>, <21>, <22>, <23>, <24>, <25>, <26>, <27>, <28>, <29>,
442 <30>, <31>, <32>, <33>, <34>, <35>, <36>, <37>, <38>, <39>,
443 <40>, <41>, <42>, <43>, <44>, <45>, <46>, <48>, <49>, <96>;
444 };
445 };
446
447 exynos-pm {
448 compatible = "samsung,exynos-pm";
449 reg = <0x0 0x11850000 0x1000>,
450 <0x0 0x12301200 0x100>;
451 reg-names = "gpio_alive_base",
452 "gicd_ispendrn_base";
453 num-eint = <24>;
454 num-gic = <16>;
455 suspend_mode_idx = <8>; /* SYS_SLEEP */
456 suspend_psci_idx = <1024>; /* PSCI_SYSTEM_SLEEP */
457 cp_call_mode_idx = <10>; /* SYS_SLEEP_AUD_ON */
458 cp_call_psci_idx = <1024>; /* PSCI_SYSTEM_SLEEP */
459 usbl2_suspend_available = <1>;
460 usbl2_suspend_mode_idx = <12>; /* SYS_SLEEP_USB_ON */
461 extra_wakeup_stat = <0x60c>;
462 conn_req_offset = <0x00c0>; /* PMU_ALIVE__CONNECT_SLEEP_STATUS */
463 };
464
465 exynos-powermode {
466 wakeup-masks {
467 /*
468 * wakeup_mask configuration
469 * SICD SICD_CPD AFTR STOP
470 * LPD LPA ALPA DSTOP
471 * SLEEP SLEEP_VTS_ON SLEEP_AUD_ON FAPO
472 * SLEEP_USB_L2
473 */
474 wakeup-mask {
475 mask = <0x40000000>, <0x0>, <0x0>, <0x0>,
476 <0x0>, <0x0>, <0x0>, <0x0>,
477 <0xD00D7E7E>, <0x500D7E7E>, <0x500D7E7E>, <0x0>,
478 <0xD00D7E7E>;
479 mask-offset = <0x610>;
480 stat-offset = <0x600>;
481 };
482 wakeup-mask2 {
483 mask = <0x0>, <0x0>, <0x0>, <0x0>,
484 <0x0>, <0x0>, <0x0>, <0x0>,
485 <0xFFFF00FF>, <0xFFFF00FF>, <0xFFFF00FF>, <0x0>,
486 <0xFFFF00FF>;
487 mask-offset = <0x614>;
488 stat-offset = <0x604>;
489 };
490 wakeup-mask3 {
491 mask = <0x0>, <0x0>, <0x0>, <0x0>,
492 <0x0>, <0x0>, <0x0>, <0x0>,
493 <0xFFFF00FF>, <0xFFFF00FF>, <0xFFFF00FF>, <0x0>,
494 <0xFFFF00FF>;
495 mask-offset = <0x618>;
496 stat-offset = <0x608>;
497 };
498 wakeup-mask4 {
499 mask = <0x0>, <0x0>, <0x0>, <0x0>,
500 <0x0>, <0x0>, <0x0>, <0x0>,
501 <0x0>, <0x0>, <0x0>, <0x0>,
502 <0x0>;
503 mask-offset = <0x61c>;
504 stat-offset = <0x610>;
505 };
506 };
507 };
508
509 gic:interrupt-controller@12300000 {
510 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
511 #interrupt-cells = <3>;
512 #address-cells = <0>;
513 interrupt-controller;
514 reg = <0x0 0x12301000 0x1000>,
515 <0x0 0x12302000 0x1000>,
516 <0x0 0x12304000 0x2000>,
517 <0x0 0x12306000 0x2000>;
518 interrupts = <1 9 0xf04>;
519 };
520
521 timer {
522 compatible = "arm,armv8-timer";
523 interrupts = <GIC_PPI 13
524 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
525 <GIC_PPI 14
526 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
527 <GIC_PPI 11
528 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
529 <GIC_PPI 10
530 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
531 clock-frequency = <26000000>;
532 use-clocksource-only;
533 use-physical-timer;
534 };
535
536 clock: clock-controller@0x12100000 {
537 compatible = "samsung,exynos9610-clock";
538 reg = <0x0 0x12100000 0x8000>;
539 #clock-cells = <1>;
540 acpm-ipc-channel = <0>;
541 };
542
543 mct@10040000 {
544 compatible = "samsung,exynos4210-mct";
545 reg = <0x0 0x10040000 0x800>;
546 interrupt-controller;
547 #interrupt-cells = <1>;
548 interrupt-parent = <&mct_map>;
549 interrupts = <0>, <1>, <2>, <3>,
550 <4>, <5>, <6>, <7>,
551 <8>, <9>, <10>, <11>;
552 clocks = <&clock OSCCLK>, <&clock GATE_MCT_QCH>;
553 clock-names = "fin_pll", "mct";
554 use-clockevent-only;
555
556 mct_map: mct-map {
557 #interrupt-cells = <1>;
558 #address-cells = <0>;
559 #size-cells = <0>;
560 interrupt-map = <0 &gic 0 234 0>,
561 <1 &gic 0 235 0>,
562 <2 &gic 0 236 0>,
563 <3 &gic 0 237 0>,
564 <4 &gic 0 238 0>,
565 <5 &gic 0 239 0>,
566 <6 &gic 0 240 0>,
567 <7 &gic 0 241 0>,
568 <8 &gic 0 242 0>,
569 <9 &gic 0 243 0>,
570 <10 &gic 0 244 0>,
571 <11 &gic 0 245 0>;
572 };
573 };
574
575 speedy@11a10000 {
576 compatible = "samsung,exynos-speedy";
577 reg = <0x0 0x11a10000 0x2000>;
578 interrupts = <0 37 0>;
579 pinctrl-names = "default";
580 pinctrl-0 = <&speedy_bus>;
581 status = "disabled";
582 };
583
584 acpm {
585 compatible = "samsung,exynos-acpm";
586 #address-cells = <2>;
587 #size-cells = <1>;
588 acpm-ipc-channel = <4>;
589 fvmap_offset = <0x6000>;
590 reg = <0x0 0x11820000 0x1000>; /* TIMER_APM */
591 reg-names = "timer_apm";
592 peritimer-cnt = <0xFFFF>;
593 };
594
595 acpm_ipc {
596 compatible = "samsung,exynos-acpm-ipc";
597 #address-cells = <2>;
598 #size-cells = <1>;
599 interrupts = <0 38 0>; /* AP2APM MAILBOX SPI NUM*/
600 reg = <0x0 0x11900000 0x1000>, /* AP2APM MAILBOX */
601 <0x0 0x2039000 0x15000>; /* APM SRAM */
602 initdata-base = <0x6F00>;
603 num-timestamps = <32>;
604 debug-log-level = <0>;
605 logging-period = <500>;
606 dump-base = <0x203C000>;
607 dump-size = <0x12000>; /* 72KB */
608 };
609
610 acpm_dvfs {
611 compatible = "samsung,exynos-acpm-dvfs";
612 acpm-ipc-channel = <5>;
613 };
614
615 ITMON@0 {
616 compatible = "samsung,exynos-itmon";
617 interrupts = <0 306 0>, /* TREX_D_CORE */
618 <0 320 0>, /* TREX_D_NRT */
619 <0 307 0>; /* TREX_P_CORE */
620 };
621
622 /* ALIVE */
623 pinctrl_0: pinctrl@11850000 {
624 compatible = "samsung,exynos9610-pinctrl";
625 reg = <0x0 0x11850000 0x1000>;
626 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
627 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
628 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
629 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
630 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
631 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
632
633 wakeup-interrupt-controller {
634 compatible = "samsung,exynos7-wakeup-eint";
635 };
636 };
637
638 /* CMGP */
639 pinctrl_1: pinctrl@11C20000{
640 compatible = "samsung,exynos9610-pinctrl";
641 reg = <0x0 0x11C20000 0x1000>;
642 interrupts = <0 142 0>, <0 143 0>, <0 144 0>, <0 145 0>,
643 <0 158 0>, <0 159 0>, <0 160 0>, <0 161 0>,
644 <0 170 0>, <0 171 0>, <0 172 0>,
645 <0 173 0>, <0 174 0>, <0 185 0>, <0 196 0>,
646 <0 197 0>, <0 226 0>, <0 227 0>, <0 228 0>,
647 <0 269 0>, <0 270 0>, <0 272 0>, <0 278 0>,
648 <0 318 0>, <0 319 0>;
649
650 wakeup-interrupt-controller {
651 compatible = "samsung,exynos7-wakeup-eint";
652 };
653 };
654
655 /* DISPAUD */
656 pinctrl_2: pinctrl@14A60000{
657 compatible = "samsung,exynos9610-pinctrl";
658 reg = <0x0 0x14A60000 0x1000>;
659 };
660
661 /* FSYS */
662 pinctrl_3: pinctrl@13490000 {
663 compatible = "samsung,exynos9610-pinctrl";
664 reg = <0x0 0x13490000 0x1000>;
665 interrupts = <0 150 0>;
666 };
667
668 /* TOP */
669 pinctrl_4: pinctrl@139B0000 {
670 compatible = "samsung,exynos9610-pinctrl";
671 reg = <0x0 0x139B0000 0x1000>;
672 interrupts = <0 266 0>;
673 };
674
675 /* SHUB */
676 pinctrl_5: pinctrl@11080000{
677 compatible = "samsung,exynos9610-pinctrl";
678 reg = <0x0 0x11080000 0x1000>;
679 interrupts = <0 116 0>;
680 };
681
682 /* USI_SHUB_0 */
683 usi_0_shub: usi@11013000 {
684 compatible = "samsung,exynos-usi-v2";
685 reg = <0x0 0x11013000 0x4>;
686 /* usi_v2_mode = "i2c" or "spi" or "uart" */
687 status = "disabled";
688 };
689
690 /* USI_SHUB_0_I2C */
691 usi_0_shub_i2c: usi@11013004 {
692 compatible = "samsung,exynos-usi-v2";
693 reg = <0x0 0x11013004 0x4>;
694 /* usi_v2_mode = "i2c" or "spi" or "uart" */
695 status = "disabled";
696 };
697
698 /* USI_0_CMGP */
699 usi_0_cmgp: usi@11C12000 {
700 compatible = "samsung,exynos-usi-v2";
701 reg = <0x0 0x11C12000 0x4>;
702 /* usi_v2_mode = "i2c" or "spi" or "uart" */
703 status = "disabled";
704 };
705
706 /* USI_0_CMGP_I2C */
707 usi_0_cmgp_i2c: usi@11C12004 {
708 compatible = "samsung,exynos-usi-v2";
709 reg = <0x0 0x11C12004 0x4>;
710 /* usi_v2_mode = "i2c" or "spi" or "uart" */
711 status = "disabled";
712 };
713
714 /* USI_1_CMGP */
715 usi_1_cmgp: usi@11C12010 {
716 compatible = "samsung,exynos-usi-v2";
717 reg = <0x0 0x11C12010 0x4>;
718 /* usi_v2_mode = "i2c" or "spi" or "uart" */
719 status = "disabled";
720 };
721
722 /* USI_1_CMGP_I2C */
723 usi_1_cmgp_i2c: usi@11C12014 {
724 compatible = "samsung,exynos-usi-v2";
725 reg = <0x0 0x11C12014 0x4>;
726 /* usi_v2_mode = "i2c" or "spi" or "uart" */
727 status = "disabled";
728 };
729
730 /* USI_2_CMGP */
731 usi_2_cmgp: usi@11C12020 {
732 compatible = "samsung,exynos-usi-v2";
733 reg = <0x0 0x11C12020 0x4>;
734 /* usi_v2_mode = "i2c" or "spi" or "uart" */
735 status = "disabled";
736 };
737
738 /* USI_2_CMGP_I2C */
739 usi_2_cmgp_i2c: usi@11C12024 {
740 compatible = "samsung,exynos-usi-v2";
741 reg = <0x0 0x11C12024 0x4>;
742 /* usi_v2_mode = "i2c" or "spi" or "uart" */
743 status = "disabled";
744 };
745
746 /* USI_3_CMGP */
747 usi_3_cmgp: usi@11C12030 {
748 compatible = "samsung,exynos-usi-v2";
749 reg = <0x0 0x11C12030 0x4>;
750 /* usi_v2_mode = "i2c" or "spi" or "uart" */
751 status = "disabled";
752 };
753
754 /* USI_3_CMGP_I2C */
755 usi_3_cmgp_i2c: usi@11C12034 {
756 compatible = "samsung,exynos-usi-v2";
757 reg = <0x0 0x11C12034 0x4>;
758 /* usi_v2_mode = "i2c" or "spi" or "uart" */
759 status = "disabled";
760 };
761
762 /* USI_4_CMGP */
763 usi_4_cmgp: usi@11C12040 {
764 compatible = "samsung,exynos-usi-v2";
765 reg = <0x0 0x11C12040 0x4>;
766 /* usi_v2_mode = "i2c" or "spi" or "uart" */
767 status = "disabled";
768 };
769
770 /* USI_4_CMGP_I2C */
771 usi_4_cmgp_i2c: usi@11C12044 {
772 compatible = "samsung,exynos-usi-v2";
773 reg = <0x0 0x11C12044 0x4>;
774 /* usi_v2_mode = "i2c" or "spi" or "uart" */
775 status = "disabled";
776 };
777
778 /* USI_PERI_UART */
779 usi_peri_uart: usi@10011010 {
780 compatible = "samsung,exynos-usi-v2";
781 reg = <0x0 0x10011010 0x4>;
782 /* usi_v2_mode = "i2c" or "spi" or "uart" */
783 status = "disabled";
784 };
785
786 /* USI_PERI_CAMI2C_0 */
787 usi_peri_cami2c_0: usi@10011020 {
788 compatible = "samsung,exynos-usi-v2";
789 reg = <0x0 0x10011020 0x4>;
790 /* usi_v2_mode = "i2c" or "spi" or "uart" */
791 status = "disabled";
792 };
793
794 /* USI_PERI_CAMI2C_1 */
795 usi_peri_cami2c_1: usi@10011024 {
796 compatible = "samsung,exynos-usi-v2";
797 reg = <0x0 0x10011024 0x4>;
798 /* usi_v2_mode = "i2c" or "spi" or "uart" */
799 status = "disabled";
800 };
801
802 /* USI_PERI_CAMI2C_2 */
803 usi_peri_cami2c_2: usi@10011028 {
804 compatible = "samsung,exynos-usi-v2";
805 reg = <0x0 0x10011028 0x4>;
806 /* usi_v2_mode = "i2c" or "spi" or "uart" */
807 status = "disabled";
808 };
809
810 /* USI_PERI_CAMI2C_3 */
811 usi_peri_cami2c_3: usi@1001102C {
812 compatible = "samsung,exynos-usi-v2";
813 reg = <0x0 0x1001102C 0x4>;
814 /* usi_v2_mode = "i2c" or "spi" or "uart" */
815 status = "disabled";
816 };
817
818 /* USI_PERI_SPI_0 */
819 usi_peri_spi_0: usi@10011030 {
820 compatible = "samsung,exynos-usi-v2";
821 reg = <0x0 0x10011030 0x4>;
822 /* usi_v2_mode = "i2c" or "spi" or "uart" */
823 status = "disabled";
824 };
825
826 /* USI_PERI_SPI_1 */
827 usi_peri_spi_1: usi@10011034 {
828 compatible = "samsung,exynos-usi-v2";
829 reg = <0x0 0x10011034 0x4>;
830 /* usi_v2_mode = "i2c" or "spi" or "uart" */
831 status = "disabled";
832 };
833
834 /* USI_PERI_USI_0 */
835 usi_peri_usi_0: usi@1001103C {
836 compatible = "samsung,exynos-usi-v2";
837 reg = <0x0 0x1001103C 0x4>;
838 /* usi_v2_mode = "i2c" or "spi" or "uart" */
839 status = "disabled";
840 };
841
842 /* USI_PERI_USI_0_I2C */
843 usi_peri_usi_0_i2c: usi@10011040 {
844 compatible = "samsung,exynos-usi-v2";
845 reg = <0x0 0x10011040 0x4>;
846 /* usi_v2_mode = "i2c" or "spi" or "uart" */
847 status = "disabled";
848 };
849
850 /* USI_PERI_SPI_2 */
851 usi_peri_spi_2: usi@10011038 {
852 compatible = "samsung,exynos-usi-v2";
853 reg = <0x0 0x10011038 0x4>;
854 /* usi_v2_mode = "i2c" or "spi" or "uart" */
855 status = "disabled";
856 };
857
858 /* USI_0_SHUB */
859 hsi2c_0: hsi2c@110C0000 {
860 compatible = "samsung,exynos5-hsi2c";
861 samsung,check-transdone-int;
862 default-clk = <200000000>;
863 reg = <0x0 0x110C0000 0x1000>;
864 interrupts = <0 112 0>;
865 #address-cells = <1>;
866 #size-cells = <0>;
867 pinctrl-names = "default";
868 pinctrl-0 = <&hsi2c0_bus>;
869 clocks = <&clock MUX_SHUB_USI00>, <&clock GATE_USI_SHUB00_QCH>;
870 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
871 samsung,scl-clk-stretching;
872 samsung,usi-i2c-v2;
873 gpio_scl= <&gph0 0 0x1>;
874 gpio_sda= <&gph0 1 0x1>;
875 status = "disabled";
876 };
877
878 /* USI_0_SHUB_I2C */
879 hsi2c_1: hsi2c@110D0000 {
880 compatible = "samsung,exynos5-hsi2c";
881 samsung,check-transdone-int;
882 default-clk = <200000000>;
883 reg = <0x0 0x110D0000 0x1000>;
884 interrupts = <0 117 0>;
885 #address-cells = <1>;
886 #size-cells = <0>;
887 pinctrl-names = "default";
888 pinctrl-0 = <&hsi2c1_bus>;
889 clocks = <&clock MUX_SHUB_I2C>, <&clock GATE_I2C_SHUB00_QCH>;
890 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
891 samsung,scl-clk-stretching;
892 samsung,usi-i2c-v2;
893 gpio_scl= <&gph0 2 0x1>;
894 gpio_sda= <&gph0 3 0x1>;
895 status = "disabled";
896 };
897
898 /* USI_0_CMGP */
899 hsi2c_2: hsi2c@11D00000 {
900 compatible = "samsung,exynos5-hsi2c";
901 samsung,check-transdone-int;
902 default-clk = <200000000>;
903 reg = <0x0 0x11D00000 0x1000>;
904 interrupts = <0 311 0>;
905 #address-cells = <1>;
906 #size-cells = <0>;
907 pinctrl-names = "default";
908 pinctrl-0 = <&hsi2c2_bus>;
909 clocks = <&clock CMGP00_USI>, <&clock GATE_USI_CMGP00_QCH>;
910 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
911 samsung,scl-clk-stretching;
912 samsung,usi-i2c-v2;
913 gpio_scl= <&gpm0 0 0x1>;
914 gpio_sda= <&gpm1 0 0x1>;
915 status = "disabled";
916 };
917
918 /* USI_0_CMGP_I2C */
919 hsi2c_3: hsi2c@11D10000 {
920 compatible = "samsung,exynos5-hsi2c";
921 samsung,check-transdone-int;
922 default-clk = <200000000>;
923 reg = <0x0 0x11D10000 0x1000>;
924 interrupts = <0 273 0>;
925 #address-cells = <1>;
926 #size-cells = <0>;
927 pinctrl-names = "default";
928 pinctrl-0 = <&hsi2c3_bus>;
929 clocks = <&clock CMGP_I2C>, <&clock GATE_I2C_CMGP00_QCH>;
930 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
931 samsung,scl-clk-stretching;
932 samsung,usi-i2c-v2;
933 gpio_scl= <&gpm2 0 0x1>;
934 gpio_sda= <&gpm3 0 0x1>;
935 status = "disabled";
936 };
937
938 /* USI_1_CMGP */
939 hsi2c_4: hsi2c@11D20000 {
940 compatible = "samsung,exynos5-hsi2c";
941 samsung,check-transdone-int;
942 default-clk = <200000000>;
943 reg = <0x0 0x11D20000 0x1000>;
944 interrupts = <0 312 0>;
945 #address-cells = <1>;
946 #size-cells = <0>;
947 pinctrl-names = "default";
948 pinctrl-0 = <&hsi2c4_bus>;
949 clocks = <&clock CMGP01_USI>, <&clock GATE_USI_CMGP01_QCH>;
950 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
951 samsung,scl-clk-stretching;
952 samsung,usi-i2c-v2;
953 gpio_scl= <&gpm4 0 0x1>;
954 gpio_sda= <&gpm5 0 0x1>;
955 status = "disabled";
956 };
957
958 /* USI_1_CMGP_I2C */
959 hsi2c_5: hsi2c@11D30000 {
960 compatible = "samsung,exynos5-hsi2c";
961 samsung,check-transdone-int;
962 default-clk = <200000000>;
963 reg = <0x0 0x11D30000 0x1000>;
964 interrupts = <0 274 0>;
965 #address-cells = <1>;
966 #size-cells = <0>;
967 pinctrl-names = "default";
968 pinctrl-0 = <&hsi2c5_bus>;
969 clocks = <&clock CMGP_I2C>, <&clock GATE_I2C_CMGP01_QCH>;
970 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
971 samsung,scl-clk-stretching;
972 samsung,usi-i2c-v2;
973 gpio_scl= <&gpm6 0 0x1>;
974 gpio_sda= <&gpm7 0 0x1>;
975 status = "disabled";
976 };
977
978 /* USI_2_CMGP */
979 hsi2c_6: hsi2c@11D40000 {
980 compatible = "samsung,exynos5-hsi2c";
981 samsung,check-transdone-int;
982 default-clk = <200000000>;
983 reg = <0x0 0x11D40000 0x1000>;
984 interrupts = <0 313 0>;
985 #address-cells = <1>;
986 #size-cells = <0>;
987 pinctrl-names = "default";
988 pinctrl-0 = <&hsi2c6_bus>;
989 clocks = <&clock CMGP02_USI>, <&clock GATE_USI_CMGP02_QCH>;
990 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
991 samsung,scl-clk-stretching;
992 samsung,usi-i2c-v2;
993 gpio_scl= <&gpm8 0 0x1>;
994 gpio_sda= <&gpm9 0 0x1>;
995 status = "disabled";
996 };
997
998 /* USI_2_CMGP_I2C */
999 hsi2c_7: hsi2c@11D50000 {
1000 compatible = "samsung,exynos5-hsi2c";
1001 samsung,check-transdone-int;
1002 default-clk = <200000000>;
1003 reg = <0x0 0x11D50000 0x1000>;
1004 interrupts = <0 275 0>;
1005 #address-cells = <1>;
1006 #size-cells = <0>;
1007 pinctrl-names = "default";
1008 pinctrl-0 = <&hsi2c7_bus>;
1009 clocks = <&clock CMGP_I2C>, <&clock GATE_I2C_CMGP02_QCH>;
1010 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
1011 samsung,scl-clk-stretching;
1012 samsung,usi-i2c-v2;
1013 gpio_scl= <&gpm10 0 0x1>;
1014 gpio_sda= <&gpm11 0 0x1>;
1015 status = "disabled";
1016 };
1017
1018 /* USI_3_CMGP */
1019 hsi2c_8: hsi2c@11D60000 {
1020 compatible = "samsung,exynos5-hsi2c";
1021 samsung,check-transdone-int;
1022 default-clk = <200000000>;
1023 reg = <0x0 0x11D60000 0x1000>;
1024 interrupts = <0 314 0>;
1025 #address-cells = <1>;
1026 #size-cells = <0>;
1027 pinctrl-names = "default";
1028 pinctrl-0 = <&hsi2c8_bus>;
1029 clocks = <&clock CMGP03_USI>, <&clock GATE_USI_CMGP03_QCH>;
1030 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
1031 samsung,scl-clk-stretching;
1032 samsung,usi-i2c-v2;
1033 gpio_scl= <&gpm12 0 0x1>;
1034 gpio_sda= <&gpm13 0 0x1>;
1035 status = "disabled";
1036 };
1037
1038 /* USI_3_CMGP_I2C */
1039 hsi2c_9: hsi2c@11D70000 {
1040 compatible = "samsung,exynos5-hsi2c";
1041 samsung,check-transdone-int;
1042 default-clk = <200000000>;
1043 reg = <0x0 0x11D70000 0x1000>;
1044 interrupts = <0 276 0>;
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1047 pinctrl-names = "default";
1048 pinctrl-0 = <&hsi2c9_bus>;
1049 clocks = <&clock CMGP_I2C>, <&clock GATE_I2C_CMGP03_QCH>;
1050 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
1051 samsung,scl-clk-stretching;
1052 samsung,usi-i2c-v2;
1053 gpio_scl= <&gpm14 0 0x1>;
1054 gpio_sda= <&gpm15 0 0x1>;
1055 status = "disabled";
1056 };
1057
1058 /* USI_4_CMGP */
1059 hsi2c_10: hsi2c@11D80000 {
1060 compatible = "samsung,exynos5-hsi2c";
1061 samsung,check-transdone-int;
1062 default-clk = <200000000>;
1063 reg = <0x0 0x11D80000 0x1000>;
1064 interrupts = <0 315 0>;
1065 #address-cells = <1>;
1066 #size-cells = <0>;
1067 pinctrl-names = "default";
1068 pinctrl-0 = <&hsi2c10_bus>;
1069 clocks = <&clock CMGP04_USI>, <&clock GATE_USI_CMGP04_QCH>;
1070 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
1071 samsung,scl-clk-stretching;
1072 samsung,usi-i2c-v2;
1073 gpio_scl= <&gpm16 0 0x1>;
1074 gpio_sda= <&gpm17 0 0x1>;
1075 status = "disabled";
1076 };
1077
1078 /* USI_4_CMGP_I2C */
1079 hsi2c_11: hsi2c@11D90000 {
1080 compatible = "samsung,exynos5-hsi2c";
1081 samsung,check-transdone-int;
1082 default-clk = <200000000>;
1083 reg = <0x0 0x11D90000 0x1000>;
1084 interrupts = <0 277 0>;
1085 #address-cells = <1>;
1086 #size-cells = <0>;
1087 pinctrl-names = "default";
1088 pinctrl-0 = <&hsi2c11_bus>;
1089 clocks = <&clock CMGP_I2C>, <&clock GATE_I2C_CMGP04_QCH>;
1090 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
1091 samsung,scl-clk-stretching;
1092 samsung,usi-i2c-v2;
1093 gpio_scl= <&gpm18 0 0x1>;
1094 gpio_sda= <&gpm19 0 0x1>;
1095 status = "disabled";
1096 };
1097
1098 /* USI_PERI_CAMI2C_0 */
1099 hsi2c_12: hsi2c@138A0000 {
1100 compatible = "samsung,exynos5-hsi2c";
1101 samsung,check-transdone-int;
1102 default-clk = <200000000>;
1103 reg = <0x0 0x138A0000 0x1000>;
1104 interrupts = <0 257 0>;
1105 #address-cells = <1>;
1106 #size-cells = <0>;
1107 pinctrl-names = "default";
1108 pinctrl-0 = <&hsi2c12_bus>;
1109 clocks = <&clock I2C>, <&clock GATE_CAMI2C_0_QCH>;
1110 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
1111 samsung,scl-clk-stretching;
1112 samsung,usi-i2c-v2;
1113 gpio_scl= <&gpc0 1 0x1>;
1114 gpio_sda= <&gpc0 0 0x1>;
1115 status = "disabled";
1116 };
1117
1118 /* USI_PERI_CAMI2C_1 */
1119 hsi2c_13: hsi2c@138B0000 {
1120 compatible = "samsung,exynos5-hsi2c";
1121 samsung,check-transdone-int;
1122 default-clk = <200000000>;
1123 reg = <0x0 0x138B0000 0x1000>;
1124 interrupts = <0 258 0>;
1125 #address-cells = <1>;
1126 #size-cells = <0>;
1127 pinctrl-names = "default";
1128 pinctrl-0 = <&hsi2c13_bus>;
1129 clocks = <&clock I2C>, <&clock GATE_CAMI2C_1_QCH>;
1130 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
1131 samsung,scl-clk-stretching;
1132 samsung,usi-i2c-v2;
1133 gpio_scl= <&gpc0 3 0x1>;
1134 gpio_sda= <&gpc0 2 0x1>;
1135 status = "disabled";
1136 };
1137
1138 /* USI_PERI_CAMI2C_2 */
1139 hsi2c_14: hsi2c@138C0000 {
1140 compatible = "samsung,exynos5-hsi2c";
1141 samsung,check-transdone-int;
1142 default-clk = <200000000>;
1143 reg = <0x0 0x138C0000 0x1000>;
1144 interrupts = <0 259 0>;
1145 #address-cells = <1>;
1146 #size-cells = <0>;
1147 pinctrl-names = "default";
1148 pinctrl-0 = <&hsi2c14_bus>;
1149 clocks = <&clock I2C>, <&clock GATE_CAMI2C_2_QCH>;
1150 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
1151 samsung,scl-clk-stretching;
1152 samsung,usi-i2c-v2;
1153 gpio_scl= <&gpc0 5 0x1>;
1154 gpio_sda= <&gpc0 4 0x1>;
1155 status = "disabled";
1156 };
1157
1158 /* USI_PERI_CAMI2C_3 */
1159 hsi2c_15: hsi2c@138D0000 {
1160 compatible = "samsung,exynos5-hsi2c";
1161 samsung,check-transdone-int;
1162 default-clk = <200000000>;
1163 reg = <0x0 0x138D0000 0x1000>;
1164 interrupts = <0 260 0>;
1165 #address-cells = <1>;
1166 #size-cells = <0>;
1167 pinctrl-names = "default";
1168 pinctrl-0 = <&hsi2c15_bus>;
1169 clocks = <&clock I2C>, <&clock GATE_CAMI2C_3_QCH>;
1170 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
1171 samsung,scl-clk-stretching;
1172 samsung,usi-i2c-v2;
1173 gpio_scl= <&gpc0 7 0x1>;
1174 gpio_sda= <&gpc0 6 0x1>;
1175 status = "disabled";
1176 };
1177
1178 /* USI_PERI_USI_0 */
1179 hsi2c_16: hsi2c@13920000 {
1180 compatible = "samsung,exynos5-hsi2c";
1181 samsung,check-transdone-int;
1182 default-clk = <200000000>;
1183 reg = <0x0 0x13920000 0x1000>;
1184 interrupts = <0 267 0>;
1185 #address-cells = <1>;
1186 #size-cells = <0>;
1187 pinctrl-names = "default";
1188 pinctrl-0 = <&hsi2c16_bus>;
1189 clocks = <&clock USI_USI>, <&clock GATE_USI00_USI_QCH>;
1190 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
1191 samsung,scl-clk-stretching;
1192 samsung,usi-i2c-v2;
1193 gpio_scl= <&gpc1 0 0x1>;
1194 gpio_sda= <&gpc1 1 0x1>;
1195 status = "disabled";
1196 };
1197
1198 /* USI_PERI_USI_0_I2C */
1199 hsi2c_17: hsi2c@13930000 {
1200 compatible = "samsung,exynos5-hsi2c";
1201 samsung,check-transdone-int;
1202 default-clk = <200000000>;
1203 reg = <0x0 0x13930000 0x1000>;
1204 interrupts = <0 268 0>;
1205 #address-cells = <1>;
1206 #size-cells = <0>;
1207 pinctrl-names = "default";
1208 pinctrl-0 = <&hsi2c17_bus>;
1209 clocks = <&clock USI_I2C>, <&clock GATE_USI00_I2C_QCH>;
1210 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
1211 samsung,scl-clk-stretching;
1212 samsung,usi-i2c-v2;
1213 gpio_scl= <&gpc1 2 0x1>;
1214 gpio_sda= <&gpc1 3 0x1>;
1215 status = "disabled";
1216 };
1217
1218 /* USI_0_SHUB */
1219 spi_0: spi@110C0000 {
1220 compatible = "samsung,exynos-spi";
1221 reg = <0x0 0x110C0000 0x100>;
1222 samsung,spi-fifosize = <64>;
1223 interrupts = <0 112 0>;
1224 swap-mode;
1225 #address-cells = <1>;
1226 #size-cells = <0>;
1227 clocks = <&clock GATE_USI_SHUB00_QCH>, <&clock MUX_SHUB_USI00>;
1228 clock-names = "gate_spi_clk", "ipclk_spi";
1229 pinctrl-names = "default";
1230 pinctrl-0 = <&spi0_bus>;
1231 status = "disabled";
1232 };
1233
1234 /* USI_0_CMGP */
1235 spi_1: spi@11D00000 {
1236 compatible = "samsung,exynos-spi";
1237 reg = <0x0 0x11D00000 0x100>;
1238 samsung,spi-fifosize = <64>;
1239 interrupts = <0 311 0>;
1240 swap-mode;
1241 #address-cells = <1>;
1242 #size-cells = <0>;
1243 clocks = <&clock GATE_USI_CMGP00_QCH>, <&clock CMGP00_USI>;
1244 clock-names = "gate_spi_clk", "ipclk_spi";
1245 pinctrl-names = "default";
1246 pinctrl-0 = <&spi1_bus>;
1247 status = "disabled";
1248 };
1249
1250 /* USI_1_CMGP */
1251 spi_2: spi@11D20000 {
1252 compatible = "samsung,exynos-spi";
1253 reg = <0x0 0x11D20000 0x100>;
1254 samsung,spi-fifosize = <64>;
1255 interrupts = <0 312 0>;
1256 swap-mode;
1257 #address-cells = <1>;
1258 #size-cells = <0>;
1259 clocks = <&clock GATE_USI_CMGP01_QCH>, <&clock CMGP01_USI>;
1260 clock-names = "gate_spi_clk", "ipclk_spi";
1261 pinctrl-names = "default";
1262 pinctrl-0 = <&spi2_bus>;
1263 status = "disabled";
1264 };
1265
1266 /* USI_2_CMGP */
1267 spi_3: spi@11D40000 {
1268 compatible = "samsung,exynos-spi";
1269 reg = <0x0 0x11D40000 0x100>;
1270 samsung,spi-fifosize = <64>;
1271 interrupts = <0 313 0>;
1272 swap-mode;
1273 #address-cells = <1>;
1274 #size-cells = <0>;
1275 clocks = <&clock GATE_USI_CMGP02_QCH>, <&clock CMGP02_USI>;
1276 clock-names = "gate_spi_clk", "ipclk_spi";
1277 pinctrl-names = "default";
1278 pinctrl-0 = <&spi3_bus>;
1279 status = "disabled";
1280 };
1281
1282 /* USI_3_CMGP */
1283 spi_4: spi@11D60000 {
1284 compatible = "samsung,exynos-spi";
1285 reg = <0x0 0x11D60000 0x100>;
1286 samsung,spi-fifosize = <64>;
1287 interrupts = <0 314 0>;
1288 swap-mode;
1289 #address-cells = <1>;
1290 #size-cells = <0>;
1291 clocks = <&clock GATE_USI_CMGP03_QCH>, <&clock CMGP03_USI>;
1292 clock-names = "gate_spi_clk", "ipclk_spi";
1293 pinctrl-names = "default";
1294 pinctrl-0 = <&spi4_bus>;
1295 status = "disabled";
1296 };
1297
1298 /* USI_4_CMGP */
1299 spi_5: spi@11D80000 {
1300 compatible = "samsung,exynos-spi";
1301 reg = <0x0 0x11D80000 0x100>;
1302 samsung,spi-fifosize = <64>;
1303 interrupts = <0 315 0>;
1304 swap-mode;
1305 #address-cells = <1>;
1306 #size-cells = <0>;
1307 clocks = <&clock GATE_USI_CMGP04_QCH>, <&clock CMGP04_USI>;
1308 clock-names = "gate_spi_clk", "ipclk_spi";
1309 pinctrl-names = "default";
1310 pinctrl-0 = <&spi5_bus>;
1311 status = "disabled";
1312 };
1313
1314 /* USI_PERI_SPI_0 */
1315 spi_6: spi@13900000 {
1316 compatible = "samsung,exynos-spi";
1317 reg = <0x0 0x13900000 0x100>;
1318 samsung,spi-fifosize = <64>;
1319 interrupts = <0 254 0>;
1320 /*
1321 dma-mode;
1322 dmas = <&pdma0 19 &pdma0 18>;
1323 */
1324 dma-names = "tx", "rx";
1325 swap-mode;
1326 #address-cells = <1>;
1327 #size-cells = <0>;
1328 clocks = <&clock GATE_SPI_0_QCH>, <&clock SPI0>;
1329 clock-names = "gate_spi_clk", "ipclk_spi";
1330 pinctrl-names = "default";
1331 pinctrl-0 = <&spi6_bus>;
1332 status = "disabled";
1333 };
1334
1335 /* USI_PERI_SPI_1 */
1336 spi_7: spi@13910000 {
1337 compatible = "samsung,exynos-spi";
1338 reg = <0x0 0x13910000 0x100>;
1339 samsung,spi-fifosize = <64>;
1340 interrupts = <0 255 0>;
1341 /*
1342 dma-mode;
1343 dmas = <&pdma0 21 &pdma0 20>;
1344 */
1345 dma-names = "tx", "rx";
1346 swap-mode;
1347 #address-cells = <1>;
1348 #size-cells = <0>;
1349 clocks = <&clock GATE_SPI_1_QCH>, <&clock SPI1>;
1350 clock-names = "gate_spi_clk", "ipclk_spi";
1351 pinctrl-names = "default";
1352 pinctrl-0 = <&spi7_bus>;
1353 status = "disabled";
1354 };
1355
1356 /* USI_PERI_USI_0 */
1357 spi_8: spi@13920000 {
1358 compatible = "samsung,exynos-spi";
1359 reg = <0x0 0x13920000 0x100>;
1360 samsung,spi-fifosize = <64>;
1361 interrupts = <0 267 0>;
1362 /*
1363 dma-mode;
1364 dmas = <&pdma0 25 &pdma0 24>;
1365 */
1366 dma-names = "tx", "rx";
1367 swap-mode;
1368 #address-cells = <1>;
1369 #size-cells = <0>;
1370 clocks = <&clock GATE_USI00_USI_QCH>, <&clock USI_USI>;
1371 clock-names = "gate_spi_clk", "ipclk_spi";
1372 pinctrl-names = "default";
1373 pinctrl-0 = <&spi8_bus>;
1374 status = "disabled";
1375 };
1376
1377 /* SPI USI_PERI_SPI_2 */
1378 spi_9: spi@13940000 {
1379 compatible = "samsung,exynos-spi";
1380 reg = <0x0 0x13940000 0x100>;
1381 samsung,spi-fifosize = <256>;
1382 interrupts = <0 256 0>;
1383 /*
1384 dma-mode;
1385 dmas = <&pdma0 23 &pdma0 22>;
1386 */
1387 dma-names = "tx", "rx";
1388 swap-mode;
1389 #address-cells = <1>;
1390 #size-cells = <0>;
1391 clocks = <&clock GATE_SPI_2_QCH>, <&clock SPI2>;
1392 clock-names = "gate_spi_clk", "ipclk_spi";
1393 pinctrl-names = "default";
1394 pinctrl-0 = <&spi9_bus>;
1395 status = "disabled";
1396 };
1397
1398 /* USI_PERI_UART */
1399 serial_0: uart@13820000 {
1400 compatible = "samsung,exynos-uart";
1401 samsung,separate-uart-clk;
1402 reg = <0x0 0x13820000 0x100>;
1403 samsung,fifo-size = <256>;
1404 interrupts = <0 246 0>;
1405 pinctrl-names = "default";
1406 pinctrl-0 = <&uart0_bus>; /* or _bus_dual */
1407 samsung,usi-serial-v2;
1408 clocks = <&clock GATE_UART_QCH>, <&clock UART>;
1409 clock-names = "gate_uart_clk0", "ipclk_uart0";
1410 status = "disabled";
1411 };
1412
1413 /* USI_0_SHUB */
1414 serial_1: uart@110C0000 {
1415 compatible = "samsung,exynos-uart";
1416 samsung,separate-uart-clk;
1417 reg = <0x0 0x110C0000 0x100>;
1418 samsung,fifo-size = <64>;
1419 interrupts = <0 112 0>;
1420 pinctrl-names = "default";
1421 pinctrl-0 = <&uart1_bus_single>; /* or _bus_dual */
1422 samsung,usi-serial-v2;
1423 clocks = <&clock GATE_USI_SHUB00_QCH>, <&clock MUX_SHUB_USI00>;
1424 clock-names = "gate_uart_clk1", "ipclk_uart1";
1425 status = "disabled";
1426 };
1427
1428 /* USI_0_CMGP */
1429 serial_2: uart@11D00000 {
1430 compatible = "samsung,exynos-uart";
1431 samsung,separate-uart-clk;
1432 reg = <0x0 0x11D00000 0x100>;
1433 samsung,fifo-size = <64>;
1434 interrupts = <0 311 0>;
1435 pinctrl-names = "default";
1436 pinctrl-0 = <&uart2_bus_single>; /* or _bus_dual */
1437 samsung,usi-serial-v2;
1438 clocks = <&clock GATE_USI_CMGP00_QCH>, <&clock CMGP00_USI>;
1439 clock-names = "gate_uart_clk2", "ipclk_uart2";
1440 status = "disabled";
1441 };
1442
1443 /* USI_1_CMGP */
1444 serial_3: uart@11D20000 {
1445 compatible = "samsung,exynos-uart";
1446 samsung,separate-uart-clk;
1447 reg = <0x0 0x11D20000 0x100>;
1448 samsung,fifo-size = <64>;
1449 interrupts = <0 312 0>;
1450 pinctrl-names = "default";
1451 pinctrl-0 = <&uart3_bus_single>; /* or _bus_dual */
1452 samsung,usi-serial-v2;
1453 clocks = <&clock GATE_USI_CMGP01_QCH>, <&clock CMGP01_USI>;
1454 clock-names = "gate_uart_clk3", "ipclk_uart3";
1455 status = "disabled";
1456 };
1457
1458 /* USI_2_CMGP */
1459 serial_4: uart@11D40000 {
1460 compatible = "samsung,exynos-uart";
1461 samsung,separate-uart-clk;
1462 reg = <0x0 0x11D40000 0x100>;
1463 samsung,fifo-size = <64>;
1464 interrupts = <0 313 0>;
1465 pinctrl-names = "default";
1466 pinctrl-0 = <&uart4_bus_single>; /* or _bus_dual */
1467 samsung,usi-serial-v2;
1468 clocks = <&clock GATE_USI_CMGP02_QCH>, <&clock CMGP02_USI>;
1469 clock-names = "gate_uart_clk4", "ipclk_uart4";
1470 status = "disabled";
1471 };
1472
1473 /* USI_3_CMGP */
1474 serial_5: uart@11D60000 {
1475 compatible = "samsung,exynos-uart";
1476 samsung,separate-uart-clk;
1477 reg = <0x0 0x11D60000 0x100>;
1478 samsung,fifo-size = <64>;
1479 interrupts = <0 314 0>;
1480 pinctrl-names = "default";
1481 pinctrl-0 = <&uart5_bus_single>; /* or _bus_dual */
1482 samsung,usi-serial-v2;
1483 clocks = <&clock GATE_USI_CMGP03_QCH>, <&clock CMGP03_USI>;
1484 clock-names = "gate_uart_clk5", "ipclk_uart5";
1485 status = "disabled";
1486 };
1487
1488 /* USI_4_CMGP */
1489 serial_6: uart@11D80000 {
1490 compatible = "samsung,exynos-uart";
1491 samsung,separate-uart-clk;
1492 reg = <0x0 0x11D80000 0x100>;
1493 samsung,fifo-size = <64>;
1494 interrupts = <0 315 0>;
1495 pinctrl-names = "default";
1496 pinctrl-0 = <&uart6_bus_single>; /* or _bus_dual */
1497 samsung,usi-serial-v2;
1498 clocks = <&clock GATE_USI_CMGP04_QCH>, <&clock CMGP04_USI>;
1499 clock-names = "gate_uart_clk6", "ipclk_uart6";
1500 status = "disabled";
1501 };
1502
1503 /* USI_PERI_USI_0 */
1504 serial_7: uart@13920000 {
1505 compatible = "samsung,exynos-uart";
1506 samsung,separate-uart-clk;
1507 reg = <0x0 0x13920000 0x100>;
1508 samsung,fifo-size = <64>;
1509 interrupts = <0 267 0>;
1510 pinctrl-names = "default";
1511 pinctrl-0 = <&uart7_bus_single>; /* or _bus_dual */
1512 samsung,usi-serial-v2;
1513 clocks = <&clock GATE_USI00_USI_QCH>, <&clock USI_USI>;
1514 clock-names = "gate_uart_clk7", "ipclk_uart7";
1515 status = "disabled";
1516 };
1517
1518 /* I2C_0 */
1519 i2c_0: i2c@13830000 {
1520 compatible = "samsung,s3c2440-i2c";
1521 reg = <0x0 0x13830000 0x100>;
1522 interrupts = <0 247 0>;
1523 #address-cells = <1>;
1524 #size-cells = <0>;
1525 pinctrl-names = "default";
1526 pinctrl-0 = <&i2c0_bus>;
1527 clocks = <&clock GATE_I2C_0_QCH>, <&clock GATE_I2C_0_QCH>;
1528 clock-names = "rate_i2c", "gate_i2c";
1529 status = "disabled";
1530 };
1531
1532 /* I2C_1 */
1533 i2c_1: i2c@13840000 {
1534 compatible = "samsung,s3c2440-i2c";
1535 reg = <0x0 0x13840000 0x100>;
1536 interrupts = <0 248 0>;
1537 #address-cells = <1>;
1538 #size-cells = <0>;
1539 pinctrl-names = "default";
1540 pinctrl-0 = <&i2c1_bus>;
1541 clocks = <&clock GATE_I2C_1_QCH>, <&clock GATE_I2C_1_QCH>;
1542 clock-names = "rate_i2c", "gate_i2c";
1543 status = "disabled";
1544 };
1545
1546 /* I2C_2 */
1547 i2c_2: i2c@13850000 {
1548 compatible = "samsung,s3c2440-i2c";
1549 reg = <0x0 0x13850000 0x100>;
1550 interrupts = <0 249 0>;
1551 #address-cells = <1>;
1552 #size-cells = <0>;
1553 pinctrl-names = "default";
1554 pinctrl-0 = <&i2c2_bus>;
1555 clocks = <&clock GATE_I2C_2_QCH>, <&clock GATE_I2C_2_QCH>;
1556 clock-names = "rate_i2c", "gate_i2c";
1557 status = "disabled";
1558 };
1559
1560 /* I2C_3 */
1561 i2c_3: i2c@13860000 {
1562 compatible = "samsung,s3c2440-i2c";
1563 reg = <0x0 0x13860000 0x100>;
1564 interrupts = <0 250 0>;
1565 #address-cells = <1>;
1566 #size-cells = <0>;
1567 pinctrl-names = "default";
1568 pinctrl-0 = <&i2c3_bus>;
1569 clocks = <&clock GATE_I2C_3_QCH>, <&clock GATE_I2C_3_QCH>;
1570 clock-names = "rate_i2c", "gate_i2c";
1571 status = "disabled";
1572 };
1573
1574 /* I2C_4 */
1575 i2c_4: i2c@13870000 {
1576 compatible = "samsung,s3c2440-i2c";
1577 reg = <0x0 0x13870000 0x100>;
1578 interrupts = <0 251 0>;
1579 #address-cells = <1>;
1580 #size-cells = <0>;
1581 pinctrl-names = "default";
1582 pinctrl-0 = <&i2c4_bus>;
1583 clocks = <&clock GATE_I2C_4_QCH>, <&clock GATE_I2C_4_QCH>;
1584 clock-names = "rate_i2c", "gate_i2c";
1585 status = "disabled";
1586 };
1587
1588 /* I2C_5 */
1589 i2c_5: i2c@13880000 {
1590 compatible = "samsung,s3c2440-i2c";
1591 reg = <0x0 0x13880000 0x100>;
1592 interrupts = <0 252 0>;
1593 #address-cells = <1>;
1594 #size-cells = <0>;
1595 pinctrl-names = "default";
1596 pinctrl-0 = <&i2c5_bus>;
1597 clocks = <&clock GATE_I2C_5_QCH>, <&clock GATE_I2C_5_QCH>;
1598 clock-names = "rate_i2c", "gate_i2c";
1599 status = "disabled";
1600 };
1601
1602 /* I2C_6 */
1603 i2c_6: i2c@13890000 {
1604 compatible = "samsung,s3c2440-i2c";
1605 reg = <0x0 0x13890000 0x100>;
1606 interrupts = <0 253 0>;
1607 #address-cells = <1>;
1608 #size-cells = <0>;
1609 pinctrl-names = "default";
1610 pinctrl-0 = <&i2c6_bus>;
1611 clocks = <&clock GATE_I2C_6_QCH>, <&clock GATE_I2C_6_QCH>;
1612 clock-names = "rate_i2c", "gate_i2c";
1613 status = "disabled";
1614 };
1615
1616 exynos_dm: exynos-dm@17000000 {
1617 compatible = "samsung,exynos-dvfs-manager";
1618 reg = <0x0 0x17000000 0x0>;
1619 acpm-ipc-channel = <1>;
1620 dm_domains {
1621 cpufreq_cl0 {
1622 dm-index = <DM_CPU_CL0>;
1623 available = "true";
1624 cal_id = <ACPM_DVFS_CPUCL0>;
1625 dm_type_name = "dm_cpu_cl0";
1626 };
1627 cpufreq_cl1 {
1628 dm-index = <DM_CPU_CL1>;
1629 available = "true";
1630 cal_id = <ACPM_DVFS_CPUCL1>;
1631 dm_type_name = "dm_cpu_cl1";
1632 };
1633 devfreq_mif {
1634 dm-index = <DM_MIF>;
1635 available = "true";
1636 policy_use = "true";
1637 cal_id = <ACPM_DVFS_MIF>;
1638 dm_type_name = "dm_mif";
1639 };
1640 devfreq_int {
1641 dm-index = <DM_INT>;
1642 available = "true";
1643 policy_use = "true";
1644 cal_id = <ACPM_DVFS_INT>;
1645 dm_type_name = "dm_int";
1646 };
1647 devfreq_intcam {
1648 dm-index = <DM_INTCAM>;
1649 available = "true";
1650 cal_id = <ACPM_DVFS_INTCAM>;
1651 dm_type_name = "dm_intcam";
1652 };
1653 devfreq_cam {
1654 dm-index = <DM_CAM>;
1655 available = "true";
1656 cal_id = <ACPM_DVFS_CAM>;
1657 dm_type_name = "dm_cam";
1658 };
1659 devfreq_disp {
1660 dm-index = <DM_DISP>;
1661 available = "true";
1662 cal_id = <ACPM_DVFS_DISP>;
1663 dm_type_name = "dm_disp";
1664 };
1665 devfreq_aud {
1666 dm-index = <DM_AUD>;
1667 available = "true";
1668 cal_id = <ACPM_DVFS_AUD>;
1669 dm_type_name = "dm_aud";
1670 };
1671 dvfs_gpu {
1672 dm-index = <DM_GPU>;
1673 available = "false";
1674 cal_id = <ACPM_DVFS_G3D>;
1675 dm_type_name = "dm_gpu";
1676 };
1677 };
1678 };
1679
1680 exynos_devfreq {
1681 compatible = "samsung,exynos-devfreq-root";
1682 #address-cells = <2>;
1683 #size-cells = <1>;
1684 ranges;
1685 devfreq_0: devfreq_mif@17000010 {
1686 compatible = "samsung,exynos-devfreq";
1687 reg = <0x0 0x17000010 0x0>;
1688 devfreq_type = <DEVFREQ_MIF>;
1689 devfreq_domain_name = "dvfs_mif";
1690 pm_qos_class = <13>; /* PM_QOS_BUS_THROUGHPUT */
1691 pm_qos_class_max = <14>; /* PM_QOS_BUS_THROUGHPUT_MAX */
1692 ess_flag = <ESS_FLAG_MIF>;
1693 dm-index = <DM_MIF>;
1694
1695 /* Delay time */
1696 use_delay_time = "true";
1697 delay_time_list = "20";
1698
1699 freq_info = <2093000 546000 419000 419000 2093000 419000>;
1700 /* initial_freq, default_qos, suspend_freq, min_freq, max_freq reboot_freq */
1701
1702 /* Booting value */
1703 boot_info = <40 2093000>;
1704 /* boot_qos_timeout, boot_freq */
1705
1706 /* governor data */
1707 governor = <SIMPLE_INTERACTIVE>;
1708
1709 bts_update = "false";
1710 dfs_id = <ACPM_DVFS_MIF>;
1711 acpm-ipc-channel = <1>;
1712 use_acpm = "true";
1713 update_fvp = "true";
1714 };
1715
1716 devfreq_1: devfreq_int@17000020 {
1717 compatible = "samsung,exynos-devfreq";
1718 reg = <0x0 0x17000020 0x0>;
1719 devfreq_type = <DEVFREQ_INT>;
1720 devfreq_domain_name = "dvfs_int";
1721 pm_qos_class = <9>; /* PM_QOS_DEVICE_THROUGHPUT */
1722 pm_qos_class_max = <11>; /* PM_QOS_DEVICE_THROUGHPUT_MAX */
1723 ess_flag = <ESS_FLAG_INT>;
1724 dm-index = <DM_INT>;
1725
1726 /* Delay time */
1727 use_delay_time = "false";
1728
1729 freq_info = <667000 100000 667000 100000 667000 100000>;
1730 /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
1731
1732 /* Booting value */
1733 boot_info = <40 667000>;
1734 /* boot_qos_timeout, boot_freq */
1735
1736 /* governor data */
1737 governor = <SIMPLE_INTERACTIVE>;
1738
1739 bts_update = "false";
1740 dfs_id = <ACPM_DVFS_INT>;
1741 acpm-ipc-channel = <1>;
1742 use_acpm = "true";
1743 skew {
1744 skew_0 {
1745 constraint_dm_type = <DM_MIF>;
1746 constraint_type = <CONSTRAINT_MIN>;
1747 };
1748 };
1749 };
1750
1751 devfreq_2: devfreq_intcam@17000030 {
1752 compatible = "samsung,exynos-devfreq";
1753 reg = <0x0 0x17000030 0x0>;
1754 devfreq_type = <DEVFREQ_INTCAM>;
1755 devfreq_domain_name = "dvfs_intcam";
1756 pm_qos_class = <10>; /* PM_QOS_INTCAM_THROUGHPUT */
1757 pm_qos_class_max = <12>; /* PM_QOS_INTCAM_THROUGHPUT_MAX */
1758 ess_flag = <ESS_FLAG_INTCAM>;
1759 dm-index = <DM_INTCAM>;
1760
1761 /* Delay time */
1762 use_delay_time = "false";
1763
1764 freq_info = <690000 650000 690000 650000 690000 650000>;
1765 /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
1766
1767 /* Booting value */
1768 boot_info = <40 640000>;
1769 /* boot_qos_timeout, boot_freq */
1770
1771 /* governor data */
1772 governor = <SIMPLE_INTERACTIVE>;
1773
1774 bts_update = "false";
1775 dfs_id = <ACPM_DVFS_INTCAM>;
1776 };
1777
1778 devfreq_3: devfreq_disp@17000040 {
1779 compatible = "samsung,exynos-devfreq";
1780 reg = <0x0 0x17000040 0x0>;
1781 devfreq_type = <DEVFREQ_DISP>;
1782 devfreq_domain_name = "dvfs_disp";
1783 pm_qos_class = <17>; /* PM_QOS_DISPLAY_THROUGHPUT */
1784 pm_qos_class_max = <18>; /* PM_QOS_DISPLAY_THROUGHPUT_MAX */
1785 ess_flag = <ESS_FLAG_DISP>;
1786 dm-index = <DM_DISP>;
1787
1788 /* Delay time */
1789 use_delay_time = "false";
1790
1791 freq_info = <533000 167000 533000 167000 533000 533000>;
1792 /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
1793
1794 /* Booting value */
1795 boot_info = <40 533000>;
1796 /* boot_qos_timeout, boot_freq */
1797
1798 /* governor data */
1799 governor = <SIMPLE_INTERACTIVE>;
1800
1801 bts_update = "false";
1802 dfs_id = <ACPM_DVFS_DISP>;
1803 };
1804
1805 devfreq_4: devfreq_cam@17000050 {
1806 compatible = "samsung,exynos-devfreq";
1807 reg = <0x0 0x17000050 0x0>;
1808 devfreq_type = <DEVFREQ_CAM>;
1809 devfreq_domain_name = "dvfs_cam";
1810 pm_qos_class = <19>; /* PM_QOS_CAM_THROUGHPUT */
1811 pm_qos_class_max = <21>; /* PM_QOS_CAM_THROUGHPUT_MAX */
1812 ess_flag = <ESS_FLAG_ISP>;
1813 dm-index = <DM_CAM>;
1814
1815 /* Delay time */
1816 use_delay_time = "false";
1817
1818 freq_info = <690000 640000 690000 640000 700000 640000>;
1819 /* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
1820
1821 /* Booting value */
1822 boot_info = <40 690000>;
1823 /* boot_qos_timeout, boot_freq */
1824
1825 /* governor data */
1826 governor = <SIMPLE_INTERACTIVE>;
1827
1828 bts_update = "false";
1829
1830 dfs_id = <ACPM_DVFS_CAM>;
1831 };
1832
1833 devfreq_5: devfreq_aud@17000060 {
1834 compatible = "samsung,exynos-devfreq";
1835 reg = <0x0 0x17000060 0x0>;
1836 devfreq_type = <DEVFREQ_AUD>;
1837 devfreq_domain_name = "dvfs_aud";
1838 pm_qos_class = <20>; /* PM_QOS_AUD_THROUGHPUT */
1839 pm_qos_class_max = <22>; /* PM_QOS_AUD_THROUGHPUT_MAX */
1840 ess_flag = <ESS_FLAG_AUD>;
1841 dm-index = <DM_AUD>;
1842
1843 /* Delay time */
1844 use_delay_time = "false";
1845
1846 freq_info = <393000 393000 393000 393000 1180000 393000>;
1847 /* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
1848
1849 /* Booting value */
1850 boot_info = <40 393000>;
1851 /* boot_qos_timeout, boot_freq */
1852
1853 /* governor data */
1854 governor = <SIMPLE_INTERACTIVE>;
1855
1856 bts_update = "false";
1857 dfs_id = <ACPM_DVFS_AUD>;
1858
1859 samsung,power-domain = <&pd_dispaud>;
1860 pd_name = "pd-dispaud";
1861 };
1862 };
1863
1864 tmuctrl_0: BIG@10070000 {
1865 compatible = "samsung,exynos9610-tmu";
1866 reg = <0x0 0x10070000 0x700>;
1867 interrupts = <0 231 0>;
1868 tmu_name = "BIG";
1869 id = <0>;
1870 sensors = <4>; /* P2 */
1871 sensing_mode = "max";
1872 hotplug_enable = <1>;
1873 hotplug_in_threshold = <91>;
1874 hotplug_out_threshold = <96>;
1875 #include "exynos9610-tmu-sensor-conf.dtsi"
1876 };
1877
1878 tmuctrl_1: LITTLE@10070000 {
1879 compatible = "samsung,exynos9610-tmu";
1880 reg = <0x0 0x10070000 0x700>;
1881 interrupts = <0 231 0>;
1882 tmu_name = "LITTLE";
1883 id = <1>;
1884 sensors = <2>; /* P1 */
1885 sensing_mode = "max";
1886 #include "exynos9610-tmu-sensor-conf.dtsi"
1887 };
1888
1889 tmuctrl_2: G3D@10070000 {
1890 compatible = "samsung,exynos9610-tmu";
1891 reg = <0x0 0x10070000 0x700>;
1892 interrupts = <0 231 0>;
1893 tmu_name = "G3D";
1894 id = <2>;
1895 sensors = <1>; /* P0 */
1896 sensing_mode = "max";
1897 #include "exynos9610-tmu-sensor-conf.dtsi"
1898 };
1899
1900 tmuctrl_3: ISP@10070000 {
1901 compatible = "samsung,exynos9610-tmu";
1902 reg = <0x0 0x10070000 0x700>;
1903 interrupts = <0 231 0>;
1904 tmu_name = "ISP";
1905 id = <3>;
1906 sensors = <2>; /* P1 */
1907 sensing_mode = "max";
1908 #include "exynos9610-tmu-sensor-conf.dtsi"
1909 };
1910
1911 acpm_tmu {
1912 acpm-ipc-channel = <7>;
1913 };
1914
1915 thermal-zones {
1916 big_thermal: BIG {
1917 zone_name = "BIG_THERMAL";
1918 polling-delay-passive = <50>;
1919 polling-delay = <1000>;
1920 thermal-sensors = <&tmuctrl_0>;
1921 governor = "power_allocator";
1922 sustainable-power = <0>;
1923 k_po = <0>;
1924 k_pu = <0>;
1925 k_i = <0>;
1926 i_max = <0>;
1927 integral_cutoff = <0>;
1928
1929 trips {
1930 big_cold: big-cold {
1931 temperature = <20000>;
1932 hysteresis = <5000>; /* millicelsius */
1933 type = "active";
1934 };
1935 big_switch_on: big-switch-on {
1936 temperature = <63000>; /* millicelsius */
1937 hysteresis = <2000>; /* millicelsius */
1938 type = "active";
1939 };
1940 big_control_temp: big-control-temp {
1941 temperature = <83000>; /* millicelsius */
1942 hysteresis = <5000>; /* millicelsius */
1943 type = "passive";
1944 };
1945 big_alert0: big-alert0 {
1946 temperature = <95000>; /* millicelsius */
1947 hysteresis = <5000>; /* millicelsius */
1948 type = "active";
1949 };
1950 big_alert1: big-alert1 {
1951 temperature = <100000>; /* millicelsius */
1952 hysteresis = <5000>; /* millicelsius */
1953 type = "active";
1954 };
1955 big_alert2: big-alert2 {
1956 temperature = <105000>; /* millicelsius */
1957 hysteresis = <5000>; /* millicelsius */
1958 type = "active";
1959 };
1960 big_alert3: big-alert3 {
1961 temperature = <110000>; /* millicelsius */
1962 hysteresis = <5000>; /* millicelsius */
1963 type = "active";
1964 };
1965 big_hot: big-hot {
1966 temperature = <115000>; /* millicelsius */
1967 hysteresis = <5000>; /* millicelsius */
1968 type = "hot";
1969 };
1970 };
1971
1972 cooling-maps {
1973 map0 {
1974 trip = <&big_control_temp>;
1975 cooling-device = <&cpufreq_domain1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1976 };
1977 };
1978 };
1979
1980 little_thermal: LITTLE {
1981 zone_name = "LITTLE_THERMAL";
1982 polling-delay-passive = <0>;
1983 polling-delay = <0>;
1984 thermal-sensors = <&tmuctrl_1>;
1985
1986 trips {
1987 little_alert0: little-alert0 {
1988 temperature = <20000>; /* millicelsius */
1989 hysteresis = <5000>; /* millicelsius */
1990 type = "active";
1991 };
1992 little_alert1: little-alert1 {
1993 temperature = <76000>; /* millicelsius */
1994 hysteresis = <5000>; /* millicelsius */
1995 type = "active";
1996 };
1997 little_alert2: little-alert2 {
1998 temperature = <81000>; /* millicelsius */
1999 hysteresis = <5000>; /* millicelsius */
2000 type = "active";
2001 };
2002 little_alert3: little-alert3 {
2003 temperature = <91000>; /* millicelsius */
2004 hysteresis = <5000>; /* millicelsius */
2005 type = "active";
2006 };
2007 little_alert4: little-alert4 {
2008 temperature = <96000>; /* millicelsius */
2009 hysteresis = <5000>; /* millicelsius */
2010 type = "active";
2011 };
2012 little_alert5: little-alert5 {
2013 temperature = <101000>; /* millicelsius */
2014 hysteresis = <5000>; /* millicelsius */
2015 type = "active";
2016 };
2017 little_alert6: little-alert6 {
2018 temperature = <106000>; /* millicelsius */
2019 hysteresis = <5000>; /* millicelsius */
2020 type = "active";
2021 };
2022 little_hot: little-hot {
2023 temperature = <115000>; /* millicelsius */
2024 hysteresis = <5000>; /* millicelsius */
2025 type = "hot";
2026 };
2027 };
2028
2029 cooling-maps {
2030 map0 {
2031 trip = <&little_alert0>;
2032 /* Corresponds to 1534MHz at freq_table */
2033 cooling-device = <&cpufreq_domain0 0 0>;
2034 };
2035 map1 {
2036 trip = <&little_alert1>;
2037 /* Corresponds to 1326MHz at freq_table */
2038 cooling-device = <&cpufreq_domain0 0 0>;
2039 };
2040 map2 {
2041 trip = <&little_alert2>;
2042 /* Corresponds to 1118MHz at freq_table */
2043 cooling-device = <&cpufreq_domain0 0 0>;
2044 };
2045 map3 {
2046 trip = <&little_alert3>;
2047 /* Corresponds to 910MHz at freq_table */
2048 cooling-device = <&cpufreq_domain0 0 0>;
2049 };
2050 map4 {
2051 trip = <&little_alert4>;
2052 /* Corresponds to 702MHz at freq_table */
2053 cooling-device = <&cpufreq_domain0 0 0>;
2054 };
2055 map5 {
2056 trip = <&little_alert5>;
2057 /* Corresponds to 403MHz at freq_table */
2058 cooling-device = <&cpufreq_domain0 0 0>;
2059 };
2060 map6 {
2061 trip = <&little_alert6>;
2062 /* Corresponds to 403MHz at freq_table */
2063 cooling-device = <&cpufreq_domain0 0 0>;
2064 };
2065 map7 {
2066 trip = <&little_hot>;
2067 /* Corresponds to 403MHz at freq_table */
2068 cooling-device = <&cpufreq_domain0 0 0>;
2069 };
2070 };
2071 };
2072
2073 gpu_thermal: G3D {
2074 zone_name = "G3D_THERMAL";
2075 polling-delay-passive = <100>;
2076 polling-delay = <0>;
2077 thermal-sensors = <&tmuctrl_2>;
2078 governor = "power_allocator";
2079 sustainable-power = <0>;
2080 k_po = <0>;
2081 k_pu = <0>;
2082 k_i = <0>;
2083 i_max = <0>;
2084 integral_cutoff = <0>;
2085
2086 trips {
2087 gpu_cold: gpu-cold {
2088 temperature = <20000>;
2089 hysteresis = <5000>; /* millicelsius */
2090 type = "active";
2091 };
2092 gpu_switch_on: gpu-switch-on {
2093 temperature = <80000>; /* millicelsius */
2094 hysteresis = <2000>; /* millicelsius */
2095 type = "active";
2096 };
2097 gpu_control_temp: gpu-control-temp {
2098 temperature = <88000>; /* millicelsius */
2099 hysteresis = <5000>; /* millicelsius */
2100 type = "passive";
2101 };
2102 gpu_alert0: gpu-alert0 {
2103 temperature = <95000>; /* millicelsius */
2104 hysteresis = <5000>; /* millicelsius */
2105 type = "active";
2106 };
2107 gpu_alert1: gpu-alert1 {
2108 temperature = <100000>; /* millicelsius */
2109 hysteresis = <5000>; /* millicelsius */
2110 type = "active";
2111 };
2112 gpu_alert2: gpu-alert2 {
2113 temperature = <105000>; /* millicelsius */
2114 hysteresis = <5000>; /* millicelsius */
2115 type = "active";
2116 };
2117 gpu_alert3: gpu-alert3 {
2118 temperature = <110000>; /* millicelsius */
2119 hysteresis = <5000>; /* millicelsius */
2120 type = "active";
2121 };
2122 gpu_hot: gpu-hot {
2123 temperature = <115000>; /* millicelsius */
2124 hysteresis = <5000>; /* millicelsius */
2125 type = "hot";
2126 };
2127 };
2128
2129 cooling-maps {
2130 map0 {
2131 trip = <&gpu_control_temp>;
2132 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2133 };
2134 };
2135 };
2136
2137 isp_thermal: ISP {
2138 zone_name = "ISP_THERMAL";
2139 polling-delay-passive = <0>;
2140 polling-delay = <0>;
2141 thermal-sensors = <&tmuctrl_3>;
2142
2143 trips {
2144 isp_alert0: isp-alert0 {
2145 temperature = <20000>; /* millicelsius */
2146 hysteresis = <5000>; /* millicelsius */
2147 type = "active";
2148 };
2149 isp_alert1: isp-alert1 {
2150 temperature = <76000>; /* millicelsius */
2151 hysteresis = <5000>; /* millicelsius */
2152 type = "active";
2153 };
2154 isp_alert2: isp-alert2 {
2155 temperature = <81000>; /* millicelsius */
2156 hysteresis = <5000>; /* millicelsius */
2157 type = "active";
2158 };
2159 isp_alert3: isp-alert3 {
2160 temperature = <91000>; /* millicelsius */
2161 hysteresis = <5000>; /* millicelsius */
2162 type = "active";
2163 };
2164 isp_alert4: isp-alert4 {
2165 temperature = <96000>; /* millicelsius */
2166 hysteresis = <5000>; /* millicelsius */
2167 type = "active";
2168 };
2169 isp_alert5: isp-alert5 {
2170 temperature = <101000>; /* millicelsius */
2171 hysteresis = <5000>; /* millicelsius */
2172 type = "active";
2173 };
2174 isp_alert6: isp-alert6 {
2175 temperature = <106000>; /* millicelsius */
2176 hysteresis = <5000>; /* millicelsius */
2177 type = "active";
2178 };
2179 isp_hot: isp-hot {
2180 temperature = <115000>; /* millicelsius */
2181 hysteresis = <5000>; /* millicelsius */
2182 type = "hot";
2183 };
2184 };
2185
2186 cooling-maps {
2187 map0 {
2188 trip = <&isp_alert0>;
2189 /* Corresponds to No limit */
2190 cooling-device = <&fimc_is 0 0>;
2191 };
2192 map1 {
2193 trip = <&isp_alert1>;
2194 /* Corresponds to No limit */
2195 cooling-device = <&fimc_is 0 0>;
2196 };
2197 map2 {
2198 trip = <&isp_alert2>;
2199 /* Corresponds to 15fps at freq_table */
2200 cooling-device = <&fimc_is 0 0>;
2201 };
2202 map3 {
2203 trip = <&isp_alert3>;
2204 /* Corresponds to 5fps at freq_table */
2205 cooling-device = <&fimc_is 0 0>;
2206 };
2207 map4 {
2208 trip = <&isp_alert4>;
2209 /* Corresponds to 5fps at freq_table */
2210 cooling-device = <&fimc_is 0 0>;
2211 };
2212 map5 {
2213 trip = <&isp_alert5>;
2214 /* Corresponds to 5fps at freq_table */
2215 cooling-device = <&fimc_is 0 0>;
2216 };
2217 map6 {
2218 trip = <&isp_alert6>;
2219 /* Corresponds to 5fps at freq_table */
2220 cooling-device = <&fimc_is 0 0>;
2221 };
2222 map7 {
2223 trip = <&isp_hot>;
2224 /* Corresponds to HW trip */
2225 cooling-device = <&fimc_is 0 0>;
2226 };
2227 };
2228 };
2229 };
2230
2231 fmp_0: fmp {
2232 compatible = "samsung,exynos-fmp";
2233 };
2234
2235 ufs: ufs@0x13520000 {
2236 /* ----------------------- */
2237 /* 1. SYSTEM CONFIGURATION */
2238 /* ----------------------- */
2239 compatible ="samsung,exynos-ufs";
2240 #address-cells = <2>;
2241 #size-cells = <1>;
2242 ranges;
2243 reg =
2244 <0x0 0x13520000 0x200>, /* 0: HCI standard */
2245 <0x0 0x13521100 0x200>, /* 1: Vendor specificed */
2246 <0x0 0x13510000 0x8000>, /* 2: UNIPRO */
2247 <0x0 0x13530000 0x100>; /* 3: UFS protector */
2248 interrupts = <0 157 0>;
2249 pinctrl-names = "default";
2250 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
2251 clocks =
2252 /* aclk clock */
2253 <&clock GATE_UFS_EMBD_QCH_UFS>,
2254 /* unipro clocks */
2255 <&clock UFS_EMBD>;
2256
2257 clock-names =
2258 /* aclk clocks */
2259 "GATE_UFS_EMBD_QCH_UFS",
2260 /* unipro clocks */
2261 "UFS_EMBD";
2262
2263 /* PM QoS for INT power domain */
2264 /* ufs-pm-qos-int = <400000>;*/
2265
2266 /* DMA coherent callback, should be coupled with 'ufs-sys' */
2267 dma-coherent;
2268
2269 /* UFS PHY isolation and TCXO control */
2270 samsung,pmu-phandle = <&pmu_system_controller>;
2271
2272 /* TCXO exclusive control */
2273 tcxo-ex-ctrl = <0>;
2274
2275 /* UFS IO coherency */
2276 samsung,sysreg-fsys-phandle = <&sysreg_fsys_system_controller>;
2277
2278 /* ----------------------- */
2279 /* 2. UFS COMMON */
2280 /* ----------------------- */
2281 freq-table-hz = <0 0>, <0 0>;
2282
2283 vcc-supply = <&ufs_fixed_vcc>;
2284 vcc-fixed-regulator;
2285
2286
2287 /* ----------------------- */
2288 /* 3. UFS EXYNOS */
2289 /* ----------------------- */
2290 hw-rev = <UFS_VER_0005>;
2291
2292 /* power mode change */
2293 ufs,pmd-attr-lane = /bits/ 8 <1>;
2294 ufs,pmd-attr-gear = /bits/ 8 <3>;
2295
2296 /* hiberantion */
2297 ufs-rx-min-activate-time-cap = <3>;
2298 ufs-rx-hibern8-time-cap = <2>;
2299 ufs-tx-hibern8-time-cap = <2>;
2300
2301 /* board type for UFS CAL */
2302 brd-for-cal = <0>;
2303
2304 fmp-id = <0>;
2305 smu-id = <0>;
2306
2307 /* ----------------------- */
2308 /* 4. ADDITIONAL NODES */
2309 /* ----------------------- */
2310 ufs-phy {
2311 #address-cells = <2>;
2312 #size-cells = <1>;
2313 ranges;
2314 reg = <0x0 0x13524000 0x800>;
2315 };
2316
2317 ufs-dma-coherency {
2318 #address-cells = <2>;
2319 #size-cells = <1>;
2320
2321 offset = <0x1010>;
2322 mask = <(BIT_8 | BIT_9)>;
2323 val = <(BIT_8 | BIT_9)>;
2324 };
2325 };
2326
2327 ufs_fixed_vcc: fixedregulator@0 {
2328 compatible = "regulator-fixed";
2329 regulator-name = "ufs-vcc";
2330 gpio = <&gpg4 0 0>;
2331 regulator-boot-on;
2332 enable-active-high;
2333 };
2334
2335 exynos-pmu {
2336 compatible = "samsung,exynos-pmu";
2337 samsung,syscon-phandle = <&pmu_system_controller>;
2338 };
2339
2340 pmu_system_controller: system-controller@11860000 {
2341 compatible = "samsung,exynos9610-pmu", "syscon";
2342 reg = <0x0 0x11860000 0x10000>;
2343 };
2344
2345 exynos-sysreg-fsys {
2346 compatible = "samsung,exynos-sysreg-fsys";
2347 samsung,syscon-phandle = <&sysreg_fsys_system_controller>;
2348 };
2349
2350 sysreg_fsys_system_controller: system-controller@13410000 {
2351 compatible = "samsung,exynos9610-sysreg-fsys", "syscon";
2352 reg = <0x0 0x13410000 0x1020>;
2353 };
2354
2355 /* DMA */
2356 amba {
2357 #address-cells = <2>;
2358 #size-cells = <1>;
2359 compatible = "arm,amba-bus";
2360 interrupt-parent = <&gic>;
2361 ranges;
2362
2363 pdma0: pdma0@120C0000 {
2364 compatible = "arm,pl330", "arm,primecell";
2365 reg = <0x0 0x120C0000 0x1000>;
2366 interrupts = <0 294 0>;
2367 clocks = <&clock GATE_PDMA_CORE_QCH>;
2368 clock-names = "apb_pclk";
2369 #dma-cells = <1>;
2370 #dma-channels = <8>;
2371 #dma-requests = <32>;
2372 #dma-multi-irq = <1>;
2373 dma-arwrapper = <0x120C4400>,
2374 <0x120C4420>,
2375 <0x120C4440>,
2376 <0x120C4460>,
2377 <0x120C4480>,
2378 <0x120C44A0>,
2379 <0x120C44C0>,
2380 <0x120C44E0>;
2381 dma-awwrapper = <0x120C4404>,
2382 <0x120C4424>,
2383 <0x120C4444>,
2384 <0x120C4464>,
2385 <0x120C4484>,
2386 <0x120C44A4>,
2387 <0x120C44C4>,
2388 <0x120C44E4>;
2389 dma-instwrapper = <0x120C4500>;
2390 dma-mask-bit = <36>;
2391 coherent-mask-bit = <36>;
2392 };
2393 };
2394
2395 watchdog_cl0@10050000 {
2396 compatible = "samsung,exynos7-wdt";
2397 reg = <0x0 0x10050000 0x100>;
2398 interrupts = <0 232 0>;
2399 clocks = <&clock OSCCLK>, <&clock GATE_WDT_CLUSTER0_QCH>;
2400 clock-names = "rate_watchdog", "gate_watchdog";
2401 timeout-sec = <30>;
2402 samsung,syscon-phandle = <&pmu_system_controller>;
2403 index = <0>; /* if little cluster then index is 0*/
2404 };
2405
2406 exynos_adc: adc@11C30000 {
2407 compatible = "samsung,exynos-adc-v3";
2408 reg = <0x0 0x11C30000 0x100>;
2409 sysreg = <0x11C10000>;
2410 interrupts = <0 271 0>;
2411 #io-channel-cells = <1>;
2412 io-channel-ranges;
2413 clocks = <&clock GATE_ADC_CMGP_QCH_S0>;
2414 clock-names = "gate_adcif";
2415 };
2416
2417 rtc@11A20000 {
2418 compatible = "samsung,exynos8-rtc";
2419 reg = <0x0 0x11A20000 0x100>;
2420 interrupts = <0 29 0>, <0 30 0>;
2421 use-chub-only;
2422 };
2423
2424 sec_pwm: pwm@13970000 {
2425 compatible = "samsung,s3c6400-pwm";
2426 reg = <0x0 0x13970000 0x1000>;
2427 samsung,pwm-outputs = <0>, <1>, <2>, <3>, <4>;
2428 #pwm-cells = <3>;
2429 clocks = <&clock GATE_PWM_MOTOR_QCH>, <&clock OSCCLK>;
2430 clock-names = "pwm_pclk", "pwm_sclk";
2431 status = "ok";
2432 };
2433
2434 dpp_0: dpp@0x14884000 { /* GF */
2435 compatible = "samsung,exynos9-dpp";
2436 #pb-id-cells = <3>;
2437 /* DPU_DMA, DPP, DPU_DMA_COMMON */
2438 reg = <0x0 0x14884000 0x1000>, <0x0 0x14895000 0x1000>, <0x0 0x14880000 0x110>;
2439 /* DPU_DMA IRQ, DPP IRQ */
2440 interrupts = <0 210 0>, <0 214 0>;
2441 attr = <0x50007>; /* DPP/IDMA/FLIP/BLOCK/AFBC */
2442 port = <0>; /* AXI port number */
2443
2444 /* HW restriction */
2445 src_f_w = <16 65534 1>;
2446 src_f_h = <16 8190 1>;
2447 src_w = <16 2560 1>;
2448 src_h = <16 3040 1>;
2449 src_xy_align = <1 1>;
2450
2451 dst_f_w = <16 8190 1>;
2452 dst_f_h = <16 8190 1>;
2453 dst_w = <16 2560 1>;
2454 dst_h = <16 3040 1>;
2455 dst_xy_align = <1 1>;
2456
2457 blk_w = <4 2560 1>;
2458 blk_h = <1 3040 1>;
2459 blk_xy_align = <1 1>;
2460
2461 src_h_rot_max = <2160>;
2462 };
2463
2464 dpp_1: dpp@0x14883000 { /* VG0 */
2465 compatible = "samsung,exynos9-dpp";
2466 #pb-id-cells = <3>;
2467 reg = <0x0 0x14883000 0x1000>, <0x0 0x14896000 0x1000>;
2468 interrupts = <0 211 0>, <0 215 0>;
2469 attr = <0x500B6>; /* DPP/IDMA/HDR10/SCALE/CSC/FLIP/BLOCK */
2470 port = <0>; /* AXI port number */
2471 };
2472
2473 dpp_2: dpp@0x14881000 { /* G0 */
2474 compatible = "samsung,exynos9-dpp";
2475 #pb-id-cells = <3>;
2476 reg = <0x0 0x14881000 0x1000>, <0x0 0x14891000 0x1000>;
2477 interrupts = <0 208 0>, <0 212 0>;
2478 attr = <0x50006>; /* DPP/IDMA/FLIP/BLOCK */
2479 port = <0>; /* AXI port number */
2480 };
2481
2482 dpp_3: dpp@0x14882000 { /* G1 */
2483 compatible = "samsung,exynos9-dpp";
2484 #pb-id-cells = <3>;
2485 reg = <0x0 0x14882000 0x1000>, <0x0 0x14892000 0x1000>;
2486 interrupts = <0 209 0>, <0 213 0>;
2487 attr = <0x50006>; /* DPP/IDMA/FLIP/BLOCK */
2488 port = <0>; /* AXI port number */
2489 };
2490
2491 disp_ss: disp_ss@0x14810000 { /* SYSREG_DISPAUD */
2492 compatible = "samsung,exynos9-disp_ss";
2493 reg = <0x0 0x14811000 0x10>;
2494 };
2495
2496 mipi_phy_dsim: phy_m4s4top_dsi0@0x11860000 {
2497 compatible = "samsung,mipi-phy-m4s4-top";
2498 samsung,pmu-syscon = <&pmu_system_controller>;
2499 isolation = <0x070C>;
2500 /* PHY reset be controlled from DSIM */
2501 /* reg = <0x0 0x14811008 0x4>; */
2502 /* reset = <0 1>; */
2503 /* init = <4 5>; */ /* PHY reset control path bit of SYSREG */
2504 owner = <0>; /* 0: DSI, 1: CSI */
2505 #phy-cells = <1>;
2506 };
2507
2508 dsim_0: dsim@0x148E0000 {
2509 compatible = "samsung,exynos9-dsim";
2510 reg = <0x0 0x148E0000 0x100>;
2511 interrupts = <0 204 0>;
2512 iommus = <&sysmmu_dpu>;
2513 phys = <&mipi_phy_dsim 0>;
2514 phy-names = "dsim_dphy";
2515
2516 /* clock */
2517 clock-names = "aclk";
2518 clocks = <&clock UMUX_CLKCMU_DISPAUD_BUS>;
2519
2520 memory-region = <&fb_rmem>;
2521 ddi_id = <0xffffffff>;
2522 };
2523
2524 decon_f: decon_f@0x148B0000 {
2525 compatible = "samsung,exynos9-decon"; /* exynos9810 */
2526 #pb-id-cells = <4>;
2527 reg = <0x0 0x148B0000 0x10000>;
2528
2529 /* interrupt num : FRAME_START, FRMAE_DONE, EXTRA, GPIO_PERIC1(EXT_INT_TE: GPD0[0]) */
2530 interrupts = <0 199 0>,
2531 <0 200 0>,
2532 <0 203 0>,
2533 <0 266 0>;
2534
2535 /* pinctrl */
2536 pinctrl-names = "hw_te_on", "hw_te_off";
2537 pinctrl-0 = <&decon_f_te_on>;
2538 pinctrl-1 = <&decon_f_te_off>;
2539
2540 max_win = <4>;
2541 default_win = <0>;
2542 default_idma = <0>;
2543 psr_mode = <0>; /* 0: video mode, 1: DP command mode, 2: MIPI command mode */
2544 trig_mode = <0>; /* 0: hw trigger, 1: sw trigger */
2545 dsi_mode = <0>; /* 0: single dsi, 1: dual dsi */
2546
2547 /* 0: DSI, 1: eDP, 2:HDMI, 3: WB */
2548 out_type = <0>;
2549 /* 0: DSI0, 1: DSI1, 2: DSI2 */
2550 out_idx = <0>;
2551
2552 /* power domain */
2553 pd_name = "pd-dispaud";
2554
2555 /* pixel per clock */
2556 ppc = <2>;
2557
2558 chip_ver = <9610>;
2559
2560 dpp_cnt = <4>;
2561 dsim_cnt = <2>;
2562 decon_cnt = <3>;
2563
2564 #address-cells = <2>;
2565 #size-cells = <1>;
2566 ranges;
2567
2568 /* EINT for TE */
2569 gpios = <&gpc2 3 0xf>;
2570 /* sw te pending register */
2571 te_eint {
2572 /* NWEINT_GPD0_PEND */
2573 reg = <0x0 0x139B0a14 0x4>;
2574 };
2575
2576 cam-stat {
2577 /* ISPPRE_STATUS(0x1406404C), ISPHQ_STATUS(0x14064054), ISPLP_STATUS(0x1406405C) */
2578 reg = <0x0 0x11864024 0x4>;
2579 };
2580 };
2581
2582 abox_gic: abox_gic@0x14AF0000 {
2583 compatible = "samsung,abox_gic";
2584 status = "okay";
2585 reg = <0x0 0x14AF1000 0x1000>, <0x0 0x14AF2000 0x1004>;
2586 reg-names = "gicd", "gicc";
2587 interrupts = <0 198 0>;
2588 };
2589
2590 abox: abox@0x14A50000 {
2591 compatible = "samsung,abox";
2592 status = "okay";
2593 reg = <0x0 0x14A50000 0x10000>, <0x0 0x14810000 0x3000>, <0x0 0x14B00000 0x35000>;
2594 reg-names = "sfr", "sysreg", "sram";
2595 #address-cells = <2>;
2596 #size-cells = <1>;
2597 ranges;
2598 quirks = "try to asrc off", "off on suspend", "scsc bt";
2599 #sound-dai-cells = <1>;
2600 ipc_tx_offset = <0x22000>;
2601 ipc_rx_offset = <0x22300>;
2602 ipc_tx_ack_offset = <0x222FC>;
2603 ipc_rx_ack_offset = <0x225FC>;
2604 abox_gic = <&abox_gic>;
2605 clocks = <&clock PLL_OUT_AUD>, <&clock GATE_ABOX_QCH_CPU>,
2606 <&clock DOUT_CLK_AUD_AUDIF>, <&clock DOUT_CLK_AUD_ACLK>;
2607 clock-names = "pll", "cpu", "audif", "bus";
2608 uaif_max_div = <512>;
2609 iommus = <&sysmmu_abox>;
2610 pm_qos_int = <0 0 0 0 0>;
2611 pm_qos_aud = <1180000 800000 590000 394000 0>;
2612
2613 abox_rdma_0: abox_rdma@0x14A51000 {
2614 compatible = "samsung,abox-rdma";
2615 reg = <0x0 0x14A51000 0x100>;
2616 id = <0>;
2617 type = "normal";
2618 };
2619
2620 abox_rdma_1: abox_rdma@0x14A51100 {
2621 compatible = "samsung,abox-rdma";
2622 reg = <0x0 0x14A51100 0x100>;
2623 id = <1>;
2624 type = "normal";
2625 };
2626
2627 abox_rdma_2: abox_rdma@0x14A51200 {
2628 compatible = "samsung,abox-rdma";
2629 reg = <0x0 0x14A51200 0x100>;
2630 id = <2>;
2631 type = "normal";
2632 };
2633
2634 abox_rdma_3: abox_rdma@0x14A51300 {
2635 compatible = "samsung,abox-rdma";
2636 reg = <0x0 0x14A51300 0x100>;
2637 id = <3>;
2638 type = "sync";
2639 };
2640
2641 abox_rdma_4: abox_rdma@0x14A51400 {
2642 compatible = "samsung,abox-rdma";
2643 reg = <0x0 0x14A51400 0x100>;
2644 id = <4>;
2645 type = "call";
2646 };
2647
2648 abox_rdma_5: abox_rdma@0x14A51500 {
2649 compatible = "samsung,abox-rdma";
2650 reg = <0x0 0x14A51500 0x100>, <0x0 0x14B22600 0x70>;
2651 id = <5>;
2652 type = "compress";
2653 };
2654
2655 abox_rdma_6: abox_rdma@0x14A51600 {
2656 compatible = "samsung,abox-rdma";
2657 reg = <0x0 0x14A51600 0x100>;
2658 id = <6>;
2659 type = "realtime";
2660 scsc_bt;
2661 };
2662
2663 abox_rdma_7: abox_rdma@0x14A51700 {
2664 compatible = "samsung,abox-rdma";
2665 reg = <0x0 0x14A51700 0x100>;
2666 id = <7>;
2667 type = "realtime";
2668 };
2669
2670 abox_wdma_0: abox_wdma@0x14A52000 {
2671 compatible = "samsung,abox-wdma";
2672 reg = <0x0 0x14A52000 0x100>;
2673 id = <0>;
2674 type = "normal";
2675 scsc_bt;
2676 };
2677
2678 abox_wdma_1: abox_wdma@0x14A52100 {
2679 compatible = "samsung,abox-wdma";
2680 reg = <0x0 0x14A52100 0x100>;
2681 id = <1>;
2682 type = "normal";
2683 };
2684
2685 abox_wdma_2: abox_wdma@0x14A52200 {
2686 compatible = "samsung,abox-wdma";
2687 reg = <0x0 0x14A52200 0x100>;
2688 id = <2>;
2689 type = "call";
2690 };
2691
2692 abox_wdma_3: abox_wdma@0x14A52300 {
2693 compatible = "samsung,abox-wdma";
2694 reg = <0x0 0x14A52300 0x100>;
2695 id = <3>;
2696 type = "realtime";
2697 };
2698
2699 abox_wdma_4: abox_wdma@0x14A52400 {
2700 compatible = "samsung,abox-wdma";
2701 reg = <0x0 0x14A52400 0x100>;
2702 id = <4>;
2703 type = "realtime";
2704 };
2705
2706 abox_uaif_0: abox_uaif@0x14A50500 {
2707 compatible = "samsung,abox-uaif";
2708 reg = <0x0 0x14A50500 0x10>;
2709 id = <0>;
2710 clocks = <&clock DOUT_CLK_AUD_UAIF0>, <&clock GATE_ABOX_QCH_S_BCLK0>;
2711 clock-names = "bclk", "bclk_gate";
2712 pinctrl-names = "default", "sleep";
2713 pinctrl-0 = <&aud_i2s0_bus &aud_i2s0_sdo_bus &aud_codec_mclk>;
2714 pinctrl-1 = <&aud_i2s0_idle &aud_codec_mclk_idle>;
2715 #sound-dai-cells = <0>;
2716 };
2717
2718 abox_uaif_1: abox_uaif@0x14A50510 {
2719 compatible = "samsung,abox-uaif";
2720 reg = <0x0 0x14A50510 0x10>;
2721 id = <1>;
2722 clocks = <&clock DOUT_CLK_AUD_UAIF1>, <&clock GATE_ABOX_QCH_S_BCLK1>;
2723 clock-names = "bclk", "bclk_gate";
2724 pinctrl-names = "default", "sleep";
2725 pinctrl-0 = <&aud_i2s1_bus &aud_i2s1_sdo_bus>;
2726 pinctrl-1 = <&aud_i2s1_idle>;
2727 #sound-dai-cells = <0>;
2728 };
2729
2730 abox_uaif_2: abox_uaif@0x14A50520 {
2731 compatible = "samsung,abox-uaif";
2732 reg = <0x0 0x14A50520 0x10>;
2733 id = <2>;
2734 clocks = <&clock DOUT_CLK_AUD_UAIF2>, <&clock GATE_ABOX_QCH_S_BCLK2>;
2735 clock-names = "bclk", "bclk_gate";
2736 pinctrl-names = "default", "sleep";
2737 pinctrl-0 = <&aud_i2s2_bus &aud_i2s2_sdo_bus>;
2738 pinctrl-1 = <&aud_i2s2_idle>;
2739 #sound-dai-cells = <0>;
2740 };
2741
2742 abox_uaif_4: abox_uaif@0x14A50540 {
2743 compatible = "samsung,abox-uaif";
2744 reg = <0x0 0x14A50540 0x10>;
2745 id = <4>;
2746 /* UAIF4 is connected to UAIF0 as slave */
2747 clocks = <&clock DOUT_CLK_AUD_UAIF0>, <&clock GATE_ABOX_QCH_S_BCLK0>;
2748 clock-names = "bclk", "bclk_gate";
2749 #sound-dai-cells = <0>;
2750 };
2751
2752 abox_dsif: abox_dsif@0x14A50550 {
2753 compatible = "samsung,abox-dsif";
2754 reg = <0x0 0x14A50550 0x10>;
2755 id = <5>;
2756 clocks = <&clock DOUT_CLK_AUD_DSIF>, <&clock GATE_ABOX_QCH_S_BCLK_DSIF>;
2757 clock-names = "bclk", "bclk_gate";
2758 /* DSIF and UAIF2 shares GPIO
2759 * pinctrl-names = "default", "sleep";
2760 * pinctrl-0 = <&aud_dsd_bus>;
2761 * pinctrl-1 = <&aud_dsd_idle>;
2762 */
2763 #sound-dai-cells = <0>;
2764 };
2765
2766 abox_spdy: abox_spdy@0x14A50560 {
2767 compatible = "samsung,abox-spdy";
2768 reg = <0x0 0x14A50560 0x10>;
2769 id = <6>;
2770 clocks = <&clock DOUT_CLK_AUD_FM>, <&clock GATE_ABOX_QCH_FM>;
2771 clock-names = "bclk", "bclk_gate";
2772 /* FM SPEEDY GPIO is controlled by FM radio driver
2773 * pinctrl-names = "default", "sleep";
2774 * pinctrl-0 = <&aud_fm_bus>;
2775 * pinctrl-1 = <&aud_fm_idle>;
2776 */
2777 #sound-dai-cells = <0>;
2778 };
2779
2780 abox_effect: abox_effect@0x14B2E000 {
2781 compatible = "samsung,abox-effect";
2782 reg = <0x0 0x14B2E000 0x1000>;
2783 reg-names = "reg";
2784 abox = <&abox>;
2785 };
2786
2787 abox_debug: abox-debug@0 {
2788 compatible = "samsung,abox-debug";
2789 memory-region = <&abox_rmem>;
2790 reg = <0x0 0x0 0x0>;
2791 };
2792
2793 abox_vss: abox_vss@0 {
2794 compatible = "samsung,abox-vss";
2795 magic_offset = <0x600000>;
2796 reg = <0x0 0x0 0x0>;
2797 };
2798
2799 abox_bt: abox_bt@0 {
2800 compatible = "samsung,abox-bt";
2801 reg = <0x0 0x0 0x0>, <0x0 0x119D0000 0x1000>;
2802 reg-names = "sfr", "mailbox";
2803 };
2804
2805 ext_bin_0: ext_bin@0 {
2806 status = "enabled";
2807 samsung,name = "dsm.bin";
2808 samsung,area = <1>; /* 0:SRAM, 1:DRAM, 2:VSS */
2809 samsung,offset = <0x502000>;
2810 };
2811 ext_bin_1: ext_bin@1 {
2812 status = "okay";
2813 samsung,name = "AP_AUDIO_SLSI.bin";
2814 samsung,area = <1>;
2815 samsung,offset = <0x7F0000>;
2816 };
2817 ext_bin_2: ext_bin@2 {
2818 status = "disabled";
2819 samsung,name = "APBargeIn_AUDIO_SLSI.bin";
2820 samsung,area = <1>;
2821 samsung,offset = <0x7EC000>;
2822 };
2823 ext_bin_3: ext_bin@3 {
2824 status = "disabled";
2825 samsung,name = "SoundBoosterParam.bin";
2826 samsung,area = <1>;
2827 samsung,offset = <0x4FC000>;
2828 };
2829 ext_bin_4: ext_bin@4 {
2830 status = "disabled";
2831 samsung,name = "dummy.bin";
2832 samsung,area = <1>;
2833 samsung,offset = <0x800000>;
2834 };
2835 ext_bin_5: ext_bin@5 {
2836 status = "disabled";
2837 samsung,name = "APBiBF_AUDIO_SLSI.bin";
2838 samsung,area = <1>;
2839 samsung,offset = <0x7EF000>;
2840 };
2841 ext_bin_6: ext_bin@6 {
2842 status = "disabled";
2843 samsung,name = "dummy.bin";
2844 samsung,area = <1>;
2845 samsung,offset = <0x800000>;
2846 };
2847 ext_bin_7: ext_bin@7 {
2848 status = "disabled";
2849 samsung,name = "dummy.bin";
2850 samsung,area = <1>;
2851 samsung,offset = <0x800000>;
2852 };
2853 };
2854
2855 udc: usb@13200000 {
2856 compatible = "samsung,exynos-dwusb";
2857 clocks = <&clock GATE_USB30DRD_QCH_USB30>;
2858 clock-names = "hsdrd";
2859 reg = <0x0 0x13200000 0x10000>;
2860 #address-cells = <2>;
2861 #size-cells = <1>;
2862 ranges;
2863 status = "disabled";
2864
2865 usbdrd_dwc3: dwc3 {
2866 compatible = "synopsys,dwc3";
2867 reg = <0x0 0x13200000 0x10000>;
2868 interrupts = <0 186 0>;
2869 //suspend_clk_freq = <66000000>;
2870 tx-fifo-resize = <0>;
2871 adj-sof-accuracy = <0>;
2872 is_not_vbus_pad = <1>;
2873 enable_sprs_transfer = <1>;
2874 qos_int_level = <100000 200000>;
2875 phys = <&usbdrd_phy 0>, <&usbdrd3_phy 1>;
2876 phy-names = "usb2-phy", "usb3-phy";
2877 /* check susphy support */
2878 xhci_l2_support = <0>;
2879 /* support usb audio offloading: 1, if not: 0 */
2880 usb_audio_offloading = <0>;
2881 /* don't support USB L2 sleep */
2882 ldos = <0>;
2883 /*
2884 * dis-u2-freeclk-exists-quirk, dis_u2_susphy_quirk are alternative.
2885 * One of them should be selected
2886 */
2887 snps,dis-u2-freeclk-exists-quirk;
2888 /* snps,dis_u2_susphy_quirk; */
2889 };
2890 };
2891
2892 usbdrd_phy: phy@131D0000 {
2893 compatible = "samsung,exynos-usbdrd-phy";
2894 reg = <0x0 0x131D0000 0x200>;
2895 clocks = <&clock GATE_USB30DRD_QCH_USB30>, <&clock GATE_USB30DRD_QCH_USBPHY_20CTRL>,
2896 <&clock GATE_USB30DRD_QCH_USBPHY_30CTRL_0>, <&clock GATE_USB30DRD_QCH_USBPHY_30CTRL_1>,
2897 <&clock OSCCLK>;
2898 clock-names = "hsdrd", "usb20", "usb30_0", "usb30_1", "oscclk";
2899 samsung,pmu-syscon = <&pmu_system_controller>;
2900 pmu_mask = <0x3>;
2901 pmu_offset = <0x704>;
2902 //pmu_offset_dp = <0x66c>;
2903
2904 /* USBDP combo phy version - 0x200 */
2905 phy_version = <0x300>;
2906 /* if it doesn't need phy user mux, */
2907 /* you should write "none" */
2908 /* but refclk shouldn't be omitted */
2909 phyclk_mux = "none";
2910 phy_refclk = "oscclk";
2911
2912 /* if Main phy has the other phy, it must be set to 1. jusf for usbphy_info */
2913 has_other_phy = <0>;
2914 /* if combo phy is used, it must be set to 1. usbphy_sub_info is enabled */
2915 has_combo_phy = <0>;
2916 sub_phy_version = <0x300>;
2917
2918 /* ip type */
2919 /* USB3DRD = 0 */
2920 /* USB3HOST = 1 */
2921 /* USB2DRD = 2 */
2922 /* USB2HOST = 3 */
2923 ip_type = <0x2>;
2924
2925 /* for PHY CAL */
2926 /* choice only one item */
2927 phy_refsel_clockcore = <1>;
2928 phy_refsel_ext_osc = <0>;
2929 phy_refsel_xtal = <0>;
2930 phy_refsel_diff_pad = <0>;
2931 phy_refsel_diff_internal = <0>;
2932 phy_refsel_diff_single = <0>;
2933
2934 /* true : 1 , false : 0 */
2935 use_io_for_ovc = <0>;
2936 common_block_disable = <1>;
2937 is_not_vbus_pad = <1>;
2938 used_phy_port = <0>;
2939
2940 status = "disabled";
2941
2942 #phy-cells = <1>;
2943 ranges;
2944 };
2945
2946 usbdrd3_phy: phy@131F0000 {
2947 compatible = "samsung,exynos-usbdrd-phy";
2948 reg = <0x0 0x131F0000 0x1000>,
2949 <0x0 0x131E0000 0x800>;
2950 clocks = <&clock GATE_USB30DRD_QCH_USB30>, <&clock GATE_USB30DRD_QCH_USBPHY_20CTRL>,
2951 <&clock GATE_USB30DRD_QCH_USBPHY_30CTRL_0>, <&clock GATE_USB30DRD_QCH_USBPHY_30CTRL_1>,
2952 <&clock OSCCLK>;
2953 clock-names = "hsdrd", "usb20", "usb30_0", "usb30_1", "oscclk";
2954 samsung,pmu-syscon = <&pmu_system_controller>;
2955 pmu_mask = <0x3>;
2956 pmu_offset = <0x704>;
2957 //pmu_offset_dp = <0x66c>;
2958
2959 /* USBDP combo phy version - 0x200 */
2960 phy_version = <0x530>;
2961 /* if it doesn't need phy user mux, */
2962 /* you should write "none" */
2963 /* but refclk shouldn't be omitted */
2964 phyclk_mux = "none";
2965 phy_refclk = "oscclk";
2966
2967 /* if Main phy has the other phy, it must be set to 1. jusf for usbphy_info */
2968 has_other_phy = <1>;
2969 /* if combo phy is used, it must be set to 1. usbphy_sub_info is enabled */
2970 has_combo_phy = <0>;
2971 sub_phy_version = <0x300>;
2972
2973 /* ip type */
2974 /* USB3DRD = 0 */
2975 /* USB3HOST = 1 */
2976 /* USB2DRD = 2 */
2977 /* USB2HOST = 3 */
2978 ip_type = <0x0>;
2979
2980 /* for PHY CAL */
2981 /* choice only one item */
2982 phy_refsel_clockcore = <1>;
2983 phy_refsel_ext_osc = <0>;
2984 phy_refsel_xtal = <0>;
2985 phy_refsel_diff_pad = <0>;
2986 phy_refsel_diff_internal = <0>;
2987 phy_refsel_diff_single = <0>;
2988
2989 /* true : 1 , false : 0 */
2990 use_io_for_ovc = <0>;
2991 common_block_disable = <1>;
2992 is_not_vbus_pad = <1>;
2993 used_phy_port = <0>;
2994
2995 status = "disabled";
2996
2997 #phy-cells = <1>;
2998 ranges;
2999 };
3000
3001
3002 iommu-domain_dpu {
3003 compatible = "samsung,exynos-iommu-bus";
3004 #dma-address-cells = <1>;
3005 #dma-size-cells = <1>;
3006 ranges;
3007
3008 /* start address, size */
3009 dma-window = <0x10000000 0xEFFF0000>;
3010
3011 domain-clients = <&dsim_0>;
3012 };
3013
3014 iommu-domain_vipx {
3015 compatible = "samsung,exynos-iommu-bus";
3016
3017 /* #address-cells = <2>; */
3018 /* #size-cells = <1>; */
3019 /* ranges; */
3020 #dma-address-cells = <1>;
3021 #dma-size-cells = <1>;
3022 dma-window = <0x30000000 0xB0000000>;
3023
3024 domain-clients = <&vipx>, <&vipx_vertex>;
3025 };
3026
3027 iommu-domain_abox {
3028 compatible = "samsung,exynos-iommu-bus";
3029 #address-cells = <2>;
3030 #size-cells = <1>;
3031 ranges;
3032
3033 domain-clients = <&abox>;
3034 };
3035
3036 iommu-domain_isp {
3037 compatible = "samsung,exynos-iommu-bus";
3038 #address-cells = <2>;
3039 #size-cells = <1>;
3040 ranges;
3041
3042 domain-clients = <&fimc_is>, <&fimc_is_sensor0>, <&fimc_is_sensor1>,
3043 <&fimc_is_sensor2>, <&fimc_is_sensor3>, <&camerapp_gdc>;
3044 };
3045
3046 iommu-domain_mfc {
3047 compatible = "samsung,exynos-iommu-bus";
3048 #address-cells = <2>;
3049 #size-cells = <1>;
3050 ranges;
3051
3052 domain-clients = <&mfc_0>;
3053 };
3054
3055 iommu-domain_g2dmscljpeg {
3056 compatible = "samsung,exynos-iommu-bus";
3057 #address-cells = <2>;
3058 #size-cells = <1>;
3059 ranges;
3060
3061 domain-clients = <&fimg2d>, <&scaler_0>, <&smfc>;
3062 };
3063
3064 fimg2d: g2d@12E40000 {
3065 compatible = "samsung,exynos9610-g2d";
3066 reg = <0x0 0x12E40000 0x9000>;
3067 interrupts = <0 165 0>;
3068 clock-names = "gate";
3069 clocks = <&clock GATE_G2D_QCH>;
3070 iommus = <&sysmmu_g2d>;
3071 hw_ppc =
3072 /* sc_up none x1 x1/4 x1/9 x1/16 */
3073 <1700 1550 1100 1800 2550 3500 /* rgb32 non-rotated */
3074 1650 1350 1000 1500 2600 3250 /* rgb32 rotated */
3075 1500 1450 1300 1700 2550 5950 /* yuv2p non-rotated */
3076 1600 1000 950 1650 2600 3500 /* yuv2p rotated */
3077 1200 950 950 1350 1550 2050 /* 8+2 non-rotated */
3078 1250 450 450 1100 1450 1850 /* 8+2 rotated */
3079 1900>; /* colorfill */
3080
3081 g2d_dvfs_table = <667000 667000
3082 533000 533000
3083 400000 400000
3084 200000 200000
3085 100000 100000
3086 >;
3087 dma-coherent;
3088 };
3089
3090 scaler_0: scaler@12E60000 {
3091 compatible = "samsung,exynos5-scaler";
3092 reg = <0x0 0x12E60000 0x3000>;
3093 interrupts = <0 164 0>;
3094 clocks = <&clock GATE_MSCL_QCH>;
3095 clock-names = "gate";
3096 iommus = <&sysmmu_g2d>;
3097 };
3098
3099 smfc: smfc@12E30000 {
3100 compatible = "samsung,exynos8890-jpeg";
3101 dma-coherent;
3102 reg = <0x0 0x12E30000 0x1000>;
3103 interrupts = <0 163 0>;
3104 clocks = <&clock GATE_JPEG_QCH>;
3105 clock-names = "gate";
3106 iommus = <&sysmmu_g2d>;
3107 smfc,int_qos_minlock = <534000>;
3108 };
3109
3110 /* mali */
3111 mali: mali@11500000 {
3112 compatible = "arm,mali";
3113 reg = <0x0 0x11500000 0x5000>;
3114 interrupts = <0 66 0>,
3115 <0 67 0>,
3116 <0 65 0>;
3117 interrupt-names = "JOB", "MMU", "GPU";
3118 g3d_cmu_cal_id = <ACPM_DVFS_G3D>;
3119 samsung,power-domain = <&pd_g3d>;
3120 g3d_genpd_name = "pd-g3d"; /*KC, RM: pd-g3d, LT,MK: pd-embedded_g3d*/
3121 #cooling-cells = <2>; /* min followed by max */
3122 governor = "interactive";
3123 interactive_info = <377000 94 0>;
3124 gpu_dvfs_table_size = <11 7>; /*<row col>*/
3125 /* 8 columns freq down up stay mif little middle big */
3126 gpu_dvfs_table = < 1053000 95 100 1 2093000 1534000 0
3127 949000 90 98 1 2093000 1534000 0
3128 839000 90 98 1 2093000 1534000 0
3129 764000 90 98 1 1539000 1456000 0
3130 683000 90 95 1 1539000 1456000 0
3131 572000 90 95 1 1539000 1456000 0
3132 546000 90 95 1 1539000 1326000 0
3133 455000 90 95 1 676000 702000 0
3134 385000 85 95 1 546000 598000 0
3135 338000 70 90 1 419000 403000 0
3136 260000 70 90 1 419000 403000 0 >;
3137 gpu_sustainable_info = <0 0 0 0 0>;
3138 gpu_pmqos_cpu_cluster_num = <2>;
3139 gpu_pmu_status_reg_offset = <0x4064>;
3140 gpu_pmu_status_local_pwr_mask = <0xF>; /*0x1 << 0*/
3141 gpu_max_clock = <1053000>;
3142 gpu_max_clock_limit = <1053000>;
3143 gpu_min_clock = <260000>;
3144 gpu_dvfs_start_clock = <260000>;
3145 gpu_dvfs_bl_config_clock = <260000>;
3146 gpu_default_voltage = <800000>;
3147 gpu_cold_minimum_vol = <0>;
3148 gpu_voltage_offset_margin = <37500>;
3149 gpu_tmu_control = <1>;
3150 gpu_temp_throttling_level_num = <6>;
3151 gpu_temp_throttling = <764000 572000 455000 338000 260000 260000>;
3152 gpu_power_coeff = <625>;
3153 gpu_dvfs_time_interval = <5>; /*1 tick : 10ms*/
3154 gpu_default_wakeup_lock = <1>;
3155 gpu_bus_devfreq = <0>;
3156 gpu_dynamic_abb = <0>;
3157 gpu_early_clk_gating = <0>;
3158 gpu_dvs = <0>;
3159 gpu_inter_frame_pm = <0>;
3160 gpu_perf_gathering = <0>;
3161 gpu_runtime_pm_delay_time = <50>;
3162 gpu_dvfs_polling_time = <30>;
3163 gpu_pmqos_int_disable = <1>;
3164 gpu_pmqos_mif_max_clock = <2093000>;
3165 gpu_pmqos_mif_max_clock_base = <546000>;
3166 gpu_cl_dvfs_start_base = <546000>;
3167 gpu_debug_level = <3>; /*DEBUG(1) INFO(2) WARNING(3) ERROR(4)*/
3168 gpu_trace_level = <8>; /*TRACE_ALL*/
3169 gpu_bts_support = <1>;
3170 gpu_mo_min_clock = <764000>;
3171 gpu_boost_gpu_min_lock = <0>;
3172 gpu_boost_egl_min_lock = <1248000>;
3173 gpu_vk_boost_max_lock = <2000>; /* to activate vk boost, should set proper clock*/
3174 gpu_vk_boost_mif_min_lock = <0>;
3175 gpu_asv_cali_lock_val = <0>; /*Should check this value when MALI_ASV_CALIBRATION_SUPPORT is enabled*/
3176 gpu_set_pmu_duration_reg = <0>; /* only for KC for now*/
3177 gpu_set_pmu_duration_val = <0>; /* only for KC for now*/
3178 };
3179
3180 reboot {
3181 compatible = "exynos,reboot";
3182 pmu_base = <0x11860000>;
3183 };
3184
3185 schedutil_gov {
3186 schedutil_domain0: domain@0 {
3187 device_type = "schedutil-domain";
3188 shared-cpus = "0-3";
3189 enabled = <0>; /* Disabled */
3190 qos_min_class = <3>;
3191 };
3192
3193 schedutil_domain1: domain@1 {
3194 device_type = "schedutil-domain";
3195 shared-cpus = "4-7";
3196 enabled = <1>; /* Enabled */
3197 expired_time = <80>; /* 80ms */
3198 qos_min_class = <5>;
3199 };
3200 };
3201
3202 schedutil {
3203 domain@0 {
3204 device_type = "freqvar-tune";
3205 shared-cpus = "0-3";
3206
3207 boost_table = < 0 >;
3208 up_rate_limit_table = < 5 >;
3209 down_rate_limit_table = < 5 >;
3210 upscale_ratio_table = < 80 >;
3211 };
3212
3213 domain@1 {
3214 device_type = "freqvar-tune";
3215 shared-cpus = "4-7";
3216
3217 boost_table = < 0 >;
3218 up_rate_limit_table = < 5 >;
3219 down_rate_limit_table = < 5 >;
3220 upscale_ratio_table = < 80 >;
3221 };
3222 };
3223
3224 cpufreq {
3225 cpufreq_domain0: domain@0 {
3226 device_type = "cpufreq-domain";
3227 sibling-cpus = "0-3";
3228 cal-id = <ACPM_DVFS_CPUCL0>;
3229 dm-type = <DM_CPU_CL0>;
3230
3231 min-freq = <403000>;
3232
3233 /* PM QoS Class ID */
3234 pm_qos-min-class = <3>;
3235 pm_qos-max-class = <4>;
3236
3237 user-boost = <0>;
3238
3239 #cooling-cells = <2>; /* min followed by max */
3240
3241 dm-constraints {
3242 mif-perf {
3243 const-type = <CONSTRAINT_MIN>;
3244 dm-type = <DM_MIF>;
3245 /* cpu mif */
3246 table = < 1742000 845000
3247 1638000 845000
3248 1534000 845000
3249 1456000 845000
3250 1326000 845000
3251 1222000 676000
3252 1118000 676000
3253 1053000 676000
3254 910000 676000
3255 806000 546000
3256 702000 546000
3257 598000 419000
3258 403000 0
3259 >;
3260 };
3261 };
3262 };
3263
3264 cpufreq_domain1: domain@1 {
3265 device_type = "cpufreq-domain";
3266 sibling-cpus = "4-7";
3267 cal-id = <ACPM_DVFS_CPUCL1>;
3268 dm-type = <DM_CPU_CL1>;
3269
3270 min-freq = <936000>;
3271
3272 /* PM QoS Class ID */
3273 pm_qos-min-class = <5>;
3274 pm_qos-max-class = <6>;
3275
3276 #cooling-cells = <2>; /* min followed by max */
3277
3278 dm-constraints {
3279 mif-perf {
3280 const-type = <CONSTRAINT_MIN>;
3281 dm-type = <DM_MIF>;
3282 /* cpu mif */
3283 table = < 2314000 2093000
3284 2210000 2093000
3285 2184000 2093000
3286 2080000 2093000
3287 1976000 2093000
3288 1898000 2002000
3289 1768000 2002000
3290 1664000 1014000
3291 1508000 1014000
3292 1456000 845000
3293 1352000 845000
3294 1248000 676000
3295 1144000 676000
3296 1040000 546000
3297 936000 546000
3298 832000 546000
3299 728000 546000 >;
3300 };
3301 };
3302 };
3303 };
3304
3305 dwmmc_2: dwmmc2@13550000 {
3306 compatible = "samsung,exynos-dw-mshc";
3307 reg = <0x0 0x13550000 0x2000>;
3308 reg-names = "dw_mmc";
3309 interrupts = <0 147 0>;
3310 #address-cells = <1>;
3311 #size-cells = <0>;
3312 clocks = <&clock MMC_CARD>;
3313 clock-names = "ciu";
3314 status = "disabled";
3315 };
3316
3317 contexthub_0: contexthub {
3318 compatible = "samsung,exynos-nanohub";
3319 interrupts = <0 39 0>,<0 111 0>; /* INTREQ_MAILBOX_SHUB2AP, INTREQ_WDT_SHUB */
3320 /* mailbox, sram, dumpgpr, chub reset & cub cpu reset, baaw_p_apm_shub, chub cpu clock */
3321 reg = <0x0 0x11980000 0x200>,
3322 <0x0 0x11200000 0x40000>,
3323 <0x0 0x111f0000 0x100>,
3324 <0x0 0x11863d20 0x10>,
3325 <0x0 0x11100000 0x100>,
3326 <0x0 0x11003010 0x10>;
3327 reg-names = "mailbox", "sram", "dumpgpr",
3328 "chub_reset", "chub_baaw", "cmu_chub_qch";
3329 /* BAAW-P-APM-SHUB */
3330 baaw,baaw-p-apm-chub = <0x40300 0x40800 0x11900>;
3331 /* none, pass, os.checked.bin, Exynos9610.bin */
3332 os-type = "os.checked.bin";
3333 reset-mode = "block";
3334 };
3335
3336 /* Secure log */
3337 seclog {
3338 compatible = "samsung,exynos-seclog";
3339 interrupts = <0 455 0>;
3340 };
3341
3342 /* tbase */
3343 tee {
3344 compatible = "samsung,exynos-tee";
3345 interrupts = <0 454 0>;
3346 };
3347
3348 baaw_p_wlbt: syscon@12050000 {
3349 compatible = "baaw_p_wlbt", "syscon";
3350 reg = <0x0 0x12050000 0xff>;
3351 };
3352
3353 dbus_baaw: syscon@14C20000 {
3354 compatible = "dbus_baaw", "syscon";
3355 reg = <0x0 0x14C20000 0x300>;
3356 };
3357
3358 pbus_baaw: syscon@14C30000 {
3359 compatible = "pbus_baaw", "syscon";
3360 reg = <0x0 0x14C30000 0x300>;
3361 };
3362
3363 wlbt_remap_base: syscon@14C50000 {
3364 compatible = "wlbt_remap", "syscon";
3365 reg = <0x0 0x14C50000 0x300>;
3366 };
3367
3368 boot_cfg: syscon@14C60000 {
3369 compatible = "boot_cfg", "syscon";
3370 reg = <0x0 0x14C60000 0x1100>;
3371 };
3372
3373 /* MAILBOX_AP2WLBT */
3374 scsc_wifibt: scsc_wifibt@119c0000 {
3375 compatible = "samsung,scsc_wifibt";
3376 /* Mailbox Registers */
3377 reg = <0x0 0x119c0000 0x180>;
3378 /* 10.3.2 External GIC IRQ table */
3379 //SPI[42] 74 BLK_ALIVE INTREQ__MAILBOX_WLBT2AP
3380 //SPI[28] 60 BLK_ALIVE INTREQ__ALIVE_WLBT_ACTIVE
3381 //SPI[72] 104 BLK_WLBT WB2AP_WDOG_RESET_REQ__ALV
3382 //SPI[73] 105 BLK_WLBT WB2AP_CFG_REQ__ALV
3383 interrupts = <0 42 4>, <0 28 4>, <0 72 4>, <0 73 4>;
3384 interrupt-names = "MBOX","ALIVE","WDOG","CFG_REQ";
3385 /* PMU alive handle */
3386 samsung,syscon-phandle = <&pmu_system_controller>;
3387 samsung,baaw_p_wlbt-syscon-phandle = <&baaw_p_wlbt>;
3388 samsung,dbus_baaw-syscon-phandle = <&dbus_baaw>;
3389 samsung,pbus_baaw-syscon-phandle = <&pbus_baaw>;
3390 samsung,wlbt_remap-syscon-phandle = <&wlbt_remap_base>;
3391 samsung,boot_cfg-syscon-phandle = <&boot_cfg>;
3392 /* MIF / INT / CL0 / CL1 */
3393 /* this qos_table should be per-platform. Leave it here until we have multiple platfrom support */
3394 qos_table = <
3395 419000 100000 403000 728000 /* SCSC_QOS_MIN */
3396 1014000 533000 910000 1664000 /* SCSC_QOS_MED */
3397 2093000 667000 1534000 2392000 /* SCSC_QOS_MAX */
3398 >;
3399 /* SMAPPER */
3400 smapper_num_banks = <11>;
3401 smapper_reg = <0x14c40000 0x10000>;
3402 smapper_bank_table {
3403 smapper_bank_0 {
3404 bank_num = <0x0>;
3405 fw_window_start = <0x82000000>;
3406 fw_window_size = <0x100000>;
3407 num_entries = <160>;
3408 is_large = <1>;
3409 };
3410 smapper_bank_1 {
3411 bank_num = <0x1>;
3412 fw_window_start = <0x82100000>;
3413 fw_window_size = <0x100000>;
3414 num_entries = <160>;
3415 is_large = <1>;
3416 };
3417 smapper_bank_2 {
3418 bank_num = <0x2>;
3419 fw_window_start = <0x82200000>;
3420 fw_window_size = <0x100000>;
3421 num_entries = <160>;
3422 is_large = <1>;
3423 };
3424 smapper_bank_3 {
3425 bank_num = <0x3>;
3426 fw_window_start = <0x82300000>;
3427 fw_window_size = <0x100000>;
3428 num_entries = <160>;
3429 is_large = <1>;
3430 };
3431 smapper_bank_4 {
3432 bank_num = <0x4>;
3433 fw_window_start = <0x83000000>;
3434 fw_window_size = <0x100000>;
3435 num_entries = <64>;
3436 is_large = <0>;
3437 };
3438 smapper_bank_5 {
3439 bank_num = <0x5>;
3440 fw_window_start = <0x83100000>;
3441 fw_window_size = <0x100000>;
3442 num_entries = <64>;
3443 is_large = <0>;
3444 };
3445 smapper_bank_6 {
3446 bank_num = <0x6>;
3447 fw_window_start = <0x83200000>;
3448 fw_window_size = <0x100000>;
3449 num_entries = <64>;
3450 is_large = <0>;
3451 };
3452 smapper_bank_7 {
3453 bank_num = <0x7>;
3454 fw_window_start = <0x83300000>;
3455 fw_window_size = <0x100000>;
3456 num_entries = <64>;
3457 is_large = <0>;
3458 };
3459 smapper_bank_8 {
3460 bank_num = <0x8>;
3461 fw_window_start = <0x83400000>;
3462 fw_window_size = <0x100000>;
3463 num_entries = <64>;
3464 is_large = <0>;
3465 };
3466 smapper_bank_9 {
3467 bank_num = <0x9>;
3468 fw_window_start = <0x83500000>;
3469 fw_window_size = <0x100000>;
3470 num_entries = <64>;
3471 is_large = <0>;
3472 };
3473 smapper_bank_10 {
3474 bank_num = <0xa>;
3475 fw_window_start = <0x83600000>;
3476 fw_window_size = <0x100000>;
3477 num_entries = <64>;
3478 is_large = <0>;
3479 };
3480 };
3481 };
3482
3483 fm@14AC0000 {
3484 compatible = "samsung,exynos9610-fm";
3485 reg = <0x0 0x14AC0000 0x2000>,
3486 <0x0 0x14800800 0x10>;
3487 elna_gpio = <&gpg1 0 0x1>; /* FM_LNA_EN */
3488 pinctrl-names = "default";
3489 pinctrl-0 = <&fm_lna_en>;
3490 clocks = <&clock MUX_AUD_FM>,
3491 <&clock GATE_ABOX_QCH_FM>,
3492 <&clock DOUT_CLK_AUD_FM>; /* mux_aud_fm, qch_fm, clk_aud_fm */
3493 clock-names = "mux_aud_fm", "qch_fm", "clk_aud_fm";
3494 samsung,syscon-phandle = <&pmu_system_controller>;
3495 samsung,power-domain = <&pd_dispaud>;
3496 status = "ok";
3497 };
3498
3499 exynos-bcmdbg {
3500 compatible = "samsung,exynos-bcm_dbg";
3501
3502 pd-name = "pd-trex", "pd-dispaud", "pd-g2d", "pd-mfc", "pd-isp",
3503 "pd-cam", "pd-vipx1", "pd-vipx2", "pd-usb", "pd-fsys";
3504
3505 max_define_event = <PRE_DEFINE_EVT_MAX>;
3506 bcm_cnt_nr = <4>;
3507 /* define_event_index ev0 ev1 ev2 ev3 */
3508 define_events = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0 0x0>,
3509 <PEAK_LATENCY_FMT_EVT 0x4 0x5 0x26 0x27>;
3510 default_define_event = <PEAK_LATENCY_FMT_EVT>;
3511
3512 /* sm_id_mask sm_id_value */
3513 define_filter_id = <NO_PRE_DEFINE_EVT 0x0 0x0>,
3514 <PEAK_LATENCY_FMT_EVT 0x0 0x0>;
3515 /* ev0 ev1 ev2 ev3 */
3516 define_filter_id_active = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0 0x0>,
3517 <PEAK_LATENCY_FMT_EVT 0x0 0x0 0x0 0x0>;
3518 /* sm_other_type0 sm_other_mask0 sm_other_value0 */
3519 define_filter_other_0 = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0>,
3520 <PEAK_LATENCY_FMT_EVT 0x0 0x0 0x0>;
3521 /* sm_other_type1 sm_other_mask1 sm_other_value1 */
3522 define_filter_other_1 = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0>,
3523 <PEAK_LATENCY_FMT_EVT 0x0 0x0 0x0>;
3524 /* ev0 ev1 ev2 ev3 */
3525 define_filter_other_active = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0 0x0>,
3526 <PEAK_LATENCY_FMT_EVT 0x0 0x0 0x0 0x0>;
3527 /* peak_mask peak_id */
3528 define_sample_id = <NO_PRE_DEFINE_EVT 0x0 0x0>,
3529 <PEAK_LATENCY_FMT_EVT 0x0 0x0>;
3530 /* ev0 ev1 ev2 ev3 */
3531 define_sample_id_enable = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0 0x0>,
3532 <PEAK_LATENCY_FMT_EVT 0x0 0x0 0x1 0x1>;
3533 bcm_ip_nr = <31>;
3534 initial_run_bcm_ip = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>,
3535 <11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>, <20>,
3536 <21>, <22>, <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>;
3537 initial_bcm_run = <BCM_STOP>;
3538 /* msec (max 500msec) */
3539 initial_period = <1>;
3540 initial_bcm_mode = <BCM_MODE_INTERVAL>;
3541 available_stop_owner = <PANIC_HANDLE CAMERA_DRIVER MODEM_IF ITMON_HANDLE>;
3542 buff_size = <0x100000>;
3543 };
3544
3545 vipx: vipx@10D60000 {
3546 compatible = "samsung,exynos-vipx";
3547 id = <0>;
3548 reg = <0x0 0x10D60000 0x10000>, /* VIPX_CPU_SS1 */
3549 <0x0 0x10F60000 0x10000>, /* VIPX_CPU_SS2 */
3550 <0x0 0x10D90000 0x2000>, /* ITCM(8K) */
3551 <0x0 0x10DA0000 0x4000>; /* DTCM(16K) */
3552 pinctrl-names = "default","release";
3553 pinctrl-0 = <>;
3554 pinctrl-1 = <>;
3555 clocks = <&clock UMUX_CLKCMU_VIPX1_BUS>,
3556 <&clock GATE_VIPX1_QCH>,
3557 <&clock UMUX_CLKCMU_VIPX2_BUS>,
3558 <&clock GATE_VIPX2_QCH>,
3559 <&clock GATE_VIPX2_QCH_LOCAL>;
3560 clock-names = "UMUX_CLKCMU_VIPX1_BUS",
3561 "GATE_VIPX1_QCH",
3562 "UMUX_CLKCMU_VIPX2_BUS",
3563 "GATE_VIPX2_QCH",
3564 "GATE_VIPX2_QCH_LOCAL";
3565
3566 interrupts = <0 129 0>,
3567 <0 130 0>;
3568 iommus = <&sysmmu_vipx1>, <&sysmmu_vipx2>;
3569 status = "ok";
3570 };
3571
3572 vipx_vertex: vipx_vertex@10D60000 {
3573 compatible = "samsung,exynos-vipx-vertex";
3574 id = <0>;
3575 reg = <0x0 0x10D60000 0x10000>, /* VIPX_CPU_SS1 */
3576 <0x0 0x10F60000 0x10000>, /* VIPX_CPU_SS2 */
3577 <0x0 0x10D90000 0x2000>, /* ITCM(8K) */
3578 <0x0 0x10DA0000 0x4000>; /* DTCM(16K) */
3579 pinctrl-names = "default","release";
3580 pinctrl-0 = <>;
3581 pinctrl-1 = <>;
3582 clocks = <&clock UMUX_CLKCMU_VIPX1_BUS>,
3583 <&clock GATE_VIPX1_QCH>,
3584 <&clock UMUX_CLKCMU_VIPX2_BUS>,
3585 <&clock GATE_VIPX2_QCH>,
3586 <&clock GATE_VIPX2_QCH_LOCAL>;
3587 clock-names = "UMUX_CLKCMU_VIPX1_BUS",
3588 "GATE_VIPX1_QCH",
3589 "UMUX_CLKCMU_VIPX2_BUS",
3590 "GATE_VIPX2_QCH",
3591 "GATE_VIPX2_QCH_LOCAL";
3592
3593 interrupts = <0 129 0>,
3594 <0 130 0>;
3595 iommus = <&sysmmu_vipx1>, <&sysmmu_vipx2>;
3596 status = "ok";
3597 };
3598 };
Motorola kernel-slsi