arch/arm64/boot/dts/exynos/exynos9610.dtsi

   1 /*
   2  * SAMSUNG EXYNOS9610 SoC device tree source
   3  *
   4  * Copyright (c) 2017 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS9610 SoC device nodes are listed in this file.
   8  * EXYNOS9610 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <dt-bindings/clock/exynos9610.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include "exynos9610-pinctrl.dtsi"
  19 #include <dt-bindings/ufs/ufs.h>
  20 #include "exynos9610-sysmmu.dtsi"
  21
  22 / {
  23         compatible = "samsung,armv8", "samsung,exynos9610";
  24         interrupt-parent = <&gic>;
  25         #address-cells = <2>;
  26         #size-cells = <1>;
  27
  28         aliases {
  29                 pinctrl0 = &pinctrl_0;
  30                 pinctrl1 = &pinctrl_1;
  31                 pinctrl2 = &pinctrl_2;
  32                 pinctrl3 = &pinctrl_3;
  33                 pinctrl4 = &pinctrl_4;
  34 //              pinctrl5 = &pinctrl_5;
  35                 usi0 = &usi_0_shub;
  36                 usi1 = &usi_0_shub_i2c;
  37                 usi2 = &usi_0_cmgp;
  38                 usi3 = &usi_0_cmgp_i2c;
  39                 usi4 = &usi_1_cmgp;
  40                 usi5 = &usi_1_cmgp_i2c;
  41                 usi6 = &usi_2_cmgp;
  42                 usi7 = &usi_2_cmgp_i2c;
  43                 usi8 = &usi_3_cmgp;
  44                 usi9 = &usi_3_cmgp_i2c;
  45                 usi10 = &usi_4_cmgp;
  46                 usi11 = &usi_4_cmgp_i2c;
  47                 usi12 = &usi_peri_uart;
  48                 usi13 = &usi_peri_cami2c_0;
  49                 usi14 = &usi_peri_cami2c_1;
  50                 usi15 = &usi_peri_cami2c_2;
  51                 usi16 = &usi_peri_cami2c_3;
  52                 usi17 = &usi_peri_spi_0;
  53                 usi18 = &usi_peri_spi_1;
  54                 usi19 = &usi_peri_usi_0;
  55                 usi20 = &usi_peri_usi_0_i2c;
  56                 usi21 = &usi_peri_spi_2;
  57                 hsi2c0 = &hsi2c_0;
  58                 hsi2c1 = &hsi2c_1;
  59                 hsi2c2 = &hsi2c_2;
  60                 hsi2c3 = &hsi2c_3;
  61                 hsi2c4 = &hsi2c_4;
  62                 hsi2c5 = &hsi2c_5;
  63                 hsi2c6 = &hsi2c_6;
  64                 hsi2c7 = &hsi2c_7;
  65                 hsi2c8 = &hsi2c_8;
  66                 hsi2c9 = &hsi2c_9;
  67                 hsi2c10 = &hsi2c_10;
  68                 hsi2c11 = &hsi2c_11;
  69                 hsi2c12 = &hsi2c_12;
  70                 hsi2c13 = &hsi2c_13;
  71                 hsi2c14 = &hsi2c_14;
  72                 hsi2c15 = &hsi2c_15;
  73                 hsi2c16 = &hsi2c_16;
  74                 hsi2c17 = &hsi2c_17;
  75                 spi0 = &spi_0;
  76                 spi1 = &spi_1;
  77                 spi2 = &spi_2;
  78                 spi3 = &spi_3;
  79                 spi4 = &spi_4;
  80                 spi5 = &spi_5;
  81                 spi6 = &spi_6;
  82                 spi7 = &spi_7;
  83                 spi8 = &spi_8;
  84                 spi9 = &spi_9;
  85                 uart0 = &serial_0;
  86                 uart1 = &serial_1;
  87                 uart2 = &serial_2;
  88                 uart3 = &serial_3;
  89                 uart4 = &serial_4;
  90                 uart5 = &serial_5;
  91                 uart6 = &serial_6;
  92                 uart7 = &serial_7;
  93         };
  94
  95         chipid@10000000 {
  96                 compatible = "samsung,exynos9610-chipid";
  97                 reg = <0x0 0x10000000 0x100>;
  98         };
  99
 100         cpus {
 101                 #address-cells = <2>;
 102                 #size-cells = <0>;
 103
 104                 cpu0: cpu@100 {
 105                         device_type = "cpu";
 106                         compatible = "arm,cortex-a53", "arm,armv8";
 107                         reg = <0x0 0x0>;
 108                         enable-method = "psci";
 109                 };
 110                 cpu1: cpu@101 {
 111                         device_type = "cpu";
 112                         compatible = "arm,cortex-a53", "arm,armv8";
 113                         reg = <0x0 0x1>;
 114                         enable-method = "psci";
 115                 };
 116                 cpu2: cpu@102 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a53", "arm,armv8";
 119                         reg = <0x0 0x2>;
 120                         enable-method = "psci";
 121                 };
 122                 cpu3: cpu@103 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a53", "arm,armv8";
 125                         reg = <0x0 0x3>;
 126                         enable-method = "psci";
 127                 };
 128                 cpu4: cpu@0 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a73", "arm,armv8";
 131                         reg = <0x0 0x100>;
 132                         enable-method = "psci";
 133                 };
 134                 cpu5: cpu@1 {
 135                         device_type = "cpu";
 136                         compatible = "arm,cortex-a73", "arm,armv8";
 137                         reg = <0x0 0x101>;
 138                         enable-method = "psci";
 139                 };
 140                 cpu6: cpu@2 {
 141                         device_type = "cpu";
 142                         compatible = "arm,cortex-a73", "arm,armv8";
 143                         reg = <0x0 0x102>;
 144                         enable-method = "psci";
 145                 };
 146                 cpu7: cpu@3 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a73", "arm,armv8";
 149                         reg = <0x0 0x103>;
 150                         enable-method = "psci";
 151                 };
 152         };
 153
 154         psci {
 155                 compatible = "arm,psci";
 156                 method = "smc";
 157                 cpu_suspend = <0xC4000001>;
 158                 cpu_off = <0x84000002>;
 159                 cpu_on = <0xC4000003>;
 160         };
 161
 162         gic:interrupt-controller@12300000 {
 163                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 164                 #interrupt-cells = <3>;
 165                 #address-cells = <0>;
 166                 interrupt-controller;
 167                 reg =   <0x0 0x12301000 0x1000>,
 168                         <0x0 0x12302000 0x1000>,
 169                         <0x0 0x12304000 0x2000>,
 170                         <0x0 0x12306000 0x2000>;
 171                 interrupts = <1 9 0xf04>;
 172         };
 173
 174         timer {
 175                 compatible = "arm,armv8-timer";
 176                 interrupts = <GIC_PPI 13
 177                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 178                              <GIC_PPI 14
 179                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 180                              <GIC_PPI 11
 181                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 182                              <GIC_PPI 10
 183                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 184                 clock-frequency = <26000000>;
 185                 use-clocksource-only;
 186                 use-physical-timer;
 187         };
 188
 189         clock: clock-controller@0x12100000 {
 190                 compatible = "samsung,exynos9610-clock";
 191                 reg = <0x0 0x12100000 0x8000>;
 192                 #clock-cells = <1>;
 193                 acpm-ipc-channel = <0>;
 194         };
 195
 196         mct@10040000 {
 197                 compatible = "samsung,exynos4210-mct";
 198                 reg = <0x0 0x10040000 0x800>;
 199                 interrupt-controller;
 200                 #interrupt-cells = <1>;
 201                 interrupt-parent = <&mct_map>;
 202                 interrupts =    <0>, <1>, <2>, <3>,
 203                                 <4>, <5>, <6>, <7>,
 204                                 <8>, <9>, <10>, <11>;
 205                 clocks = <&clock OSCCLK>, <&clock GATE_MCT_QCH>;
 206                 clock-names = "fin_pll", "mct";
 207                 use-clockevent-only;
 208
 209                 mct_map: mct-map {
 210                         #interrupt-cells = <1>;
 211                         #address-cells = <0>;
 212                         #size-cells = <0>;
 213                         interrupt-map = <0 &gic 0 234 0>,
 214                                         <1 &gic 0 235 0>,
 215                                         <2 &gic 0 236 0>,
 216                                         <3 &gic 0 237 0>,
 217                                         <4 &gic 0 238 0>,
 218                                         <5 &gic 0 239 0>,
 219                                         <6 &gic 0 240 0>,
 220                                         <7 &gic 0 241 0>,
 221                                         <8 &gic 0 242 0>,
 222                                         <9 &gic 0 243 0>,
 223                                         <10 &gic 0 244 0>,
 224                                         <11 &gic 0 245 0>;
 225                 };
 226         };
 227
 228         speedy@11a10000 {
 229                 compatible = "samsung,exynos-speedy";
 230                 reg = <0x0 0x11a10000 0x2000>;
 231                 interrupts = <0 37 0>;
 232                 #address-cells = <1>;
 233                 #size-cells = <0>;
 234                 pinctrl-names = "default";
 235                 pinctrl-0 = <&speedy_bus>;
 236                 status = "disabled";
 237         };
 238
 239         acpm {
 240                 compatible = "samsung,exynos-acpm";
 241                 #address-cells = <2>;
 242                 #size-cells = <1>;
 243                 acpm-ipc-channel = <4>;
 244                 fvmap_offset = <0x6000>;
 245                 reg = <0x0 0x11820000 0x1000>;          /* TIMER_APM */
 246                 reg-names = "timer_apm";
 247                 peritimer-cnt = <0xFFFF>;
 248         };
 249
 250         acpm_ipc {
 251                 compatible = "samsung,exynos-acpm-ipc";
 252                 #address-cells = <2>;
 253                 #size-cells = <1>;
 254                 interrupts = <0 38 0>;                  /* AP2APM MAILBOX SPI NUM*/
 255                 reg = <0x0 0x11900000 0x1000>,          /* AP2APM MAILBOX */
 256                     <0x0 0x2039000 0x15000>;        /* APM SRAM */
 257                 initdata-base = <0x6F00>;
 258                 num-timestamps = <32>;
 259                 debug-log-level = <0>;
 260                 logging-period = <500>;
 261                 dump-base = <0x203C000>;
 262                 dump-size = <0x12000>;                  /* 72KB */
 263         };
 264
 265         acpm_dvfs {
 266                 compatible = "samsung,exynos-acpm-dvfs";
 267                 acpm-ipc-channel = <5>;
 268         };
 269
 270         /* ALIVE */
 271         pinctrl_0: pinctrl@11850000 {
 272                 compatible = "samsung,exynos9610-pinctrl";
 273                 reg = <0x0 0x11850000 0x1000>;
 274                 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
 275                                 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
 276                                 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
 277                                 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
 278                                 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
 279                                 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
 280
 281                 wakeup-interrupt-controller {
 282                         compatible = "samsung,exynos7-wakeup-eint";
 283                 };
 284         };
 285
 286         /* CMGP */
 287         pinctrl_1: pinctrl@11C20000{
 288                 compatible = "samsung,exynos9610-pinctrl";
 289                 reg = <0x0 0x11C20000 0x1000>;
 290                 interrupts = <0 142 0>, <0 143 0>, <0 144 0>, <0 145 0>,
 291                                 <0 158 0>, <0 159 0>, <0 160 0>, <0 161 0>,
 292                                 <0 162 0>, <0 170 0>, <0 171 0>, <0 172 0>,
 293                                 <0 173 0>, <0 174 0>, <0 185 0>, <0 196 0>,
 294                                 <0 197 0>, <0 226 0>, <0 227 0>, <0 228 0>,
 295                                 <0 269 0>, <0 270 0>, <0 272 0>, <0 278 0>,
 296                                 <0 318 0>, <0 319 0>;
 297
 298                 wakeup-interrupt-controller {
 299                         compatible = "samsung,exynos7-wakeup-eint";
 300                 };
 301         };
 302
 303         /* DISPAUD */
 304         pinctrl_2: pinctrl@14A60000{
 305                 compatible = "samsung,exynos9610-pinctrl";
 306                 reg = <0x0 0x14A60000 0x1000>;
 307         };
 308
 309         /* FSYS */
 310         pinctrl_3: pinctrl@13490000 {
 311                 compatible = "samsung,exynos9610-pinctrl";
 312                 reg = <0x0 0x13490000 0x1000>;
 313                 interrupts = <0 150 0>;
 314         };
 315
 316         /* TOP */
 317         pinctrl_4: pinctrl@139B0000 {
 318                 compatible = "samsung,exynos9610-pinctrl";
 319                 reg = <0x0 0x139B0000 0x1000>;
 320                 interrupts = <0 266 0>;
 321         };
 322
 323 #if 0
 324         /* SHUB */
 325         pinctrl_5: pinctrl@11080000{
 326                 compatible = "samsung,exynos9610-pinctrl";
 327                 reg = <0x0 0x11080000 0x1000>;
 328                 interrupts = <0 116 0>;
 329         };
 330 #endif
 331
 332         /* USI_SHUB_0 */
 333         usi_0_shub: usi@11013000 {
 334                 compatible = "samsung,exynos-usi-v2";
 335                 reg = <0x0 0x11013000 0x4>;
 336                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 337                 status = "disabled";
 338         };
 339
 340         /* USI_SHUB_0_I2C */
 341         usi_0_shub_i2c: usi@11013004 {
 342                 compatible = "samsung,exynos-usi-v2";
 343                 reg = <0x0 0x11013018 0x4>;
 344                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 345                 status = "disabled";
 346         };
 347
 348         /* USI_0_CMGP */
 349         usi_0_cmgp: usi@11C12000 {
 350                 compatible = "samsung,exynos-usi-v2";
 351                 reg = <0x0 0x11C12000 0x4>;
 352                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 353                 status = "disabled";
 354         };
 355
 356         /* USI_0_CMGP_I2C */
 357         usi_0_cmgp_i2c: usi@11C12004 {
 358                 compatible = "samsung,exynos-usi-v2";
 359                 reg = <0x0 0x11C12004 0x4>;
 360                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 361                 status = "disabled";
 362         };
 363
 364         /* USI_1_CMGP */
 365         usi_1_cmgp: usi@11C12010 {
 366                 compatible = "samsung,exynos-usi-v2";
 367                 reg = <0x0 0x11C12010 0x4>;
 368                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 369                 status = "disabled";
 370         };
 371
 372         /* USI_1_CMGP_I2C */
 373         usi_1_cmgp_i2c: usi@11C12014 {
 374                 compatible = "samsung,exynos-usi-v2";
 375                 reg = <0x0 0x11C12014 0x4>;
 376                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 377                 status = "disabled";
 378         };
 379
 380         /* USI_2_CMGP */
 381         usi_2_cmgp: usi@11C12020 {
 382                 compatible = "samsung,exynos-usi-v2";
 383                 reg = <0x0 0x11C12020 0x4>;
 384                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 385                 status = "disabled";
 386         };
 387
 388         /* USI_2_CMGP_I2C */
 389         usi_2_cmgp_i2c: usi@11C12024 {
 390                 compatible = "samsung,exynos-usi-v2";
 391                 reg = <0x0 0x11C12024 0x4>;
 392                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 393                 status = "disabled";
 394         };
 395
 396         /* USI_3_CMGP */
 397         usi_3_cmgp: usi@11C12030 {
 398                 compatible = "samsung,exynos-usi-v2";
 399                 reg = <0x0 0x11C12030 0x4>;
 400                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 401                 status = "disabled";
 402         };
 403
 404         /* USI_3_CMGP_I2C */
 405         usi_3_cmgp_i2c: usi@11C12034 {
 406                 compatible = "samsung,exynos-usi-v2";
 407                 reg = <0x0 0x11C12034 0x4>;
 408                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 409                 status = "disabled";
 410         };
 411
 412         /* USI_4_CMGP */
 413         usi_4_cmgp: usi@11C12040 {
 414                 compatible = "samsung,exynos-usi-v2";
 415                 reg = <0x0 0x11C12040 0x4>;
 416                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 417                 status = "disabled";
 418         };
 419
 420         /* USI_4_CMGP_I2C */
 421         usi_4_cmgp_i2c: usi@11C12044 {
 422                 compatible = "samsung,exynos-usi-v2";
 423                 reg = <0x0 0x11C12044 0x4>;
 424                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 425                 status = "disabled";
 426         };
 427
 428         /* USI_PERI_UART */
 429         usi_peri_uart: usi@10011010 {
 430                 compatible = "samsung,exynos-usi-v2";
 431                 reg = <0x0 0x10011010 0x4>;
 432                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 433                 status = "disabled";
 434         };
 435
 436         /* USI_PERI_CAMI2C_0 */
 437         usi_peri_cami2c_0: usi@10011020 {
 438                 compatible = "samsung,exynos-usi-v2";
 439                 reg = <0x0 0x10011020 0x4>;
 440                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 441                 status = "disabled";
 442         };
 443
 444         /* USI_PERI_CAMI2C_1 */
 445         usi_peri_cami2c_1: usi@10011024 {
 446                 compatible = "samsung,exynos-usi-v2";
 447                 reg = <0x0 0x10011024 0x4>;
 448                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 449                 status = "disabled";
 450         };
 451
 452         /* USI_PERI_CAMI2C_2 */
 453         usi_peri_cami2c_2: usi@10011028 {
 454                 compatible = "samsung,exynos-usi-v2";
 455                 reg = <0x0 0x10011028 0x4>;
 456                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 457                 status = "disabled";
 458         };
 459
 460         /* USI_PERI_CAMI2C_3 */
 461         usi_peri_cami2c_3: usi@1001102C {
 462                 compatible = "samsung,exynos-usi-v2";
 463                 reg = <0x0 0x1001102C 0x4>;
 464                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 465                 status = "disabled";
 466         };
 467
 468         /* USI_PERI_SPI_0 */
 469         usi_peri_spi_0: usi@10011030 {
 470                 compatible = "samsung,exynos-usi-v2";
 471                 reg = <0x0 0x10011030 0x4>;
 472                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 473                 status = "disabled";
 474         };
 475
 476         /* USI_PERI_SPI_1 */
 477         usi_peri_spi_1: usi@10011034 {
 478                 compatible = "samsung,exynos-usi-v2";
 479                 reg = <0x0 0x10011034 0x4>;
 480                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 481                 status = "disabled";
 482         };
 483
 484         /* USI_PERI_USI_0 */
 485         usi_peri_usi_0: usi@1001103C {
 486                 compatible = "samsung,exynos-usi-v2";
 487                 reg = <0x0 0x1001103C 0x4>;
 488                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 489                 status = "disabled";
 490         };
 491
 492         /* USI_PERI_USI_0_I2C */
 493         usi_peri_usi_0_i2c: usi@10011040 {
 494                 compatible = "samsung,exynos-usi-v2";
 495                 reg = <0x0 0x10011040 0x4>;
 496                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 497                 status = "disabled";
 498         };
 499
 500         /* USI_PERI_SPI_2 */
 501         usi_peri_spi_2: usi@10011038 {
 502                 compatible = "samsung,exynos-usi-v2";
 503                 reg = <0x0 0x10011038 0x4>;
 504                 /*      usi_v2_mode = "i2c" or "spi" or "uart"  */
 505                 status = "disabled";
 506         };
 507
 508         /* USI_0_SHUB */
 509         hsi2c_0: hsi2c@110C0000 {
 510                 compatible = "samsung,exynos5-hsi2c";
 511                 samsung,check-transdone-int;
 512                 default-clk = <200000000>;
 513                 reg = <0x0 0x110C0000 0x1000>;
 514                 interrupts = <0 112 0>;
 515                 #address-cells = <1>;
 516                 #size-cells = <0>;
 517                 pinctrl-names = "default";
 518                 pinctrl-0 = <&hsi2c0_bus>;
 519                 clocks = <&clock MUX_SHUB_USI00>, <&clock GATE_USI_SHUB00_QCH>;
 520                 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
 521                 samsung,scl-clk-stretching;
 522                 samsung,usi-i2c-v2;
 523                 gpio_scl= <&gph0 0 0x1>;
 524                 gpio_sda= <&gph0 1 0x1>;
 525                 status = "disabled";
 526         };
 527
 528         /* USI_0_SHUB_I2C */
 529         hsi2c_1: hsi2c@110D0000 {
 530                 compatible = "samsung,exynos5-hsi2c";
 531                 samsung,check-transdone-int;
 532                 default-clk = <200000000>;
 533                 reg = <0x0 0x110D0000 0x1000>;
 534                 interrupts = <0 117 0>;
 535                 #address-cells = <1>;
 536                 #size-cells = <0>;
 537                 pinctrl-names = "default";
 538                 pinctrl-0 = <&hsi2c1_bus>;
 539                 clocks = <&clock MUX_SHUB_I2C>, <&clock GATE_I2C_SHUB00_QCH>;
 540                 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
 541                 samsung,scl-clk-stretching;
 542                 samsung,usi-i2c-v2;
 543                 gpio_scl= <&gph0 2 0x1>;
 544                 gpio_sda= <&gph0 3 0x1>;
 545                 status = "disabled";
 546         };
 547
 548         /* USI_0_CMGP */
 549         hsi2c_2: hsi2c@11D00000 {
 550                 compatible = "samsung,exynos5-hsi2c";
 551                 samsung,check-transdone-int;
 552                 default-clk = <200000000>;
 553                 reg = <0x0 0x11D00000 0x1000>;
 554                 interrupts = <0 311 0>;
 555                 #address-cells = <1>;
 556                 #size-cells = <0>;
 557                 pinctrl-names = "default";
 558                 pinctrl-0 = <&hsi2c2_bus>;
 559                 clocks = <&clock CMGP00_USI>, <&clock GATE_USI_CMGP00_QCH>;
 560                 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
 561                 samsung,scl-clk-stretching;
 562                 samsung,usi-i2c-v2;
 563                 gpio_scl= <&gpm0 0 0x1>;
 564                 gpio_sda= <&gpm1 0 0x1>;
 565                 status = "disabled";
 566         };
 567
 568         /* USI_0_CMGP_I2C */
 569         hsi2c_3: hsi2c@11D10000 {
 570                 compatible = "samsung,exynos5-hsi2c";
 571                 samsung,check-transdone-int;
 572                 default-clk = <200000000>;
 573                 reg = <0x0 0x11D10000 0x1000>;
 574                 interrupts = <0 273 0>;
 575                 #address-cells = <1>;
 576                 #size-cells = <0>;
 577                 pinctrl-names = "default";
 578                 pinctrl-0 = <&hsi2c3_bus>;
 579                 clocks = <&clock CMGP_I2C>, <&clock GATE_I2C_CMGP00_QCH>;
 580                 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
 581                 samsung,scl-clk-stretching;
 582                 samsung,usi-i2c-v2;
 583                 gpio_scl= <&gpm2 0 0x1>;
 584                 gpio_sda= <&gpm3 0 0x1>;
 585                 status = "disabled";
 586         };
 587
 588         /* USI_1_CMGP */
 589         hsi2c_4: hsi2c@11D20000 {
 590                 compatible = "samsung,exynos5-hsi2c";
 591                 samsung,check-transdone-int;
 592                 default-clk = <200000000>;
 593                 reg = <0x0 0x11D20000 0x1000>;
 594                 interrupts = <0 312 0>;
 595                 #address-cells = <1>;
 596                 #size-cells = <0>;
 597                 pinctrl-names = "default";
 598                 pinctrl-0 = <&hsi2c4_bus>;
 599                 clocks = <&clock CMGP01_USI>, <&clock GATE_USI_CMGP01_QCH>;
 600                 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
 601                 samsung,scl-clk-stretching;
 602                 samsung,usi-i2c-v2;
 603                 gpio_scl= <&gpm4 0 0x1>;
 604                 gpio_sda= <&gpm5 0 0x1>;
 605                 status = "disabled";
 606         };
 607
 608         /* USI_1_CMGP_I2C */
 609         hsi2c_5: hsi2c@11D30000 {
 610                 compatible = "samsung,exynos5-hsi2c";
 611                 samsung,check-transdone-int;
 612                 default-clk = <200000000>;
 613                 reg = <0x0 0x11D30000 0x1000>;
 614                 interrupts = <0 274 0>;
 615                 #address-cells = <1>;
 616                 #size-cells = <0>;
 617                 pinctrl-names = "default";
 618                 pinctrl-0 = <&hsi2c5_bus>;
 619                 clocks = <&clock CMGP_I2C>, <&clock GATE_I2C_CMGP01_QCH>;
 620                 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
 621                 samsung,scl-clk-stretching;
 622                 samsung,usi-i2c-v2;
 623                 gpio_scl= <&gpm6 0 0x1>;
 624                 gpio_sda= <&gpm7 0 0x1>;
 625                 status = "disabled";
 626         };
 627
 628         /* USI_2_CMGP */
 629         hsi2c_6: hsi2c@11D40000 {
 630                 compatible = "samsung,exynos5-hsi2c";
 631                 samsung,check-transdone-int;
 632                 default-clk = <200000000>;
 633                 reg = <0x0 0x11D40000 0x1000>;
 634                 interrupts = <0 313 0>;
 635                 #address-cells = <1>;
 636                 #size-cells = <0>;
 637                 pinctrl-names = "default";
 638                 pinctrl-0 = <&hsi2c6_bus>;
 639                 clocks = <&clock CMGP02_USI>, <&clock GATE_USI_CMGP02_QCH>;
 640                 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
 641                 samsung,scl-clk-stretching;
 642                 samsung,usi-i2c-v2;
 643                 gpio_scl= <&gpm8 0 0x1>;
 644                 gpio_sda= <&gpm9 0 0x1>;
 645                 status = "disabled";
 646         };
 647
 648         /* USI_2_CMGP_I2C */
 649         hsi2c_7: hsi2c@11D50000 {
 650                 compatible = "samsung,exynos5-hsi2c";
 651                 samsung,check-transdone-int;
 652                 default-clk = <200000000>;
 653                 reg = <0x0 0x11D50000 0x1000>;
 654                 interrupts = <0 275 0>;
 655                 #address-cells = <1>;
 656                 #size-cells = <0>;
 657                 pinctrl-names = "default";
 658                 pinctrl-0 = <&hsi2c7_bus>;
 659                 clocks = <&clock CMGP_I2C>, <&clock GATE_I2C_CMGP02_QCH>;
 660                 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
 661                 samsung,scl-clk-stretching;
 662                 samsung,usi-i2c-v2;
 663                 gpio_scl= <&gpm10 0 0x1>;
 664                 gpio_sda= <&gpm11 0 0x1>;
 665                 status = "disabled";
 666         };
 667
 668         /* USI_3_CMGP */
 669         hsi2c_8: hsi2c@11D60000 {
 670                 compatible = "samsung,exynos5-hsi2c";
 671                 samsung,check-transdone-int;
 672                 default-clk = <200000000>;
 673                 reg = <0x0 0x11D60000 0x1000>;
 674                 interrupts = <0 314 0>;
 675                 #address-cells = <1>;
 676                 #size-cells = <0>;
 677                 pinctrl-names = "default";
 678                 pinctrl-0 = <&hsi2c8_bus>;
 679                 clocks = <&clock CMGP03_USI>, <&clock GATE_USI_CMGP03_QCH>;
 680                 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
 681                 samsung,scl-clk-stretching;
 682                 samsung,usi-i2c-v2;
 683                 gpio_scl= <&gpm12 0 0x1>;
 684                 gpio_sda= <&gpm13 0 0x1>;
 685                 status = "disabled";
 686         };
 687
 688         /* USI_3_CMGP_I2C */
 689         hsi2c_9: hsi2c@11D70000 {
 690                 compatible = "samsung,exynos5-hsi2c";
 691                 samsung,check-transdone-int;
 692                 default-clk = <200000000>;
 693                 reg = <0x0 0x11D70000 0x1000>;
 694                 interrupts = <0 276 0>;
 695                 #address-cells = <1>;
 696                 #size-cells = <0>;
 697                 pinctrl-names = "default";
 698                 pinctrl-0 = <&hsi2c9_bus>;
 699                 clocks = <&clock CMGP_I2C>, <&clock GATE_I2C_CMGP03_QCH>;
 700                 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
 701                 samsung,scl-clk-stretching;
 702                 samsung,usi-i2c-v2;
 703                 gpio_scl= <&gpm14 0 0x1>;
 704                 gpio_sda= <&gpm15 0 0x1>;
 705                 status = "disabled";
 706         };
 707
 708         /* USI_4_CMGP */
 709         hsi2c_10: hsi2c@11D80000 {
 710                 compatible = "samsung,exynos5-hsi2c";
 711                 samsung,check-transdone-int;
 712                 default-clk = <200000000>;
 713                 reg = <0x0 0x11D80000 0x1000>;
 714                 interrupts = <0 315 0>;
 715                 #address-cells = <1>;
 716                 #size-cells = <0>;
 717                 pinctrl-names = "default";
 718                 pinctrl-0 = <&hsi2c10_bus>;
 719                 clocks = <&clock CMGP04_USI>, <&clock GATE_USI_CMGP04_QCH>;
 720                 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
 721                 samsung,scl-clk-stretching;
 722                 samsung,usi-i2c-v2;
 723                 gpio_scl= <&gpm16 0 0x1>;
 724                 gpio_sda= <&gpm17 0 0x1>;
 725                 status = "disabled";
 726         };
 727
 728         /* USI_4_CMGP_I2C */
 729         hsi2c_11: hsi2c@11D90000 {
 730                 compatible = "samsung,exynos5-hsi2c";
 731                 samsung,check-transdone-int;
 732                 default-clk = <200000000>;
 733                 reg = <0x0 0x11D90000 0x1000>;
 734                 interrupts = <0 277 0>;
 735                 #address-cells = <1>;
 736                 #size-cells = <0>;
 737                 pinctrl-names = "default";
 738                 pinctrl-0 = <&hsi2c11_bus>;
 739                 clocks = <&clock CMGP_I2C>, <&clock GATE_I2C_CMGP04_QCH>;
 740                 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
 741                 samsung,scl-clk-stretching;
 742                 samsung,usi-i2c-v2;
 743                 gpio_scl= <&gpm18 0 0x1>;
 744                 gpio_sda= <&gpm19 0 0x1>;
 745                 status = "disabled";
 746         };
 747
 748         /* USI_PERI_CAMI2C_0 */
 749         hsi2c_12: hsi2c@138A0000 {
 750                 compatible = "samsung,exynos5-hsi2c";
 751                 samsung,check-transdone-int;
 752                 default-clk = <200000000>;
 753                 reg = <0x0 0x138A0000 0x1000>;
 754                 interrupts = <0 257 0>;
 755                 #address-cells = <1>;
 756                 #size-cells = <0>;
 757                 pinctrl-names = "default";
 758                 pinctrl-0 = <&hsi2c12_bus>;
 759                 clocks = <&clock I2C>, <&clock GATE_CAMI2C_0_QCH>;
 760                 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
 761                 samsung,scl-clk-stretching;
 762                 samsung,usi-i2c-v2;
 763                 gpio_scl= <&gpc0 1 0x1>;
 764                 gpio_sda= <&gpc0 0 0x1>;
 765                 status = "disabled";
 766         };
 767
 768         /* USI_PERI_CAMI2C_1 */
 769         hsi2c_13: hsi2c@138B0000 {
 770                 compatible = "samsung,exynos5-hsi2c";
 771                 samsung,check-transdone-int;
 772                 default-clk = <200000000>;
 773                 reg = <0x0 0x138B0000 0x1000>;
 774                 interrupts = <0 258 0>;
 775                 #address-cells = <1>;
 776                 #size-cells = <0>;
 777                 pinctrl-names = "default";
 778                 pinctrl-0 = <&hsi2c13_bus>;
 779                 clocks = <&clock I2C>, <&clock GATE_CAMI2C_1_QCH>;
 780                 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
 781                 samsung,scl-clk-stretching;
 782                 samsung,usi-i2c-v2;
 783                 gpio_scl= <&gpc0 3 0x1>;
 784                 gpio_sda= <&gpc0 2 0x1>;
 785                 status = "disabled";
 786         };
 787
 788         /* USI_PERI_CAMI2C_2 */
 789         hsi2c_14: hsi2c@138C0000 {
 790                 compatible = "samsung,exynos5-hsi2c";
 791                 samsung,check-transdone-int;
 792                 default-clk = <200000000>;
 793                 reg = <0x0 0x138C0000 0x1000>;
 794                 interrupts = <0 259 0>;
 795                 #address-cells = <1>;
 796                 #size-cells = <0>;
 797                 pinctrl-names = "default";
 798                 pinctrl-0 = <&hsi2c14_bus>;
 799                 clocks = <&clock I2C>, <&clock GATE_CAMI2C_2_QCH>;
 800                 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
 801                 samsung,scl-clk-stretching;
 802                 samsung,usi-i2c-v2;
 803                 gpio_scl= <&gpc0 5 0x1>;
 804                 gpio_sda= <&gpc0 4 0x1>;
 805                 status = "disabled";
 806         };
 807
 808         /* USI_PERI_CAMI2C_3 */
 809         hsi2c_15: hsi2c@138D0000 {
 810                 compatible = "samsung,exynos5-hsi2c";
 811                 samsung,check-transdone-int;
 812                 default-clk = <200000000>;
 813                 reg = <0x0 0x138D0000 0x1000>;
 814                 interrupts = <0 260 0>;
 815                 #address-cells = <1>;
 816                 #size-cells = <0>;
 817                 pinctrl-names = "default";
 818                 pinctrl-0 = <&hsi2c15_bus>;
 819                 clocks = <&clock I2C>, <&clock GATE_CAMI2C_3_QCH>;
 820                 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
 821                 samsung,scl-clk-stretching;
 822                 samsung,usi-i2c-v2;
 823                 gpio_scl= <&gpc0 7 0x1>;
 824                 gpio_sda= <&gpc0 6 0x1>;
 825                 status = "disabled";
 826         };
 827
 828         /* USI_PERI_USI_0 */
 829         hsi2c_16: hsi2c@13920000 {
 830                 compatible = "samsung,exynos5-hsi2c";
 831                 samsung,check-transdone-int;
 832                 default-clk = <200000000>;
 833                 reg = <0x0 0x13920000 0x1000>;
 834                 interrupts = <0 267 0>;
 835                 #address-cells = <1>;
 836                 #size-cells = <0>;
 837                 pinctrl-names = "default";
 838                 pinctrl-0 = <&hsi2c16_bus>;
 839                 clocks = <&clock USI_USI>, <&clock GATE_USI00_USI_QCH>;
 840                 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
 841                 samsung,scl-clk-stretching;
 842                 samsung,usi-i2c-v2;
 843                 gpio_scl= <&gpc1 0 0x1>;
 844                 gpio_sda= <&gpc1 1 0x1>;
 845                 status = "disabled";
 846         };
 847
 848         /* USI_PERI_USI_0_I2C */
 849         hsi2c_17: hsi2c@13930000 {
 850                 compatible = "samsung,exynos5-hsi2c";
 851                 samsung,check-transdone-int;
 852                 default-clk = <200000000>;
 853                 reg = <0x0 0x13930000 0x1000>;
 854                 interrupts = <0 268 0>;
 855                 #address-cells = <1>;
 856                 #size-cells = <0>;
 857                 pinctrl-names = "default";
 858                 pinctrl-0 = <&hsi2c17_bus>;
 859                 clocks = <&clock USI_I2C>, <&clock GATE_USI00_I2C_QCH>;
 860                 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
 861                 samsung,scl-clk-stretching;
 862                 samsung,usi-i2c-v2;
 863                 gpio_scl= <&gpc1 2 0x1>;
 864                 gpio_sda= <&gpc1 3 0x1>;
 865                 status = "disabled";
 866         };
 867
 868         /* USI_0_SHUB */
 869         spi_0: spi@110C0000 {
 870                 compatible = "samsung,exynos-spi";
 871                 reg = <0x0 0x110C0000 0x100>;
 872                 samsung,spi-fifosize = <64>;
 873                 interrupts = <0 112 0>;
 874 /*
 875                 dma-mode;
 876                 dmas = <&pdma0 25 &pdma0 24>;
 877 */
 878                 dma-names = "tx", "rx";
 879                 swap-mode;
 880                 #address-cells = <1>;
 881                 #size-cells = <0>;
 882                 clocks = <&clock GATE_USI_SHUB00_QCH>, <&clock MUX_SHUB_USI00>;
 883                 clock-names = "gate_spi_clk", "ipclk_spi0";
 884                 pinctrl-names = "default";
 885                 pinctrl-0 = <&spi0_bus>;
 886                 status = "disabled";
 887         };
 888
 889         /* USI_0_CMGP */
 890         spi_1: spi@11D00000 {
 891                 compatible = "samsung,exynos-spi";
 892                 reg = <0x0 0x11D00000 0x100>;
 893                 samsung,spi-fifosize = <64>;
 894                 interrupts = <0 311 0>;
 895 /*
 896                 dma-mode;
 897                 dmas = <&pdma0 25 &pdma0 24>;
 898 */
 899                 dma-names = "tx", "rx";
 900                 swap-mode;
 901                 #address-cells = <1>;
 902                 #size-cells = <0>;
 903                 clocks = <&clock GATE_USI_CMGP00_QCH>, <&clock CMGP00_USI>;
 904                 clock-names = "gate_spi_clk", "ipclk_spi0";
 905                 pinctrl-names = "default";
 906                 pinctrl-0 = <&spi1_bus>;
 907                 status = "disabled";
 908         };
 909
 910         /* USI_1_CMGP */
 911         spi_2: spi@11D20000 {
 912                 compatible = "samsung,exynos-spi";
 913                 reg = <0x0 0x11D20000 0x100>;
 914                 samsung,spi-fifosize = <64>;
 915                 interrupts = <0 312 0>;
 916 /*
 917                 dma-mode;
 918                 dmas = <&pdma0 25 &pdma0 24>;
 919 */
 920                 dma-names = "tx", "rx";
 921                 swap-mode;
 922                 #address-cells = <1>;
 923                 #size-cells = <0>;
 924                 clocks = <&clock GATE_USI_CMGP01_QCH>, <&clock CMGP01_USI>;
 925                 clock-names = "gate_spi_clk", "ipclk_spi0";
 926                 pinctrl-names = "default";
 927                 pinctrl-0 = <&spi2_bus>;
 928                 status = "disabled";
 929         };
 930
 931         /* USI_2_CMGP */
 932         spi_3: spi@11D40000 {
 933                 compatible = "samsung,exynos-spi";
 934                 reg = <0x0 0x11D40000 0x100>;
 935                 samsung,spi-fifosize = <64>;
 936                 interrupts = <0 313 0>;
 937 /*
 938                 dma-mode;
 939                 dmas = <&pdma0 25 &pdma0 24>;
 940 */
 941                 dma-names = "tx", "rx";
 942                 swap-mode;
 943                 #address-cells = <1>;
 944                 #size-cells = <0>;
 945                 clocks = <&clock GATE_USI_CMGP02_QCH>, <&clock CMGP02_USI>;
 946                 clock-names = "gate_spi_clk", "ipclk_spi0";
 947                 pinctrl-names = "default";
 948                 pinctrl-0 = <&spi3_bus>;
 949                 status = "disabled";
 950         };
 951
 952         /* USI_3_CMGP */
 953         spi_4: spi@11D60000 {
 954                 compatible = "samsung,exynos-spi";
 955                 reg = <0x0 0x11D60000 0x100>;
 956                 samsung,spi-fifosize = <64>;
 957                 interrupts = <0 314 0>;
 958 /*
 959                 dma-mode;
 960                 dmas = <&pdma0 25 &pdma0 24>;
 961 */
 962                 dma-names = "tx", "rx";
 963                 swap-mode;
 964                 #address-cells = <1>;
 965                 #size-cells = <0>;
 966                 clocks = <&clock GATE_USI_CMGP03_QCH>, <&clock CMGP03_USI>;
 967                 clock-names = "gate_spi_clk", "ipclk_spi0";
 968                 pinctrl-names = "default";
 969                 pinctrl-0 = <&spi4_bus>;
 970                 status = "disabled";
 971         };
 972
 973         /* USI_4_CMGP */
 974         spi_5: spi@11D80000 {
 975                 compatible = "samsung,exynos-spi";
 976                 reg = <0x0 0x11D80000 0x100>;
 977                 samsung,spi-fifosize = <64>;
 978                 interrupts = <0 315 0>;
 979 /*
 980                 dma-mode;
 981                 dmas = <&pdma0 25 &pdma0 24>;
 982 */
 983                 dma-names = "tx", "rx";
 984                 swap-mode;
 985                 #address-cells = <1>;
 986                 #size-cells = <0>;
 987                 clocks = <&clock GATE_USI_CMGP04_QCH>, <&clock CMGP04_USI>;
 988                 clock-names = "gate_spi_clk", "ipclk_spi0";
 989                 pinctrl-names = "default";
 990                 pinctrl-0 = <&spi5_bus>;
 991                 status = "disabled";
 992         };
 993
 994         /* USI_PERI_SPI_0  */
 995         spi_6: spi@13900000 {
 996                 compatible = "samsung,exynos-spi";
 997                 reg = <0x0 0x13900000 0x100>;
 998                 samsung,spi-fifosize = <64>;
 999                 interrupts = <0 254 0>;
1000 /*
1001                 dma-mode;
1002                 dmas = <&pdma0 19 &pdma0 18>;
1003 */
1004                 dma-names = "tx", "rx";
1005                 swap-mode;
1006                 #address-cells = <1>;
1007                 #size-cells = <0>;
1008                 clocks = <&clock GATE_SPI_0_QCH>, <&clock SPI0>;
1009                 clock-names = "gate_spi_clk", "ipclk_spi0";
1010                 pinctrl-names = "default";
1011                 pinctrl-0 = <&spi6_bus>;
1012                 status = "disabled";
1013         };
1014
1015         /* USI_PERI_SPI_1  */
1016         spi_7: spi@13910000 {
1017                 compatible = "samsung,exynos-spi";
1018                 reg = <0x0 0x13910000 0x100>;
1019                 samsung,spi-fifosize = <64>;
1020                 interrupts = <0 255 0>;
1021 /*
1022                 dma-mode;
1023                 dmas = <&pdma0 21 &pdma0 20>;
1024 */
1025                 dma-names = "tx", "rx";
1026                 swap-mode;
1027                 #address-cells = <1>;
1028                 #size-cells = <0>;
1029                 clocks = <&clock GATE_SPI_1_QCH>, <&clock SPI1>;
1030                 clock-names = "gate_spi_clk", "ipclk_spi0";
1031                 pinctrl-names = "default";
1032                 pinctrl-0 = <&spi7_bus>;
1033                 status = "disabled";
1034         };
1035
1036         /* USI_PERI_USI_0 */
1037         spi_8: spi@13920000 {
1038                 compatible = "samsung,exynos-spi";
1039                 reg = <0x0 0x13920000 0x100>;
1040                 samsung,spi-fifosize = <64>;
1041                 interrupts = <0 267 0>;
1042 /*
1043                 dma-mode;
1044                 dmas = <&pdma0 25 &pdma0 24>;
1045 */
1046                 dma-names = "tx", "rx";
1047                 swap-mode;
1048                 #address-cells = <1>;
1049                 #size-cells = <0>;
1050                 clocks = <&clock GATE_USI00_USI_QCH>, <&clock USI_USI>;
1051                 clock-names = "gate_spi_clk", "ipclk_spi0";
1052                 pinctrl-names = "default";
1053                 pinctrl-0 = <&spi8_bus>;
1054                 status = "disabled";
1055         };
1056
1057         /* SPI USI_PERI_SPI_2 */
1058         spi_9: spi@13940000 {
1059                 compatible = "samsung,exynos-spi";
1060                 reg = <0x0 0x13940000 0x100>;
1061                 samsung,spi-fifosize = <256>;
1062                 interrupts = <0 256 0>;
1063 /*
1064                 dma-mode;
1065                 dmas = <&pdma0 23 &pdma0 22>;
1066 */
1067                 dma-names = "tx", "rx";
1068                 swap-mode;
1069                 #address-cells = <1>;
1070                 #size-cells = <0>;
1071                 clocks = <&clock GATE_SPI_2_QCH>, <&clock SPI2>;
1072                 clock-names = "gate_spi_clk", "ipclk_spi0";
1073                 pinctrl-names = "default";
1074                 pinctrl-0 = <&spi9_bus>;
1075                 status = "disabled";
1076         };
1077
1078         /* USI_PERI_UART */
1079         serial_0: uart@13820000 {
1080                 compatible = "samsung,exynos-uart";
1081                 samsung,separate-uart-clk;
1082                 reg = <0x0 0x13820000 0x100>;
1083                 samsung,fifo-size = <256>;
1084                 interrupts = <0 246 0>;
1085                 pinctrl-names = "default";
1086                 pinctrl-0 = <&uart0_bus>; /* or _bus_dual */
1087                 samsung,usi-serial-v2;
1088                 clocks = <&clock GATE_UART_QCH>, <&clock UART>;
1089                 clock-names = "gate_uart_clk0", "ipclk_uart0";
1090                 status = "disabled";
1091         };
1092
1093         /* USI_0_SHUB */
1094         serial_1: uart@110C0000 {
1095                 compatible = "samsung,exynos-uart";
1096                 samsung,separate-uart-clk;
1097                 reg = <0x0 0x110C0000 0x100>;
1098                 samsung,fifo-size = <64>;
1099                 interrupts = <0 112 0>;
1100                 pinctrl-names = "default";
1101                 pinctrl-0 = <&uart1_bus_single>; /* or _bus_dual */
1102                 samsung,usi-serial-v2;
1103                 clocks = <&clock GATE_USI_SHUB00_QCH>, <&clock MUX_SHUB_USI00>;
1104                 clock-names = "gate_uart_clk1", "ipclk_uart1";
1105                 status = "disabled";
1106         };
1107
1108         /* USI_0_CMGP */
1109         serial_2: uart@11D00000 {
1110                 compatible = "samsung,exynos-uart";
1111                 samsung,separate-uart-clk;
1112                 reg = <0x0 0x11D00000 0x100>;
1113                 samsung,fifo-size = <64>;
1114                 interrupts = <0 311 0>;
1115                 pinctrl-names = "default";
1116                 pinctrl-0 = <&uart2_bus_single>; /* or _bus_dual */
1117                 samsung,usi-serial-v2;
1118                 clocks = <&clock GATE_USI_CMGP00_QCH>, <&clock CMGP00_USI>;
1119                 clock-names = "gate_uart_clk2", "ipclk_uart2";
1120                 status = "disabled";
1121         };
1122
1123         /* USI_1_CMGP */
1124         serial_3: uart@11D20000 {
1125                 compatible = "samsung,exynos-uart";
1126                 samsung,separate-uart-clk;
1127                 reg = <0x0 0x11D20000 0x100>;
1128                 samsung,fifo-size = <64>;
1129                 interrupts = <0 312 0>;
1130                 pinctrl-names = "default";
1131                 pinctrl-0 = <&uart3_bus_single>; /* or _bus_dual */
1132                 samsung,usi-serial-v2;
1133                 clocks = <&clock GATE_USI_CMGP01_QCH>, <&clock CMGP01_USI>;
1134                 clock-names = "gate_uart_clk3", "ipclk_uart3";
1135                 status = "disabled";
1136         };
1137
1138         /* USI_2_CMGP */
1139         serial_4: uart@11D40000 {
1140                 compatible = "samsung,exynos-uart";
1141                 samsung,separate-uart-clk;
1142                 reg = <0x0 0x11D40000 0x100>;
1143                 samsung,fifo-size = <64>;
1144                 interrupts = <0 313 0>;
1145                 pinctrl-names = "default";
1146                 pinctrl-0 = <&uart4_bus_single>; /* or _bus_dual */
1147                 samsung,usi-serial-v2;
1148                 clocks = <&clock GATE_USI_CMGP02_QCH>, <&clock CMGP02_USI>;
1149                 clock-names = "gate_uart_clk4", "ipclk_uart4";
1150                 status = "disabled";
1151         };
1152
1153         /* USI_3_CMGP */
1154         serial_5: uart@11D60000 {
1155                 compatible = "samsung,exynos-uart";
1156                 samsung,separate-uart-clk;
1157                 reg = <0x0 0x11D60000 0x100>;
1158                 samsung,fifo-size = <64>;
1159                 interrupts = <0 314 0>;
1160                 pinctrl-names = "default";
1161                 pinctrl-0 = <&uart5_bus_single>; /* or _bus_dual */
1162                 samsung,usi-serial-v2;
1163                 clocks = <&clock GATE_USI_CMGP03_QCH>, <&clock CMGP03_USI>;
1164                 clock-names = "gate_uart_clk5", "ipclk_uart5";
1165                 status = "disabled";
1166         };
1167
1168         /* USI_4_CMGP */
1169         serial_6: uart@11D80000 {
1170                 compatible = "samsung,exynos-uart";
1171                 samsung,separate-uart-clk;
1172                 reg = <0x0 0x11D80000 0x100>;
1173                 samsung,fifo-size = <64>;
1174                 interrupts = <0 315 0>;
1175                 pinctrl-names = "default";
1176                 pinctrl-0 = <&uart6_bus_single>; /* or _bus_dual */
1177                 samsung,usi-serial-v2;
1178                 clocks = <&clock GATE_USI_CMGP04_QCH>, <&clock CMGP04_USI>;
1179                 clock-names = "gate_uart_clk6", "ipclk_uart6";
1180                 status = "disabled";
1181         };
1182
1183         /* USI_PERI_USI_0 */
1184         serial_7: uart@13920000 {
1185                 compatible = "samsung,exynos-uart";
1186                 samsung,separate-uart-clk;
1187                 reg = <0x0 0x13920000 0x100>;
1188                 samsung,fifo-size = <64>;
1189                 interrupts = <0 267 0>;
1190                 pinctrl-names = "default";
1191                 pinctrl-0 = <&uart7_bus_single>; /* or _bus_dual */
1192                 samsung,usi-serial-v2;
1193                 clocks = <&clock GATE_USI00_USI_QCH>, <&clock USI_USI>;
1194                 clock-names = "gate_uart_clk7", "ipclk_uart7";
1195                 status = "disabled";
1196         };
1197
1198         /* I2C_0 */
1199         i2c_0: i2c@13830000 {
1200                 compatible = "samsung,s3c2440-i2c";
1201                 reg = <0x0 0x13830000 0x100>;
1202                 interrupts = <0 247 0>;
1203                 #address-cells = <1>;
1204                 #size-cells = <0>;
1205                 pinctrl-names = "default";
1206                 pinctrl-0 = <&i2c0_bus>;
1207                 clocks = <&clock GATE_I2C_0_QCH>, <&clock GATE_I2C_0_QCH>;
1208                 clock-names = "rate_i2c", "gate_i2c";
1209                 status = "disabled";
1210         };
1211
1212         /* I2C_1 */
1213         i2c_1: i2c@13840000 {
1214                 compatible = "samsung,s3c2440-i2c";
1215                 reg = <0x0 0x13840000 0x100>;
1216                 interrupts = <0 248 0>;
1217                 #address-cells = <1>;
1218                 #size-cells = <0>;
1219                 pinctrl-names = "default";
1220                 pinctrl-0 = <&i2c1_bus>;
1221                 clocks = <&clock GATE_I2C_1_QCH>, <&clock GATE_I2C_1_QCH>;
1222                 clock-names = "rate_i2c", "gate_i2c";
1223                 status = "disabled";
1224         };
1225
1226         /* I2C_2 */
1227         i2c_2: i2c@13850000 {
1228                 compatible = "samsung,s3c2440-i2c";
1229                 reg = <0x0 0x13850000 0x100>;
1230                 interrupts = <0 249 0>;
1231                 #address-cells = <1>;
1232                 #size-cells = <0>;
1233                 pinctrl-names = "default";
1234                 pinctrl-0 = <&i2c2_bus>;
1235                 clocks = <&clock GATE_I2C_2_QCH>, <&clock GATE_I2C_2_QCH>;
1236                 clock-names = "rate_i2c", "gate_i2c";
1237                 status = "disabled";
1238         };
1239
1240         /* I2C_3 */
1241         i2c_3: i2c@13860000 {
1242                 compatible = "samsung,s3c2440-i2c";
1243                 reg = <0x0 0x13860000 0x100>;
1244                 interrupts = <0 250 0>;
1245                 #address-cells = <1>;
1246                 #size-cells = <0>;
1247                 pinctrl-names = "default";
1248                 pinctrl-0 = <&i2c3_bus>;
1249                 clocks = <&clock GATE_I2C_3_QCH>, <&clock GATE_I2C_3_QCH>;
1250                 clock-names = "rate_i2c", "gate_i2c";
1251                 status = "disabled";
1252         };
1253
1254         /* I2C_4 */
1255         i2c_4: i2c@13870000 {
1256                 compatible = "samsung,s3c2440-i2c";
1257                 reg = <0x0 0x13870000 0x100>;
1258                 interrupts = <0 251 0>;
1259                 #address-cells = <1>;
1260                 #size-cells = <0>;
1261                 pinctrl-names = "default";
1262                 pinctrl-0 = <&i2c4_bus>;
1263                 clocks = <&clock GATE_I2C_4_QCH>, <&clock GATE_I2C_4_QCH>;
1264                 clock-names = "rate_i2c", "gate_i2c";
1265                 status = "disabled";
1266         };
1267
1268         /* I2C_5 */
1269         i2c_5: i2c@13880000 {
1270                 compatible = "samsung,s3c2440-i2c";
1271                 reg = <0x0 0x13880000 0x100>;
1272                 interrupts = <0 252 0>;
1273                 #address-cells = <1>;
1274                 #size-cells = <0>;
1275                 pinctrl-names = "default";
1276                 pinctrl-0 = <&i2c5_bus>;
1277                 clocks = <&clock GATE_I2C_5_QCH>, <&clock GATE_I2C_5_QCH>;
1278                 clock-names = "rate_i2c", "gate_i2c";
1279                 status = "disabled";
1280         };
1281
1282         /* I2C_6 */
1283         i2c_6: i2c@13890000 {
1284                 compatible = "samsung,s3c2440-i2c";
1285                 reg = <0x0 0x13890000 0x100>;
1286                 interrupts = <0 253 0>;
1287                 #address-cells = <1>;
1288                 #size-cells = <0>;
1289                 pinctrl-names = "default";
1290                 pinctrl-0 = <&i2c6_bus>;
1291                 clocks = <&clock GATE_I2C_6_QCH>, <&clock GATE_I2C_6_QCH>;
1292                 clock-names = "rate_i2c", "gate_i2c";
1293                 status = "disabled";
1294         };
1295
1296         ufs: ufs@0x13520000 {
1297                 /* ----------------------- */
1298                 /* 1. SYSTEM CONFIGURATION */
1299                 /* ----------------------- */
1300                 compatible ="samsung,exynos-ufs";
1301                 #address-cells = <2>;
1302                 #size-cells = <1>;
1303                 ranges;
1304                 reg =
1305                         <0x0 0x13520000 0x200>, /* 0: HCI standard */
1306                         <0x0 0x13521100 0x200>, /* 1: Vendor specificed */
1307                         <0x0 0x13510000 0x8000>,        /* 2: UNIPRO */
1308                         <0x0 0x13530000 0x100>; /* 3: UFS protector */
1309                 interrupts = <0 157 0>;
1310                 pinctrl-names = "default";
1311                 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
1312                 clocks =
1313                         /* aclk clock */
1314                         <&clock GATE_UFS_EMBD_QCH_UFS>,
1315                         /* unipro clocks */
1316                         <&clock UFS_EMBD>;
1317
1318                 clock-names =
1319                         /* aclk clocks */
1320                         "GATE_UFS_EMBD_QCH_UFS",
1321                         /* unipro clocks */
1322                         "UFS_EMBD";
1323
1324                 /* PM QoS for INT power domain */
1325 /*              ufs-pm-qos-int = <400000>;*/
1326
1327                 /* DMA coherent callback, should be coupled with 'ufs-sys' */
1328                 dma-coherent;
1329
1330                 /* UFS PHY isolation and TCXO control */
1331                 samsung,pmu-phandle = <&pmu_system_controller>;
1332
1333                 /* TCXO exclusive control  */
1334                 tcxo-ex-ctrl = <0>;
1335
1336                 /* UFS IO coherency  */
1337                 samsung,sysreg-fsys-phandle = <&sysreg_fsys_system_controller>;
1338
1339                 /* ----------------------- */
1340                 /* 2. UFS COMMON           */
1341                 /* ----------------------- */
1342                 freq-table-hz = <0 0>, <0 0>;
1343
1344                 vcc-supply = <&ufs_fixed_vcc>;
1345                 vcc-fixed-regulator;
1346
1347
1348                 /* ----------------------- */
1349                 /* 3. UFS EXYNOS           */
1350                 /* ----------------------- */
1351                 hw-rev = <UFS_VER_0005>;
1352
1353                 /* power mode change */
1354                 ufs,pmd-attr-lane = /bits/ 8 <1>;
1355                 ufs,pmd-attr-gear = /bits/ 8 <3>;
1356
1357                 /* hiberantion */
1358                 ufs-rx-min-activate-time-cap = <3>;
1359                 ufs-rx-hibern8-time-cap = <2>;
1360                 ufs-tx-hibern8-time-cap = <2>;
1361
1362                 /* board type for UFS CAL */
1363                 brd-for-cal = <0>;
1364
1365                 fmp-id = <0>;
1366                 smu-id = <0>;
1367
1368                 /* ----------------------- */
1369                 /* 4. ADDITIONAL NODES     */
1370                 /* ----------------------- */
1371                 ufs-phy {
1372                         #address-cells = <2>;
1373                         #size-cells = <1>;
1374                         ranges;
1375                         reg = <0x0 0x13524000 0x800>;
1376                 };
1377
1378                 ufs-dma-coherency {
1379                         #address-cells = <2>;
1380                         #size-cells = <1>;
1381
1382                         offset = <0x1010>;
1383                         mask = <(BIT_8 | BIT_9)>;
1384                         val = <(BIT_8 | BIT_9)>;
1385                 };
1386         };
1387
1388         ufs_fixed_vcc: fixedregulator@0 {
1389                        compatible = "regulator-fixed";
1390                        regulator-name = "ufs-vcc";
1391                        gpio = <&gpg4 0 0>;
1392                        regulator-boot-on;
1393                        enable-active-high;
1394         };
1395
1396         exynos-pmu {
1397                 compatible = "samsung,exynos-pmu";
1398                 samsung,syscon-phandle = <&pmu_system_controller>;
1399         };
1400
1401         pmu_system_controller: system-controller@11860000 {
1402                 compatible = "samsung,exynos9610-pmu", "syscon";
1403                 reg = <0x0 0x11860000 0x10000>;
1404         };
1405
1406         exynos-sysreg-fsys {
1407                 compatible = "samsung,exynos-sysreg-fsys";
1408                 samsung,syscon-phandle = <&sysreg_fsys_system_controller>;
1409         };
1410
1411         sysreg_fsys_system_controller: system-controller@13410000 {
1412                 compatible = "samsung,exynos9610-sysreg-fsys", "syscon";
1413                 reg = <0x0 0x13410000 0x1020>;
1414         };
1415
1416         /* DMA */
1417         amba {
1418                 #address-cells = <2>;
1419                 #size-cells = <1>;
1420                 compatible = "arm,amba-bus";
1421                 interrupt-parent = <&gic>;
1422                 ranges;
1423
1424                 pdma0: pdma0@120C0000 {
1425                         compatible = "arm,pl330", "arm,primecell";
1426                         reg = <0x0 0x120C0000 0x1000>;
1427                         interrupts = <0 294 0>;
1428                         clocks = <&clock GATE_PDMA_CORE_QCH>;
1429                         clock-names = "apb_pclk";
1430                         #dma-cells = <1>;
1431                         #dma-channels = <8>;
1432                         #dma-requests = <32>;
1433                         #dma-multi-irq = <1>;
1434                         dma-arwrapper = <0x120C4400>,
1435                                         <0x120C4420>,
1436                                         <0x120C4440>,
1437                                         <0x120C4460>,
1438                                         <0x120C4480>,
1439                                         <0x120C44A0>,
1440                                         <0x120C44C0>,
1441                                         <0x120C44E0>;
1442                         dma-awwrapper = <0x120C4404>,
1443                                         <0x120C4424>,
1444                                         <0x120C4444>,
1445                                         <0x120C4464>,
1446                                         <0x120C4484>,
1447                                         <0x120C44A4>,
1448                                         <0x120C44C4>,
1449                                         <0x120C44E4>;
1450                         dma-instwrapper = <0x120C4500>;
1451                         dma-mask-bit = <36>;
1452                         coherent-mask-bit = <36>;
1453                 };
1454         };
1455
1456         watchdog_cl0@10050000 {
1457                 compatible = "samsung,exynos7-wdt";
1458                 reg = <0x0 0x10050000 0x100>;
1459                 interrupts = <0 232 0>;
1460                 clocks = <&clock OSCCLK>, <&clock GATE_WDT_CLUSTER0_QCH>;
1461                 clock-names = "rate_watchdog", "gate_watchdog";
1462                 timeout-sec = <30>;
1463                 samsung,syscon-phandle = <&pmu_system_controller>;
1464                 index = <0>; /* if little cluster then index is 0*/
1465         };
1466
1467         exynos_adc: adc@11C30000 {
1468                 compatible = "samsung,exynos-adc-v3";
1469                 reg = <0x0 0x11C30000 0x100>;
1470                 sysreg = <0x11C10000>;
1471                 interrupts = <0 271 0>;
1472                 #io-channel-cells = <1>;
1473                 io-channel-ranges;
1474                 clocks = <&clock GATE_ADC_CMGP_QCH_S0>;
1475                 clock-names = "gate_adcif";
1476         };
1477
1478         rtc@11A20000 {
1479                 compatible = "samsung,exynos8-rtc";
1480                 reg = <0x0 0x11A20000 0x100>;
1481                 interrupts = <0 29 0>, <0 30 0>;
1482                 use-chub-only;
1483         };
1484
1485         sec_pwm: pwm@13970000 {
1486                 compatible = "samsung,s3c6400-pwm";
1487                 reg = <0x0 0x13970000 0x1000>;
1488                 samsung,pwm-outputs = <0>, <1>, <2>, <3>, <4>;
1489                 #pwm-cells = <3>;
1490                 clocks = <&clock GATE_PWM_MOTOR_QCH>, <&clock OSCCLK>;
1491                 clock-names = "pwm_pclk", "pwm_sclk";
1492                 status = "ok";
1493         };
1494
1495         iommu-domain_dpu {
1496                 compatible = "samsung,exynos-iommu-bus";
1497                 #address-cells = <2>;
1498                 #size-cells = <1>;
1499                 ranges;
1500
1501                 domain-clients = <>;
1502         };
1503
1504         iommu-domain_vipx {
1505                 compatible = "samsung,exynos-iommu-bus";
1506                 #address-cells = <2>;
1507                 #size-cells = <1>;
1508                 ranges;
1509
1510                 domain-clients = <>;
1511         };
1512
1513         iommu-domain_abox {
1514                 compatible = "samsung,exynos-iommu-bus";
1515                 #address-cells = <2>;
1516                 #size-cells = <1>;
1517                 ranges;
1518
1519                 domain-clients = <>;
1520         };
1521
1522         iommu-domain_isp {
1523                 compatible = "samsung,exynos-iommu-bus";
1524                 #address-cells = <2>;
1525                 #size-cells = <1>;
1526                 ranges;
1527
1528                 domain-clients = <>;
1529         };
1530
1531         iommu-domain_mfc {
1532                 compatible = "samsung,exynos-iommu-bus";
1533                 #address-cells = <2>;
1534                 #size-cells = <1>;
1535                 ranges;
1536
1537                 domain-clients = <>;
1538         };
1539
1540         iommu-domain_g2dmscljpeg {
1541                 compatible = "samsung,exynos-iommu-bus";
1542                 #address-cells = <2>;
1543                 #size-cells = <1>;
1544                 ranges;
1545
1546                 domain-clients = <>;
1547         };
1548 };