drivers/net/wireless/bcmdhd_1_77/include/bcmdevs.h

   1 /*
   2  * Broadcom device-specific manifest constants.
   3  *
   4  * Copyright (C) 1999-2018, Broadcom Corporation
   5  *
   6  *      Unless you and Broadcom execute a separate written software license
   7  * agreement governing use of this software, this software is licensed to you
   8  * under the terms of the GNU General Public License version 2 (the "GPL"),
   9  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
  10  * following added to such license:
  11  *
  12  *      As a special exception, the copyright holders of this software give you
  13  * permission to link this software with independent modules, and to copy and
  14  * distribute the resulting executable under terms of your choice, provided that
  15  * you also meet, for each linked independent module, the terms and conditions of
  16  * the license of that module.  An independent module is a module which is not
  17  * derived from this software.  The special exception does not apply to any
  18  * modifications of the software.
  19  *
  20  *      Notwithstanding the above, under no circumstances may you combine this
  21  * software in any way with any other Broadcom software provided under a license
  22  * other than the GPL, without Broadcom's express prior written consent.
  23  *
  24  *
  25  * <<Broadcom-WL-IPTag/Open:>>
  26  *
  27  * $Id: bcmdevs.h 625027 2016-03-15 08:20:18Z $
  28  */
  29
  30 #ifndef _BCMDEVS_H
  31 #define _BCMDEVS_H
  32
  33 /* PCI vendor IDs */
  34 #define VENDOR_EPIGRAM          0xfeda
  35 #define VENDOR_BROADCOM         0x14e4
  36 #define VENDOR_3COM             0x10b7
  37 #define VENDOR_NETGEAR          0x1385
  38 #define VENDOR_DIAMOND          0x1092
  39 #define VENDOR_INTEL            0x8086
  40 #define VENDOR_DELL             0x1028
  41 #define VENDOR_HP               0x103c
  42 #define VENDOR_HP_COMPAQ        0x0e11
  43 #define VENDOR_APPLE            0x106b
  44 #define VENDOR_SI_IMAGE         0x1095          /* Silicon Image, used by Arasan SDIO Host */
  45 #define VENDOR_BUFFALO          0x1154          /* Buffalo vendor id */
  46 #define VENDOR_TI               0x104c          /* Texas Instruments */
  47 #define VENDOR_RICOH            0x1180          /* Ricoh */
  48 #define VENDOR_JMICRON          0x197b
  49
  50
  51 /* PCMCIA vendor IDs */
  52 #define VENDOR_BROADCOM_PCMCIA  0x02d0
  53
  54 /* SDIO vendor IDs */
  55 #define VENDOR_BROADCOM_SDIO    0x00BF
  56
  57 /* DONGLE VID/PIDs */
  58 #define BCM_DNGL_VID            0x0a5c
  59 #define BCM_DNGL_BL_PID_4328    0xbd12
  60 #define BCM_DNGL_BL_PID_4322    0xbd13
  61 #define BCM_DNGL_BL_PID_4319    0xbd16
  62 #define BCM_DNGL_BL_PID_43236   0xbd17
  63 #define BCM_DNGL_BL_PID_4332    0xbd18
  64 #define BCM_DNGL_BL_PID_4330    0xbd19
  65 #define BCM_DNGL_BL_PID_4334    0xbd1a
  66 #define BCM_DNGL_BL_PID_43239   0xbd1b
  67 #define BCM_DNGL_BL_PID_4324    0xbd1c
  68 #define BCM_DNGL_BL_PID_4360    0xbd1d
  69 #define BCM_DNGL_BL_PID_43143   0xbd1e
  70 #define BCM_DNGL_BL_PID_43242   0xbd1f
  71 #define BCM_DNGL_BL_PID_43342   0xbd21
  72 #define BCM_DNGL_BL_PID_4335    0xbd20
  73 #define BCM_DNGL_BL_PID_43341   0xbd22
  74 #define BCM_DNGL_BL_PID_4350    0xbd23
  75 #define BCM_DNGL_BL_PID_4345    0xbd24
  76 #define BCM_DNGL_BL_PID_4349    0xbd25
  77 #define BCM_DNGL_BL_PID_4354    0xbd26
  78 #define BCM_DNGL_BL_PID_43569   0xbd27
  79 #define BCM_DNGL_BL_PID_43909   0xbd28
  80 #define BCM_DNGL_BL_PID_4373    0xbd29
  81
  82 #define BCM_DNGL_BDC_PID        0x0bdc
  83 #define BCM_DNGL_JTAG_PID       0x4a44
  84
  85 /* HW USB BLOCK [CPULESS USB] PIDs */
  86 #define BCM_HWUSB_PID_43239     43239
  87
  88 /* PCI Device IDs */
  89 #ifdef DEPRECATED /* These products have been deprecated */
  90 #define BCM4210_DEVICE_ID       0x1072          /* never used */
  91 #define BCM4230_DEVICE_ID       0x1086          /* never used */
  92 #define BCM4401_ENET_ID         0x170c          /* 4401b0 production enet cards */
  93 #define BCM3352_DEVICE_ID       0x3352          /* bcm3352 device id */
  94 #define BCM3360_DEVICE_ID       0x3360          /* bcm3360 device id */
  95 #define BCM4211_DEVICE_ID       0x4211
  96 #define BCM4231_DEVICE_ID       0x4231
  97 #define BCM4303_D11B_ID         0x4303          /* 4303 802.11b */
  98 #define BCM4311_D11G_ID         0x4311          /* 4311 802.11b/g id */
  99 #define BCM4311_D11DUAL_ID      0x4312          /* 4311 802.11a/b/g id */
 100 #define BCM4311_D11A_ID         0x4313          /* 4311 802.11a id */
 101 #define BCM4328_D11DUAL_ID      0x4314          /* 4328/4312 802.11a/g id */
 102 #define BCM4328_D11G_ID         0x4315          /* 4328/4312 802.11g id */
 103 #define BCM4328_D11A_ID         0x4316          /* 4328/4312 802.11a id */
 104 #define BCM4318_D11A_ID         0x431a          /* 4318 802.11a id */
 105 #define BCM4325_D11DUAL_ID      0x431b          /* 4325 802.11a/g id */
 106 #define BCM4325_D11G_ID         0x431c          /* 4325 802.11g id */
 107 #define BCM4325_D11A_ID         0x431d          /* 4325 802.11a id */
 108 #define BCM4306_UART_ID         0x4322          /* 4306 uart */
 109 #define BCM4306_V90_ID          0x4323          /* 4306 v90 codec */
 110 #define BCM4306_D11G_ID2        0x4325          /* BCM4306_D11G_ID; INF w/loose binding war */
 111 #define BCM4321_D11N_ID         0x4328          /* 4321 802.11n dualband id */
 112 #define BCM4321_D11N2G_ID       0x4329          /* 4321 802.11n 2.4Ghz band id */
 113 #define BCM4321_D11N5G_ID       0x432a          /* 4321 802.11n 5Ghz band id */
 114 #define BCM4322_D11N_ID         0x432b          /* 4322 802.11n dualband device */
 115 #define BCM4322_D11N2G_ID       0x432c          /* 4322 802.11n 2.4GHz device */
 116 #define BCM4322_D11N5G_ID       0x432d          /* 4322 802.11n 5GHz device */
 117 #define BCM4329_D11N_ID         0x432e          /* 4329 802.11n dualband device */
 118 #define BCM4329_D11N2G_ID       0x432f          /* 4329 802.11n 2.4G device */
 119 #define BCM4329_D11N5G_ID       0x4330          /* 4329 802.11n 5G device */
 120 #define BCM4315_D11DUAL_ID      0x4334          /* 4315 802.11a/g id */
 121 #define BCM4315_D11G_ID         0x4335          /* 4315 802.11g id */
 122 #define BCM4315_D11A_ID         0x4336          /* 4315 802.11a id */
 123 #define BCM4319_D11N_ID         0x4337          /* 4319 802.11n dualband device */
 124 #define BCM4319_D11N2G_ID       0x4338          /* 4319 802.11n 2.4G device */
 125 #define BCM4319_D11N5G_ID       0x4339          /* 4319 802.11n 5G device */
 126 #define BCM43231_D11N2G_ID      0x4340          /* 43231 802.11n 2.4GHz device */
 127 #define BCM43221_D11N2G_ID      0x4341          /* 43221 802.11n 2.4GHz device */
 128 #define BCM43222_D11N_ID        0x4350          /* 43222 802.11n dualband device */
 129 #define BCM43222_D11N2G_ID      0x4351          /* 43222 802.11n 2.4GHz device */
 130 #define BCM43222_D11N5G_ID      0x4352          /* 43222 802.11n 5GHz device */
 131 #define BCM43226_D11N_ID        0x4354          /* 43226 802.11n dualband device */
 132 #endif /* DEPRECATED */
 133 /* DEPRECATED but used */
 134 #define BCM4306_D11G_ID         0x4320          /* 4306 802.11g */
 135 #define BCM4306_D11A_ID         0x4321          /* 4306 802.11a */
 136 #define BCM4306_D11DUAL_ID      0x4324          /* 4306 dual A+B */
 137 #define BCM4318_D11G_ID         0x4318          /* 4318 802.11b/g id */
 138 #define BCM4318_D11DUAL_ID      0x4319          /* 4318 802.11a/b/g id */
 139 /* DEPRECATED */
 140
 141 #define BCM53572_D11N2G_ID      0x4329          /* 53572 802.11n 2.4Ghz band id (same as BCM4321) */
 142 #define BCM43224_D11N_ID        0x4353          /* 43224 802.11n dualband device */
 143 #define BCM43224_D11N_ID_VEN1   0x0576          /* Vendor specific 43224 802.11n db device */
 144 #define BCM43236_D11N_ID        0x4346          /* 43236 802.11n dualband device */
 145 #define BCM43236_D11N2G_ID      0x4347          /* 43236 802.11n 2.4GHz device */
 146 #define BCM43236_D11N5G_ID      0x4348          /* 43236 802.11n 5GHz device */
 147 #define BCM43225_D11N2G_ID      0x4357          /* 43225 802.11n 2.4GHz device */
 148 #define BCM43421_D11N_ID        0xA99D          /* 43421 802.11n dualband device */
 149 #define BCM4313_D11N2G_ID       0x4727          /* 4313 802.11n 2.4G device */
 150 #define BCM4330_D11N_ID         0x4360          /* 4330 802.11n dualband device */
 151 #define BCM4330_D11N2G_ID       0x4361          /* 4330 802.11n 2.4G device */
 152 #define BCM4330_D11N5G_ID       0x4362          /* 4330 802.11n 5G device */
 153 #define BCM4336_D11N_ID         0x4343          /* 4336 802.11n 2.4GHz device */
 154 #define BCM6362_D11N_ID         0x435f          /* 6362 802.11n dualband device */
 155 #define BCM6362_D11N2G_ID       0x433f          /* 6362 802.11n 2.4Ghz band id */
 156 #define BCM6362_D11N5G_ID       0x434f          /* 6362 802.11n 5Ghz band id */
 157 #define BCM4331_D11N_ID         0x4331          /* 4331 802.11n dualband id */
 158 #define BCM4331_D11N2G_ID       0x4332          /* 4331 802.11n 2.4Ghz band id */
 159 #define BCM4331_D11N5G_ID       0x4333          /* 4331 802.11n 5Ghz band id */
 160 #define BCM43237_D11N_ID        0x4355          /* 43237 802.11n dualband device */
 161 #define BCM43237_D11N5G_ID      0x4356          /* 43237 802.11n 5GHz device */
 162 #define BCM43227_D11N2G_ID      0x4358          /* 43228 802.11n 2.4GHz device */
 163 #define BCM43228_D11N_ID        0x4359          /* 43228 802.11n DualBand device */
 164 #define BCM43228_D11N5G_ID      0x435a          /* 43228 802.11n 5GHz device */
 165 #define BCM43362_D11N_ID        0x4363          /* 43362 802.11n 2.4GHz device */
 166 #define BCM43239_D11N_ID        0x4370          /* 43239 802.11n dualband device */
 167 #define BCM4324_D11N_ID         0x4374          /* 4324 802.11n dualband device */
 168 #define BCM43217_D11N2G_ID      0x43a9          /* 43217 802.11n 2.4GHz device */
 169 #define BCM43131_D11N2G_ID      0x43aa          /* 43131 802.11n 2.4GHz device */
 170 #define BCM4314_D11N2G_ID       0x4364          /* 4314 802.11n 2.4G device */
 171 #define BCM43142_D11N2G_ID      0x4365          /* 43142 802.11n 2.4G device */
 172 #define BCM43143_D11N2G_ID      0x4366          /* 43143 802.11n 2.4G device */
 173 #define BCM4334_D11N_ID         0x4380          /* 4334 802.11n dualband device */
 174 #define BCM4334_D11N2G_ID       0x4381          /* 4334 802.11n 2.4G device */
 175 #define BCM4334_D11N5G_ID       0x4382          /* 4334 802.11n 5G device */
 176 #define BCM43342_D11N_ID        0x4383          /* 43342 802.11n dualband device */
 177 #define BCM43342_D11N2G_ID      0x4384          /* 43342 802.11n 2.4G device */
 178 #define BCM43342_D11N5G_ID      0x4385          /* 43342 802.11n 5G device */
 179 #define BCM43341_D11N_ID        0x4386          /* 43341 802.11n dualband device */
 180 #define BCM43341_D11N2G_ID      0x4387          /* 43341 802.11n 2.4G device */
 181 #define BCM43341_D11N5G_ID      0x4388          /* 43341 802.11n 5G device */
 182 #define BCM4360_D11AC_ID        0x43a0
 183 #define BCM4360_D11AC2G_ID      0x43a1
 184 #define BCM4360_D11AC5G_ID      0x43a2
 185 #define BCM4345_D11AC_ID        0x43ab          /* 4345 802.11ac dualband device */
 186 #define BCM4345_D11AC2G_ID      0x43ac          /* 4345 802.11ac 2.4G device */
 187 #define BCM4345_D11AC5G_ID      0x43ad          /* 4345 802.11ac 5G device */
 188 #define BCM43455_D11AC_ID       0x43e3          /* 43455 802.11ac dualband device */
 189 #define BCM43455_D11AC2G_ID     0x43e4          /* 43455 802.11ac 2.4G device */
 190 #define BCM43455_D11AC5G_ID     0x43e5          /* 43455 802.11ac 5G device */
 191 #define BCM4335_D11AC_ID        0x43ae
 192 #define BCM4335_D11AC2G_ID      0x43af
 193 #define BCM4335_D11AC5G_ID      0x43b0
 194 #define BCM4352_D11AC_ID        0x43b1          /* 4352 802.11ac dualband device */
 195 #define BCM4352_D11AC2G_ID      0x43b2          /* 4352 802.11ac 2.4G device */
 196 #define BCM4352_D11AC5G_ID      0x43b3          /* 4352 802.11ac 5G device */
 197 #define BCM43602_D11AC_ID       0x43ba          /* ac dualband PCI devid SPROM programmed */
 198 #define BCM43602_D11AC2G_ID     0x43bb          /* 43602 802.11ac 2.4G device */
 199 #define BCM43602_D11AC5G_ID     0x43bc          /* 43602 802.11ac 5G device */
 200 #define BCM4349_D11AC_ID        0x4349          /* 4349 802.11ac dualband device */
 201 #define BCM4349_D11AC2G_ID      0x43dd          /* 4349 802.11ac 2.4G device */
 202 #define BCM4349_D11AC5G_ID      0x43de          /* 4349 802.11ac 5G device */
 203 #define BCM53573_D11AC_ID       0x43b4          /* 53573 802.11ac dualband device */
 204 #define BCM53573_D11AC2G_ID     0x43b5          /* 53573 802.11ac 2.4G device */
 205 #define BCM53573_D11AC5G_ID     0x43b6          /* 53573 802.11ac 5G device */
 206 #define BCM47189_D11AC_ID       0x43c6          /* 47189 802.11ac dualband device */
 207 #define BCM47189_D11AC2G_ID     0x43c7          /* 47189 802.11ac 2.4G device */
 208 #define BCM47189_D11AC5G_ID     0x43c8          /* 47189 802.11ac 5G device */
 209 #define BCM4355_D11AC_ID        0x43dc          /* 4355 802.11ac dualband device */
 210 #define BCM4355_D11AC2G_ID      0x43fc          /* 4355 802.11ac 2.4G device */
 211 #define BCM4355_D11AC5G_ID      0x43fd          /* 4355 802.11ac 5G device */
 212 #define BCM4359_D11AC_ID        0x43ef          /* 4359 802.11ac dualband device */
 213 #define BCM4359_D11AC2G_ID      0x43fe          /* 4359 802.11ac 2.4G device */
 214 #define BCM4359_D11AC5G_ID      0x43ff          /* 4359 802.11ac 5G device */
 215 #define BCM43596_D11AC_ID       0x4415          /* 43596 802.11ac dualband device */
 216 #define BCM43596_D11AC2G_ID     0x4416          /* 43596 802.11ac 2.4G device */
 217 #define BCM43596_D11AC5G_ID     0x4417          /* 43596 802.11ac 5G device */
 218 #define BCM43597_D11AC_ID       0x441c          /* 43597 802.11ac dualband device */
 219 #define BCM43597_D11AC2G_ID     0x441d          /* 43597 802.11ac 2.4G device */
 220 #define BCM43597_D11AC5G_ID     0x441e          /* 43597 802.11ac 5G device */
 221 #define BCM43909_D11AC_ID       0x43d0          /* 43909 802.11ac dualband device */
 222 #define BCM43909_D11AC2G_ID     0x43d1          /* 43909 802.11ac 2.4G device */
 223 #define BCM43909_D11AC5G_ID     0x43d2          /* 43909 802.11ac 5G device */
 224 #define BCM43012_D11N_ID        0xA804          /* 43012 802.11n dualband device */
 225 #define BCM43012_D11N2G_ID      0xA805          /* 43012 802.11n 2.4G device */
 226 #define BCM43012_D11N5G_ID      0xA806          /* 43012 802.11n 5G device */
 227
 228 /* PCI Subsystem ID */
 229 #define BCM943228HMB_SSID_VEN1  0x0607
 230 #define BCM94313HMGBL_SSID_VEN1 0x0608
 231 #define BCM94313HMG_SSID_VEN1   0x0609
 232 #define BCM943142HM_SSID_VEN1   0x0611
 233
 234 #define BCM43143_D11N2G_ID      0x4366          /* 43143 802.11n 2.4G device */
 235
 236 #define BCM43242_D11N_ID        0x4367          /* 43242 802.11n dualband device */
 237 #define BCM43242_D11N2G_ID      0x4368          /* 43242 802.11n 2.4G device */
 238 #define BCM43242_D11N5G_ID      0x4369          /* 43242 802.11n 5G device */
 239
 240 #define BCM4350_D11AC_ID        0x43a3
 241 #define BCM4350_D11AC2G_ID      0x43a4
 242 #define BCM4350_D11AC5G_ID      0x43a5
 243
 244 #define BCM43556_D11AC_ID       0x43b7
 245 #define BCM43556_D11AC2G_ID     0x43b8
 246 #define BCM43556_D11AC5G_ID     0x43b9
 247
 248 #define BCM43558_D11AC_ID       0x43c0
 249 #define BCM43558_D11AC2G_ID     0x43c1
 250 #define BCM43558_D11AC5G_ID     0x43c2
 251
 252 #define BCM43566_D11AC_ID       0x43d3
 253 #define BCM43566_D11AC2G_ID     0x43d4
 254 #define BCM43566_D11AC5G_ID     0x43d5
 255
 256 #define BCM43568_D11AC_ID       0x43d6
 257 #define BCM43568_D11AC2G_ID     0x43d7
 258 #define BCM43568_D11AC5G_ID     0x43d8
 259
 260 #define BCM43569_D11AC_ID       0x43d9
 261 #define BCM43569_D11AC2G_ID     0x43da
 262 #define BCM43569_D11AC5G_ID     0x43db
 263
 264 #define BCM43570_D11AC_ID       0x43d9
 265 #define BCM43570_D11AC2G_ID     0x43da
 266 #define BCM43570_D11AC5G_ID     0x43db
 267
 268 #define BCM4354_D11AC_ID        0x43df          /* 4354 802.11ac dualband device */
 269 #define BCM4354_D11AC2G_ID      0x43e0          /* 4354 802.11ac 2.4G device */
 270 #define BCM4354_D11AC5G_ID      0x43e1          /* 4354 802.11ac 5G device */
 271 #define BCM43430_D11N2G_ID      0x43e2          /* 43430 802.11n 2.4G device */
 272 #define BCM43018_D11N2G_ID      0x441b          /* 43018 802.11n 2.4G device */
 273
 274
 275 #define BCM4347_D11AC_ID        0x440a          /* 4347 802.11ac dualband device */
 276 #define BCM4347_D11AC2G_ID      0x440b          /* 4347 802.11ac 2.4G device */
 277 #define BCM4347_D11AC5G_ID      0x440c          /* 4347 802.11ac 5G device */
 278
 279 #define BCM4361_D11AC_ID        0x441f          /* 4361 802.11ac dualband device */
 280 #define BCM4361_D11AC2G_ID      0x4420          /* 4361 802.11ac 2.4G device */
 281 #define BCM4361_D11AC5G_ID      0x4421          /* 4361 802.11ac 5G device */
 282
 283 #define BCM4364_D11AC_ID        0x4464          /* 4364 802.11ac dualband device */
 284 #define BCM4364_D11AC2G_ID      0x446a          /* 4364 802.11ac 2.4G device */
 285 #define BCM4364_D11AC5G_ID      0x446b          /* 4364 802.11ac 5G device */
 286
 287 #define BCM4365_D11AC_ID        0x43ca
 288 #define BCM4365_D11AC2G_ID      0x43cb
 289 #define BCM4365_D11AC5G_ID      0x43cc
 290
 291 #define BCM4366_D11AC_ID        0x43c3
 292 #define BCM4366_D11AC2G_ID      0x43c4
 293 #define BCM4366_D11AC5G_ID      0x43c5
 294
 295 #define BCM43349_D11N_ID        0x43e6          /* 43349 802.11n dualband id */
 296 #define BCM43349_D11N2G_ID      0x43e7          /* 43349 802.11n 2.4Ghz band id */
 297 #define BCM43349_D11N5G_ID      0x43e8          /* 43349 802.11n 5Ghz band id */
 298
 299 #define BCM4358_D11AC_ID        0x43e9          /* 4358 802.11ac dualband device */
 300 #define BCM4358_D11AC2G_ID      0x43ea          /* 4358 802.11ac 2.4G device */
 301 #define BCM4358_D11AC5G_ID      0x43eb          /* 4358 802.11ac 5G device */
 302
 303 #define BCM4356_D11AC_ID        0x43ec          /* 4356 802.11ac dualband device */
 304 #define BCM4356_D11AC2G_ID      0x43ed          /* 4356 802.11ac 2.4G device */
 305 #define BCM4356_D11AC5G_ID      0x43ee          /* 4356 802.11ac 5G device */
 306
 307 #define BCM4371_D11AC_ID        0x440d          /* 4371 802.11ac dualband device */
 308 #define BCM4371_D11AC2G_ID      0x440e          /* 4371 802.11ac 2.4G device */
 309 #define BCM4371_D11AC5G_ID      0x440f          /* 4371 802.11ac 5G device */
 310 #define BCM7271_D11AC_ID        0x4410          /* 7271 802.11ac dualband device */
 311 #define BCM7271_D11AC2G_ID      0x4411          /* 7271 802.11ac 2.4G device */
 312 #define BCM7271_D11AC5G_ID      0x4412          /* 7271 802.11ac 5G device */
 313
 314 #define BCM4373_D11AC_ID        0x4418          /* 4373 802.11ac dualband device */
 315 #define BCM4373_D11AC2G_ID      0x4419          /* 4373 802.11ac 2.4G device */
 316 #define BCM4373_D11AC5G_ID      0x441a          /* 4373 802.11ac 5G device */
 317
 318 #define BCMGPRS_UART_ID         0x4333          /* Uart id used by 4306/gprs card */
 319 #define BCMGPRS2_UART_ID        0x4344          /* Uart id used by 4306/gprs card */
 320 #define FPGA_JTAGM_ID           0x43f0          /* FPGA jtagm device id */
 321 #define BCM_JTAGM_ID            0x43f1          /* BCM jtagm device id */
 322 #define SDIOH_FPGA_ID           0x43f2          /* sdio host fpga */
 323 #define BCM_SDIOH_ID            0x43f3          /* BCM sdio host id */
 324 #define SDIOD_FPGA_ID           0x43f4          /* sdio device fpga */
 325 #define SPIH_FPGA_ID            0x43f5          /* PCI SPI Host Controller FPGA */
 326 #define BCM_SPIH_ID             0x43f6          /* Synopsis SPI Host Controller */
 327 #define MIMO_FPGA_ID            0x43f8          /* FPGA mimo minimacphy device id */
 328 #define BCM_JTAGM2_ID           0x43f9          /* BCM alternate jtagm device id */
 329 #define SDHCI_FPGA_ID           0x43fa          /* Standard SDIO Host Controller FPGA */
 330 #define BCM4402_ENET_ID         0x4402          /* 4402 enet */
 331 #define BCM4402_V90_ID          0x4403          /* 4402 v90 codec */
 332 #define BCM4410_DEVICE_ID       0x4410          /* bcm44xx family pci iline */
 333 #define BCM4412_DEVICE_ID       0x4412          /* bcm44xx family pci enet */
 334 #define BCM4430_DEVICE_ID       0x4430          /* bcm44xx family cardbus iline */
 335 #define BCM4432_DEVICE_ID       0x4432          /* bcm44xx family cardbus enet */
 336 #define BCM4704_ENET_ID         0x4706          /* 4704 enet (Use 47XX_ENET_ID instead!) */
 337 #define BCM4710_DEVICE_ID       0x4710          /* 4710 primary function 0 */
 338 #define BCM47XX_AUDIO_ID        0x4711          /* 47xx audio codec */
 339 #define BCM47XX_V90_ID          0x4712          /* 47xx v90 codec */
 340 #define BCM47XX_ENET_ID         0x4713          /* 47xx enet */
 341 #define BCM47XX_EXT_ID          0x4714          /* 47xx external i/f */
 342 #define BCM47XX_GMAC_ID         0x4715          /* 47xx Unimac based GbE */
 343 #define BCM47XX_USBH_ID         0x4716          /* 47xx usb host */
 344 #define BCM47XX_USBD_ID         0x4717          /* 47xx usb device */
 345 #define BCM47XX_IPSEC_ID        0x4718          /* 47xx ipsec */
 346 #define BCM47XX_ROBO_ID         0x4719          /* 47xx/53xx roboswitch core */
 347 #define BCM47XX_USB20H_ID       0x471a          /* 47xx usb 2.0 host */
 348 #define BCM47XX_USB20D_ID       0x471b          /* 47xx usb 2.0 device */
 349 #define BCM47XX_ATA100_ID       0x471d          /* 47xx parallel ATA */
 350 #define BCM47XX_SATAXOR_ID      0x471e          /* 47xx serial ATA & XOR DMA */
 351 #define BCM47XX_GIGETH_ID       0x471f          /* 47xx GbE (5700) */
 352 #ifdef DEPRECATED /* These products have been deprecated */
 353 #define BCM4712_MIPS_ID         0x4720          /* 4712 base devid */
 354 #define BCM4716_DEVICE_ID       0x4722          /* 4716 base devid */
 355 #endif /* DEPRECATED */
 356 #define BCM47XX_USB30H_ID       0x472a          /* 47xx usb 3.0 host */
 357 #define BCM47XX_USB30D_ID       0x472b          /* 47xx usb 3.0 device */
 358 #define BCM47XX_USBHUB_ID       0x472c          /* 47xx usb hub */
 359 #define BCM47XX_SMBUS_EMU_ID    0x47fe          /* 47xx emulated SMBus device */
 360 #define BCM47XX_XOR_EMU_ID      0x47ff          /* 47xx emulated XOR engine */
 361 #define EPI41210_DEVICE_ID      0xa0fa          /* bcm4210 */
 362 #define EPI41230_DEVICE_ID      0xa10e          /* bcm4230 */
 363 #define JINVANI_SDIOH_ID        0x4743          /* Jinvani SDIO Gold Host */
 364 #define BCM27XX_SDIOH_ID        0x2702          /* BCM27xx Standard SDIO Host */
 365 #define PCIXX21_FLASHMEDIA_ID   0x803b          /* TI PCI xx21 Standard Host Controller */
 366 #define PCIXX21_SDIOH_ID        0x803c          /* TI PCI xx21 Standard Host Controller */
 367 #define R5C822_SDIOH_ID         0x0822          /* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host */
 368 #define JMICRON_SDIOH_ID        0x2381          /* JMicron Standard SDIO Host Controller */
 369
 370 #define BCM43452_D11AC_ID       0x47ab          /* 43452 802.11ac dualband device */
 371 #define BCM43452_D11AC2G_ID     0x47ac          /* 43452 802.11ac 2.4G device */
 372 #define BCM43452_D11AC5G_ID     0x47ad          /* 43452 802.11ac 5G device */
 373
 374 /* Chip IDs */
 375 #ifdef DEPRECATED /* These products have been deprecated */
 376 #define BCM4306_CHIP_ID         0x4306          /* 4306 chipcommon chipid */
 377 #define BCM4311_CHIP_ID         0x4311          /* 4311 PCIe 802.11a/b/g */
 378 #define BCM43111_CHIP_ID        43111           /* 43111 chipcommon chipid (OTP chipid) */
 379 #define BCM43112_CHIP_ID        43112           /* 43112 chipcommon chipid (OTP chipid) */
 380 #define BCM4312_CHIP_ID         0x4312          /* 4312 chipcommon chipid */
 381 #define BCM4315_CHIP_ID         0x4315          /* 4315 chip id */
 382 #define BCM4318_CHIP_ID         0x4318          /* 4318 chipcommon chipid */
 383 #define BCM4319_CHIP_ID         0x4319          /* 4319 chip id */
 384 #define BCM4320_CHIP_ID         0x4320          /* 4320 chipcommon chipid */
 385 #define BCM4321_CHIP_ID         0x4321          /* 4321 chipcommon chipid */
 386 #define BCM4322_CHIP_ID         0x4322          /* 4322 chipcommon chipid */
 387 #define BCM43221_CHIP_ID        43221           /* 43221 chipcommon chipid (OTP chipid) */
 388 #define BCM43222_CHIP_ID        43222           /* 43222 chipcommon chipid */
 389 #define BCM43226_CHIP_ID        43226           /* 43226 chipcommon chipid */
 390 #define BCM43231_CHIP_ID        43231           /* 43231 chipcommon chipid (OTP chipid) */
 391 #define BCM4342_CHIP_ID         4342            /* 4342 chipcommon chipid (OTP, RBBU) */
 392 #define BCM4325_CHIP_ID         0x4325          /* 4325 chip id */
 393 #define BCM4328_CHIP_ID         0x4328          /* 4328 chip id */
 394 #define BCM4329_CHIP_ID         0x4329          /* 4329 chipcommon chipid */
 395 #define BCM4712_CHIP_ID         0x4712          /* 4712 chipcommon chipid */
 396 #endif /* DEPRECATED */
 397
 398 /* DEPRECATED but still referenced in components - start */
 399 #define BCM4716_CHIP_ID         0x4716          /* 4716 chipcommon chipid */
 400 #define BCM4748_CHIP_ID         0x4748          /* 4716 chipcommon chipid (OTP, RBBU) */
 401 #define BCM47162_CHIP_ID        47162           /* 47162 chipcommon chipid */
 402 #define BCM5354_CHIP_ID         0x5354          /* 5354 chipcommon chipid */
 403 /* DEPRECATED but still referenced in components - end */
 404
 405 #define BCM43224_CHIP_ID        43224           /* 43224 chipcommon chipid */
 406 #define BCM43225_CHIP_ID        43225           /* 43225 chipcommon chipid */
 407 #define BCM43227_CHIP_ID        43227           /* 43227 chipcommon chipid */
 408 #define BCM43228_CHIP_ID        43228           /* 43228 chipcommon chipid */
 409 #define BCM43217_CHIP_ID        43217           /* 43217 chip id (OTP chipid) */
 410 #define BCM4313_CHIP_ID         0x4313          /* 4313 chip id */
 411 #define BCM43131_CHIP_ID        43131           /* 43131 chip id (OTP chipid) */
 412 #define BCM43234_CHIP_ID        43234           /* 43234 chipcommon chipid */
 413 #define BCM43235_CHIP_ID        43235           /* 43235 chipcommon chipid */
 414 #define BCM43236_CHIP_ID        43236           /* 43236 chipcommon chipid */
 415 #define BCM43237_CHIP_ID        43237           /* 43237 chipcommon chipid */
 416 #define BCM43238_CHIP_ID        43238           /* 43238 chipcommon chipid */
 417 #define BCM43239_CHIP_ID        43239           /* 43239 chipcommon chipid */
 418 #define BCM43420_CHIP_ID        43420           /* 43222 chipcommon chipid (OTP, RBBU) */
 419 #define BCM43421_CHIP_ID        43421           /* 43224 chipcommon chipid (OTP, RBBU) */
 420 #define BCM43428_CHIP_ID        43428           /* 43228 chipcommon chipid (OTP, RBBU) */
 421 #define BCM43431_CHIP_ID        43431           /* 4331  chipcommon chipid (OTP, RBBU) */
 422 #define BCM43460_CHIP_ID        43460           /* 4360  chipcommon chipid (OTP, RBBU) */
 423 #define BCM4331_CHIP_ID         0x4331          /* 4331 chipcommon chipid */
 424 #define BCM4336_CHIP_ID         0x4336          /* 4336 chipcommon chipid */
 425 #define BCM43362_CHIP_ID        43362           /* 43362 chipcommon chipid */
 426 #define BCM4330_CHIP_ID         0x4330          /* 4330 chipcommon chipid */
 427 #define BCM6362_CHIP_ID         0x6362          /* 6362 chipcommon chipid */
 428 #define BCM4314_CHIP_ID         0x4314          /* 4314 chipcommon chipid */
 429 #define BCM43142_CHIP_ID        43142           /* 43142 chipcommon chipid */
 430 #define BCM43143_CHIP_ID        43143           /* 43143 chipcommon chipid */
 431 #define BCM4324_CHIP_ID         0x4324          /* 4324 chipcommon chipid */
 432 #define BCM43242_CHIP_ID        43242           /* 43242 chipcommon chipid */
 433 #define BCM43243_CHIP_ID        43243           /* 43243 chipcommon chipid */
 434 #define BCM4334_CHIP_ID         0x4334          /* 4334 chipcommon chipid */
 435 #define BCM4335_CHIP_ID         0x4335          /* 4335 chipcommon chipid */
 436 #define BCM4339_CHIP_ID         0x4339          /* 4339 chipcommon chipid */
 437 #define BCM43349_CHIP_ID        43349                   /* 43349(0xA955) chipcommon chipid */
 438 #define BCM4360_CHIP_ID         0x4360          /* 4360 chipcommon chipid */
 439 #define BCM4364_CHIP_ID         0x4364                  /* 4364 chipcommon chipid */
 440 #define BCM4352_CHIP_ID         0x4352          /* 4352 chipcommon chipid */
 441 #define BCM43526_CHIP_ID        0xAA06
 442 #define BCM43340_CHIP_ID        43340           /* 43340 chipcommon chipid */
 443 #define BCM43341_CHIP_ID        43341           /* 43341 chipcommon chipid */
 444 #define BCM43342_CHIP_ID        43342           /* 43342 chipcommon chipid */
 445 #define BCM4350_CHIP_ID         0x4350          /* 4350 chipcommon chipid */
 446 #define BCM4354_CHIP_ID         0x4354          /* 4354 chipcommon chipid */
 447 #define BCM4356_CHIP_ID         0x4356          /* 4356 chipcommon chipid */
 448 #define BCM4371_CHIP_ID         0x4371          /* 4371 chipcommon chipid */
 449 #define BCM43556_CHIP_ID        0xAA24          /* 43556 chipcommon chipid */
 450 #define BCM43558_CHIP_ID        0xAA26          /* 43558 chipcommon chipid */
 451 #define BCM43562_CHIP_ID        0xAA2A          /* 43562 chipcommon chipid */
 452 #define BCM43566_CHIP_ID        0xAA2E          /* 43566 chipcommon chipid */
 453 #define BCM43567_CHIP_ID        0xAA2F          /* 43567 chipcommon chipid */
 454 #define BCM43568_CHIP_ID        0xAA30          /* 43568 chipcommon chipid */
 455 #define BCM43569_CHIP_ID        0xAA31          /* 43569 chipcommon chipid */
 456 #define BCM43570_CHIP_ID        0xAA32          /* 43570 chipcommon chipid */
 457 #define BCM4358_CHIP_ID         0x4358          /* 4358 chipcommon chipid */
 458 #define BCM43012_CHIP_ID        0xA804                  /* 43012 chipcommon chipid */
 459 #define BCM4350_CHIP(chipid)    ((CHIPID(chipid) == BCM4350_CHIP_ID) || \
 460                                 (CHIPID(chipid) == BCM4354_CHIP_ID) || \
 461                                 (CHIPID(chipid) == BCM43556_CHIP_ID) || \
 462                                 (CHIPID(chipid) == BCM43558_CHIP_ID) || \
 463                                 (CHIPID(chipid) == BCM43566_CHIP_ID) || \
 464                                 (CHIPID(chipid) == BCM43567_CHIP_ID) || \
 465                                 (CHIPID(chipid) == BCM43568_CHIP_ID) || \
 466                                 (CHIPID(chipid) == BCM43569_CHIP_ID) || \
 467                                 (CHIPID(chipid) == BCM43570_CHIP_ID) || \
 468                                 (CHIPID(chipid) == BCM4358_CHIP_ID)) /* 4350 variations */
 469
 470 #define BCM4345_CHIP_ID         0x4345          /* 4345 chipcommon chipid */
 471 #define BCM43454_CHIP_ID        43454           /* 43454 chipcommon chipid */
 472 #define BCM43455_CHIP_ID        43455           /* 43455 chipcommon chipid */
 473 #define BCM43457_CHIP_ID        43457           /* 43457 chipcommon chipid */
 474 #define BCM43458_CHIP_ID        43458           /* 43458 chipcommon chipid */
 475
 476 #define BCM4345_CHIP(chipid)    (CHIPID(chipid) == BCM4345_CHIP_ID || \
 477                                  CHIPID(chipid) == BCM43454_CHIP_ID || \
 478                                  CHIPID(chipid) == BCM43455_CHIP_ID || \
 479                                  CHIPID(chipid) == BCM43457_CHIP_ID || \
 480                                  CHIPID(chipid) == BCM43458_CHIP_ID)
 481
 482 #define CASE_BCM4345_CHIP       case BCM4345_CHIP_ID: /* fallthrough */ \
 483                                 case BCM43454_CHIP_ID: /* fallthrough */ \
 484                                 case BCM43455_CHIP_ID: /* fallthrough */ \
 485                                 case BCM43457_CHIP_ID: /* fallthrough */ \
 486                                 case BCM43458_CHIP_ID
 487
 488 #define BCM43430_CHIP_ID        43430           /* 43430 chipcommon chipid */
 489 #define BCM43018_CHIP_ID        43018           /* 43018 chipcommon chipid */
 490 #define BCM4349_CHIP_ID         0x4349          /* 4349 chipcommon chipid */
 491 #define BCM4355_CHIP_ID         0x4355          /* 4355 chipcommon chipid */
 492 #define BCM4359_CHIP_ID         0x4359          /* 4359 chipcommon chipid */
 493 #define BCM4349_CHIP(chipid)    ((CHIPID(chipid) == BCM4349_CHIP_ID) || \
 494                                 (CHIPID(chipid) == BCM4355_CHIP_ID) || \
 495                                 (CHIPID(chipid) == BCM4359_CHIP_ID))
 496 #define BCM4349_CHIP_GRPID              BCM4349_CHIP_ID: \
 497                                         case BCM4355_CHIP_ID: \
 498                                         case BCM4359_CHIP_ID
 499 #define BCM43596_CHIP_ID                43596           /* 43596 chipcommon chipid */
 500 #define BCM4347_CHIP_ID         0x4347          /* 4347 chipcommon chipid */
 501 #define BCM4357_CHIP_ID         0x4357          /* 4357 chipcommon chipid */
 502 #define BCM4361_CHIP_ID         0x4361          /* 4361 chipcommon chipid */
 503 #define BCM4347_CHIP(chipid)    ((CHIPID(chipid) == BCM4347_CHIP_ID) || \
 504                                 (CHIPID(chipid) == BCM4357_CHIP_ID) || \
 505                                 (CHIPID(chipid) == BCM4361_CHIP_ID))
 506 #define BCM4347_CHIP_GRPID              BCM4347_CHIP_ID: \
 507                                         case BCM4357_CHIP_ID: \
 508                                         case BCM4361_CHIP_ID
 509
 510 #define BCM4365_CHIP_ID         0x4365          /* 4365 chipcommon chipid */
 511 #define BCM4366_CHIP_ID         0x4366          /* 4366 chipcommon chipid */
 512 #define BCM4365_CHIP(chipid)    ((CHIPID(chipid) == BCM4365_CHIP_ID) || \
 513                                 (CHIPID(chipid) == BCM4366_CHIP_ID))
 514
 515
 516 #define BCM43909_CHIP_ID        0xab85          /* 43909 chipcommon chipid */
 517
 518 #define BCM43602_CHIP_ID        0xaa52          /* 43602 chipcommon chipid */
 519 #define BCM43462_CHIP_ID        0xa9c6          /* 43462 chipcommon chipid */
 520 #define BCM43522_CHIP_ID        0xaa02          /* 43522 chipcommon chipid */
 521 #define BCM43602_CHIP(chipid)   ((CHIPID(chipid) == BCM43602_CHIP_ID) || \
 522                                 (CHIPID(chipid) == BCM43462_CHIP_ID) || \
 523                                 (CHIPID(chipid) == BCM43522_CHIP_ID)) /* 43602 variations */
 524 #define BCM43012_CHIP(chipid)   (CHIPID(chipid) == BCM43012_CHIP_ID)
 525 #define CASE_BCM43602_CHIP              case BCM43602_CHIP_ID: /* fallthrough */ \
 526                                 case BCM43462_CHIP_ID: /* fallthrough */ \
 527                                 case BCM43522_CHIP_ID
 528
 529 #define BCM4402_CHIP_ID         0x4402          /* 4402 chipid */
 530 #define BCM4704_CHIP_ID         0x4704          /* 4704 chipcommon chipid */
 531 #define BCM4706_CHIP_ID         0x5300          /* 4706 chipcommon chipid */
 532 #define BCM4707_CHIP_ID         53010           /* 4707 chipcommon chipid */
 533 #define BCM47094_CHIP_ID        53030           /* 47094 chipcommon chipid */
 534 #define BCM53018_CHIP_ID        53018           /* 53018 chipcommon chipid */
 535 #define BCM4707_CHIP(chipid)    (((chipid) == BCM4707_CHIP_ID) || \
 536                                 ((chipid) == BCM53018_CHIP_ID) || \
 537                                 ((chipid) == BCM47094_CHIP_ID))
 538 #define BCM4710_CHIP_ID         0x4710          /* 4710 chipid */
 539 #define BCM4749_CHIP_ID         0x4749          /* 5357 chipcommon chipid (OTP, RBBU) */
 540 #define BCM4785_CHIP_ID         0x4785          /* 4785 chipcommon chipid */
 541 #define BCM5350_CHIP_ID         0x5350          /* 5350 chipcommon chipid */
 542 #define BCM5352_CHIP_ID         0x5352          /* 5352 chipcommon chipid */
 543 #define BCM5365_CHIP_ID         0x5365          /* 5365 chipcommon chipid */
 544 #define BCM5356_CHIP_ID         0x5356          /* 5356 chipcommon chipid */
 545 #define BCM5357_CHIP_ID         0x5357          /* 5357 chipcommon chipid */
 546 #define BCM53572_CHIP_ID        53572           /* 53572 chipcommon chipid */
 547 #define BCM53573_CHIP_ID        53573           /* 53573 chipcommon chipid */
 548 #define BCM53574_CHIP_ID        53574           /* 53574 chipcommon chipid */
 549 #define BCM53573_CHIP(chipid)   ((CHIPID(chipid) == BCM53573_CHIP_ID) || \
 550                                 (CHIPID(chipid) == BCM53574_CHIP_ID))
 551 #define BCM53573_CHIP_GRPID     BCM53573_CHIP_ID : \
 552                                 case BCM53574_CHIP_ID
 553 #define BCM53573_DEVICE(devid)  (((devid) == BCM53573_D11AC_ID) || \
 554                                 ((devid) == BCM53573_D11AC2G_ID) || \
 555                                 ((devid) == BCM53573_D11AC5G_ID) || \
 556                                 ((devid) == BCM47189_D11AC_ID) || \
 557                                 ((devid) == BCM47189_D11AC2G_ID) || \
 558                                 ((devid) == BCM47189_D11AC5G_ID))
 559
 560 #define BCM7271_CHIP_ID         0x05c9          /* 7271 chipcommon chipid */
 561 #define BCM4373_CHIP_ID         0x4373          /* 4373 chipcommon chipid */
 562
 563 /* Package IDs */
 564 #ifdef DEPRECATED /* These products have been deprecated */
 565 #define BCM4303_PKG_ID          2               /* 4303 package id */
 566 #define BCM4309_PKG_ID          1               /* 4309 package id */
 567 #define BCM4712LARGE_PKG_ID     0               /* 340pin 4712 package id */
 568 #define BCM4712SMALL_PKG_ID     1               /* 200pin 4712 package id */
 569 #define BCM4712MID_PKG_ID       2               /* 225pin 4712 package id */
 570 #define BCM4328USBD11G_PKG_ID   2               /* 4328 802.11g USB package id */
 571 #define BCM4328USBDUAL_PKG_ID   3               /* 4328 802.11a/g USB package id */
 572 #define BCM4328SDIOD11G_PKG_ID  4               /* 4328 802.11g SDIO package id */
 573 #define BCM4328SDIODUAL_PKG_ID  5               /* 4328 802.11a/g SDIO package id */
 574 #define BCM4329_289PIN_PKG_ID   0               /* 4329 289-pin package id */
 575 #define BCM4329_182PIN_PKG_ID   1               /* 4329N 182-pin package id */
 576 #define BCM5354E_PKG_ID         1               /* 5354E package id */
 577 #define BCM4716_PKG_ID          8               /* 4716 package id */
 578 #define BCM4717_PKG_ID          9               /* 4717 package id */
 579 #define BCM4718_PKG_ID          10              /* 4718 package id */
 580 #endif  /* DEPRECATED */
 581 #define BCM5356_PKG_NONMODE     1               /* 5356 package without nmode suppport */
 582 #define BCM5358U_PKG_ID         8               /* 5358U package id */
 583 #define BCM5358_PKG_ID          9               /* 5358 package id */
 584 #define BCM47186_PKG_ID         10              /* 47186 package id */
 585 #define BCM5357_PKG_ID          11              /* 5357 package id */
 586 #define BCM5356U_PKG_ID         12              /* 5356U package id */
 587 #define BCM53572_PKG_ID         8               /* 53572 package id */
 588 #define BCM5357C0_PKG_ID        8               /* 5357c0 package id (the same as 53572) */
 589 #define BCM47188_PKG_ID         9               /* 47188 package id */
 590 #define BCM5358C0_PKG_ID        0xa             /* 5358c0 package id */
 591 #define BCM5356C0_PKG_ID        0xb             /* 5356c0 package id */
 592 #define BCM4331TT_PKG_ID        8               /* 4331 12x12 package id */
 593 #define BCM4331TN_PKG_ID        9               /* 4331 12x9 package id */
 594 #define BCM4331TNA0_PKG_ID     0xb              /* 4331 12x9 package id */
 595 #define BCM47189_PKG_ID         1               /* 47189 package id */
 596 #define BCM53573_PKG_ID         0               /* 53573 package id */
 597 #define BCM4706L_PKG_ID         1               /* 4706L package id */
 598
 599 #define HDLSIM5350_PKG_ID       1               /* HDL simulator package id for a 5350 */
 600 #define HDLSIM_PKG_ID           14              /* HDL simulator package id */
 601 #define HWSIM_PKG_ID            15              /* Hardware simulator package id */
 602 #define BCM43224_FAB_CSM        0x8             /* the chip is manufactured by CSM */
 603 #define BCM43224_FAB_SMIC       0xa             /* the chip is manufactured by SMIC */
 604 #define BCM4336_WLBGA_PKG_ID    0x8
 605 #define BCM4330_WLBGA_PKG_ID    0x0
 606 #define BCM4314PCIE_ARM_PKG_ID          (8 | 0) /* 4314 QFN PCI package id, bit 3 tie high */
 607 #define BCM4314SDIO_PKG_ID              (8 | 1) /* 4314 QFN SDIO package id */
 608 #define BCM4314PCIE_PKG_ID              (8 | 2) /* 4314 QFN PCI (ARM-less) package id */
 609 #define BCM4314SDIO_ARM_PKG_ID          (8 | 3) /* 4314 QFN SDIO (ARM-less) package id */
 610 #define BCM4314SDIO_FPBGA_PKG_ID        (8 | 4) /* 4314 FpBGA SDIO package id */
 611 #define BCM4314DEV_PKG_ID               (8 | 6) /* 4314 Developement package id */
 612
 613 #define BCM4707_PKG_ID          1               /* 4707 package id */
 614 #define BCM4708_PKG_ID          2               /* 4708 package id */
 615 #define BCM4709_PKG_ID          0               /* 4709 package id */
 616
 617 #define PCIXX21_FLASHMEDIA0_ID  0x8033          /* TI PCI xx21 Standard Host Controller */
 618 #define PCIXX21_SDIOH0_ID       0x8034          /* TI PCI xx21 Standard Host Controller */
 619
 620 #define BCM4335_WLCSP_PKG_ID    (0x0)   /* WLCSP Module/Mobile SDIO/HSIC. */
 621 #define BCM4335_FCBGA_PKG_ID    (0x1)   /* FCBGA PC/Embeded/Media PCIE/SDIO */
 622 #define BCM4335_WLBGA_PKG_ID    (0x2)   /* WLBGA COB/Mobile SDIO/HSIC. */
 623 #define BCM4335_FCBGAD_PKG_ID   (0x3)   /* FCBGA Debug Debug/Dev All if's. */
 624 #define BCM4335_PKG_MASK        (0x3)
 625 #define BCM43602_12x12_PKG_ID   (0x1)   /* 12x12 pins package, used for e.g. router designs */
 626
 627 /* boardflags */
 628 #define BFL_BTC2WIRE            0x00000001  /* old 2wire Bluetooth coexistence, OBSOLETE */
 629 #define BFL_BTCOEX      0x00000001      /* Board supports BTCOEX */
 630 #define BFL_PACTRL              0x00000002  /* Board has gpio 9 controlling the PA */
 631 #define BFL_AIRLINEMODE 0x00000004  /* Board implements gpio radio disable indication */
 632 #define BFL_ADCDIV              0x00000008  /* Board has the rssi ADC divider */
 633 #define BFL_DIS_256QAM          0x00000008
 634 #define BFL_ENETROBO            0x00000010  /* Board has robo switch or core */
 635 #define BFL_TSSIAVG             0x00000010  /* TSSI averaging for ACPHY chips */
 636 #define BFL_NOPLLDOWN           0x00000020  /* Not ok to power down the chip pll and oscillator */
 637 #define BFL_CCKHIPWR            0x00000040  /* Can do high-power CCK transmission */
 638 #define BFL_ENETADM             0x00000080  /* Board has ADMtek switch */
 639 #define BFL_ENETVLAN            0x00000100  /* Board has VLAN capability */
 640 #define BFL_LTECOEX             0x00000200  /* LTE Coex enabled */
 641 #define BFL_NOPCI               0x00000400  /* Board leaves PCI floating */
 642 #define BFL_FEM                 0x00000800  /* Board supports the Front End Module */
 643 #define BFL_EXTLNA              0x00001000  /* Board has an external LNA in 2.4GHz band */
 644 #define BFL_HGPA                0x00002000  /* Board has a high gain PA */
 645 #define BFL_BTC2WIRE_ALTGPIO    0x00004000  /* Board's BTC 2wire is in the alternate gpios */
 646 #define BFL_ALTIQ               0x00008000  /* Alternate I/Q settings */
 647 #define BFL_NOPA                0x00010000  /* Board has no PA */
 648 #define BFL_RSSIINV             0x00020000  /* Board's RSSI uses positive slope(not TSSI) */
 649 #define BFL_PAREF               0x00040000  /* Board uses the PARef LDO */
 650 #define BFL_3TSWITCH            0x00080000  /* Board uses a triple throw switch shared with BT */
 651 #define BFL_PHASESHIFT          0x00100000  /* Board can support phase shifter */
 652 #define BFL_BUCKBOOST           0x00200000  /* Power topology uses BUCKBOOST */
 653 #define BFL_FEM_BT              0x00400000  /* Board has FEM and switch to share antenna w/ BT */
 654 #define BFL_NOCBUCK             0x00800000  /* Power topology doesn't use CBUCK */
 655 #define BFL_CCKFAVOREVM         0x01000000  /* Favor CCK EVM over spectral mask */
 656 #define BFL_PALDO               0x02000000  /* Power topology uses PALDO */
 657 #define BFL_LNLDO2_2P5          0x04000000  /* Select 2.5V as LNLDO2 output voltage */
 658 #define BFL_FASTPWR             0x08000000
 659 #define BFL_UCPWRCTL_MININDX    0x08000000  /* Enforce min power index to avoid FEM damage */
 660 #define BFL_EXTLNA_5GHz         0x10000000  /* Board has an external LNA in 5GHz band */
 661 #define BFL_TRSW_1by2           0x20000000  /* Board has 2 TRSW's in 1by2 designs */
 662 #define BFL_GAINBOOSTA01        0x20000000  /* 5g Gainboost for core0 and core1 */
 663 #define BFL_LO_TRSW_R_5GHz      0x40000000  /* In 5G do not throw TRSW to T for clipLO gain */
 664 #define BFL_ELNA_GAINDEF        0x80000000  /* Backoff InitGain based on elna_2g/5g field
 665                                              * when this flag is set
 666                                              */
 667 #define BFL_EXTLNA_TX   0x20000000      /* Temp boardflag to indicate to */
 668
 669 /* boardflags2 */
 670 #define BFL2_RXBB_INT_REG_DIS   0x00000001  /* Board has an external rxbb regulator */
 671 #define BFL2_APLL_WAR           0x00000002  /* Flag to implement alternative A-band PLL settings */
 672 #define BFL2_TXPWRCTRL_EN       0x00000004  /* Board permits enabling TX Power Control */
 673 #define BFL2_2X4_DIV            0x00000008  /* Board supports the 2X4 diversity switch */
 674 #define BFL2_5G_PWRGAIN         0x00000010  /* Board supports 5G band power gain */
 675 #define BFL2_PCIEWAR_OVR        0x00000020  /* Board overrides ASPM and Clkreq settings */
 676 #define BFL2_CAESERS_BRD        0x00000040  /* Board is Caesers brd (unused by sw) */
 677 #define BFL2_BTC3WIRE           0x00000080  /* Board support legacy 3 wire or 4 wire */
 678 #define BFL2_BTCLEGACY          0x00000080  /* Board support legacy 3/4 wire, to replace
 679                                              * BFL2_BTC3WIRE
 680                                              */
 681 #define BFL2_SKWRKFEM_BRD       0x00000100  /* 4321mcm93 board uses Skyworks FEM */
 682 #define BFL2_SPUR_WAR           0x00000200  /* Board has a WAR for clock-harmonic spurs */
 683 #define BFL2_GPLL_WAR           0x00000400  /* Flag to narrow G-band PLL loop b/w */
 684 #define BFL2_TRISTATE_LED       0x00000800  /* Tri-state the LED */
 685 #define BFL2_SINGLEANT_CCK      0x00001000  /* Tx CCK pkts on Ant 0 only */
 686 #define BFL2_2G_SPUR_WAR        0x00002000  /* WAR to reduce and avoid clock-harmonic spurs in 2G */
 687 #define BFL2_BPHY_ALL_TXCORES   0x00004000  /* Transmit bphy frames using all tx cores */
 688 #define BFL2_FCC_BANDEDGE_WAR   0x00008000  /* Activates WAR to improve FCC bandedge performance */
 689 #define BFL2_DAC_SPUR_IMPROVEMENT 0x00008000       /* Reducing DAC Spurs */
 690 #define BFL2_GPLL_WAR2          0x00010000  /* Flag to widen G-band PLL loop b/w */
 691 #define BFL2_REDUCED_PA_TURNONTIME 0x00010000  /* Flag to reduce PA turn on Time */
 692 #define BFL2_IPALVLSHIFT_3P3    0x00020000
 693 #define BFL2_INTERNDET_TXIQCAL  0x00040000  /* Use internal envelope detector for TX IQCAL */
 694 #define BFL2_XTALBUFOUTEN       0x00080000  /* Keep the buffered Xtal output from radio on */
 695                                 /* Most drivers will turn it off without this flag */
 696                                 /* to save power. */
 697
 698 #define BFL2_ANAPACTRL_2G       0x00100000  /* 2G ext PAs are controlled by analog PA ctrl lines */
 699 #define BFL2_ANAPACTRL_5G       0x00200000  /* 5G ext PAs are controlled by analog PA ctrl lines */
 700 #define BFL2_ELNACTRL_TRSW_2G   0x00400000  /* AZW4329: 2G gmode_elna_gain controls TR Switch */
 701 #define BFL2_BT_SHARE_ANT0      0x00800000  /* share core0 antenna with BT */
 702 #define BFL2_TEMPSENSE_HIGHER   0x01000000  /* The tempsense threshold can sustain higher value
 703                                              * than programmed. The exact delta is decided by
 704                                              * driver per chip/boardtype. This can be used
 705                                              * when tempsense qualification happens after shipment
 706                                              */
 707 #define BFL2_BTC3WIREONLY       0x02000000  /* standard 3 wire btc only.  4 wire not supported */
 708 #define BFL2_PWR_NOMINAL        0x04000000  /* 0: power reduction on, 1: no power reduction */
 709 #define BFL2_EXTLNA_PWRSAVE     0x08000000  /* boardflag to enable ucode to apply power save */
 710                                                 /* ucode control of eLNA during Tx */
 711 #define BFL2_4313_RADIOREG      0x10000000
 712                                                                            /*  board rework */
 713 #define BFL2_DYNAMIC_VMID       0x10000000  /* enable dynamic Vmid in idle TSSI CAL for 4331 */
 714
 715 #define BFL2_SDR_EN             0x20000000  /* SDR enabled or disabled */
 716 #define BFL2_DYNAMIC_VMID       0x10000000  /* boardflag to enable dynamic Vmid idle TSSI CAL */
 717 #define BFL2_LNA1BYPFORTR2G     0x40000000  /* acphy, enable lna1 bypass for clip gain, 2g */
 718 #define BFL2_LNA1BYPFORTR5G     0x80000000  /* acphy, enable lna1 bypass for clip gain, 5g */
 719
 720 /* SROM 11 - 11ac boardflag definitions */
 721 #define BFL_SROM11_BTCOEX  0x00000001  /* Board supports BTCOEX */
 722 #define BFL_SROM11_WLAN_BT_SH_XTL  0x00000002  /* bluetooth and wlan share same crystal */
 723 #define BFL_SROM11_EXTLNA       0x00001000  /* Board has an external LNA in 2.4GHz band */
 724 #define BFL_SROM11_EPA_TURNON_TIME     0x00018000  /* 2 bits for different PA turn on times */
 725 #define BFL_SROM11_EPA_TURNON_TIME_SHIFT  15
 726 #define BFL_SROM11_PRECAL_TX_IDX        0x00040000  /* Dedicated TX IQLOCAL IDX values */
 727                                 /* per subband, as derived from 43602A1 MCH5 */
 728 #define BFL_SROM11_EXTLNA_5GHz  0x10000000  /* Board has an external LNA in 5GHz band */
 729 #define BFL_SROM11_GAINBOOSTA01 0x20000000  /* 5g Gainboost for core0 and core1 */
 730 #define BFL2_SROM11_APLL_WAR    0x00000002  /* Flag to implement alternative A-band PLL settings */
 731 #define BFL2_SROM11_ANAPACTRL_2G  0x00100000  /* 2G ext PAs are ctrl-ed by analog PA ctrl lines */
 732 #define BFL2_SROM11_ANAPACTRL_5G  0x00200000  /* 5G ext PAs are ctrl-ed by analog PA ctrl lines */
 733 #define BFL2_SROM11_SINGLEANT_CCK       0x00001000  /* Tx CCK pkts on Ant 0 only */
 734 #define BFL2_SROM11_EPA_ON_DURING_TXIQLOCAL    0x00020000  /* Keep ext. PA's on in TX IQLO CAL */
 735
 736 /* boardflags3 */
 737 #define BFL3_FEMCTRL_SUB          0x00000007  /* acphy, subrevs of femctrl on top of srom_femctrl */
 738 #define BFL3_RCAL_WAR             0x00000008  /* acphy, rcal war active on this board (4335a0) */
 739 #define BFL3_TXGAINTBLID          0x00000070  /* acphy, txgain table id */
 740 #define BFL3_TXGAINTBLID_SHIFT    0x4         /* acphy, txgain table id shift bit */
 741 #define BFL3_TSSI_DIV_WAR         0x00000080  /* acphy, Seperate paparam for 20/40/80 */
 742 #define BFL3_TSSI_DIV_WAR_SHIFT   0x7         /* acphy, Seperate paparam for 20/40/80 shift bit */
 743 #define BFL3_FEMTBL_FROM_NVRAM    0x00000100  /* acphy, femctrl table is read from nvram */
 744 #define BFL3_FEMTBL_FROM_NVRAM_SHIFT 0x8         /* acphy, femctrl table is read from nvram */
 745 #define BFL3_AGC_CFG_2G           0x00000200  /* acphy, gain control configuration for 2G */
 746 #define BFL3_AGC_CFG_5G           0x00000400  /* acphy, gain control configuration for 5G */
 747 #define BFL3_PPR_BIT_EXT          0x00000800  /* acphy, bit position for 1bit extension for ppr */
 748 #define BFL3_PPR_BIT_EXT_SHIFT    11          /* acphy, bit shift for 1bit extension for ppr */
 749 #define BFL3_BBPLL_SPR_MODE_DIS   0x00001000  /* acphy, disables bbpll spur modes */
 750 #define BFL3_RCAL_OTP_VAL_EN      0x00002000  /* acphy, to read rcal_trim value from otp */
 751 #define BFL3_2GTXGAINTBL_BLANK    0x00004000  /* acphy, blank the first X ticks of 2g gaintbl */
 752 #define BFL3_2GTXGAINTBL_BLANK_SHIFT 14       /* acphy, blank the first X ticks of 2g gaintbl */
 753 #define BFL3_5GTXGAINTBL_BLANK    0x00008000  /* acphy, blank the first X ticks of 5g gaintbl */
 754 #define BFL3_5GTXGAINTBL_BLANK_SHIFT 15       /* acphy, blank the first X ticks of 5g gaintbl */
 755 #define BFL3_PHASETRACK_MAX_ALPHABETA     0x00010000  /* acphy, to max out alpha,beta to 511 */
 756 #define BFL3_PHASETRACK_MAX_ALPHABETA_SHIFT 16       /* acphy, to max out alpha,beta to 511 */
 757 /* acphy, to use backed off gaintbl for lte-coex */
 758 #define BFL3_LTECOEX_GAINTBL_EN           0x00060000
 759 /* acphy, to use backed off gaintbl for lte-coex */
 760 #define BFL3_LTECOEX_GAINTBL_EN_SHIFT 17
 761 #define BFL3_5G_SPUR_WAR          0x00080000  /* acphy, enable spur WAR in 5G band */
 762 #define BFL3_1X1_RSDB_ANT         0x01000000  /* to find if 2-ant RSDB board or 1-ant RSDB board */
 763 #define BFL3_1X1_RSDB_ANT_SHIFT           24
 764
 765 /* acphy: lpmode2g and lpmode_5g related boardflags */
 766 #define BFL3_ACPHY_LPMODE_2G      0x00300000  /* bits 20:21 for lpmode_2g choice */
 767 #define BFL3_ACPHY_LPMODE_2G_SHIFT        20
 768
 769 #define BFL3_ACPHY_LPMODE_5G      0x00C00000  /* bits 22:23 for lpmode_5g choice */
 770 #define BFL3_ACPHY_LPMODE_5G_SHIFT        22
 771
 772 #define BFL3_EXT_LPO_ISCLOCK      0x02000000  /* External LPO is clock, not x-tal */
 773 #define BFL3_FORCE_INT_LPO_SEL    0x04000000  /* Force internal lpo */
 774 #define BFL3_FORCE_EXT_LPO_SEL    0x08000000  /* Force external lpo */
 775
 776 #define BFL3_EN_BRCM_IMPBF        0x10000000  /* acphy, Allow BRCM Implicit TxBF */
 777 #define BFL3_AVVMID_FROM_NVRAM    0x40000000  /* Read Av Vmid from NVRAM  */
 778 #define BFL3_VLIN_EN_FROM_NVRAM    0x80000000  /* Read Vlin En from NVRAM  */
 779
 780 #define BFL3_AVVMID_FROM_NVRAM_SHIFT   30   /* Read Av Vmid from NVRAM  */
 781 #define BFL3_VLIN_EN_FROM_NVRAM_SHIFT   31   /* Enable Vlin  from NVRAM  */
 782
 783 /* boardflags4 for SROM12 */
 784 #define BFL4_SROM12_4dBPAD      (1 << 0)   /* To distinguigh between normal and 4dB pad board */
 785 #define BFL4_SROM12_2G_DETTYPE      (1 << 1)   /* Determine power detector type for 2G */
 786 #define BFL4_SROM12_5G_DETTYPE      (1 << 2)   /* Determine power detector type for 5G */
 787 #define BFL4_4364_HARPOON 0x0100   /* Harpoon module 4364 */
 788 #define BFL4_4364_GODZILLA 0x0200   /* Godzilla module 4364 */
 789
 790
 791 /* papd params */
 792 #define PAPD_TX_ATTN_2G 0xFF
 793 #define PAPD_TX_ATTN_5G 0xFF00
 794 #define PAPD_TX_ATTN_5G_SHIFT 8
 795 #define PAPD_RX_ATTN_2G 0xFF
 796 #define PAPD_RX_ATTN_5G 0xFF00
 797 #define PAPD_RX_ATTN_5G_SHIFT 8
 798 #define PAPD_CAL_IDX_2G 0xFF
 799 #define PAPD_CAL_IDX_5G 0xFF00
 800 #define PAPD_CAL_IDX_5G_SHIFT 8
 801 #define PAPD_BBMULT_2G 0xFF
 802 #define PAPD_BBMULT_5G 0xFF00
 803 #define PAPD_BBMULT_5G_SHIFT 8
 804 #define TIA_GAIN_MODE_2G 0xFF
 805 #define TIA_GAIN_MODE_5G 0xFF00
 806 #define TIA_GAIN_MODE_5G_SHIFT 8
 807 #define PAPD_EPS_OFFSET_2G 0xFFFF
 808 #define PAPD_EPS_OFFSET_5G 0xFFFF0000
 809 #define PAPD_EPS_OFFSET_5G_SHIFT 16
 810 #define PAPD_CALREF_DB_2G 0xFF
 811 #define PAPD_CALREF_DB_5G 0xFF00
 812 #define PAPD_CALREF_DB_5G_SHIFT 8
 813
 814
 815 /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
 816 #define BOARD_GPIO_BTC3W_IN     0x850   /* bit 4 is RF_ACTIVE, bit 6 is STATUS, bit 11 is PRI */
 817 #define BOARD_GPIO_BTC3W_OUT    0x020   /* bit 5 is TX_CONF */
 818 #define BOARD_GPIO_BTCMOD_IN    0x010   /* bit 4 is the alternate BT Coexistence Input */
 819 #define BOARD_GPIO_BTCMOD_OUT   0x020   /* bit 5 is the alternate BT Coexistence Out */
 820 #define BOARD_GPIO_BTC_IN       0x080   /* bit 7 is BT Coexistence Input */
 821 #define BOARD_GPIO_BTC_OUT      0x100   /* bit 8 is BT Coexistence Out */
 822 #define BOARD_GPIO_PACTRL       0x200   /* bit 9 controls the PA on new 4306 boards */
 823 #define BOARD_GPIO_12           0x1000  /* gpio 12 */
 824 #define BOARD_GPIO_13           0x2000  /* gpio 13 */
 825 #define BOARD_GPIO_BTC4_IN      0x0800  /* gpio 11, coex4, in */
 826 #define BOARD_GPIO_BTC4_BT      0x2000  /* gpio 12, coex4, bt active */
 827 #define BOARD_GPIO_BTC4_STAT    0x4000  /* gpio 14, coex4, status */
 828 #define BOARD_GPIO_BTC4_WLAN    0x8000  /* gpio 15, coex4, wlan active */
 829 #define BOARD_GPIO_1_WLAN_PWR   0x02    /* throttle WLAN power on X21 board */
 830 #define BOARD_GPIO_2_WLAN_PWR   0x04    /* throttle WLAN power on X29C board */
 831 #define BOARD_GPIO_3_WLAN_PWR   0x08    /* throttle WLAN power on X28 board */
 832 #define BOARD_GPIO_4_WLAN_PWR   0x10    /* throttle WLAN power on X19 board */
 833 #define BOARD_GPIO_13_WLAN_PWR  0x2000  /* throttle WLAN power on X14 board */
 834
 835 #define GPIO_BTC4W_OUT_4312  0x010  /* bit 4 is BT_IODISABLE */
 836 #define GPIO_BTC4W_OUT_43224  0x020  /* bit 5 is BT_IODISABLE */
 837 #define GPIO_BTC4W_OUT_43224_SHARED  0x0e0  /* bit 5 is BT_IODISABLE */
 838 #define GPIO_BTC4W_OUT_43225  0x0e0  /* bit 5 BT_IODISABLE, bit 6 SW_BT, bit 7 SW_WL */
 839 #define GPIO_BTC4W_OUT_43421  0x020  /* bit 5 is BT_IODISABLE */
 840 #define GPIO_BTC4W_OUT_4313  0x060  /* bit 5 SW_BT, bit 6 SW_WL */
 841 #define GPIO_BTC4W_OUT_4331_SHARED  0x010  /* GPIO 4  */
 842
 843 #define PCI_CFG_GPIO_SCS        0x10    /* PCI config space bit 4 for 4306c0 slow clock source */
 844 #define PCI_CFG_GPIO_HWRAD      0x20    /* PCI config space GPIO 13 for hw radio disable */
 845 #define PCI_CFG_GPIO_XTAL       0x40    /* PCI config space GPIO 14 for Xtal power-up */
 846 #define PCI_CFG_GPIO_PLL        0x80    /* PCI config space GPIO 15 for PLL power-down */
 847
 848 /* power control defines */
 849 #define PLL_DELAY               150             /* us pll on delay */
 850 #define FREF_DELAY              200             /* us fref change delay */
 851 #define MIN_SLOW_CLK            32              /* us Slow clock period */
 852 #define XTAL_ON_DELAY           1000            /* us crystal power-on delay */
 853
 854
 855 /* 43341 Boards */
 856 #define BCM943341WLABGS_SSID    0x062d
 857
 858 /* 43342 Boards */
 859 #define BCM943342FCAGBI_SSID    0x0641
 860
 861 /* 43012 wlbga Board */
 862 #define BCM943012WLREF_SSID     0x07d7
 863
 864 /* 43012 fcbga Board */
 865 #define BCM943012FCREF_SSID     0x07d4
 866
 867 /* 43602 Boards, unclear yet what boards will be created. */
 868 #define BCM943602RSVD1_SSID     0x06a5
 869 #define BCM943602RSVD2_SSID     0x06a6
 870 #define BCM943602X87            0X0133
 871 #define BCM943602X87P2          0X0152
 872 #define BCM943602X87P3          0X0153
 873 #define BCM943602X238           0X0132
 874 #define BCM943602X238D          0X014A
 875 #define BCM943602X238DP2        0X0155
 876 #define BCM943602X238DP3        0X0156
 877 #define BCM943602X100           0x0761
 878 #define BCM943602X100GS         0x0157
 879 #define BCM943602X100P2         0x015A
 880
 881 /* # of GPIO pins */
 882 #define GPIO_NUMPINS            32
 883
 884 /* These values are used by dhd host driver. */
 885 #define RDL_RAM_BASE_4319 0x60000000
 886 #define RDL_RAM_BASE_4329 0x60000000
 887 #define RDL_RAM_SIZE_4319 0x48000
 888 #define RDL_RAM_SIZE_4329  0x48000
 889 #define RDL_RAM_SIZE_43236 0x70000
 890 #define RDL_RAM_BASE_43236 0x60000000
 891 #define RDL_RAM_SIZE_4328 0x60000
 892 #define RDL_RAM_BASE_4328 0x80000000
 893 #define RDL_RAM_SIZE_4322 0x60000
 894 #define RDL_RAM_BASE_4322 0x60000000
 895 #define RDL_RAM_SIZE_4360  0xA0000
 896 #define RDL_RAM_BASE_4360  0x60000000
 897 #define RDL_RAM_SIZE_43242  0x90000
 898 #define RDL_RAM_BASE_43242  0x60000000
 899 #define RDL_RAM_SIZE_43143  0x70000
 900 #define RDL_RAM_BASE_43143  0x60000000
 901 #define RDL_RAM_SIZE_4350  0xC0000
 902 #define RDL_RAM_BASE_4350  0x180800
 903
 904 /* generic defs for nvram "muxenab" bits
 905 * Note: these differ for 4335a0. refer bcmchipc.h for specific mux options.
 906 */
 907 #define MUXENAB_UART            0x00000001
 908 #define MUXENAB_GPIO            0x00000002
 909 #define MUXENAB_ERCX            0x00000004      /* External Radio BT coex */
 910 #define MUXENAB_JTAG            0x00000008
 911 #define MUXENAB_HOST_WAKE       0x00000010      /* configure GPIO for SDIO host_wake */
 912 #define MUXENAB_I2S_EN          0x00000020
 913 #define MUXENAB_I2S_MASTER      0x00000040
 914 #define MUXENAB_I2S_FULL        0x00000080
 915 #define MUXENAB_SFLASH          0x00000100
 916 #define MUXENAB_RFSWCTRL0       0x00000200
 917 #define MUXENAB_RFSWCTRL1       0x00000400
 918 #define MUXENAB_RFSWCTRL2       0x00000800
 919 #define MUXENAB_SECI            0x00001000
 920 #define MUXENAB_BT_LEGACY       0x00002000
 921 #define MUXENAB_HOST_WAKE1      0x00004000      /* configure alternative GPIO for SDIO host_wake */
 922
 923 /* Boot flags */
 924 #define FLASH_KERNEL_NFLASH     0x00000001
 925 #define FLASH_BOOT_NFLASH       0x00000002
 926
 927 #endif /* _BCMDEVS_H */