- OMAP5432
compatible = "ti,omap5432", "ti,omap5"
+- DRA762
+ compatible = "ti,dra762", "ti,dra7"
+
- DRA742
compatible = "ti,dra742", "ti,dra74", "ti,dra7"
ARM/ZTE ARCHITECTURE
M: Jun Nie <jun.nie@linaro.org>
M: Baoyou Xie <baoyou.xie@linaro.org>
+M: Shawn Guo <shawnguo@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
+F: arch/arm/boot/dts/zx2967*
F: arch/arm/mach-zx/
+F: arch/arm64/boot/dts/zte/
F: drivers/clk/zte/
+F: drivers/dma/zx_dma.c
+F: drivers/gpio/gpio-zx.c
+F: drivers/i2c/busses/i2c-zx2967.c
+F: drivers/mmc/host/dw_mmc-zx.*
+F: drivers/pinctrl/zte/
F: drivers/reset/reset-zx2967.c
F: drivers/soc/zte/
+F: drivers/thermal/zx2967_thermal.c
+F: drivers/watchdog/zx2967_wdt.c
F: Documentation/devicetree/bindings/arm/zte.txt
-F: Documentation/devicetree/bindings/clock/zx296702-clk.txt
+F: Documentation/devicetree/bindings/clock/zx2967*.txt
+F: Documentation/devicetree/bindings/dma/zxdma.txt
+F: Documentation/devicetree/bindings/gpio/zx296702-gpio.txt
+F: Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
+F: Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt
+F: Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt
F: Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt
F: Documentation/devicetree/bindings/soc/zte/
-F: include/dt-bindings/soc/zx*.h
+F: Documentation/devicetree/bindings/sound/zte,*.txt
+F: Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
+F: Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt
+F: include/dt-bindings/clock/zx2967*.h
+F: include/dt-bindings/soc/zte,*.h
+F: sound/soc/codecs/zx_aud96p22.c
+F: sound/soc/zte/
ARM/ZYNQ ARCHITECTURE
M: Michal Simek <michal.simek@xilinx.com>
F: drivers/crypto/cavium/cpt/
CAVIUM THUNDERX2 ARM64 SOC
+M: Robert Richter <rrichter@cavium.com>
M: Jayachandran C <jnair@caviumnetworks.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
config DEBUG_OMAP2UART1
bool "OMAP2/3/4 UART1 (omap2/3 sdp boards and some omap3 boards)"
depends on ARCH_OMAP2PLUS
- select DEBUG_OMAP2PLUS_UART
+ select DEBUG_UART_8250
help
This covers at least h4, 2430sdp, 3430sdp, 3630sdp,
omap3 torpedo and 3530 lv som.
config DEBUG_OMAP2UART2
bool "Kernel low-level debugging messages via OMAP2/3/4 UART2"
depends on ARCH_OMAP2PLUS
- select DEBUG_OMAP2PLUS_UART
+ select DEBUG_UART_8250
config DEBUG_OMAP2UART3
bool "Kernel low-level debugging messages via OMAP2 UART3 (n8x0)"
depends on ARCH_OMAP2PLUS
- select DEBUG_OMAP2PLUS_UART
+ select DEBUG_UART_8250
config DEBUG_OMAP3UART3
bool "Kernel low-level debugging messages via OMAP3 UART3 (most omap3 boards)"
depends on ARCH_OMAP2PLUS
- select DEBUG_OMAP2PLUS_UART
+ select DEBUG_UART_8250
help
This covers at least cm_t3x, beagle, crane, devkit8000,
igep00x0, ldp, n900, n9(50), pandora, overo, touchbook,
config DEBUG_OMAP4UART3
bool "Kernel low-level debugging messages via OMAP4/5 UART3 (omap4 blaze, panda, omap5 sevm)"
depends on ARCH_OMAP2PLUS
- select DEBUG_OMAP2PLUS_UART
+ select DEBUG_UART_8250
config DEBUG_OMAP3UART4
bool "Kernel low-level debugging messages via OMAP36XX UART4"
depends on ARCH_OMAP2PLUS
- select DEBUG_OMAP2PLUS_UART
+ select DEBUG_UART_8250
config DEBUG_OMAP4UART4
bool "Kernel low-level debugging messages via OMAP4/5 UART4"
depends on ARCH_OMAP2PLUS
- select DEBUG_OMAP2PLUS_UART
+ select DEBUG_UART_8250
config DEBUG_OMAP7XXUART1
bool "Kernel low-level debugging via OMAP730 UART1"
config DEBUG_TI81XXUART1
bool "Kernel low-level debugging messages via TI81XX UART1 (ti8148evm)"
depends on ARCH_OMAP2PLUS
- select DEBUG_OMAP2PLUS_UART
+ select DEBUG_UART_8250
config DEBUG_TI81XXUART2
bool "Kernel low-level debugging messages via TI81XX UART2"
depends on ARCH_OMAP2PLUS
- select DEBUG_OMAP2PLUS_UART
+ select DEBUG_UART_8250
config DEBUG_TI81XXUART3
bool "Kernel low-level debugging messages via TI81XX UART3 (ti8168evm)"
depends on ARCH_OMAP2PLUS
- select DEBUG_OMAP2PLUS_UART
+ select DEBUG_UART_8250
config DEBUG_AM33XXUART1
bool "Kernel low-level debugging messages via AM33XX UART1"
depends on ARCH_OMAP2PLUS
- select DEBUG_OMAP2PLUS_UART
+ select DEBUG_UART_8250
config DEBUG_ZOOM_UART
bool "Kernel low-level debugging messages via Zoom2/3 UART"
via SCIF2 on Renesas R-Car H1 (R8A7779).
config DEBUG_RCAR_GEN2_SCIF0
- bool "Kernel low-level debugging messages via SCIF0 on R8A7790/R8A7791/R8A7792/R8A7793"
- depends on ARCH_R8A7790 || ARCH_R8A7791 || ARCH_R8A7792 || ARCH_R8A7793
+ bool "Kernel low-level debugging messages via SCIF0 on R-Car Gen2 and RZ/G1"
+ depends on ARCH_R8A7743 || ARCH_R8A7790 || ARCH_R8A7791 || \
+ ARCH_R8A7792 || ARCH_R8A7793
help
Say Y here if you want kernel low-level debugging support
- via SCIF0 on Renesas R-Car H2 (R8A7790), M2-W (R8A7791), V2H
- (R8A7792), or M2-N (R8A7793).
+ via SCIF0 on Renesas RZ/G1M (R8A7743), R-Car H2 (R8A7790),
+ M2-W (R8A7791), V2H (R8A7792), or M2-N (R8A7793).
config DEBUG_RCAR_GEN2_SCIF2
bool "Kernel low-level debugging messages via SCIF2 on R8A7794"
default 0x40090000 if DEBUG_LPC32XX
default 0x40100000 if DEBUG_PXA_UART1
default 0x42000000 if DEBUG_GEMINI
+ default 0x44e09000 if DEBUG_AM33XXUART1
+ default 0x48020000 if DEBUG_OMAP4UART3 || DEBUG_TI81XXUART1
+ default 0x48022000 if DEBUG_TI81XXUART2
+ default 0x48024000 if DEBUG_TI81XXUART3
+ default 0x4806a000 if DEBUG_OMAP2UART1 || DEBUG_OMAP3UART1 || \
+ DEBUG_OMAP4UART1 || DEBUG_OMAP5UART1
+ default 0x4806c000 if DEBUG_OMAP2UART2 || DEBUG_OMAP3UART2 || \
+ DEBUG_OMAP4UART2 || DEBUG_OMAP5UART2
+ default 0x4806e000 if DEBUG_OMAP2UART3 || DEBUG_OMAP4UART4
+ default 0x49020000 if DEBUG_OMAP3UART3
+ default 0x49042000 if DEBUG_OMAP3UART4
default 0x50000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \
DEBUG_S3C2410_UART0)
default 0x50004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \
default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1
default 0xf8ffee00 if DEBUG_AT91_SAM9263_DBGU
default 0xf8fff200 if DEBUG_AT91_RM9200_DBGU
+ default 0xf9e09000 if DEBUG_AM33XXUART1
+ default 0xfa020000 if DEBUG_OMAP4UART3 || DEBUG_TI81XXUART1
+ default 0xfa022000 if DEBUG_TI81XXUART2
+ default 0xfa024000 if DEBUG_TI81XXUART3
+ default 0xfa06a000 if DEBUG_OMAP2UART1 || DEBUG_OMAP3UART1 || \
+ DEBUG_OMAP4UART1 || DEBUG_OMAP5UART1
+ default 0xfa06c000 if DEBUG_OMAP2UART2 || DEBUG_OMAP3UART2 || \
+ DEBUG_OMAP4UART2 || DEBUG_OMAP5UART2
+ default 0xfa06e000 if DEBUG_OMAP2UART3 || DEBUG_OMAP4UART4
default 0xfa71e000 if DEBUG_QCOM_UARTDM
default 0xfb002000 if DEBUG_CNS3XXX
default 0xfb009000 if DEBUG_REALVIEW_STD_PORT
default 0xfb00c000 if DEBUG_AT91_SAMA5D4_USART3
+ default 0xfb020000 if DEBUG_OMAP3UART3
+ default 0xfb042000 if DEBUG_OMAP3UART4
default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT
default 0xfc705000 if DEBUG_ZTE_ZX
default 0xfcfe8600 if DEBUG_BCM63XX_UART
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
+ ti,dp83867-rxctrl-strap-quirk;
};
dp83867_1: ethernet-phy@3 {
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
+ ti,dp83867-rxctrl-strap-quirk;
};
};
ti,min-output-impedance;
interrupt-parent = <&gpio6>;
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+ ti,dp83867-rxctrl-strap-quirk;
};
dp83867_1: ethernet-phy@3 {
ti,min-output-impedance;
interrupt-parent = <&gpio6>;
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+ ti,dp83867-rxctrl-strap-quirk;
};
};
#include <linux/serial_reg.h>
-/* OMAP2 serial ports */
-#define OMAP2_UART1_BASE 0x4806a000
-#define OMAP2_UART2_BASE 0x4806c000
-#define OMAP2_UART3_BASE 0x4806e000
-
-/* OMAP3 serial ports */
-#define OMAP3_UART1_BASE OMAP2_UART1_BASE
-#define OMAP3_UART2_BASE OMAP2_UART2_BASE
-#define OMAP3_UART3_BASE 0x49020000
-#define OMAP3_UART4_BASE 0x49042000 /* Only on 36xx */
-#define OMAP3_UART4_AM35XX_BASE 0x4809E000 /* Only on AM35xx */
-
-/* OMAP4 serial ports */
-#define OMAP4_UART1_BASE OMAP2_UART1_BASE
-#define OMAP4_UART2_BASE OMAP2_UART2_BASE
-#define OMAP4_UART3_BASE 0x48020000
-#define OMAP4_UART4_BASE 0x4806e000
-
-/* TI81XX serial ports */
-#define TI81XX_UART1_BASE 0x48020000
-#define TI81XX_UART2_BASE 0x48022000
-#define TI81XX_UART3_BASE 0x48024000
-
-/* AM3505/3517 UART4 */
-#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
-
-/* AM33XX serial port */
-#define AM33XX_UART1_BASE 0x44E09000
-
-/* OMAP5 serial ports */
-#define OMAP5_UART1_BASE OMAP2_UART1_BASE
-#define OMAP5_UART2_BASE OMAP2_UART2_BASE
-#define OMAP5_UART3_BASE OMAP4_UART3_BASE
-#define OMAP5_UART4_BASE OMAP4_UART4_BASE
-#define OMAP5_UART5_BASE 0x48066000
-#define OMAP5_UART6_BASE 0x48068000
-
/* External port on Zoom2/3 */
#define ZOOM_UART_BASE 0x10000000
#define ZOOM_UART_VIRT 0xfa400000
bne 100f @ already configured
/* Configure the UART offset from the phys/virt base */
-#ifdef CONFIG_DEBUG_OMAP2UART1
- mov \rp, #UART_OFFSET(OMAP2_UART1_BASE) @ omap2/3/4
- b 98f
-#endif
-#ifdef CONFIG_DEBUG_OMAP2UART2
- mov \rp, #UART_OFFSET(OMAP2_UART2_BASE) @ omap2/3/4
- b 98f
-#endif
-#ifdef CONFIG_DEBUG_OMAP2UART3
- mov \rp, #UART_OFFSET(OMAP2_UART3_BASE)
- b 98f
-#endif
-#ifdef CONFIG_DEBUG_OMAP3UART3
- mov \rp, #UART_OFFSET(OMAP3_UART1_BASE)
- add \rp, \rp, #0x00fb0000
- add \rp, \rp, #0x00006000 @ OMAP3_UART3_BASE
- b 98f
-#endif
-#ifdef CONFIG_DEBUG_OMAP4UART3
- mov \rp, #UART_OFFSET(OMAP4_UART3_BASE)
- b 98f
-#endif
-#ifdef CONFIG_DEBUG_OMAP3UART4
- mov \rp, #UART_OFFSET(OMAP3_UART1_BASE)
- add \rp, \rp, #0x00fb0000
- add \rp, \rp, #0x00028000 @ OMAP3_UART4_BASE
- b 98f
-#endif
-#ifdef CONFIG_DEBUG_OMAP4UART4
- mov \rp, #UART_OFFSET(OMAP4_UART4_BASE)
- b 98f
-#endif
-#ifdef CONFIG_DEBUG_TI81XXUART1
- mov \rp, #UART_OFFSET(TI81XX_UART1_BASE)
- b 98f
-#endif
-#ifdef CONFIG_DEBUG_TI81XXUART2
- mov \rp, #UART_OFFSET(TI81XX_UART2_BASE)
- b 98f
-#endif
-#ifdef CONFIG_DEBUG_TI81XXUART3
- mov \rp, #UART_OFFSET(TI81XX_UART3_BASE)
- b 98f
-#endif
-#ifdef CONFIG_DEBUG_AM33XXUART1
- ldr \rp, =AM33XX_UART1_BASE
- and \rp, \rp, #0x00ffffff
- b 97f
-#endif
#ifdef CONFIG_DEBUG_ZOOM_UART
ldr \rp, =ZOOM_UART_BASE
str \rp, [\tmp, #0] @ omap_uart_phys
#endif
b 10b
- /* AM33XX: Store both phys and virt address for the uart */
-97: add \rp, \rp, #0x44000000 @ phys base
- str \rp, [\tmp, #0] @ omap_uart_phys
- sub \rp, \rp, #0x44000000 @ phys base
- add \rp, \rp, #0xf9000000 @ virt base
- str \rp, [\tmp, #4] @ omap_uart_virt
- mov \rp, #(UART_LSR << OMAP_PORT_SHIFT)
- str \rp, [\tmp, #8] @ omap_uart_lsr
-
- b 10b
-
- /* Store both phys and virt address for the uart */
-98: add \rp, \rp, #0x48000000 @ phys base
- str \rp, [\tmp, #0] @ omap_uart_phys
- sub \rp, \rp, #0x48000000 @ phys base
- add \rp, \rp, #0xfa000000 @ virt base
- str \rp, [\tmp, #4] @ omap_uart_virt
- mov \rp, #(UART_LSR << OMAP_PORT_SHIFT)
- str \rp, [\tmp, #8] @ omap_uart_lsr
-
- b 10b
-
.align
99: .word .
.word omap_uart_phys
ops = arm_cpuidle_get_ops(enable_method);
if (!ops) {
- pr_warn("%s: unsupported enable-method property: %s\n",
- dn->full_name, enable_method);
+ pr_warn("%pOF: unsupported enable-method property: %s\n",
+ dn, enable_method);
return -EOPNOTSUPP;
}
if (of_node_cmp(cpu->type, "cpu"))
continue;
- pr_debug(" * %s...\n", cpu->full_name);
+ pr_debug(" * %pOF...\n", cpu);
/*
* A device tree containing CPU nodes with missing "reg"
* properties is considered invalid to build the
*/
cell = of_get_property(cpu, "reg", &prop_bytes);
if (!cell || prop_bytes < sizeof(*cell)) {
- pr_debug(" * %s missing reg property\n",
- cpu->full_name);
+ pr_debug(" * %pOF missing reg property\n", cpu);
of_node_put(cpu);
return;
}
rate = of_get_property(cn, "clock-frequency", &len);
if (!rate || len != 4) {
- pr_err("%s missing clock-frequency property\n",
- cn->full_name);
+ pr_err("%pOF missing clock-frequency property\n", cn);
continue;
}
.enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
.set_rate = set_keytchclk_rate,
};
+static struct clk clk_adc = {
+ .parent = &clk_xtali,
+ .sw_locked = 1,
+ .enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV,
+ .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_TSEN,
+ .set_rate = set_keytchclk_rate,
+};
static struct clk clk_spi = {
.parent = &clk_xtali,
.rate = EP93XX_EXT_CLK_RATE,
INIT_CK(NULL, "pll2", &clk_pll2),
INIT_CK("ohci-platform", NULL, &clk_usb_host),
INIT_CK("ep93xx-keypad", NULL, &clk_keypad),
+ INIT_CK("ep93xx-adc", NULL, &clk_adc),
INIT_CK("ep93xx-fb", NULL, &clk_video),
INIT_CK("ep93xx-spi.0", NULL, &clk_spi),
INIT_CK("ep93xx-i2s", "mclk", &clk_i2s_mclk),
}
EXPORT_SYMBOL(ep93xx_ide_release_gpio);
+/*************************************************************************
+ * EP93xx ADC
+ *************************************************************************/
+static struct resource ep93xx_adc_resources[] = {
+ DEFINE_RES_MEM(EP93XX_ADC_PHYS_BASE, 0x28),
+ DEFINE_RES_IRQ(IRQ_EP93XX_TOUCH),
+};
+
+static struct platform_device ep93xx_adc_device = {
+ .name = "ep93xx-adc",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(ep93xx_adc_resources),
+ .resource = ep93xx_adc_resources,
+};
+
+void __init ep93xx_register_adc(void)
+{
+ /* Power up ADC, deactivate Touch Screen Controller */
+ ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_TIN,
+ EP93XX_SYSCON_DEVCFG_ADCPD);
+
+ platform_device_register(&ep93xx_adc_device);
+}
+
/*************************************************************************
* EP93xx Security peripheral
*************************************************************************/
edb93xx_register_pwm();
edb93xx_register_fb();
edb93xx_register_ide();
+ ep93xx_register_adc();
}
void ep93xx_i2s_release(void);
void ep93xx_register_ac97(void);
void ep93xx_register_ide(void);
+void ep93xx_register_adc(void);
int ep93xx_ide_acquire_gpio(struct platform_device *pdev);
void ep93xx_ide_release_gpio(struct platform_device *pdev);
#define EP93XX_KEY_MATRIX_PHYS_BASE EP93XX_APB_PHYS(0x000f0000)
#define EP93XX_KEY_MATRIX_BASE EP93XX_APB_IOMEM(0x000f0000)
+#define EP93XX_ADC_PHYS_BASE EP93XX_APB_PHYS(0x00100000)
#define EP93XX_ADC_BASE EP93XX_APB_IOMEM(0x00100000)
#define EP93XX_TOUCHSCREEN_BASE EP93XX_APB_IOMEM(0x00100000)
struct irq_domain *parent_domain, *domain;
if (!parent) {
- pr_err("%s: no parent, giving up\n", node->full_name);
+ pr_err("%pOF: no parent, giving up\n", node);
return -ENODEV;
}
parent_domain = irq_find_host(parent);
if (!parent_domain) {
- pr_err("%s: unable to obtain parent domain\n", node->full_name);
+ pr_err("%pOF: unable to obtain parent domain\n", node);
return -ENXIO;
}
pmu_base_addr = of_iomap(node, 0);
if (!pmu_base_addr) {
- pr_err("%s: failed to find exynos pmu register\n",
- node->full_name);
+ pr_err("%pOF: failed to find exynos pmu register\n", node);
return -ENOMEM;
}
menuconfig ARCH_GEMINI
bool "Cortina Systems Gemini"
depends on ARCH_MULTI_V4
+ select ARCH_HAS_RESET_CONTROLLER
+ select ARM_AMBA
select ARM_APPENDED_DTB # Old Redboot bootloaders deployed
+ select COMMON_CLK_GEMINI
select FARADAY_FTINTC010
select FTTMR010_TIMER
select GPIO_FTGPIO010
select GPIOLIB
+ select PINCTRL
+ select PINCTRL_GEMINI
select POWER_RESET
select POWER_RESET_GEMINI_POWEROFF
select POWER_RESET_SYSCON
virt = ioremap(start_addr, PAGE_SIZE);
- writel_relaxed(0xe51ff004, virt); /* ldr pc, [rc, #-4] */
+ writel_relaxed(0xe51ff004, virt); /* ldr pc, [pc, #-4] */
writel_relaxed(jump_addr, virt + 4); /* pc jump phy address */
iounmap(virt);
}
int i;
if (!parent) {
- pr_err("%s: no parent, giving up\n", node->full_name);
+ pr_err("%pOF: no parent, giving up\n", node);
return -ENODEV;
}
parent_domain = irq_find_host(parent);
if (!parent_domain) {
- pr_err("%s: unable to obtain parent domain\n", node->full_name);
+ pr_err("%pOF: unable to obtain parent domain\n", node);
return -ENXIO;
}
select ARM_ERRATA_720789
select ARM_ERRATA_753970
select ARM_GIC
+ select ARM_GLOBAL_TIMER
+ select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
select ARMADA_370_XP_IRQ
select ARMADA_38X_CLK
select HAVE_ARM_SCU
clk_prepare_enable(clk);
/* store MAC address register contents in local-mac-address */
- pr_err(FW_INFO "%s: local-mac-address is not set\n",
- np->full_name);
+ pr_err(FW_INFO "%pOF: local-mac-address is not set\n", np);
pmac = kzalloc(sizeof(*pmac) + 6, GFP_KERNEL);
if (!pmac)
select OMAP_INTERCONNECT_BARRIER
select PM_OPP if PM
select ZONE_DMA if ARM_LPAE
+ select PINCTRL_TI_IODELAY if OF && PINCTRL
config ARCH_OMAP2PLUS
bool
#ifdef CONFIG_SOC_DRA7XX
static const char *const dra74x_boards_compat[] __initconst = {
+ "ti,dra762",
"ti,am5728",
"ti,am5726",
"ti,dra742",
return errata;
}
-static const struct dma_slave_map omap24xx_sdma_map[] = {
- { "omap-gpmc", "rxtx", SDMA_FILTER_PARAM(4) },
- { "omap-aes", "tx", SDMA_FILTER_PARAM(9) },
- { "omap-aes", "rx", SDMA_FILTER_PARAM(10) },
- { "omap-sham", "rx", SDMA_FILTER_PARAM(13) },
- { "omap2_mcspi.2", "tx0", SDMA_FILTER_PARAM(15) },
- { "omap2_mcspi.2", "rx0", SDMA_FILTER_PARAM(16) },
- { "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(17) },
- { "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(18) },
- { "omap-mcbsp.4", "tx", SDMA_FILTER_PARAM(19) },
- { "omap-mcbsp.4", "rx", SDMA_FILTER_PARAM(20) },
- { "omap-mcbsp.5", "tx", SDMA_FILTER_PARAM(21) },
- { "omap-mcbsp.5", "rx", SDMA_FILTER_PARAM(22) },
- { "omap2_mcspi.2", "tx1", SDMA_FILTER_PARAM(23) },
- { "omap2_mcspi.2", "rx1", SDMA_FILTER_PARAM(24) },
- { "omap_i2c.1", "tx", SDMA_FILTER_PARAM(27) },
- { "omap_i2c.1", "rx", SDMA_FILTER_PARAM(28) },
- { "omap_i2c.2", "tx", SDMA_FILTER_PARAM(29) },
- { "omap_i2c.2", "rx", SDMA_FILTER_PARAM(30) },
- { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(31) },
- { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(32) },
- { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(33) },
- { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(34) },
- { "omap2_mcspi.0", "tx0", SDMA_FILTER_PARAM(35) },
- { "omap2_mcspi.0", "rx0", SDMA_FILTER_PARAM(36) },
- { "omap2_mcspi.0", "tx1", SDMA_FILTER_PARAM(37) },
- { "omap2_mcspi.0", "rx1", SDMA_FILTER_PARAM(38) },
- { "omap2_mcspi.0", "tx2", SDMA_FILTER_PARAM(39) },
- { "omap2_mcspi.0", "rx2", SDMA_FILTER_PARAM(40) },
- { "omap2_mcspi.0", "tx3", SDMA_FILTER_PARAM(41) },
- { "omap2_mcspi.0", "rx3", SDMA_FILTER_PARAM(42) },
- { "omap2_mcspi.1", "tx0", SDMA_FILTER_PARAM(43) },
- { "omap2_mcspi.1", "rx0", SDMA_FILTER_PARAM(44) },
- { "omap2_mcspi.1", "tx1", SDMA_FILTER_PARAM(45) },
- { "omap2_mcspi.1", "rx1", SDMA_FILTER_PARAM(46) },
- { "omap_hsmmc.1", "tx", SDMA_FILTER_PARAM(47) },
- { "omap_hsmmc.1", "rx", SDMA_FILTER_PARAM(48) },
- { "omap_uart.0", "tx", SDMA_FILTER_PARAM(49) },
- { "omap_uart.0", "rx", SDMA_FILTER_PARAM(50) },
- { "omap_uart.1", "tx", SDMA_FILTER_PARAM(51) },
- { "omap_uart.1", "rx", SDMA_FILTER_PARAM(52) },
- { "omap_uart.2", "tx", SDMA_FILTER_PARAM(53) },
- { "omap_uart.2", "rx", SDMA_FILTER_PARAM(54) },
- { "omap_hsmmc.0", "tx", SDMA_FILTER_PARAM(61) },
- { "omap_hsmmc.0", "rx", SDMA_FILTER_PARAM(62) },
-
- /* external DMA requests when tusb6010 is used */
- { "musb-tusb", "dmareq0", SDMA_FILTER_PARAM(2) },
- { "musb-tusb", "dmareq1", SDMA_FILTER_PARAM(3) },
- { "musb-tusb", "dmareq2", SDMA_FILTER_PARAM(14) }, /* OMAP2420 only */
- { "musb-tusb", "dmareq3", SDMA_FILTER_PARAM(15) }, /* OMAP2420 only */
- { "musb-tusb", "dmareq4", SDMA_FILTER_PARAM(16) }, /* OMAP2420 only */
- { "musb-tusb", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */
-};
-
static const struct dma_slave_map omap24xx_sdma_dt_map[] = {
/* external DMA requests when tusb6010 is used */
{ "musb-hdrc.1.auto", "dmareq0", SDMA_FILTER_PARAM(2) },
{ "musb-hdrc.1.auto", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */
};
-static const struct dma_slave_map omap3xxx_sdma_map[] = {
- { "omap-gpmc", "rxtx", SDMA_FILTER_PARAM(4) },
- { "omap2_mcspi.2", "tx0", SDMA_FILTER_PARAM(15) },
- { "omap2_mcspi.2", "rx0", SDMA_FILTER_PARAM(16) },
- { "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(17) },
- { "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(18) },
- { "omap-mcbsp.4", "tx", SDMA_FILTER_PARAM(19) },
- { "omap-mcbsp.4", "rx", SDMA_FILTER_PARAM(20) },
- { "omap-mcbsp.5", "tx", SDMA_FILTER_PARAM(21) },
- { "omap-mcbsp.5", "rx", SDMA_FILTER_PARAM(22) },
- { "omap2_mcspi.2", "tx1", SDMA_FILTER_PARAM(23) },
- { "omap2_mcspi.2", "rx1", SDMA_FILTER_PARAM(24) },
- { "omap_i2c.3", "tx", SDMA_FILTER_PARAM(25) },
- { "omap_i2c.3", "rx", SDMA_FILTER_PARAM(26) },
- { "omap_i2c.1", "tx", SDMA_FILTER_PARAM(27) },
- { "omap_i2c.1", "rx", SDMA_FILTER_PARAM(28) },
- { "omap_i2c.2", "tx", SDMA_FILTER_PARAM(29) },
- { "omap_i2c.2", "rx", SDMA_FILTER_PARAM(30) },
- { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(31) },
- { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(32) },
- { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(33) },
- { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(34) },
- { "omap2_mcspi.0", "tx0", SDMA_FILTER_PARAM(35) },
- { "omap2_mcspi.0", "rx0", SDMA_FILTER_PARAM(36) },
- { "omap2_mcspi.0", "tx1", SDMA_FILTER_PARAM(37) },
- { "omap2_mcspi.0", "rx1", SDMA_FILTER_PARAM(38) },
- { "omap2_mcspi.0", "tx2", SDMA_FILTER_PARAM(39) },
- { "omap2_mcspi.0", "rx2", SDMA_FILTER_PARAM(40) },
- { "omap2_mcspi.0", "tx3", SDMA_FILTER_PARAM(41) },
- { "omap2_mcspi.0", "rx3", SDMA_FILTER_PARAM(42) },
- { "omap2_mcspi.1", "tx0", SDMA_FILTER_PARAM(43) },
- { "omap2_mcspi.1", "rx0", SDMA_FILTER_PARAM(44) },
- { "omap2_mcspi.1", "tx1", SDMA_FILTER_PARAM(45) },
- { "omap2_mcspi.1", "rx1", SDMA_FILTER_PARAM(46) },
- { "omap_hsmmc.1", "tx", SDMA_FILTER_PARAM(47) },
- { "omap_hsmmc.1", "rx", SDMA_FILTER_PARAM(48) },
- { "omap_uart.0", "tx", SDMA_FILTER_PARAM(49) },
- { "omap_uart.0", "rx", SDMA_FILTER_PARAM(50) },
- { "omap_uart.1", "tx", SDMA_FILTER_PARAM(51) },
- { "omap_uart.1", "rx", SDMA_FILTER_PARAM(52) },
- { "omap_uart.2", "tx", SDMA_FILTER_PARAM(53) },
- { "omap_uart.2", "rx", SDMA_FILTER_PARAM(54) },
- { "omap_hsmmc.0", "tx", SDMA_FILTER_PARAM(61) },
- { "omap_hsmmc.0", "rx", SDMA_FILTER_PARAM(62) },
- { "omap-aes", "tx", SDMA_FILTER_PARAM(65) },
- { "omap-aes", "rx", SDMA_FILTER_PARAM(66) },
- { "omap-sham", "rx", SDMA_FILTER_PARAM(69) },
- { "omap2_mcspi.3", "tx0", SDMA_FILTER_PARAM(70) },
- { "omap2_mcspi.3", "rx0", SDMA_FILTER_PARAM(71) },
- { "omap_hsmmc.2", "tx", SDMA_FILTER_PARAM(77) },
- { "omap_hsmmc.2", "rx", SDMA_FILTER_PARAM(78) },
- { "omap_uart.3", "tx", SDMA_FILTER_PARAM(81) },
- { "omap_uart.3", "rx", SDMA_FILTER_PARAM(82) },
-};
-
static struct omap_system_dma_plat_info dma_plat_info __initdata = {
.reg_map = reg_map,
.channel_stride = 0x60,
p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
p.errata = configure_dma_errata();
- if (!of_have_populated_dt()) {
- if (soc_is_omap24xx()) {
- p.slave_map = omap24xx_sdma_map;
- p.slavecnt = ARRAY_SIZE(omap24xx_sdma_map);
- } else if (soc_is_omap34xx() || soc_is_omap3630()) {
- p.slave_map = omap3xxx_sdma_map;
- p.slavecnt = ARRAY_SIZE(omap3xxx_sdma_map);
- } else {
- pr_err("%s: The legacy DMA map is not provided!\n",
- __func__);
- return -ENODEV;
- }
- } else {
- if (soc_is_omap24xx()) {
- /* DMA slave map for drivers not yet converted to DT */
- p.slave_map = omap24xx_sdma_dt_map;
- p.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map);
- }
+ if (soc_is_omap24xx()) {
+ /* DMA slave map for drivers not yet converted to DT */
+ p.slave_map = omap24xx_sdma_dt_map;
+ p.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map);
}
pdev = omap_device_build(name, 0, oh, &p, sizeof(p));
static int __init omap2_system_dma_init(void)
{
- struct platform_device *pdev;
- int res;
-
- res = omap_hwmod_for_each_by_class("dma",
+ return omap_hwmod_for_each_by_class("dma",
omap2_system_dma_init_dev, NULL);
- if (res)
- return res;
-
- if (of_have_populated_dt())
- return res;
-
- pdev = platform_device_register_full(&omap_dma_dev_info);
- if (IS_ERR(pdev))
- return PTR_ERR(pdev);
-
- return res;
}
omap_arch_initcall(omap2_system_dma_init);
hawkeye = (idcode >> 12) & 0xffff;
rev = (idcode >> 28) & 0xff;
switch (hawkeye) {
+ case 0xbb50:
+ switch (rev) {
+ case 0:
+ default:
+ omap_revision = DRA762_REV_ES1_0;
+ break;
+ }
+ break;
+
case 0xb990:
switch (rev) {
case 0:
c = &omap443x_cfg;
else if (soc_is_omap446x())
c = &omap446x_cfg;
- else if (soc_is_dra74x() || soc_is_omap54xx())
+ else if (soc_is_dra74x() || soc_is_omap54xx() || soc_is_dra76x())
c = &omap5_cfg;
if (!c) {
cfg.startup_addr = c->startup_addr;
cfg.wakeupgen_base = omap_get_wakeupgen_base();
- if (soc_is_dra74x() || soc_is_omap54xx()) {
+ if (soc_is_dra74x() || soc_is_omap54xx() || soc_is_dra76x()) {
if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
cfg.startup_addr = omap5_secondary_hyp_startup;
omap5_erratum_workaround_801819();
u32 val;
if (!parent) {
- pr_err("%s: no parent, giving up\n", node->full_name);
+ pr_err("%pOF: no parent, giving up\n", node);
return -ENODEV;
}
parent_domain = irq_find_host(parent);
if (!parent_domain) {
- pr_err("%s: unable to obtain parent domain\n", node->full_name);
+ pr_err("%pOF: unable to obtain parent domain\n", node);
return -ENXIO;
}
/* Not supported on OMAP4 ES1.0 silicon */
if (!ret && !pm_runtime_status_suspended(dev)) {
if (pm_generic_runtime_suspend(dev) == 0) {
- pm_runtime_set_suspended(dev);
omap_device_idle(pdev);
od->flags |= OMAP_DEVICE_SUSPENDED;
}
if (od->flags & OMAP_DEVICE_SUSPENDED) {
od->flags &= ~OMAP_DEVICE_SUSPENDED;
omap_device_enable(pdev);
- /*
- * XXX: we run before core runtime pm has resumed itself. At
- * this point in time, we just restore the runtime pm state and
- * considering symmetric operations in resume, we donot expect
- * to fail. If we failed, something changed in core runtime_pm
- * framework OR some device driver messed things up, hence, WARN
- */
- WARN(pm_runtime_set_active(dev),
- "Could not set %s runtime state active\n", dev_name(dev));
pm_generic_runtime_resume(dev);
}
if (mem)
pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
else
- pr_err("omap_hwmod: %s: Missing dt reg%i for %s\n",
- oh->name, index, np->full_name);
+ pr_err("omap_hwmod: %s: Missing dt reg%i for %pOF\n",
+ oh->name, index, np);
return -ENXIO;
}
};
/* SoC variant specific hwmod links */
+static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = {
+ &dra7xx_l4_per3__usb_otg_ss4,
+ NULL,
+};
+
static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_per3__usb_otg_ss4,
NULL,
ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
else if (!ret && soc_is_dra72x())
ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
+ else if (!ret && soc_is_dra76x())
+ ret = omap_hwmod_register_links(dra76x_hwmod_ocp_ifs);
if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
- /* now for the IPs *NOT* in dra71 */
- if (!ret && !of_machine_is_compatible("ti,dra718"))
+ /* now for the IPs available only in dra74 and dra72 */
+ if (!ret && !of_machine_is_compatible("ti,dra718") && !soc_is_dra76x())
ret = omap_hwmod_register_links(dra74x_dra72x_hwmod_ocp_ifs);
return ret;
}
#endif
+#ifdef CONFIG_SOC_DRA7XX
+static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc1;
+static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc2;
+static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc3;
+
+static void __init dra7x_evm_mmc_quirk(void)
+{
+ if (omap_rev() == DRA752_REV_ES1_1 || omap_rev() == DRA752_REV_ES1_0) {
+ dra7_hsmmc_data_mmc1.version = "rev11";
+ dra7_hsmmc_data_mmc1.max_freq = 96000000;
+
+ dra7_hsmmc_data_mmc2.version = "rev11";
+ dra7_hsmmc_data_mmc2.max_freq = 48000000;
+
+ dra7_hsmmc_data_mmc3.version = "rev11";
+ dra7_hsmmc_data_mmc3.max_freq = 48000000;
+ }
+}
+#endif
+
static struct pcs_pdata pcs_pdata;
void omap_pcs_legacy_init(int irq, void (*rearm)(void))
&omap4_iommu_pdata),
OF_DEV_AUXDATA("ti,omap4-iommu", 0x55082000, "55082000.mmu",
&omap4_iommu_pdata),
+#endif
+#ifdef CONFIG_SOC_DRA7XX
+ OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x4809c000, "4809c000.mmc",
+ &dra7_hsmmc_data_mmc1),
+ OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480b4000, "480b4000.mmc",
+ &dra7_hsmmc_data_mmc2),
+ OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480ad000, "480ad000.mmc",
+ &dra7_hsmmc_data_mmc3),
#endif
/* Common auxdata */
OF_DEV_AUXDATA("pinctrl-single", 0, NULL, &pcs_pdata),
#endif
#ifdef CONFIG_SOC_OMAP5
{ "ti,omap5-uevm", omap5_uevm_legacy_init, },
+#endif
+#ifdef CONFIG_SOC_DRA7XX
+ { "ti,dra7-evm", dra7x_evm_mmc_quirk, },
#endif
{ /* sentinel */ },
};
#include "prcm44xx.h"
#include "prm7xx.h"
#include "prcm_mpu7xx.h"
+#include "soc.h"
/* iva_7xx_pwrdm: IVA-HD power domain */
static struct powerdomain iva_7xx_pwrdm = {
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
+/* custefuse_aon_7xx_pwrdm: Customer efuse controller power domain */
+static struct powerdomain custefuse_aon_7xx_pwrdm = {
+ .name = "custefuse_pwrdm",
+ .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_ON,
+};
+
/* ipu_7xx_pwrdm: Audio back end power domain */
static struct powerdomain ipu_7xx_pwrdm = {
.name = "ipu_pwrdm",
static struct powerdomain *powerdomains_dra7xx[] __initdata = {
&iva_7xx_pwrdm,
&rtc_7xx_pwrdm,
- &custefuse_7xx_pwrdm,
&ipu_7xx_pwrdm,
&dss_7xx_pwrdm,
&l4per_7xx_pwrdm,
NULL
};
+static struct powerdomain *powerdomains_dra76x[] __initdata = {
+ &custefuse_aon_7xx_pwrdm,
+ NULL
+};
+
+static struct powerdomain *powerdomains_dra74x[] __initdata = {
+ &custefuse_7xx_pwrdm,
+ NULL
+};
+
+static struct powerdomain *powerdomains_dra72x[] __initdata = {
+ &custefuse_aon_7xx_pwrdm,
+ NULL
+};
+
void __init dra7xx_powerdomains_init(void)
{
pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
pwrdm_register_pwrdms(powerdomains_dra7xx);
+
+ if (soc_is_dra76x())
+ pwrdm_register_pwrdms(powerdomains_dra76x);
+ else if (soc_is_dra74x())
+ pwrdm_register_pwrdms(powerdomains_dra74x);
+ else if (soc_is_dra72x())
+ pwrdm_register_pwrdms(powerdomains_dra72x);
+
pwrdm_complete_init();
}
np = of_find_matching_node(NULL, omap3_prm_dt_match_table);
if (np) {
irq_num = of_irq_get(np, 0);
- if (irq_num >= 0)
+ if (irq_num > 0)
omap3_prcm_irq_setup.irq = irq_num;
}
* Already have OMAP4 IRQ num. For all other platforms, we need
* IRQ numbers from DT
*/
- if (irq_num < 0 && !(prm_init_data->flags & PRM_IRQ_DEFAULT)) {
+ if (irq_num <= 0 && !(prm_init_data->flags & PRM_IRQ_DEFAULT)) {
if (irq_num == -EPROBE_DEFER)
return irq_num;
}
/* Once OMAP4 DT is filled as well */
- if (irq_num >= 0) {
+ if (irq_num > 0) {
omap4_prcm_irq_setup.irq = irq_num;
omap4_prcm_irq_setup.xlate_irq = NULL;
}
IS_TI_SUBCLASS(814x, 0x814)
IS_AM_SUBCLASS(335x, 0x335)
IS_AM_SUBCLASS(437x, 0x437)
+IS_DRA_SUBCLASS(76x, 0x76)
IS_DRA_SUBCLASS(75x, 0x75)
IS_DRA_SUBCLASS(72x, 0x72)
#define soc_is_omap54xx() 0
#define soc_is_omap543x() 0
#define soc_is_dra7xx() 0
+#define soc_is_dra76x() 0
#define soc_is_dra74x() 0
#define soc_is_dra72x() 0
#if defined(CONFIG_SOC_DRA7XX)
#undef soc_is_dra7xx
+#undef soc_is_dra76x
#undef soc_is_dra74x
#undef soc_is_dra72x
#define soc_is_dra7xx() is_dra7xx()
+#define soc_is_dra76x() is_dra76x()
#define soc_is_dra74x() is_dra75x()
#define soc_is_dra72x() is_dra72x()
#endif
#define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8))
#define DRA7XX_CLASS 0x07000000
+#define DRA762_REV_ES1_0 (DRA7XX_CLASS | (0x62 << 16) | (0x10 << 8))
#define DRA752_REV_ES1_0 (DRA7XX_CLASS | (0x52 << 16) | (0x10 << 8))
#define DRA752_REV_ES1_1 (DRA7XX_CLASS | (0x52 << 16) | (0x11 << 8))
#define DRA752_REV_ES2_0 (DRA7XX_CLASS | (0x52 << 16) | (0x20 << 8))
depends on ARCH_MULTI_V7
select PINCTRL
select PINCTRL_ROCKCHIP
+ select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
select ARCH_HAS_RESET_CONTROLLER
select ARM_AMBA
select ARM_GIC
select ROCKCHIP_TIMER
select ARM_GLOBAL_TIMER
select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
+ select ZONE_DMA if ARM_LPAE
help
Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs
containing the RK2928, RK30xx and RK31xx series.
else
np = of_get_cpu_node(cpu, NULL);
- return of_reset_control_get(np, NULL);
+ return of_reset_control_get_exclusive(np, NULL);
}
static int pmu_set_power_domain(int pd, bool on)
ret = of_address_to_resource(node, 0, &res);
if (ret < 0) {
- pr_err("%s: could not get address for node %s\n",
- __func__, node->full_name);
+ pr_err("%s: could not get address for node %pOF\n",
+ __func__, node);
return ret;
}
config H1940BT
tristate "Control the state of H1940 bluetooth chip"
depends on ARCH_H1940
- select RFKILL
+ depends on RFKILL
help
This is a simple driver that is able to control
the state of built in bluetooth chip on h1940.
return gs;
#endif
-#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
+#if defined(CONFIG_CPU_S3C2412)
return __raw_readl(S3C2412_GSTATUS1);
#else
return 1UL; /* don't look like an 2400 */
#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
-#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
+#if defined(CONFIG_CPU_S3C2412)
#define S3C2412_OSCSET S3C2410_CLKREG(0x18)
#define S3C2412_CLKSRC S3C2410_CLKREG(0x1C)
#define S3C2412_CLKSRC_UREFCLK_EXTCLK (1<<12)
#define S3C2412_CLKSRC_EREFCLK_EXTCLK (1<<14)
-#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
+#endif /* CONFIG_CPU_S3C2412 */
#define S3C2416_CLKDIV2 S3C2410_CLKREG(0x28)
.nr_sets = ARRAY_SIZE(mini2440_nand_sets),
.sets = mini2440_nand_sets,
.ignore_unset_ecc = 1,
- .ecc_mode = NAND_ECC_SOFT,
+ .ecc_mode = NAND_ECC_HW,
};
/* DM9000AEP 10/100 ethernet controller */
&s3c_device_wdt,
&s3c_device_i2c0,
&s3c_device_hsmmc1,
-#ifdef CONFIG_SND_SOC_SMDK2443_WM9710
- &s3c_device_ac97,
-#endif
&s3c2443_device_dma,
};
static void __init smdk2443_machine_init(void)
{
s3c_i2c0_set_platdata(NULL);
-
-#ifdef CONFIG_SND_SOC_SMDK2443_WM9710
- s3c24xx_ac97_setup_gpio(S3C24XX_AC97_GPE0);
-#endif
-
platform_add_devices(smdk2443_devices, ARRAY_SIZE(smdk2443_devices));
smdk_machine_init();
}
#include <mach/regs-gpio.h>
#include <mach/regs-clock.h>
-/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
+/*
+ * S3C24XX_DEBUG_RESUME is dangerous if your bootloader does not
* reset the UART configuration, only enable if you really need this!
-*/
-//#define CONFIG_DEBUG_RESUME
+ */
+//#define S3C24XX_DEBUG_RESUME
.text
str r12, [ r14, #0x54 ]
#endif
-#ifdef CONFIG_DEBUG_RESUME
+#ifdef S3C24XX_DEBUG_RESUME
mov r3, #'L'
strb r3, [ r2, #S3C2410_UTXH ]
1001:
ldrb r14, [ r3, #S3C2410_UTRSTAT ]
tst r14, #S3C2410_UTRSTAT_TXE
beq 1001b
-#endif /* CONFIG_DEBUG_RESUME */
+#endif /* S3C24XX_DEBUG_RESUME */
b cpu_resume
config ARCH_SHMOBILE
bool
-config ARCH_SHMOBILE_MULTI
- bool
-
config PM_RMOBILE
bool
select PM
depends on ARCH_MULTI_V7 && MMU
select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
select ARCH_SHMOBILE
- select ARCH_SHMOBILE_MULTI
select ARM_GIC
select GPIOLIB
select HAVE_ARM_SCU if SMP
*/
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/smp.h>
#include <linux/soc/renesas/rcar-sysc.h>
#include <asm/io.h>
struct device_node *np, *cpus;
bool has_a7 = false;
bool has_a15 = false;
- phys_addr_t boot_vector_addr = ICRAM1;
+ struct resource res;
u32 syscier = 0;
+ int error;
if (once++)
return;
else if (of_machine_is_compatible("renesas,r8a7791"))
syscier = 0x00111003;
+ np = of_find_compatible_node(NULL, NULL, "renesas,smp-sram");
+ if (!np) {
+ /* No smp-sram in DT, fall back to hardcoded address */
+ res = (struct resource)DEFINE_RES_MEM(ICRAM1,
+ shmobile_boot_size);
+ goto map;
+ }
+
+ error = of_address_to_resource(np, 0, &res);
+ if (error) {
+ pr_err("Failed to get smp-sram address: %d\n", error);
+ return;
+ }
+
+map:
/* RAM for jump stub, because BAR requires 256KB aligned address */
- p = ioremap_nocache(boot_vector_addr, shmobile_boot_size);
+ if (res.start & (256 * 1024 - 1) ||
+ resource_size(&res) < shmobile_boot_size) {
+ pr_err("Invalid smp-sram region\n");
+ return;
+ }
+
+ p = ioremap(res.start, resource_size(&res));
+ if (!p)
+ return;
+
memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
iounmap(p);
/* setup reset vectors */
p = ioremap_nocache(RST, 0x63);
- bar = phys_to_sbar(boot_vector_addr);
+ bar = phys_to_sbar(res.start);
if (has_a15) {
writel_relaxed(bar, p + CA15BAR);
writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
return;
}
- pr_debug("Special PM domain %s type %d for %s\n", pd->name, type,
- np->full_name);
+ pr_debug("Special PM domain %s type %d for %pOF\n", pd->name, type, np);
special_pds[num_special_pds].pd = pd;
special_pds[num_special_pds].type = type;
for_each_compatible_node(np, NULL, "renesas,sysc-rmobile") {
base = of_iomap(np, 0);
if (!base) {
- pr_warn("%s cannot map reg 0\n", np->full_name);
+ pr_warn("%pOF cannot map reg 0\n", np);
continue;
}
pmd = of_get_child_by_name(np, "pm-domains");
if (!pmd) {
- pr_warn("%s lacks pm-domains node\n", np->full_name);
+ pr_warn("%pOF lacks pm-domains node\n", np);
continue;
}
#include "common.h"
#include "rcar-gen2.h"
+static const struct of_device_id cpg_matches[] __initconst = {
+ { .compatible = "renesas,rcar-gen2-cpg-clocks", },
+ { .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" },
+ { .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" },
+ { .compatible = "renesas,r8a7791-cpg-mssr", .data = "extal" },
+ { .compatible = "renesas,r8a7793-cpg-mssr", .data = "extal" },
+ { /* sentinel */ }
+};
+
static unsigned int __init get_extal_freq(void)
{
+ const struct of_device_id *match;
struct device_node *cpg, *extal;
u32 freq = 20000000;
+ int idx = 0;
- cpg = of_find_compatible_node(NULL, NULL,
- "renesas,rcar-gen2-cpg-clocks");
+ cpg = of_find_matching_node_and_match(NULL, cpg_matches, &match);
if (!cpg)
return freq;
- extal = of_parse_phandle(cpg, "clocks", 0);
+ if (match->data)
+ idx = of_property_match_string(cpg, "clock-names", match->data);
+ extal = of_parse_phandle(cpg, "clocks", idx);
of_node_put(cpg);
if (!extal)
return freq;
void __iomem *base;
u32 freq;
- if (of_machine_is_compatible("renesas,r8a7792") ||
+ if (of_machine_is_compatible("renesas,r8a7745") ||
+ of_machine_is_compatible("renesas,r8a7792") ||
of_machine_is_compatible("renesas,r8a7794")) {
freq = 260000000 / 8; /* ZS / 8 */
/* CNTVOFF has to be initialized either from non-secure
select ARCH_HAS_RESET_CONTROLLER
select RESET_CONTROLLER
select SOC_BUS
+ select ZONE_DMA if ARM_LPAE
+ select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
help
This enables support for NVIDIA Tegra based systems.
/* deal with the registers that move under the 2412/2413 */
-#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
+#if defined(CONFIG_CPU_S3C2412)
#ifndef __ASSEMBLY__
extern void __iomem *s3c24xx_va_gpio2;
#endif
if (!of_device_is_compatible(np, "ti,am437x-ocp2scp")) {
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
regs = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(regs))
- goto err0;
+ if (IS_ERR(regs)) {
+ ret = PTR_ERR(regs);
+ goto err1;
+ }
pm_runtime_get_sync(&pdev->dev);
reg = readl_relaxed(regs + OCP2SCP_TIMING);
return 0;
+err1:
+ pm_runtime_disable(&pdev->dev);
+
err0:
device_for_each_child(&pdev->dev, NULL, ocp2scp_remove_devices);
static int realview_soc_probe(struct platform_device *pdev)
{
- static struct regmap *syscon_regmap;
+ struct regmap *syscon_regmap;
struct soc_device *soc_dev;
struct soc_device_attribute *soc_dev_attr;
struct device_node *np = pdev->dev.of_node;
#define HSMMC_HAS_HSPE_SUPPORT (1 << 2)
unsigned features;
+ /* string specifying a particular variant of hardware */
+ char *version;
+
int gpio_cd; /* gpio (card detect) */
int gpio_cod; /* gpio (cover detect) */
int gpio_wp; /* gpio (write protect) */
projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / commitdiff