drivers/soc/samsung/cal-if/exynos9610/cmucal-vclk.c

   1 #include "../cmucal.h"
   2 #include "cmucal-node.h"
   3 #include "cmucal-vclk.h"
   4
   5 #include "cmucal-vclklut.h"
   6
   7 /*=================CMUCAL version: S5E9610================================*/
   8
   9 /*=================CLK in each VCLK================================*/
  10
  11
  12 /* DVFS List */
  13 enum clk_id cmucal_vclk_vdd_cpucl0[] = {
  14         PLL_CPUCL0,
  15 };
  16 enum clk_id cmucal_vclk_vdd_cpucl1[] = {
  17         DIV_CLK_CLUSTER1_ACLK,
  18         PLL_CPUCL1,
  19 };
  20 enum clk_id cmucal_vclk_vdd_g3d[] = {
  21         PLL_G3D,
  22 };
  23 enum clk_id cmucal_vclk_vdd_int[] = {
  24         CLKCMU_DISPAUD_DISP,
  25         CLKCMU_FSYS_BUS,
  26         CLKCMU_G2D_MSCL,
  27         CLKCMU_FSYS_MMC_CARD,
  28         CLKCMU_FSYS_MMC_EMBD,
  29         CLKCMU_CORE_BUS,
  30         CLKCMU_CORE_CCI,
  31         CLKCMU_CORE_G3D,
  32         CLKCMU_CAM_BUS,
  33         CLKCMU_VIPX1_BUS,
  34         CLKCMU_ISP_BUS,
  35         CLKCMU_ISP_VRA,
  36         CLKCMU_ISP_GDC,
  37         CLKCMU_G2D_G2D,
  38         CLKCMU_USB_BUS,
  39         CLKCMU_DISPAUD_AUD,
  40         CLKCMU_MFC_MFC,
  41         CLKCMU_MFC_WFD,
  42         CLKCMU_VIPX2_BUS,
  43         MUX_CLKCMU_G2D_MSCL,
  44         MUX_CLKCMU_DISPAUD_DISP,
  45         MUX_CLKCMU_FSYS_BUS,
  46         MUX_CLKCMU_CORE_CCI,
  47         MUX_CLKCMU_CORE_G3D,
  48         MUX_CLKCMU_CORE_BUS,
  49         MUX_CLKCMU_CAM_BUS,
  50         MUX_CLKCMU_VIPX1_BUS,
  51         MUX_CLKCMU_ISP_BUS,
  52         MUX_CLKCMU_ISP_VRA,
  53         MUX_CLKCMU_ISP_GDC,
  54         MUX_CLKCMU_G2D_G2D,
  55         MUX_CLKCMU_CPUCL0_DBG,
  56         MUX_CLKCMU_USB_BUS,
  57         MUX_CLKCMU_DISPAUD_AUD,
  58         MUX_CLKCMU_MFC_MFC,
  59         MUX_CLKCMU_MFC_WFD,
  60         MUX_CLKCMU_VIPX2_BUS,
  61 };
  62 enum clk_id cmucal_vclk_vdd_cam[] = {
  63         DIV_CLK_AUD_AUDIF,
  64 };
  65 enum clk_id cmucal_vclk_vdd_mif[] = {
  66         PLL_MIF,
  67 };
  68
  69 /* SPECIAL List */
  70 enum clk_id cmucal_vclk_clkcmu_shub_bus[] = {
  71         CLKCMU_SHUB_BUS,
  72         MUX_CLKCMU_SHUB_BUS,
  73 };
  74 enum clk_id cmucal_vclk_div_clk_cmgp_adc[] = {
  75         MUX_CLK_CMGP_ADC,
  76         DIV_CLK_CMGP_ADC,
  77 };
  78 enum clk_id cmucal_vclk_div_clk_cmgp_usi01[] = {
  79         DIV_CLK_CMGP_USI01,
  80         MUX_CLK_CMGP_USI01,
  81 };
  82 enum clk_id cmucal_vclk_div_clk_cmgp_usi03[] = {
  83         DIV_CLK_CMGP_USI03,
  84         MUX_CLK_CMGP_USI03,
  85 };
  86 enum clk_id cmucal_vclk_div_clk_cmgp_usi02[] = {
  87         DIV_CLK_CMGP_USI02,
  88         MUX_CLK_CMGP_USI02,
  89 };
  90 enum clk_id cmucal_vclk_div_clk_cmgp_usi00[] = {
  91         DIV_CLK_CMGP_USI00,
  92         MUX_CLK_CMGP_USI00,
  93 };
  94 enum clk_id cmucal_vclk_div_clk_cmgp_usi04[] = {
  95         DIV_CLK_CMGP_USI04,
  96         MUX_CLK_CMGP_USI04,
  97 };
  98 enum clk_id cmucal_vclk_clkcmu_fsys_ufs_embd[] = {
  99         CLKCMU_FSYS_UFS_EMBD,
 100         MUX_CLKCMU_FSYS_UFS_EMBD,
 101 };
 102 enum clk_id cmucal_vclk_div_clk_cmu_cmuref[] = {
 103         MUX_CMU_CMUREF,
 104         DIV_CLK_CMU_CMUREF,
 105         MUX_CLK_CMU_CMUREF,
 106 };
 107 enum clk_id cmucal_vclk_clkcmu_hpm[] = {
 108         CLKCMU_HPM,
 109         MUX_CLKCMU_HPM,
 110 };
 111 enum clk_id cmucal_vclk_clkcmu_peri_ip[] = {
 112         CLKCMU_PERI_IP,
 113         MUX_CLKCMU_PERI_IP,
 114 };
 115 enum clk_id cmucal_vclk_clkcmu_mif_busp[] = {
 116         CLKCMU_MIF_BUSP,
 117         MUX_CLKCMU_MIF_BUSP,
 118 };
 119 enum clk_id cmucal_vclk_clkcmu_apm_bus[] = {
 120         CLKCMU_APM_BUS,
 121         MUX_CLKCMU_APM_BUS,
 122 };
 123 enum clk_id cmucal_vclk_clkcmu_cis_clk1[] = {
 124         CLKCMU_CIS_CLK1,
 125         MUX_CLKCMU_CIS_CLK1,
 126 };
 127 enum clk_id cmucal_vclk_clkcmu_cis_clk3[] = {
 128         CLKCMU_CIS_CLK3,
 129         MUX_CLKCMU_CIS_CLK3,
 130 };
 131 enum clk_id cmucal_vclk_clkcmu_usb_usb30drd[] = {
 132         CLKCMU_USB_USB30DRD,
 133         MUX_CLKCMU_USB_USB30DRD,
 134 };
 135 enum clk_id cmucal_vclk_clkcmu_cis_clk0[] = {
 136         CLKCMU_CIS_CLK0,
 137         MUX_CLKCMU_CIS_CLK0,
 138 };
 139 enum clk_id cmucal_vclk_clkcmu_usb_dpgtc[] = {
 140         CLKCMU_USB_DPGTC,
 141         MUX_CLKCMU_USB_DPGTC,
 142 };
 143 enum clk_id cmucal_vclk_clkcmu_cis_clk2[] = {
 144         CLKCMU_CIS_CLK2,
 145         MUX_CLKCMU_CIS_CLK2,
 146 };
 147 enum clk_id cmucal_vclk_clkcmu_peri_uart[] = {
 148         CLKCMU_PERI_UART,
 149         MUX_CLKCMU_PERI_UART,
 150 };
 151 enum clk_id cmucal_vclk_div_clk_cluster0_pclkdbg[] = {
 152         DIV_CLK_CLUSTER0_PCLKDBG,
 153 };
 154 enum clk_id cmucal_vclk_div_clk_cluster0_aclk[] = {
 155         DIV_CLK_CLUSTER0_ACLK,
 156 };
 157 enum clk_id cmucal_vclk_div_clk_cpucl0_cmuref[] = {
 158         DIV_CLK_CPUCL0_CMUREF,
 159 };
 160 enum clk_id cmucal_vclk_div_clk_cluster0_cntclk[] = {
 161         DIV_CLK_CLUSTER0_CNTCLK,
 162 };
 163 enum clk_id cmucal_vclk_div_clk_cluster1_cntclk[] = {
 164         DIV_CLK_CLUSTER1_CNTCLK,
 165 };
 166 enum clk_id cmucal_vclk_div_clk_cpucl1_cmuref[] = {
 167         DIV_CLK_CPUCL1_CMUREF,
 168 };
 169 enum clk_id cmucal_vclk_div_clk_aud_dsif[] = {
 170         DIV_CLK_AUD_DSIF,
 171 };
 172 enum clk_id cmucal_vclk_div_clk_aud_uaif0[] = {
 173         MUX_CLK_AUD_UAIF0,
 174         DIV_CLK_AUD_UAIF0,
 175 };
 176 enum clk_id cmucal_vclk_div_clk_aud_uaif2[] = {
 177         MUX_CLK_AUD_UAIF2,
 178         DIV_CLK_AUD_UAIF2,
 179 };
 180 enum clk_id cmucal_vclk_div_clk_aud_cpu_pclkdbg[] = {
 181         DIV_CLK_AUD_CPU_PCLKDBG,
 182 };
 183 enum clk_id cmucal_vclk_div_clk_aud_uaif1[] = {
 184         MUX_CLK_AUD_UAIF1,
 185         DIV_CLK_AUD_UAIF1,
 186 };
 187 enum clk_id cmucal_vclk_div_clk_aud_fm[] = {
 188         DIV_CLK_AUD_FM,
 189         MUX_CLK_AUD_FM,
 190         DIV_CLK_AUD_FM_SPDY
 191 };
 192 enum clk_id cmucal_vclk_mux_mif_cmuref[] = {
 193         MUX_MIF_CMUREF,
 194 };
 195 enum clk_id cmucal_vclk_mux_mif1_cmuref[] = {
 196         MUX_MIF1_CMUREF,
 197 };
 198 enum clk_id cmucal_vclk_pll_mif1[] = {
 199         PLL_MIF1,
 200 };
 201 enum clk_id cmucal_vclk_div_clk_peri_spi0[] = {
 202         DIV_CLK_PERI_SPI0,
 203 };
 204 enum clk_id cmucal_vclk_div_clk_peri_spi2[] = {
 205         DIV_CLK_PERI_SPI2,
 206 };
 207 enum clk_id cmucal_vclk_div_clk_peri_usi_i2c[] = {
 208         DIV_CLK_PERI_USI_I2C,
 209 };
 210 enum clk_id cmucal_vclk_div_clk_peri_spi1[] = {
 211         DIV_CLK_PERI_SPI1,
 212 };
 213 enum clk_id cmucal_vclk_div_clk_peri_usi_usi[] = {
 214         DIV_CLK_PERI_USI_USI,
 215 };
 216 enum clk_id cmucal_vclk_div_clk_shub_i2c[] = {
 217         DIV_CLK_SHUB_I2C,
 218         MUX_CLK_SHUB_I2C,
 219 };
 220 enum clk_id cmucal_vclk_div_clk_shub_usi00[] = {
 221         DIV_CLK_SHUB_USI00,
 222         MUX_CLK_SHUB_USI00,
 223 };
 224
 225 /* COMMON List */
 226 enum clk_id cmucal_vclk_blk_apm[] = {
 227         DIV_CLK_APM_BUS,
 228         MUX_CLK_APM_BUS,
 229 };
 230 enum clk_id cmucal_vclk_blk_cam[] = {
 231         DIV_CLK_CAM_BUSP,
 232 };
 233 enum clk_id cmucal_vclk_blk_cmgp[] = {
 234         DIV_CLK_CMGP_I2C,
 235         MUX_CLK_CMGP_I2C,
 236 };
 237 enum clk_id cmucal_vclk_blk_cmu[] = {
 238         AP2CP_SHARED0_PLL_CLK,
 239         CLKCMU_PERI_BUS,
 240         AP2CP_SHARED1_PLL_CLK,
 241         CLKCMU_CPUCL0_DBG,
 242         MUX_CLKCMU_FSYS_MMC_EMBD,
 243         MUX_CLKCMU_PERI_BUS,
 244         MUX_CLKCMU_FSYS_MMC_CARD,
 245         PLL_SHARED0_DIV4,
 246         PLL_SHARED1_DIV4,
 247         PLL_SHARED0_DIV2,
 248         PLL_SHARED0_DIV3,
 249         PLL_SHARED1_DIV2,
 250         PLL_MMC_DIV2,
 251         PLL_SHARED0,
 252         PLL_SHARED1_DIV3,
 253         PLL_MMC,
 254         PLL_SHARED1,
 255 };
 256 enum clk_id cmucal_vclk_blk_core[] = {
 257         DIV_CLK_CORE_BUSP,
 258         MUX_CLK_CORE_GIC,
 259 };
 260 enum clk_id cmucal_vclk_blk_cpucl0[] = {
 261         DIV_CLK_CPUCL0_PCLK,
 262 };
 263 enum clk_id cmucal_vclk_blk_cpucl1[] = {
 264         DIV_CLK_CPUCL1_PCLK,
 265         DIV_CLK_CPUCL1_PCLKDBG,
 266 };
 267 enum clk_id cmucal_vclk_blk_dispaud[] = {
 268         DIV_CLK_AUD_CPU_ACLK,
 269         DIV_CLK_DISPAUD_BUSP,
 270         MUX_CLK_AUD_BUS,
 271         DIV_CLK_AUD_BUS,
 272         PLL_AUD,
 273         MUX_CLK_AUD_CPU_HCH,
 274         DIV_CLK_AUD_CPU,
 275 };
 276 enum clk_id cmucal_vclk_blk_g2d[] = {
 277         DIV_CLK_G2D_BUSP,
 278 };
 279 enum clk_id cmucal_vclk_blk_g3d[] = {
 280         DIV_CLK_G3D_BUSP,
 281 };
 282 enum clk_id cmucal_vclk_blk_isp[] = {
 283         DIV_CLK_ISP_BUSP,
 284 };
 285 enum clk_id cmucal_vclk_blk_mfc[] = {
 286         DIV_CLK_MFC_BUSP,
 287 };
 288 enum clk_id cmucal_vclk_blk_peri[] = {
 289         DIV_CLK_PERI_I2C,
 290 };
 291 enum clk_id cmucal_vclk_blk_shub[] = {
 292         DIV_CLK_SHUB_USI01,
 293         MUX_CLK_SHUB_USI01,
 294 };
 295 enum clk_id cmucal_vclk_blk_vipx1[] = {
 296         DIV_CLK_VIPX1_BUSP,
 297 };
 298 enum clk_id cmucal_vclk_blk_vipx2[] = {
 299         DIV_CLK_VIPX2_BUSP,
 300 };
 301
 302 /* GATING List */
 303 enum clk_id cmucal_vclk_ip_apbif_gpio_alive[] = {
 304         GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
 305 };
 306 enum clk_id cmucal_vclk_ip_apbif_pmu_alive[] = {
 307         GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
 308 };
 309 enum clk_id cmucal_vclk_ip_apbif_rtc[] = {
 310         GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK,
 311 };
 312 enum clk_id cmucal_vclk_ip_apbif_top_rtc[] = {
 313         GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK,
 314 };
 315 enum clk_id cmucal_vclk_ip_apm_cmu_apm[] = {
 316         CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK,
 317 };
 318 enum clk_id cmucal_vclk_ip_grebeintegration[] = {
 319         GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
 320 };
 321 enum clk_id cmucal_vclk_ip_intmem[] = {
 322         GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK,
 323         GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK,
 324 };
 325 enum clk_id cmucal_vclk_ip_lhm_axi_p_apm[] = {
 326         GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK,
 327 };
 328 enum clk_id cmucal_vclk_ip_lhm_axi_p_apm_gnss[] = {
 329         GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK,
 330 };
 331 enum clk_id cmucal_vclk_ip_lhm_axi_p_apm_modem[] = {
 332         GOUT_BLK_APM_UID_LHM_AXI_P_APM_MODEM_IPCLKPORT_I_CLK,
 333 };
 334 enum clk_id cmucal_vclk_ip_lhm_axi_p_apm_shub[] = {
 335         GOUT_BLK_APM_UID_LHM_AXI_P_APM_SHUB_IPCLKPORT_I_CLK,
 336 };
 337 enum clk_id cmucal_vclk_ip_lhm_axi_p_apm_wlbt[] = {
 338         GOUT_BLK_APM_UID_LHM_AXI_P_APM_WLBT_IPCLKPORT_I_CLK,
 339 };
 340 enum clk_id cmucal_vclk_ip_lhs_axi_d_apm[] = {
 341         GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
 342 };
 343 enum clk_id cmucal_vclk_ip_lhs_axi_lp_shub[] = {
 344         GOUT_BLK_APM_UID_LHS_AXI_LP_SHUB_IPCLKPORT_I_CLK,
 345 };
 346 enum clk_id cmucal_vclk_ip_mailbox_ap2cp[] = {
 347         GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK,
 348 };
 349 enum clk_id cmucal_vclk_ip_mailbox_ap2cp_s[] = {
 350         GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK,
 351 };
 352 enum clk_id cmucal_vclk_ip_mailbox_ap2gnss[] = {
 353         GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK,
 354 };
 355 enum clk_id cmucal_vclk_ip_mailbox_ap2shub[] = {
 356         GOUT_BLK_APM_UID_MAILBOX_AP2SHUB_IPCLKPORT_PCLK,
 357 };
 358 enum clk_id cmucal_vclk_ip_mailbox_ap2wlbt[] = {
 359         GOUT_BLK_APM_UID_MAILBOX_AP2WLBT_IPCLKPORT_PCLK,
 360 };
 361 enum clk_id cmucal_vclk_ip_mailbox_apm2ap[] = {
 362         GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK,
 363 };
 364 enum clk_id cmucal_vclk_ip_mailbox_apm2cp[] = {
 365         GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK,
 366 };
 367 enum clk_id cmucal_vclk_ip_mailbox_apm2gnss[] = {
 368         GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK,
 369 };
 370 enum clk_id cmucal_vclk_ip_mailbox_apm2shub[] = {
 371         GOUT_BLK_APM_UID_MAILBOX_APM2SHUB_IPCLKPORT_PCLK,
 372 };
 373 enum clk_id cmucal_vclk_ip_mailbox_apm2wlbt[] = {
 374         GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK,
 375 };
 376 enum clk_id cmucal_vclk_ip_mailbox_cp2gnss[] = {
 377         GOUT_BLK_APM_UID_MAILBOX_CP2GNSS_IPCLKPORT_PCLK,
 378 };
 379 enum clk_id cmucal_vclk_ip_mailbox_cp2shub[] = {
 380         GOUT_BLK_APM_UID_MAILBOX_CP2SHUB_IPCLKPORT_PCLK,
 381 };
 382 enum clk_id cmucal_vclk_ip_mailbox_cp2wlbt[] = {
 383         GOUT_BLK_APM_UID_MAILBOX_CP2WLBT_IPCLKPORT_PCLK,
 384 };
 385 enum clk_id cmucal_vclk_ip_mailbox_shub2gnss[] = {
 386         GOUT_BLK_APM_UID_MAILBOX_SHUB2GNSS_IPCLKPORT_PCLK,
 387 };
 388 enum clk_id cmucal_vclk_ip_mailbox_shub2wlbt[] = {
 389         GOUT_BLK_APM_UID_MAILBOX_SHUB2WLBT_IPCLKPORT_PCLK,
 390 };
 391 enum clk_id cmucal_vclk_ip_mailbox_wlbt2abox[] = {
 392         GOUT_BLK_APM_UID_MAILBOX_WLBT2ABOX_IPCLKPORT_PCLK,
 393 };
 394 enum clk_id cmucal_vclk_ip_mailbox_wlbt2gnss[] = {
 395         GOUT_BLK_APM_UID_MAILBOX_WLBT2GNSS_IPCLKPORT_PCLK,
 396 };
 397 enum clk_id cmucal_vclk_ip_pem[] = {
 398         GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK,
 399 };
 400 enum clk_id cmucal_vclk_ip_pgen_lite_apm[] = {
 401         GOUT_BLK_APM_UID_PGEN_LITE_APM_IPCLKPORT_CLK,
 402 };
 403 enum clk_id cmucal_vclk_ip_pmu_intr_gen[] = {
 404         GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
 405 };
 406 enum clk_id cmucal_vclk_ip_speedy_apm[] = {
 407         GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK,
 408 };
 409 enum clk_id cmucal_vclk_ip_sysreg_apm[] = {
 410         GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
 411 };
 412 enum clk_id cmucal_vclk_ip_wdt_apm[] = {
 413         GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK,
 414 };
 415 enum clk_id cmucal_vclk_ip_xiu_dp_apm[] = {
 416         GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK,
 417 };
 418 enum clk_id cmucal_vclk_ip_blk_cam[] = {
 419         GOUT_BLK_CAM_UID_BLK_CAM_IPCLKPORT_CLK_CAM_BUSD,
 420 };
 421 enum clk_id cmucal_vclk_ip_btm_cam[] = {
 422         GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_ACLK,
 423         GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_PCLK,
 424 };
 425 enum clk_id cmucal_vclk_ip_cam_cmu_cam[] = {
 426         CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK,
 427 };
 428 enum clk_id cmucal_vclk_ip_lhm_axi_p_cam[] = {
 429         GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK,
 430 };
 431 enum clk_id cmucal_vclk_ip_lhs_acel_d_cam[] = {
 432         GOUT_BLK_CAM_UID_LHS_ACEL_D_CAM_IPCLKPORT_I_CLK,
 433 };
 434 enum clk_id cmucal_vclk_ip_lhs_atb_camisp[] = {
 435         GOUT_BLK_CAM_UID_LHS_ATB_CAMISP_IPCLKPORT_I_CLK,
 436 };
 437 enum clk_id cmucal_vclk_ip_sysreg_cam[] = {
 438         GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK,
 439 };
 440 enum clk_id cmucal_vclk_ip_is6p10p0_cam[] = {
 441         GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_3AA,
 442         GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_CSIS0,
 443         GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_CSIS1,
 444         GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_CSIS2,
 445         GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_CSIS3,
 446         GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_DMA,
 447         GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_GLUE_CSIS0,
 448         GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_GLUE_CSIS1,
 449         GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_GLUE_CSIS2,
 450         GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_GLUE_CSIS3,
 451         GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_PAFSTAT_CORE,
 452         GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_PPMU_CAM,
 453         GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_RDMA,
 454         GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_SMMU_CAM,
 455         GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_XIU_D_CAM,
 456         GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM0,
 457         GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM1,
 458         GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_PCLK_PPMU_CAM,
 459 };
 460 enum clk_id cmucal_vclk_ip_adc_cmgp[] = {
 461         GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0,
 462         GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1,
 463 };
 464 enum clk_id cmucal_vclk_ip_cmgp_cmu_cmgp[] = {
 465         CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK,
 466 };
 467 enum clk_id cmucal_vclk_ip_gpio_cmgp[] = {
 468         GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK,
 469 };
 470 enum clk_id cmucal_vclk_ip_i2c_cmgp00[] = {
 471         GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK,
 472         GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK,
 473 };
 474 enum clk_id cmucal_vclk_ip_i2c_cmgp01[] = {
 475         GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK,
 476         GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK,
 477 };
 478 enum clk_id cmucal_vclk_ip_i2c_cmgp02[] = {
 479         GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK,
 480         GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK,
 481 };
 482 enum clk_id cmucal_vclk_ip_i2c_cmgp03[] = {
 483         GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK,
 484         GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK,
 485 };
 486 enum clk_id cmucal_vclk_ip_i2c_cmgp04[] = {
 487         GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_IPCLK,
 488         GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_PCLK,
 489 };
 490 enum clk_id cmucal_vclk_ip_sysreg_cmgp[] = {
 491         GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK,
 492 };
 493 enum clk_id cmucal_vclk_ip_sysreg_cmgp2cp[] = {
 494         GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK,
 495 };
 496 enum clk_id cmucal_vclk_ip_sysreg_cmgp2gnss[] = {
 497         GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK,
 498 };
 499 enum clk_id cmucal_vclk_ip_sysreg_cmgp2pmu_ap[] = {
 500         GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK,
 501 };
 502 enum clk_id cmucal_vclk_ip_sysreg_cmgp2pmu_shub[] = {
 503         GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_SHUB_IPCLKPORT_PCLK,
 504 };
 505 enum clk_id cmucal_vclk_ip_sysreg_cmgp2shub[] = {
 506         GOUT_BLK_CMGP_UID_SYSREG_CMGP2SHUB_IPCLKPORT_PCLK,
 507 };
 508 enum clk_id cmucal_vclk_ip_sysreg_cmgp2wlbt[] = {
 509         GOUT_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK,
 510 };
 511 enum clk_id cmucal_vclk_ip_usi_cmgp00[] = {
 512         GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK,
 513         GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK,
 514 };
 515 enum clk_id cmucal_vclk_ip_usi_cmgp01[] = {
 516         GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK,
 517         GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK,
 518 };
 519 enum clk_id cmucal_vclk_ip_usi_cmgp02[] = {
 520         GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK,
 521         GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK,
 522 };
 523 enum clk_id cmucal_vclk_ip_usi_cmgp03[] = {
 524         GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK,
 525         GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK,
 526 };
 527 enum clk_id cmucal_vclk_ip_usi_cmgp04[] = {
 528         GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_IPCLK,
 529         GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_PCLK,
 530 };
 531 enum clk_id cmucal_vclk_ip_otp[] = {
 532         CLK_BLK_CMU_UID_OTP_IPCLKPORT_CLK,
 533 };
 534 enum clk_id cmucal_vclk_ip_ad_apb_cci_550[] = {
 535         GOUT_BLK_CORE_UID_AD_APB_CCI_550_IPCLKPORT_PCLKM,
 536 };
 537 enum clk_id cmucal_vclk_ip_ad_apb_dit[] = {
 538         GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM,
 539 };
 540 enum clk_id cmucal_vclk_ip_ad_apb_pdma0[] = {
 541         GOUT_BLK_CORE_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM,
 542 };
 543 enum clk_id cmucal_vclk_ip_ad_apb_pgen_pdma[] = {
 544         GOUT_BLK_CORE_UID_AD_APB_PGEN_PDMA_IPCLKPORT_PCLKM,
 545 };
 546 enum clk_id cmucal_vclk_ip_ad_apb_ppfw_mem0[] = {
 547         GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM0_IPCLKPORT_PCLKM,
 548 };
 549 enum clk_id cmucal_vclk_ip_ad_apb_ppfw_mem1[] = {
 550         GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM1_IPCLKPORT_PCLKM,
 551 };
 552 enum clk_id cmucal_vclk_ip_ad_apb_ppfw_peri[] = {
 553         GOUT_BLK_CORE_UID_AD_APB_PPFW_PERI_IPCLKPORT_PCLKM,
 554 };
 555 enum clk_id cmucal_vclk_ip_ad_apb_spdma[] = {
 556         GOUT_BLK_CORE_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM,
 557 };
 558 enum clk_id cmucal_vclk_ip_ad_axi_gic[] = {
 559         GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM,
 560 };
 561 enum clk_id cmucal_vclk_ip_asyncsfr_wr_dmc0[] = {
 562         GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC0_IPCLKPORT_I_PCLK,
 563 };
 564 enum clk_id cmucal_vclk_ip_asyncsfr_wr_dmc1[] = {
 565         GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC1_IPCLKPORT_I_PCLK,
 566 };
 567 enum clk_id cmucal_vclk_ip_axi_us_a40_64to128_dit[] = {
 568         GOUT_BLK_CORE_UID_AXI_US_A40_64to128_DIT_IPCLKPORT_aclk,
 569 };
 570 enum clk_id cmucal_vclk_ip_baaw_p_gnss[] = {
 571         GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK,
 572 };
 573 enum clk_id cmucal_vclk_ip_baaw_p_modem[] = {
 574         GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK,
 575 };
 576 enum clk_id cmucal_vclk_ip_baaw_p_shub[] = {
 577         GOUT_BLK_CORE_UID_BAAW_P_SHUB_IPCLKPORT_I_PCLK,
 578 };
 579 enum clk_id cmucal_vclk_ip_baaw_p_wlbt[] = {
 580         GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK,
 581 };
 582 enum clk_id cmucal_vclk_ip_cci_550[] = {
 583         GOUT_BLK_CORE_UID_CCI_550_IPCLKPORT_ACLK,
 584 };
 585 enum clk_id cmucal_vclk_ip_core_cmu_core[] = {
 586         CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK,
 587 };
 588 enum clk_id cmucal_vclk_ip_dit[] = {
 589         GOUT_BLK_CORE_UID_DIT_IPCLKPORT_iClkL2A,
 590 };
 591 enum clk_id cmucal_vclk_ip_gic400_aihwacg[] = {
 592         GOUT_BLK_CORE_UID_GIC400_AIHWACG_IPCLKPORT_CLK,
 593 };
 594 enum clk_id cmucal_vclk_ip_lhm_acel_d0_isp[] = {
 595         GOUT_BLK_CORE_UID_LHM_ACEL_D0_ISP_IPCLKPORT_I_CLK,
 596 };
 597 enum clk_id cmucal_vclk_ip_lhm_acel_d0_mfc[] = {
 598         GOUT_BLK_CORE_UID_LHM_ACEL_D0_MFC_IPCLKPORT_I_CLK,
 599 };
 600 enum clk_id cmucal_vclk_ip_lhm_acel_d1_isp[] = {
 601         GOUT_BLK_CORE_UID_LHM_ACEL_D1_ISP_IPCLKPORT_I_CLK,
 602 };
 603 enum clk_id cmucal_vclk_ip_lhm_acel_d1_mfc[] = {
 604         GOUT_BLK_CORE_UID_LHM_ACEL_D1_MFC_IPCLKPORT_I_CLK,
 605 };
 606 enum clk_id cmucal_vclk_ip_lhm_acel_d_cam[] = {
 607         GOUT_BLK_CORE_UID_LHM_ACEL_D_CAM_IPCLKPORT_I_CLK,
 608 };
 609 enum clk_id cmucal_vclk_ip_lhm_acel_d_dpu[] = {
 610         GOUT_BLK_CORE_UID_LHM_ACEL_D_DPU_IPCLKPORT_I_CLK,
 611 };
 612 enum clk_id cmucal_vclk_ip_lhm_acel_d_fsys[] = {
 613         GOUT_BLK_CORE_UID_LHM_ACEL_D_FSYS_IPCLKPORT_I_CLK,
 614 };
 615 enum clk_id cmucal_vclk_ip_lhm_acel_d_g2d[] = {
 616         GOUT_BLK_CORE_UID_LHM_ACEL_D_G2D_IPCLKPORT_I_CLK,
 617 };
 618 enum clk_id cmucal_vclk_ip_lhm_acel_d_usb[] = {
 619         GOUT_BLK_CORE_UID_LHM_ACEL_D_USB_IPCLKPORT_I_CLK,
 620 };
 621 enum clk_id cmucal_vclk_ip_lhm_acel_d_vipx1[] = {
 622         GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX1_IPCLKPORT_I_CLK,
 623 };
 624 enum clk_id cmucal_vclk_ip_lhm_acel_d_vipx2[] = {
 625         GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX2_IPCLKPORT_I_CLK,
 626 };
 627 enum clk_id cmucal_vclk_ip_lhm_ace_d_cpucl0[] = {
 628         GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK,
 629 };
 630 enum clk_id cmucal_vclk_ip_lhm_ace_d_cpucl1[] = {
 631         GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK,
 632 };
 633 enum clk_id cmucal_vclk_ip_lhm_axi_d0_modem[] = {
 634         GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK,
 635 };
 636 enum clk_id cmucal_vclk_ip_lhm_axi_d1_modem[] = {
 637         GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK,
 638 };
 639 enum clk_id cmucal_vclk_ip_lhm_axi_d_abox[] = {
 640         GOUT_BLK_CORE_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK,
 641 };
 642 enum clk_id cmucal_vclk_ip_lhm_axi_d_apm[] = {
 643         GOUT_BLK_CORE_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK,
 644 };
 645 enum clk_id cmucal_vclk_ip_lhm_axi_d_cssys[] = {
 646         GOUT_BLK_CORE_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK,
 647 };
 648 enum clk_id cmucal_vclk_ip_lhm_axi_d_g3d[] = {
 649         GOUT_BLK_CORE_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK,
 650 };
 651 enum clk_id cmucal_vclk_ip_lhm_axi_d_gnss[] = {
 652         GOUT_BLK_CORE_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK,
 653 };
 654 enum clk_id cmucal_vclk_ip_lhm_axi_d_shub[] = {
 655         GOUT_BLK_CORE_UID_LHM_AXI_D_SHUB_IPCLKPORT_I_CLK,
 656 };
 657 enum clk_id cmucal_vclk_ip_lhm_axi_d_wlbt[] = {
 658         GOUT_BLK_CORE_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK,
 659 };
 660 enum clk_id cmucal_vclk_ip_lhs_axi_d0_mif_cp[] = {
 661         GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CP_IPCLKPORT_I_CLK,
 662 };
 663 enum clk_id cmucal_vclk_ip_lhs_axi_d0_mif_cpu[] = {
 664         GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CPU_IPCLKPORT_I_CLK,
 665 };
 666 enum clk_id cmucal_vclk_ip_lhs_axi_d0_mif_nrt[] = {
 667         GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_NRT_IPCLKPORT_I_CLK,
 668 };
 669 enum clk_id cmucal_vclk_ip_lhs_axi_d0_mif_rt[] = {
 670         GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_RT_IPCLKPORT_I_CLK,
 671 };
 672 enum clk_id cmucal_vclk_ip_lhs_axi_d1_mif_cp[] = {
 673         GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CP_IPCLKPORT_I_CLK,
 674 };
 675 enum clk_id cmucal_vclk_ip_lhs_axi_d1_mif_cpu[] = {
 676         GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CPU_IPCLKPORT_I_CLK,
 677 };
 678 enum clk_id cmucal_vclk_ip_lhs_axi_d1_mif_nrt[] = {
 679         GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_NRT_IPCLKPORT_I_CLK,
 680 };
 681 enum clk_id cmucal_vclk_ip_lhs_axi_d1_mif_rt[] = {
 682         GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_RT_IPCLKPORT_I_CLK,
 683 };
 684 enum clk_id cmucal_vclk_ip_lhs_axi_p_apm[] = {
 685         GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK,
 686 };
 687 enum clk_id cmucal_vclk_ip_lhs_axi_p_cam[] = {
 688         GOUT_BLK_CORE_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK,
 689 };
 690 enum clk_id cmucal_vclk_ip_lhs_axi_p_cpucl0[] = {
 691         GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK,
 692 };
 693 enum clk_id cmucal_vclk_ip_lhs_axi_p_cpucl1[] = {
 694         GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK,
 695 };
 696 enum clk_id cmucal_vclk_ip_lhs_axi_p_dispaud[] = {
 697         GOUT_BLK_CORE_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK,
 698 };
 699 enum clk_id cmucal_vclk_ip_lhs_axi_p_fsys[] = {
 700         GOUT_BLK_CORE_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK,
 701 };
 702 enum clk_id cmucal_vclk_ip_lhs_axi_p_g2d[] = {
 703         GOUT_BLK_CORE_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK,
 704 };
 705 enum clk_id cmucal_vclk_ip_lhs_axi_p_g3d[] = {
 706         GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK,
 707 };
 708 enum clk_id cmucal_vclk_ip_lhs_axi_p_gnss[] = {
 709         GOUT_BLK_CORE_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK,
 710 };
 711 enum clk_id cmucal_vclk_ip_lhs_axi_p_isp[] = {
 712         GOUT_BLK_CORE_UID_LHS_AXI_P_ISP_IPCLKPORT_I_CLK,
 713 };
 714 enum clk_id cmucal_vclk_ip_lhs_axi_p_mfc[] = {
 715         GOUT_BLK_CORE_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK,
 716 };
 717 enum clk_id cmucal_vclk_ip_lhs_axi_p_mif0[] = {
 718         GOUT_BLK_CORE_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK,
 719 };
 720 enum clk_id cmucal_vclk_ip_lhs_axi_p_mif1[] = {
 721         GOUT_BLK_CORE_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK,
 722 };
 723 enum clk_id cmucal_vclk_ip_lhs_axi_p_modem[] = {
 724         GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK,
 725 };
 726 enum clk_id cmucal_vclk_ip_lhs_axi_p_peri[] = {
 727         GOUT_BLK_CORE_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK,
 728 };
 729 enum clk_id cmucal_vclk_ip_lhs_axi_p_shub[] = {
 730         GOUT_BLK_CORE_UID_LHS_AXI_P_SHUB_IPCLKPORT_I_CLK,
 731 };
 732 enum clk_id cmucal_vclk_ip_lhs_axi_p_usb[] = {
 733         GOUT_BLK_CORE_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK,
 734 };
 735 enum clk_id cmucal_vclk_ip_lhs_axi_p_vipx1[] = {
 736         GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX1_IPCLKPORT_I_CLK,
 737 };
 738 enum clk_id cmucal_vclk_ip_lhs_axi_p_vipx2[] = {
 739         GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX2_IPCLKPORT_I_CLK,
 740 };
 741 enum clk_id cmucal_vclk_ip_lhs_axi_p_wlbt[] = {
 742         GOUT_BLK_CORE_UID_LHS_AXI_P_WLBT_IPCLKPORT_I_CLK,
 743 };
 744 enum clk_id cmucal_vclk_ip_pdma_core[] = {
 745         GOUT_BLK_CORE_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0,
 746 };
 747 enum clk_id cmucal_vclk_ip_pgen_lite_sirex[] = {
 748         GOUT_BLK_CORE_UID_PGEN_LITE_SIREX_IPCLKPORT_CLK,
 749 };
 750 enum clk_id cmucal_vclk_ip_pgen_pdma[] = {
 751         GOUT_BLK_CORE_UID_PGEN_PDMA_IPCLKPORT_CLK,
 752 };
 753 enum clk_id cmucal_vclk_ip_ppcfw_g3d[] = {
 754         GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK,
 755         GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK,
 756 };
 757 enum clk_id cmucal_vclk_ip_ppfw_core_mem0[] = {
 758         GOUT_BLK_CORE_UID_PPFW_CORE_MEM0_IPCLKPORT_CLK,
 759 };
 760 enum clk_id cmucal_vclk_ip_ppfw_core_mem1[] = {
 761         GOUT_BLK_CORE_UID_PPFW_CORE_MEM1_IPCLKPORT_CLK,
 762 };
 763 enum clk_id cmucal_vclk_ip_ppfw_core_peri[] = {
 764         GOUT_BLK_CORE_UID_PPFW_CORE_PERI_IPCLKPORT_CLK,
 765 };
 766 enum clk_id cmucal_vclk_ip_ppmu_ace_cpucl0[] = {
 767         GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_ACLK,
 768         GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_PCLK,
 769 };
 770 enum clk_id cmucal_vclk_ip_ppmu_ace_cpucl1[] = {
 771         GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_ACLK,
 772         GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_PCLK,
 773 };
 774 enum clk_id cmucal_vclk_ip_sfr_apbif_cmu_topc[] = {
 775         GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK,
 776 };
 777 enum clk_id cmucal_vclk_ip_sirex[] = {
 778         GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_i_ACLK,
 779         GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_i_PCLK,
 780 };
 781 enum clk_id cmucal_vclk_ip_spdma_core[] = {
 782         GOUT_BLK_CORE_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1,
 783 };
 784 enum clk_id cmucal_vclk_ip_sysreg_core[] = {
 785         GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK,
 786 };
 787 enum clk_id cmucal_vclk_ip_trex_d_core[] = {
 788         GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK,
 789         GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_CCLK,
 790         GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK,
 791         GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_pclk,
 792 };
 793 enum clk_id cmucal_vclk_ip_trex_d_nrt[] = {
 794         GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK,
 795         GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_pclk,
 796 };
 797 enum clk_id cmucal_vclk_ip_trex_p_core[] = {
 798         GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE,
 799         GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_CCLK_P_CORE,
 800         GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE,
 801         GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_pclk,
 802 };
 803 enum clk_id cmucal_vclk_ip_xiu_d_core[] = {
 804         GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK,
 805 };
 806 enum clk_id cmucal_vclk_ip_adm_apb_g_cssys_core[] = {
 807         GOUT_BLK_CPUCL0_UID_ADM_APB_G_CSSYS_CORE_IPCLKPORT_PCLKM,
 808 };
 809 enum clk_id cmucal_vclk_ip_ads_ahb_g_cssys_fsys[] = {
 810         GOUT_BLK_CPUCL0_UID_ADS_AHB_G_CSSYS_FSYS_IPCLKPORT_HCLKS,
 811 };
 812 enum clk_id cmucal_vclk_ip_ads_apb_g_cssys_cpucl1[] = {
 813         GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKS,
 814 };
 815 enum clk_id cmucal_vclk_ip_ads_apb_g_p8q[] = {
 816         GOUT_BLK_CPUCL0_UID_ADS_APB_G_P8Q_IPCLKPORT_PCLKS,
 817 };
 818 enum clk_id cmucal_vclk_ip_ad_apb_p_dump_pc_cpucl0[] = {
 819         GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM,
 820 };
 821 enum clk_id cmucal_vclk_ip_ad_apb_p_dump_pc_cpucl1[] = {
 822         GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM,
 823 };
 824 enum clk_id cmucal_vclk_ip_busif_hpmcpucl0[] = {
 825         GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK,
 826 };
 827 enum clk_id cmucal_vclk_ip_cpucl0_cmu_cpucl0[] = {
 828         CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK,
 829 };
 830 enum clk_id cmucal_vclk_ip_cssys_dbg[] = {
 831         GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG,
 832 };
 833 enum clk_id cmucal_vclk_ip_dump_pc_cpucl0[] = {
 834         GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK,
 835 };
 836 enum clk_id cmucal_vclk_ip_dump_pc_cpucl1[] = {
 837         GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK,
 838 };
 839 enum clk_id cmucal_vclk_ip_hpm_cpucl0[] = {
 840         CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_hpm_targetclk_c,
 841 };
 842 enum clk_id cmucal_vclk_ip_lhm_axi_p_cpucl0[] = {
 843         GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK,
 844 };
 845 enum clk_id cmucal_vclk_ip_lhs_axi_d_cssys[] = {
 846         GOUT_BLK_CPUCL0_UID_LHS_AXI_D_CSSYS_IPCLKPORT_I_CLK,
 847 };
 848 enum clk_id cmucal_vclk_ip_secjtag[] = {
 849         GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_i_clk,
 850 };
 851 enum clk_id cmucal_vclk_ip_sysreg_cpucl0[] = {
 852         GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK,
 853 };
 854 enum clk_id cmucal_vclk_ip_adm_apb_g_cssys_cpucl1[] = {
 855         GOUT_BLK_CPUCL1_UID_ADM_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKM,
 856 };
 857 enum clk_id cmucal_vclk_ip_busif_hpmcpucl1[] = {
 858         GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK,
 859 };
 860 enum clk_id cmucal_vclk_ip_cpucl1_cmu_cpucl1[] = {
 861         CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK,
 862 };
 863 enum clk_id cmucal_vclk_ip_hpm_cpucl1[] = {
 864         CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_hpm_targetclk_c,
 865 };
 866 enum clk_id cmucal_vclk_ip_lhm_axi_p_cpucl1[] = {
 867         GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK,
 868 };
 869 enum clk_id cmucal_vclk_ip_lhs_ace_d_cpucl1[] = {
 870         GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK,
 871 };
 872 enum clk_id cmucal_vclk_ip_sysreg_cpucl1[] = {
 873         GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK,
 874 };
 875 enum clk_id cmucal_vclk_ip_abox[] = {
 876         GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK,
 877         GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_DSIF,
 878         GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY,
 879         CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0,
 880         CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1,
 881         CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2,
 882         GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB,
 883         GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7,
 884         GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_DBG,
 885         GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_OSC_SPDY,
 886 };
 887 enum clk_id cmucal_vclk_ip_axi_us_32to128[] = {
 888         GOUT_BLK_DISPAUD_UID_AXI_US_32to128_IPCLKPORT_aclk,
 889 };
 890 enum clk_id cmucal_vclk_ip_blk_dispaud[] = {
 891         GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_AUD,
 892         GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_DISP,
 893 };
 894 enum clk_id cmucal_vclk_ip_btm_abox[] = {
 895         GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_ACLK,
 896         GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_PCLK,
 897 };
 898 enum clk_id cmucal_vclk_ip_btm_dpu[] = {
 899         GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_ACLK,
 900         GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_PCLK,
 901 };
 902 enum clk_id cmucal_vclk_ip_dftmux_dispaud[] = {
 903         GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK,
 904 };
 905 enum clk_id cmucal_vclk_ip_dispaud_cmu_dispaud[] = {
 906         CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK,
 907 };
 908 enum clk_id cmucal_vclk_ip_dpu[] = {
 909         GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON,
 910         GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA,
 911         GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP,
 912 };
 913 enum clk_id cmucal_vclk_ip_gpio_dispaud[] = {
 914         GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK,
 915 };
 916 enum clk_id cmucal_vclk_ip_lhm_axi_p_dispaud[] = {
 917         GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK,
 918 };
 919 enum clk_id cmucal_vclk_ip_lhs_acel_d_dpu[] = {
 920         GOUT_BLK_DISPAUD_UID_LHS_ACEL_D_DPU_IPCLKPORT_I_CLK,
 921 };
 922 enum clk_id cmucal_vclk_ip_lhs_axi_d_abox[] = {
 923         GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK,
 924 };
 925 enum clk_id cmucal_vclk_ip_peri_axi_asb[] = {
 926         GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM,
 927         GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK,
 928 };
 929 enum clk_id cmucal_vclk_ip_ppmu_abox[] = {
 930         GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_ACLK,
 931         GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_PCLK,
 932 };
 933 enum clk_id cmucal_vclk_ip_ppmu_dpu[] = {
 934         GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_ACLK,
 935         GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_PCLK,
 936 };
 937 enum clk_id cmucal_vclk_ip_smmu_abox[] = {
 938         GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK,
 939 };
 940 enum clk_id cmucal_vclk_ip_smmu_dpu[] = {
 941         GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK,
 942 };
 943 enum clk_id cmucal_vclk_ip_sysreg_dispaud[] = {
 944         GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK,
 945 };
 946 enum clk_id cmucal_vclk_ip_wdt_aud[] = {
 947         GOUT_BLK_DISPAUD_UID_WDT_AUD_IPCLKPORT_PCLK,
 948 };
 949 enum clk_id cmucal_vclk_ip_adm_ahb_sss[] = {
 950         GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,
 951 };
 952 enum clk_id cmucal_vclk_ip_btm_fsys[] = {
 953         GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_ACLK,
 954         GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_PCLK,
 955 };
 956 enum clk_id cmucal_vclk_ip_fsys_cmu_fsys[] = {
 957         CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK,
 958 };
 959 enum clk_id cmucal_vclk_ip_gpio_fsys[] = {
 960         GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK,
 961 };
 962 enum clk_id cmucal_vclk_ip_lhm_axi_p_fsys[] = {
 963         GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK,
 964 };
 965 enum clk_id cmucal_vclk_ip_lhs_acel_d_fsys[] = {
 966         GOUT_BLK_FSYS_UID_LHS_ACEL_D_FSYS_IPCLKPORT_I_CLK,
 967 };
 968 enum clk_id cmucal_vclk_ip_mmc_card[] = {
 969         GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK,
 970         GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
 971 };
 972 enum clk_id cmucal_vclk_ip_mmc_embd[] = {
 973         GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK,
 974         GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN,
 975 };
 976 enum clk_id cmucal_vclk_ip_pgen_lite_fsys[] = {
 977         GOUT_BLK_FSYS_UID_PGEN_LITE_FSYS_IPCLKPORT_CLK,
 978 };
 979 enum clk_id cmucal_vclk_ip_ppmu_fsys[] = {
 980         GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK,
 981         GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK,
 982 };
 983 enum clk_id cmucal_vclk_ip_rtic[] = {
 984         GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_i_ACLK,
 985         GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_i_PCLK,
 986 };
 987 enum clk_id cmucal_vclk_ip_sss[] = {
 988         GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_i_ACLK,
 989         GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_i_PCLK,
 990 };
 991 enum clk_id cmucal_vclk_ip_sysreg_fsys[] = {
 992         GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK,
 993 };
 994 enum clk_id cmucal_vclk_ip_ufs_embd[] = {
 995         GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
 996         GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
 997         GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
 998 };
 999 enum clk_id cmucal_vclk_ip_xiu_d_fsys[] = {
1000         GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK,
1001 };
1002 enum clk_id cmucal_vclk_ip_as_axi_jpeg[] = {
1003         GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKM,
1004         GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKS,
1005 };
1006 enum clk_id cmucal_vclk_ip_as_axi_mscl[] = {
1007         GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKM,
1008         GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKS,
1009 };
1010 enum clk_id cmucal_vclk_ip_blk_g2d[] = {
1011         GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_G2D,
1012         GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_MSCL,
1013 };
1014 enum clk_id cmucal_vclk_ip_btm_g2d[] = {
1015         GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_ACLK,
1016         GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_PCLK,
1017 };
1018 enum clk_id cmucal_vclk_ip_g2d[] = {
1019         GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK,
1020 };
1021 enum clk_id cmucal_vclk_ip_g2d_cmu_g2d[] = {
1022         CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK,
1023 };
1024 enum clk_id cmucal_vclk_ip_jpeg[] = {
1025         GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_FIMP_CLK,
1026 };
1027 enum clk_id cmucal_vclk_ip_lhm_axi_p_g2d[] = {
1028         GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK,
1029 };
1030 enum clk_id cmucal_vclk_ip_lhs_acel_d_g2d[] = {
1031         GOUT_BLK_G2D_UID_LHS_ACEL_D_G2D_IPCLKPORT_I_CLK,
1032 };
1033 enum clk_id cmucal_vclk_ip_mscl[] = {
1034         GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK,
1035 };
1036 enum clk_id cmucal_vclk_ip_pgen100_lite_g2d[] = {
1037         GOUT_BLK_G2D_UID_PGEN100_LITE_G2D_IPCLKPORT_CLK,
1038 };
1039 enum clk_id cmucal_vclk_ip_ppmu_g2d[] = {
1040         GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_ACLK,
1041         GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_PCLK,
1042 };
1043 enum clk_id cmucal_vclk_ip_sysmmu_g2d[] = {
1044         GOUT_BLK_G2D_UID_SYSMMU_G2D_IPCLKPORT_CLK,
1045 };
1046 enum clk_id cmucal_vclk_ip_sysreg_g2d[] = {
1047         GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK,
1048 };
1049 enum clk_id cmucal_vclk_ip_xiu_d_mscl[] = {
1050         GOUT_BLK_G2D_UID_XIU_D_MSCL_IPCLKPORT_ACLK,
1051 };
1052 enum clk_id cmucal_vclk_ip_btm_g3d[] = {
1053         GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_ACLK,
1054         GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_PCLK,
1055 };
1056 enum clk_id cmucal_vclk_ip_busif_hpmg3d[] = {
1057         GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK,
1058 };
1059 enum clk_id cmucal_vclk_ip_g3d[] = {
1060         CLK_BLK_G3D_UID_G3D_IPCLKPORT_CLK,
1061 };
1062 enum clk_id cmucal_vclk_ip_g3d_cmu_g3d[] = {
1063         CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK,
1064 };
1065 enum clk_id cmucal_vclk_ip_gray2bin_g3d[] = {
1066         GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK,
1067 };
1068 enum clk_id cmucal_vclk_ip_hpm_g3d[] = {
1069         CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_hpm_targetclk_c,
1070 };
1071 enum clk_id cmucal_vclk_ip_lhm_axi_g3dsfr[] = {
1072         GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK,
1073 };
1074 enum clk_id cmucal_vclk_ip_lhm_axi_p_g3d[] = {
1075         GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK,
1076 };
1077 enum clk_id cmucal_vclk_ip_lhs_axi_d_g3d[] = {
1078         GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK,
1079 };
1080 enum clk_id cmucal_vclk_ip_lhs_axi_g3dsfr[] = {
1081         GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK,
1082 };
1083 enum clk_id cmucal_vclk_ip_pgen_lite_g3d[] = {
1084         GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK,
1085 };
1086 enum clk_id cmucal_vclk_ip_sysreg_g3d[] = {
1087         GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK,
1088 };
1089 enum clk_id cmucal_vclk_ip_blk_isp[] = {
1090         GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_BUSD,
1091         GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_GDC,
1092         GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_VRA,
1093 };
1094 enum clk_id cmucal_vclk_ip_btm_isp0[] = {
1095         GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_ACLK,
1096         GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_PCLK,
1097 };
1098 enum clk_id cmucal_vclk_ip_btm_isp1[] = {
1099         GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_ACLK,
1100         GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_PCLK,
1101 };
1102 enum clk_id cmucal_vclk_ip_isp_cmu_isp[] = {
1103         CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK,
1104 };
1105 enum clk_id cmucal_vclk_ip_lhm_atb_camisp[] = {
1106         GOUT_BLK_ISP_UID_LHM_ATB_CAMISP_IPCLKPORT_I_CLK,
1107 };
1108 enum clk_id cmucal_vclk_ip_lhm_axi_p_isp[] = {
1109         GOUT_BLK_ISP_UID_LHM_AXI_P_ISP_IPCLKPORT_I_CLK,
1110 };
1111 enum clk_id cmucal_vclk_ip_lhs_acel_d0_isp[] = {
1112         GOUT_BLK_ISP_UID_LHS_ACEL_D0_ISP_IPCLKPORT_I_CLK,
1113 };
1114 enum clk_id cmucal_vclk_ip_lhs_acel_d1_isp[] = {
1115         GOUT_BLK_ISP_UID_LHS_ACEL_D1_ISP_IPCLKPORT_I_CLK,
1116 };
1117 enum clk_id cmucal_vclk_ip_sysreg_isp[] = {
1118         GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK,
1119 };
1120 enum clk_id cmucal_vclk_ip_is6p10p0_isp[] = {
1121         GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_GDC,
1122         GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_ISP,
1123         GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_MCSC,
1124         GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_PPMU_ISP0,
1125         GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_PPMU_ISP1,
1126         GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_SMMU_ISP0,
1127         GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_SMMU_ISP1,
1128         GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_VRA,
1129         GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_GDC,
1130         GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_VRA,
1131         GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_GDC,
1132         GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_VRA,
1133         GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_XIU_D_ISP,
1134         GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_PCLK_PPMU_ISP0,
1135         GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_PCLK_PPMU_ISP1,
1136         GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_PGEN_LITE_ISP_PCLK,
1137 };
1138 enum clk_id cmucal_vclk_ip_as_axi_wfd[] = {
1139         GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM,
1140         GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS,
1141 };
1142 enum clk_id cmucal_vclk_ip_blk_mfc[] = {
1143         GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_MFC,
1144         GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_WFD,
1145 };
1146 enum clk_id cmucal_vclk_ip_btm_mfcd0[] = {
1147         GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK,
1148         GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK,
1149 };
1150 enum clk_id cmucal_vclk_ip_btm_mfcd1[] = {
1151         GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK,
1152         GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK,
1153 };
1154 enum clk_id cmucal_vclk_ip_lhm_axi_p_mfc[] = {
1155         GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK,
1156 };
1157 enum clk_id cmucal_vclk_ip_lhs_acel_d0_mfc[] = {
1158         GOUT_BLK_MFC_UID_LHS_ACEL_D0_MFC_IPCLKPORT_I_CLK,
1159 };
1160 enum clk_id cmucal_vclk_ip_lhs_acel_d1_mfc[] = {
1161         GOUT_BLK_MFC_UID_LHS_ACEL_D1_MFC_IPCLKPORT_I_CLK,
1162 };
1163 enum clk_id cmucal_vclk_ip_lh_atb_mfc[] = {
1164         GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI,
1165         GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI,
1166 };
1167 enum clk_id cmucal_vclk_ip_mfc[] = {
1168         GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK,
1169 };
1170 enum clk_id cmucal_vclk_ip_mfc_cmu_mfc[] = {
1171         CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK,
1172 };
1173 enum clk_id cmucal_vclk_ip_pgen100_lite_mfc[] = {
1174         GOUT_BLK_MFC_UID_PGEN100_LITE_MFC_IPCLKPORT_CLK,
1175 };
1176 enum clk_id cmucal_vclk_ip_ppmu_mfcd0[] = {
1177         GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK,
1178         GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK,
1179 };
1180 enum clk_id cmucal_vclk_ip_ppmu_mfcd1[] = {
1181         GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK,
1182         GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK,
1183 };
1184 enum clk_id cmucal_vclk_ip_sysmmu_mfcd0[] = {
1185         GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK,
1186 };
1187 enum clk_id cmucal_vclk_ip_sysmmu_mfcd1[] = {
1188         GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK,
1189 };
1190 enum clk_id cmucal_vclk_ip_sysreg_mfc[] = {
1191         GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK,
1192 };
1193 enum clk_id cmucal_vclk_ip_wfd[] = {
1194         GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK,
1195 };
1196 enum clk_id cmucal_vclk_ip_xiu_d_mfc[] = {
1197         GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK,
1198 };
1199 enum clk_id cmucal_vclk_ip_busif_hpmmif[] = {
1200         GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK,
1201 };
1202 enum clk_id cmucal_vclk_ip_ddr_phy[] = {
1203         GOUT_BLK_MIF_UID_DDR_PHY_IPCLKPORT_PCLK,
1204 };
1205 enum clk_id cmucal_vclk_ip_dmc[] = {
1206         GOUT_BLK_MIF_UID_DMC_IPCLKPORT_ACLK,
1207         GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU,
1208         GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF,
1209         GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE,
1210         GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK,
1211 };
1212 enum clk_id cmucal_vclk_ip_hpm_mif[] = {
1213         CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_hpm_targetclk_c,
1214 };
1215 enum clk_id cmucal_vclk_ip_lhm_axi_d_mif_cp[] = {
1216         CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CP_IPCLKPORT_I_CLK,
1217 };
1218 enum clk_id cmucal_vclk_ip_lhm_axi_d_mif_cpu[] = {
1219         CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CPU_IPCLKPORT_I_CLK,
1220 };
1221 enum clk_id cmucal_vclk_ip_lhm_axi_d_mif_nrt[] = {
1222         CLK_BLK_MIF_UID_LHM_AXI_D_MIF_NRT_IPCLKPORT_I_CLK,
1223 };
1224 enum clk_id cmucal_vclk_ip_lhm_axi_d_mif_rt[] = {
1225         CLK_BLK_MIF_UID_LHM_AXI_D_MIF_RT_IPCLKPORT_I_CLK,
1226 };
1227 enum clk_id cmucal_vclk_ip_lhm_axi_p_mif[] = {
1228         GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK,
1229 };
1230 enum clk_id cmucal_vclk_ip_mif_cmu_mif[] = {
1231         CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK,
1232 };
1233 enum clk_id cmucal_vclk_ip_ppmu_dmc_cpu[] = {
1234         CLK_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK,
1235         GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK,
1236 };
1237 enum clk_id cmucal_vclk_ip_qe_dmc_cpu[] = {
1238         GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK,
1239         GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK,
1240 };
1241 enum clk_id cmucal_vclk_ip_sfrapb_bridge_ddr_phy[] = {
1242         GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDR_PHY_IPCLKPORT_PCLK,
1243 };
1244 enum clk_id cmucal_vclk_ip_sfrapb_bridge_dmc[] = {
1245         GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK,
1246 };
1247 enum clk_id cmucal_vclk_ip_sfrapb_bridge_dmc_pf[] = {
1248         GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK,
1249 };
1250 enum clk_id cmucal_vclk_ip_sfrapb_bridge_dmc_ppmpu[] = {
1251         GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK,
1252 };
1253 enum clk_id cmucal_vclk_ip_sfrapb_bridge_dmc_secure[] = {
1254         GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK,
1255 };
1256 enum clk_id cmucal_vclk_ip_sysreg_mif[] = {
1257         GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK,
1258 };
1259 enum clk_id cmucal_vclk_ip_busif_hpmmif1[] = {
1260         GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK,
1261 };
1262 enum clk_id cmucal_vclk_ip_dmc1[] = {
1263         GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_ACLK,
1264         GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK,
1265         GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PF,
1266         GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PPMPU,
1267         GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_SECURE,
1268 };
1269 enum clk_id cmucal_vclk_ip_hpm_mif1[] = {
1270         GOUT_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_hpm_targetclk_c,
1271 };
1272 enum clk_id cmucal_vclk_ip_lhm_axi_d_mif1_cp[] = {
1273         GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CP_IPCLKPORT_I_CLK,
1274 };
1275 enum clk_id cmucal_vclk_ip_lhm_axi_d_mif1_cpu[] = {
1276         GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CPU_IPCLKPORT_I_CLK,
1277 };
1278 enum clk_id cmucal_vclk_ip_lhm_axi_d_mif1_nrt[] = {
1279         GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_NRT_IPCLKPORT_I_CLK,
1280 };
1281 enum clk_id cmucal_vclk_ip_lhm_axi_d_mif1_rt[] = {
1282         GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_RT_IPCLKPORT_I_CLK,
1283 };
1284 enum clk_id cmucal_vclk_ip_mif1_cmu_mif1[] = {
1285         CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK,
1286 };
1287 enum clk_id cmucal_vclk_ip_axi2ahb_msd32_peri[] = {
1288         GOUT_BLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_aclk,
1289 };
1290 enum clk_id cmucal_vclk_ip_busif_tmu[] = {
1291         GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK,
1292 };
1293 enum clk_id cmucal_vclk_ip_cami2c_0[] = {
1294         GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_IPCLK,
1295         GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_PCLK,
1296 };
1297 enum clk_id cmucal_vclk_ip_cami2c_1[] = {
1298         GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_IPCLK,
1299         GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_PCLK,
1300 };
1301 enum clk_id cmucal_vclk_ip_cami2c_2[] = {
1302         GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_IPCLK,
1303         GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_PCLK,
1304 };
1305 enum clk_id cmucal_vclk_ip_cami2c_3[] = {
1306         GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_IPCLK,
1307         GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_PCLK,
1308 };
1309 enum clk_id cmucal_vclk_ip_gpio_peri[] = {
1310         GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK,
1311 };
1312 enum clk_id cmucal_vclk_ip_i2c_0[] = {
1313         GOUT_BLK_PERI_UID_I2C_0_IPCLKPORT_PCLK,
1314 };
1315 enum clk_id cmucal_vclk_ip_i2c_1[] = {
1316         GOUT_BLK_PERI_UID_I2C_1_IPCLKPORT_PCLK,
1317 };
1318 enum clk_id cmucal_vclk_ip_i2c_2[] = {
1319         GOUT_BLK_PERI_UID_I2C_2_IPCLKPORT_PCLK,
1320 };
1321 enum clk_id cmucal_vclk_ip_i2c_3[] = {
1322         GOUT_BLK_PERI_UID_I2C_3_IPCLKPORT_PCLK,
1323 };
1324 enum clk_id cmucal_vclk_ip_i2c_4[] = {
1325         GOUT_BLK_PERI_UID_I2C_4_IPCLKPORT_PCLK,
1326 };
1327 enum clk_id cmucal_vclk_ip_i2c_5[] = {
1328         GOUT_BLK_PERI_UID_I2C_5_IPCLKPORT_PCLK,
1329 };
1330 enum clk_id cmucal_vclk_ip_i2c_6[] = {
1331         GOUT_BLK_PERI_UID_I2C_6_IPCLKPORT_PCLK,
1332 };
1333 enum clk_id cmucal_vclk_ip_lhm_axi_p_peri[] = {
1334         GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK,
1335 };
1336 enum clk_id cmucal_vclk_ip_mct[] = {
1337         GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK,
1338 };
1339 enum clk_id cmucal_vclk_ip_otp_con_top[] = {
1340         GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
1341 };
1342 enum clk_id cmucal_vclk_ip_peri_cmu_peri[] = {
1343         CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK,
1344 };
1345 enum clk_id cmucal_vclk_ip_pwm_motor[] = {
1346         GOUT_BLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_PCLK_S0,
1347 };
1348 enum clk_id cmucal_vclk_ip_spi_0[] = {
1349         GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_IPCLK,
1350         GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_PCLK,
1351 };
1352 enum clk_id cmucal_vclk_ip_spi_1[] = {
1353         GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_IPCLK,
1354         GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_PCLK,
1355 };
1356 enum clk_id cmucal_vclk_ip_spi_2[] = {
1357         GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_IPCLK,
1358         GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_PCLK,
1359 };
1360 enum clk_id cmucal_vclk_ip_sysreg_peri[] = {
1361         GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK,
1362 };
1363 enum clk_id cmucal_vclk_ip_uart[] = {
1364         GOUT_BLK_PERI_UID_UART_IPCLKPORT_IPCLK,
1365         GOUT_BLK_PERI_UID_UART_IPCLKPORT_PCLK,
1366 };
1367 enum clk_id cmucal_vclk_ip_usi00_i2c[] = {
1368         GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK,
1369         GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK,
1370 };
1371 enum clk_id cmucal_vclk_ip_usi00_usi[] = {
1372         GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK,
1373         GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK,
1374 };
1375 enum clk_id cmucal_vclk_ip_wdt_cluster0[] = {
1376         GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
1377 };
1378 enum clk_id cmucal_vclk_ip_wdt_cluster1[] = {
1379         GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
1380 };
1381 enum clk_id cmucal_vclk_ip_baaw_d_shub[] = {
1382         GOUT_BLK_SHUB_UID_BAAW_D_SHUB_IPCLKPORT_I_PCLK,
1383 };
1384 enum clk_id cmucal_vclk_ip_baaw_p_apm_shub[] = {
1385         GOUT_BLK_SHUB_UID_BAAW_P_APM_SHUB_IPCLKPORT_I_PCLK,
1386 };
1387 enum clk_id cmucal_vclk_ip_cm4_shub[] = {
1388         GOUT_BLK_SHUB_UID_CM4_SHUB_IPCLKPORT_FCLK,
1389 };
1390 enum clk_id cmucal_vclk_ip_gpio_shub[] = {
1391         GOUT_BLK_SHUB_UID_GPIO_SHUB_IPCLKPORT_PCLK,
1392 };
1393 enum clk_id cmucal_vclk_ip_i2c_shub00[] = {
1394         GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_IPCLK,
1395         GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_PCLK,
1396 };
1397 enum clk_id cmucal_vclk_ip_lhm_axi_lp_shub[] = {
1398         GOUT_BLK_SHUB_UID_LHM_AXI_LP_SHUB_IPCLKPORT_I_CLK,
1399 };
1400 enum clk_id cmucal_vclk_ip_lhm_axi_p_shub[] = {
1401         GOUT_BLK_SHUB_UID_LHM_AXI_P_SHUB_IPCLKPORT_I_CLK,
1402 };
1403 enum clk_id cmucal_vclk_ip_lhs_axi_d_shub[] = {
1404         GOUT_BLK_SHUB_UID_LHS_AXI_D_SHUB_IPCLKPORT_I_CLK,
1405 };
1406 enum clk_id cmucal_vclk_ip_lhs_axi_p_apm_shub[] = {
1407         GOUT_BLK_SHUB_UID_LHS_AXI_P_APM_SHUB_IPCLKPORT_I_CLK,
1408 };
1409 enum clk_id cmucal_vclk_ip_pdma_shub[] = {
1410         GOUT_BLK_SHUB_UID_PDMA_SHUB_IPCLKPORT_ACLK,
1411 };
1412 enum clk_id cmucal_vclk_ip_pwm_shub[] = {
1413         GOUT_BLK_SHUB_UID_PWM_SHUB_IPCLKPORT_i_PCLK_S0,
1414 };
1415 enum clk_id cmucal_vclk_ip_shub_cmu_shub[] = {
1416         CLK_BLK_SHUB_UID_SHUB_CMU_SHUB_IPCLKPORT_PCLK,
1417 };
1418 enum clk_id cmucal_vclk_ip_sweeper_d_shub[] = {
1419         GOUT_BLK_SHUB_UID_SWEEPER_D_SHUB_IPCLKPORT_ACLK,
1420 };
1421 enum clk_id cmucal_vclk_ip_sweeper_p_apm_shub[] = {
1422         GOUT_BLK_SHUB_UID_SWEEPER_P_APM_SHUB_IPCLKPORT_ACLK,
1423 };
1424 enum clk_id cmucal_vclk_ip_sysreg_shub[] = {
1425         GOUT_BLK_SHUB_UID_SYSREG_SHUB_IPCLKPORT_PCLK,
1426 };
1427 enum clk_id cmucal_vclk_ip_timer_shub[] = {
1428         GOUT_BLK_SHUB_UID_TIMER_SHUB_IPCLKPORT_PCLK,
1429 };
1430 enum clk_id cmucal_vclk_ip_usi_shub00[] = {
1431         GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_IPCLK,
1432         GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_PCLK,
1433 };
1434 enum clk_id cmucal_vclk_ip_wdt_shub[] = {
1435         GOUT_BLK_SHUB_UID_WDT_SHUB_IPCLKPORT_PCLK,
1436 };
1437 enum clk_id cmucal_vclk_ip_xiu_dp_shub[] = {
1438         GOUT_BLK_SHUB_UID_XIU_DP_SHUB_IPCLKPORT_ACLK,
1439 };
1440 enum clk_id cmucal_vclk_ip_btm_usb[] = {
1441         GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_ACLK,
1442         GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_PCLK,
1443 };
1444 enum clk_id cmucal_vclk_ip_dp_link[] = {
1445         GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_DP_GTC_CLK,
1446         GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_PCLK,
1447 };
1448 enum clk_id cmucal_vclk_ip_lhm_axi_p_usb[] = {
1449         GOUT_BLK_USB_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK,
1450 };
1451 enum clk_id cmucal_vclk_ip_lhs_acel_d_usb[] = {
1452         GOUT_BLK_USB_UID_LHS_ACEL_D_USB_IPCLKPORT_I_CLK,
1453 };
1454 enum clk_id cmucal_vclk_ip_pgen_lite_usb[] = {
1455         GOUT_BLK_USB_UID_PGEN_LITE_USB_IPCLKPORT_CLK,
1456 };
1457 enum clk_id cmucal_vclk_ip_ppmu_usb[] = {
1458         GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK,
1459         GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK,
1460 };
1461 enum clk_id cmucal_vclk_ip_sysreg_usb[] = {
1462         GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK,
1463 };
1464 enum clk_id cmucal_vclk_ip_usb30drd[] = {
1465         GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_20,
1466         GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_0,
1467         GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_1,
1468         GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_USB30DRD_ref_clk,
1469         GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_bus_clk_early,
1470 };
1471 enum clk_id cmucal_vclk_ip_usb_cmu_usb[] = {
1472         CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK,
1473 };
1474 enum clk_id cmucal_vclk_ip_us_d_usb[] = {
1475         GOUT_BLK_USB_UID_US_D_USB_IPCLKPORT_aclk,
1476 };
1477 enum clk_id cmucal_vclk_ip_blk_vipx1[] = {
1478         GOUT_BLK_VIPX1_UID_BLK_VIPX1_IPCLKPORT_CLK_VIPX1_BUSD,
1479 };
1480 enum clk_id cmucal_vclk_ip_btm_d_vipx1[] = {
1481         GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_ACLK,
1482         GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_PCLK,
1483 };
1484 enum clk_id cmucal_vclk_ip_lhm_atb_vipx1[] = {
1485         GOUT_BLK_VIPX1_UID_LHM_ATB_VIPX1_IPCLKPORT_I_CLK,
1486 };
1487 enum clk_id cmucal_vclk_ip_lhm_axi_p_vipx1[] = {
1488         GOUT_BLK_VIPX1_UID_LHM_AXI_P_VIPX1_IPCLKPORT_I_CLK,
1489 };
1490 enum clk_id cmucal_vclk_ip_lhs_acel_d_vipx1[] = {
1491         GOUT_BLK_VIPX1_UID_LHS_ACEL_D_VIPX1_IPCLKPORT_I_CLK,
1492 };
1493 enum clk_id cmucal_vclk_ip_lhs_atb_vipx1[] = {
1494         GOUT_BLK_VIPX1_UID_LHS_ATB_VIPX1_IPCLKPORT_I_CLK,
1495 };
1496 enum clk_id cmucal_vclk_ip_lhs_axi_p_vipx1_local[] = {
1497         GOUT_BLK_VIPX1_UID_LHS_AXI_P_VIPX1_LOCAL_IPCLKPORT_I_CLK,
1498 };
1499 enum clk_id cmucal_vclk_ip_pgen_lite_vipx1[] = {
1500         GOUT_BLK_VIPX1_UID_PGEN_LITE_VIPX1_IPCLKPORT_CLK,
1501 };
1502 enum clk_id cmucal_vclk_ip_ppmu_d_vipx1[] = {
1503         GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_ACLK,
1504         GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_PCLK,
1505 };
1506 enum clk_id cmucal_vclk_ip_smmu_d_vipx1[] = {
1507         GOUT_BLK_VIPX1_UID_SMMU_D_VIPX1_IPCLKPORT_CLK,
1508 };
1509 enum clk_id cmucal_vclk_ip_sysreg_vipx1[] = {
1510         GOUT_BLK_VIPX1_UID_SYSREG_VIPX1_IPCLKPORT_PCLK,
1511 };
1512 enum clk_id cmucal_vclk_ip_vipx1[] = {
1513         GOUT_BLK_VIPX1_UID_VIPX1_IPCLKPORT_CLK,
1514 };
1515 enum clk_id cmucal_vclk_ip_vipx1_cmu_vipx1[] = {
1516         CLK_BLK_VIPX1_UID_VIPX1_CMU_VIPX1_IPCLKPORT_PCLK,
1517 };
1518 enum clk_id cmucal_vclk_ip_xiu_d_vipx1[] = {
1519         GOUT_BLK_VIPX1_UID_XIU_D_VIPX1_IPCLKPORT_ACLK,
1520 };
1521 enum clk_id cmucal_vclk_ip_blk_vipx2[] = {
1522         GOUT_BLK_VIPX2_UID_BLK_VIPX2_IPCLKPORT_CLK_VIPX2_BUSD,
1523 };
1524 enum clk_id cmucal_vclk_ip_btm_d_vipx2[] = {
1525         GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_ACLK,
1526         GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_PCLK,
1527 };
1528 enum clk_id cmucal_vclk_ip_lhm_atb_vipx2[] = {
1529         GOUT_BLK_VIPX2_UID_LHM_ATB_VIPX2_IPCLKPORT_I_CLK,
1530 };
1531 enum clk_id cmucal_vclk_ip_lhm_axi_p_vipx2[] = {
1532         GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_IPCLKPORT_I_CLK,
1533 };
1534 enum clk_id cmucal_vclk_ip_lhm_axi_p_vipx2_local[] = {
1535         GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_LOCAL_IPCLKPORT_I_CLK,
1536 };
1537 enum clk_id cmucal_vclk_ip_lhs_acel_d_vipx2[] = {
1538         GOUT_BLK_VIPX2_UID_LHS_ACEL_D_VIPX2_IPCLKPORT_I_CLK,
1539 };
1540 enum clk_id cmucal_vclk_ip_lhs_atb_vipx2[] = {
1541         GOUT_BLK_VIPX2_UID_LHS_ATB_VIPX2_IPCLKPORT_I_CLK,
1542 };
1543 enum clk_id cmucal_vclk_ip_pgen_lite_vipx2[] = {
1544         GOUT_BLK_VIPX2_UID_PGEN_LITE_VIPX2_IPCLKPORT_CLK,
1545 };
1546 enum clk_id cmucal_vclk_ip_ppmu_d_vipx2[] = {
1547         GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_ACLK,
1548         GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_PCLK,
1549 };
1550 enum clk_id cmucal_vclk_ip_smmu_d_vipx2[] = {
1551         GOUT_BLK_VIPX2_UID_SMMU_D_VIPX2_IPCLKPORT_CLK,
1552 };
1553 enum clk_id cmucal_vclk_ip_sysreg_vipx2[] = {
1554         GOUT_BLK_VIPX2_UID_SYSREG_VIPX2_IPCLKPORT_PCLK,
1555 };
1556 enum clk_id cmucal_vclk_ip_vipx2[] = {
1557         GOUT_BLK_VIPX2_UID_VIPX2_IPCLKPORT_CLK,
1558 };
1559 enum clk_id cmucal_vclk_ip_vipx2_cmu_vipx2[] = {
1560         CLK_BLK_VIPX2_UID_VIPX2_CMU_VIPX2_IPCLKPORT_PCLK,
1561 };
1562
1563 /* Switching LUT */
1564 /* -1 is the Value of EMPTY_CAL_ID */
1565 struct switch_lut tail_blk_cpucl0_lut[] = {
1566         {799500, 0, 0},
1567         {399750, 0, 1},
1568         {266500, 2, 1},
1569 };
1570 struct switch_lut tail_blk_cpucl1_lut[] = {
1571         {799500, 0, 0},
1572         {399750, 0, 1},
1573 };
1574 struct switch_lut tail_blk_dispaud_lut[] = {
1575         {1332500, 0, 0},
1576         {799500, 1, 0},
1577         {399750, 1, 1},
1578 };
1579 struct switch_lut tail_blk_g3d_lut[] = {
1580         {799500, 0, 0},
1581         {399750, 0, 1},
1582         {199875, 0, 3},
1583 };
1584 struct switch_lut tail_blk_mif_lut[] = {
1585         {1599000, 0, -1},
1586         {1332500, 1, -1},
1587 };
1588 struct switch_lut tail_blk_mif1_lut[] = {
1589         {1599000, 0, -1},
1590         {1332500, 1, -1},
1591 };
1592
1593 /* DVFS LUT */
1594 struct vclk_lut vdd_cpucl0_lut[] = {
1595         {1850333, vdd_cpucl0_sod_lut_params},
1596         {1449500, vdd_cpucl0_od_lut_params},
1597         {1049750, vdd_cpucl0_nm_lut_params},
1598         {600166, vdd_cpucl0_ud_lut_params},
1599         {300083, vdd_cpucl0_sud_lut_params},
1600 };
1601 struct vclk_lut vdd_cpucl1_lut[] = {
1602         {2400666, vdd_cpucl1_sod_lut_params},
1603         {1898000, vdd_cpucl1_od_lut_params},
1604         {1499333, vdd_cpucl1_nm_lut_params},
1605         {850200, vdd_cpucl1_ud_lut_params},
1606         {549899, vdd_cpucl1_sud_lut_params},
1607 };
1608 struct vclk_lut vdd_g3d_lut[] = {
1609         {1200000, vdd_g3d_sod_lut_params},
1610         {1000000, vdd_g3d_od_lut_params},
1611         {750000, vdd_g3d_nm_lut_params},
1612         {550000, vdd_g3d_ud_lut_params},
1613         {300000, vdd_g3d_sud_lut_params},
1614 };
1615 struct vclk_lut vdd_int_lut[] = {
1616         {400000, vdd_int_nm_lut_params},
1617         {300000, vdd_int_od_lut_params},
1618         {200000, vdd_int_sud_lut_params},
1619         {100000, vdd_int_ud_lut_params},
1620 };
1621 struct vclk_lut vdd_cam_lut[] = {
1622         {400000, vdd_cam_nm_lut_params},
1623         {300000, vdd_cam_od_lut_params},
1624         {200000, vdd_cam_sud_lut_params},
1625         {100000, vdd_cam_ud_lut_params},
1626 };
1627 struct vclk_lut vdd_mif_lut[] = {
1628         {4264000, vdd_mif_nm_lut_params},
1629         {1399666, vdd_mif_sud_lut_params},
1630         {1332500, vdd_mif_ud_lut_params},
1631 };
1632
1633 /* SPECIAL LUT */
1634 struct vclk_lut clkcmu_shub_bus_lut[] = {
1635         {400000, spl_clk_shub_i2c_blk_apm_nm_lut_params},
1636 };
1637 struct vclk_lut div_clk_cmgp_adc_lut[] = {
1638         {33333, mux_clk_cmgp_adc_blk_cmgp_nm_lut_params},
1639 };
1640 struct vclk_lut div_clk_cmgp_usi01_lut[] = {
1641         {200000, spl_clk_cmgp_usi01_blk_cmgp_nm_lut_params},
1642 };
1643 struct vclk_lut div_clk_cmgp_usi03_lut[] = {
1644         {200000, spl_clk_cmgp_usi03_blk_cmgp_nm_lut_params},
1645 };
1646 struct vclk_lut div_clk_cmgp_usi02_lut[] = {
1647         {200000, spl_clk_cmgp_usi02_blk_cmgp_nm_lut_params},
1648 };
1649 struct vclk_lut div_clk_cmgp_usi00_lut[] = {
1650         {200000, spl_clk_cmgp_usi00_blk_cmgp_nm_lut_params},
1651 };
1652 struct vclk_lut div_clk_cmgp_usi04_lut[] = {
1653         {200000, spl_clk_cmgp_usi04_blk_cmgp_nm_lut_params},
1654 };
1655 struct vclk_lut clkcmu_fsys_ufs_embd_lut[] = {
1656         {133250, spl_clk_fsys_ufs_embd_blk_cmu_nm_lut_params},
1657 };
1658 struct vclk_lut div_clk_cmu_cmuref_lut[] = {
1659         {199875, occ_cmu_cmuref_blk_cmu_nm_lut_params},
1660 };
1661 struct vclk_lut clkcmu_hpm_lut[] = {
1662         {799500, clkcmu_hpm_blk_cmu_nm_lut_params},
1663 };
1664 struct vclk_lut clkcmu_peri_ip_lut[] = {
1665         {399750, spl_clk_peri_spi0_blk_cmu_nm_lut_params},
1666 };
1667 struct vclk_lut clkcmu_mif_busp_lut[] = {
1668         {199875, occ_mif_cmuref_blk_cmu_nm_lut_params},
1669 };
1670 struct vclk_lut clkcmu_apm_bus_lut[] = {
1671         {399750, spl_clk_shub_i2c_blk_cmu_nm_lut_params},
1672 };
1673 struct vclk_lut clkcmu_cis_clk1_lut[] = {
1674         {99937, clkcmu_cis_clk1_blk_cmu_nm_lut_params},
1675 };
1676 struct vclk_lut clkcmu_cis_clk3_lut[] = {
1677         {99937, clkcmu_cis_clk3_blk_cmu_nm_lut_params},
1678 };
1679 struct vclk_lut clkcmu_usb_usb30drd_lut[] = {
1680         {49968, spl_clk_usb_usb30drd_blk_cmu_nm_lut_params},
1681 };
1682 struct vclk_lut clkcmu_cis_clk0_lut[] = {
1683         {99937, clkcmu_cis_clk0_blk_cmu_nm_lut_params},
1684 };
1685 struct vclk_lut clkcmu_usb_dpgtc_lut[] = {
1686         {99937, spl_clk_usb_dpgtc_blk_cmu_nm_lut_params},
1687 };
1688 struct vclk_lut clkcmu_cis_clk2_lut[] = {
1689         {99937, clkcmu_cis_clk2_blk_cmu_nm_lut_params},
1690 };
1691 struct vclk_lut clkcmu_peri_uart_lut[] = {
1692         {199875, spl_clk_peri_uart_blk_cmu_nm_lut_params},
1693 };
1694 struct vclk_lut div_clk_cluster0_pclkdbg_lut[] = {
1695         {231291, div_clk_cluster0_pclkdbg_blk_cpucl0_sod_lut_params},
1696         {181187, div_clk_cluster0_pclkdbg_blk_cpucl0_od_lut_params},
1697         {131218, div_clk_cluster0_pclkdbg_blk_cpucl0_nm_lut_params},
1698         {75020, div_clk_cluster0_pclkdbg_blk_cpucl0_ud_lut_params},
1699         {37510, div_clk_cluster0_pclkdbg_blk_cpucl0_sud_lut_params},
1700 };
1701 struct vclk_lut div_clk_cluster0_aclk_lut[] = {
1702         {925166, div_clk_cluster0_aclk_blk_cpucl0_sod_lut_params},
1703         {724750, div_clk_cluster0_aclk_blk_cpucl0_od_lut_params},
1704         {524875, div_clk_cluster0_aclk_blk_cpucl0_nm_lut_params},
1705         {300083, div_clk_cluster0_aclk_blk_cpucl0_ud_lut_params},
1706         {150041, div_clk_cluster0_aclk_blk_cpucl0_sud_lut_params},
1707 };
1708 struct vclk_lut div_clk_cpucl0_cmuref_lut[] = {
1709         {925166, spl_clk_cpucl0_cmuref_blk_cpucl0_sod_lut_params},
1710         {724750, spl_clk_cpucl0_cmuref_blk_cpucl0_od_lut_params},
1711         {524875, spl_clk_cpucl0_cmuref_blk_cpucl0_nm_lut_params},
1712         {300083, spl_clk_cpucl0_cmuref_blk_cpucl0_ud_lut_params},
1713         {150041, spl_clk_cpucl0_cmuref_blk_cpucl0_sud_lut_params},
1714 };
1715 struct vclk_lut div_clk_cluster0_cntclk_lut[] = {
1716         {462583, div_clk_cluster0_cntclk_blk_cpucl0_sod_lut_params},
1717         {362375, div_clk_cluster0_cntclk_blk_cpucl0_od_lut_params},
1718         {262437, div_clk_cluster0_cntclk_blk_cpucl0_nm_lut_params},
1719         {150041, div_clk_cluster0_cntclk_blk_cpucl0_ud_lut_params},
1720         {75020, div_clk_cluster0_cntclk_blk_cpucl0_sud_lut_params},
1721 };
1722 struct vclk_lut div_clk_cluster1_cntclk_lut[] = {
1723         {600166, div_clk_cluster1_cntclk_blk_cpucl1_sod_lut_params},
1724         {474500, div_clk_cluster1_cntclk_blk_cpucl1_od_lut_params},
1725         {374833, div_clk_cluster1_cntclk_blk_cpucl1_nm_lut_params},
1726         {212550, div_clk_cluster1_cntclk_blk_cpucl1_ud_lut_params},
1727         {137474, div_clk_cluster1_cntclk_blk_cpucl1_sud_lut_params},
1728 };
1729 struct vclk_lut div_clk_cpucl1_cmuref_lut[] = {
1730         {1200333, spl_clk_cpucl1_cmuref_blk_cpucl1_sod_lut_params},
1731         {949000, spl_clk_cpucl1_cmuref_blk_cpucl1_od_lut_params},
1732         {749666, spl_clk_cpucl1_cmuref_blk_cpucl1_nm_lut_params},
1733         {425100, spl_clk_cpucl1_cmuref_blk_cpucl1_ud_lut_params},
1734         {274949, spl_clk_cpucl1_cmuref_blk_cpucl1_sud_lut_params},
1735 };
1736 struct vclk_lut div_clk_aud_dsif_lut[] = {
1737         {58982, spl_clk_aud_dsif_blk_dispaud_sud_lut_params},
1738         {39321, spl_clk_aud_dsif_blk_dispaud_ud_lut_params},
1739         {24999, spl_clk_aud_dsif_blk_dispaud_od_lut_params},
1740         {24576, spl_clk_aud_dsif_blk_dispaud_nm_lut_params},
1741 };
1742 struct vclk_lut div_clk_aud_uaif0_lut[] = {
1743         {26000, dft_clk_aud_uaif0_blk_dispaud_nm_lut_params},
1744 };
1745 struct vclk_lut div_clk_aud_uaif2_lut[] = {
1746         {26000, dft_clk_aud_uaif2_blk_dispaud_nm_lut_params},
1747 };
1748 struct vclk_lut div_clk_aud_cpu_pclkdbg_lut[] = {
1749         {147456, spl_clk_aud_cpu_pclkdbg_blk_dispaud_nm_lut_params},
1750         {99937, spl_clk_aud_cpu_pclkdbg_blk_dispaud_od_lut_params},
1751 };
1752 struct vclk_lut div_clk_aud_uaif1_lut[] = {
1753         {26000, dft_clk_aud_uaif1_blk_dispaud_nm_lut_params},
1754 };
1755 struct vclk_lut div_clk_aud_fm_lut[] = {
1756         {30000, dft_clk_aud_fm_blk_dispaud_nm_lut_params},
1757 };
1758 struct vclk_lut mux_mif_cmuref_lut[] = {
1759         {199875, occ_mif_cmuref_blk_mif_nm_lut_params},
1760 };
1761 struct vclk_lut mux_mif1_cmuref_lut[] = {
1762         {100000, occ_mif1_cmuref_blk_mif1_nm_lut_params},
1763 };
1764 struct vclk_lut pll_mif1_lut[] = {
1765         {100000, clk_mif1_busd_blk_mif1_nm_lut_params},
1766 };
1767 struct vclk_lut div_clk_peri_spi0_lut[] = {
1768         {399750, spl_clk_peri_spi0_blk_peri_nm_lut_params},
1769 };
1770 struct vclk_lut div_clk_peri_spi2_lut[] = {
1771         {399750, spl_clk_peri_spi2_blk_peri_nm_lut_params},
1772 };
1773 struct vclk_lut div_clk_peri_usi_i2c_lut[] = {
1774         {199875, spl_clk_peri_usi_i2c_blk_peri_nm_lut_params},
1775 };
1776 struct vclk_lut div_clk_peri_spi1_lut[] = {
1777         {399750, spl_clk_peri_spi1_blk_peri_nm_lut_params},
1778 };
1779 struct vclk_lut div_clk_peri_usi_usi_lut[] = {
1780         {399750, spl_clk_peri_usi_usi_blk_peri_nm_lut_params},
1781 };
1782 struct vclk_lut div_clk_shub_i2c_lut[] = {
1783         {200000, spl_clk_shub_i2c_blk_shub_nm_lut_params},
1784 };
1785 struct vclk_lut div_clk_shub_usi00_lut[] = {
1786         {400000, spl_clk_shub_usi00_blk_shub_nm_lut_params},
1787 };
1788
1789 /* COMMON LUT */
1790 struct vclk_lut blk_apm_lut[] = {
1791         {400000, blk_apm_lut_params},
1792 };
1793 struct vclk_lut blk_cam_lut[] = {
1794         {266500, blk_cam_lut_params},
1795 };
1796 struct vclk_lut blk_cmgp_lut[] = {
1797         {200000, blk_cmgp_lut_params},
1798 };
1799 struct vclk_lut blk_cmu_lut[] = {
1800         {799999, blk_cmu_lut_params},
1801 };
1802 struct vclk_lut blk_core_lut[] = {
1803         {333125, blk_core_lut_params},
1804 };
1805 struct vclk_lut blk_cpucl0_lut[] = {
1806         {131218, blk_cpucl0_lut_params},
1807 };
1808 struct vclk_lut blk_cpucl1_lut[] = {
1809         {187416, blk_cpucl1_lut_params},
1810 };
1811 struct vclk_lut blk_dispaud_lut[] = {
1812         {1179648, blk_dispaud_lut_params},
1813 };
1814 struct vclk_lut blk_g2d_lut[] = {
1815         {266500, blk_g2d_lut_params},
1816 };
1817 struct vclk_lut blk_g3d_lut[] = {
1818         {187500, blk_g3d_lut_params},
1819 };
1820 struct vclk_lut blk_isp_lut[] = {
1821         {222083, blk_isp_lut_params},
1822 };
1823 struct vclk_lut blk_mfc_lut[] = {
1824         {333125, blk_mfc_lut_params},
1825 };
1826 struct vclk_lut blk_peri_lut[] = {
1827         {199875, blk_peri_lut_params},
1828 };
1829 struct vclk_lut blk_shub_lut[] = {
1830         {400000, blk_shub_lut_params},
1831 };
1832 struct vclk_lut blk_vipx1_lut[] = {
1833         {266500, blk_vipx1_lut_params},
1834 };
1835 struct vclk_lut blk_vipx2_lut[] = {
1836         {266500, blk_vipx2_lut_params},
1837 };
1838 /*=================VCLK Switch list================================*/
1839
1840 struct vclk_switch vclk_switch_blk_cpucl0[] = {
1841         {MUX_CLK_CPUCL0_PLL, MUX_CLKCMU_CPUCL0_SWITCH, CLKCMU_CPUCL0_SWITCH, GATE_CLKCMU_CPUCL0_SWITCH, MUX_CLKCMU_CPUCL0_SWITCH_USER, tail_blk_cpucl0_lut, 3},
1842 };
1843 struct vclk_switch vclk_switch_blk_cpucl1[] = {
1844         {MUX_CLK_CPUCL1_PLL, MUX_CLKCMU_CPUCL1_SWITCH, CLKCMU_CPUCL1_SWITCH, GATE_CLKCMU_CPUCL1_SWITCH, MUX_CLKCMU_CPUCL1_SWITCH_USER, tail_blk_cpucl1_lut, 2},
1845 };
1846 struct vclk_switch vclk_switch_blk_dispaud[] = {
1847         {MUX_CLK_AUD_CPU, MUX_CLKCMU_DISPAUD_CPU, CLKCMU_DISPAUD_CPU, GATE_CLKCMU_DISPAUD_CPU, MUX_CLKCMU_DISPAUD_CPU_USER, tail_blk_dispaud_lut, 3},
1848 };
1849 struct vclk_switch vclk_switch_blk_g3d[] = {
1850         {MUX_CLK_G3D_BUSD, MUX_CLKCMU_G3D_SWITCH, CLKCMU_G3D_SWITCH, GATE_CLKCMU_G3D_SWITCH, MUX_CLKCMU_G3D_SWITCH_USER, tail_blk_g3d_lut, 3},
1851 };
1852 struct vclk_switch vclk_switch_blk_mif[] = {
1853         {MUX_CLK_MIF_DDRPHY_CLK2X, MUX_CLKCMU_MIF_SWITCH, EMPTY_CAL_ID, CLKCMU_MIF_SWITCH, EMPTY_CAL_ID, tail_blk_mif_lut, 2},
1854 };
1855 struct vclk_switch vclk_switch_blk_mif1[] = {
1856         {MUX_CLK_MIF1_DDRPHY_CLK2X, MUX_CLKCMU_MIF_SWITCH, EMPTY_CAL_ID, CLKCMU_MIF_SWITCH, EMPTY_CAL_ID, tail_blk_mif1_lut, 2},
1857 };
1858
1859 /*=================VCLK list================================*/
1860
1861 struct vclk cmucal_vclk_list[] = {
1862
1863 /* DVFS VCLK */
1864         CMUCAL_VCLK(VCLK_VDD_CPUCL0, vdd_cpucl0_lut, cmucal_vclk_vdd_cpucl0, NULL, vclk_switch_blk_cpucl0),
1865         CMUCAL_VCLK(VCLK_VDD_CPUCL1, vdd_cpucl1_lut, cmucal_vclk_vdd_cpucl1, NULL, vclk_switch_blk_cpucl1),
1866         CMUCAL_VCLK(VCLK_VDD_G3D, vdd_g3d_lut, cmucal_vclk_vdd_g3d, NULL, vclk_switch_blk_g3d),
1867         CMUCAL_VCLK(VCLK_VDD_INT, vdd_int_lut, cmucal_vclk_vdd_int, NULL, NULL),
1868         CMUCAL_VCLK(VCLK_VDD_CAM, vdd_cam_lut, cmucal_vclk_vdd_cam, NULL, NULL),
1869         CMUCAL_VCLK(VCLK_VDD_MIF, vdd_mif_lut, cmucal_vclk_vdd_mif, NULL, vclk_switch_blk_mif),
1870
1871 /* SPECIAL VCLK */
1872         CMUCAL_VCLK(VCLK_CLKCMU_SHUB_BUS, clkcmu_shub_bus_lut, cmucal_vclk_clkcmu_shub_bus, NULL, NULL),
1873         CMUCAL_VCLK(VCLK_DIV_CLK_CMGP_ADC, div_clk_cmgp_adc_lut, cmucal_vclk_div_clk_cmgp_adc, NULL, NULL),
1874         CMUCAL_VCLK(VCLK_DIV_CLK_CMGP_USI01, div_clk_cmgp_usi01_lut, cmucal_vclk_div_clk_cmgp_usi01, NULL, NULL),
1875         CMUCAL_VCLK(VCLK_DIV_CLK_CMGP_USI03, div_clk_cmgp_usi03_lut, cmucal_vclk_div_clk_cmgp_usi03, NULL, NULL),
1876         CMUCAL_VCLK(VCLK_DIV_CLK_CMGP_USI02, div_clk_cmgp_usi02_lut, cmucal_vclk_div_clk_cmgp_usi02, NULL, NULL),
1877         CMUCAL_VCLK(VCLK_DIV_CLK_CMGP_USI00, div_clk_cmgp_usi00_lut, cmucal_vclk_div_clk_cmgp_usi00, NULL, NULL),
1878         CMUCAL_VCLK(VCLK_DIV_CLK_CMGP_USI04, div_clk_cmgp_usi04_lut, cmucal_vclk_div_clk_cmgp_usi04, NULL, NULL),
1879         CMUCAL_VCLK(VCLK_CLKCMU_FSYS_UFS_EMBD, clkcmu_fsys_ufs_embd_lut, cmucal_vclk_clkcmu_fsys_ufs_embd, NULL, NULL),
1880         CMUCAL_VCLK(VCLK_DIV_CLK_CMU_CMUREF, div_clk_cmu_cmuref_lut, cmucal_vclk_div_clk_cmu_cmuref, NULL, NULL),
1881         CMUCAL_VCLK(VCLK_CLKCMU_HPM, clkcmu_hpm_lut, cmucal_vclk_clkcmu_hpm, NULL, NULL),
1882         CMUCAL_VCLK(VCLK_CLKCMU_PERI_IP, clkcmu_peri_ip_lut, cmucal_vclk_clkcmu_peri_ip, NULL, NULL),
1883         CMUCAL_VCLK(VCLK_CLKCMU_MIF_BUSP, clkcmu_mif_busp_lut, cmucal_vclk_clkcmu_mif_busp, NULL, NULL),
1884         CMUCAL_VCLK(VCLK_CLKCMU_APM_BUS, clkcmu_apm_bus_lut, cmucal_vclk_clkcmu_apm_bus, NULL, NULL),
1885         CMUCAL_VCLK(VCLK_CLKCMU_CIS_CLK1, clkcmu_cis_clk1_lut, cmucal_vclk_clkcmu_cis_clk1, NULL, NULL),
1886         CMUCAL_VCLK(VCLK_CLKCMU_CIS_CLK3, clkcmu_cis_clk3_lut, cmucal_vclk_clkcmu_cis_clk3, NULL, NULL),
1887         CMUCAL_VCLK(VCLK_CLKCMU_USB_USB30DRD, clkcmu_usb_usb30drd_lut, cmucal_vclk_clkcmu_usb_usb30drd, NULL, NULL),
1888         CMUCAL_VCLK(VCLK_CLKCMU_CIS_CLK0, clkcmu_cis_clk0_lut, cmucal_vclk_clkcmu_cis_clk0, NULL, NULL),
1889         CMUCAL_VCLK(VCLK_CLKCMU_USB_DPGTC, clkcmu_usb_dpgtc_lut, cmucal_vclk_clkcmu_usb_dpgtc, NULL, NULL),
1890         CMUCAL_VCLK(VCLK_CLKCMU_CIS_CLK2, clkcmu_cis_clk2_lut, cmucal_vclk_clkcmu_cis_clk2, NULL, NULL),
1891         CMUCAL_VCLK(VCLK_CLKCMU_PERI_UART, clkcmu_peri_uart_lut, cmucal_vclk_clkcmu_peri_uart, NULL, NULL),
1892         CMUCAL_VCLK(VCLK_DIV_CLK_CLUSTER0_PCLKDBG, div_clk_cluster0_pclkdbg_lut, cmucal_vclk_div_clk_cluster0_pclkdbg, NULL, NULL),
1893         CMUCAL_VCLK(VCLK_DIV_CLK_CLUSTER0_ACLK, div_clk_cluster0_aclk_lut, cmucal_vclk_div_clk_cluster0_aclk, NULL, NULL),
1894         CMUCAL_VCLK(VCLK_DIV_CLK_CPUCL0_CMUREF, div_clk_cpucl0_cmuref_lut, cmucal_vclk_div_clk_cpucl0_cmuref, NULL, NULL),
1895         CMUCAL_VCLK(VCLK_DIV_CLK_CLUSTER0_CNTCLK, div_clk_cluster0_cntclk_lut, cmucal_vclk_div_clk_cluster0_cntclk, NULL, NULL),
1896         CMUCAL_VCLK(VCLK_DIV_CLK_CLUSTER1_CNTCLK, div_clk_cluster1_cntclk_lut, cmucal_vclk_div_clk_cluster1_cntclk, NULL, NULL),
1897         CMUCAL_VCLK(VCLK_DIV_CLK_CPUCL1_CMUREF, div_clk_cpucl1_cmuref_lut, cmucal_vclk_div_clk_cpucl1_cmuref, NULL, NULL),
1898         CMUCAL_VCLK(VCLK_DIV_CLK_AUD_DSIF, div_clk_aud_dsif_lut, cmucal_vclk_div_clk_aud_dsif, NULL, NULL),
1899         CMUCAL_VCLK(VCLK_DIV_CLK_AUD_UAIF0, div_clk_aud_uaif0_lut, cmucal_vclk_div_clk_aud_uaif0, NULL, NULL),
1900         CMUCAL_VCLK(VCLK_DIV_CLK_AUD_UAIF2, div_clk_aud_uaif2_lut, cmucal_vclk_div_clk_aud_uaif2, NULL, NULL),
1901         CMUCAL_VCLK(VCLK_DIV_CLK_AUD_CPU_PCLKDBG, div_clk_aud_cpu_pclkdbg_lut, cmucal_vclk_div_clk_aud_cpu_pclkdbg, NULL, NULL),
1902         CMUCAL_VCLK(VCLK_DIV_CLK_AUD_UAIF1, div_clk_aud_uaif1_lut, cmucal_vclk_div_clk_aud_uaif1, NULL, NULL),
1903         CMUCAL_VCLK(VCLK_DIV_CLK_AUD_FM, div_clk_aud_fm_lut, cmucal_vclk_div_clk_aud_fm, NULL, NULL),
1904         CMUCAL_VCLK(VCLK_MUX_MIF_CMUREF, mux_mif_cmuref_lut, cmucal_vclk_mux_mif_cmuref, NULL, NULL),
1905         CMUCAL_VCLK(VCLK_MUX_MIF1_CMUREF, mux_mif1_cmuref_lut, cmucal_vclk_mux_mif1_cmuref, NULL, NULL),
1906         CMUCAL_VCLK(VCLK_PLL_MIF1, pll_mif1_lut, cmucal_vclk_pll_mif1, NULL, vclk_switch_blk_mif1),
1907         CMUCAL_VCLK(VCLK_DIV_CLK_PERI_SPI0, div_clk_peri_spi0_lut, cmucal_vclk_div_clk_peri_spi0, NULL, NULL),
1908         CMUCAL_VCLK(VCLK_DIV_CLK_PERI_SPI2, div_clk_peri_spi2_lut, cmucal_vclk_div_clk_peri_spi2, NULL, NULL),
1909         CMUCAL_VCLK(VCLK_DIV_CLK_PERI_USI_I2C, div_clk_peri_usi_i2c_lut, cmucal_vclk_div_clk_peri_usi_i2c, NULL, NULL),
1910         CMUCAL_VCLK(VCLK_DIV_CLK_PERI_SPI1, div_clk_peri_spi1_lut, cmucal_vclk_div_clk_peri_spi1, NULL, NULL),
1911         CMUCAL_VCLK(VCLK_DIV_CLK_PERI_USI_USI, div_clk_peri_usi_usi_lut, cmucal_vclk_div_clk_peri_usi_usi, NULL, NULL),
1912         CMUCAL_VCLK(VCLK_DIV_CLK_SHUB_I2C, div_clk_shub_i2c_lut, cmucal_vclk_div_clk_shub_i2c, NULL, NULL),
1913         CMUCAL_VCLK(VCLK_DIV_CLK_SHUB_USI00, div_clk_shub_usi00_lut, cmucal_vclk_div_clk_shub_usi00, NULL, NULL),
1914
1915 /* COMMON VCLK */
1916         CMUCAL_VCLK(VCLK_BLK_APM, blk_apm_lut, cmucal_vclk_blk_apm, NULL, NULL),
1917         CMUCAL_VCLK(VCLK_BLK_CAM, blk_cam_lut, cmucal_vclk_blk_cam, NULL, NULL),
1918         CMUCAL_VCLK(VCLK_BLK_CMGP, blk_cmgp_lut, cmucal_vclk_blk_cmgp, NULL, NULL),
1919         CMUCAL_VCLK(VCLK_BLK_CMU, blk_cmu_lut, cmucal_vclk_blk_cmu, NULL, NULL),
1920         CMUCAL_VCLK(VCLK_BLK_CORE, blk_core_lut, cmucal_vclk_blk_core, NULL, NULL),
1921         CMUCAL_VCLK(VCLK_BLK_CPUCL0, blk_cpucl0_lut, cmucal_vclk_blk_cpucl0, NULL, NULL),
1922         CMUCAL_VCLK(VCLK_BLK_CPUCL1, blk_cpucl1_lut, cmucal_vclk_blk_cpucl1, NULL, NULL),
1923         CMUCAL_VCLK(VCLK_BLK_DISPAUD, blk_dispaud_lut, cmucal_vclk_blk_dispaud, NULL, vclk_switch_blk_dispaud),
1924         CMUCAL_VCLK(VCLK_BLK_G2D, blk_g2d_lut, cmucal_vclk_blk_g2d, NULL, NULL),
1925         CMUCAL_VCLK(VCLK_BLK_G3D, blk_g3d_lut, cmucal_vclk_blk_g3d, NULL, NULL),
1926         CMUCAL_VCLK(VCLK_BLK_ISP, blk_isp_lut, cmucal_vclk_blk_isp, NULL, NULL),
1927         CMUCAL_VCLK(VCLK_BLK_MFC, blk_mfc_lut, cmucal_vclk_blk_mfc, NULL, NULL),
1928         CMUCAL_VCLK(VCLK_BLK_PERI, blk_peri_lut, cmucal_vclk_blk_peri, NULL, NULL),
1929         CMUCAL_VCLK(VCLK_BLK_SHUB, blk_shub_lut, cmucal_vclk_blk_shub, NULL, NULL),
1930         CMUCAL_VCLK(VCLK_BLK_VIPX1, blk_vipx1_lut, cmucal_vclk_blk_vipx1, NULL, NULL),
1931         CMUCAL_VCLK(VCLK_BLK_VIPX2, blk_vipx2_lut, cmucal_vclk_blk_vipx2, NULL, NULL),
1932
1933 /* GATING VCLK */
1934         CMUCAL_VCLK_NULL(VCLK_IP_APBIF_GPIO_ALIVE, NULL, cmucal_vclk_ip_apbif_gpio_alive, NULL, NULL),
1935         CMUCAL_VCLK_NULL(VCLK_IP_APBIF_PMU_ALIVE, NULL, cmucal_vclk_ip_apbif_pmu_alive, NULL, NULL),
1936         CMUCAL_VCLK_NULL(VCLK_IP_APBIF_RTC, NULL, cmucal_vclk_ip_apbif_rtc, NULL, NULL),
1937         CMUCAL_VCLK_NULL(VCLK_IP_APBIF_TOP_RTC, NULL, cmucal_vclk_ip_apbif_top_rtc, NULL, NULL),
1938         CMUCAL_VCLK_NULL(VCLK_IP_APM_CMU_APM, NULL, cmucal_vclk_ip_apm_cmu_apm, NULL, NULL),
1939         CMUCAL_VCLK_NULL(VCLK_IP_GREBEINTEGRATION, NULL, cmucal_vclk_ip_grebeintegration, NULL, NULL),
1940         CMUCAL_VCLK_NULL(VCLK_IP_INTMEM, NULL, cmucal_vclk_ip_intmem, NULL, NULL),
1941         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_APM, NULL, cmucal_vclk_ip_lhm_axi_p_apm, NULL, NULL),
1942         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_APM_GNSS, NULL, cmucal_vclk_ip_lhm_axi_p_apm_gnss, NULL, NULL),
1943         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_APM_MODEM, NULL, cmucal_vclk_ip_lhm_axi_p_apm_modem, NULL, NULL),
1944         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_APM_SHUB, NULL, cmucal_vclk_ip_lhm_axi_p_apm_shub, NULL, NULL),
1945         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_APM_WLBT, NULL, cmucal_vclk_ip_lhm_axi_p_apm_wlbt, NULL, NULL),
1946         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_D_APM, NULL, cmucal_vclk_ip_lhs_axi_d_apm, NULL, NULL),
1947         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_LP_SHUB, NULL, cmucal_vclk_ip_lhs_axi_lp_shub, NULL, NULL),
1948         CMUCAL_VCLK_NULL(VCLK_IP_MAILBOX_AP2CP, NULL, cmucal_vclk_ip_mailbox_ap2cp, NULL, NULL),
1949         CMUCAL_VCLK_NULL(VCLK_IP_MAILBOX_AP2CP_S, NULL, cmucal_vclk_ip_mailbox_ap2cp_s, NULL, NULL),
1950         CMUCAL_VCLK_NULL(VCLK_IP_MAILBOX_AP2GNSS, NULL, cmucal_vclk_ip_mailbox_ap2gnss, NULL, NULL),
1951         CMUCAL_VCLK_NULL(VCLK_IP_MAILBOX_AP2SHUB, NULL, cmucal_vclk_ip_mailbox_ap2shub, NULL, NULL),
1952         CMUCAL_VCLK_NULL(VCLK_IP_MAILBOX_AP2WLBT, NULL, cmucal_vclk_ip_mailbox_ap2wlbt, NULL, NULL),
1953         CMUCAL_VCLK_NULL(VCLK_IP_MAILBOX_APM2AP, NULL, cmucal_vclk_ip_mailbox_apm2ap, NULL, NULL),
1954         CMUCAL_VCLK_NULL(VCLK_IP_MAILBOX_APM2CP, NULL, cmucal_vclk_ip_mailbox_apm2cp, NULL, NULL),
1955         CMUCAL_VCLK_NULL(VCLK_IP_MAILBOX_APM2GNSS, NULL, cmucal_vclk_ip_mailbox_apm2gnss, NULL, NULL),
1956         CMUCAL_VCLK_NULL(VCLK_IP_MAILBOX_APM2SHUB, NULL, cmucal_vclk_ip_mailbox_apm2shub, NULL, NULL),
1957         CMUCAL_VCLK_NULL(VCLK_IP_MAILBOX_APM2WLBT, NULL, cmucal_vclk_ip_mailbox_apm2wlbt, NULL, NULL),
1958         CMUCAL_VCLK_NULL(VCLK_IP_MAILBOX_CP2GNSS, NULL, cmucal_vclk_ip_mailbox_cp2gnss, NULL, NULL),
1959         CMUCAL_VCLK_NULL(VCLK_IP_MAILBOX_CP2SHUB, NULL, cmucal_vclk_ip_mailbox_cp2shub, NULL, NULL),
1960         CMUCAL_VCLK_NULL(VCLK_IP_MAILBOX_CP2WLBT, NULL, cmucal_vclk_ip_mailbox_cp2wlbt, NULL, NULL),
1961         CMUCAL_VCLK_NULL(VCLK_IP_MAILBOX_SHUB2GNSS, NULL, cmucal_vclk_ip_mailbox_shub2gnss, NULL, NULL),
1962         CMUCAL_VCLK_NULL(VCLK_IP_MAILBOX_SHUB2WLBT, NULL, cmucal_vclk_ip_mailbox_shub2wlbt, NULL, NULL),
1963         CMUCAL_VCLK_NULL(VCLK_IP_MAILBOX_WLBT2ABOX, NULL, cmucal_vclk_ip_mailbox_wlbt2abox, NULL, NULL),
1964         CMUCAL_VCLK_NULL(VCLK_IP_MAILBOX_WLBT2GNSS, NULL, cmucal_vclk_ip_mailbox_wlbt2gnss, NULL, NULL),
1965         CMUCAL_VCLK_NULL(VCLK_IP_PEM, NULL, cmucal_vclk_ip_pem, NULL, NULL),
1966         CMUCAL_VCLK_NULL(VCLK_IP_PGEN_LITE_APM, NULL, cmucal_vclk_ip_pgen_lite_apm, NULL, NULL),
1967         CMUCAL_VCLK_NULL(VCLK_IP_PMU_INTR_GEN, NULL, cmucal_vclk_ip_pmu_intr_gen, NULL, NULL),
1968         CMUCAL_VCLK_NULL(VCLK_IP_SPEEDY_APM, NULL, cmucal_vclk_ip_speedy_apm, NULL, NULL),
1969         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_APM, NULL, cmucal_vclk_ip_sysreg_apm, NULL, NULL),
1970         CMUCAL_VCLK_NULL(VCLK_IP_WDT_APM, NULL, cmucal_vclk_ip_wdt_apm, NULL, NULL),
1971         CMUCAL_VCLK_NULL(VCLK_IP_XIU_DP_APM, NULL, cmucal_vclk_ip_xiu_dp_apm, NULL, NULL),
1972         CMUCAL_VCLK_NULL(VCLK_IP_BLK_CAM, NULL, cmucal_vclk_ip_blk_cam, NULL, NULL),
1973         CMUCAL_VCLK_NULL(VCLK_IP_BTM_CAM, NULL, cmucal_vclk_ip_btm_cam, NULL, NULL),
1974         CMUCAL_VCLK_NULL(VCLK_IP_CAM_CMU_CAM, NULL, cmucal_vclk_ip_cam_cmu_cam, NULL, NULL),
1975         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_CAM, NULL, cmucal_vclk_ip_lhm_axi_p_cam, NULL, NULL),
1976         CMUCAL_VCLK_NULL(VCLK_IP_LHS_ACEL_D_CAM, NULL, cmucal_vclk_ip_lhs_acel_d_cam, NULL, NULL),
1977         CMUCAL_VCLK_NULL(VCLK_IP_LHS_ATB_CAMISP, NULL, cmucal_vclk_ip_lhs_atb_camisp, NULL, NULL),
1978         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_CAM, NULL, cmucal_vclk_ip_sysreg_cam, NULL, NULL),
1979         CMUCAL_VCLK_NULL(VCLK_IP_is6p10p0_CAM, NULL, cmucal_vclk_ip_is6p10p0_cam, NULL, NULL),
1980         CMUCAL_VCLK_NULL(VCLK_IP_ADC_CMGP, NULL, cmucal_vclk_ip_adc_cmgp, NULL, NULL),
1981         CMUCAL_VCLK_NULL(VCLK_IP_CMGP_CMU_CMGP, NULL, cmucal_vclk_ip_cmgp_cmu_cmgp, NULL, NULL),
1982         CMUCAL_VCLK_NULL(VCLK_IP_GPIO_CMGP, NULL, cmucal_vclk_ip_gpio_cmgp, NULL, NULL),
1983         CMUCAL_VCLK_NULL(VCLK_IP_I2C_CMGP00, NULL, cmucal_vclk_ip_i2c_cmgp00, NULL, NULL),
1984         CMUCAL_VCLK_NULL(VCLK_IP_I2C_CMGP01, NULL, cmucal_vclk_ip_i2c_cmgp01, NULL, NULL),
1985         CMUCAL_VCLK_NULL(VCLK_IP_I2C_CMGP02, NULL, cmucal_vclk_ip_i2c_cmgp02, NULL, NULL),
1986         CMUCAL_VCLK_NULL(VCLK_IP_I2C_CMGP03, NULL, cmucal_vclk_ip_i2c_cmgp03, NULL, NULL),
1987         CMUCAL_VCLK_NULL(VCLK_IP_I2C_CMGP04, NULL, cmucal_vclk_ip_i2c_cmgp04, NULL, NULL),
1988         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_CMGP, NULL, cmucal_vclk_ip_sysreg_cmgp, NULL, NULL),
1989         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_CMGP2CP, NULL, cmucal_vclk_ip_sysreg_cmgp2cp, NULL, NULL),
1990         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_CMGP2GNSS, NULL, cmucal_vclk_ip_sysreg_cmgp2gnss, NULL, NULL),
1991         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_CMGP2PMU_AP, NULL, cmucal_vclk_ip_sysreg_cmgp2pmu_ap, NULL, NULL),
1992         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_CMGP2PMU_SHUB, NULL, cmucal_vclk_ip_sysreg_cmgp2pmu_shub, NULL, NULL),
1993         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_CMGP2SHUB, NULL, cmucal_vclk_ip_sysreg_cmgp2shub, NULL, NULL),
1994         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_CMGP2WLBT, NULL, cmucal_vclk_ip_sysreg_cmgp2wlbt, NULL, NULL),
1995         CMUCAL_VCLK_NULL(VCLK_IP_USI_CMGP00, NULL, cmucal_vclk_ip_usi_cmgp00, NULL, NULL),
1996         CMUCAL_VCLK_NULL(VCLK_IP_USI_CMGP01, NULL, cmucal_vclk_ip_usi_cmgp01, NULL, NULL),
1997         CMUCAL_VCLK_NULL(VCLK_IP_USI_CMGP02, NULL, cmucal_vclk_ip_usi_cmgp02, NULL, NULL),
1998         CMUCAL_VCLK_NULL(VCLK_IP_USI_CMGP03, NULL, cmucal_vclk_ip_usi_cmgp03, NULL, NULL),
1999         CMUCAL_VCLK_NULL(VCLK_IP_USI_CMGP04, NULL, cmucal_vclk_ip_usi_cmgp04, NULL, NULL),
2000         CMUCAL_VCLK_NULL(VCLK_IP_OTP, NULL, cmucal_vclk_ip_otp, NULL, NULL),
2001         CMUCAL_VCLK_NULL(VCLK_IP_AD_APB_CCI_550, NULL, cmucal_vclk_ip_ad_apb_cci_550, NULL, NULL),
2002         CMUCAL_VCLK_NULL(VCLK_IP_AD_APB_DIT, NULL, cmucal_vclk_ip_ad_apb_dit, NULL, NULL),
2003         CMUCAL_VCLK_NULL(VCLK_IP_AD_APB_PDMA0, NULL, cmucal_vclk_ip_ad_apb_pdma0, NULL, NULL),
2004         CMUCAL_VCLK_NULL(VCLK_IP_AD_APB_PGEN_PDMA, NULL, cmucal_vclk_ip_ad_apb_pgen_pdma, NULL, NULL),
2005         CMUCAL_VCLK_NULL(VCLK_IP_AD_APB_PPFW_MEM0, NULL, cmucal_vclk_ip_ad_apb_ppfw_mem0, NULL, NULL),
2006         CMUCAL_VCLK_NULL(VCLK_IP_AD_APB_PPFW_MEM1, NULL, cmucal_vclk_ip_ad_apb_ppfw_mem1, NULL, NULL),
2007         CMUCAL_VCLK_NULL(VCLK_IP_AD_APB_PPFW_PERI, NULL, cmucal_vclk_ip_ad_apb_ppfw_peri, NULL, NULL),
2008         CMUCAL_VCLK_NULL(VCLK_IP_AD_APB_SPDMA, NULL, cmucal_vclk_ip_ad_apb_spdma, NULL, NULL),
2009         CMUCAL_VCLK_NULL(VCLK_IP_AD_AXI_GIC, NULL, cmucal_vclk_ip_ad_axi_gic, NULL, NULL),
2010         CMUCAL_VCLK_NULL(VCLK_IP_ASYNCSFR_WR_DMC0, NULL, cmucal_vclk_ip_asyncsfr_wr_dmc0, NULL, NULL),
2011         CMUCAL_VCLK_NULL(VCLK_IP_ASYNCSFR_WR_DMC1, NULL, cmucal_vclk_ip_asyncsfr_wr_dmc1, NULL, NULL),
2012         CMUCAL_VCLK_NULL(VCLK_IP_AXI_US_A40_64to128_DIT, NULL, cmucal_vclk_ip_axi_us_a40_64to128_dit, NULL, NULL),
2013         CMUCAL_VCLK_NULL(VCLK_IP_BAAW_P_GNSS, NULL, cmucal_vclk_ip_baaw_p_gnss, NULL, NULL),
2014         CMUCAL_VCLK_NULL(VCLK_IP_BAAW_P_MODEM, NULL, cmucal_vclk_ip_baaw_p_modem, NULL, NULL),
2015         CMUCAL_VCLK_NULL(VCLK_IP_BAAW_P_SHUB, NULL, cmucal_vclk_ip_baaw_p_shub, NULL, NULL),
2016         CMUCAL_VCLK_NULL(VCLK_IP_BAAW_P_WLBT, NULL, cmucal_vclk_ip_baaw_p_wlbt, NULL, NULL),
2017         CMUCAL_VCLK_NULL(VCLK_IP_CCI_550, NULL, cmucal_vclk_ip_cci_550, NULL, NULL),
2018         CMUCAL_VCLK_NULL(VCLK_IP_CORE_CMU_CORE, NULL, cmucal_vclk_ip_core_cmu_core, NULL, NULL),
2019         CMUCAL_VCLK_NULL(VCLK_IP_DIT, NULL, cmucal_vclk_ip_dit, NULL, NULL),
2020         CMUCAL_VCLK_NULL(VCLK_IP_GIC400_AIHWACG, NULL, cmucal_vclk_ip_gic400_aihwacg, NULL, NULL),
2021         CMUCAL_VCLK_NULL(VCLK_IP_LHM_ACEL_D0_ISP, NULL, cmucal_vclk_ip_lhm_acel_d0_isp, NULL, NULL),
2022         CMUCAL_VCLK_NULL(VCLK_IP_LHM_ACEL_D0_MFC, NULL, cmucal_vclk_ip_lhm_acel_d0_mfc, NULL, NULL),
2023         CMUCAL_VCLK_NULL(VCLK_IP_LHM_ACEL_D1_ISP, NULL, cmucal_vclk_ip_lhm_acel_d1_isp, NULL, NULL),
2024         CMUCAL_VCLK_NULL(VCLK_IP_LHM_ACEL_D1_MFC, NULL, cmucal_vclk_ip_lhm_acel_d1_mfc, NULL, NULL),
2025         CMUCAL_VCLK_NULL(VCLK_IP_LHM_ACEL_D_CAM, NULL, cmucal_vclk_ip_lhm_acel_d_cam, NULL, NULL),
2026         CMUCAL_VCLK_NULL(VCLK_IP_LHM_ACEL_D_DPU, NULL, cmucal_vclk_ip_lhm_acel_d_dpu, NULL, NULL),
2027         CMUCAL_VCLK_NULL(VCLK_IP_LHM_ACEL_D_FSYS, NULL, cmucal_vclk_ip_lhm_acel_d_fsys, NULL, NULL),
2028         CMUCAL_VCLK_NULL(VCLK_IP_LHM_ACEL_D_G2D, NULL, cmucal_vclk_ip_lhm_acel_d_g2d, NULL, NULL),
2029         CMUCAL_VCLK_NULL(VCLK_IP_LHM_ACEL_D_USB, NULL, cmucal_vclk_ip_lhm_acel_d_usb, NULL, NULL),
2030         CMUCAL_VCLK_NULL(VCLK_IP_LHM_ACEL_D_VIPX1, NULL, cmucal_vclk_ip_lhm_acel_d_vipx1, NULL, NULL),
2031         CMUCAL_VCLK_NULL(VCLK_IP_LHM_ACEL_D_VIPX2, NULL, cmucal_vclk_ip_lhm_acel_d_vipx2, NULL, NULL),
2032         CMUCAL_VCLK_NULL(VCLK_IP_LHM_ACE_D_CPUCL0, NULL, cmucal_vclk_ip_lhm_ace_d_cpucl0, NULL, NULL),
2033         CMUCAL_VCLK_NULL(VCLK_IP_LHM_ACE_D_CPUCL1, NULL, cmucal_vclk_ip_lhm_ace_d_cpucl1, NULL, NULL),
2034         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_D0_MODEM, NULL, cmucal_vclk_ip_lhm_axi_d0_modem, NULL, NULL),
2035         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_D1_MODEM, NULL, cmucal_vclk_ip_lhm_axi_d1_modem, NULL, NULL),
2036         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_D_ABOX, NULL, cmucal_vclk_ip_lhm_axi_d_abox, NULL, NULL),
2037         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_D_APM, NULL, cmucal_vclk_ip_lhm_axi_d_apm, NULL, NULL),
2038         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_D_CSSYS, NULL, cmucal_vclk_ip_lhm_axi_d_cssys, NULL, NULL),
2039         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_D_G3D, NULL, cmucal_vclk_ip_lhm_axi_d_g3d, NULL, NULL),
2040         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_D_GNSS, NULL, cmucal_vclk_ip_lhm_axi_d_gnss, NULL, NULL),
2041         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_D_SHUB, NULL, cmucal_vclk_ip_lhm_axi_d_shub, NULL, NULL),
2042         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_D_WLBT, NULL, cmucal_vclk_ip_lhm_axi_d_wlbt, NULL, NULL),
2043         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_D0_MIF_CP, NULL, cmucal_vclk_ip_lhs_axi_d0_mif_cp, NULL, NULL),
2044         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_D0_MIF_CPU, NULL, cmucal_vclk_ip_lhs_axi_d0_mif_cpu, NULL, NULL),
2045         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_D0_MIF_NRT, NULL, cmucal_vclk_ip_lhs_axi_d0_mif_nrt, NULL, NULL),
2046         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_D0_MIF_RT, NULL, cmucal_vclk_ip_lhs_axi_d0_mif_rt, NULL, NULL),
2047         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_D1_MIF_CP, NULL, cmucal_vclk_ip_lhs_axi_d1_mif_cp, NULL, NULL),
2048         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_D1_MIF_CPU, NULL, cmucal_vclk_ip_lhs_axi_d1_mif_cpu, NULL, NULL),
2049         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_D1_MIF_NRT, NULL, cmucal_vclk_ip_lhs_axi_d1_mif_nrt, NULL, NULL),
2050         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_D1_MIF_RT, NULL, cmucal_vclk_ip_lhs_axi_d1_mif_rt, NULL, NULL),
2051         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_APM, NULL, cmucal_vclk_ip_lhs_axi_p_apm, NULL, NULL),
2052         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_CAM, NULL, cmucal_vclk_ip_lhs_axi_p_cam, NULL, NULL),
2053         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_CPUCL0, NULL, cmucal_vclk_ip_lhs_axi_p_cpucl0, NULL, NULL),
2054         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_CPUCL1, NULL, cmucal_vclk_ip_lhs_axi_p_cpucl1, NULL, NULL),
2055         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_DISPAUD, NULL, cmucal_vclk_ip_lhs_axi_p_dispaud, NULL, NULL),
2056         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_FSYS, NULL, cmucal_vclk_ip_lhs_axi_p_fsys, NULL, NULL),
2057         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_G2D, NULL, cmucal_vclk_ip_lhs_axi_p_g2d, NULL, NULL),
2058         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_G3D, NULL, cmucal_vclk_ip_lhs_axi_p_g3d, NULL, NULL),
2059         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_GNSS, NULL, cmucal_vclk_ip_lhs_axi_p_gnss, NULL, NULL),
2060         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_ISP, NULL, cmucal_vclk_ip_lhs_axi_p_isp, NULL, NULL),
2061         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_MFC, NULL, cmucal_vclk_ip_lhs_axi_p_mfc, NULL, NULL),
2062         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_MIF0, NULL, cmucal_vclk_ip_lhs_axi_p_mif0, NULL, NULL),
2063         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_MIF1, NULL, cmucal_vclk_ip_lhs_axi_p_mif1, NULL, NULL),
2064         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_MODEM, NULL, cmucal_vclk_ip_lhs_axi_p_modem, NULL, NULL),
2065         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_PERI, NULL, cmucal_vclk_ip_lhs_axi_p_peri, NULL, NULL),
2066         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_SHUB, NULL, cmucal_vclk_ip_lhs_axi_p_shub, NULL, NULL),
2067         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_USB, NULL, cmucal_vclk_ip_lhs_axi_p_usb, NULL, NULL),
2068         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_VIPX1, NULL, cmucal_vclk_ip_lhs_axi_p_vipx1, NULL, NULL),
2069         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_VIPX2, NULL, cmucal_vclk_ip_lhs_axi_p_vipx2, NULL, NULL),
2070         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_WLBT, NULL, cmucal_vclk_ip_lhs_axi_p_wlbt, NULL, NULL),
2071         CMUCAL_VCLK_NULL(VCLK_IP_PDMA_CORE, NULL, cmucal_vclk_ip_pdma_core, NULL, NULL),
2072         CMUCAL_VCLK_NULL(VCLK_IP_PGEN_LITE_SIREX, NULL, cmucal_vclk_ip_pgen_lite_sirex, NULL, NULL),
2073         CMUCAL_VCLK_NULL(VCLK_IP_PGEN_PDMA, NULL, cmucal_vclk_ip_pgen_pdma, NULL, NULL),
2074         CMUCAL_VCLK_NULL(VCLK_IP_PPCFW_G3D, NULL, cmucal_vclk_ip_ppcfw_g3d, NULL, NULL),
2075         CMUCAL_VCLK_NULL(VCLK_IP_PPFW_CORE_MEM0, NULL, cmucal_vclk_ip_ppfw_core_mem0, NULL, NULL),
2076         CMUCAL_VCLK_NULL(VCLK_IP_PPFW_CORE_MEM1, NULL, cmucal_vclk_ip_ppfw_core_mem1, NULL, NULL),
2077         CMUCAL_VCLK_NULL(VCLK_IP_PPFW_CORE_PERI, NULL, cmucal_vclk_ip_ppfw_core_peri, NULL, NULL),
2078         CMUCAL_VCLK_NULL(VCLK_IP_PPMU_ACE_CPUCL0, NULL, cmucal_vclk_ip_ppmu_ace_cpucl0, NULL, NULL),
2079         CMUCAL_VCLK_NULL(VCLK_IP_PPMU_ACE_CPUCL1, NULL, cmucal_vclk_ip_ppmu_ace_cpucl1, NULL, NULL),
2080         CMUCAL_VCLK_NULL(VCLK_IP_SFR_APBIF_CMU_TOPC, NULL, cmucal_vclk_ip_sfr_apbif_cmu_topc, NULL, NULL),
2081         CMUCAL_VCLK_NULL(VCLK_IP_SIREX, NULL, cmucal_vclk_ip_sirex, NULL, NULL),
2082         CMUCAL_VCLK_NULL(VCLK_IP_SPDMA_CORE, NULL, cmucal_vclk_ip_spdma_core, NULL, NULL),
2083         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_CORE, NULL, cmucal_vclk_ip_sysreg_core, NULL, NULL),
2084         CMUCAL_VCLK_NULL(VCLK_IP_TREX_D_CORE, NULL, cmucal_vclk_ip_trex_d_core, NULL, NULL),
2085         CMUCAL_VCLK_NULL(VCLK_IP_TREX_D_NRT, NULL, cmucal_vclk_ip_trex_d_nrt, NULL, NULL),
2086         CMUCAL_VCLK_NULL(VCLK_IP_TREX_P_CORE, NULL, cmucal_vclk_ip_trex_p_core, NULL, NULL),
2087         CMUCAL_VCLK_NULL(VCLK_IP_XIU_D_CORE, NULL, cmucal_vclk_ip_xiu_d_core, NULL, NULL),
2088         CMUCAL_VCLK_NULL(VCLK_IP_ADM_APB_G_CSSYS_CORE, NULL, cmucal_vclk_ip_adm_apb_g_cssys_core, NULL, NULL),
2089         CMUCAL_VCLK_NULL(VCLK_IP_ADS_AHB_G_CSSYS_FSYS, NULL, cmucal_vclk_ip_ads_ahb_g_cssys_fsys, NULL, NULL),
2090         CMUCAL_VCLK_NULL(VCLK_IP_ADS_APB_G_CSSYS_CPUCL1, NULL, cmucal_vclk_ip_ads_apb_g_cssys_cpucl1, NULL, NULL),
2091         CMUCAL_VCLK_NULL(VCLK_IP_ADS_APB_G_P8Q, NULL, cmucal_vclk_ip_ads_apb_g_p8q, NULL, NULL),
2092         CMUCAL_VCLK_NULL(VCLK_IP_AD_APB_P_DUMP_PC_CPUCL0, NULL, cmucal_vclk_ip_ad_apb_p_dump_pc_cpucl0, NULL, NULL),
2093         CMUCAL_VCLK_NULL(VCLK_IP_AD_APB_P_DUMP_PC_CPUCL1, NULL, cmucal_vclk_ip_ad_apb_p_dump_pc_cpucl1, NULL, NULL),
2094         CMUCAL_VCLK_NULL(VCLK_IP_BUSIF_HPMCPUCL0, NULL, cmucal_vclk_ip_busif_hpmcpucl0, NULL, NULL),
2095         CMUCAL_VCLK_NULL(VCLK_IP_CPUCL0_CMU_CPUCL0, NULL, cmucal_vclk_ip_cpucl0_cmu_cpucl0, NULL, NULL),
2096         CMUCAL_VCLK_NULL(VCLK_IP_CSSYS_DBG, NULL, cmucal_vclk_ip_cssys_dbg, NULL, NULL),
2097         CMUCAL_VCLK_NULL(VCLK_IP_DUMP_PC_CPUCL0, NULL, cmucal_vclk_ip_dump_pc_cpucl0, NULL, NULL),
2098         CMUCAL_VCLK_NULL(VCLK_IP_DUMP_PC_CPUCL1, NULL, cmucal_vclk_ip_dump_pc_cpucl1, NULL, NULL),
2099         CMUCAL_VCLK_NULL(VCLK_IP_HPM_CPUCL0, NULL, cmucal_vclk_ip_hpm_cpucl0, NULL, NULL),
2100         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_CPUCL0, NULL, cmucal_vclk_ip_lhm_axi_p_cpucl0, NULL, NULL),
2101         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_D_CSSYS, NULL, cmucal_vclk_ip_lhs_axi_d_cssys, NULL, NULL),
2102         CMUCAL_VCLK_NULL(VCLK_IP_SECJTAG, NULL, cmucal_vclk_ip_secjtag, NULL, NULL),
2103         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_CPUCL0, NULL, cmucal_vclk_ip_sysreg_cpucl0, NULL, NULL),
2104         CMUCAL_VCLK_NULL(VCLK_IP_ADM_APB_G_CSSYS_CPUCL1, NULL, cmucal_vclk_ip_adm_apb_g_cssys_cpucl1, NULL, NULL),
2105         CMUCAL_VCLK_NULL(VCLK_IP_BUSIF_HPMCPUCL1, NULL, cmucal_vclk_ip_busif_hpmcpucl1, NULL, NULL),
2106         CMUCAL_VCLK_NULL(VCLK_IP_CPUCL1_CMU_CPUCL1, NULL, cmucal_vclk_ip_cpucl1_cmu_cpucl1, NULL, NULL),
2107         CMUCAL_VCLK_NULL(VCLK_IP_HPM_CPUCL1, NULL, cmucal_vclk_ip_hpm_cpucl1, NULL, NULL),
2108         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_CPUCL1, NULL, cmucal_vclk_ip_lhm_axi_p_cpucl1, NULL, NULL),
2109         CMUCAL_VCLK_NULL(VCLK_IP_LHS_ACE_D_CPUCL1, NULL, cmucal_vclk_ip_lhs_ace_d_cpucl1, NULL, NULL),
2110         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_CPUCL1, NULL, cmucal_vclk_ip_sysreg_cpucl1, NULL, NULL),
2111         CMUCAL_VCLK_NULL(VCLK_IP_ABOX, NULL, cmucal_vclk_ip_abox, NULL, NULL),
2112         CMUCAL_VCLK_NULL(VCLK_IP_AXI_US_32to128, NULL, cmucal_vclk_ip_axi_us_32to128, NULL, NULL),
2113         CMUCAL_VCLK_NULL(VCLK_IP_BLK_DISPAUD, NULL, cmucal_vclk_ip_blk_dispaud, NULL, NULL),
2114         CMUCAL_VCLK_NULL(VCLK_IP_BTM_ABOX, NULL, cmucal_vclk_ip_btm_abox, NULL, NULL),
2115         CMUCAL_VCLK_NULL(VCLK_IP_BTM_DPU, NULL, cmucal_vclk_ip_btm_dpu, NULL, NULL),
2116         CMUCAL_VCLK_NULL(VCLK_IP_DFTMUX_DISPAUD, NULL, cmucal_vclk_ip_dftmux_dispaud, NULL, NULL),
2117         CMUCAL_VCLK_NULL(VCLK_IP_DISPAUD_CMU_DISPAUD, NULL, cmucal_vclk_ip_dispaud_cmu_dispaud, NULL, NULL),
2118         CMUCAL_VCLK_NULL(VCLK_IP_DPU, NULL, cmucal_vclk_ip_dpu, NULL, NULL),
2119         CMUCAL_VCLK_NULL(VCLK_IP_GPIO_DISPAUD, NULL, cmucal_vclk_ip_gpio_dispaud, NULL, NULL),
2120         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_DISPAUD, NULL, cmucal_vclk_ip_lhm_axi_p_dispaud, NULL, NULL),
2121         CMUCAL_VCLK_NULL(VCLK_IP_LHS_ACEL_D_DPU, NULL, cmucal_vclk_ip_lhs_acel_d_dpu, NULL, NULL),
2122         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_D_ABOX, NULL, cmucal_vclk_ip_lhs_axi_d_abox, NULL, NULL),
2123         CMUCAL_VCLK_NULL(VCLK_IP_PERI_AXI_ASB, NULL, cmucal_vclk_ip_peri_axi_asb, NULL, NULL),
2124         CMUCAL_VCLK_NULL(VCLK_IP_PPMU_ABOX, NULL, cmucal_vclk_ip_ppmu_abox, NULL, NULL),
2125         CMUCAL_VCLK_NULL(VCLK_IP_PPMU_DPU, NULL, cmucal_vclk_ip_ppmu_dpu, NULL, NULL),
2126         CMUCAL_VCLK_NULL(VCLK_IP_SMMU_ABOX, NULL, cmucal_vclk_ip_smmu_abox, NULL, NULL),
2127         CMUCAL_VCLK_NULL(VCLK_IP_SMMU_DPU, NULL, cmucal_vclk_ip_smmu_dpu, NULL, NULL),
2128         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_DISPAUD, NULL, cmucal_vclk_ip_sysreg_dispaud, NULL, NULL),
2129         CMUCAL_VCLK_NULL(VCLK_IP_WDT_AUD, NULL, cmucal_vclk_ip_wdt_aud, NULL, NULL),
2130         CMUCAL_VCLK_NULL(VCLK_IP_ADM_AHB_SSS, NULL, cmucal_vclk_ip_adm_ahb_sss, NULL, NULL),
2131         CMUCAL_VCLK_NULL(VCLK_IP_BTM_FSYS, NULL, cmucal_vclk_ip_btm_fsys, NULL, NULL),
2132         CMUCAL_VCLK_NULL(VCLK_IP_FSYS_CMU_FSYS, NULL, cmucal_vclk_ip_fsys_cmu_fsys, NULL, NULL),
2133         CMUCAL_VCLK_NULL(VCLK_IP_GPIO_FSYS, NULL, cmucal_vclk_ip_gpio_fsys, NULL, NULL),
2134         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_FSYS, NULL, cmucal_vclk_ip_lhm_axi_p_fsys, NULL, NULL),
2135         CMUCAL_VCLK_NULL(VCLK_IP_LHS_ACEL_D_FSYS, NULL, cmucal_vclk_ip_lhs_acel_d_fsys, NULL, NULL),
2136         CMUCAL_VCLK_NULL(VCLK_IP_MMC_CARD, NULL, cmucal_vclk_ip_mmc_card, NULL, NULL),
2137         CMUCAL_VCLK_NULL(VCLK_IP_MMC_EMBD, NULL, cmucal_vclk_ip_mmc_embd, NULL, NULL),
2138         CMUCAL_VCLK_NULL(VCLK_IP_PGEN_LITE_FSYS, NULL, cmucal_vclk_ip_pgen_lite_fsys, NULL, NULL),
2139         CMUCAL_VCLK_NULL(VCLK_IP_PPMU_FSYS, NULL, cmucal_vclk_ip_ppmu_fsys, NULL, NULL),
2140         CMUCAL_VCLK_NULL(VCLK_IP_RTIC, NULL, cmucal_vclk_ip_rtic, NULL, NULL),
2141         CMUCAL_VCLK_NULL(VCLK_IP_SSS, NULL, cmucal_vclk_ip_sss, NULL, NULL),
2142         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_FSYS, NULL, cmucal_vclk_ip_sysreg_fsys, NULL, NULL),
2143         CMUCAL_VCLK_NULL(VCLK_IP_UFS_EMBD, NULL, cmucal_vclk_ip_ufs_embd, NULL, NULL),
2144         CMUCAL_VCLK_NULL(VCLK_IP_XIU_D_FSYS, NULL, cmucal_vclk_ip_xiu_d_fsys, NULL, NULL),
2145         CMUCAL_VCLK_NULL(VCLK_IP_AS_AXI_JPEG, NULL, cmucal_vclk_ip_as_axi_jpeg, NULL, NULL),
2146         CMUCAL_VCLK_NULL(VCLK_IP_AS_AXI_MSCL, NULL, cmucal_vclk_ip_as_axi_mscl, NULL, NULL),
2147         CMUCAL_VCLK_NULL(VCLK_IP_BLK_G2D, NULL, cmucal_vclk_ip_blk_g2d, NULL, NULL),
2148         CMUCAL_VCLK_NULL(VCLK_IP_BTM_G2D, NULL, cmucal_vclk_ip_btm_g2d, NULL, NULL),
2149         CMUCAL_VCLK_NULL(VCLK_IP_G2D, NULL, cmucal_vclk_ip_g2d, NULL, NULL),
2150         CMUCAL_VCLK_NULL(VCLK_IP_G2D_CMU_G2D, NULL, cmucal_vclk_ip_g2d_cmu_g2d, NULL, NULL),
2151         CMUCAL_VCLK_NULL(VCLK_IP_JPEG, NULL, cmucal_vclk_ip_jpeg, NULL, NULL),
2152         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_G2D, NULL, cmucal_vclk_ip_lhm_axi_p_g2d, NULL, NULL),
2153         CMUCAL_VCLK_NULL(VCLK_IP_LHS_ACEL_D_G2D, NULL, cmucal_vclk_ip_lhs_acel_d_g2d, NULL, NULL),
2154         CMUCAL_VCLK_NULL(VCLK_IP_MSCL, NULL, cmucal_vclk_ip_mscl, NULL, NULL),
2155         CMUCAL_VCLK_NULL(VCLK_IP_PGEN100_LITE_G2D, NULL, cmucal_vclk_ip_pgen100_lite_g2d, NULL, NULL),
2156         CMUCAL_VCLK_NULL(VCLK_IP_PPMU_G2D, NULL, cmucal_vclk_ip_ppmu_g2d, NULL, NULL),
2157         CMUCAL_VCLK_NULL(VCLK_IP_SYSMMU_G2D, NULL, cmucal_vclk_ip_sysmmu_g2d, NULL, NULL),
2158         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_G2D, NULL, cmucal_vclk_ip_sysreg_g2d, NULL, NULL),
2159         CMUCAL_VCLK_NULL(VCLK_IP_XIU_D_MSCL, NULL, cmucal_vclk_ip_xiu_d_mscl, NULL, NULL),
2160         CMUCAL_VCLK_NULL(VCLK_IP_BTM_G3D, NULL, cmucal_vclk_ip_btm_g3d, NULL, NULL),
2161         CMUCAL_VCLK_NULL(VCLK_IP_BUSIF_HPMG3D, NULL, cmucal_vclk_ip_busif_hpmg3d, NULL, NULL),
2162         CMUCAL_VCLK_NULL(VCLK_IP_G3D, NULL, cmucal_vclk_ip_g3d, NULL, NULL),
2163         CMUCAL_VCLK_NULL(VCLK_IP_G3D_CMU_G3D, NULL, cmucal_vclk_ip_g3d_cmu_g3d, NULL, NULL),
2164         CMUCAL_VCLK_NULL(VCLK_IP_GRAY2BIN_G3D, NULL, cmucal_vclk_ip_gray2bin_g3d, NULL, NULL),
2165         CMUCAL_VCLK_NULL(VCLK_IP_HPM_G3D, NULL, cmucal_vclk_ip_hpm_g3d, NULL, NULL),
2166         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_G3DSFR, NULL, cmucal_vclk_ip_lhm_axi_g3dsfr, NULL, NULL),
2167         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_G3D, NULL, cmucal_vclk_ip_lhm_axi_p_g3d, NULL, NULL),
2168         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_D_G3D, NULL, cmucal_vclk_ip_lhs_axi_d_g3d, NULL, NULL),
2169         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_G3DSFR, NULL, cmucal_vclk_ip_lhs_axi_g3dsfr, NULL, NULL),
2170         CMUCAL_VCLK_NULL(VCLK_IP_PGEN_LITE_G3D, NULL, cmucal_vclk_ip_pgen_lite_g3d, NULL, NULL),
2171         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_G3D, NULL, cmucal_vclk_ip_sysreg_g3d, NULL, NULL),
2172         CMUCAL_VCLK_NULL(VCLK_IP_BLK_ISP, NULL, cmucal_vclk_ip_blk_isp, NULL, NULL),
2173         CMUCAL_VCLK_NULL(VCLK_IP_BTM_ISP0, NULL, cmucal_vclk_ip_btm_isp0, NULL, NULL),
2174         CMUCAL_VCLK_NULL(VCLK_IP_BTM_ISP1, NULL, cmucal_vclk_ip_btm_isp1, NULL, NULL),
2175         CMUCAL_VCLK_NULL(VCLK_IP_ISP_CMU_ISP, NULL, cmucal_vclk_ip_isp_cmu_isp, NULL, NULL),
2176         CMUCAL_VCLK_NULL(VCLK_IP_LHM_ATB_CAMISP, NULL, cmucal_vclk_ip_lhm_atb_camisp, NULL, NULL),
2177         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_ISP, NULL, cmucal_vclk_ip_lhm_axi_p_isp, NULL, NULL),
2178         CMUCAL_VCLK_NULL(VCLK_IP_LHS_ACEL_D0_ISP, NULL, cmucal_vclk_ip_lhs_acel_d0_isp, NULL, NULL),
2179         CMUCAL_VCLK_NULL(VCLK_IP_LHS_ACEL_D1_ISP, NULL, cmucal_vclk_ip_lhs_acel_d1_isp, NULL, NULL),
2180         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_ISP, NULL, cmucal_vclk_ip_sysreg_isp, NULL, NULL),
2181         CMUCAL_VCLK_NULL(VCLK_IP_is6p10p0_ISP, NULL, cmucal_vclk_ip_is6p10p0_isp, NULL, NULL),
2182         CMUCAL_VCLK_NULL(VCLK_IP_AS_AXI_WFD, NULL, cmucal_vclk_ip_as_axi_wfd, NULL, NULL),
2183         CMUCAL_VCLK_NULL(VCLK_IP_BLK_MFC, NULL, cmucal_vclk_ip_blk_mfc, NULL, NULL),
2184         CMUCAL_VCLK_NULL(VCLK_IP_BTM_MFCD0, NULL, cmucal_vclk_ip_btm_mfcd0, NULL, NULL),
2185         CMUCAL_VCLK_NULL(VCLK_IP_BTM_MFCD1, NULL, cmucal_vclk_ip_btm_mfcd1, NULL, NULL),
2186         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_MFC, NULL, cmucal_vclk_ip_lhm_axi_p_mfc, NULL, NULL),
2187         CMUCAL_VCLK_NULL(VCLK_IP_LHS_ACEL_D0_MFC, NULL, cmucal_vclk_ip_lhs_acel_d0_mfc, NULL, NULL),
2188         CMUCAL_VCLK_NULL(VCLK_IP_LHS_ACEL_D1_MFC, NULL, cmucal_vclk_ip_lhs_acel_d1_mfc, NULL, NULL),
2189         CMUCAL_VCLK_NULL(VCLK_IP_LH_ATB_MFC, NULL, cmucal_vclk_ip_lh_atb_mfc, NULL, NULL),
2190         CMUCAL_VCLK_NULL(VCLK_IP_MFC, NULL, cmucal_vclk_ip_mfc, NULL, NULL),
2191         CMUCAL_VCLK_NULL(VCLK_IP_MFC_CMU_MFC, NULL, cmucal_vclk_ip_mfc_cmu_mfc, NULL, NULL),
2192         CMUCAL_VCLK_NULL(VCLK_IP_PGEN100_LITE_MFC, NULL, cmucal_vclk_ip_pgen100_lite_mfc, NULL, NULL),
2193         CMUCAL_VCLK_NULL(VCLK_IP_PPMU_MFCD0, NULL, cmucal_vclk_ip_ppmu_mfcd0, NULL, NULL),
2194         CMUCAL_VCLK_NULL(VCLK_IP_PPMU_MFCD1, NULL, cmucal_vclk_ip_ppmu_mfcd1, NULL, NULL),
2195         CMUCAL_VCLK_NULL(VCLK_IP_SYSMMU_MFCD0, NULL, cmucal_vclk_ip_sysmmu_mfcd0, NULL, NULL),
2196         CMUCAL_VCLK_NULL(VCLK_IP_SYSMMU_MFCD1, NULL, cmucal_vclk_ip_sysmmu_mfcd1, NULL, NULL),
2197         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_MFC, NULL, cmucal_vclk_ip_sysreg_mfc, NULL, NULL),
2198         CMUCAL_VCLK_NULL(VCLK_IP_WFD, NULL, cmucal_vclk_ip_wfd, NULL, NULL),
2199         CMUCAL_VCLK_NULL(VCLK_IP_XIU_D_MFC, NULL, cmucal_vclk_ip_xiu_d_mfc, NULL, NULL),
2200         CMUCAL_VCLK_NULL(VCLK_IP_BUSIF_HPMMIF, NULL, cmucal_vclk_ip_busif_hpmmif, NULL, NULL),
2201         CMUCAL_VCLK_NULL(VCLK_IP_DDR_PHY, NULL, cmucal_vclk_ip_ddr_phy, NULL, NULL),
2202         CMUCAL_VCLK_NULL(VCLK_IP_DMC, NULL, cmucal_vclk_ip_dmc, NULL, NULL),
2203         CMUCAL_VCLK_NULL(VCLK_IP_HPM_MIF, NULL, cmucal_vclk_ip_hpm_mif, NULL, NULL),
2204         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_D_MIF_CP, NULL, cmucal_vclk_ip_lhm_axi_d_mif_cp, NULL, NULL),
2205         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_D_MIF_CPU, NULL, cmucal_vclk_ip_lhm_axi_d_mif_cpu, NULL, NULL),
2206         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_D_MIF_NRT, NULL, cmucal_vclk_ip_lhm_axi_d_mif_nrt, NULL, NULL),
2207         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_D_MIF_RT, NULL, cmucal_vclk_ip_lhm_axi_d_mif_rt, NULL, NULL),
2208         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_MIF, NULL, cmucal_vclk_ip_lhm_axi_p_mif, NULL, NULL),
2209         CMUCAL_VCLK_NULL(VCLK_IP_MIF_CMU_MIF, NULL, cmucal_vclk_ip_mif_cmu_mif, NULL, NULL),
2210         CMUCAL_VCLK_NULL(VCLK_IP_PPMU_DMC_CPU, NULL, cmucal_vclk_ip_ppmu_dmc_cpu, NULL, NULL),
2211         CMUCAL_VCLK_NULL(VCLK_IP_QE_DMC_CPU, NULL, cmucal_vclk_ip_qe_dmc_cpu, NULL, NULL),
2212         CMUCAL_VCLK_NULL(VCLK_IP_SFRAPB_BRIDGE_DDR_PHY, NULL, cmucal_vclk_ip_sfrapb_bridge_ddr_phy, NULL, NULL),
2213         CMUCAL_VCLK_NULL(VCLK_IP_SFRAPB_BRIDGE_DMC, NULL, cmucal_vclk_ip_sfrapb_bridge_dmc, NULL, NULL),
2214         CMUCAL_VCLK_NULL(VCLK_IP_SFRAPB_BRIDGE_DMC_PF, NULL, cmucal_vclk_ip_sfrapb_bridge_dmc_pf, NULL, NULL),
2215         CMUCAL_VCLK_NULL(VCLK_IP_SFRAPB_BRIDGE_DMC_PPMPU, NULL, cmucal_vclk_ip_sfrapb_bridge_dmc_ppmpu, NULL, NULL),
2216         CMUCAL_VCLK_NULL(VCLK_IP_SFRAPB_BRIDGE_DMC_SECURE, NULL, cmucal_vclk_ip_sfrapb_bridge_dmc_secure, NULL, NULL),
2217         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_MIF, NULL, cmucal_vclk_ip_sysreg_mif, NULL, NULL),
2218         CMUCAL_VCLK_NULL(VCLK_IP_BUSIF_HPMMIF1, NULL, cmucal_vclk_ip_busif_hpmmif1, NULL, NULL),
2219         CMUCAL_VCLK_NULL(VCLK_IP_DMC1, NULL, cmucal_vclk_ip_dmc1, NULL, NULL),
2220         CMUCAL_VCLK_NULL(VCLK_IP_HPM_MIF1, NULL, cmucal_vclk_ip_hpm_mif1, NULL, NULL),
2221         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_D_MIF1_CP, NULL, cmucal_vclk_ip_lhm_axi_d_mif1_cp, NULL, NULL),
2222         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_D_MIF1_CPU, NULL, cmucal_vclk_ip_lhm_axi_d_mif1_cpu, NULL, NULL),
2223         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_D_MIF1_NRT, NULL, cmucal_vclk_ip_lhm_axi_d_mif1_nrt, NULL, NULL),
2224         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_D_MIF1_RT, NULL, cmucal_vclk_ip_lhm_axi_d_mif1_rt, NULL, NULL),
2225         CMUCAL_VCLK_NULL(VCLK_IP_MIF1_CMU_MIF1, NULL, cmucal_vclk_ip_mif1_cmu_mif1, NULL, NULL),
2226         CMUCAL_VCLK_NULL(VCLK_IP_AXI2AHB_MSD32_PERI, NULL, cmucal_vclk_ip_axi2ahb_msd32_peri, NULL, NULL),
2227         CMUCAL_VCLK_NULL(VCLK_IP_BUSIF_TMU, NULL, cmucal_vclk_ip_busif_tmu, NULL, NULL),
2228         CMUCAL_VCLK_NULL(VCLK_IP_CAMI2C_0, NULL, cmucal_vclk_ip_cami2c_0, NULL, NULL),
2229         CMUCAL_VCLK_NULL(VCLK_IP_CAMI2C_1, NULL, cmucal_vclk_ip_cami2c_1, NULL, NULL),
2230         CMUCAL_VCLK_NULL(VCLK_IP_CAMI2C_2, NULL, cmucal_vclk_ip_cami2c_2, NULL, NULL),
2231         CMUCAL_VCLK_NULL(VCLK_IP_CAMI2C_3, NULL, cmucal_vclk_ip_cami2c_3, NULL, NULL),
2232         CMUCAL_VCLK_NULL(VCLK_IP_GPIO_PERI, NULL, cmucal_vclk_ip_gpio_peri, NULL, NULL),
2233         CMUCAL_VCLK_NULL(VCLK_IP_I2C_0, NULL, cmucal_vclk_ip_i2c_0, NULL, NULL),
2234         CMUCAL_VCLK_NULL(VCLK_IP_I2C_1, NULL, cmucal_vclk_ip_i2c_1, NULL, NULL),
2235         CMUCAL_VCLK_NULL(VCLK_IP_I2C_2, NULL, cmucal_vclk_ip_i2c_2, NULL, NULL),
2236         CMUCAL_VCLK_NULL(VCLK_IP_I2C_3, NULL, cmucal_vclk_ip_i2c_3, NULL, NULL),
2237         CMUCAL_VCLK_NULL(VCLK_IP_I2C_4, NULL, cmucal_vclk_ip_i2c_4, NULL, NULL),
2238         CMUCAL_VCLK_NULL(VCLK_IP_I2C_5, NULL, cmucal_vclk_ip_i2c_5, NULL, NULL),
2239         CMUCAL_VCLK_NULL(VCLK_IP_I2C_6, NULL, cmucal_vclk_ip_i2c_6, NULL, NULL),
2240         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_PERI, NULL, cmucal_vclk_ip_lhm_axi_p_peri, NULL, NULL),
2241         CMUCAL_VCLK_NULL(VCLK_IP_MCT, NULL, cmucal_vclk_ip_mct, NULL, NULL),
2242         CMUCAL_VCLK_NULL(VCLK_IP_OTP_CON_TOP, NULL, cmucal_vclk_ip_otp_con_top, NULL, NULL),
2243         CMUCAL_VCLK_NULL(VCLK_IP_PERI_CMU_PERI, NULL, cmucal_vclk_ip_peri_cmu_peri, NULL, NULL),
2244         CMUCAL_VCLK_NULL(VCLK_IP_PWM_MOTOR, NULL, cmucal_vclk_ip_pwm_motor, NULL, NULL),
2245         CMUCAL_VCLK_NULL(VCLK_IP_SPI_0, NULL, cmucal_vclk_ip_spi_0, NULL, NULL),
2246         CMUCAL_VCLK_NULL(VCLK_IP_SPI_1, NULL, cmucal_vclk_ip_spi_1, NULL, NULL),
2247         CMUCAL_VCLK_NULL(VCLK_IP_SPI_2, NULL, cmucal_vclk_ip_spi_2, NULL, NULL),
2248         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_PERI, NULL, cmucal_vclk_ip_sysreg_peri, NULL, NULL),
2249         CMUCAL_VCLK_NULL(VCLK_IP_UART, NULL, cmucal_vclk_ip_uart, NULL, NULL),
2250         CMUCAL_VCLK_NULL(VCLK_IP_USI00_I2C, NULL, cmucal_vclk_ip_usi00_i2c, NULL, NULL),
2251         CMUCAL_VCLK_NULL(VCLK_IP_USI00_USI, NULL, cmucal_vclk_ip_usi00_usi, NULL, NULL),
2252         CMUCAL_VCLK_NULL(VCLK_IP_WDT_CLUSTER0, NULL, cmucal_vclk_ip_wdt_cluster0, NULL, NULL),
2253         CMUCAL_VCLK_NULL(VCLK_IP_WDT_CLUSTER1, NULL, cmucal_vclk_ip_wdt_cluster1, NULL, NULL),
2254         CMUCAL_VCLK_NULL(VCLK_IP_BAAW_D_SHUB, NULL, cmucal_vclk_ip_baaw_d_shub, NULL, NULL),
2255         CMUCAL_VCLK_NULL(VCLK_IP_BAAW_P_APM_SHUB, NULL, cmucal_vclk_ip_baaw_p_apm_shub, NULL, NULL),
2256         CMUCAL_VCLK_NULL(VCLK_IP_CM4_SHUB, NULL, cmucal_vclk_ip_cm4_shub, NULL, NULL),
2257         CMUCAL_VCLK_NULL(VCLK_IP_GPIO_SHUB, NULL, cmucal_vclk_ip_gpio_shub, NULL, NULL),
2258         CMUCAL_VCLK_NULL(VCLK_IP_I2C_SHUB00, NULL, cmucal_vclk_ip_i2c_shub00, NULL, NULL),
2259         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_LP_SHUB, NULL, cmucal_vclk_ip_lhm_axi_lp_shub, NULL, NULL),
2260         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_SHUB, NULL, cmucal_vclk_ip_lhm_axi_p_shub, NULL, NULL),
2261         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_D_SHUB, NULL, cmucal_vclk_ip_lhs_axi_d_shub, NULL, NULL),
2262         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_APM_SHUB, NULL, cmucal_vclk_ip_lhs_axi_p_apm_shub, NULL, NULL),
2263         CMUCAL_VCLK_NULL(VCLK_IP_PDMA_SHUB, NULL, cmucal_vclk_ip_pdma_shub, NULL, NULL),
2264         CMUCAL_VCLK_NULL(VCLK_IP_PWM_SHUB, NULL, cmucal_vclk_ip_pwm_shub, NULL, NULL),
2265         CMUCAL_VCLK_NULL(VCLK_IP_SHUB_CMU_SHUB, NULL, cmucal_vclk_ip_shub_cmu_shub, NULL, NULL),
2266         CMUCAL_VCLK_NULL(VCLK_IP_SWEEPER_D_SHUB, NULL, cmucal_vclk_ip_sweeper_d_shub, NULL, NULL),
2267         CMUCAL_VCLK_NULL(VCLK_IP_SWEEPER_P_APM_SHUB, NULL, cmucal_vclk_ip_sweeper_p_apm_shub, NULL, NULL),
2268         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_SHUB, NULL, cmucal_vclk_ip_sysreg_shub, NULL, NULL),
2269         CMUCAL_VCLK_NULL(VCLK_IP_TIMER_SHUB, NULL, cmucal_vclk_ip_timer_shub, NULL, NULL),
2270         CMUCAL_VCLK_NULL(VCLK_IP_USI_SHUB00, NULL, cmucal_vclk_ip_usi_shub00, NULL, NULL),
2271         CMUCAL_VCLK_NULL(VCLK_IP_WDT_SHUB, NULL, cmucal_vclk_ip_wdt_shub, NULL, NULL),
2272         CMUCAL_VCLK_NULL(VCLK_IP_XIU_DP_SHUB, NULL, cmucal_vclk_ip_xiu_dp_shub, NULL, NULL),
2273         CMUCAL_VCLK_NULL(VCLK_IP_BTM_USB, NULL, cmucal_vclk_ip_btm_usb, NULL, NULL),
2274         CMUCAL_VCLK_NULL(VCLK_IP_DP_LINK, NULL, cmucal_vclk_ip_dp_link, NULL, NULL),
2275         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_USB, NULL, cmucal_vclk_ip_lhm_axi_p_usb, NULL, NULL),
2276         CMUCAL_VCLK_NULL(VCLK_IP_LHS_ACEL_D_USB, NULL, cmucal_vclk_ip_lhs_acel_d_usb, NULL, NULL),
2277         CMUCAL_VCLK_NULL(VCLK_IP_PGEN_LITE_USB, NULL, cmucal_vclk_ip_pgen_lite_usb, NULL, NULL),
2278         CMUCAL_VCLK_NULL(VCLK_IP_PPMU_USB, NULL, cmucal_vclk_ip_ppmu_usb, NULL, NULL),
2279         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_USB, NULL, cmucal_vclk_ip_sysreg_usb, NULL, NULL),
2280         CMUCAL_VCLK_NULL(VCLK_IP_USB30DRD, NULL, cmucal_vclk_ip_usb30drd, NULL, NULL),
2281         CMUCAL_VCLK_NULL(VCLK_IP_USB_CMU_USB, NULL, cmucal_vclk_ip_usb_cmu_usb, NULL, NULL),
2282         CMUCAL_VCLK_NULL(VCLK_IP_US_D_USB, NULL, cmucal_vclk_ip_us_d_usb, NULL, NULL),
2283         CMUCAL_VCLK_NULL(VCLK_IP_BLK_VIPX1, NULL, cmucal_vclk_ip_blk_vipx1, NULL, NULL),
2284         CMUCAL_VCLK_NULL(VCLK_IP_BTM_D_VIPX1, NULL, cmucal_vclk_ip_btm_d_vipx1, NULL, NULL),
2285         CMUCAL_VCLK_NULL(VCLK_IP_LHM_ATB_VIPX1, NULL, cmucal_vclk_ip_lhm_atb_vipx1, NULL, NULL),
2286         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_VIPX1, NULL, cmucal_vclk_ip_lhm_axi_p_vipx1, NULL, NULL),
2287         CMUCAL_VCLK_NULL(VCLK_IP_LHS_ACEL_D_VIPX1, NULL, cmucal_vclk_ip_lhs_acel_d_vipx1, NULL, NULL),
2288         CMUCAL_VCLK_NULL(VCLK_IP_LHS_ATB_VIPX1, NULL, cmucal_vclk_ip_lhs_atb_vipx1, NULL, NULL),
2289         CMUCAL_VCLK_NULL(VCLK_IP_LHS_AXI_P_VIPX1_LOCAL, NULL, cmucal_vclk_ip_lhs_axi_p_vipx1_local, NULL, NULL),
2290         CMUCAL_VCLK_NULL(VCLK_IP_PGEN_LITE_VIPX1, NULL, cmucal_vclk_ip_pgen_lite_vipx1, NULL, NULL),
2291         CMUCAL_VCLK_NULL(VCLK_IP_PPMU_D_VIPX1, NULL, cmucal_vclk_ip_ppmu_d_vipx1, NULL, NULL),
2292         CMUCAL_VCLK_NULL(VCLK_IP_SMMU_D_VIPX1, NULL, cmucal_vclk_ip_smmu_d_vipx1, NULL, NULL),
2293         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_VIPX1, NULL, cmucal_vclk_ip_sysreg_vipx1, NULL, NULL),
2294         CMUCAL_VCLK_NULL(VCLK_IP_VIPX1, NULL, cmucal_vclk_ip_vipx1, NULL, NULL),
2295         CMUCAL_VCLK_NULL(VCLK_IP_VIPX1_CMU_VIPX1, NULL, cmucal_vclk_ip_vipx1_cmu_vipx1, NULL, NULL),
2296         CMUCAL_VCLK_NULL(VCLK_IP_XIU_D_VIPX1, NULL, cmucal_vclk_ip_xiu_d_vipx1, NULL, NULL),
2297         CMUCAL_VCLK_NULL(VCLK_IP_BLK_VIPX2, NULL, cmucal_vclk_ip_blk_vipx2, NULL, NULL),
2298         CMUCAL_VCLK_NULL(VCLK_IP_BTM_D_VIPX2, NULL, cmucal_vclk_ip_btm_d_vipx2, NULL, NULL),
2299         CMUCAL_VCLK_NULL(VCLK_IP_LHM_ATB_VIPX2, NULL, cmucal_vclk_ip_lhm_atb_vipx2, NULL, NULL),
2300         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_VIPX2, NULL, cmucal_vclk_ip_lhm_axi_p_vipx2, NULL, NULL),
2301         CMUCAL_VCLK_NULL(VCLK_IP_LHM_AXI_P_VIPX2_LOCAL, NULL, cmucal_vclk_ip_lhm_axi_p_vipx2_local, NULL, NULL),
2302         CMUCAL_VCLK_NULL(VCLK_IP_LHS_ACEL_D_VIPX2, NULL, cmucal_vclk_ip_lhs_acel_d_vipx2, NULL, NULL),
2303         CMUCAL_VCLK_NULL(VCLK_IP_LHS_ATB_VIPX2, NULL, cmucal_vclk_ip_lhs_atb_vipx2, NULL, NULL),
2304         CMUCAL_VCLK_NULL(VCLK_IP_PGEN_LITE_VIPX2, NULL, cmucal_vclk_ip_pgen_lite_vipx2, NULL, NULL),
2305         CMUCAL_VCLK_NULL(VCLK_IP_PPMU_D_VIPX2, NULL, cmucal_vclk_ip_ppmu_d_vipx2, NULL, NULL),
2306         CMUCAL_VCLK_NULL(VCLK_IP_SMMU_D_VIPX2, NULL, cmucal_vclk_ip_smmu_d_vipx2, NULL, NULL),
2307         CMUCAL_VCLK_NULL(VCLK_IP_SYSREG_VIPX2, NULL, cmucal_vclk_ip_sysreg_vipx2, NULL, NULL),
2308         CMUCAL_VCLK_NULL(VCLK_IP_VIPX2, NULL, cmucal_vclk_ip_vipx2, NULL, NULL),
2309         CMUCAL_VCLK_NULL(VCLK_IP_VIPX2_CMU_VIPX2, NULL, cmucal_vclk_ip_vipx2_cmu_vipx2, NULL, NULL),
2310 };
2311 unsigned int cmucal_vclk_size = 440;