drivers/scsi/ufs/ufshci.h

   1 /*
   2  * Universal Flash Storage Host controller driver
   3  *
   4  * This code is based on drivers/scsi/ufs/ufshci.h
   5  * Copyright (C) 2011-2013 Samsung India Software Operations
   6  *
   7  * Authors:
   8  *      Santosh Yaraganavi <santosh.sy@samsung.com>
   9  *      Vinayak Holikatti <h.vinayak@samsung.com>
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License
  13  * as published by the Free Software Foundation; either version 2
  14  * of the License, or (at your option) any later version.
  15  * See the COPYING file in the top-level directory or visit
  16  * <http://www.gnu.org/licenses/gpl-2.0.html>
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * This program is provided "AS IS" and "WITH ALL FAULTS" and
  24  * without warranty of any kind. You are solely responsible for
  25  * determining the appropriateness of using and distributing
  26  * the program and assume all risks associated with your exercise
  27  * of rights with respect to the program, including but not limited
  28  * to infringement of third party rights, the risks and costs of
  29  * program errors, damage to or loss of data, programs or equipment,
  30  * and unavailability or interruption of operations. Under no
  31  * circumstances will the contributor of this Program be liable for
  32  * any damages of any kind arising from your use or distribution of
  33  * this program.
  34  */
  35
  36 #ifndef _UFSHCI_H
  37 #define _UFSHCI_H
  38
  39 enum {
  40         TASK_REQ_UPIU_SIZE_DWORDS       = 8,
  41         TASK_RSP_UPIU_SIZE_DWORDS       = 8,
  42         ALIGNED_UPIU_SIZE               = 512,
  43 };
  44
  45 /* UFSHCI Registers */
  46 enum {
  47         REG_CONTROLLER_CAPABILITIES             = 0x00,
  48         REG_UFS_VERSION                         = 0x08,
  49         REG_CONTROLLER_DEV_ID                   = 0x10,
  50         REG_CONTROLLER_PROD_ID                  = 0x14,
  51         REG_AUTO_HIBERNATE_IDLE_TIMER           = 0x18,
  52         REG_INTERRUPT_STATUS                    = 0x20,
  53         REG_INTERRUPT_ENABLE                    = 0x24,
  54         REG_CONTROLLER_STATUS                   = 0x30,
  55         REG_CONTROLLER_ENABLE                   = 0x34,
  56         REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER    = 0x38,
  57         REG_UIC_ERROR_CODE_DATA_LINK_LAYER      = 0x3C,
  58         REG_UIC_ERROR_CODE_NETWORK_LAYER        = 0x40,
  59         REG_UIC_ERROR_CODE_TRANSPORT_LAYER      = 0x44,
  60         REG_UIC_ERROR_CODE_DME                  = 0x48,
  61         REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL    = 0x4C,
  62         REG_UTP_TRANSFER_REQ_LIST_BASE_L        = 0x50,
  63         REG_UTP_TRANSFER_REQ_LIST_BASE_H        = 0x54,
  64         REG_UTP_TRANSFER_REQ_DOOR_BELL          = 0x58,
  65         REG_UTP_TRANSFER_REQ_LIST_CLEAR         = 0x5C,
  66         REG_UTP_TRANSFER_REQ_LIST_RUN_STOP      = 0x60,
  67         REG_UTP_TRANSFER_REQ_LIST_CNR   = 0x64,
  68         REG_UTP_TASK_REQ_LIST_BASE_L            = 0x70,
  69         REG_UTP_TASK_REQ_LIST_BASE_H            = 0x74,
  70         REG_UTP_TASK_REQ_DOOR_BELL              = 0x78,
  71         REG_UTP_TASK_REQ_LIST_CLEAR             = 0x7C,
  72         REG_UTP_TASK_REQ_LIST_RUN_STOP          = 0x80,
  73         REG_UIC_COMMAND                         = 0x90,
  74         REG_UIC_COMMAND_ARG_1                   = 0x94,
  75         REG_UIC_COMMAND_ARG_2                   = 0x98,
  76         REG_UIC_COMMAND_ARG_3                   = 0x9C,
  77
  78         UFSHCI_REG_SPACE_SIZE                   = 0xA0,
  79
  80         REG_CRYPTO_CAPABILITY                   = 0x100,
  81         REG_UFS_CRYPTOCAP                       = 0x104,
  82
  83         UFSHCI_CRYPTO_REG_SPACE_SIZE            = 0x400,
  84 };
  85
  86 /* Controller capability masks */
  87 enum {
  88         MASK_TRANSFER_REQUESTS_SLOTS            = 0x0000001F,
  89         MASK_TASK_MANAGEMENT_REQUEST_SLOTS      = 0x00070000,
  90         MASK_64_ADDRESSING_SUPPORT              = 0x01000000,
  91         MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
  92         MASK_UIC_DME_TEST_MODE_SUPPORT          = 0x04000000,
  93 };
  94
  95 #define UFS_MASK(mask, offset)          ((mask) << (offset))
  96
  97 /* UFS Version 08h */
  98 #define MINOR_VERSION_NUM_MASK          UFS_MASK(0xFFFF, 0)
  99 #define MAJOR_VERSION_NUM_MASK          UFS_MASK(0xFFFF, 16)
 100
 101 /* Controller UFSHCI version */
 102 enum {
 103         UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
 104         UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
 105         UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
 106         UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
 107 };
 108
 109 /*
 110  * HCDDID - Host Controller Identification Descriptor
 111  *        - Device ID and Device Class 10h
 112  */
 113 #define DEVICE_CLASS    UFS_MASK(0xFFFF, 0)
 114 #define DEVICE_ID       UFS_MASK(0xFF, 24)
 115
 116 /*
 117  * HCPMID - Host Controller Identification Descriptor
 118  *        - Product/Manufacturer ID  14h
 119  */
 120 #define MANUFACTURE_ID_MASK     UFS_MASK(0xFFFF, 0)
 121 #define PRODUCT_ID_MASK         UFS_MASK(0xFFFF, 16)
 122
 123 #define UFS_BIT(x)      (1L << (x))
 124
 125 #define UTP_TRANSFER_REQ_COMPL                  UFS_BIT(0)
 126 #define UIC_DME_END_PT_RESET                    UFS_BIT(1)
 127 #define UIC_ERROR                               UFS_BIT(2)
 128 #define UIC_TEST_MODE                           UFS_BIT(3)
 129 #define UIC_POWER_MODE                          UFS_BIT(4)
 130 #define UIC_HIBERNATE_EXIT                      UFS_BIT(5)
 131 #define UIC_HIBERNATE_ENTER                     UFS_BIT(6)
 132 #define UIC_LINK_LOST                           UFS_BIT(7)
 133 #define UIC_LINK_STARTUP                        UFS_BIT(8)
 134 #define UTP_TASK_REQ_COMPL                      UFS_BIT(9)
 135 #define UIC_COMMAND_COMPL                       UFS_BIT(10)
 136 #define DEVICE_FATAL_ERROR                      UFS_BIT(11)
 137 #define CONTROLLER_FATAL_ERROR                  UFS_BIT(16)
 138 #define SYSTEM_BUS_FATAL_ERROR                  UFS_BIT(17)
 139
 140 #define UFSHCD_UIC_PWR_MASK     (UIC_HIBERNATE_ENTER |\
 141                                 UIC_HIBERNATE_EXIT |\
 142                                 UIC_POWER_MODE)
 143
 144 #define UFSHCD_UIC_MASK         (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
 145
 146 #define UFSHCD_ERROR_MASK       (UIC_ERROR |\
 147                                 DEVICE_FATAL_ERROR |\
 148                                 CONTROLLER_FATAL_ERROR |\
 149                                 SYSTEM_BUS_FATAL_ERROR |\
 150                                 UIC_LINK_LOST)
 151
 152 #define INT_FATAL_ERRORS        (DEVICE_FATAL_ERROR |\
 153                                 CONTROLLER_FATAL_ERROR |\
 154                                 SYSTEM_BUS_FATAL_ERROR |\
 155                                 UIC_LINK_LOST)
 156
 157 /* HCS - Host Controller Status 30h */
 158 #define DEVICE_PRESENT                          UFS_BIT(0)
 159 #define UTP_TRANSFER_REQ_LIST_READY             UFS_BIT(1)
 160 #define UTP_TASK_REQ_LIST_READY                 UFS_BIT(2)
 161 #define UIC_COMMAND_READY                       UFS_BIT(3)
 162 #define HOST_ERROR_INDICATOR                    UFS_BIT(4)
 163 #define DEVICE_ERROR_INDICATOR                  UFS_BIT(5)
 164 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK   UFS_MASK(0x7, 8)
 165
 166 #define UFSHCD_STATUS_READY     (UTP_TRANSFER_REQ_LIST_READY |\
 167                                 UTP_TASK_REQ_LIST_READY |\
 168                                 UIC_COMMAND_READY)
 169
 170 enum {
 171         PWR_OK          = 0x0,
 172         PWR_LOCAL       = 0x01,
 173         PWR_REMOTE      = 0x02,
 174         PWR_BUSY        = 0x03,
 175         PWR_ERROR_CAP   = 0x04,
 176         PWR_FATAL_ERROR = 0x05,
 177 };
 178
 179 /* HCE - Host Controller Enable 34h */
 180 #define CONTROLLER_ENABLE       UFS_BIT(0)
 181 #define CONTROLLER_DISABLE      0x0
 182 #define CRYPTO_GENERAL_ENABLE   UFS_BIT(1)
 183
 184 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
 185 #define UIC_PHY_ADAPTER_LAYER_ERROR                     UFS_BIT(31)
 186 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK           0x1F
 187 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK             0xF
 188
 189 /* UECDL - Host UIC Error Code Data Link Layer 3Ch */
 190 #define UIC_DATA_LINK_LAYER_ERROR               UFS_BIT(31)
 191 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK     0x7FFF
 192 #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP     UFS_BIT(1)
 193 #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP    UFS_BIT(2)
 194 #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP     UFS_BIT(3)
 195 #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF     UFS_BIT(5)
 196 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT       UFS_BIT(13)
 197 #define UIC_DATA_LINK_LAYER_ERROR_PA_ERROR_IND_RECEIVED         UFS_BIT(14)
 198 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED  0x0001
 199 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
 200
 201 /* UECN - Host UIC Error Code Network Layer 40h */
 202 #define UIC_NETWORK_LAYER_ERROR                 UFS_BIT(31)
 203 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK       0x7
 204 #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE     BIT(0)
 205 #define UIC_NETWORK_BAD_DEVICEID_ENC            BIT(1)
 206 #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING   BIT(2)
 207
 208 /* UECT - Host UIC Error Code Transport Layer 44h */
 209 #define UIC_TRANSPORT_LAYER_ERROR               UFS_BIT(31)
 210 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK     0x7F
 211 #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE   BIT(0)
 212 #define UIC_TRANSPORT_UNKNOWN_CPORTID           BIT(1)
 213 #define UIC_TRANSPORT_NO_CONNECTION_RX          BIT(2)
 214 #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING       BIT(3)
 215 #define UIC_TRANSPORT_BAD_TC                    BIT(4)
 216 #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW        BIT(5)
 217 #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING     BIT(6)
 218
 219 /* UECDME - Host UIC Error Code DME 48h */
 220 #define UIC_DME_ERROR                   UFS_BIT(31)
 221 #define UIC_DME_ERROR_CODE_MASK         0x1
 222
 223 #define INT_AGGR_TIMEOUT_VAL_MASK               0xFF
 224 #define INT_AGGR_COUNTER_THRESHOLD_MASK         UFS_MASK(0x1F, 8)
 225 #define INT_AGGR_COUNTER_AND_TIMER_RESET        UFS_BIT(16)
 226 #define INT_AGGR_STATUS_BIT                     UFS_BIT(20)
 227 #define INT_AGGR_PARAM_WRITE                    UFS_BIT(24)
 228 #define INT_AGGR_ENABLE                         UFS_BIT(31)
 229
 230 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
 231 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT      UFS_BIT(0)
 232
 233 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
 234 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT          UFS_BIT(0)
 235
 236 /* UICCMD - UIC Command */
 237 #define COMMAND_OPCODE_MASK             0xFF
 238 #define GEN_SELECTOR_INDEX_MASK         0xFFFF
 239
 240 #define MIB_ATTRIBUTE_MASK              UFS_MASK(0xFFFF, 16)
 241 #define RESET_LEVEL                     0xFF
 242
 243 #define ATTR_SET_TYPE_MASK              UFS_MASK(0xFF, 16)
 244 #define CONFIG_RESULT_CODE_MASK         0xFF
 245 #define GENERIC_ERROR_CODE_MASK         0xFF
 246
 247 /* GenSelectorIndex calculation macros for M-PHY attributes */
 248 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
 249 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
 250
 251 #define UIC_ARG_MIB_SEL(attr, sel)      ((((attr) & 0xFFFF) << 16) |\
 252                                          ((sel) & 0xFFFF))
 253 #define UIC_ARG_MIB(attr)               UIC_ARG_MIB_SEL(attr, 0)
 254 #define UIC_ARG_ATTR_TYPE(t)            (((t) & 0xFF) << 16)
 255 #define UIC_GET_ATTR_ID(v)              (((v) >> 16) & 0xFFFF)
 256
 257 /* Link Status*/
 258 enum link_status {
 259         UFSHCD_LINK_IS_DOWN     = 1,
 260         UFSHCD_LINK_IS_UP       = 2,
 261 };
 262 #define UFSHCI_SECTOR_SIZE                      0x1000
 263 #define MIN_SECTOR_SIZE                         0x200
 264
 265 /* UIC Commands */
 266 enum uic_cmd_dme {
 267         UIC_CMD_DME_GET                 = 0x01,
 268         UIC_CMD_DME_SET                 = 0x02,
 269         UIC_CMD_DME_PEER_GET            = 0x03,
 270         UIC_CMD_DME_PEER_SET            = 0x04,
 271         UIC_CMD_DME_POWERON             = 0x10,
 272         UIC_CMD_DME_POWEROFF            = 0x11,
 273         UIC_CMD_DME_ENABLE              = 0x12,
 274         UIC_CMD_DME_RESET               = 0x14,
 275         UIC_CMD_DME_END_PT_RST          = 0x15,
 276         UIC_CMD_DME_LINK_STARTUP        = 0x16,
 277         UIC_CMD_DME_HIBER_ENTER         = 0x17,
 278         UIC_CMD_DME_HIBER_EXIT          = 0x18,
 279         UIC_CMD_DME_TEST_MODE           = 0x1A,
 280 };
 281
 282 /* UIC Config result code / Generic error code */
 283 enum {
 284         UIC_CMD_RESULT_SUCCESS                  = 0x00,
 285         UIC_CMD_RESULT_INVALID_ATTR             = 0x01,
 286         UIC_CMD_RESULT_FAILURE                  = 0x01,
 287         UIC_CMD_RESULT_INVALID_ATTR_VALUE       = 0x02,
 288         UIC_CMD_RESULT_READ_ONLY_ATTR           = 0x03,
 289         UIC_CMD_RESULT_WRITE_ONLY_ATTR          = 0x04,
 290         UIC_CMD_RESULT_BAD_INDEX                = 0x05,
 291         UIC_CMD_RESULT_LOCKED_ATTR              = 0x06,
 292         UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX   = 0x07,
 293         UIC_CMD_RESULT_PEER_COMM_FAILURE        = 0x08,
 294         UIC_CMD_RESULT_BUSY                     = 0x09,
 295         UIC_CMD_RESULT_DME_FAILURE              = 0x0A,
 296 };
 297
 298 #define MASK_UIC_COMMAND_RESULT                 0xFF
 299
 300 #define INT_AGGR_COUNTER_THLD_VAL(c)    (((c) & 0x1F) << 8)
 301 #define INT_AGGR_TIMEOUT_VAL(t)         (((t) & 0xFF) << 0)
 302
 303 /* Interrupt disable masks */
 304 enum {
 305         /* Interrupt disable mask for UFSHCI v1.0 */
 306         INTERRUPT_MASK_ALL_VER_10       = 0x30FFF,
 307         INTERRUPT_MASK_RW_VER_10        = 0x30000,
 308
 309         /* Interrupt disable mask for UFSHCI v1.1 */
 310         INTERRUPT_MASK_ALL_VER_11       = 0x31FFF,
 311
 312         /* Interrupt disable mask for UFSHCI v2.1 */
 313         INTERRUPT_MASK_ALL_VER_21       = 0x71FFF,
 314 };
 315
 316 /*
 317  * Request Descriptor Definitions
 318  */
 319
 320 /* Transfer request command type */
 321 enum {
 322         UTP_CMD_TYPE_SCSI               = 0x0,
 323         UTP_CMD_TYPE_UFS                = 0x1,
 324         UTP_CMD_TYPE_DEV_MANAGE         = 0x2,
 325 };
 326
 327 /* To accommodate UFS2.0 required Command type */
 328 enum {
 329         UTP_CMD_TYPE_UFS_STORAGE        = 0x1,
 330 };
 331
 332 enum {
 333         UTP_SCSI_COMMAND                = 0x00000000,
 334         UTP_NATIVE_UFS_COMMAND          = 0x10000000,
 335         UTP_DEVICE_MANAGEMENT_FUNCTION  = 0x20000000,
 336         UTP_REQ_DESC_INT_CMD            = 0x01000000,
 337 };
 338
 339 /* UTP Transfer Request Data Direction (DD) */
 340 enum {
 341         UTP_NO_DATA_TRANSFER    = 0x00000000,
 342         UTP_HOST_TO_DEVICE      = 0x02000000,
 343         UTP_DEVICE_TO_HOST      = 0x04000000,
 344 };
 345
 346 /* Overall command status values */
 347 enum {
 348         OCS_SUCCESS                     = 0x0,
 349         OCS_INVALID_CMD_TABLE_ATTR      = 0x1,
 350         OCS_INVALID_PRDT_ATTR           = 0x2,
 351         OCS_MISMATCH_DATA_BUF_SIZE      = 0x3,
 352         OCS_MISMATCH_RESP_UPIU_SIZE     = 0x4,
 353         OCS_PEER_COMM_FAILURE           = 0x5,
 354         OCS_ABORTED                     = 0x6,
 355         OCS_FATAL_ERROR                 = 0x7,
 356         OCS_INVALID_COMMAND_STATUS      = 0x0F,
 357         MASK_OCS                        = 0x0F,
 358 };
 359
 360 /* The maximum length of the data byte count field in the PRDT is 256KB */
 361 #define PRDT_DATA_BYTE_COUNT_MAX        (256 * 1024)
 362 /* The granularity of the data byte count field in the PRDT is 32-bit */
 363 #define PRDT_DATA_BYTE_COUNT_PAD        4
 364
 365 /**
 366  * struct ufshcd_sg_entry - UFSHCI PRD Entry
 367  * @base_addr: Lower 32bit physical address DW-0
 368  * @upper_addr: Upper 32bit physical address DW-1
 369  * @reserved: Reserved for future use DW-2
 370  * @size: size of physical segment DW-3
 371  */
 372 struct ufshcd_sg_entry {
 373         __le32 base_addr;       /* des0 */
 374         __le32 upper_addr;      /* des1 */
 375         __le32 reserved;        /* des2 */
 376         __le32 size;            /* des3 */
 377 #ifdef CONFIG_SCSI_UFS_EXYNOS_FMP
 378         __le32 file_iv0;        /* des4 */
 379         __le32 file_iv1;        /* des5 */
 380         __le32 file_iv2;        /* des6 */
 381         __le32 file_iv3;        /* des7 */
 382         __le32 file_enckey0;    /* des8 */
 383         __le32 file_enckey1;    /* des9 */
 384         __le32 file_enckey2;    /* des10 */
 385         __le32 file_enckey3;    /* des11 */
 386         __le32 file_enckey4;    /* des12 */
 387         __le32 file_enckey5;    /* des13 */
 388         __le32 file_enckey6;    /* des14 */
 389         __le32 file_enckey7;    /* des15 */
 390         __le32 file_twkey0;     /* des16 */
 391         __le32 file_twkey1;     /* des17 */
 392         __le32 file_twkey2;     /* des18 */
 393         __le32 file_twkey3;     /* des19 */
 394         __le32 file_twkey4;     /* des20 */
 395         __le32 file_twkey5;     /* des21 */
 396         __le32 file_twkey6;     /* des22 */
 397         __le32 file_twkey7;     /* des23 */
 398         __le32 disk_iv0;        /* des24 */
 399         __le32 disk_iv1;        /* des25 */
 400         __le32 disk_iv2;        /* des26 */
 401         __le32 disk_iv3;        /* des27 */
 402         __le32 reserved0;       /* des28 */
 403         __le32 reserved1;       /* des29 */
 404         __le32 reserved2;       /* des30 */
 405         __le32 reserved3;       /* des31 */
 406 #endif /* CONFIG_SCSI_UFS_EXYNOS_FMP */
 407 };
 408
 409 /**
 410  * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
 411  * @command_upiu: Command UPIU Frame address
 412  * @response_upiu: Response UPIU Frame address
 413  * @prd_table: Physical Region Descriptor
 414  */
 415 struct utp_transfer_cmd_desc {
 416         u8 command_upiu[ALIGNED_UPIU_SIZE];
 417         u8 response_upiu[ALIGNED_UPIU_SIZE];
 418         struct ufshcd_sg_entry    prd_table[SG_ALL];
 419 };
 420
 421 /**
 422  * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
 423  * @dword0: Descriptor Header DW0
 424  * @dword1: Descriptor Header DW1
 425  * @dword2: Descriptor Header DW2
 426  * @dword3: Descriptor Header DW3
 427  */
 428 struct request_desc_header {
 429         __le32 dword_0;
 430         __le32 dword_1;
 431         __le32 dword_2;
 432         __le32 dword_3;
 433 };
 434
 435 /**
 436  * struct utp_transfer_req_desc - UTRD structure
 437  * @header: UTRD header DW-0 to DW-3
 438  * @command_desc_base_addr_lo: UCD base address low DW-4
 439  * @command_desc_base_addr_hi: UCD base address high DW-5
 440  * @response_upiu_length: response UPIU length DW-6
 441  * @response_upiu_offset: response UPIU offset DW-6
 442  * @prd_table_length: Physical region descriptor length DW-7
 443  * @prd_table_offset: Physical region descriptor offset DW-7
 444  */
 445 struct utp_transfer_req_desc {
 446
 447         /* DW 0-3 */
 448         struct request_desc_header header;
 449
 450         /* DW 4-5*/
 451         __le32  command_desc_base_addr_lo;
 452         __le32  command_desc_base_addr_hi;
 453
 454         /* DW 6 */
 455         __le16  response_upiu_length;
 456         __le16  response_upiu_offset;
 457
 458         /* DW 7 */
 459         __le16  prd_table_length;
 460         __le16  prd_table_offset;
 461 };
 462
 463 /**
 464  * struct utp_task_req_desc - UTMRD structure
 465  * @header: UTMRD header DW-0 to DW-3
 466  * @task_req_upiu: Pointer to task request UPIU DW-4 to DW-11
 467  * @task_rsp_upiu: Pointer to task response UPIU DW12 to DW-19
 468  */
 469 struct utp_task_req_desc {
 470
 471         /* DW 0-3 */
 472         struct request_desc_header header;
 473
 474         /* DW 4-11 */
 475         __le32 task_req_upiu[TASK_REQ_UPIU_SIZE_DWORDS];
 476
 477         /* DW 12-19 */
 478         __le32 task_rsp_upiu[TASK_RSP_UPIU_SIZE_DWORDS];
 479 };
 480
 481 #endif /* End of Header */