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[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / arch / arm64 / boot / dts / exynos / exynos9609-wing.dts
1 /*
2 * SAMSUNG EXYNOS9610 board device tree source
3 *
4 * Copyright (c) 2017 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 /dts-v1/;
13 /plugin/;
14
15 #include "exynos9610_battery_data.dtsi"
16 #include <dt-bindings/clock/exynos9610.h>
17 #include "modem-ss360ap-sit-pdata.dtsi"
18 #include "exynos9610-display-lcd.dtsi"
19 #include "novatek-nt36xxx-i2c.dtsi"
20 #include "wing-sensor.dtsi"
21
22 / {
23 compatible = "samsung,exynos9610", "samsung,WING";
24 board_id = <0x0>;
25 board_rev = <0x0>;
26
27 fragment@model {
28 target-path = "/";
29 __overlay__ {
30 #address-cells = <2>;
31 #size-cells = <1>;
32 model = "Samsung Wing board based on EXYNOS9610";
33
34 ect {
35 parameter_address = <0x90000000>;
36 parameter_size = <0x19000>;
37 };
38
39 chosen {
40 bootargs = "console=ram skip_initramfs rootwait ro init=/init clk_ignore_unused bcm_setup=0xffffff80f8e00000 androidboot.hardware=exynos9610 androidboot.selinux=permissive androidboot.debug_level=0x4948 firmware_class.path=/vendor/firmware ecd_setup=disable reserve-fimc=0xffffff80fa000000 pmic_info=0x3 ccic_info=0x1 epx_activate=true ";
41 linux,initrd-start = <0x84000000>;
42 linux,initrd-end = <0x841FFFFF>;
43 };
44
45 fixed-rate-clocks {
46 oscclk {
47 compatible = "samsung,exynos9610-oscclk";
48 clock-frequency = <26000000>;
49 };
50 };
51
52 firmware {
53 android {
54 compatible = "android,firmware";
55 vbmeta {
56 compatible = "android,vbmeta";
57 parts = "vbmeta,boot,system,vendor";
58 };
59 fstab {
60 compatible = "android,fstab";
61 vendor {
62 compatible = "android,vendor";
63 dev = "/dev/block/platform/13520000.ufs/by-name/vendor";
64 type = "ext4";
65 mnt_flags = "ro";
66 fsmgr_flags = "wait,avb,slotselect";
67 };
68 };
69 };
70 };
71
72 ifconn {
73 status = "okay";
74 compatible = "samsung,ifconn";
75 ifconn,usbpd = "s2mm005";
76 ifconn,muic = "s2mu106-muic";
77 };
78
79 /*Fingerprint start*/
80 et320: et320{
81 compatible = "egistec,et320";
82 status = "ok";
83 reg = <0>;
84 clocks = <&clock GATE_SPI_1_QCH>, <&clock SPI1>;
85 clock-names = "spi", "spi_busclk0";
86 pinctrl-names = "default";
87 pinctrl-0 = <&spi7_bus &spi7_cs_func>;
88 egistec,gpio_irq = <&gpa0 5 0>;
89 egistec,gpio_rst = <&gpa1 1 0>;
90 };
91 /*Fingerprint end*/
92
93 speedy@11a10000 {
94 status = "okay";
95 #address-cells = <1>;
96 #size-cells = <0>;
97 s2mpu09mfd@00 {
98 compatible = "samsung,s2mpu09mfd";
99 acpm-ipc-channel = <2>;
100 i2c-speedy-address;
101 s2mpu09,wakeup = "enabled";
102 s2mpu09,irq-gpio = <&gpa2 0 0>;
103 reg = <0x00>;
104 interrupts = <2 0 0>;
105 interrupt-parent = <&gpa2>;
106 pinctrl-names = "default";
107 pinctrl-0 = <&pmic_irq &pm_wrsti>;
108 /* RTC: wtsr/smpl */
109 wtsr_en = "enabled"; /* enable */
110 smpl_en = "enabled"; /* enable */
111 wtsr_timer_val = <3>; /* 1000ms */
112 smpl_timer_val = <4>; /* 500ms */
113 check_jigon = <0>; /* do not check jigon */
114 /* RTC: If it's first boot, reset rtc to 1/1/2017 12:00:00(Sun) */
115 init_time,sec = <0>;
116 init_time,min = <0>;
117 init_time,hour = <12>;
118 init_time,mday = <1>;
119 init_time,mon = <0>;
120 init_time,year = <117>;
121 init_time,wday = <0>;
122
123 regulators {
124 b1_reg: BUCK1 {
125 regulator-name = "vdd_mif";
126 regulator-min-microvolt = <500000>;
127 regulator-max-microvolt = <1100000>;
128 regulator-always-on;
129 regulator-ramp-delay = <12000>;
130 regulator-initial-mode = <2>;
131 };
132
133 b2_reg: BUCK2 {
134 regulator-name = "vdd_cpucl1";
135 regulator-min-microvolt = <500000>;
136 regulator-max-microvolt = <1300000>;
137 regulator-always-on;
138 regulator-ramp-delay = <12000>;
139 regulator-initial-mode = <1>;
140 };
141
142 b3_reg: BUCK3 {
143 regulator-name = "vdd_cpucl0";
144 regulator-min-microvolt = <500000>;
145 regulator-max-microvolt = <1300000>;
146 regulator-always-on;
147 regulator-ramp-delay = <12000>;
148 regulator-initial-mode = <1>;
149 };
150
151 b4_reg: BUCK4{
152 regulator-name = "vdd_int";
153 regulator-min-microvolt = <500000>;
154 regulator-max-microvolt = <1100000>;
155 regulator-always-on;
156 regulator-ramp-delay = <12000>;
157 regulator-initial-mode = <2>;
158 };
159
160 b5_reg: BUCK5 {
161 regulator-name = "vdd_g3d";
162 regulator-min-microvolt = <500000>;
163 regulator-max-microvolt = <1200000>;
164 regulator-always-on;
165 regulator-ramp-delay = <12000>;
166 regulator-initial-mode = <2>;
167 };
168
169 b6_reg: BUCK6 {
170 regulator-name = "vdd_cam_vipx";
171 regulator-min-microvolt = <500000>;
172 regulator-max-microvolt = <1300000>;
173 regulator-always-on;
174 regulator-ramp-delay = <12000>;
175 regulator-initial-mode = <2>;
176 };
177
178 b7_reg: BUCK7 {
179 regulator-name = "vdd2_mem";
180 regulator-min-microvolt = <500000>;
181 regulator-max-microvolt = <1300000>;
182 regulator-always-on;
183 regulator-ramp-delay = <12000>;
184 regulator-initial-mode = <3>;
185 };
186
187 b8_reg: BUCK8 {
188 regulator-name = "vdd_lldo";
189 regulator-min-microvolt = <1200000>;
190 regulator-max-microvolt = <1500000>;
191 regulator-always-on;
192 regulator-ramp-delay = <12000>;
193 regulator-initial-mode = <3>;
194 };
195
196 b9_reg: BUCK9 {
197 regulator-name = "vdd_mldo";
198 regulator-min-microvolt = <1800000>;
199 regulator-max-microvolt = <2100000>;
200 regulator-always-on;
201 regulator-ramp-delay = <12000>;
202 regulator-initial-mode = <3>;
203 };
204
205 l1_reg: LDO1 {
206 regulator-name = "vdd_ldo1";
207 regulator-min-microvolt = <700000>;
208 regulator-max-microvolt = <1300000>;
209 regulator-always-on;
210 regulator-ramp-delay = <12000>;
211 regulator-initial-mode = <3>;
212 };
213
214 l2_reg: LDO2 {
215 regulator-name = "vqmmc";
216 regulator-min-microvolt = <1800000>;
217 regulator-max-microvolt = <3375000>;
218 regulator-ramp-delay = <12000>;
219 };
220
221 l3_reg: LDO3 {
222 regulator-name = "vdd_ldo3";
223 regulator-min-microvolt = <800000>;
224 regulator-max-microvolt = <1950000>;
225 regulator-always-on;
226 regulator-ramp-delay = <12000>;
227 regulator-initial-mode = <3>;
228 };
229
230 l4_reg: LDO4 {
231 regulator-name = "vdd_ldo4";
232 regulator-min-microvolt = <500000>;
233 regulator-max-microvolt = <1100000>;
234 regulator-always-on;
235 regulator-ramp-delay = <12000>;
236 regulator-initial-mode = <1>;
237 };
238
239 l5_reg: LDO5 {
240 regulator-name = "vdd_ldo5";
241 regulator-min-microvolt = <800000>;
242 regulator-max-microvolt = <1300000>;
243 regulator-always-on;
244 regulator-ramp-delay = <12000>;
245 regulator-initial-mode = <1>;
246 };
247
248 l6_reg: LDO6 {
249 regulator-name = "vdd_ldo6";
250 regulator-min-microvolt = <800000>;
251 regulator-max-microvolt = <1300000>;
252 regulator-always-on;
253 regulator-ramp-delay = <12000>;
254 regulator-initial-mode = <1>;
255 };
256
257 l7_reg: LDO7 {
258 regulator-name = "vdd_ldo7";
259 regulator-min-microvolt = <800000>;
260 regulator-max-microvolt = <1950000>;
261 regulator-always-on;
262 regulator-ramp-delay = <12000>;
263 regulator-initial-mode = <1>;
264 };
265
266 l8_reg: LDO8 {
267 regulator-name = "vdd_ldo8";
268 regulator-min-microvolt = <500000>;
269 regulator-max-microvolt = <1300000>;
270 regulator-always-on;
271 regulator-ramp-delay = <12000>;
272 regulator-initial-mode = <1>;
273 };
274
275 l9_reg: LDO9 {
276 regulator-name = "vdd_ldo9";
277 regulator-min-microvolt = <500000>;
278 regulator-max-microvolt = <1300000>;
279 regulator-always-on;
280 regulator-ramp-delay = <12000>;
281 regulator-initial-mode = <1>;
282 };
283
284 l10_reg: LDO10 {
285 regulator-name = "vdd_ldo10";
286 regulator-min-microvolt = <500000>;
287 regulator-max-microvolt = <1300000>;
288 regulator-always-on;
289 regulator-ramp-delay = <12000>;
290 regulator-initial-mode = <1>;
291 };
292
293 l11_reg: LDO11 {
294 regulator-name = "vdd_ldo11";
295 regulator-min-microvolt = <500000>;
296 regulator-max-microvolt = <1300000>;
297 regulator-always-on;
298 regulator-ramp-delay = <12000>;
299 regulator-initial-mode = <1>;
300 };
301
302 l12_reg: LDO12 {
303 regulator-name = "vdd_ldo12";
304 regulator-min-microvolt = <800000>;
305 regulator-max-microvolt = <1300000>;
306 regulator-always-on;
307 regulator-ramp-delay = <12000>;
308 regulator-initial-mode = <1>;
309 };
310
311 l13_reg: LDO13 {
312 regulator-name = "vdd_ldo13";
313 regulator-min-microvolt = <800000>;
314 regulator-max-microvolt = <1950000>;
315 regulator-always-on;
316 regulator-ramp-delay = <12000>;
317 regulator-initial-mode = <1>;
318 };
319
320 l14_reg: LDO14 {
321 regulator-name = "vdd_ldo14";
322 regulator-min-microvolt = <1800000>;
323 regulator-max-microvolt = <3375000>;
324 regulator-always-on;
325 regulator-ramp-delay = <12000>;
326 regulator-initial-mode = <1>;
327 };
328
329 l33_reg: LDO33 {
330 regulator-name = "vdd_ldo33";
331 regulator-min-microvolt = <800000>;
332 regulator-max-microvolt = <1950000>;
333 regulator-ramp-delay = <12000>;
334 };
335
336 l34_reg: LDO34 {
337 regulator-name = "vdd_ldo34";
338 regulator-min-microvolt = <1800000>;
339 regulator-max-microvolt = <3375000>;
340 regulator-ramp-delay = <12000>;
341 };
342
343 l35_reg: LDO35 {
344 regulator-name = "vmmc";
345 regulator-min-microvolt = <1800000>;
346 regulator-max-microvolt = <3375000>;
347 regulator-ramp-delay = <12000>;
348 };
349
350 l36_reg: LDO36 {
351 regulator-name = "vdd_ldo36";
352 regulator-min-microvolt = <500000>;
353 regulator-max-microvolt = <1300000>;
354 regulator-always-on;
355 regulator-ramp-delay = <12000>;
356 regulator-initial-mode = <1>;
357 };
358
359 l37_reg: LDO37 {
360 regulator-name = "vdd_ldo37";
361 regulator-min-microvolt = <3300000>;
362 regulator-max-microvolt = <3300000>;
363 regulator-ramp-delay = <12000>;
364 regulator-always-on;
365 };
366
367 l38_reg: LDO38 {
368 regulator-name = "vdd_ldo38";
369 regulator-min-microvolt = <1800000>;
370 regulator-max-microvolt = <3375000>;
371 regulator-ramp-delay = <12000>;
372 regulator-always-on;
373 };
374
375 l39_reg: LDO39 {
376 regulator-name = "vdd_ldo39";
377 regulator-min-microvolt = <800000>;
378 regulator-max-microvolt = <1950000>;
379 regulator-ramp-delay = <12000>;
380 regulator-always-on;
381 };
382
383 l40_reg: LDO40 {
384 regulator-name = "vdd_ldo40";
385 regulator-min-microvolt = <1800000>;
386 regulator-max-microvolt = <3375000>;
387 regulator-ramp-delay = <12000>;
388 regulator-initial-mode = <3>;
389 regulator-always-on;
390 };
391
392 l41_reg: LDO41 {
393 regulator-name = "vdd_ldo41";
394 regulator-min-microvolt = <1800000>;
395 regulator-max-microvolt = <3375000>;
396 regulator-ramp-delay = <12000>;
397 };
398
399 l42_reg: LDO42 {
400 regulator-name = "vdd_ldo42";
401 regulator-min-microvolt = <800000>;
402 regulator-max-microvolt = <1950000>;
403 regulator-ramp-delay = <12000>;
404 regulator-always-on;
405 };
406
407 l43_reg: LDO43 {
408 regulator-name = "vdd_ldo43";
409 regulator-min-microvolt = <500000>;
410 regulator-max-microvolt = <1300000>;
411 regulator-always-on;
412 regulator-ramp-delay = <12000>;
413 regulator-initial-mode = <1>;
414 };
415
416 l44_reg: LDO44 {
417 regulator-name = "vdd_ldo44";
418 regulator-min-microvolt = <800000>;
419 regulator-max-microvolt = <1300000>;
420 regulator-ramp-delay = <12000>;
421 regulator-always-on;
422 };
423 };
424 };
425 };
426
427
428 exynos_rgt {
429 compatible = "samsung,exynos-rgt";
430 };
431
432 mailbox_cp: mcu_ipc@11920000 {
433 compatible = "samsung,exynos-shd-ipc-mailbox";
434 reg = <0x0 0x11920000 0x180>;
435 mcu,name = "mcu_ipc_cp";
436 mcu,id = <0>;
437 interrupts = <0 40 0 >;
438 };
439
440 mailbox_gnss: mcu_ipc@11A00000 {
441 compatible = "samsung,exynos-shd-ipc-mailbox";
442 reg = <0x0 0x11A00000 0x180>;
443 mcu,name = "mcu_ipc_gnss";
444 mcu,id = <1>;
445 interrupts = <0 43 0>; /* INTREQ__MAILBOX_GNSS2AP */
446 };
447
448 gnss_pdata {
449 status = "okay";
450
451 compatible = "samsung,gnss_shdmem_if";
452 shmem,name = "KEPLER";
453 shmem,device_node_name = "gnss_ipc";
454
455 /* INTREQ__ALIVE_GNSS_ACTIVE, INTREQ__GNSS2AP_WDOG_RESET, INTREQ__GNSS2AP_WAKEUP, INTREQ__GNSS2AP */
456 interrupts = <0 27 0>, <0 81 0>, <0 80 0>, <0 79 0>;
457 interrupt-names = "ACTIVE", "WATCHDOG", "WAKEUP", "REQ_INIT";
458
459 memory-region = <&gnss_reserved>;
460 mbox_info = <&mailbox_gnss>;
461
462 mbx,int_ap2gnss_bcmd = <0>;
463 mbx,int_ap2gnss_req_fault_info = <1>;
464 mbx,int_ap2gnss_ipc_msg = <2>;
465 mbx,int_ap2gnss_ack_wake_set = <3>;
466 mbx,int_ap2gnss_ack_wake_clr = <4>;
467
468 mbx,irq_gnss2ap_bcmd = <0>;
469 mbx,irq_gnss2ap_rsp_fault_info = <1>;
470 mbx,irq_gnss2ap_ipc_msg = <2>;
471 mbx,irq_gnss2ap_req_wake_clr = <4>;
472
473 mbx,reg_bcmd_ctrl = <0>, <1>, <2>, <3>;
474
475 reg_rx_ipc_msg = <1 5>;
476 reg_tx_ipc_msg = <1 4>;
477 reg_rx_head = <1 3>;
478 reg_rx_tail = <1 2>;
479 reg_tx_head = <1 1>;
480 reg_tx_tail = <1 0>;
481 fault_info = <1 0x200000 0x180000>;
482
483 shmem,ipc_offset = <0x380000>;
484 shmem,ipc_size = <0x80000>;
485 shmem,ipc_reg_cnt = <32>;
486 };
487
488 gpio_keys {
489 status = "okay";
490 compatible = "gpio-keys";
491 #address-cells = <1>;
492 #size-cells = <0>;
493 pinctrl-names = "default";
494 pinctrl-0 = <&key_voldown &key_volup &key_power>;
495 button@1 {
496 label = "gpio-keys: KEY_VOLUMEDOWN";
497 linux,code = <114>;
498 gpios = <&gpa1 6 0xf>;
499 };
500 button@2 {
501 label = "gpio-keys: KEY_VOLUMEUP";
502 linux,code = <115>;
503 gpios = <&gpa1 5 0xf>;
504 };
505 button@3 {
506 label = "gpio-keys: KEY_POWER";
507 linux,code = <116>;
508 gpios = <&gpa1 7 0xf>;
509 gpio-key,wakeup = <1>;
510 };
511 };
512
513 dwmmc2@13550000 {
514 status = "okay";
515 num-slots = <1>;
516 supports-4bit;
517 supports-cmd23;
518 supports-erase;
519 supports-highspeed;
520 sd-uhs-sdr50;
521 sd-uhs-sdr104;
522 card-detect-invert;
523 card-detect-gpio;
524 bypass-for-allpass;
525 card-init-hwacg-ctrl;
526 skip-init-mmc-scan;
527 qos-dvfs-level = <100000>;
528 fifo-depth = <0x40>;
529 desc-size = <4>;
530 card-detect-delay = <200>;
531 data-timeout = <200>;
532 hto-timeout = <80>;
533 samsung,dw-mshc-ciu-div = <3>;
534 clock-frequency = <800000000>;
535 samsung,dw-mshc-sdr-timing = <3 0 2 0>;
536 samsung,dw-mshc-ddr-timing = <3 0 2 1>;
537 samsung,dw-mshc-sdr50-timing = <3 0 4 2>;
538 samsung,dw-mshc-sdr104-timing = <3 0 3 0>;
539
540 num-ref-clks = <9>;
541 ciu_clkin = <25 50 50 25 50 100 200 50 50>;
542
543 /* Swapping clock drive strength */
544 clk-drive-number = <4>;
545 pinctrl-names = "default",
546 "fast-slew-rate-1x",
547 "fast-slew-rate-2x",
548 "fast-slew-rate-3x",
549 "fast-slew-rate-4x";
550 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4 &dwmmc2_cd_ext_irq>;
551 pinctrl-1 = <&sd2_clk_fast_slew_rate_1x>;
552 pinctrl-2 = <&sd2_clk_fast_slew_rate_2x>;
553 pinctrl-3 = <&sd2_clk_fast_slew_rate_3x>;
554 pinctrl-4 = <&sd2_clk_fast_slew_rate_4x>;
555
556 card-detect = <&gpa0 7 0xf>;
557 #address-cells = <1>;
558 #size-cells = <0>;
559 slot@0 {
560 reg = <0>;
561 bus-width = <4>;
562 disable-wp;
563 };
564 };
565
566 usb_notifier {
567 compatible = "samsung,usb-notifier";
568 udc = <&udc>;
569 };
570
571 usb_hs_tune:usb_hs_tune {
572 hs_tune_cnt = <12>;
573
574 /* value = <device host> */
575 hs_tune1 {
576 tune_name = "tx_vref";
577 tune_value = <0xf 0xf>;
578 };
579
580 hs_tune2 {
581 tune_name = "tx_pre_emp";
582 tune_value = <0x3 0x3>;
583 };
584
585 hs_tune3 {
586 tune_name = "tx_pre_emp_plus";
587 tune_value = <0x0 0x0>;
588 };
589
590 hs_tune4 {
591 tune_name = "tx_res";
592 tune_value = <0x3 0x3>;
593 };
594
595 hs_tune5 {
596 tune_name = "tx_rise";
597 tune_value = <0x3 0x3>;
598 };
599
600 hs_tune6 {
601 tune_name = "tx_hsxv";
602 tune_value = <0x3 0x3>;
603 };
604
605 hs_tune7 {
606 tune_name = "tx_fsls";
607 tune_value = <0x3 0x3>;
608 };
609
610 hs_tune8 {
611 tune_name = "rx_sqrx";
612 tune_value = <0x7 0x7>;
613 };
614
615 hs_tune9 {
616 tune_name = "compdis";
617 tune_value = <0x7 0x7>;
618 };
619
620 hs_tune10 {
621 tune_name = "otg";
622 tune_value = <0x2 0x2>;
623 };
624
625 hs_tune11 {
626 /* true : 1, false: 0 */
627 /* <enable_user_imp user_imp_value> */
628 tune_name = "enable_user_imp";
629 tune_value = <0x0 0x0>;
630 };
631
632 hs_tune12 {
633 /* PHY clk : 1 , FREE clk : 0 */
634 tune_name = "is_phyclock";
635 tune_value = <0x1 0x1>;
636 };
637 };
638
639 usb3_ss_tune:ss_tune {
640 ss_tune_cnt = <15>;
641
642 /* value = <device host> */
643 ss_tune1 {
644 tune_name = "tx0_term_offset";
645 tune_value = <0x0 0x0>;
646 };
647
648 ss_tune2 {
649 tune_name = "pcs_tx_swing_full";
650 tune_value = <0x7f 0x7f>;
651 };
652
653 ss_tune3 {
654 tune_name = "pcs_tx_deemph_6db";
655 tune_value = <0x1c 0x1c>;
656 };
657
658 ss_tune4 {
659 tune_name = "pcs_tx_deemph_3p5db";
660 tune_value = <0x1c 0x1c>;
661 };
662
663 ss_tune5 {
664 tune_name = "tx_vboost_lvl_sstx";
665 tune_value = <0x7 0x7>;
666 };
667
668 ss_tune6 {
669 tune_name = "tx_vboost_lvl";
670 tune_value = <0x4 0x4>;
671 };
672
673 ss_tune7 {
674 tune_name = "los_level";
675 tune_value = <0x9 0x9>;
676 };
677
678 ss_tune8 {
679 tune_name = "los_bias";
680 tune_value = <0x5 0x5>;
681 };
682
683 ss_tune9 {
684 tune_name = "pcs_rx_los_mask_val";
685 tune_value = <0x104 0x104>;
686 };
687
688 ss_tune10 {
689 tune_name = "tx_eye_height_cntl_en";
690 tune_value = <0x1 0x1>;
691 };
692
693 ss_tune11 {
694 tune_name = "pipe_tx_deemph_update_delay";
695 tune_value = <0x2 0x2>;
696 };
697
698 ss_tune12 {
699 tune_name = "pcs_tx_swing_full_sstx";
700 tune_value = <0x7f 0x7f>;
701 };
702 ss_tune13 {
703 tune_name = "rx_eq_fix_val";
704 tune_value = <0x2 0x2>;
705 };
706
707 ss_tune14 {
708 tune_name = "rx_decode_mode";
709 tune_value = <0x1 0x1>;
710 };
711
712 ss_tune15 {
713 tune_name = "decrese_ss_tx_imp";
714 tune_value = <0x1 0x1>;
715 };
716 };
717
718 usb3_hs_tune:usb3_hs_tune {
719 hs_tune_cnt = <10>;
720
721 /* value = <device host> */
722 hs_tune1 {
723 tune_name = "tx_pre_emp";
724 tune_value = <0x3 0x3>;
725 };
726
727 hs_tune2 {
728 tune_name = "tx_pre_emp_plus";
729 tune_value = <0x0 0x0>;
730 };
731
732 hs_tune3 {
733 tune_name = "tx_vref";
734 tune_value = <0x7 0x7>;
735 };
736
737 hs_tune4 {
738 tune_name = "rx_sqrx";
739 tune_value = <0x7 0x7>;
740 };
741
742 hs_tune5 {
743 tune_name = "tx_rise";
744 tune_value = <0x3 0x3>;
745 };
746
747 hs_tune6 {
748 tune_name = "compdis";
749 tune_value = <0x7 0x7>;
750 };
751
752 hs_tune7 {
753 tune_name = "tx_hsxv";
754 tune_value = <0x3 0x3>;
755 };
756
757 hs_tune8 {
758 tune_name = "tx_fsls";
759 tune_value = <0x3 0x3>;
760 };
761
762 hs_tune9 {
763 tune_name = "tx_res";
764 tune_value = <0x3 0x3>;
765 };
766
767 hs_tune10 {
768 tune_name = "utim_clk";
769 tune_value = <0x1 0x1>;
770 };
771 };
772
773 /* Secure RPMB */
774 ufs-srpmb {
775 compatible = "samsung,ufs-srpmb";
776 interrupts = <0 460 0>;
777 };
778
779 V_SYS: fixedregulator@0 {
780 compatible = "regulator-fixed";
781 regulator-name = "V_SYS";
782 regulator-min-microvolt = <4200000>;
783 regulator-max-microvolt = <4200000>;
784 regulator-boot-on;
785 regulator-always-on;
786 };
787
788
789 dummy_audio_codec: audio_codec_dummy {
790 status = "okay";
791 compatible = "snd-soc-dummy";
792 };
793
794 dummy_audio_cpu: audio_cpu_dummy {
795 compatible = "samsung,dummy-cpu";
796 status = "okay";
797 };
798
799 sound {
800 status = "okay";
801 compatible = "samsung,exynos9610-madera";
802
803 clock-names = "xclkout";
804 clocks = <&clock OSC_AUD>;
805 pinctrl-names = "default";
806 pinctrl-0 = <&xclkout0>;
807
808 cirrus,sysclk = <1 4 98304000>;
809 cirrus,dspclk = <8 4 147456000>;
810 cirrus,fll1-refclk = <1 0 26000000 98304000>;
811
812 cirrus,opclk = <3 0 12288000>;
813
814 samsung,routing =
815 "HEADSETMIC", "MICBIAS1B",
816 "IN1BR", "HEADSETMIC",
817 "DMIC1", "MICBIAS2A",
818 "IN1AL", "DMIC1",
819 "DMIC2", "MICBIAS2A",
820 "IN2L", "DMIC2",
821 "DMIC3", "MICBIAS2B",
822 "IN2R", "DMIC3",
823 "RECEIVER", "EPOUTN",
824 "RECEIVER", "EPOUTP",
825 "HEADPHONE", "HPOUTL",
826 "HEADPHONE", "HPOUTR",
827 "AIF2 Playback", "OPCLK",
828 "AIF2 Capture", "OPCLK",
829 "VOUTPUT", "ABOX UAIF0 Playback",
830 "SPEAKER", "Left SPK",
831 "VOUTPUTCALL", "ABOX SIFS0 Playback",
832 "ABOX SIFS0 Capture", "VINPUTCALL";
833
834 samsung,codec = <&abox &abox_uaif_0 &abox_uaif_1 &abox_uaif_2
835 &abox_uaif_4 &abox_dsif &abox_spdy &cs35l41_left>;
836 samsung,prefix = "ABOX", "ABOX", "ABOX", "ABOX",
837 "ABOX", "ABOX", "ABOX", "Left";
838 samsung,aux = <&abox_effect &abox_bt>;
839
840 rdma@0 {
841 cpu {
842 sound-dai = <&abox 0>;
843 };
844 platform {
845 sound-dai = <&abox_rdma_0>;
846 };
847 codec {
848 sound-dai = <&dummy_audio_codec>;
849 };
850 };
851 rdma@1 {
852 cpu {
853 sound-dai = <&abox 1>;
854 };
855 platform {
856 sound-dai = <&abox_rdma_1>;
857 };
858 codec {
859 sound-dai = <&dummy_audio_codec>;
860 };
861 };
862 rdma@2 {
863 cpu {
864 sound-dai = <&abox 2>;
865 };
866 platform {
867 sound-dai = <&abox_rdma_2>;
868 };
869 codec {
870 sound-dai = <&dummy_audio_codec>;
871 };
872 };
873 rdma@3 {
874 cpu {
875 sound-dai = <&abox 3>;
876 };
877 platform {
878 sound-dai = <&abox_rdma_3>;
879 };
880 codec {
881 sound-dai = <&dummy_audio_codec>;
882 };
883 };
884 rdma@4 {
885 cpu {
886 sound-dai = <&abox 4>;
887 };
888 platform {
889 sound-dai = <&abox_rdma_4>;
890 };
891 codec {
892 sound-dai = <&dummy_audio_codec>;
893 };
894 };
895 rdma@5 {
896 cpu {
897 sound-dai = <&abox 5>;
898 };
899 platform {
900 sound-dai = <&abox_rdma_5>;
901 };
902 codec {
903 sound-dai = <&dummy_audio_codec>;
904 };
905 };
906 rdma@6 {
907 cpu {
908 sound-dai = <&abox 6>;
909 };
910 platform {
911 sound-dai = <&abox_rdma_6>;
912 };
913 codec {
914 sound-dai = <&dummy_audio_codec>;
915 };
916 };
917 rdma@7 {
918 cpu {
919 sound-dai = <&abox 7>;
920 };
921 platform {
922 sound-dai = <&abox_rdma_7>;
923 };
924 codec {
925 sound-dai = <&dummy_audio_codec>;
926 };
927 };
928 wdma@0 {
929 cpu {
930 sound-dai = <&abox 8>;
931 };
932 platform {
933 sound-dai = <&abox_wdma_0>;
934 };
935 codec {
936 sound-dai = <&dummy_audio_codec>;
937 };
938 };
939 wdma@1 {
940 cpu {
941 sound-dai = <&abox 9>;
942 };
943 platform {
944 sound-dai = <&abox_wdma_1>;
945 };
946 codec {
947 sound-dai = <&dummy_audio_codec>;
948 };
949 };
950 wdma@2 {
951 cpu {
952 sound-dai = <&abox 10>;
953 };
954 platform {
955 sound-dai = <&abox_wdma_2>;
956 };
957 codec {
958 sound-dai = <&dummy_audio_codec>;
959 };
960 };
961 wdma@3 {
962 cpu {
963 sound-dai = <&abox 11>;
964 };
965 platform {
966 sound-dai = <&abox_wdma_3>;
967 };
968 codec {
969 sound-dai = <&dummy_audio_codec>;
970 };
971 };
972 wdma@4 {
973 cpu {
974 sound-dai = <&abox 12>;
975 };
976 platform {
977 sound-dai = <&abox_wdma_4>;
978 };
979 codec {
980 sound-dai = <&dummy_audio_codec>;
981 };
982 };
983 /** ToDo: enable dp_audio link after enabling DP Audio
984 * dp_audio@0 {
985 * cpu {
986 * sound-dai = <&dummy_audio_cpu>;
987 * };
988 * codec {
989 * sound-dai = <&dummy_audio_codec>;
990 * };
991 * };
992 */
993 uaif@0 {
994 format = "i2s";
995 cpu {
996 sound-dai = <&abox_uaif_0>;
997 };
998 codec {
999 sound-dai = <&cs47l35 0>;
1000 };
1001 };
1002 uaif@1 {
1003 format = "i2s";
1004 cpu {
1005 sound-dai = <&abox_uaif_1>;
1006 };
1007 codec {
1008 sound-dai = <&dummy_audio_codec>;
1009 };
1010 };
1011 uaif@2 {
1012 format = "i2s";
1013 cpu {
1014 sound-dai = <&abox_uaif_2>;
1015 };
1016 codec {
1017 sound-dai = <&cs47l35 2>;
1018 };
1019 };
1020 uaif@4 {
1021 format = "i2s";
1022 bitclock-master;
1023 frame-master;
1024 cpu {
1025 sound-dai = <&abox_uaif_4>;
1026 };
1027 codec {
1028 sound-dai = <&dummy_audio_codec>;
1029 };
1030 };
1031 dsif@0 {
1032 format = "pdm";
1033 cpu {
1034 sound-dai = <&abox_dsif>;
1035 };
1036 codec {
1037 sound-dai = <&dummy_audio_codec>;
1038 };
1039 };
1040 spdy@0 {
1041 cpu {
1042 sound-dai = <&abox_spdy>;
1043 };
1044 codec {
1045 sound-dai = <&dummy_audio_codec>;
1046 };
1047 };
1048 sifs0@0 {
1049 cpu {
1050 sound-dai = <&abox 13>;
1051 };
1052 codec {
1053 sound-dai = <&dummy_audio_codec>;
1054 };
1055 };
1056 sifs1@0 {
1057 cpu {
1058 sound-dai = <&abox 14>;
1059 };
1060 codec {
1061 sound-dai = <&dummy_audio_codec>;
1062 };
1063 };
1064 sifs2@0 {
1065 cpu {
1066 sound-dai = <&abox 15>;
1067 };
1068 codec {
1069 sound-dai = <&dummy_audio_codec>;
1070 };
1071 };
1072
1073 codec-left-amp@0 {
1074 format = "i2s";
1075
1076 cpu {
1077 sound-dai = <&cs47l35 1>;
1078 };
1079 codec {
1080 sound-dai = <&cs35l41_left 0>;
1081 };
1082 };
1083 };
1084
1085
1086 #if 0
1087 fimc_is@144B0000 {
1088 vender {
1089 rear_sensor_id = <47>; /* 46: RPB, 20: 2P8, 47: 2P7SQ */
1090 front_sensor_id = <7>; /* 6B2 */
1091 rear_second_sensor_id = <48>; /* 48: 2T7SX */
1092 secure_sensor_id = <22>; /* 5E2 */
1093 };
1094
1095 fimc_is_dvfs {
1096 #define DVFS_INT_CAM_L0 690000
1097 #define DVFS_INT_CAM_L1 680000
1098 #define DVFS_INT_CAM_L2 670000
1099 #define DVFS_INT_CAM_L3 660000
1100 #define DVFS_INT_CAM_L4 650000
1101
1102 #define DVFS_INT_L0 667000
1103 #define DVFS_INT_L1 533000
1104 #define DVFS_INT_L2 400000
1105 #define DVFS_INT_L3 200000
1106 #define DVFS_INT_L4 100000
1107
1108 #define DVFS_CAM_L0 690000
1109 #define DVFS_CAM_L1 680000
1110 #define DVFS_CAM_L2 670000
1111 #define DVFS_CAM_L3 660000
1112 #define DVFS_CAM_L4 650000
1113 #define DVFS_CAM_L5 640000
1114
1115 #define DVFS_MIF_L0 2093000
1116 #define DVFS_MIF_L1 2002000
1117 #define DVFS_MIF_L2 1794000
1118 #define DVFS_MIF_L3 1539000
1119 #define DVFS_MIF_L4 1352000
1120 #define DVFS_MIF_L5 1014000
1121 #define DVFS_MIF_L6 845000
1122 #define DVFS_MIF_L7 676000
1123 #define DVFS_MIF_L8 546000
1124 #define DVFS_MIF_L9 419000
1125
1126 table0 {
1127 desc = "dvfs table v0.0 for 16M/2M";
1128
1129 default_int_cam = <DVFS_INT_CAM_L0>;
1130 default_cam = <DVFS_CAM_L0>;
1131 default_mif = <DVFS_MIF_L0>;
1132 default_int = <DVFS_INT_L0>;
1133 default_hpg = <1>;
1134
1135 front_preview_int_cam = <DVFS_INT_CAM_L0>;
1136 front_preview_cam = <DVFS_CAM_L0>;
1137 front_preview_mif = <DVFS_MIF_L0>;
1138 front_preview_int = <DVFS_INT_L0>;
1139 front_preview_hpg = <1>;
1140
1141 front_preview_full_int_cam = <DVFS_INT_CAM_L0>;
1142 front_preview_full_cam = <DVFS_CAM_L0>;
1143 front_preview_full_mif = <DVFS_MIF_L0>;
1144 front_preview_full_int = <DVFS_INT_L0>;
1145 front_preview_full_hpg = <1>;
1146
1147 front_capture_int_cam = <DVFS_INT_CAM_L0>;
1148 front_capture_cam = <DVFS_CAM_L0>;
1149 front_capture_mif = <DVFS_MIF_L0>;
1150 front_capture_int = <DVFS_INT_L0>;
1151 front_capture_hpg = <1>;
1152
1153 front_video_int_cam = <DVFS_INT_CAM_L0>;
1154 front_video_cam = <DVFS_CAM_L0>;
1155 front_video_mif = <DVFS_MIF_L0>;
1156 front_video_int = <DVFS_INT_L0>;
1157 front_video_hpg = <1>;
1158
1159 front_video_capture_int_cam = <DVFS_INT_CAM_L0>;
1160 front_video_capture_cam = <DVFS_CAM_L0>;
1161 front_video_capture_mif = <DVFS_MIF_L0>;
1162 front_video_capture_int = <DVFS_INT_L0>;
1163 front_video_capture_hpg = <1>;
1164
1165 front_wide_selfie_int_cam = <DVFS_INT_CAM_L0>;
1166 front_wide_selfie_cam = <DVFS_CAM_L0>;
1167 front_wide_selfie_mif = <DVFS_MIF_L0>;
1168 front_wide_selfie_int = <DVFS_INT_L0>;
1169 front_wide_selfie_hpg = <1>;
1170
1171 front_vt1_int_cam = <DVFS_INT_CAM_L0>;
1172 front_vt1_cam = <DVFS_CAM_L0>;
1173 front_vt1_mif = <DVFS_MIF_L0>;
1174 front_vt1_int = <DVFS_INT_L0>;
1175 front_vt1_hpg = <1>;
1176
1177 front_vt2_int_cam = <DVFS_INT_CAM_L0>;
1178 front_vt2_cam = <DVFS_CAM_L0>;
1179 front_vt2_mif = <DVFS_MIF_L0>;
1180 front_vt2_int = <DVFS_INT_L0>;
1181 front_vt2_hpg = <1>;
1182
1183 front_vt4_int_cam = <DVFS_INT_CAM_L0>;
1184 front_vt4_cam = <DVFS_CAM_L0>;
1185 front_vt4_mif = <DVFS_MIF_L0>;
1186 front_vt4_int = <DVFS_INT_L0>;
1187 front_vt4_hpg = <1>;
1188
1189 rear_preview_fhd_int_cam = <DVFS_INT_CAM_L0>;
1190 rear_preview_fhd_cam = <DVFS_CAM_L0>;
1191 rear_preview_fhd_mif = <DVFS_MIF_L0>;
1192 rear_preview_fhd_int = <DVFS_INT_L0>;
1193 rear_preview_fhd_hpg = <1>;
1194
1195 rear_preview_hd_int_cam = <DVFS_INT_CAM_L0>;
1196 rear_preview_hd_cam = <DVFS_CAM_L0>;
1197 rear_preview_hd_mif = <DVFS_MIF_L0>;
1198 rear_preview_hd_int = <DVFS_INT_L0>;
1199 rear_preview_hd_hpg = <1>;
1200
1201 rear_preview_uhd_int_cam = <DVFS_INT_CAM_L0>;
1202 rear_preview_uhd_cam = <DVFS_CAM_L0>;
1203 rear_preview_uhd_mif = <DVFS_MIF_L0>;
1204 rear_preview_uhd_int = <DVFS_INT_L0>;
1205 rear_preview_uhd_hpg = <1>;
1206
1207 rear_preview_full_int_cam = <DVFS_INT_CAM_L0>;
1208 rear_preview_full_cam = <DVFS_CAM_L0>;
1209 rear_preview_full_mif = <DVFS_MIF_L0>;
1210 rear_preview_full_int = <DVFS_INT_L0>;
1211 rear_preview_full_hpg = <1>;
1212
1213 rear_capture_int_cam = <DVFS_INT_CAM_L0>;
1214 rear_capture_cam = <DVFS_CAM_L0>;
1215 rear_capture_mif = <DVFS_MIF_L0>;
1216 rear_capture_int = <DVFS_INT_L0>;
1217 rear_capture_hpg = <1>;
1218
1219 rear_video_fhd_int_cam = <DVFS_INT_CAM_L0>;
1220 rear_video_fhd_cam = <DVFS_CAM_L0>;
1221 rear_video_fhd_mif = <DVFS_MIF_L0>;
1222 rear_video_fhd_int = <DVFS_INT_L0>;
1223 rear_video_fhd_hpg = <1>;
1224
1225 rear_video_hd_int_cam = <DVFS_INT_CAM_L0>;
1226 rear_video_hd_cam = <DVFS_CAM_L0>;
1227 rear_video_hd_mif = <DVFS_MIF_L0>;
1228 rear_video_hd_int = <DVFS_INT_L0>;
1229 rear_video_hd_hpg = <1>;
1230
1231 rear_video_uhd_int_cam = <DVFS_INT_CAM_L0>;
1232 rear_video_uhd_cam = <DVFS_CAM_L0>;
1233 rear_video_uhd_mif = <DVFS_MIF_L0>;
1234 rear_video_uhd_int = <DVFS_INT_L0>;
1235 rear_video_uhd_hpg = <1>;
1236
1237 rear_video_fhd_capture_int_cam = <DVFS_INT_CAM_L0>;
1238 rear_video_fhd_capture_cam = <DVFS_CAM_L0>;
1239 rear_video_fhd_capture_mif = <DVFS_MIF_L0>;
1240 rear_video_fhd_capture_int = <DVFS_INT_L0>;
1241 rear_video_fhd_capture_hpg = <1>;
1242
1243 rear_video_hd_capture_int_cam = <DVFS_INT_CAM_L0>;
1244 rear_video_hd_capture_cam = <DVFS_CAM_L0>;
1245 rear_video_hd_capture_mif = <DVFS_MIF_L0>;
1246 rear_video_hd_capture_int = <DVFS_INT_L0>;
1247 rear_video_hd_capture_hpg = <1>;
1248
1249 rear_video_uhd_capture_int_cam = <DVFS_INT_CAM_L0>;
1250 rear_video_uhd_capture_cam = <DVFS_CAM_L0>;
1251 rear_video_uhd_capture_mif = <DVFS_MIF_L0>;
1252 rear_video_uhd_capture_int = <DVFS_INT_L0>;
1253 rear_video_uhd_capture_hpg = <1>;
1254
1255 secure_front_int_cam = <DVFS_INT_CAM_L0>;
1256 secure_front_cam = <DVFS_CAM_L0>;
1257 secure_front_mif = <DVFS_MIF_L0>;
1258 secure_front_int = <DVFS_INT_L0>;
1259 secure_front_hpg = <1>;
1260
1261 pip_preview_int_cam = <DVFS_INT_CAM_L0>;
1262 pip_preview_cam = <DVFS_CAM_L0>;
1263 pip_preview_mif = <DVFS_MIF_L0>;
1264 pip_preview_int = <DVFS_INT_L0>;
1265 pip_preview_hpg = <1>;
1266
1267 pip_capture_int_cam = <DVFS_INT_CAM_L0>;
1268 pip_capture_cam = <DVFS_CAM_L0>;
1269 pip_capture_mif = <DVFS_MIF_L0>;
1270 pip_capture_int = <DVFS_INT_L0>;
1271 pip_capture_hpg = <1>;
1272
1273 pip_video_int_cam = <DVFS_INT_CAM_L0>;
1274 pip_video_cam = <DVFS_CAM_L0>;
1275 pip_video_mif = <DVFS_MIF_L0>;
1276 pip_video_int = <DVFS_INT_L0>;
1277 pip_video_hpg = <1>;
1278
1279 pip_video_capture_int_cam = <DVFS_INT_CAM_L0>;
1280 pip_video_capture_cam = <DVFS_CAM_L0>;
1281 pip_video_capture_mif = <DVFS_MIF_L0>;
1282 pip_video_capture_int = <DVFS_INT_L0>;
1283 pip_video_capture_hpg = <1>;
1284
1285 preview_high_speed_fps_int_cam = <DVFS_INT_CAM_L1>;
1286 preview_high_speed_fps_cam = <DVFS_CAM_L3>;
1287 preview_high_speed_fps_mif = <DVFS_MIF_L5>;
1288 preview_high_speed_fps_int = <DVFS_INT_L0>;
1289 preview_high_speed_fps_hpg = <1>;
1290
1291 video_high_speed_60fps_int_cam = <DVFS_INT_CAM_L0>;
1292 video_high_speed_60fps_cam = <DVFS_CAM_L0>;
1293 video_high_speed_60fps_mif = <DVFS_MIF_L0>;
1294 video_high_speed_60fps_int = <DVFS_INT_L0>;
1295 video_high_speed_60fps_hpg = <1>;
1296
1297 video_high_speed_480fps_int_cam = <DVFS_INT_CAM_L0>;
1298 video_high_speed_480fps_cam = <DVFS_CAM_L0>;
1299 video_high_speed_480fps_mif = <DVFS_MIF_L0>;
1300 video_high_speed_480fps_int = <DVFS_INT_L0>;
1301 video_high_speed_480fps_hpg = <1>;
1302
1303 video_high_speed_60fps_capture_int_cam = <DVFS_INT_CAM_L0>;
1304 video_high_speed_60fps_capture_cam = <DVFS_CAM_L0>;
1305 video_high_speed_60fps_capture_mif = <DVFS_MIF_L0>;
1306 video_high_speed_60fps_capture_int = <DVFS_INT_L0>;
1307 video_high_speed_60fps_capture_hpg = <1>;
1308
1309 ext_front_int_cam = <DVFS_INT_CAM_L0>;
1310 ext_front_cam = <DVFS_CAM_L0>;
1311 ext_front_mif = <DVFS_MIF_L0>;
1312 ext_front_int = <DVFS_INT_L0>;
1313 ext_front_hpg = <1>;
1314
1315 ext_secure_int_cam = <DVFS_INT_CAM_L3>;
1316 ext_secure_cam = <DVFS_CAM_L4>;
1317 ext_secure_mif = <DVFS_MIF_L7>;
1318 ext_secure_int = <DVFS_INT_L4>;
1319 ext_secure_hpg = <1>;
1320
1321 max_int_cam = <DVFS_INT_CAM_L0>;
1322 max_cam = <DVFS_CAM_L0>;
1323 max_mif = <DVFS_MIF_L0>;
1324 max_int = <DVFS_INT_L0>;
1325 max_hpg = <1>;
1326 };
1327 };
1328 };
1329
1330 fimc_is_flash_gpio: fimc-is-flash-gpio@0 {
1331 compatible = "samsung,sensor-flash-gpio";
1332 id = <0>;
1333 status = "okay";
1334
1335 torch-gpio = <&gpg3 1 0x1>;
1336 flash-gpio = <&gpg3 0 0x1>;
1337 };
1338
1339 fimc_is_sensor_2p7sq: fimc-is_sensor_2p7sq@47 {
1340 compatible = "samsung,sensor-module-2p7sq";
1341
1342 pinctrl-names = "pin0", "pin1", "pin2", "release";
1343 pinctrl-0 = <>;
1344 pinctrl-1 = <&fimc_is_mclk0_out>;
1345 pinctrl-2 = <&fimc_is_mclk0_fn>;
1346 pinctrl-3 = <>;
1347
1348 position = <0>; /* Rear:0. Front:1. Rear_sub:2. Secure:3. */
1349 id = <0>; /* fimc_is_sensor id */
1350 mclk_ch = <0>;
1351 sensor_i2c_ch = <0>; /* SENSOR_CONTROL_I2C0 */
1352
1353 gpio_mclk = <&gpc2 0 0x1>;
1354 gpio_reset = <&gpc1 0 0x1>; /* sensor reset */
1355
1356 power_seq_id = <1>; /* Rumba S6 Compatible */
1357
1358 status = "okay";
1359
1360 af {
1361 product_name = <20>; /* ACTUATOR_NAME_LC898217 */
1362 i2c_ch = <0>; /* SENSOR_CONTROL_I2C0 */
1363 };
1364
1365 flash {
1366 product_name = <11>; /* FLASH_GPIO */
1367 };
1368 };
1369
1370 fimc_is_sensor_2t7sx: fimc-is_sensor_2t7sx@48 {
1371 compatible = "samsung,sensor-module-2t7sx";
1372
1373 pinctrl-names = "pin0", "pin1", "pin2", "release";
1374 pinctrl-0 = <>;
1375 pinctrl-1 = <&fimc_is_mclk2_out>;
1376 pinctrl-2 = <&fimc_is_mclk2_fn>;
1377 pinctrl-3 = <>;
1378
1379 position = <2>; /* Rear:0. Front:1. Rear_sub:2. Secure:3. */
1380 id = <2>; /* fimc_is_sensor id */
1381 mclk_ch = <2>;
1382 sensor_i2c_ch = <1>; /* SENSOR_CONTROL_I2C1 */
1383
1384 gpio_mclk = <&gpc2 2 0x1>;
1385 gpio_reset = <&gpc0 6 0x1>; /* sensor reset */
1386
1387 power_seq_id = <1>; /* Rumba S6 Compatible */
1388
1389 status = "okay";
1390
1391 af {
1392 product_name = <20>; /* ACTUATOR_NAME_LC898217 */
1393 i2c_ch = <1>; /* SENSOR_CONTROL_I2C1 */
1394 };
1395
1396 flash {
1397 product_name = <11>; /* FLASH_GPIO */
1398 };
1399 };
1400
1401 /* FRONT CAMERA */
1402 fimc_is_sensor_6b2: fimc-is_sensor_6b2@7 {
1403 compatible = "samsung,sensor-module-6b2";
1404
1405 pinctrl-names = "pin0", "pin1", "pin2", "release";
1406 pinctrl-0 = <>;
1407 pinctrl-1 = <&fimc_is_mclk1_out>;
1408 pinctrl-2 = <&fimc_is_mclk1_fn>;
1409 pinctrl-3 = <>;
1410
1411 position = <1>; /* Rear:0. Front:1. Rear_sub:2. Secure:3. */
1412 id = <1>; /* fimc_is_sensor id */
1413 mclk_ch = <1>;
1414 sensor_i2c_ch = <2>; /* SENSOR_CONTROL_I2C4 */
1415
1416 gpio_mclk = <&gpc2 1 0x1>;
1417 gpio_reset = <&gpc1 2 0x1>; /* sensor reset */
1418 status = "okay";
1419
1420 af {
1421 product_name = <100>; /* NOTHING */
1422 i2c_ch = <2>; /* SENSOR_CONTROL_I2C2 */
1423 };
1424
1425 flash {
1426 product_name = <100>; /* NOTHING */
1427 };
1428
1429 ois {
1430 product_name = <100>; /* NOTHING */
1431 };
1432
1433 internal_vc {
1434 /* DUMMY */
1435 };
1436 };
1437
1438 /* I2C_CAM0 */ /* SENSOR_CONTROL_I2C0 */
1439 hsi2c_12: hsi2c@138A0000 {
1440 gpios = <&gpc0 0 0 &gpc0 1 0>;
1441 status = "okay";
1442 clock-frequency = <400000>;
1443 samsung,reset-before-trans;
1444 samsung,polling-mode;
1445
1446 fimc-is-2p7sq@2d {
1447 compatible = "samsung,exynos5-fimc-is-cis-2p7sq";
1448 reg = <0x2d>; /* 1 bit right shift */
1449 id = <0>; /* matching fimc_is_sensor id */
1450 setfile = "setA";
1451 };
1452
1453 fimc-is-actuator@72 {
1454 compatible = "samsung,exynos5-fimc-is-actuator-lc898217";
1455 reg = <0x72>; /* 1 bit right shift */
1456 id = <0>; /* matching fimc_is_sensor id */
1457 place = <0>;
1458 };
1459 };
1460
1461 /* I2C_CAM1 */ /* SENSOR_CONTROL_I2C1 */
1462 hsi2c_13: hsi2c@138B0000 {
1463 gpios = <&gpc0 2 0 &gpc0 3 0>;
1464 status = "okay";
1465 clock-frequency = <400000>;
1466 samsung,reset-before-trans;
1467 samsung,polling-mode;
1468
1469 fimc-is-2t7sx@10 {
1470 compatible = "samsung,exynos5-fimc-is-cis-2t7sx";
1471 reg = <0x10>; /* 1 bit right shift */
1472 id = <2>; /* matching fimc_is_sensor id */
1473 setfile = "setA";
1474 };
1475
1476 fimc-is-actuator@74 {
1477 compatible = "samsung,exynos5-fimc-is-actuator-lc898217";
1478 reg = <0x74>; /* 1 bit right shift */
1479 id = <2>; /* matching fimc_is_sensor id */
1480 place = <1>; /* HACK */
1481 };
1482 };
1483
1484 /* I2C_CAM2 */ /* SENSOR_CONTROL_I2C2 */
1485 hsi2c_14: hsi2c@138C0000 {
1486 gpios = <&gpc0 4 0 &gpc0 5 0>;
1487 status = "okay";
1488 clock-frequency = <400000>;
1489 samsung,reset-before-trans;
1490
1491 fimc-is-6b2@35 {
1492 compatible = "samsung,exynos5-fimc-is-cis-6b2";
1493 reg = <0x35>; /* 1 bit right shift */
1494 id = <1>; /* matching fimc_is_sensor id */
1495 setfile = "setA";
1496 };
1497 };
1498
1499 /* I2C_CAM3 */ /* SENSOR_CONTROL_I2C3 */
1500 hsi2c_15: hsi2c@138D0000 {
1501 gpios = <&gpc0 6 0 &gpc0 7 0>;
1502 status = "okay";
1503 clock-frequency = <400000>;
1504 samsung,reset-before-trans;
1505
1506 fimc-is-actuator@72 {
1507 compatible = "samsung,exynos5-fimc-is-actuator-dw9780";
1508 reg = <0x72>; /* 1 bit right shift */
1509 id = <0>; /* matching fimc_is_sensor id */
1510 place = <1>; /* HACK */
1511 };
1512 };
1513
1514 fimc_is_sensor0: fimc_is_sensor@14400000 {
1515 scenario = <SENSOR_SCENARIO_NORMAL>; /* Normal, Vision, OIS etc */
1516 id = <0>;
1517 csi_ch = <0>;
1518 dma_ch = <0 0 0 0 0 1 1 1>;
1519 vc_ch = <0 1 2 3 0 1 2 3>;
1520 flite_ch = <FLITE_ID_NOTHING>;
1521 is_bns = <0>;
1522 /* use_ssvc1_internal; */
1523 /* use_ssvc2_internal; */
1524 status = "okay";
1525 };
1526
1527 fimc_is_sensor1: fimc_is_sensor@14410000 {
1528 scenario = <SENSOR_SCENARIO_NORMAL>; /* Normal, Vision, OIS etc */
1529 id = <1>;
1530 csi_ch = <1>;
1531 dma_ch = <1 1 1 1 1 1 1 1>;
1532 vc_ch = <0 1 2 3 0 1 2 3>;
1533 flite_ch = <FLITE_ID_NOTHING>;
1534 is_bns = <0>;
1535 status = "okay";
1536 };
1537
1538 fimc_is_sensor2: fimc_is_sensor@14420000 {
1539 scenario = <SENSOR_SCENARIO_NORMAL>; /* Normal, Vision, OIS etc */
1540 id = <2>;
1541 csi_ch = <2>;
1542 dma_ch = <2 2 2 2>;
1543 vc_ch = <0 1 2 3>;
1544 flite_ch = <FLITE_ID_NOTHING>;
1545 is_bns = <0>;
1546 status = "okay";
1547 };
1548
1549 fimc_is_sensor3: fimc_is_sensor@14430000 {
1550 scenario = <SENSOR_SCENARIO_SECURE>; /* Normal, Vision, OIS etc */
1551 id = <3>;
1552 csi_ch = <3>;
1553 dma_ch = <3 3 3 3>;
1554 vc_ch = <0 1 2 3>;
1555 flite_ch = <FLITE_ID_NOTHING>;
1556 is_bns = <0>;
1557 status = "okay";
1558 };
1559 #endif
1560 }; /* end of __overlay__ */
1561 }; /* end of fragment */
1562 }; /* end of root */
1563
1564 &i2c_0 {
1565 #address-cells = <1>;
1566 #size-cells = <0>;
1567 status = "okay";
1568 s2mu106-fuelgauge@3B {
1569 compatible = "samsung,s2mu106-fuelgauge";
1570 reg = <0x3B>;
1571 pinctrl-names = "default";
1572 pinctrl-0 = <&fuel_irq>;
1573 fuelgauge,fuel_int = <&gpa2 3 0>;
1574 fuelgauge,fuel_alert_vol = <3400>;
1575 fuelgauge,fuel_alert_soc = <1>;
1576 fuelgauge,type_str = "SDI";
1577 fuelgauge,model_type = <1>;
1578 };
1579
1580 usbpd-s2mu106@3C {
1581 compatible = "sec-usbpd,i2c";
1582 reg = <0x3C>;
1583 pinctrl-names = "default";
1584 pinctrl-0 = <&usbpd_irq>;
1585 usbpd,usbpd_int = <&gpa2 2 0>;
1586
1587 pdic-manager {
1588 /* sink */
1589 pdic,max_power = <5000>;
1590 pdic,op_power = <2500>;
1591 pdic,max_voltage = <6000>;
1592 pdic,max_current = <2000>;
1593 pdic,min_current = <500>;
1594
1595 pdic,giveback = <0>;
1596 pdic,usb_com_capable = <1>;
1597 pdic,no_usb_suspend = <1>;
1598
1599 /* source */
1600 source,max_voltage = <5000>;
1601 source,min_voltage = <4000>;
1602 source,max_power = <2500>;
1603
1604 /* sink cap */
1605 sink,capable_max_voltage = <9000>;
1606 };
1607 };
1608 };
1609
1610 &i2c_1 {
1611 #address-cells = <1>;
1612 #size-cells = <0>;
1613 status = "okay";
1614 s2mu106@3d {
1615 compatible = "samsung,s2mu106mfd";
1616 reg = <0x3d>;
1617 pinctrl-names = "default";
1618 pinctrl-0 = <&if_pmic_irq>;
1619 s2mu106,irq-gpio = <&gpa2 1 0>;
1620 s2mu106,wakeup;
1621
1622 muic {
1623 status = "okay";
1624 muic,uart_addr = "11850000.pinctrl";
1625 muic,uart_rxd = "gpq0-3";
1626 muic,uart_txd = "gpq0-4";
1627 };
1628 };
1629
1630 s2mu106-haptic {
1631 status = "okay";
1632 haptic,pwm_id = <1>;
1633 haptic,operation_mode = <2>; /* 0 : ERM_I2C, 1 : ERM_GPIO, 2 : LRA */
1634 haptic,hbst_en;
1635 haptic,hbst_automode;
1636 haptic,boost_level = <5000>;
1637 };
1638
1639 s2mcs02-charger@41 {
1640 compatible = "samsung,s2mcs02-charger";
1641 reg = <0x41>;
1642 default-clk = <100000000>;
1643 };
1644
1645 flash_led {
1646 /* Change here if you want to use FLED_EN pin
1647 fled-en1-gpio = <&gpg1 2 0>;
1648 fled-en2-gpio = <&gpg1 2 0>;
1649 fled-en3-gpio = <&gpg1 2 0>;
1650 fled-en4-gpio = <&gpg1 2 0>;
1651 */
1652 status = "okay";
1653 default_current = <50>;
1654 max_current = <200>;
1655 default_timer = <0>;
1656
1657 s2mu106-channel1 {
1658 id = <0>;
1659 /*
1660 current = <100>;
1661 timer = <200>;
1662 */
1663 };
1664
1665 s2mu106-channel2 {
1666 id = <1>;
1667 /*
1668 current = <100>;
1669 timer = <200>;
1670 */
1671 };
1672
1673 s2mu106-channel3 {
1674 id = <2>;
1675 /*
1676 current = <100>;
1677 timer = <200>;
1678 */
1679 };
1680 };
1681
1682 s2mu106-charger {
1683 status = "okay";
1684 battery,charger_name = "s2mu106-charger";
1685 battery,chg_gpio_en = <0>;
1686 battery,chg_polarity_en = <0>;
1687 battery,chg_gpio_status = <0>;
1688 battery,chg_polarity_status = <0>;
1689 battery,chg_float_voltage = <4350>;
1690 battery,chg_recharge_vcell = <4250>;
1691 battery,chg_full_vcell = <4300>;
1692 battery,full_check_type = <2>;
1693 battery,full_check_type_2nd = <2>;
1694 battery,input_current_limit = <
1695 500 450 500 1200 500 1200 1200 1000 1000 1000
1696 1000 500 500 1200 1000 500 450>;
1697 battery,fast_charging_current = <
1698 500 450 500 1200 500 1200 1200 1000 1000 1000
1699 1000 500 500 1200 1000 500 450>;
1700 battery,full_check_current_1st = <
1701 300 0 300 300 300 300 300 300 300 300
1702 300 300 300 300 300 300 0>;
1703 battery,full_check_current_2nd = <
1704 100 0 100 100 100 100 100 100 100 100
1705 100 100 100 100 100 100 0>;
1706 };
1707 };
1708
1709 &i2c_2 {
1710 #address-cells = <1>;
1711 #size-cells = <0>;
1712 status = "okay";
1713
1714 sec-nfc@27 {
1715 compatible = "sec-nfc";
1716 reg = <0x27>;
1717
1718 sec-nfc,ven-gpio = <&gpg0 0 0>;
1719 sec-nfc,firm-gpio = <&gpg0 2 0>;
1720
1721 sec-nfc,irq-gpio = <&gpa1 2 0>;
1722 sec-nfc,clk_req-gpio = <&gpg0 1 0>;
1723 sec-nfc,ldo_en = <&gpm22 0 0>;
1724
1725 clock-names = "OSC_NFC";
1726 clocks = <&clock OSC_NFC>;
1727 pinctrl-names = "default";
1728 pinctrl-0 = <&xclkout1>;
1729 };
1730 };
1731
1732 &sec_pwm {
1733 status = "okay";
1734 pinctrl-names = "default";
1735 pinctrl-0 = <&motor_pwm>;
1736 };
1737
1738
1739 &fmp_0 {
1740 exynos,block-type = "sda";
1741 exynos,fips-block_offset = <5>;
1742 };
1743
1744 &contexthub_0 {
1745 /* chub irq pin lists */
1746 chub-irq-pin = <162>;
1747 clocks =
1748 /* SHUB */
1749 <&clock UMUX_CLKCMU_SHUB_BUS>,
1750 /* MAG. SENSOR : AK09918C */
1751 <&clock CMGP01_USI>,
1752 /* PROX. SENSOR : TMD3702 */
1753 <&clock CMGP03_USI>,
1754 /* ALS SENSOR : BH1726 */
1755 <&clock CMGP_I2C>;
1756 clock-names =
1757 "chub_bus",
1758 "cmgp_usi01",
1759 "cmgp_usi03",
1760 "cmgp_i2c";
1761 };
1762
1763 &pinctrl_0 {
1764 pmic_irq: pmic-irq {
1765 samsung,pins = "gpa2-0";
1766 samsung,pin-pud = <3>;
1767 samsung,pin-drv = <3>;
1768 };
1769
1770 sub_pmic_irq: sub-pmic-irq {
1771 samsung,pins = "gpa1-3";
1772 samsung,pin-function = <0>;
1773 samsung,pin-pud = <0>;
1774 samsung,pin-drv = <0>;
1775 };
1776
1777
1778 key_voldown: key-voldown {
1779 samsung,pins = "gpa1-6";
1780 samsung,pin-function = <0xf>;
1781 samsung,pin-pud = <0>;
1782 samsung,pin-drv = <0>;
1783 };
1784
1785 key_volup: key-volup {
1786 samsung,pins = "gpa1-5";
1787 samsung,pin-function = <0xf>;
1788 samsung,pin-pud = <0>;
1789 samsung,pin-drv = <0>;
1790 };
1791
1792 key_power: key-power {
1793 samsung,pins = "gpa1-7";
1794 samsung,pin-function = <0xf>;
1795 samsung,pin-pud = <0>;
1796 samsung,pin-drv = <0>;
1797 };
1798
1799 dwmmc2_cd_ext_irq: dwmmc2_cd_ext_irq {
1800 samsung,pins = "gpa0-7";
1801 samsung,pin-function = <0xf>;
1802 samsung,pin-pud = <0>;
1803 samsung,pin-drv = <3>;
1804 };
1805
1806 attn_irq: attn-irq {
1807 samsung,pins = "gpa2-4";
1808 samsung,pin-function = <0xf>;
1809 samsung,pin-pud = <0>;
1810 samsung,pin-drv = <0>;
1811 };
1812
1813 attn_input: attn-input {
1814 samsung,pins = "gpa2-4";
1815 samsung,pin-function = <0>;
1816 samsung,pin-pud = <1>;
1817 };
1818
1819 if_pmic_irq: if-pmic-irq {
1820 samsung,pins = "gpa2-1";
1821 samsung,pin-function = <0>;
1822 samsung,pin-pud = <0>;
1823 samsung,pin-drv = <0>;
1824 };
1825
1826 fuel_irq: fuel-irq {
1827 samsung,pins = "gpa2-3";
1828 samsung,pin-function = <0>;
1829 samsung,pin-pud = <0>;
1830 samsung,pin-drv = <0>;
1831 };
1832
1833 usbpd_irq: usbpd-irq {
1834 samsung,pins = "gpa2-2";
1835 samsung,pin-function = <0xf>;
1836 samsung,pin-pud = <3>;
1837 samsung,pin-drv = <3>;
1838 };
1839 /* TODO: Need to check pin number
1840 small_charger_irq: small-charger-irq {
1841 samsung,pins = "gpa2-5";
1842 samsung,pin-function = <0>;
1843 samsung,pin-pud = <0>;
1844 samsung,pin-drv = <0>;
1845 };
1846 */
1847 cap_int_status: cap_int_status {
1848 samsung,pins = "gpa2-6";
1849 samsung,pin-function = <0>;
1850 samsung,pin-val = <1>;
1851 samsung,pin-pud = <1>;
1852 };
1853 };
1854
1855 &pinctrl_4 {
1856 /* Warm reset information from AP */
1857 pm_wrsti: pm-wrsti {
1858 samsung,pins = "gpg0-7";
1859 samsung,pin-con-pdn = <3>;
1860 };
1861
1862 motor_pwm: motor_pwm {
1863 samsung,pins = "gpg4-2";
1864 samsung,pin-function = <2>;
1865 samsung,pin-pud = <1>;
1866 samsung,pin-drv = <0>;
1867 };
1868
1869 vdd_on: vdd-on {
1870 samsung,pins ="gpg3-4";
1871 samsung,pin-function = <1>;
1872 samsung,pin-val = <1>;
1873 samsung,pin-pud = <3>;
1874 };
1875
1876 vdd_off: vdd-off {
1877 samsung,pins ="gpg3-4";
1878 samsung,pin-function = <0>;
1879 samsung,pin-val = <0>;
1880 samsung,pin-pud = <1>;
1881 };
1882
1883 codec_reset: codec-reset {
1884 samsung,pins ="gpg3-2";
1885 samsung,pin-pud = <0>;
1886 samsung,pin-con-pdn =<3>;
1887 samsung,pin-pud-pdn = <0>;
1888 };
1889
1890 codec_en: codec_en {
1891 samsung,pins = "gpg1-1";
1892 samsung,pin-function = <1>;
1893 samsung,pin-pud = <3>;
1894 samsung,pin-val = <1>;
1895 };
1896 #if 0 /*Should be removed: enable speaker amp on EVB board*/
1897 amp_sda: amp-sda {
1898 samsung,pins = "gpp2-2";
1899 samsung,pin-function = <3>;
1900 samsung,pin-pud = <3>;
1901 samsung,pin-drv = <0>;
1902 };
1903 amp_scl: amp-scl {
1904 samsung,pins = "gpp2-1";
1905 samsung,pin-function = <3>;
1906 samsung,pin-pud = <3>;
1907 samsung,pin-drv = <0>;
1908 };
1909 amp_ad1: amp-ad1 {
1910 samsung,pins = "gpp2-0";
1911 samsung,pin-function = <1>;
1912 samsung,pin-val = <0>;
1913 samsung,pin-pud = <1>;
1914 };
1915 amp_ad0: amp-ad0 {
1916 samsung,pins = "gpp2-3";
1917 samsung,pin-function = <1>;
1918 samsung,pin-val = <0>;
1919 samsung,pin-pud = <1>;
1920 };
1921 #endif
1922 };
1923
1924 &udc {
1925 status = "okay";
1926 };
1927
1928 &usbdrd_dwc3 {
1929 dr_mode = "otg";
1930 maximum-speed = "high-speed";
1931 };
1932
1933 &usbdrd_phy {
1934 status = "okay";
1935 usb3phy-isolation = <1>;
1936
1937 hs_tune_param = <&usb_hs_tune>;
1938 };
1939
1940 &usbdrd3_phy {
1941 status = "okay";
1942 usb3phy-isolation = <1>;
1943
1944 hs_tune_param = <&usb3_hs_tune>;
1945 ss_tune_param = <&usb3_ss_tune>;
1946 };
1947
1948 &serial_0 {
1949 status = "okay";
1950 };
1951
1952 &dsim_0 {
1953 lcd_info = <&nt36672a>;
1954 /* reset, lcd_bias_enp, lcd_bias_enn, lcd_bl_en*/
1955 gpios = <&gpg1 4 0x1>, <&gpg3 1 0x1>, <&gpg3 0 0x1>, <&gpg2 1 0x1>;
1956 };
1957
1958 /* USI_0_SHUB */
1959 &usi_0_shub {
1960 usi_v2_mode = "spi";
1961 status = "okay";
1962 };
1963
1964 /* USI_SHUB_0_I2C */
1965 &usi_0_shub_i2c {
1966 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1967 status = "disabled";
1968 };
1969
1970 /* USI_0_CMGP */
1971 &usi_0_cmgp {
1972 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1973 usi_v2_mode = "i2c";
1974 status = "okay";
1975 };
1976
1977 /* USI_0_CMGP_I2C */
1978 &usi_0_cmgp_i2c {
1979 usi_v2_mode = "i2c";
1980 status = "okay";
1981 };
1982
1983 /* USI_1_CMGP */
1984 &usi_1_cmgp {
1985 usi_v2_mode = "i2c";
1986 status = "okay";
1987 };
1988
1989 /* USI_1_CMGP_I2C */
1990 &usi_1_cmgp_i2c {
1991 usi_v2_mode = "i2c";
1992 status = "okay";
1993 };
1994
1995 /* USI_2_CMGP */
1996 &usi_2_cmgp {
1997 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1998 usi_v2_mode = "i2c";
1999 status = "okay";
2000 };
2001
2002 /* USI_2_CMGP_I2C */
2003 &usi_2_cmgp_i2c {
2004 usi_v2_mode = "i2c";
2005 status = "okay";
2006 };
2007
2008 /* USI_3_CMGP */
2009 &usi_3_cmgp {
2010 /* usi_v2_mode = "i2c" or "spi" or "uart" */
2011 status = "disabled";
2012 };
2013
2014 /* USI_3_CMGP_I2C */
2015 &usi_3_cmgp_i2c {
2016 /* usi_v2_mode = "i2c" or "spi" or "uart" */
2017 status = "disabled";
2018 };
2019
2020 /* USI_4_CMGP */
2021 &usi_4_cmgp {
2022 /* usi_v2_mode = "i2c" or "spi" or "uart" */
2023 status = "disabled";
2024 };
2025
2026 /* USI_4_CMGP_I2C */
2027 &usi_4_cmgp_i2c {
2028 /* usi_v2_mode = "i2c" or "spi" or "uart" */
2029 status = "disabled";
2030 };
2031
2032 /* USI_PERI_UART */
2033 &usi_peri_uart {
2034 usi_v2_mode = "uart";
2035 status = "okay";
2036 };
2037
2038 /* USI_PERI_CAMI2C_0 */
2039 &usi_peri_cami2c_0 {
2040 usi_v2_mode = "i2c";
2041 status = "okay";
2042 };
2043
2044 /* USI_PERI_CAMI2C_1 */
2045 &usi_peri_cami2c_1 {
2046 usi_v2_mode = "i2c";
2047 status = "okay";
2048 };
2049
2050 /* USI_PERI_CAMI2C_2 */
2051 &usi_peri_cami2c_2 {
2052 usi_v2_mode = "i2c";
2053 status = "okay";
2054 };
2055
2056 /* USI_PERI_CAMI2C_3 */
2057 &usi_peri_cami2c_3 {
2058 usi_v2_mode = "i2c";
2059 status = "okay";
2060 };
2061
2062 /* USI_PERI_SPI_0 */
2063 &usi_peri_spi_0 {
2064 usi_v2_mode = "spi";
2065 status = "okay";
2066 };
2067
2068 /* USI_PERI_SPI_1 */
2069 &usi_peri_spi_1 {
2070 usi_v2_mode = "spi";
2071 status = "okay";
2072 };
2073
2074 /* USI_PERI_USI_0 */
2075 &usi_peri_usi_0 {
2076 /* usi_v2_mode = "i2c" or "spi" or "uart" */
2077 status = "disabled";
2078 };
2079
2080 /* USI_PERI_USI_0_I2C */
2081 &usi_peri_usi_0_i2c {
2082 /* usi_v2_mode = "i2c" or "spi" or "uart" */
2083 status = "disabled";
2084 };
2085
2086 /* USI_PERI_SPI_2 */
2087 &usi_peri_spi_2 {
2088 usi_v2_mode = "spi";
2089 status = "okay";
2090 };
2091
2092 &spi_6 {
2093 status = "okay";
2094 pinctrl-names = "default";
2095 pinctrl-0 = <&spi6_bus &spi6_cs_func>;
2096 /*cs-gpios = <&gpp2 3 0>;*/
2097 /*gpp2[3]*/
2098 /*num-cs = <1>;*/
2099 #address-cells = <1>;
2100 #size-cells = <0>;
2101 cs35l41_left: cs35l41@0 {
2102 compatible = "cirrus,cs35l41";
2103 reg = <0x0>;
2104
2105 spi-max-frequency = <9600000>;
2106
2107 interrupts = <2 0 0>;
2108 interrupt-controller;
2109 interrupt-parent = <&gpa0>;
2110 reset-gpios = <&gpg3 3 0>;
2111 #sound-dai-cells = <1>;
2112
2113 VA-supply = <&l42_reg>;
2114 VP-supply = <&V_SYS>;
2115
2116 cirrus,boost-peak-milliamp = <4500>;
2117 cirrus,boost-ind-nanohenry = <1000>;
2118 cirrus,boost-cap-microfarad = <15>;
2119 cirrus,asp-sdout-hiz = <0x1>;
2120 cirrus,gpio-config2 {
2121 cirrus,gpio-src-select = <0x4>;
2122 cirrus,gpio-output-enable;
2123 };
2124
2125 controller-data {
2126 /*cs-gpio = <gpm8 0 0>*/
2127 /*cs-gpios = <&gpp2 3 0>;*/
2128 samsung,spi-feedback-delay = <1>;
2129 samsung,spi-chip-select-mode = <0>;
2130 };
2131 };
2132 };
2133
2134 #if 0
2135 &i2c@0 {
2136 status = "okay";
2137 compatible = "i2c-gpio";
2138
2139 pinctrl-names = "default";
2140 pinctrl-0 = <&amp_sda &amp_scl &amp_ad0 &amp_ad1>;
2141
2142 gpios = <&gpp2 2 0 /* sda */
2143 &gpp2 1 0 /* scl */
2144 >;
2145
2146 #address-cells = <1>;
2147 #size-cells = <0>;
2148
2149 cs35l41_left: cs35l41@40 {
2150 compatible = "cirrus,cs35l41";
2151 reg = <0x40>;
2152
2153 interrupts = <2 0 0>;
2154 interrupt-controller;
2155 interrupt-parent = <&gpa0>;
2156 reset-gpios = <&gpg3 3 0>;
2157 #sound-dai-cells = <1>;
2158
2159 VA-supply = <&l42_reg>;
2160 VP-supply = <&V_SYS>;
2161
2162 cirrus,boost-peak-milliamp = <4500>;
2163 cirrus,boost-ind-nanohenry = <1000>;
2164 cirrus,boost-cap-microfarad = <15>;
2165 cirrus,asp-sdout-hiz = <0x1>;
2166 cirrus,gpio-config2 {
2167 cirrus,gpio-src-select = <0x4>;
2168 cirrus,gpio-output-enable;
2169 };
2170 };
2171 };
2172 #endif
2173
2174 &spi_9 {
2175 pinctrl-names = "default";
2176 pinctrl-0 = <&spi9_bus &spi9_cs_func &codec_en>;
2177 status = "okay";
2178 #address-cells = <1>;
2179 #size-cells = <0>;
2180 cs47l35: cs47l35@0 {
2181 compatible = "cirrus,cs47l35";
2182 reg = <0x0>;
2183
2184 spi-max-frequency = <11000000>;
2185
2186 interrupts = <6 0 0>;
2187 interrupt-controller;
2188 #interrupt-cells = <2>;
2189 interrupt-parent = <&gpa0>;
2190 gpio-controller;
2191 #gpio-cells = <2>;
2192 #sound-dai-cells = <1>;
2193
2194 /*l42_reg shoulde be change after board fixed*/
2195 AVDD-supply = <&l42_reg>;
2196 DBVDD1-supply = <&l42_reg>;
2197 DBVDD2-supply = <&l42_reg>;
2198 CPVDD1-supply = <&l42_reg>;
2199 CPVDD2-supply = <&l44_reg>;
2200 DCVDD-supply = <&l44_reg>;
2201 SPKVDD-supply = <&V_SYS>;
2202
2203 reset-gpios = <&gpg3 2 0>;
2204
2205 cirrus,dmic-ref = <0 0 0>;
2206 cirrus,inmode = <
2207 0 0 0 0 /* IN1 */
2208 0 0 0 0 /* IN2 */
2209 >;
2210
2211 cirrus,gpsw = <1 0>;
2212
2213 pinctrl-names = "probe", "active";
2214 pinctrl-0 = <&codec_reset>;
2215 pinctrl-1 = <&codec_reset &cs47l35_defaults>;
2216
2217 madera_pinctrl: madera-pinctrl {
2218 compatible = "cirrus,madera-pinctrl";
2219 cs47l35_defaults: cs47l35-gpio-defaults {
2220 aif1 {
2221 groups = "aif1";
2222 function = "aif1";
2223 bias-bus-hold;
2224 };
2225
2226 aif2 {
2227 groups = "aif2";
2228 function = "aif2";
2229 bias-bus-hold;
2230 };
2231
2232 aif3 {
2233 groups = "aif3";
2234 function = "aif3";
2235 bias-bus-hold;
2236 };
2237
2238 gpio6 { /* Amp Clock */
2239 groups = "gpio6";
2240 function = "opclk";
2241 bias-pull-up;
2242 output-low;
2243 };
2244
2245 gpio5 { /* Mic Polarity Flip */
2246 groups = "gpio5";
2247 function = "io";
2248 };
2249 };
2250 };
2251
2252
2253 micvdd {
2254 regulator-min-microvolt = <3000000>;
2255 regulator-max-microvolt = <3000000>;
2256 };
2257
2258 MICBIAS1 {
2259 regulator-min-microvolt = <2800000>;
2260 regulator-max-microvolt = <2800000>;
2261 cirrus,ext-cap = <1>;
2262 };
2263 MICBIAS1A {
2264 regulator-active-discharge = <1>;
2265 };
2266 MICBIAS1B {
2267 regulator-active-discharge = <1>;
2268 };
2269
2270 MICBIAS2 {
2271 regulator-min-microvolt = <2800000>;
2272 regulator-max-microvolt = <2800000>;
2273 cirrus,ext-cap = <1>;
2274 };
2275
2276 MICBIAS2A {
2277 regulator-active-discharge = <1>;
2278 };
2279 MICBIAS2B {
2280 regulator-active-discharge = <1>;
2281 };
2282
2283 cirrus,accdet {
2284 #address-cells = <1>;
2285 #size-cells = <0>;
2286
2287 acc@1 {
2288 reg = <1>;
2289
2290 cirrus,micd-configs = <
2291 0 0 2 0 0
2292 >;
2293 cirrus,micd-bias-start-time = <8>;
2294 cirrus,micd-rate = <6>;
2295 /*cirrus,micd-pol-gpios = <&cs47l35 4 0>;*/
2296 cirrus,micd-detect-debounce-ms = <500>;
2297 /*cirrus,jd-use-jd2;*/
2298 /*cirrus,micd-clamp-mode = <0x8>;*/
2299 };
2300 };
2301
2302 controller-data {
2303 samsung,spi-feedback-delay = <1>;
2304 samsung,spi-chip-select-mode = <0>;
2305 };
2306 };
2307 };