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Revert "(CR) arm64: dts: Keep VCCQ power when S2R mode for Sandisk UFS"
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / arch / arm64 / boot / dts / exynos / exynos9609-robusta2_common.dtsi
1 /*
2 * SAMSUNG EXYNOS9610 board device tree source
3 *
4 * Copyright (c) 2017 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include "exynos9610_battery_data.dtsi"
13 #include <dt-bindings/clock/exynos9610.h>
14 #include "modem-ss360ap-sit-pdata.dtsi"
15 #include "exynos9610-display-lcd.dtsi"
16 #include "novatek-nt36xxx-i2c.dtsi"
17 #include "himax-hx83112a-i2c.dtsi"
18 #include "wing-sensor.dtsi"
19 #include "exynos9610-robusta2-motor.dtsi"
20 #include "exynos9610_gpio_config_macros.dtsi"
21 #include "carrier-channel-ids.dtsi"
22
23 / {
24 fragment@common {
25 target-path = "/";
26 __overlay__ {
27 #address-cells = <2>;
28 #size-cells = <1>;
29
30 fixed-rate-clocks {
31 oscclk {
32 compatible = "samsung,exynos9610-oscclk";
33 clock-frequency = <26000000>;
34 };
35 };
36
37 firmware {
38 android {
39 compatible = "android,firmware";
40 vbmeta {
41 compatible = "android,vbmeta";
42 parts = "vbmeta,boot,system,vendor,dtbo,oem";
43 };
44 fstab {
45 compatible = "android,fstab";
46 vendor {
47 compatible = "android,vendor";
48 dev = "/dev/block/platform/13520000.ufs/by-name/vendor";
49 type = "ext4";
50 mnt_flags = "ro";
51 fsmgr_flags = "wait,avb,slotselect";
52 };
53 oem {
54 compatible = "android,oem";
55 dev = "/dev/block/platform/13520000.ufs/by-name/oem";
56 type = "ext4";
57 mnt_flags = "ro,barrier=1,discard";
58 fsmgr_flags = "wait,avb,slotselect";
59 };
60 };
61 };
62 };
63
64 ifconn {
65 status = "okay";
66 compatible = "samsung,ifconn";
67 ifconn,usbpd = "s2mm005";
68 ifconn,muic = "s2mu106-muic";
69 };
70
71 /*Fingerprint start*/
72 et320: et320{
73 compatible = "egistec,et320";
74 status = "ok";
75 reg = <0>;
76 clocks = <&clock GATE_SPI_1_QCH>, <&clock SPI1>;
77 clock-names = "spi", "spi_busclk0";
78 pinctrl-names = "default";
79 pinctrl-0 = <&spi7_bus &spi7_cs_func>;
80 egistec,gpio_irq = <&gpa0 5 0>;
81 egistec,gpio_rst = <&gpa1 1 0>;
82 egistec,gpio_ldo3p3_en = <&gpg2 0 0>;
83 egistec,gpio_ldo1p8_en = <&gpg2 2 0>;
84 };
85 /*Fingerprint end*/
86
87 speedy@11a10000 {
88 status = "okay";
89 #address-cells = <1>;
90 #size-cells = <0>;
91 s2mpu09mfd@00 {
92 compatible = "samsung,s2mpu09mfd";
93 acpm-ipc-channel = <2>;
94 i2c-speedy-address;
95 s2mpu09,wakeup = "enabled";
96 s2mpu09,irq-gpio = <&gpa2 0 0>;
97 reg = <0x00>;
98 interrupts = <2 0 0>;
99 interrupt-parent = <&gpa2>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&pmic_irq &pm_wrsti>;
102 /* RTC: wtsr/smpl */
103 wtsr_en = "enabled"; /* enable */
104 smpl_en = "enabled"; /* enable */
105 wtsr_timer_val = <3>; /* 1000ms */
106 smpl_timer_val = <4>; /* 500ms */
107 check_jigon = <0>; /* do not check jigon */
108 /* RTC: If it's first boot, reset rtc to 1/1/2017 12:00:00(Sun) */
109 init_time,sec = <0>;
110 init_time,min = <0>;
111 init_time,hour = <12>;
112 init_time,mday = <1>;
113 init_time,mon = <0>;
114 init_time,year = <117>;
115 init_time,wday = <0>;
116
117 regulators {
118 b1_reg: BUCK1 {
119 regulator-name = "vdd_mif";
120 regulator-min-microvolt = <500000>;
121 regulator-max-microvolt = <1100000>;
122 regulator-always-on;
123 regulator-ramp-delay = <12000>;
124 regulator-initial-mode = <2>;
125 };
126
127 b2_reg: BUCK2 {
128 regulator-name = "vdd_cpucl1";
129 regulator-min-microvolt = <500000>;
130 regulator-max-microvolt = <1300000>;
131 regulator-always-on;
132 regulator-ramp-delay = <12000>;
133 regulator-initial-mode = <1>;
134 };
135
136 b3_reg: BUCK3 {
137 regulator-name = "vdd_cpucl0";
138 regulator-min-microvolt = <500000>;
139 regulator-max-microvolt = <1300000>;
140 regulator-always-on;
141 regulator-ramp-delay = <12000>;
142 regulator-initial-mode = <1>;
143 };
144
145 b4_reg: BUCK4{
146 regulator-name = "vdd_int";
147 regulator-min-microvolt = <500000>;
148 regulator-max-microvolt = <1100000>;
149 regulator-always-on;
150 regulator-ramp-delay = <12000>;
151 regulator-initial-mode = <2>;
152 };
153
154 b5_reg: BUCK5 {
155 regulator-name = "vdd_g3d";
156 regulator-min-microvolt = <500000>;
157 regulator-max-microvolt = <1200000>;
158 regulator-always-on;
159 regulator-ramp-delay = <12000>;
160 regulator-initial-mode = <2>;
161 };
162
163 b6_reg: BUCK6 {
164 regulator-name = "vdd_cam_vipx";
165 regulator-min-microvolt = <500000>;
166 regulator-max-microvolt = <1300000>;
167 regulator-always-on;
168 regulator-ramp-delay = <12000>;
169 regulator-initial-mode = <2>;
170 };
171
172 b7_reg: BUCK7 {
173 regulator-name = "vdd2_mem";
174 regulator-min-microvolt = <500000>;
175 regulator-max-microvolt = <1300000>;
176 regulator-always-on;
177 regulator-ramp-delay = <12000>;
178 regulator-initial-mode = <3>;
179 };
180
181 b8_reg: BUCK8 {
182 regulator-name = "vdd_lldo";
183 regulator-min-microvolt = <1200000>;
184 regulator-max-microvolt = <1500000>;
185 regulator-always-on;
186 regulator-ramp-delay = <12000>;
187 regulator-initial-mode = <3>;
188 };
189
190 b9_reg: BUCK9 {
191 regulator-name = "vdd_mldo";
192 regulator-min-microvolt = <1800000>;
193 regulator-max-microvolt = <2100000>;
194 regulator-always-on;
195 regulator-ramp-delay = <12000>;
196 regulator-initial-mode = <3>;
197 };
198
199 l1_reg: LDO1 {
200 regulator-name = "vdd_ldo1";
201 regulator-min-microvolt = <700000>;
202 regulator-max-microvolt = <1300000>;
203 regulator-always-on;
204 regulator-ramp-delay = <12000>;
205 regulator-initial-mode = <3>;
206 };
207
208 l2_reg: LDO2 {
209 regulator-name = "vqmmc";
210 regulator-min-microvolt = <1800000>;
211 regulator-max-microvolt = <3375000>;
212 regulator-ramp-delay = <12000>;
213 };
214
215 l3_reg: LDO3 {
216 regulator-name = "vdd_ldo3";
217 regulator-min-microvolt = <800000>;
218 regulator-max-microvolt = <1950000>;
219 regulator-always-on;
220 regulator-ramp-delay = <12000>;
221 regulator-initial-mode = <3>;
222 };
223
224 l4_reg: LDO4 {
225 regulator-name = "vdd_ldo4";
226 regulator-min-microvolt = <500000>;
227 regulator-max-microvolt = <1100000>;
228 regulator-always-on;
229 regulator-ramp-delay = <12000>;
230 regulator-initial-mode = <1>;
231 };
232
233 l5_reg: LDO5 {
234 regulator-name = "vdd_ldo5";
235 regulator-min-microvolt = <800000>;
236 regulator-max-microvolt = <1300000>;
237 regulator-always-on;
238 regulator-ramp-delay = <12000>;
239 regulator-initial-mode = <1>;
240 };
241
242 l6_reg: LDO6 {
243 regulator-name = "vdd_ldo6";
244 regulator-min-microvolt = <800000>;
245 regulator-max-microvolt = <1300000>;
246 regulator-always-on;
247 regulator-ramp-delay = <12000>;
248 regulator-initial-mode = <1>;
249 };
250
251 l7_reg: LDO7 {
252 regulator-name = "vdd_ldo7";
253 regulator-min-microvolt = <800000>;
254 regulator-max-microvolt = <1950000>;
255 regulator-always-on;
256 regulator-ramp-delay = <12000>;
257 regulator-initial-mode = <1>;
258 };
259
260 l8_reg: LDO8 {
261 regulator-name = "vdd_ldo8";
262 regulator-min-microvolt = <500000>;
263 regulator-max-microvolt = <1300000>;
264 regulator-always-on;
265 regulator-ramp-delay = <12000>;
266 regulator-initial-mode = <1>;
267 };
268
269 l9_reg: LDO9 {
270 regulator-name = "vdd_ldo9";
271 regulator-min-microvolt = <500000>;
272 regulator-max-microvolt = <1300000>;
273 regulator-always-on;
274 regulator-ramp-delay = <12000>;
275 regulator-initial-mode = <1>;
276 };
277
278 l10_reg: LDO10 {
279 regulator-name = "vdd_ldo10";
280 regulator-min-microvolt = <500000>;
281 regulator-max-microvolt = <1300000>;
282 regulator-always-on;
283 regulator-ramp-delay = <12000>;
284 regulator-initial-mode = <1>;
285 };
286
287 l11_reg: LDO11 {
288 regulator-name = "vdd_ldo11";
289 regulator-min-microvolt = <500000>;
290 regulator-max-microvolt = <1300000>;
291 regulator-always-on;
292 regulator-ramp-delay = <12000>;
293 regulator-initial-mode = <1>;
294 };
295
296 l12_reg: LDO12 {
297 regulator-name = "vdd_ldo12";
298 regulator-min-microvolt = <800000>;
299 regulator-max-microvolt = <1300000>;
300 regulator-always-on;
301 regulator-ramp-delay = <12000>;
302 regulator-initial-mode = <1>;
303 };
304
305 l13_reg: LDO13 {
306 regulator-name = "vdd_ldo13";
307 regulator-min-microvolt = <800000>;
308 regulator-max-microvolt = <1950000>;
309 regulator-always-on;
310 regulator-ramp-delay = <12000>;
311 regulator-initial-mode = <1>;
312 };
313
314 l14_reg: LDO14 {
315 regulator-name = "vdd_ldo14";
316 regulator-min-microvolt = <1800000>;
317 regulator-max-microvolt = <3375000>;
318 regulator-always-on;
319 regulator-ramp-delay = <12000>;
320 regulator-initial-mode = <1>;
321 };
322
323 l33_reg: LDO33 {
324 regulator-name = "vdd_ldo33";
325 regulator-min-microvolt = <800000>;
326 regulator-max-microvolt = <1950000>;
327 regulator-ramp-delay = <12000>;
328 };
329
330 l34_reg: LDO34 {
331 regulator-name = "vdd_ldo34";
332 regulator-min-microvolt = <1800000>;
333 regulator-max-microvolt = <3375000>;
334 regulator-ramp-delay = <12000>;
335 };
336
337 l35_reg: LDO35 {
338 regulator-name = "vmmc";
339 regulator-min-microvolt = <1800000>;
340 regulator-max-microvolt = <3375000>;
341 regulator-ramp-delay = <12000>;
342 };
343
344 l36_reg: LDO36 {
345 regulator-name = "vdd_ldo36";
346 regulator-min-microvolt = <500000>;
347 regulator-max-microvolt = <1300000>;
348 regulator-always-on;
349 regulator-ramp-delay = <12000>;
350 regulator-initial-mode = <1>;
351 };
352
353 l37_reg: LDO37 {
354 regulator-name = "vdd_ldo37";
355 regulator-min-microvolt = <3300000>;
356 regulator-max-microvolt = <3300000>;
357 regulator-ramp-delay = <12000>;
358 /* regulator-always-on; */
359 regulator-initial-mode = <3>;
360 };
361
362 l38_reg: LDO38 {
363 regulator-name = "VLDO38_PMIC_RCAM_AFVCC_2P8";
364 regulator-min-microvolt = <2800000>;
365 regulator-max-microvolt = <2800000>;
366 regulator-ramp-delay = <12000>;
367 };
368
369 l39_reg: LDO39 {
370 regulator-name = "vdd_ldo39";
371 regulator-min-microvolt = <800000>;
372 regulator-max-microvolt = <1950000>;
373 regulator-ramp-delay = <12000>;
374 regulator-always-on;
375 };
376
377 l40_reg: LDO40 {
378 regulator-name = "vdd_ldo40";
379 regulator-min-microvolt = <3000000>;
380 regulator-max-microvolt = <3000000>;
381 regulator-ramp-delay = <12000>;
382 regulator-initial-mode = <3>;
383 regulator-always-on;
384 };
385
386 l41_reg: LDO41 {
387 regulator-name = "VLDO41_PMIC_FCAM_AVDD_2P8";
388 regulator-min-microvolt = <2800000>;
389 regulator-max-microvolt = <2800000>;
390 regulator-ramp-delay = <12000>;
391 };
392
393 l42_reg: LDO42 {
394 regulator-name = "vdd_ldo42";
395 regulator-min-microvolt = <800000>;
396 regulator-max-microvolt = <1950000>;
397 regulator-ramp-delay = <12000>;
398 regulator-always-on;
399 };
400
401 l43_reg: LDO43 {
402 regulator-name = "vdd_ldo43";
403 regulator-min-microvolt = <500000>;
404 regulator-max-microvolt = <1300000>;
405 regulator-always-on;
406 regulator-ramp-delay = <12000>;
407 regulator-initial-mode = <1>;
408 };
409
410 l44_reg: LDO44 {
411 regulator-name = "VLDO44_PMIC_DCAM_DVDD_1P2";
412 regulator-min-microvolt = <1200000>;
413 regulator-max-microvolt = <1200000>;
414 regulator-ramp-delay = <12000>;
415 };
416 };
417 };
418 };
419
420
421 exynos_rgt {
422 compatible = "samsung,exynos-rgt";
423 };
424
425 mailbox_cp: mcu_ipc@11920000 {
426 compatible = "samsung,exynos-shd-ipc-mailbox";
427 reg = <0x0 0x11920000 0x180>;
428 mcu,name = "mcu_ipc_cp";
429 mcu,id = <0>;
430 interrupts = <0 40 0 >;
431 };
432
433 mailbox_gnss: mcu_ipc@11A00000 {
434 compatible = "samsung,exynos-shd-ipc-mailbox";
435 reg = <0x0 0x11A00000 0x180>;
436 mcu,name = "mcu_ipc_gnss";
437 mcu,id = <1>;
438 interrupts = <0 43 0>; /* INTREQ__MAILBOX_GNSS2AP */
439 };
440
441 gnss_pdata {
442 status = "okay";
443
444 compatible = "samsung,gnss_shdmem_if";
445 shmem,name = "KEPLER";
446 shmem,device_node_name = "gnss_ipc";
447
448 /* INTREQ__ALIVE_GNSS_ACTIVE, INTREQ__GNSS2AP_WDOG_RESET, INTREQ__GNSS2AP_WAKEUP, INTREQ__GNSS2AP */
449 interrupts = <0 27 0>, <0 81 0>, <0 80 0>, <0 79 0>;
450 interrupt-names = "ACTIVE", "WATCHDOG", "WAKEUP", "REQ_INIT";
451
452 memory-region = <&gnss_reserved>;
453 mbox_info = <&mailbox_gnss>;
454
455 mbx,int_ap2gnss_bcmd = <0>;
456 mbx,int_ap2gnss_req_fault_info = <1>;
457 mbx,int_ap2gnss_ipc_msg = <2>;
458 mbx,int_ap2gnss_ack_wake_set = <3>;
459 mbx,int_ap2gnss_ack_wake_clr = <4>;
460
461 mbx,irq_gnss2ap_bcmd = <0>;
462 mbx,irq_gnss2ap_rsp_fault_info = <1>;
463 mbx,irq_gnss2ap_ipc_msg = <2>;
464 mbx,irq_gnss2ap_req_wake_clr = <4>;
465
466 mbx,reg_bcmd_ctrl = <0>, <1>, <2>, <3>;
467
468 reg_rx_ipc_msg = <1 5>;
469 reg_tx_ipc_msg = <1 4>;
470 reg_rx_head = <1 3>;
471 reg_rx_tail = <1 2>;
472 reg_tx_head = <1 1>;
473 reg_tx_tail = <1 0>;
474 fault_info = <1 0x200000 0x180000>;
475
476 shmem,ipc_offset = <0x380000>;
477 shmem,ipc_size = <0x80000>;
478 shmem,ipc_reg_cnt = <32>;
479 };
480
481 gpio_keys {
482 status = "okay";
483 compatible = "gpio-keys";
484 #address-cells = <1>;
485 #size-cells = <0>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&key_voldown &key_volup &key_power>;
488 button@1 {
489 label = "gpio-keys: KEY_VOLUMEDOWN";
490 linux,code = <114>;
491 gpios = <&gpa1 6 0xf>;
492 };
493 button@2 {
494 label = "gpio-keys: KEY_VOLUMEUP";
495 linux,code = <115>;
496 gpios = <&gpa1 5 0xf>;
497 };
498 button@3 {
499 label = "gpio-keys: KEY_POWER";
500 linux,code = <116>;
501 gpios = <&gpa1 7 0xf>;
502 gpio-key,wakeup = <1>;
503 };
504 };
505
506 dwmmc2@13550000 {
507 status = "okay";
508 num-slots = <1>;
509 supports-4bit;
510 supports-cmd23;
511 supports-highspeed;
512 sd-uhs-sdr50;
513 sd-uhs-sdr104;
514 card-detect-invert;
515 card-detect-gpio;
516 bypass-for-allpass;
517 card-init-hwacg-ctrl;
518 skip-init-mmc-scan;
519 skip-init-no-tray;
520 pm-ignore-notify;
521 qos-dvfs-level = <100000>;
522 fifo-depth = <0x40>;
523 desc-size = <4>;
524 card-detect-delay = <200>;
525 data-timeout = <200>;
526 hto-timeout = <80>;
527 samsung,dw-mshc-ciu-div = <3>;
528 clock-frequency = <800000000>;
529 samsung,dw-mshc-sdr-timing = <3 0 2 0>;
530 samsung,dw-mshc-ddr-timing = <3 0 2 1>;
531 samsung,dw-mshc-sdr50-timing = <3 0 4 2>;
532 samsung,dw-mshc-sdr104-timing = <3 0 3 0>;
533
534 num-ref-clks = <9>;
535 ciu_clkin = <25 50 50 25 50 100 200 50 50>;
536
537 /* Swapping clock drive strength */
538 clk-drive-number = <4>;
539 pinctrl-names = "default",
540 "fast-slew-rate-1x",
541 "fast-slew-rate-2x",
542 "fast-slew-rate-3x",
543 "fast-slew-rate-4x";
544 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4 &dwmmc2_cd_ext_irq>;
545 pinctrl-1 = <&sd2_clk_fast_slew_rate_1x>;
546 pinctrl-2 = <&sd2_clk_fast_slew_rate_2x>;
547 pinctrl-3 = <&sd2_clk_fast_slew_rate_3x>;
548 pinctrl-4 = <&sd2_clk_fast_slew_rate_4x>;
549
550 card-detect = <&gpa0 7 0xf>;
551 #address-cells = <1>;
552 #size-cells = <0>;
553 slot@0 {
554 reg = <0>;
555 bus-width = <4>;
556 disable-wp;
557 };
558 };
559
560 usb_notifier {
561 compatible = "samsung,usb-notifier";
562 udc = <&udc>;
563 };
564
565 usb_hs_tune:usb_hs_tune {
566 hs_tune_cnt = <12>;
567
568 /* value = <device host> */
569 hs_tune1 {
570 tune_name = "tx_vref";
571 tune_value = <0xf 0xf>;
572 };
573
574 hs_tune2 {
575 tune_name = "tx_pre_emp";
576 tune_value = <0x3 0x3>;
577 };
578
579 hs_tune3 {
580 tune_name = "tx_pre_emp_plus";
581 tune_value = <0x0 0x0>;
582 };
583
584 hs_tune4 {
585 tune_name = "tx_res";
586 tune_value = <0x3 0x3>;
587 };
588
589 hs_tune5 {
590 tune_name = "tx_rise";
591 tune_value = <0x3 0x3>;
592 };
593
594 hs_tune6 {
595 tune_name = "tx_hsxv";
596 tune_value = <0x3 0x3>;
597 };
598
599 hs_tune7 {
600 tune_name = "tx_fsls";
601 tune_value = <0x3 0x3>;
602 };
603
604 hs_tune8 {
605 tune_name = "rx_sqrx";
606 tune_value = <0x7 0x7>;
607 };
608
609 hs_tune9 {
610 tune_name = "compdis";
611 tune_value = <0x7 0x7>;
612 };
613
614 hs_tune10 {
615 tune_name = "otg";
616 tune_value = <0x2 0x2>;
617 };
618
619 hs_tune11 {
620 /* true : 1, false: 0 */
621 /* <enable_user_imp user_imp_value> */
622 tune_name = "enable_user_imp";
623 tune_value = <0x0 0x0>;
624 };
625
626 hs_tune12 {
627 /* PHY clk : 1 , FREE clk : 0 */
628 tune_name = "is_phyclock";
629 tune_value = <0x1 0x1>;
630 };
631 };
632
633 usb3_ss_tune:ss_tune {
634 ss_tune_cnt = <15>;
635
636 /* value = <device host> */
637 ss_tune1 {
638 tune_name = "tx0_term_offset";
639 tune_value = <0x0 0x0>;
640 };
641
642 ss_tune2 {
643 tune_name = "pcs_tx_swing_full";
644 tune_value = <0x7f 0x7f>;
645 };
646
647 ss_tune3 {
648 tune_name = "pcs_tx_deemph_6db";
649 tune_value = <0x1c 0x1c>;
650 };
651
652 ss_tune4 {
653 tune_name = "pcs_tx_deemph_3p5db";
654 tune_value = <0x1c 0x1c>;
655 };
656
657 ss_tune5 {
658 tune_name = "tx_vboost_lvl_sstx";
659 tune_value = <0x7 0x7>;
660 };
661
662 ss_tune6 {
663 tune_name = "tx_vboost_lvl";
664 tune_value = <0x4 0x4>;
665 };
666
667 ss_tune7 {
668 tune_name = "los_level";
669 tune_value = <0x9 0x9>;
670 };
671
672 ss_tune8 {
673 tune_name = "los_bias";
674 tune_value = <0x5 0x5>;
675 };
676
677 ss_tune9 {
678 tune_name = "pcs_rx_los_mask_val";
679 tune_value = <0x104 0x104>;
680 };
681
682 ss_tune10 {
683 tune_name = "tx_eye_height_cntl_en";
684 tune_value = <0x1 0x1>;
685 };
686
687 ss_tune11 {
688 tune_name = "pipe_tx_deemph_update_delay";
689 tune_value = <0x2 0x2>;
690 };
691
692 ss_tune12 {
693 tune_name = "pcs_tx_swing_full_sstx";
694 tune_value = <0x7f 0x7f>;
695 };
696 ss_tune13 {
697 tune_name = "rx_eq_fix_val";
698 tune_value = <0x2 0x2>;
699 };
700
701 ss_tune14 {
702 tune_name = "rx_decode_mode";
703 tune_value = <0x1 0x1>;
704 };
705
706 ss_tune15 {
707 tune_name = "decrese_ss_tx_imp";
708 tune_value = <0x1 0x1>;
709 };
710 };
711
712 usb3_hs_tune:usb3_hs_tune {
713 hs_tune_cnt = <10>;
714
715 /* value = <device host> */
716 hs_tune1 {
717 tune_name = "tx_pre_emp";
718 tune_value = <0x3 0x3>;
719 };
720
721 hs_tune2 {
722 tune_name = "tx_pre_emp_plus";
723 tune_value = <0x0 0x0>;
724 };
725
726 hs_tune3 {
727 tune_name = "tx_vref";
728 tune_value = <0x7 0x7>;
729 };
730
731 hs_tune4 {
732 tune_name = "rx_sqrx";
733 tune_value = <0x7 0x7>;
734 };
735
736 hs_tune5 {
737 tune_name = "tx_rise";
738 tune_value = <0x3 0x3>;
739 };
740
741 hs_tune6 {
742 tune_name = "compdis";
743 tune_value = <0x7 0x7>;
744 };
745
746 hs_tune7 {
747 tune_name = "tx_hsxv";
748 tune_value = <0x3 0x3>;
749 };
750
751 hs_tune8 {
752 tune_name = "tx_fsls";
753 tune_value = <0x3 0x3>;
754 };
755
756 hs_tune9 {
757 tune_name = "tx_res";
758 tune_value = <0x3 0x3>;
759 };
760
761 hs_tune10 {
762 tune_name = "utim_clk";
763 tune_value = <0x1 0x1>;
764 };
765 };
766
767 /* Secure RPMB */
768 ufs-srpmb {
769 compatible = "samsung,ufs-srpmb";
770 interrupts = <0 460 0>;
771 };
772
773 V_SYS: fixedregulator@0 {
774 compatible = "regulator-fixed";
775 regulator-name = "V_SYS";
776 regulator-min-microvolt = <4200000>;
777 regulator-max-microvolt = <4200000>;
778 regulator-boot-on;
779 regulator-always-on;
780 };
781
782
783 dummy_audio_codec: audio_codec_dummy {
784 status = "okay";
785 compatible = "snd-soc-dummy";
786 };
787
788 dummy_audio_cpu: audio_cpu_dummy {
789 compatible = "samsung,dummy-cpu";
790 status = "okay";
791 };
792
793 sound {
794 status = "okay";
795 compatible = "samsung,exynos9610-madera";
796
797 clock-names = "xclkout";
798 clocks = <&clock OSC_AUD>;
799 pinctrl-names = "default";
800 pinctrl-0 = <&xclkout0 &spk_id>;
801
802 cirrus,sysclk = <1 4 98304000>;
803 cirrus,dspclk = <8 4 147456000>;
804 cirrus,fll1-refclk = <1 0 26000000 98304000>;
805
806 cirrus,opclk = <3 0 12288000>;
807
808 gpios = <&gpm25 0 0>;
809
810 samsung,routing =
811 "HEADSETMIC", "MICBIAS1B",
812 "IN1BR", "HEADSETMIC",
813 "DMIC1", "MICBIAS2A",
814 "IN1AL", "DMIC1",
815 "DMIC2", "MICBIAS2A",
816 "IN2L", "DMIC2",
817 "DMIC3", "MICBIAS2B",
818 "IN2R", "DMIC3",
819 "RECEIVER", "EPOUTN",
820 "RECEIVER", "EPOUTP",
821 "HEADPHONE", "HPOUTL",
822 "HEADPHONE", "HPOUTR",
823 "AIF2 Playback", "OPCLK",
824 "AIF2 Capture", "OPCLK",
825 "VOUTPUT", "ABOX UAIF0 Playback",
826 "SPEAKER", "Left SPK",
827 "VOUTPUTCALL", "ABOX SIFS0 Playback",
828 "ABOX SIFS0 Capture", "VINPUTCALL";
829
830 samsung,codec = <&abox &abox_uaif_0 &abox_uaif_1 &abox_uaif_2
831 &abox_uaif_4 &abox_dsif &abox_spdy &cs35l41_left>;
832 samsung,prefix = "ABOX", "ABOX", "ABOX", "ABOX",
833 "ABOX", "ABOX", "ABOX", "SPK";
834 samsung,aux = <&abox_effect &abox_bt>;
835
836 rdma@0 {
837 cpu {
838 sound-dai = <&abox 0>;
839 };
840 platform {
841 sound-dai = <&abox_rdma_0>;
842 };
843 codec {
844 sound-dai = <&dummy_audio_codec>;
845 };
846 };
847 rdma@1 {
848 cpu {
849 sound-dai = <&abox 1>;
850 };
851 platform {
852 sound-dai = <&abox_rdma_1>;
853 };
854 codec {
855 sound-dai = <&dummy_audio_codec>;
856 };
857 };
858 rdma@2 {
859 cpu {
860 sound-dai = <&abox 2>;
861 };
862 platform {
863 sound-dai = <&abox_rdma_2>;
864 };
865 codec {
866 sound-dai = <&dummy_audio_codec>;
867 };
868 };
869 rdma@3 {
870 cpu {
871 sound-dai = <&abox 3>;
872 };
873 platform {
874 sound-dai = <&abox_rdma_3>;
875 };
876 codec {
877 sound-dai = <&dummy_audio_codec>;
878 };
879 };
880 rdma@4 {
881 cpu {
882 sound-dai = <&abox 4>;
883 };
884 platform {
885 sound-dai = <&abox_rdma_4>;
886 };
887 codec {
888 sound-dai = <&dummy_audio_codec>;
889 };
890 };
891 rdma@5 {
892 cpu {
893 sound-dai = <&abox 5>;
894 };
895 platform {
896 sound-dai = <&abox_rdma_5>;
897 };
898 codec {
899 sound-dai = <&dummy_audio_codec>;
900 };
901 };
902 rdma@6 {
903 cpu {
904 sound-dai = <&abox 6>;
905 };
906 platform {
907 sound-dai = <&abox_rdma_6>;
908 };
909 codec {
910 sound-dai = <&dummy_audio_codec>;
911 };
912 };
913 rdma@7 {
914 cpu {
915 sound-dai = <&abox 7>;
916 };
917 platform {
918 sound-dai = <&abox_rdma_7>;
919 };
920 codec {
921 sound-dai = <&dummy_audio_codec>;
922 };
923 };
924 wdma@0 {
925 cpu {
926 sound-dai = <&abox 8>;
927 };
928 platform {
929 sound-dai = <&abox_wdma_0>;
930 };
931 codec {
932 sound-dai = <&dummy_audio_codec>;
933 };
934 };
935 wdma@1 {
936 cpu {
937 sound-dai = <&abox 9>;
938 };
939 platform {
940 sound-dai = <&abox_wdma_1>;
941 };
942 codec {
943 sound-dai = <&dummy_audio_codec>;
944 };
945 };
946 wdma@2 {
947 cpu {
948 sound-dai = <&abox 10>;
949 };
950 platform {
951 sound-dai = <&abox_wdma_2>;
952 };
953 codec {
954 sound-dai = <&dummy_audio_codec>;
955 };
956 };
957 wdma@3 {
958 cpu {
959 sound-dai = <&abox 11>;
960 };
961 platform {
962 sound-dai = <&abox_wdma_3>;
963 };
964 codec {
965 sound-dai = <&dummy_audio_codec>;
966 };
967 };
968 wdma@4 {
969 cpu {
970 sound-dai = <&abox 12>;
971 };
972 platform {
973 sound-dai = <&abox_wdma_4>;
974 };
975 codec {
976 sound-dai = <&dummy_audio_codec>;
977 };
978 };
979 /** ToDo: enable dp_audio link after enabling DP Audio
980 * dp_audio@0 {
981 * cpu {
982 * sound-dai = <&dummy_audio_cpu>;
983 * };
984 * codec {
985 * sound-dai = <&dummy_audio_codec>;
986 * };
987 * };
988 */
989 uaif@0 {
990 format = "i2s";
991 cpu {
992 sound-dai = <&abox_uaif_0>;
993 };
994 codec {
995 sound-dai = <&cs47l35 0>;
996 };
997 };
998 uaif@1 {
999 format = "i2s";
1000 cpu {
1001 sound-dai = <&abox_uaif_1>;
1002 };
1003 codec {
1004 sound-dai = <&dummy_audio_codec>;
1005 };
1006 };
1007 uaif@2 {
1008 format = "i2s";
1009 cpu {
1010 sound-dai = <&abox_uaif_2>;
1011 };
1012 codec {
1013 sound-dai = <&cs47l35 2>;
1014 };
1015 };
1016 uaif@4 {
1017 format = "i2s";
1018 bitclock-master;
1019 frame-master;
1020 cpu {
1021 sound-dai = <&abox_uaif_4>;
1022 };
1023 codec {
1024 sound-dai = <&dummy_audio_codec>;
1025 };
1026 };
1027 dsif@0 {
1028 format = "pdm";
1029 cpu {
1030 sound-dai = <&abox_dsif>;
1031 };
1032 codec {
1033 sound-dai = <&dummy_audio_codec>;
1034 };
1035 };
1036 spdy@0 {
1037 cpu {
1038 sound-dai = <&abox_spdy>;
1039 };
1040 codec {
1041 sound-dai = <&dummy_audio_codec>;
1042 };
1043 };
1044 sifs0@0 {
1045 cpu {
1046 sound-dai = <&abox 13>;
1047 };
1048 codec {
1049 sound-dai = <&dummy_audio_codec>;
1050 };
1051 };
1052 sifs1@0 {
1053 cpu {
1054 sound-dai = <&abox 14>;
1055 };
1056 codec {
1057 sound-dai = <&dummy_audio_codec>;
1058 };
1059 };
1060 sifs2@0 {
1061 cpu {
1062 sound-dai = <&abox 15>;
1063 };
1064 codec {
1065 sound-dai = <&dummy_audio_codec>;
1066 };
1067 };
1068
1069 codec-left-amp@0 {
1070 format = "i2s";
1071
1072 cpu {
1073 sound-dai = <&cs47l35 1>;
1074 };
1075 codec {
1076 sound-dai = <&cs35l41_left 0>;
1077 };
1078 };
1079
1080 cpu-dsp-voice-control@0 {
1081 cpu {
1082 sound-dai = <&cs47l35 3>;
1083 };
1084 codec {
1085 sound-dai = <&dummy_audio_codec>;
1086 };
1087 };
1088
1089 cpu-dsp-trace@0 {
1090 cpu {
1091 sound-dai = <&cs47l35 4>;
1092 };
1093 codec {
1094 sound-dai = <&dummy_audio_codec>;
1095 };
1096 };
1097
1098 cpu-dsp2-text@0 {
1099 cpu {
1100 sound-dai = <&cs47l35 5>;
1101 };
1102 codec {
1103 sound-dai = <&dummy_audio_codec>;
1104 };
1105 };
1106
1107 cpu-dsp3-text@0 {
1108 cpu {
1109 sound-dai = <&cs47l35 6>;
1110 };
1111 codec {
1112 sound-dai = <&dummy_audio_codec>;
1113 };
1114 };
1115
1116 cpu-dsp1-text@0 {
1117 cpu {
1118 sound-dai = <&cs47l35 7>;
1119 };
1120 codec {
1121 sound-dai = <&dummy_audio_codec>;
1122 };
1123 };
1124 };
1125
1126 sleep_gpio {
1127 compatible = "samsung,exynos-sleepgpio";
1128 pinctrl-names = "default", "sleep";
1129 pinctrl-0 = <&sleep_top &sleep_fsys &sleep_shub &normal_alive &normal_cmgp>;
1130 pinctrl-1 = <&sleep_top &sleep_fsys &sleep_shub &sleep_alive>;
1131 };
1132
1133 exynos-bcmdbg {
1134 initial_run_bcm_ip = <0>, <1>, <2>, <3>, <4>, <6>, <7>, <8>, <9>, <10>,
1135 <11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>, <20>,
1136 <21>, <22>, <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>;
1137 };
1138 }; /* end of __overlay__ */
1139 }; /* end of fragment */
1140 }; /* end of root */
1141
1142 &i2c_0 {
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1145 status = "okay";
1146 s2mu106-fuelgauge@3B {
1147 compatible = "samsung,s2mu106-fuelgauge";
1148 reg = <0x3B>;
1149 pinctrl-names = "default";
1150 pinctrl-0 = <&fuel_irq>;
1151 fuelgauge,fuel_int = <&gpa2 3 0>;
1152 fuelgauge,fuel_alert_vol = <3400>;
1153 fuelgauge,fuel_alert_soc = <1>;
1154 fuelgauge,type_str = "SDI";
1155 fuelgauge,model_type = <1>;
1156 };
1157
1158 usbpd-s2mu106@3C {
1159 compatible = "sec-usbpd,i2c";
1160 reg = <0x3C>;
1161 pinctrl-names = "default";
1162 pinctrl-0 = <&usbpd_irq>;
1163 usbpd,usbpd_int = <&gpa2 2 0>;
1164
1165 pdic-manager {
1166 /* sink */
1167 pdic,max_power = <5000>;
1168 pdic,op_power = <2500>;
1169 pdic,max_voltage = <6000>;
1170 pdic,max_current = <2000>;
1171 pdic,min_current = <500>;
1172
1173 pdic,giveback = <0>;
1174 pdic,usb_com_capable = <1>;
1175 pdic,no_usb_suspend = <1>;
1176
1177 /* source */
1178 source,max_voltage = <5000>;
1179 source,min_voltage = <4000>;
1180 source,max_power = <2500>;
1181
1182 /* sink cap */
1183 sink,capable_max_voltage = <5000>;
1184 };
1185 };
1186 };
1187
1188 &i2c_1 {
1189 #address-cells = <1>;
1190 #size-cells = <0>;
1191 status = "okay";
1192 s2mu106@3d {
1193 compatible = "samsung,s2mu106mfd";
1194 reg = <0x3d>;
1195 pinctrl-names = "default";
1196 pinctrl-0 = <&if_pmic_irq>;
1197 s2mu106,irq-gpio = <&gpa2 1 0>;
1198 s2mu106,wakeup;
1199
1200 muic {
1201 status = "okay";
1202 muic,uart_addr = "11850000.pinctrl";
1203 muic,uart_rxd = "gpq0-3";
1204 muic,uart_txd = "gpq0-4";
1205 };
1206 };
1207
1208 s2mu106-haptic {
1209 status = "okay";
1210 haptic,pwm_id = <1>;
1211 haptic,operation_mode = <2>; /* 0 : ERM_I2C, 1 : ERM_GPIO, 2 : LRA */
1212 haptic,hbst_en;
1213 haptic,hbst_automode;
1214 haptic,boost_level = <5000>;
1215 };
1216
1217 s2mcs02-charger@41 {
1218 compatible = "samsung,s2mcs02-charger";
1219 reg = <0x41>;
1220 default-clk = <100000000>;
1221 };
1222
1223 flash_led {
1224 /* Change here if you want to use FLED_EN pin
1225 fled-en1-gpio = <&gpg1 2 0>;
1226 fled-en2-gpio = <&gpg1 2 0>;
1227 fled-en3-gpio = <&gpg1 2 0>;
1228 fled-en4-gpio = <&gpg1 2 0>;
1229 */
1230 status = "okay";
1231 default_current = <50>;
1232 max_current = <200>;
1233 default_timer = <0>;
1234
1235 s2mu106-channel1 {
1236 id = <0>;
1237 /*
1238 current = <100>;
1239 timer = <200>;
1240 */
1241 };
1242
1243 s2mu106-channel2 {
1244 id = <1>;
1245 /*
1246 current = <100>;
1247 timer = <200>;
1248 */
1249 };
1250
1251 s2mu106-channel3 {
1252 id = <2>;
1253 /*
1254 current = <100>;
1255 timer = <200>;
1256 */
1257 };
1258 };
1259
1260 s2mu106-charger {
1261 status = "okay";
1262 battery,charger_name = "s2mu106-charger";
1263 battery,chg_gpio_en = <0>;
1264 battery,chg_polarity_en = <0>;
1265 battery,chg_gpio_status = <0>;
1266 battery,chg_polarity_status = <0>;
1267 battery,chg_float_voltage = <4350>;
1268 battery,chg_recharge_vcell = <4250>;
1269 battery,chg_full_vcell = <4300>;
1270 battery,full_check_type = <2>;
1271 battery,full_check_type_2nd = <2>;
1272 battery,input_current_limit = <
1273 500 450 500 1200 500 1200 1200 1000 1000 1000
1274 1000 500 500 1200 1000 500 450>;
1275 battery,fast_charging_current = <
1276 500 450 500 1200 500 1200 1200 1000 1000 1000
1277 1000 500 500 1200 1000 500 450>;
1278 battery,full_check_current_1st = <
1279 300 0 300 300 300 300 300 300 300 300
1280 300 300 300 300 300 300 0>;
1281 battery,full_check_current_2nd = <
1282 100 0 100 100 100 100 100 100 100 100
1283 100 100 100 100 100 100 0>;
1284 };
1285 };
1286
1287 &exynos_adc {
1288 status = "okay";
1289 cpu_thermistor {
1290 compatible = "murata,ncp03wf104";
1291 status = "okay";
1292 pullup-uv = <1800000>;
1293 pullup-ohm = <100000>;
1294 pulldown-ohm = <0>;
1295 io-channels = <&exynos_adc 0>;
1296 io-channel-names = "cpu_therm";
1297 };
1298 battery_thermistor {
1299 compatible = "murata,ncp15xh103";
1300 status = "okay";
1301 pullup-uv = <1800000>;
1302 pullup-ohm = <100000>;
1303 pulldown-ohm = <0>;
1304 io-channels = <&exynos_adc 1>;
1305 io-channel-names = "bat_therm";
1306 };
1307 pa_thermistor {
1308 compatible = "murata,ncp15xh103";
1309 status = "okay";
1310 pullup-uv = <1800000>;
1311 pullup-ohm = <0>;
1312 pulldown-ohm = <10000>;
1313 io-channels = <&exynos_adc 4>;
1314 io-channel-names = "pa_therm";
1315 connected-positive;
1316 };
1317 board_thermistor {
1318 compatible = "murata,ncp03wf104";
1319 status = "okay";
1320 pullup-uv = <1800000>;
1321 pullup-ohm = <100000>;
1322 pulldown-ohm = <0>;
1323 io-channels = <&exynos_adc 7>;
1324 io-channel-names = "board_therm";
1325 };
1326 usb_con_thermistor {
1327 compatible = "murata,ncp03wf104";
1328 status = "okay";
1329 pullup-uv = <1800000>;
1330 pullup-ohm = <100000>;
1331 pulldown-ohm = <0>;
1332 io-channels = <&exynos_adc 8>;
1333 io-channel-names = "usb_con_therm";
1334 };
1335 };
1336
1337 &i2c_2 {
1338 #address-cells = <1>;
1339 #size-cells = <0>;
1340 status = "okay";
1341
1342 samsung,i2c-max-bus-freq = <600000>;
1343
1344 sec-nfc@27 {
1345 compatible = "sec-nfc";
1346 reg = <0x27>;
1347
1348 sec-nfc,ven-gpio = <&gpg0 0 0>;
1349 sec-nfc,firm-gpio = <&gpg0 2 0>;
1350
1351 sec-nfc,irq-gpio = <&gpa1 2 0>;
1352 sec-nfc,clk_req-gpio = <&gpg0 1 0>;
1353 sec-nfc,ldo_en = <&gpm22 0 0>;
1354 sec-nfc,pmic-ldo = "vdd_ldo37";
1355
1356 clock-names = "OSC_NFC";
1357 clocks = <&clock OSC_NFC>;
1358 pinctrl-names = "default";
1359 pinctrl-0 = <&xclkout1 &nfc_pd>;
1360 };
1361 };
1362
1363 &sec_pwm {
1364 status = "okay";
1365 pinctrl-names = "default";
1366 pinctrl-0 = <&motor_pwm>;
1367 };
1368
1369
1370 &fmp_0 {
1371 exynos,block-type = "sda";
1372 exynos,fips-block_offset = <5>;
1373 };
1374
1375 &contexthub_0 {
1376 /* chub irq pin lists */
1377 chub-irq-pin = <162>;
1378 clocks =
1379 /* SHUB */
1380 <&clock UMUX_CLKCMU_SHUB_BUS>,
1381 /* MAG. SENSOR : AK09918C */
1382 <&clock CMGP01_USI>,
1383 /* PROX. SENSOR : TMD3702 */
1384 <&clock CMGP03_USI>,
1385 /* ALS SENSOR : BH1726 */
1386 <&clock CMGP_I2C>;
1387 clock-names =
1388 "chub_bus",
1389 "cmgp_usi01",
1390 "cmgp_usi03",
1391 "cmgp_i2c";
1392 os-type = "os.checked_0.bin";
1393 };
1394
1395 &pinctrl_0 {
1396 pmic_irq: pmic-irq {
1397 samsung,pins = "gpa2-0";
1398 samsung,pin-pud = <3>;
1399 samsung,pin-drv = <3>;
1400 };
1401
1402 sub_pmic_irq: sub-pmic-irq {
1403 samsung,pins = "gpa1-3";
1404 samsung,pin-function = <0>;
1405 samsung,pin-pud = <0>;
1406 samsung,pin-drv = <0>;
1407 };
1408
1409
1410 key_voldown: key-voldown {
1411 samsung,pins = "gpa1-6";
1412 samsung,pin-function = <0xf>;
1413 samsung,pin-pud = <0>;
1414 samsung,pin-drv = <0>;
1415 };
1416
1417 key_volup: key-volup {
1418 samsung,pins = "gpa1-5";
1419 samsung,pin-function = <0xf>;
1420 samsung,pin-pud = <0>;
1421 samsung,pin-drv = <0>;
1422 };
1423
1424 key_power: key-power {
1425 samsung,pins = "gpa1-7";
1426 samsung,pin-function = <0xf>;
1427 samsung,pin-pud = <0>;
1428 samsung,pin-drv = <0>;
1429 };
1430
1431 dwmmc2_cd_ext_irq: dwmmc2_cd_ext_irq {
1432 samsung,pins = "gpa0-7";
1433 samsung,pin-function = <0xf>;
1434 samsung,pin-pud = <0>;
1435 samsung,pin-drv = <3>;
1436 };
1437
1438 attn_irq: attn-irq {
1439 samsung,pins = "gpa2-4";
1440 samsung,pin-function = <0xf>;
1441 samsung,pin-pud = <0>;
1442 samsung,pin-drv = <0>;
1443 };
1444
1445 attn_input: attn-input {
1446 samsung,pins = "gpa2-4";
1447 samsung,pin-function = <0>;
1448 samsung,pin-pud = <1>;
1449 };
1450
1451 if_pmic_irq: if-pmic-irq {
1452 samsung,pins = "gpa2-1";
1453 samsung,pin-function = <0>;
1454 samsung,pin-pud = <0>;
1455 samsung,pin-drv = <0>;
1456 };
1457
1458 fuel_irq: fuel-irq {
1459 samsung,pins = "gpa2-3";
1460 samsung,pin-function = <0>;
1461 samsung,pin-pud = <0>;
1462 samsung,pin-drv = <0>;
1463 };
1464
1465 usbpd_irq: usbpd-irq {
1466 samsung,pins = "gpa2-2";
1467 samsung,pin-function = <0xf>;
1468 samsung,pin-pud = <3>;
1469 samsung,pin-drv = <3>;
1470 };
1471 /* TODO: Need to check pin number
1472 small_charger_irq: small-charger-irq {
1473 samsung,pins = "gpa2-5";
1474 samsung,pin-function = <0>;
1475 samsung,pin-pud = <0>;
1476 samsung,pin-drv = <0>;
1477 };
1478 */
1479 cap_int_status: cap_int_status {
1480 samsung,pins = "gpa2-6";
1481 samsung,pin-function = <0>;
1482 samsung,pin-val = <1>;
1483 samsung,pin-pud = <3>;
1484 };
1485
1486 lra_int_status: lra_int_status {
1487 samsung,pins = "gpa2-7";
1488 samsung,pin-function = <0>;
1489 samsung,pin-val = <1>;
1490 samsung,pin-pud = <3>;
1491 };
1492
1493 sleep_alive: sleep-state {
1494 PIN_EINT_PUD(gpa0-2, DIS); /* SPK_PA_INT */
1495 PIN_IN_PUD(gpa0-3, DIS); /* SC_INTB */
1496 PIN_IN_PUD(gpa0-4, DIS); /* IF_PMIC_MRSTB */
1497 PIN_EINT_PUD(gpa0-6, DIS); /* CODEC_IRQ_N */
1498 PIN_EINT_PUD(gpa0-7, DIS); /* SD_SIM_DET */
1499
1500 //PIN_IN_PUD(gpa1-1, DOWN); /* FP_RST_NT */
1501 PIN_EINT_PUD(gpa1-2, DIS); /* NFC_IRQ */
1502 //PIN_IN_PUD(gpa1-3, DOWN); /* TP_RST_N */
1503 PIN_IN_PUD(gpa1-5, DIS); /* KEY_VOL_UP */
1504 PIN_IN_PUD(gpa1-6, DIS); /* KEY_VOL_DOWN */
1505 //PIN_INT_PUD(gpa1-7, DIS); /* PMIC_ONOB */
1506
1507 //PIN_EINT_PUD(gpa2-0, DIS); /* PMIC_IRQB */
1508 //PIN_EINT_PUD(gpa2-1, DIS); /* IF_PMIC_IRQB */
1509 PIN_EINT_PUD(gpa2-2, DIS); /* IF_PMIC_INTB */
1510 //PIN_EINT_PUD(gpa2-3, DIS); /* FG_INTB */
1511 PIN_EINT_PUD(gpa2-4, DIS); /* TP_INT_B */
1512 //PIN_IN_PUD(gpa2-5, DOWN); /* MOTOR_RSTN */
1513 PIN_EINT_PUD(gpa2-6, DIS); /* SAR_PS_INT */
1514 PIN_EINT_PUD(gpa2-7, DIS); /* MOTOR_INTN */
1515
1516 PIN_FUNC_PUD(gpq0-2, UP); /* SPEEDY_PMIC */
1517 PIN_IN_PUD(gpq0-3, DOWN); /* AP_UART0_RXD */
1518 PIN_IN_PUD(gpq0-4, UP); /* AP_UART0_TXD */
1519 };
1520
1521 normal_alive: normal-state {
1522 PIN_EINT_PUD(gpa0-2, DIS); /* SPK_PA_INT */
1523 PIN_IN_PUD(gpa0-3, DIS); /* SC_INTB */
1524 PIN_IN_PUD(gpa0-4, DIS); /* IF_PMIC_MRSTB */
1525 PIN_EINT_PUD(gpa0-6, DIS); /* CODEC_IRQ_N */
1526 PIN_EINT_PUD(gpa0-7, DIS); /* SD_SIM_DET */
1527
1528 PIN_EINT_PUD(gpa1-2, DIS); /* NFC_IRQ */
1529 PIN_EINT_PUD(gpa1-5, DIS); /* KEY_VOL_UP */
1530 PIN_EINT_PUD(gpa1-6, DIS); /* KEY_VOL_DOWN */
1531
1532 PIN_EINT_PUD(gpa2-2, DIS); /* IF_PMIC_INTB */
1533 PIN_EINT_PUD(gpa2-4, DIS); /* TP_INT_B */
1534 PIN_EINT_PUD(gpa2-6, DIS); /* SAR_PS_INT */
1535 PIN_EINT_PUD(gpa2-7, DIS); /* MOTOR_INTN */
1536
1537 PIN_FUNC_PUD(gpq0-2, UP); /* SPEEDY_PMIC */
1538 PIN_FUNC_PUD(gpq0-3, DOWN); /* AP_UART0_RXD */
1539 PIN_FUNC_PUD(gpq0-4, UP); /* AP_UART0_TXD */
1540 };
1541 };
1542
1543 &pinctrl_1 {
1544 sleep_cmgp: sleep-state {
1545 PIN_IN_PUD(gpm2-0, DIS); /* LCD_SCL */
1546 PIN_IN_PUD(gpm3-0, DIS); /* LCD_SCA */
1547 PIN_IN_PUD(gpm4-0, DIS); /* SENSOR_SCL_1.8V */
1548 PIN_IN_PUD(gpm5-0, DIS); /* SENSOR_SDA_1.8V */
1549 PIN_IN_PUD(gpm6-0, DIS); /* LT_SENSOR_SCL_1.8V */
1550 PIN_IN_PUD(gpm7-0, DIS); /* LT_SENSOR_SDA_1.8V */
1551 PIN_IN_PUD(gpm8-0, DIS); /* MOTOR_I2C_SCL */
1552 PIN_IN_PUD(gpm9-0, DIS); /* AP_UART0_TXD */
1553 PIN_IN_PUD(gpm10-0, DIS); /* SAR_SENSOR_SCL */
1554 PIN_IN_PUD(gpm11-0, DIS); /* SAR_SENSOR_SDA */
1555 PIN_IN_PUD(gpm16-0, DOWN); /* NC */
1556 PIN_IN_PUD(gpm17-0, DOWN); /* NC */
1557 PIN_EINT_PUD(gpm20-0, DIS); /* PSENSOR_INT */
1558 //PIN_IN_PUD(gpm22-0, DOWN); /* NFC_PVDDEN */
1559 PIN_IN_PUD(gpm25-0, DIS); /* SPK_ID */
1560 };
1561
1562 normal_cmgp: normal-cmgp {
1563 //PIN_EINT_PUD(gpm20-0, UP); /* PSENSOR_INT */
1564 PIN_FUNC_PUD(gpm2-0, DIS); /* LCD_SCL */
1565 PIN_FUNC_PUD(gpm3-0, DIS); /* LCD_SCA */
1566 PIN_FUNC_PUD(gpm4-0, UP); /* SENSOR_SCL_1.8V */
1567 PIN_FUNC_PUD(gpm5-0, UP); /* SENSOR_SDA_1.8V */
1568 PIN_FUNC_PUD(gpm6-0, UP); /* LT_SENSOR_SCL_1.8V */
1569 PIN_FUNC_PUD(gpm7-0, UP); /* LT_SENSOR_SDA_1.8V */
1570 PIN_FUNC_PUD(gpm8-0, DIS); /* MOTOR_I2C_SCL */
1571 PIN_FUNC_PUD(gpm9-0, DIS); /* MOTOR_I2C_SDA */
1572 PIN_FUNC_PUD(gpm10-0, DIS); /* SAR_SENSOR_SCL */
1573 PIN_FUNC_PUD(gpm11-0, DIS); /* SAR_SENSOR_SDA */
1574 PIN_EINT_PUD(gpm20-0, DIS); /* PSENSOR_INT */
1575 PIN_IN_PUD(gpm25-0, DIS); /* SPK_ID */
1576 };
1577 };
1578
1579 &pinctrl_2 {
1580 sleep_aud: sleep-state {
1581 PIN_SLP(gpb0-0, IN, DOWN); /* NC */
1582 PIN_SLP(gpb0-1, IN, DOWN); /* I2S0_CODEC_BCLK */
1583 PIN_SLP(gpb0-2, IN, DOWN); /* I2S0_CODEC_WS */
1584 PIN_SLP(gpb0-3, IN, DOWN); /* I2S0_CODEC_SDO */
1585 PIN_SLP(gpb0-4, IN, DOWN); /* I2S0_CODEC_SDI */
1586
1587 PIN_SLP(gpb1-0, IN, DOWN); /* NC */
1588 PIN_SLP(gpb1-1, IN, DOWN); /* NC */
1589 PIN_SLP(gpb1-2, IN, DOWN); /* NC */
1590 PIN_SLP(gpb1-3, IN, DOWN); /* NC */
1591
1592 PIN_SLP(gpb2-0, IN, DOWN); /* I2S2_CODEC_BCLK */
1593 PIN_SLP(gpb2-1, IN, DOWN); /* I2S2_CODEC_WS */
1594 PIN_SLP(gpb2-2, IN, DOWN); /* I2S2_CODEC_SDO */
1595 PIN_SLP(gpb2-3, IN, DOWN); /* I2S2_CODEC_SDI */
1596 PIN_SLP(gpb2-4, IN, DOWN); /* FM_SPDY_S620 */
1597 };
1598 };
1599
1600 &pinctrl_3 {
1601 sleep_fsys: sleep-fsys {
1602 PIN_SLP(gpf0-0, PREV, DIS); /* UFS_EMBD_REFCLK_OUT */
1603 PIN_SLP(gpf0-1, PREV, DIS); /* UFS_EMBD_RESETN */
1604 };
1605 };
1606
1607 &pinctrl_4 {
1608 /* Warm reset information from AP */
1609 pm_wrsti: pm-wrsti {
1610 samsung,pins = "gpg0-7";
1611 samsung,pin-con-pdn = <3>;
1612 };
1613
1614 motor_pwm: motor_pwm {
1615 samsung,pins = "gpg4-2";
1616 samsung,pin-function = <2>;
1617 samsung,pin-pud = <1>;
1618 samsung,pin-drv = <0>;
1619 };
1620
1621 vdd_on: vdd-on {
1622 samsung,pins ="gpg3-4";
1623 samsung,pin-function = <1>;
1624 samsung,pin-val = <1>;
1625 samsung,pin-pud = <3>;
1626 };
1627
1628 vdd_off: vdd-off {
1629 samsung,pins ="gpg3-4";
1630 samsung,pin-function = <0>;
1631 samsung,pin-val = <0>;
1632 samsung,pin-pud = <1>;
1633 };
1634
1635 lcd_reset: lcd_reset {
1636 samsung,pins = "gpg1-4";
1637 samsung,pin-function = <1>;
1638 samsung,pin-pud = <3>;
1639 samsung,pin-val = <1>;
1640 samsung,pin-con-pdn =<3>;
1641 samsung,pin-pud-pdn = <3>;
1642 };
1643
1644 codec_reset: codec-reset {
1645 samsung,pins ="gpg3-2";
1646 samsung,pin-pud = <0>;
1647 samsung,pin-con-pdn =<3>;
1648 samsung,pin-pud-pdn = <0>;
1649 };
1650
1651 codec_en: codec_en {
1652 samsung,pins = "gpg1-1";
1653 samsung,pin-function = <1>;
1654 samsung,pin-pud = <3>;
1655 samsung,pin-val = <1>;
1656 samsung,pin-con-pdn =<3>;
1657 samsung,pin-pud-pdn = <3>;
1658 };
1659
1660 pa_reset: pa-reset {
1661 samsung,pins ="gpg3-3";
1662 samsung,pin-con-pdn =<3>;
1663 samsung,pin-pud-pdn = <3>;
1664 };
1665
1666 nfc_pd: nfc-pd {
1667 samsung,pins ="gpg0-0";
1668 samsung,pin-function = <1>;
1669 samsung,pin-pud = <0>;
1670 samsung,pin-con-pdn =<3>;
1671 samsung,pin-pud-pdn = <0>;
1672 };
1673
1674 sleep_top: sleep-top {
1675 PIN_SLP(gpp0-0, IN, DIS); /* I2C0_FG_PMIC_SDA */
1676 PIN_SLP(gpp0-1, IN, DIS); /* I2C0_FG_PMIC_SCL */
1677 PIN_SLP(gpp0-2, IN, DIS); /* I2C1_IF_PMIC_SDA */
1678 PIN_SLP(gpp0-3, IN, DIS); /* I2C1_IF_PMIC_SCL */
1679
1680 /* Add 18.12.31 start */
1681 PIN_SLP(gpp0-4, IN, DIS); /* I2C2_NFC_SDA */
1682 PIN_SLP(gpp0-5, IN, DIS); /* I2C2_NFC_SCL */
1683 PIN_SLP(gpp0-6, IN, DOWN); /* N.C. */
1684 PIN_SLP(gpp0-7, IN, DOWN); /* N.C. */
1685
1686 PIN_SLP(gpp1-0, IN, DIS); /* I2C4_TSP_SDA */
1687 PIN_SLP(gpp1-1, IN, DIS); /* I2C4_TSP_SCL */
1688 PIN_SLP(gpp1-2, IN, DOWN); /* N.C. */
1689 PIN_SLP(gpp1-3, IN, DOWN); /* N.C. */
1690 PIN_SLP(gpp1-4, IN, DOWN); /* N.C. */
1691 PIN_SLP(gpp1-5, IN, DOWN); /* N.C. */
1692
1693 PIN_SLP(gpc0-0, IN, DIS); /* I2C_CAM0_REAR_MAIN_SDA */
1694 PIN_SLP(gpc0-1, IN, DIS); /* I2C_CAM0_REAR_MAIN_SCL */
1695 PIN_SLP(gpc0-2, IN, DIS); /* I2C_CAM1_REAR_SUB_SDA */
1696 PIN_SLP(gpc0-3, IN, DIS); /* I2C_CAM1_REAR_SUB_SCL */
1697 PIN_SLP(gpc0-4, IN, DIS); /* I2C_CAM2_FRONT_SDA */
1698 PIN_SLP(gpc0-5, IN, DIS); /* I2C_CAM2_FRONT_SCL */
1699 PIN_SLP(gpc0-6, IN, DOWN); /* N.C. */
1700 PIN_SLP(gpc0-7, IN, DOWN); /* N.C. */
1701 /* Add 18.12.31 end */
1702
1703 /* ADD 19.01.01 start */
1704 PIN_SLP(gpc1-2, IN, DOWN); /* N.C. */
1705
1706 PIN_SLP(gpc2-3, PREV, DIS); /* DISP_TES added 19.01.05 */
1707 PIN_SLP(gpc2-4, IN, DOWN); /* N.C. */
1708
1709 PIN_SLP(gpg0-0, PREV, DIS); /* NFC_PD */
1710
1711 //PIN_SLP(gpg0-1, PREV, DIS); /* NFC_CLKREQ */
1712 //PIN_SLP(gpg0-2, PREV, DIS); /* NFC_WAKE */
1713 /* ADD 19.01.01 end t*/
1714
1715 PIN_SLP(gpg0-7, PREV, DIS); /* PMIC_WRSTBI */
1716
1717 //PIN_SLP(gpg1-1, PREV, DIS); /* VDD_CODEC_EN */
1718 PIN_SLP(gpg1-4, PREV, DIS); /* LCD_RESET_N */
1719
1720 //PIN_SLP(gpg2-0, PREV, DIS); /* FP_LDO_EN_3V3 */
1721 //PIN_SLP(gpg2-1, PREV, DIS); /* LDO_BL_EN */
1722 //PIN_SLP(gpg2-2, PREV, DIS); /* FP_LDOEN_1V8 */
1723 //PIN_SLP(gpg2-3, PREV, DIS); /* FCAM_AVDD_EN */
1724 //PIN_SLP(gpg2-4, PREV, DIS); /* FCAM_DVDD_EN */
1725 //PIN_SLP(gpg2-5, PREV, DIS); /* CAM_OVDD_EN */
1726 //PIN_SLP(gpg2-6, PREV, DIS); /* RCAM_MAIN_AVDD_EN */
1727 //PIN_SLP(gpg2-7, PREV, DIS); /* RCAM_DVDD_EN */
1728
1729 //PIN_SLP(gpg3-0, PREV, DIS); /* LCD_BIAS_ENN */
1730 //PIN_SLP(gpg3-1, PREV, DIS); /* LCD_BIAS_ENP */
1731 //PIN_SLP(gpg3-3, PREV, DIS); /* AUDIO_PA_RST */
1732 //PIN_SLP(gpg3-4, PREV, DIS); /* LCD_LDO_1V8_En */
1733
1734 //PIN_SLP(gpg4-0, PREV, DIS); /* XBOOTLDO */
1735 };
1736 };
1737
1738 &pinctrl_5 {
1739 sleep_shub: sleep-shub {
1740 PIN_SLP(gph0-0, IN, DOWN); /* ACC_SPI_CLK */
1741 PIN_SLP(gph0-1, IN, DOWN); /* ACC_SPI_MOSI */
1742 PIN_SLP(gph0-2, IN, DOWN); /* ACC_SPI_MISO */
1743 PIN_SLP(gph0-3, IN, DOWN); /* ACC_SPI_CS_N */
1744 PIN_SLP(gph1-0, IN, DOWN); /* ACCEL_GRY0_INT1 */
1745 PIN_SLP(gph1-1, IN, DOWN); /* ACCEL_GRY0_INT2 */
1746 PIN_SLP(gph1-2, IN, DOWN); /* LIGHT_INT */
1747 };
1748 };
1749
1750 &udc {
1751 status = "okay";
1752 };
1753
1754 &usbdrd_dwc3 {
1755 dr_mode = "otg";
1756 maximum-speed = "high-speed";
1757 };
1758
1759 &usbdrd_phy {
1760 status = "okay";
1761 usb3phy-isolation = <1>;
1762
1763 hs_tune_param = <&usb_hs_tune>;
1764 };
1765
1766 &usbdrd3_phy {
1767 status = "okay";
1768 usb3phy-isolation = <1>;
1769
1770 hs_tune_param = <&usb3_hs_tune>;
1771 ss_tune_param = <&usb3_ss_tune>;
1772 };
1773
1774 &serial_0 {
1775 status = "okay";
1776 };
1777
1778 &dsim_0 {
1779 lcd_info = <&nt36672a>;
1780 /* reset, lcd_bias_enp, lcd_bias_enn, lcd_bl_en*/
1781 gpios = <&gpg1 4 0x1>, <&gpg3 1 0x1>, <&gpg3 0 0x1>, <&gpg2 1 0x1>;
1782 pinctrl-names = "lcd_reset";
1783 pinctrl-0 = <&lcd_reset>;
1784 };
1785
1786 /* USI_0_SHUB */
1787 &usi_0_shub {
1788 usi_v2_mode = "spi";
1789 status = "disabled";
1790 };
1791
1792 /* USI_SHUB_0_I2C */
1793 &usi_0_shub_i2c {
1794 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1795 status = "disabled";
1796 };
1797
1798 /* USI_0_CMGP */
1799 &usi_0_cmgp {
1800 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1801 usi_v2_mode = "i2c";
1802 status = "okay";
1803 };
1804
1805 /* USI_0_CMGP_I2C */
1806 &usi_0_cmgp_i2c {
1807 usi_v2_mode = "i2c";
1808 status = "okay";
1809 };
1810
1811 /* USI_1_CMGP */
1812 &usi_1_cmgp {
1813 usi_v2_mode = "i2c";
1814 status = "okay";
1815 };
1816
1817 /* USI_1_CMGP_I2C */
1818 &usi_1_cmgp_i2c {
1819 usi_v2_mode = "i2c";
1820 status = "okay";
1821 };
1822
1823 /* USI_2_CMGP */
1824 &usi_2_cmgp {
1825 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1826 usi_v2_mode = "i2c";
1827 status = "okay";
1828 };
1829
1830 /* USI_2_CMGP_I2C */
1831 &usi_2_cmgp_i2c {
1832 usi_v2_mode = "i2c";
1833 status = "okay";
1834 };
1835
1836 /* USI_3_CMGP */
1837 &usi_3_cmgp {
1838 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1839 status = "disabled";
1840 };
1841
1842 /* USI_3_CMGP_I2C */
1843 &usi_3_cmgp_i2c {
1844 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1845 status = "disabled";
1846 };
1847
1848 /* USI_4_CMGP */
1849 &usi_4_cmgp {
1850 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1851 status = "disabled";
1852 };
1853
1854 /* USI_4_CMGP_I2C */
1855 &usi_4_cmgp_i2c {
1856 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1857 status = "disabled";
1858 };
1859
1860 /* USI_PERI_UART */
1861 &usi_peri_uart {
1862 usi_v2_mode = "uart";
1863 status = "okay";
1864 };
1865
1866 /* USI_PERI_CAMI2C_0 */
1867 &usi_peri_cami2c_0 {
1868 usi_v2_mode = "i2c";
1869 status = "okay";
1870 };
1871
1872 /* USI_PERI_CAMI2C_1 */
1873 &usi_peri_cami2c_1 {
1874 usi_v2_mode = "i2c";
1875 status = "okay";
1876 };
1877
1878 /* USI_PERI_CAMI2C_2 */
1879 &usi_peri_cami2c_2 {
1880 usi_v2_mode = "i2c";
1881 status = "okay";
1882 };
1883
1884 /* USI_PERI_CAMI2C_3 */
1885 &usi_peri_cami2c_3 {
1886 usi_v2_mode = "i2c";
1887 status = "okay";
1888 };
1889
1890 /* USI_PERI_SPI_0 */
1891 &usi_peri_spi_0 {
1892 usi_v2_mode = "spi";
1893 status = "okay";
1894 };
1895
1896 /* USI_PERI_SPI_1 */
1897 &usi_peri_spi_1 {
1898 usi_v2_mode = "spi";
1899 status = "okay";
1900 };
1901
1902 /* USI_PERI_USI_0 */
1903 &usi_peri_usi_0 {
1904 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1905 status = "disabled";
1906 };
1907
1908 /* USI_PERI_USI_0_I2C */
1909 &usi_peri_usi_0_i2c {
1910 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1911 status = "disabled";
1912 };
1913
1914 /* USI_PERI_SPI_2 */
1915 &usi_peri_spi_2 {
1916 usi_v2_mode = "spi";
1917 status = "okay";
1918 };
1919
1920 &spi_6 {
1921 status = "okay";
1922 pinctrl-names = "default";
1923 pinctrl-0 = <&spi6_bus &spi6_cs_func &pa_reset>;
1924 /*cs-gpios = <&gpp2 3 0>;*/
1925 /*gpp2[3]*/
1926 /*num-cs = <1>;*/
1927 #address-cells = <1>;
1928 #size-cells = <0>;
1929 cs35l41_left: cs35l41@0 {
1930 compatible = "cirrus,cs35l41";
1931 reg = <0x0>;
1932
1933 spi-max-frequency = <9600000>;
1934
1935 interrupts = <2 0 0>;
1936 interrupt-controller;
1937 interrupt-parent = <&gpa0>;
1938 reset-gpios = <&gpg3 3 0>;
1939 #sound-dai-cells = <1>;
1940
1941 VA-supply = <&l42_reg>;
1942 VP-supply = <&V_SYS>;
1943
1944 cirrus,boost-peak-milliamp = <4500>;
1945 cirrus,boost-ind-nanohenry = <1000>;
1946 cirrus,boost-cap-microfarad = <15>;
1947 cirrus,asp-sdout-hiz = <0x1>;
1948 cirrus,gpio-config2 {
1949 cirrus,gpio-src-select = <0x4>;
1950 cirrus,gpio-output-enable;
1951 };
1952
1953 adsps {
1954 #address-cells = <1>;
1955 #size-cells = <0>;
1956 prince_l_dsp: adsp@2b80000 {
1957 reg = <0x2b80000>;
1958 firmware {
1959 protectionsp_default {
1960 cirrus,full-name;
1961 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
1962 cirrus,bin-file = "cs35l41-dsp1-spk-prot-music-aac.bin";
1963 };
1964 protectionsp_music_aac {
1965 cirrus,full-name;
1966 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
1967 cirrus,bin-file = "cs35l41-dsp1-spk-prot-music-aac.bin";
1968 };
1969 protectionsp_indmusic_aac {
1970 cirrus,full-name;
1971 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
1972 cirrus,bin-file = "cs35l41-dsp1-spk-prot-indmusic-aac.bin";
1973 };
1974 protectionsp_voice_aac {
1975 cirrus,full-name;
1976 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
1977 cirrus,bin-file = "cs35l41-dsp1-spk-prot-voice-aac.bin";
1978 };
1979 protectionsp_ringtone_aac {
1980 cirrus,full-name;
1981 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
1982 cirrus,bin-file = "cs35l41-dsp1-spk-prot-ringtone-aac.bin";
1983 };
1984 protectionsp_notification_aac {
1985 cirrus,full-name;
1986 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
1987 cirrus,bin-file = "cs35l41-dsp1-spk-prot-notification-aac.bin";
1988 };
1989 protectionsp_music_qisheng {
1990 cirrus,full-name;
1991 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
1992 cirrus,bin-file = "cs35l41-dsp1-spk-prot-music-qisheng.bin";
1993 };
1994 protectionsp_indmusic_qisheng {
1995 cirrus,full-name;
1996 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
1997 cirrus,bin-file = "cs35l41-dsp1-spk-prot-indmusic-qisheng.bin";
1998 };
1999 protectionsp_voice_qisheng {
2000 cirrus,full-name;
2001 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
2002 cirrus,bin-file = "cs35l41-dsp1-spk-prot-voice-qisheng.bin";
2003 };
2004 protectionsp_ringtone_qisheng{
2005 cirrus,full-name;
2006 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
2007 cirrus,bin-file = "cs35l41-dsp1-spk-prot-ringtone-qisheng.bin";
2008 };
2009 protectionsp_notification_qisheng {
2010 cirrus,full-name;
2011 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
2012 cirrus,bin-file = "cs35l41-dsp1-spk-prot-notification-qisheng.bin";
2013 };
2014 calibration_aac {
2015 cirrus,full-name;
2016 cirrus,wmfw-file = "cs35l41-dsp1-diag.wmfw";
2017 cirrus,bin-file = "cs35l41-dsp1-aac-cali.bin";
2018 };
2019 calibration_qisheng{
2020 cirrus,full-name;
2021 cirrus,wmfw-file = "cs35l41-dsp1-diag.wmfw";
2022 cirrus,bin-file = "cs35l41-dsp1-qissheng-cali.bin";
2023 };
2024 };
2025 };
2026 };
2027 controller-data {
2028 /*cs-gpio = <gpm8 0 0>*/
2029 /*cs-gpios = <&gpp2 3 0>;*/
2030 samsung,spi-feedback-delay = <1>;
2031 samsung,spi-chip-select-mode = <0>;
2032 };
2033 };
2034 };
2035
2036 &spi_9 {
2037 pinctrl-names = "default";
2038 pinctrl-0 = <&spi9_bus &spi9_cs_func &codec_en>;
2039 status = "okay";
2040 #address-cells = <1>;
2041 #size-cells = <0>;
2042 cs47l35: cs47l35@0 {
2043 compatible = "cirrus,cs47l35";
2044 reg = <0x0>;
2045
2046 spi-max-frequency = <11000000>;
2047
2048 interrupts = <6 8 0>;
2049 interrupt-controller;
2050 #interrupt-cells = <2>;
2051 interrupt-parent = <&gpa0>;
2052 gpio-controller;
2053 #gpio-cells = <2>;
2054 #sound-dai-cells = <1>;
2055
2056 AVDD-supply = <&l42_reg>;
2057 DBVDD1-supply = <&l42_reg>;
2058 DBVDD2-supply = <&l42_reg>;
2059 CPVDD1-supply = <&l42_reg>;
2060 /*Not used LDO44*/
2061 /*CPVDD2-supply = <&l44_reg>;*/
2062 /*DCVDD-supply = <&l44_reg>;*/
2063 SPKVDD-supply = <&V_SYS>;
2064
2065 reset-gpios = <&gpg3 2 0>;
2066
2067 cirrus,dmic-ref = <0 0 0>;
2068 cirrus,inmode = <
2069 0 0 0 0 /* IN1 */
2070 0 0 0 0 /* IN2 */
2071 >;
2072
2073 cirrus,gpsw = <1 0>;
2074
2075 pinctrl-names = "probe", "active";
2076 pinctrl-0 = <&codec_reset>;
2077 pinctrl-1 = <&codec_reset &cs47l35_defaults>;
2078
2079 madera_pinctrl: madera-pinctrl {
2080 compatible = "cirrus,madera-pinctrl";
2081 cs47l35_defaults: cs47l35-gpio-defaults {
2082 aif1 {
2083 groups = "aif1";
2084 function = "aif1";
2085 bias-bus-hold;
2086 };
2087
2088 aif2 {
2089 groups = "aif2";
2090 function = "aif2";
2091 bias-bus-hold;
2092 };
2093
2094 aif3 {
2095 groups = "aif3";
2096 function = "aif3";
2097 bias-bus-hold;
2098 };
2099
2100 gpio6 { /* Amp Clock */
2101 groups = "gpio6";
2102 function = "opclk";
2103 bias-pull-up;
2104 output-low;
2105 };
2106
2107 gpio5 { /* Mic Polarity Flip */
2108 groups = "gpio5";
2109 function = "io";
2110 };
2111 };
2112 };
2113
2114
2115 micvdd {
2116 regulator-min-microvolt = <3000000>;
2117 regulator-max-microvolt = <3000000>;
2118 };
2119
2120 audio_micbias1:MICBIAS1 {
2121 regulator-min-microvolt = <2800000>;
2122 regulator-max-microvolt = <2800000>;
2123 cirrus,ext-cap = <1>;
2124 };
2125 MICBIAS1A {
2126 regulator-active-discharge = <1>;
2127 };
2128 MICBIAS1B {
2129 regulator-active-discharge = <1>;
2130 };
2131
2132 MICBIAS2 {
2133 regulator-min-microvolt = <2800000>;
2134 regulator-max-microvolt = <2800000>;
2135 cirrus,ext-cap = <1>;
2136 };
2137
2138 MICBIAS2A {
2139 regulator-active-discharge = <1>;
2140 };
2141 MICBIAS2B {
2142 regulator-active-discharge = <1>;
2143 };
2144
2145 cirrus,accdet {
2146 #address-cells = <1>;
2147 #size-cells = <0>;
2148
2149 acc@1 {
2150 reg = <1>;
2151
2152 cirrus,micd-configs = <
2153 0 0 2 0 0
2154 >;
2155 cirrus,micd-bias-start-time = <8>;
2156 cirrus,micd-rate = <6>;
2157 /*cirrus,micd-pol-gpios = <&cs47l35 4 0>;*/
2158 cirrus,micd-detect-debounce-ms = <700>;
2159 /*cirrus,jd-use-jd2;*/
2160 /*cirrus,micd-clamp-mode = <0x8>;*/
2161 cirrus,micd-manual-debounce = <2>;
2162 };
2163 };
2164
2165 adsps {
2166 #address-cells = <1>;
2167 #size-cells = <0>;
2168 adsp@17fe00 {
2169 reg = <0x17fe00>;
2170 firmware {
2171 frontend {
2172 cirrus,wmfw-file = "marley-dsp2-aov-frontend.wmfw";
2173 cirrus,bin-file = "marley-dsp2-aov-vrgain.bin";
2174 cirrus,full-name;
2175 cirrus,compr-caps = <14 1 4 1 16000>;
2176 };
2177 };
2178 };
2179 adsp@1ffe00 {
2180 reg = <0x1ffe00>;
2181 firmware {
2182 aov {
2183 cirrus,wmfw-file = "marley-dsp3-aov-control.wmfw";
2184 cirrus,bin-file = "None";
2185 cirrus,full-name;
2186 cirrus,compr-caps = <14 1 4 1 16000>;
2187 };
2188 };
2189 };
2190 };
2191
2192 controller-data {
2193 samsung,spi-feedback-delay = <1>;
2194 samsung,spi-chip-select-mode = <0>;
2195 };
2196 };
2197 };