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[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / arch / arm64 / boot / dts / exynos / exynos9609-robusta2_common.dtsi
1 /*
2 * SAMSUNG EXYNOS9610 board device tree source
3 *
4 * Copyright (c) 2017 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include "exynos9610_battery_data.dtsi"
13 #include <dt-bindings/clock/exynos9610.h>
14 #include "modem-ss360ap-sit-pdata.dtsi"
15 #include "exynos9610-display-lcd.dtsi"
16 #include "novatek-nt36xxx-i2c.dtsi"
17 #include "himax-hx83112a-i2c.dtsi"
18 #include "wing-sensor.dtsi"
19 #include "exynos9610-robusta2-motor.dtsi"
20 #include "exynos9610_gpio_config_macros.dtsi"
21 #include "carrier-channel-ids.dtsi"
22
23 / {
24 fragment@common {
25 target-path = "/";
26 __overlay__ {
27 #address-cells = <2>;
28 #size-cells = <1>;
29
30 fixed-rate-clocks {
31 oscclk {
32 compatible = "samsung,exynos9610-oscclk";
33 clock-frequency = <26000000>;
34 };
35 };
36
37 firmware {
38 android {
39 compatible = "android,firmware";
40 vbmeta {
41 compatible = "android,vbmeta";
42 parts = "vbmeta,boot,system,vendor,dtbo,oem";
43 };
44 fstab {
45 compatible = "android,fstab";
46 vendor {
47 compatible = "android,vendor";
48 dev = "/dev/block/platform/13520000.ufs/by-name/vendor";
49 type = "ext4";
50 mnt_flags = "ro";
51 fsmgr_flags = "wait,avb,slotselect";
52 };
53 oem {
54 compatible = "android,oem";
55 dev = "/dev/block/platform/13520000.ufs/by-name/oem";
56 type = "ext4";
57 mnt_flags = "ro,barrier=1,discard";
58 fsmgr_flags = "wait,avb,slotselect";
59 };
60 };
61 };
62 };
63
64 ifconn {
65 status = "okay";
66 compatible = "samsung,ifconn";
67 ifconn,usbpd = "s2mm005";
68 ifconn,muic = "s2mu106-muic";
69 };
70
71 /*Fingerprint start*/
72 et320: et320{
73 compatible = "egistec,et320";
74 status = "ok";
75 reg = <0>;
76 clocks = <&clock GATE_SPI_1_QCH>, <&clock SPI1>;
77 clock-names = "spi", "spi_busclk0";
78 pinctrl-names = "default";
79 pinctrl-0 = <&spi7_bus &spi7_cs_func>;
80 egistec,gpio_irq = <&gpa0 5 0>;
81 egistec,gpio_rst = <&gpa1 1 0>;
82 egistec,gpio_ldo3p3_en = <&gpg2 0 0>;
83 egistec,gpio_ldo1p8_en = <&gpg2 2 0>;
84 };
85 /*Fingerprint end*/
86
87 speedy@11a10000 {
88 status = "okay";
89 #address-cells = <1>;
90 #size-cells = <0>;
91 s2mpu09mfd@00 {
92 compatible = "samsung,s2mpu09mfd";
93 acpm-ipc-channel = <2>;
94 i2c-speedy-address;
95 s2mpu09,wakeup = "enabled";
96 s2mpu09,irq-gpio = <&gpa2 0 0>;
97 reg = <0x00>;
98 interrupts = <2 0 0>;
99 interrupt-parent = <&gpa2>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&pmic_irq &pm_wrsti>;
102 /* RTC: wtsr/smpl */
103 wtsr_en = "enabled"; /* enable */
104 smpl_en = "enabled"; /* enable */
105 wtsr_timer_val = <3>; /* 1000ms */
106 smpl_timer_val = <4>; /* 500ms */
107 check_jigon = <0>; /* do not check jigon */
108 /* RTC: If it's first boot, reset rtc to 1/1/2017 12:00:00(Sun) */
109 init_time,sec = <0>;
110 init_time,min = <0>;
111 init_time,hour = <12>;
112 init_time,mday = <1>;
113 init_time,mon = <0>;
114 init_time,year = <117>;
115 init_time,wday = <0>;
116
117 regulators {
118 b1_reg: BUCK1 {
119 regulator-name = "vdd_mif";
120 regulator-min-microvolt = <500000>;
121 regulator-max-microvolt = <1100000>;
122 regulator-always-on;
123 regulator-ramp-delay = <12000>;
124 regulator-initial-mode = <2>;
125 };
126
127 b2_reg: BUCK2 {
128 regulator-name = "vdd_cpucl1";
129 regulator-min-microvolt = <500000>;
130 regulator-max-microvolt = <1300000>;
131 regulator-always-on;
132 regulator-ramp-delay = <12000>;
133 regulator-initial-mode = <1>;
134 };
135
136 b3_reg: BUCK3 {
137 regulator-name = "vdd_cpucl0";
138 regulator-min-microvolt = <500000>;
139 regulator-max-microvolt = <1300000>;
140 regulator-always-on;
141 regulator-ramp-delay = <12000>;
142 regulator-initial-mode = <1>;
143 };
144
145 b4_reg: BUCK4{
146 regulator-name = "vdd_int";
147 regulator-min-microvolt = <500000>;
148 regulator-max-microvolt = <1100000>;
149 regulator-always-on;
150 regulator-ramp-delay = <12000>;
151 regulator-initial-mode = <2>;
152 };
153
154 b5_reg: BUCK5 {
155 regulator-name = "vdd_g3d";
156 regulator-min-microvolt = <500000>;
157 regulator-max-microvolt = <1200000>;
158 regulator-always-on;
159 regulator-ramp-delay = <12000>;
160 regulator-initial-mode = <2>;
161 };
162
163 b6_reg: BUCK6 {
164 regulator-name = "vdd_cam_vipx";
165 regulator-min-microvolt = <500000>;
166 regulator-max-microvolt = <1300000>;
167 regulator-always-on;
168 regulator-ramp-delay = <12000>;
169 regulator-initial-mode = <2>;
170 };
171
172 b7_reg: BUCK7 {
173 regulator-name = "vdd2_mem";
174 regulator-min-microvolt = <500000>;
175 regulator-max-microvolt = <1300000>;
176 regulator-always-on;
177 regulator-ramp-delay = <12000>;
178 regulator-initial-mode = <3>;
179 };
180
181 b8_reg: BUCK8 {
182 regulator-name = "vdd_lldo";
183 regulator-min-microvolt = <1200000>;
184 regulator-max-microvolt = <1500000>;
185 regulator-always-on;
186 regulator-ramp-delay = <12000>;
187 regulator-initial-mode = <3>;
188 };
189
190 b9_reg: BUCK9 {
191 regulator-name = "vdd_mldo";
192 regulator-min-microvolt = <1800000>;
193 regulator-max-microvolt = <2100000>;
194 regulator-always-on;
195 regulator-ramp-delay = <12000>;
196 regulator-initial-mode = <3>;
197 };
198
199 l1_reg: LDO1 {
200 regulator-name = "vdd_ldo1";
201 regulator-min-microvolt = <700000>;
202 regulator-max-microvolt = <1300000>;
203 regulator-always-on;
204 regulator-ramp-delay = <12000>;
205 regulator-initial-mode = <3>;
206 };
207
208 l2_reg: LDO2 {
209 regulator-name = "vqmmc";
210 regulator-min-microvolt = <1800000>;
211 regulator-max-microvolt = <3375000>;
212 regulator-ramp-delay = <12000>;
213 };
214
215 l3_reg: LDO3 {
216 regulator-name = "vdd_ldo3";
217 regulator-min-microvolt = <800000>;
218 regulator-max-microvolt = <1950000>;
219 regulator-always-on;
220 regulator-ramp-delay = <12000>;
221 regulator-initial-mode = <3>;
222 };
223
224 l4_reg: LDO4 {
225 regulator-name = "vdd_ldo4";
226 regulator-min-microvolt = <500000>;
227 regulator-max-microvolt = <1100000>;
228 regulator-always-on;
229 regulator-ramp-delay = <12000>;
230 regulator-initial-mode = <1>;
231 };
232
233 l5_reg: LDO5 {
234 regulator-name = "vdd_ldo5";
235 regulator-min-microvolt = <800000>;
236 regulator-max-microvolt = <1300000>;
237 regulator-always-on;
238 regulator-ramp-delay = <12000>;
239 regulator-initial-mode = <1>;
240 };
241
242 l6_reg: LDO6 {
243 regulator-name = "vdd_ldo6";
244 regulator-min-microvolt = <800000>;
245 regulator-max-microvolt = <1300000>;
246 regulator-always-on;
247 regulator-ramp-delay = <12000>;
248 regulator-initial-mode = <1>;
249 };
250
251 l7_reg: LDO7 {
252 regulator-name = "vdd_ldo7";
253 regulator-min-microvolt = <800000>;
254 regulator-max-microvolt = <1950000>;
255 regulator-always-on;
256 regulator-ramp-delay = <12000>;
257 regulator-initial-mode = <1>;
258 };
259
260 l8_reg: LDO8 {
261 regulator-name = "vdd_ldo8";
262 regulator-min-microvolt = <500000>;
263 regulator-max-microvolt = <1300000>;
264 regulator-always-on;
265 regulator-ramp-delay = <12000>;
266 regulator-initial-mode = <1>;
267 };
268
269 l9_reg: LDO9 {
270 regulator-name = "vdd_ldo9";
271 regulator-min-microvolt = <500000>;
272 regulator-max-microvolt = <1300000>;
273 regulator-always-on;
274 regulator-ramp-delay = <12000>;
275 regulator-initial-mode = <1>;
276 };
277
278 l10_reg: LDO10 {
279 regulator-name = "vdd_ldo10";
280 regulator-min-microvolt = <500000>;
281 regulator-max-microvolt = <1300000>;
282 regulator-always-on;
283 regulator-ramp-delay = <12000>;
284 regulator-initial-mode = <1>;
285 };
286
287 l11_reg: LDO11 {
288 regulator-name = "vdd_ldo11";
289 regulator-min-microvolt = <500000>;
290 regulator-max-microvolt = <1300000>;
291 regulator-always-on;
292 regulator-ramp-delay = <12000>;
293 regulator-initial-mode = <1>;
294 };
295
296 l12_reg: LDO12 {
297 regulator-name = "vdd_ldo12";
298 regulator-min-microvolt = <800000>;
299 regulator-max-microvolt = <1300000>;
300 regulator-always-on;
301 regulator-ramp-delay = <12000>;
302 regulator-initial-mode = <1>;
303 };
304
305 l13_reg: LDO13 {
306 regulator-name = "vdd_ldo13";
307 regulator-min-microvolt = <800000>;
308 regulator-max-microvolt = <1950000>;
309 regulator-always-on;
310 regulator-ramp-delay = <12000>;
311 regulator-initial-mode = <1>;
312 };
313
314 l14_reg: LDO14 {
315 regulator-name = "vdd_ldo14";
316 regulator-min-microvolt = <1800000>;
317 regulator-max-microvolt = <3375000>;
318 regulator-always-on;
319 regulator-ramp-delay = <12000>;
320 regulator-initial-mode = <1>;
321 };
322
323 l33_reg: LDO33 {
324 regulator-name = "vdd_ldo33";
325 regulator-min-microvolt = <800000>;
326 regulator-max-microvolt = <1950000>;
327 regulator-ramp-delay = <12000>;
328 regulator-always-on;
329 regulator-initial-mode = <3>;
330 };
331
332 l34_reg: LDO34 {
333 regulator-name = "vdd_ldo34";
334 regulator-min-microvolt = <1800000>;
335 regulator-max-microvolt = <3375000>;
336 regulator-ramp-delay = <12000>;
337 };
338
339 l35_reg: LDO35 {
340 regulator-name = "vmmc";
341 regulator-min-microvolt = <1800000>;
342 regulator-max-microvolt = <3375000>;
343 regulator-ramp-delay = <12000>;
344 };
345
346 l36_reg: LDO36 {
347 regulator-name = "vdd_ldo36";
348 regulator-min-microvolt = <500000>;
349 regulator-max-microvolt = <1300000>;
350 regulator-always-on;
351 regulator-ramp-delay = <12000>;
352 regulator-initial-mode = <1>;
353 };
354
355 l37_reg: LDO37 {
356 regulator-name = "vdd_ldo37";
357 regulator-min-microvolt = <3300000>;
358 regulator-max-microvolt = <3300000>;
359 regulator-ramp-delay = <12000>;
360 /* regulator-always-on; */
361 regulator-initial-mode = <3>;
362 };
363
364 l38_reg: LDO38 {
365 regulator-name = "VLDO38_PMIC_RCAM_AFVCC_2P8";
366 regulator-min-microvolt = <2800000>;
367 regulator-max-microvolt = <2800000>;
368 regulator-ramp-delay = <12000>;
369 };
370
371 l39_reg: LDO39 {
372 regulator-name = "vdd_ldo39";
373 regulator-min-microvolt = <800000>;
374 regulator-max-microvolt = <1950000>;
375 regulator-ramp-delay = <12000>;
376 regulator-always-on;
377 };
378
379 l40_reg: LDO40 {
380 regulator-name = "vdd_ldo40";
381 regulator-min-microvolt = <3000000>;
382 regulator-max-microvolt = <3000000>;
383 regulator-ramp-delay = <12000>;
384 regulator-initial-mode = <3>;
385 regulator-always-on;
386 };
387
388 l41_reg: LDO41 {
389 regulator-name = "VLDO41_PMIC_FCAM_AVDD_2P8";
390 regulator-min-microvolt = <2800000>;
391 regulator-max-microvolt = <2800000>;
392 regulator-ramp-delay = <12000>;
393 };
394
395 l42_reg: LDO42 {
396 regulator-name = "vdd_ldo42";
397 regulator-min-microvolt = <800000>;
398 regulator-max-microvolt = <1950000>;
399 regulator-ramp-delay = <12000>;
400 regulator-always-on;
401 };
402
403 l43_reg: LDO43 {
404 regulator-name = "vdd_ldo43";
405 regulator-min-microvolt = <500000>;
406 regulator-max-microvolt = <1300000>;
407 regulator-always-on;
408 regulator-ramp-delay = <12000>;
409 regulator-initial-mode = <1>;
410 };
411
412 l44_reg: LDO44 {
413 regulator-name = "VLDO44_PMIC_DCAM_DVDD_1P2";
414 regulator-min-microvolt = <1200000>;
415 regulator-max-microvolt = <1200000>;
416 regulator-ramp-delay = <12000>;
417 };
418 };
419 };
420 };
421
422
423 exynos_rgt {
424 compatible = "samsung,exynos-rgt";
425 };
426
427 mailbox_cp: mcu_ipc@11920000 {
428 compatible = "samsung,exynos-shd-ipc-mailbox";
429 reg = <0x0 0x11920000 0x180>;
430 mcu,name = "mcu_ipc_cp";
431 mcu,id = <0>;
432 interrupts = <0 40 0 >;
433 };
434
435 mailbox_gnss: mcu_ipc@11A00000 {
436 compatible = "samsung,exynos-shd-ipc-mailbox";
437 reg = <0x0 0x11A00000 0x180>;
438 mcu,name = "mcu_ipc_gnss";
439 mcu,id = <1>;
440 interrupts = <0 43 0>; /* INTREQ__MAILBOX_GNSS2AP */
441 };
442
443 gnss_pdata {
444 status = "okay";
445
446 compatible = "samsung,gnss_shdmem_if";
447 shmem,name = "KEPLER";
448 shmem,device_node_name = "gnss_ipc";
449
450 /* INTREQ__ALIVE_GNSS_ACTIVE, INTREQ__GNSS2AP_WDOG_RESET, INTREQ__GNSS2AP_WAKEUP, INTREQ__GNSS2AP */
451 interrupts = <0 27 0>, <0 81 0>, <0 80 0>, <0 79 0>;
452 interrupt-names = "ACTIVE", "WATCHDOG", "WAKEUP", "REQ_INIT";
453
454 memory-region = <&gnss_reserved>;
455 mbox_info = <&mailbox_gnss>;
456
457 mbx,int_ap2gnss_bcmd = <0>;
458 mbx,int_ap2gnss_req_fault_info = <1>;
459 mbx,int_ap2gnss_ipc_msg = <2>;
460 mbx,int_ap2gnss_ack_wake_set = <3>;
461 mbx,int_ap2gnss_ack_wake_clr = <4>;
462
463 mbx,irq_gnss2ap_bcmd = <0>;
464 mbx,irq_gnss2ap_rsp_fault_info = <1>;
465 mbx,irq_gnss2ap_ipc_msg = <2>;
466 mbx,irq_gnss2ap_req_wake_clr = <4>;
467
468 mbx,reg_bcmd_ctrl = <0>, <1>, <2>, <3>;
469
470 reg_rx_ipc_msg = <1 5>;
471 reg_tx_ipc_msg = <1 4>;
472 reg_rx_head = <1 3>;
473 reg_rx_tail = <1 2>;
474 reg_tx_head = <1 1>;
475 reg_tx_tail = <1 0>;
476 fault_info = <1 0x200000 0x180000>;
477
478 shmem,ipc_offset = <0x380000>;
479 shmem,ipc_size = <0x80000>;
480 shmem,ipc_reg_cnt = <32>;
481 };
482
483 gpio_keys {
484 status = "okay";
485 compatible = "gpio-keys";
486 #address-cells = <1>;
487 #size-cells = <0>;
488 pinctrl-names = "default";
489 pinctrl-0 = <&key_voldown &key_volup &key_power>;
490 button@1 {
491 label = "gpio-keys: KEY_VOLUMEDOWN";
492 linux,code = <114>;
493 gpios = <&gpa1 6 0xf>;
494 };
495 button@2 {
496 label = "gpio-keys: KEY_VOLUMEUP";
497 linux,code = <115>;
498 gpios = <&gpa1 5 0xf>;
499 };
500 button@3 {
501 label = "gpio-keys: KEY_POWER";
502 linux,code = <116>;
503 gpios = <&gpa1 7 0xf>;
504 gpio-key,wakeup = <1>;
505 };
506 };
507
508 dwmmc2@13550000 {
509 status = "okay";
510 num-slots = <1>;
511 supports-4bit;
512 supports-cmd23;
513 supports-highspeed;
514 sd-uhs-sdr50;
515 sd-uhs-sdr104;
516 card-detect-invert;
517 card-detect-gpio;
518 bypass-for-allpass;
519 card-init-hwacg-ctrl;
520 skip-init-mmc-scan;
521 skip-init-no-tray;
522 pm-ignore-notify;
523 qos-dvfs-level = <100000>;
524 fifo-depth = <0x40>;
525 desc-size = <4>;
526 card-detect-delay = <200>;
527 data-timeout = <200>;
528 hto-timeout = <80>;
529 samsung,dw-mshc-ciu-div = <3>;
530 clock-frequency = <800000000>;
531 samsung,dw-mshc-sdr-timing = <3 0 2 0>;
532 samsung,dw-mshc-ddr-timing = <3 0 2 1>;
533 samsung,dw-mshc-sdr50-timing = <3 0 4 2>;
534 samsung,dw-mshc-sdr104-timing = <3 0 3 0>;
535
536 num-ref-clks = <9>;
537 ciu_clkin = <25 50 50 25 50 100 200 50 50>;
538
539 /* Swapping clock drive strength */
540 clk-drive-number = <4>;
541 pinctrl-names = "default",
542 "fast-slew-rate-1x",
543 "fast-slew-rate-2x",
544 "fast-slew-rate-3x",
545 "fast-slew-rate-4x";
546 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4 &dwmmc2_cd_ext_irq>;
547 pinctrl-1 = <&sd2_clk_fast_slew_rate_1x>;
548 pinctrl-2 = <&sd2_clk_fast_slew_rate_2x>;
549 pinctrl-3 = <&sd2_clk_fast_slew_rate_3x>;
550 pinctrl-4 = <&sd2_clk_fast_slew_rate_4x>;
551
552 card-detect = <&gpa0 7 0xf>;
553 #address-cells = <1>;
554 #size-cells = <0>;
555 slot@0 {
556 reg = <0>;
557 bus-width = <4>;
558 disable-wp;
559 };
560 };
561
562 usb_notifier {
563 compatible = "samsung,usb-notifier";
564 udc = <&udc>;
565 };
566
567 usb_hs_tune:usb_hs_tune {
568 hs_tune_cnt = <12>;
569
570 /* value = <device host> */
571 hs_tune1 {
572 tune_name = "tx_vref";
573 tune_value = <0xf 0xf>;
574 };
575
576 hs_tune2 {
577 tune_name = "tx_pre_emp";
578 tune_value = <0x3 0x3>;
579 };
580
581 hs_tune3 {
582 tune_name = "tx_pre_emp_plus";
583 tune_value = <0x0 0x0>;
584 };
585
586 hs_tune4 {
587 tune_name = "tx_res";
588 tune_value = <0x3 0x3>;
589 };
590
591 hs_tune5 {
592 tune_name = "tx_rise";
593 tune_value = <0x3 0x3>;
594 };
595
596 hs_tune6 {
597 tune_name = "tx_hsxv";
598 tune_value = <0x3 0x3>;
599 };
600
601 hs_tune7 {
602 tune_name = "tx_fsls";
603 tune_value = <0x3 0x3>;
604 };
605
606 hs_tune8 {
607 tune_name = "rx_sqrx";
608 tune_value = <0x7 0x7>;
609 };
610
611 hs_tune9 {
612 tune_name = "compdis";
613 tune_value = <0x7 0x7>;
614 };
615
616 hs_tune10 {
617 tune_name = "otg";
618 tune_value = <0x2 0x2>;
619 };
620
621 hs_tune11 {
622 /* true : 1, false: 0 */
623 /* <enable_user_imp user_imp_value> */
624 tune_name = "enable_user_imp";
625 tune_value = <0x0 0x0>;
626 };
627
628 hs_tune12 {
629 /* PHY clk : 1 , FREE clk : 0 */
630 tune_name = "is_phyclock";
631 tune_value = <0x1 0x1>;
632 };
633 };
634
635 usb3_ss_tune:ss_tune {
636 ss_tune_cnt = <15>;
637
638 /* value = <device host> */
639 ss_tune1 {
640 tune_name = "tx0_term_offset";
641 tune_value = <0x0 0x0>;
642 };
643
644 ss_tune2 {
645 tune_name = "pcs_tx_swing_full";
646 tune_value = <0x7f 0x7f>;
647 };
648
649 ss_tune3 {
650 tune_name = "pcs_tx_deemph_6db";
651 tune_value = <0x1c 0x1c>;
652 };
653
654 ss_tune4 {
655 tune_name = "pcs_tx_deemph_3p5db";
656 tune_value = <0x1c 0x1c>;
657 };
658
659 ss_tune5 {
660 tune_name = "tx_vboost_lvl_sstx";
661 tune_value = <0x7 0x7>;
662 };
663
664 ss_tune6 {
665 tune_name = "tx_vboost_lvl";
666 tune_value = <0x4 0x4>;
667 };
668
669 ss_tune7 {
670 tune_name = "los_level";
671 tune_value = <0x9 0x9>;
672 };
673
674 ss_tune8 {
675 tune_name = "los_bias";
676 tune_value = <0x5 0x5>;
677 };
678
679 ss_tune9 {
680 tune_name = "pcs_rx_los_mask_val";
681 tune_value = <0x104 0x104>;
682 };
683
684 ss_tune10 {
685 tune_name = "tx_eye_height_cntl_en";
686 tune_value = <0x1 0x1>;
687 };
688
689 ss_tune11 {
690 tune_name = "pipe_tx_deemph_update_delay";
691 tune_value = <0x2 0x2>;
692 };
693
694 ss_tune12 {
695 tune_name = "pcs_tx_swing_full_sstx";
696 tune_value = <0x7f 0x7f>;
697 };
698 ss_tune13 {
699 tune_name = "rx_eq_fix_val";
700 tune_value = <0x2 0x2>;
701 };
702
703 ss_tune14 {
704 tune_name = "rx_decode_mode";
705 tune_value = <0x1 0x1>;
706 };
707
708 ss_tune15 {
709 tune_name = "decrese_ss_tx_imp";
710 tune_value = <0x1 0x1>;
711 };
712 };
713
714 usb3_hs_tune:usb3_hs_tune {
715 hs_tune_cnt = <10>;
716
717 /* value = <device host> */
718 hs_tune1 {
719 tune_name = "tx_pre_emp";
720 tune_value = <0x3 0x3>;
721 };
722
723 hs_tune2 {
724 tune_name = "tx_pre_emp_plus";
725 tune_value = <0x0 0x0>;
726 };
727
728 hs_tune3 {
729 tune_name = "tx_vref";
730 tune_value = <0x7 0x7>;
731 };
732
733 hs_tune4 {
734 tune_name = "rx_sqrx";
735 tune_value = <0x7 0x7>;
736 };
737
738 hs_tune5 {
739 tune_name = "tx_rise";
740 tune_value = <0x3 0x3>;
741 };
742
743 hs_tune6 {
744 tune_name = "compdis";
745 tune_value = <0x7 0x7>;
746 };
747
748 hs_tune7 {
749 tune_name = "tx_hsxv";
750 tune_value = <0x3 0x3>;
751 };
752
753 hs_tune8 {
754 tune_name = "tx_fsls";
755 tune_value = <0x3 0x3>;
756 };
757
758 hs_tune9 {
759 tune_name = "tx_res";
760 tune_value = <0x3 0x3>;
761 };
762
763 hs_tune10 {
764 tune_name = "utim_clk";
765 tune_value = <0x1 0x1>;
766 };
767 };
768
769 /* Secure RPMB */
770 ufs-srpmb {
771 compatible = "samsung,ufs-srpmb";
772 interrupts = <0 460 0>;
773 };
774
775 V_SYS: fixedregulator@0 {
776 compatible = "regulator-fixed";
777 regulator-name = "V_SYS";
778 regulator-min-microvolt = <4200000>;
779 regulator-max-microvolt = <4200000>;
780 regulator-boot-on;
781 regulator-always-on;
782 };
783
784
785 dummy_audio_codec: audio_codec_dummy {
786 status = "okay";
787 compatible = "snd-soc-dummy";
788 };
789
790 dummy_audio_cpu: audio_cpu_dummy {
791 compatible = "samsung,dummy-cpu";
792 status = "okay";
793 };
794
795 sound {
796 status = "okay";
797 compatible = "samsung,exynos9610-madera";
798
799 clock-names = "xclkout";
800 clocks = <&clock OSC_AUD>;
801 pinctrl-names = "default";
802 pinctrl-0 = <&xclkout0 &spk_id>;
803
804 cirrus,sysclk = <1 4 98304000>;
805 cirrus,dspclk = <8 4 147456000>;
806 cirrus,fll1-refclk = <1 0 26000000 98304000>;
807
808 cirrus,opclk = <3 0 12288000>;
809
810 gpios = <&gpm25 0 0>;
811
812 samsung,routing =
813 "HEADSETMIC", "MICBIAS1B",
814 "IN1BR", "HEADSETMIC",
815 "DMIC1", "MICBIAS2A",
816 "IN1AL", "DMIC1",
817 "DMIC2", "MICBIAS2A",
818 "IN2L", "DMIC2",
819 "DMIC3", "MICBIAS2B",
820 "IN2R", "DMIC3",
821 "RECEIVER", "EPOUTN",
822 "RECEIVER", "EPOUTP",
823 "HEADPHONE", "HPOUTL",
824 "HEADPHONE", "HPOUTR",
825 "AIF2 Playback", "OPCLK",
826 "AIF2 Capture", "OPCLK",
827 "VOUTPUT", "ABOX UAIF0 Playback",
828 "SPEAKER", "Left SPK",
829 "VOUTPUTCALL", "ABOX SIFS0 Playback",
830 "ABOX SIFS0 Capture", "VINPUTCALL";
831
832 samsung,codec = <&abox &abox_uaif_0 &abox_uaif_1 &abox_uaif_2
833 &abox_uaif_4 &abox_dsif &abox_spdy &cs35l41_left>;
834 samsung,prefix = "ABOX", "ABOX", "ABOX", "ABOX",
835 "ABOX", "ABOX", "ABOX", "SPK";
836 samsung,aux = <&abox_effect &abox_bt>;
837
838 rdma@0 {
839 cpu {
840 sound-dai = <&abox 0>;
841 };
842 platform {
843 sound-dai = <&abox_rdma_0>;
844 };
845 codec {
846 sound-dai = <&dummy_audio_codec>;
847 };
848 };
849 rdma@1 {
850 cpu {
851 sound-dai = <&abox 1>;
852 };
853 platform {
854 sound-dai = <&abox_rdma_1>;
855 };
856 codec {
857 sound-dai = <&dummy_audio_codec>;
858 };
859 };
860 rdma@2 {
861 cpu {
862 sound-dai = <&abox 2>;
863 };
864 platform {
865 sound-dai = <&abox_rdma_2>;
866 };
867 codec {
868 sound-dai = <&dummy_audio_codec>;
869 };
870 };
871 rdma@3 {
872 cpu {
873 sound-dai = <&abox 3>;
874 };
875 platform {
876 sound-dai = <&abox_rdma_3>;
877 };
878 codec {
879 sound-dai = <&dummy_audio_codec>;
880 };
881 };
882 rdma@4 {
883 cpu {
884 sound-dai = <&abox 4>;
885 };
886 platform {
887 sound-dai = <&abox_rdma_4>;
888 };
889 codec {
890 sound-dai = <&dummy_audio_codec>;
891 };
892 };
893 rdma@5 {
894 cpu {
895 sound-dai = <&abox 5>;
896 };
897 platform {
898 sound-dai = <&abox_rdma_5>;
899 };
900 codec {
901 sound-dai = <&dummy_audio_codec>;
902 };
903 };
904 rdma@6 {
905 cpu {
906 sound-dai = <&abox 6>;
907 };
908 platform {
909 sound-dai = <&abox_rdma_6>;
910 };
911 codec {
912 sound-dai = <&dummy_audio_codec>;
913 };
914 };
915 rdma@7 {
916 cpu {
917 sound-dai = <&abox 7>;
918 };
919 platform {
920 sound-dai = <&abox_rdma_7>;
921 };
922 codec {
923 sound-dai = <&dummy_audio_codec>;
924 };
925 };
926 wdma@0 {
927 cpu {
928 sound-dai = <&abox 8>;
929 };
930 platform {
931 sound-dai = <&abox_wdma_0>;
932 };
933 codec {
934 sound-dai = <&dummy_audio_codec>;
935 };
936 };
937 wdma@1 {
938 cpu {
939 sound-dai = <&abox 9>;
940 };
941 platform {
942 sound-dai = <&abox_wdma_1>;
943 };
944 codec {
945 sound-dai = <&dummy_audio_codec>;
946 };
947 };
948 wdma@2 {
949 cpu {
950 sound-dai = <&abox 10>;
951 };
952 platform {
953 sound-dai = <&abox_wdma_2>;
954 };
955 codec {
956 sound-dai = <&dummy_audio_codec>;
957 };
958 };
959 wdma@3 {
960 cpu {
961 sound-dai = <&abox 11>;
962 };
963 platform {
964 sound-dai = <&abox_wdma_3>;
965 };
966 codec {
967 sound-dai = <&dummy_audio_codec>;
968 };
969 };
970 wdma@4 {
971 cpu {
972 sound-dai = <&abox 12>;
973 };
974 platform {
975 sound-dai = <&abox_wdma_4>;
976 };
977 codec {
978 sound-dai = <&dummy_audio_codec>;
979 };
980 };
981 /** ToDo: enable dp_audio link after enabling DP Audio
982 * dp_audio@0 {
983 * cpu {
984 * sound-dai = <&dummy_audio_cpu>;
985 * };
986 * codec {
987 * sound-dai = <&dummy_audio_codec>;
988 * };
989 * };
990 */
991 uaif@0 {
992 format = "i2s";
993 cpu {
994 sound-dai = <&abox_uaif_0>;
995 };
996 codec {
997 sound-dai = <&cs47l35 0>;
998 };
999 };
1000 uaif@1 {
1001 format = "i2s";
1002 cpu {
1003 sound-dai = <&abox_uaif_1>;
1004 };
1005 codec {
1006 sound-dai = <&dummy_audio_codec>;
1007 };
1008 };
1009 uaif@2 {
1010 format = "i2s";
1011 cpu {
1012 sound-dai = <&abox_uaif_2>;
1013 };
1014 codec {
1015 sound-dai = <&cs47l35 2>;
1016 };
1017 };
1018 uaif@4 {
1019 format = "i2s";
1020 bitclock-master;
1021 frame-master;
1022 cpu {
1023 sound-dai = <&abox_uaif_4>;
1024 };
1025 codec {
1026 sound-dai = <&dummy_audio_codec>;
1027 };
1028 };
1029 dsif@0 {
1030 format = "pdm";
1031 cpu {
1032 sound-dai = <&abox_dsif>;
1033 };
1034 codec {
1035 sound-dai = <&dummy_audio_codec>;
1036 };
1037 };
1038 spdy@0 {
1039 cpu {
1040 sound-dai = <&abox_spdy>;
1041 };
1042 codec {
1043 sound-dai = <&dummy_audio_codec>;
1044 };
1045 };
1046 sifs0@0 {
1047 cpu {
1048 sound-dai = <&abox 13>;
1049 };
1050 codec {
1051 sound-dai = <&dummy_audio_codec>;
1052 };
1053 };
1054 sifs1@0 {
1055 cpu {
1056 sound-dai = <&abox 14>;
1057 };
1058 codec {
1059 sound-dai = <&dummy_audio_codec>;
1060 };
1061 };
1062 sifs2@0 {
1063 cpu {
1064 sound-dai = <&abox 15>;
1065 };
1066 codec {
1067 sound-dai = <&dummy_audio_codec>;
1068 };
1069 };
1070
1071 codec-left-amp@0 {
1072 format = "i2s";
1073
1074 cpu {
1075 sound-dai = <&cs47l35 1>;
1076 };
1077 codec {
1078 sound-dai = <&cs35l41_left 0>;
1079 };
1080 };
1081
1082 cpu-dsp-voice-control@0 {
1083 cpu {
1084 sound-dai = <&cs47l35 3>;
1085 };
1086 codec {
1087 sound-dai = <&dummy_audio_codec>;
1088 };
1089 };
1090
1091 cpu-dsp-trace@0 {
1092 cpu {
1093 sound-dai = <&cs47l35 4>;
1094 };
1095 codec {
1096 sound-dai = <&dummy_audio_codec>;
1097 };
1098 };
1099
1100 cpu-dsp2-text@0 {
1101 cpu {
1102 sound-dai = <&cs47l35 5>;
1103 };
1104 codec {
1105 sound-dai = <&dummy_audio_codec>;
1106 };
1107 };
1108
1109 cpu-dsp3-text@0 {
1110 cpu {
1111 sound-dai = <&cs47l35 6>;
1112 };
1113 codec {
1114 sound-dai = <&dummy_audio_codec>;
1115 };
1116 };
1117
1118 cpu-dsp1-text@0 {
1119 cpu {
1120 sound-dai = <&cs47l35 7>;
1121 };
1122 codec {
1123 sound-dai = <&dummy_audio_codec>;
1124 };
1125 };
1126 };
1127
1128 sleep_gpio {
1129 compatible = "samsung,exynos-sleepgpio";
1130 pinctrl-names = "default", "sleep";
1131 pinctrl-0 = <&sleep_top &sleep_fsys &sleep_shub &normal_alive &normal_cmgp>;
1132 pinctrl-1 = <&sleep_top &sleep_fsys &sleep_shub &sleep_alive>;
1133 };
1134
1135 exynos-bcmdbg {
1136 initial_run_bcm_ip = <0>, <1>, <2>, <3>, <4>, <6>, <7>, <8>, <9>, <10>,
1137 <11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>, <20>,
1138 <21>, <22>, <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>;
1139 };
1140 }; /* end of __overlay__ */
1141 }; /* end of fragment */
1142 }; /* end of root */
1143
1144 &i2c_0 {
1145 #address-cells = <1>;
1146 #size-cells = <0>;
1147 status = "okay";
1148 s2mu106-fuelgauge@3B {
1149 compatible = "samsung,s2mu106-fuelgauge";
1150 reg = <0x3B>;
1151 pinctrl-names = "default";
1152 pinctrl-0 = <&fuel_irq>;
1153 fuelgauge,fuel_int = <&gpa2 3 0>;
1154 fuelgauge,fuel_alert_vol = <3400>;
1155 fuelgauge,fuel_alert_soc = <1>;
1156 fuelgauge,type_str = "SDI";
1157 fuelgauge,model_type = <1>;
1158 };
1159
1160 usbpd-s2mu106@3C {
1161 compatible = "sec-usbpd,i2c";
1162 reg = <0x3C>;
1163 pinctrl-names = "default";
1164 pinctrl-0 = <&usbpd_irq>;
1165 usbpd,usbpd_int = <&gpa2 2 0>;
1166
1167 pdic-manager {
1168 /* sink */
1169 pdic,max_power = <5000>;
1170 pdic,op_power = <2500>;
1171 pdic,max_voltage = <6000>;
1172 pdic,max_current = <2000>;
1173 pdic,min_current = <500>;
1174
1175 pdic,giveback = <0>;
1176 pdic,usb_com_capable = <1>;
1177 pdic,no_usb_suspend = <1>;
1178
1179 /* source */
1180 source,max_voltage = <5000>;
1181 source,min_voltage = <4000>;
1182 source,max_power = <2500>;
1183
1184 /* sink cap */
1185 sink,capable_max_voltage = <5000>;
1186 };
1187 };
1188 };
1189
1190 &i2c_1 {
1191 #address-cells = <1>;
1192 #size-cells = <0>;
1193 status = "okay";
1194 s2mu106@3d {
1195 compatible = "samsung,s2mu106mfd";
1196 reg = <0x3d>;
1197 pinctrl-names = "default";
1198 pinctrl-0 = <&if_pmic_irq>;
1199 s2mu106,irq-gpio = <&gpa2 1 0>;
1200 s2mu106,wakeup;
1201
1202 muic {
1203 status = "okay";
1204 muic,uart_addr = "11850000.pinctrl";
1205 muic,uart_rxd = "gpq0-3";
1206 muic,uart_txd = "gpq0-4";
1207 };
1208 };
1209
1210 s2mu106-haptic {
1211 status = "okay";
1212 haptic,pwm_id = <1>;
1213 haptic,operation_mode = <2>; /* 0 : ERM_I2C, 1 : ERM_GPIO, 2 : LRA */
1214 haptic,hbst_en;
1215 haptic,hbst_automode;
1216 haptic,boost_level = <5000>;
1217 };
1218
1219 s2mcs02-charger@41 {
1220 compatible = "samsung,s2mcs02-charger";
1221 reg = <0x41>;
1222 default-clk = <100000000>;
1223 };
1224
1225 flash_led {
1226 /* Change here if you want to use FLED_EN pin
1227 fled-en1-gpio = <&gpg1 2 0>;
1228 fled-en2-gpio = <&gpg1 2 0>;
1229 fled-en3-gpio = <&gpg1 2 0>;
1230 fled-en4-gpio = <&gpg1 2 0>;
1231 */
1232 status = "okay";
1233 default_current = <50>;
1234 max_current = <200>;
1235 default_timer = <0>;
1236
1237 s2mu106-channel1 {
1238 id = <0>;
1239 /*
1240 current = <100>;
1241 timer = <200>;
1242 */
1243 };
1244
1245 s2mu106-channel2 {
1246 id = <1>;
1247 /*
1248 current = <100>;
1249 timer = <200>;
1250 */
1251 };
1252
1253 s2mu106-channel3 {
1254 id = <2>;
1255 /*
1256 current = <100>;
1257 timer = <200>;
1258 */
1259 };
1260 };
1261
1262 s2mu106-charger {
1263 status = "okay";
1264 battery,charger_name = "s2mu106-charger";
1265 battery,chg_gpio_en = <0>;
1266 battery,chg_polarity_en = <0>;
1267 battery,chg_gpio_status = <0>;
1268 battery,chg_polarity_status = <0>;
1269 battery,chg_float_voltage = <4350>;
1270 battery,chg_recharge_vcell = <4250>;
1271 battery,chg_full_vcell = <4300>;
1272 battery,full_check_type = <2>;
1273 battery,full_check_type_2nd = <2>;
1274 battery,input_current_limit = <
1275 500 450 500 1200 500 1200 1200 1000 1000 1000
1276 1000 500 500 1200 1000 500 450>;
1277 battery,fast_charging_current = <
1278 500 450 500 1200 500 1200 1200 1000 1000 1000
1279 1000 500 500 1200 1000 500 450>;
1280 battery,full_check_current_1st = <
1281 300 0 300 300 300 300 300 300 300 300
1282 300 300 300 300 300 300 0>;
1283 battery,full_check_current_2nd = <
1284 100 0 100 100 100 100 100 100 100 100
1285 100 100 100 100 100 100 0>;
1286 };
1287 };
1288
1289 &exynos_adc {
1290 status = "okay";
1291 cpu_thermistor {
1292 compatible = "murata,ncp03wf104";
1293 status = "okay";
1294 pullup-uv = <1800000>;
1295 pullup-ohm = <100000>;
1296 pulldown-ohm = <0>;
1297 io-channels = <&exynos_adc 0>;
1298 io-channel-names = "cpu_therm";
1299 };
1300 battery_thermistor {
1301 compatible = "murata,ncp15xh103";
1302 status = "okay";
1303 pullup-uv = <1800000>;
1304 pullup-ohm = <100000>;
1305 pulldown-ohm = <0>;
1306 io-channels = <&exynos_adc 1>;
1307 io-channel-names = "bat_therm";
1308 };
1309 pa_thermistor {
1310 compatible = "murata,ncp15xh103";
1311 status = "okay";
1312 pullup-uv = <1800000>;
1313 pullup-ohm = <0>;
1314 pulldown-ohm = <10000>;
1315 io-channels = <&exynos_adc 4>;
1316 io-channel-names = "pa_therm";
1317 connected-positive;
1318 };
1319 board_thermistor {
1320 compatible = "murata,ncp03wf104";
1321 status = "okay";
1322 pullup-uv = <1800000>;
1323 pullup-ohm = <100000>;
1324 pulldown-ohm = <0>;
1325 io-channels = <&exynos_adc 7>;
1326 io-channel-names = "board_therm";
1327 };
1328 usb_con_thermistor {
1329 compatible = "murata,ncp03wf104";
1330 status = "okay";
1331 pullup-uv = <1800000>;
1332 pullup-ohm = <100000>;
1333 pulldown-ohm = <0>;
1334 io-channels = <&exynos_adc 8>;
1335 io-channel-names = "usb_con_therm";
1336 };
1337 };
1338
1339 &i2c_2 {
1340 #address-cells = <1>;
1341 #size-cells = <0>;
1342 status = "okay";
1343
1344 samsung,i2c-max-bus-freq = <600000>;
1345
1346 sec-nfc@27 {
1347 compatible = "sec-nfc";
1348 reg = <0x27>;
1349
1350 sec-nfc,ven-gpio = <&gpg0 0 0>;
1351 sec-nfc,firm-gpio = <&gpg0 2 0>;
1352
1353 sec-nfc,irq-gpio = <&gpa1 2 0>;
1354 sec-nfc,clk_req-gpio = <&gpg0 1 0>;
1355 sec-nfc,ldo_en = <&gpm22 0 0>;
1356 sec-nfc,pmic-ldo = "vdd_ldo37";
1357
1358 clock-names = "OSC_NFC";
1359 clocks = <&clock OSC_NFC>;
1360 pinctrl-names = "default";
1361 pinctrl-0 = <&xclkout1 &nfc_pd>;
1362 };
1363 };
1364
1365 &sec_pwm {
1366 status = "okay";
1367 pinctrl-names = "default";
1368 pinctrl-0 = <&motor_pwm>;
1369 };
1370
1371
1372 &fmp_0 {
1373 exynos,block-type = "sda";
1374 exynos,fips-block_offset = <5>;
1375 };
1376
1377 &contexthub_0 {
1378 /* chub irq pin lists */
1379 chub-irq-pin = <162>;
1380 clocks =
1381 /* SHUB */
1382 <&clock UMUX_CLKCMU_SHUB_BUS>,
1383 /* MAG. SENSOR : AK09918C */
1384 <&clock CMGP01_USI>,
1385 /* PROX. SENSOR : TMD3702 */
1386 <&clock CMGP03_USI>,
1387 /* ALS SENSOR : BH1726 */
1388 <&clock CMGP_I2C>;
1389 clock-names =
1390 "chub_bus",
1391 "cmgp_usi01",
1392 "cmgp_usi03",
1393 "cmgp_i2c";
1394 os-type = "os.checked_0.bin";
1395 };
1396
1397 &pinctrl_0 {
1398 pmic_irq: pmic-irq {
1399 samsung,pins = "gpa2-0";
1400 samsung,pin-pud = <3>;
1401 samsung,pin-drv = <3>;
1402 };
1403
1404 sub_pmic_irq: sub-pmic-irq {
1405 samsung,pins = "gpa1-3";
1406 samsung,pin-function = <0>;
1407 samsung,pin-pud = <0>;
1408 samsung,pin-drv = <0>;
1409 };
1410
1411
1412 key_voldown: key-voldown {
1413 samsung,pins = "gpa1-6";
1414 samsung,pin-function = <0xf>;
1415 samsung,pin-pud = <0>;
1416 samsung,pin-drv = <0>;
1417 };
1418
1419 key_volup: key-volup {
1420 samsung,pins = "gpa1-5";
1421 samsung,pin-function = <0xf>;
1422 samsung,pin-pud = <0>;
1423 samsung,pin-drv = <0>;
1424 };
1425
1426 key_power: key-power {
1427 samsung,pins = "gpa1-7";
1428 samsung,pin-function = <0xf>;
1429 samsung,pin-pud = <0>;
1430 samsung,pin-drv = <0>;
1431 };
1432
1433 dwmmc2_cd_ext_irq: dwmmc2_cd_ext_irq {
1434 samsung,pins = "gpa0-7";
1435 samsung,pin-function = <0xf>;
1436 samsung,pin-pud = <0>;
1437 samsung,pin-drv = <3>;
1438 };
1439
1440 attn_irq: attn-irq {
1441 samsung,pins = "gpa2-4";
1442 samsung,pin-function = <0xf>;
1443 samsung,pin-pud = <0>;
1444 samsung,pin-drv = <0>;
1445 };
1446
1447 attn_input: attn-input {
1448 samsung,pins = "gpa2-4";
1449 samsung,pin-function = <0>;
1450 samsung,pin-pud = <1>;
1451 };
1452
1453 if_pmic_irq: if-pmic-irq {
1454 samsung,pins = "gpa2-1";
1455 samsung,pin-function = <0>;
1456 samsung,pin-pud = <0>;
1457 samsung,pin-drv = <0>;
1458 };
1459
1460 fuel_irq: fuel-irq {
1461 samsung,pins = "gpa2-3";
1462 samsung,pin-function = <0>;
1463 samsung,pin-pud = <0>;
1464 samsung,pin-drv = <0>;
1465 };
1466
1467 usbpd_irq: usbpd-irq {
1468 samsung,pins = "gpa2-2";
1469 samsung,pin-function = <0xf>;
1470 samsung,pin-pud = <3>;
1471 samsung,pin-drv = <3>;
1472 };
1473 /* TODO: Need to check pin number
1474 small_charger_irq: small-charger-irq {
1475 samsung,pins = "gpa2-5";
1476 samsung,pin-function = <0>;
1477 samsung,pin-pud = <0>;
1478 samsung,pin-drv = <0>;
1479 };
1480 */
1481 cap_int_status: cap_int_status {
1482 samsung,pins = "gpa2-6";
1483 samsung,pin-function = <0>;
1484 samsung,pin-val = <1>;
1485 samsung,pin-pud = <3>;
1486 };
1487
1488 lra_int_status: lra_int_status {
1489 samsung,pins = "gpa2-7";
1490 samsung,pin-function = <0>;
1491 samsung,pin-val = <1>;
1492 samsung,pin-pud = <3>;
1493 };
1494
1495 sleep_alive: sleep-state {
1496 PIN_EINT_PUD(gpa0-2, DIS); /* SPK_PA_INT */
1497 PIN_IN_PUD(gpa0-3, DIS); /* SC_INTB */
1498 PIN_IN_PUD(gpa0-4, DIS); /* IF_PMIC_MRSTB */
1499 PIN_EINT_PUD(gpa0-6, DIS); /* CODEC_IRQ_N */
1500 PIN_EINT_PUD(gpa0-7, DIS); /* SD_SIM_DET */
1501
1502 //PIN_IN_PUD(gpa1-1, DOWN); /* FP_RST_NT */
1503 PIN_EINT_PUD(gpa1-2, DIS); /* NFC_IRQ */
1504 //PIN_IN_PUD(gpa1-3, DOWN); /* TP_RST_N */
1505 PIN_IN_PUD(gpa1-5, DIS); /* KEY_VOL_UP */
1506 PIN_IN_PUD(gpa1-6, DIS); /* KEY_VOL_DOWN */
1507 //PIN_INT_PUD(gpa1-7, DIS); /* PMIC_ONOB */
1508
1509 //PIN_EINT_PUD(gpa2-0, DIS); /* PMIC_IRQB */
1510 //PIN_EINT_PUD(gpa2-1, DIS); /* IF_PMIC_IRQB */
1511 PIN_EINT_PUD(gpa2-2, DIS); /* IF_PMIC_INTB */
1512 //PIN_EINT_PUD(gpa2-3, DIS); /* FG_INTB */
1513 PIN_EINT_PUD(gpa2-4, DIS); /* TP_INT_B */
1514 //PIN_IN_PUD(gpa2-5, DOWN); /* MOTOR_RSTN */
1515 PIN_EINT_PUD(gpa2-6, DIS); /* SAR_PS_INT */
1516 PIN_EINT_PUD(gpa2-7, DIS); /* MOTOR_INTN */
1517
1518 PIN_FUNC_PUD(gpq0-2, UP); /* SPEEDY_PMIC */
1519 PIN_IN_PUD(gpq0-3, DOWN); /* AP_UART0_RXD */
1520 PIN_IN_PUD(gpq0-4, UP); /* AP_UART0_TXD */
1521 };
1522
1523 normal_alive: normal-state {
1524 PIN_EINT_PUD(gpa0-2, DIS); /* SPK_PA_INT */
1525 PIN_IN_PUD(gpa0-3, DIS); /* SC_INTB */
1526 PIN_IN_PUD(gpa0-4, DIS); /* IF_PMIC_MRSTB */
1527 PIN_EINT_PUD(gpa0-6, DIS); /* CODEC_IRQ_N */
1528 PIN_EINT_PUD(gpa0-7, DIS); /* SD_SIM_DET */
1529
1530 PIN_EINT_PUD(gpa1-2, DIS); /* NFC_IRQ */
1531 PIN_EINT_PUD(gpa1-5, DIS); /* KEY_VOL_UP */
1532 PIN_EINT_PUD(gpa1-6, DIS); /* KEY_VOL_DOWN */
1533
1534 PIN_EINT_PUD(gpa2-2, DIS); /* IF_PMIC_INTB */
1535 PIN_EINT_PUD(gpa2-4, DIS); /* TP_INT_B */
1536 PIN_EINT_PUD(gpa2-6, DIS); /* SAR_PS_INT */
1537 PIN_EINT_PUD(gpa2-7, DIS); /* MOTOR_INTN */
1538
1539 PIN_FUNC_PUD(gpq0-2, UP); /* SPEEDY_PMIC */
1540 PIN_FUNC_PUD(gpq0-3, DOWN); /* AP_UART0_RXD */
1541 PIN_FUNC_PUD(gpq0-4, UP); /* AP_UART0_TXD */
1542 };
1543 };
1544
1545 &pinctrl_1 {
1546 sleep_cmgp: sleep-state {
1547 PIN_IN_PUD(gpm2-0, DIS); /* LCD_SCL */
1548 PIN_IN_PUD(gpm3-0, DIS); /* LCD_SCA */
1549 PIN_IN_PUD(gpm4-0, DIS); /* SENSOR_SCL_1.8V */
1550 PIN_IN_PUD(gpm5-0, DIS); /* SENSOR_SDA_1.8V */
1551 PIN_IN_PUD(gpm6-0, DIS); /* LT_SENSOR_SCL_1.8V */
1552 PIN_IN_PUD(gpm7-0, DIS); /* LT_SENSOR_SDA_1.8V */
1553 PIN_IN_PUD(gpm8-0, DIS); /* MOTOR_I2C_SCL */
1554 PIN_IN_PUD(gpm9-0, DIS); /* AP_UART0_TXD */
1555 PIN_IN_PUD(gpm10-0, DIS); /* SAR_SENSOR_SCL */
1556 PIN_IN_PUD(gpm11-0, DIS); /* SAR_SENSOR_SDA */
1557 PIN_IN_PUD(gpm16-0, DOWN); /* NC */
1558 PIN_IN_PUD(gpm17-0, DOWN); /* NC */
1559 PIN_EINT_PUD(gpm20-0, DIS); /* PSENSOR_INT */
1560 //PIN_IN_PUD(gpm22-0, DOWN); /* NFC_PVDDEN */
1561 PIN_IN_PUD(gpm25-0, DIS); /* SPK_ID */
1562 };
1563
1564 normal_cmgp: normal-cmgp {
1565 //PIN_EINT_PUD(gpm20-0, UP); /* PSENSOR_INT */
1566 PIN_FUNC_PUD(gpm2-0, DIS); /* LCD_SCL */
1567 PIN_FUNC_PUD(gpm3-0, DIS); /* LCD_SCA */
1568 PIN_FUNC_PUD(gpm4-0, UP); /* SENSOR_SCL_1.8V */
1569 PIN_FUNC_PUD(gpm5-0, UP); /* SENSOR_SDA_1.8V */
1570 PIN_FUNC_PUD(gpm6-0, UP); /* LT_SENSOR_SCL_1.8V */
1571 PIN_FUNC_PUD(gpm7-0, UP); /* LT_SENSOR_SDA_1.8V */
1572 PIN_FUNC_PUD(gpm8-0, DIS); /* MOTOR_I2C_SCL */
1573 PIN_FUNC_PUD(gpm9-0, DIS); /* MOTOR_I2C_SDA */
1574 PIN_FUNC_PUD(gpm10-0, DIS); /* SAR_SENSOR_SCL */
1575 PIN_FUNC_PUD(gpm11-0, DIS); /* SAR_SENSOR_SDA */
1576 PIN_EINT_PUD(gpm20-0, DIS); /* PSENSOR_INT */
1577 PIN_IN_PUD(gpm25-0, DIS); /* SPK_ID */
1578 };
1579 };
1580
1581 &pinctrl_2 {
1582 sleep_aud: sleep-state {
1583 PIN_SLP(gpb0-0, IN, DOWN); /* NC */
1584 PIN_SLP(gpb0-1, IN, DOWN); /* I2S0_CODEC_BCLK */
1585 PIN_SLP(gpb0-2, IN, DOWN); /* I2S0_CODEC_WS */
1586 PIN_SLP(gpb0-3, IN, DOWN); /* I2S0_CODEC_SDO */
1587 PIN_SLP(gpb0-4, IN, DOWN); /* I2S0_CODEC_SDI */
1588
1589 PIN_SLP(gpb1-0, IN, DOWN); /* NC */
1590 PIN_SLP(gpb1-1, IN, DOWN); /* NC */
1591 PIN_SLP(gpb1-2, IN, DOWN); /* NC */
1592 PIN_SLP(gpb1-3, IN, DOWN); /* NC */
1593
1594 PIN_SLP(gpb2-0, IN, DOWN); /* I2S2_CODEC_BCLK */
1595 PIN_SLP(gpb2-1, IN, DOWN); /* I2S2_CODEC_WS */
1596 PIN_SLP(gpb2-2, IN, DOWN); /* I2S2_CODEC_SDO */
1597 PIN_SLP(gpb2-3, IN, DOWN); /* I2S2_CODEC_SDI */
1598 PIN_SLP(gpb2-4, IN, DOWN); /* FM_SPDY_S620 */
1599 };
1600 };
1601
1602 &pinctrl_3 {
1603 sleep_fsys: sleep-fsys {
1604 PIN_SLP(gpf0-0, PREV, DIS); /* UFS_EMBD_REFCLK_OUT */
1605 PIN_SLP(gpf0-1, PREV, DIS); /* UFS_EMBD_RESETN */
1606 };
1607 };
1608
1609 &pinctrl_4 {
1610 /* Warm reset information from AP */
1611 pm_wrsti: pm-wrsti {
1612 samsung,pins = "gpg0-7";
1613 samsung,pin-con-pdn = <3>;
1614 };
1615
1616 motor_pwm: motor_pwm {
1617 samsung,pins = "gpg4-2";
1618 samsung,pin-function = <2>;
1619 samsung,pin-pud = <1>;
1620 samsung,pin-drv = <0>;
1621 };
1622
1623 vdd_on: vdd-on {
1624 samsung,pins ="gpg3-4";
1625 samsung,pin-function = <1>;
1626 samsung,pin-val = <1>;
1627 samsung,pin-pud = <3>;
1628 };
1629
1630 vdd_off: vdd-off {
1631 samsung,pins ="gpg3-4";
1632 samsung,pin-function = <0>;
1633 samsung,pin-val = <0>;
1634 samsung,pin-pud = <1>;
1635 };
1636
1637 lcd_reset: lcd_reset {
1638 samsung,pins = "gpg1-4";
1639 samsung,pin-function = <1>;
1640 samsung,pin-pud = <3>;
1641 samsung,pin-val = <1>;
1642 samsung,pin-con-pdn =<3>;
1643 samsung,pin-pud-pdn = <3>;
1644 };
1645
1646 codec_reset: codec-reset {
1647 samsung,pins ="gpg3-2";
1648 samsung,pin-pud = <0>;
1649 samsung,pin-con-pdn =<3>;
1650 samsung,pin-pud-pdn = <0>;
1651 };
1652
1653 codec_en: codec_en {
1654 samsung,pins = "gpg1-1";
1655 samsung,pin-function = <1>;
1656 samsung,pin-pud = <3>;
1657 samsung,pin-val = <1>;
1658 samsung,pin-con-pdn =<3>;
1659 samsung,pin-pud-pdn = <3>;
1660 };
1661
1662 pa_reset: pa-reset {
1663 samsung,pins ="gpg3-3";
1664 samsung,pin-con-pdn =<3>;
1665 samsung,pin-pud-pdn = <3>;
1666 };
1667
1668 nfc_pd: nfc-pd {
1669 samsung,pins ="gpg0-0";
1670 samsung,pin-function = <1>;
1671 samsung,pin-pud = <0>;
1672 samsung,pin-con-pdn =<3>;
1673 samsung,pin-pud-pdn = <0>;
1674 };
1675
1676 sleep_top: sleep-top {
1677 PIN_SLP(gpp0-0, IN, DIS); /* I2C0_FG_PMIC_SDA */
1678 PIN_SLP(gpp0-1, IN, DIS); /* I2C0_FG_PMIC_SCL */
1679 PIN_SLP(gpp0-2, IN, DIS); /* I2C1_IF_PMIC_SDA */
1680 PIN_SLP(gpp0-3, IN, DIS); /* I2C1_IF_PMIC_SCL */
1681
1682 /* Add 18.12.31 start */
1683 PIN_SLP(gpp0-4, IN, DIS); /* I2C2_NFC_SDA */
1684 PIN_SLP(gpp0-5, IN, DIS); /* I2C2_NFC_SCL */
1685 PIN_SLP(gpp0-6, IN, DOWN); /* N.C. */
1686 PIN_SLP(gpp0-7, IN, DOWN); /* N.C. */
1687
1688 PIN_SLP(gpp1-0, IN, DIS); /* I2C4_TSP_SDA */
1689 PIN_SLP(gpp1-1, IN, DIS); /* I2C4_TSP_SCL */
1690 PIN_SLP(gpp1-2, IN, DOWN); /* N.C. */
1691 PIN_SLP(gpp1-3, IN, DOWN); /* N.C. */
1692 PIN_SLP(gpp1-4, IN, DOWN); /* N.C. */
1693 PIN_SLP(gpp1-5, IN, DOWN); /* N.C. */
1694
1695 PIN_SLP(gpc0-0, IN, DIS); /* I2C_CAM0_REAR_MAIN_SDA */
1696 PIN_SLP(gpc0-1, IN, DIS); /* I2C_CAM0_REAR_MAIN_SCL */
1697 PIN_SLP(gpc0-2, IN, DIS); /* I2C_CAM1_REAR_SUB_SDA */
1698 PIN_SLP(gpc0-3, IN, DIS); /* I2C_CAM1_REAR_SUB_SCL */
1699 PIN_SLP(gpc0-4, IN, DIS); /* I2C_CAM2_FRONT_SDA */
1700 PIN_SLP(gpc0-5, IN, DIS); /* I2C_CAM2_FRONT_SCL */
1701 PIN_SLP(gpc0-6, IN, DOWN); /* N.C. */
1702 PIN_SLP(gpc0-7, IN, DOWN); /* N.C. */
1703 /* Add 18.12.31 end */
1704
1705 /* ADD 19.01.01 start */
1706 PIN_SLP(gpc1-2, IN, DOWN); /* N.C. */
1707
1708 PIN_SLP(gpc2-3, PREV, DIS); /* DISP_TES added 19.01.05 */
1709 PIN_SLP(gpc2-4, IN, DOWN); /* N.C. */
1710
1711 PIN_SLP(gpg0-0, PREV, DIS); /* NFC_PD */
1712
1713 //PIN_SLP(gpg0-1, PREV, DIS); /* NFC_CLKREQ */
1714 //PIN_SLP(gpg0-2, PREV, DIS); /* NFC_WAKE */
1715 /* ADD 19.01.01 end t*/
1716
1717 PIN_SLP(gpg0-7, PREV, DIS); /* PMIC_WRSTBI */
1718
1719 //PIN_SLP(gpg1-1, PREV, DIS); /* VDD_CODEC_EN */
1720 PIN_SLP(gpg1-4, PREV, DIS); /* LCD_RESET_N */
1721
1722 //PIN_SLP(gpg2-0, PREV, DIS); /* FP_LDO_EN_3V3 */
1723 //PIN_SLP(gpg2-1, PREV, DIS); /* LDO_BL_EN */
1724 //PIN_SLP(gpg2-2, PREV, DIS); /* FP_LDOEN_1V8 */
1725 //PIN_SLP(gpg2-3, PREV, DIS); /* FCAM_AVDD_EN */
1726 //PIN_SLP(gpg2-4, PREV, DIS); /* FCAM_DVDD_EN */
1727 //PIN_SLP(gpg2-5, PREV, DIS); /* CAM_OVDD_EN */
1728 //PIN_SLP(gpg2-6, PREV, DIS); /* RCAM_MAIN_AVDD_EN */
1729 //PIN_SLP(gpg2-7, PREV, DIS); /* RCAM_DVDD_EN */
1730
1731 //PIN_SLP(gpg3-0, PREV, DIS); /* LCD_BIAS_ENN */
1732 //PIN_SLP(gpg3-1, PREV, DIS); /* LCD_BIAS_ENP */
1733 //PIN_SLP(gpg3-3, PREV, DIS); /* AUDIO_PA_RST */
1734 //PIN_SLP(gpg3-4, PREV, DIS); /* LCD_LDO_1V8_En */
1735
1736 //PIN_SLP(gpg4-0, PREV, DIS); /* XBOOTLDO */
1737 };
1738 };
1739
1740 &pinctrl_5 {
1741 sleep_shub: sleep-shub {
1742 PIN_SLP(gph0-0, IN, DOWN); /* ACC_SPI_CLK */
1743 PIN_SLP(gph0-1, IN, DOWN); /* ACC_SPI_MOSI */
1744 PIN_SLP(gph0-2, IN, DOWN); /* ACC_SPI_MISO */
1745 PIN_SLP(gph0-3, IN, DOWN); /* ACC_SPI_CS_N */
1746 PIN_SLP(gph1-0, IN, DOWN); /* ACCEL_GRY0_INT1 */
1747 PIN_SLP(gph1-1, IN, DOWN); /* ACCEL_GRY0_INT2 */
1748 PIN_SLP(gph1-2, IN, DOWN); /* LIGHT_INT */
1749 };
1750 };
1751
1752 &udc {
1753 status = "okay";
1754 };
1755
1756 &usbdrd_dwc3 {
1757 dr_mode = "otg";
1758 maximum-speed = "high-speed";
1759 };
1760
1761 &usbdrd_phy {
1762 status = "okay";
1763 usb3phy-isolation = <1>;
1764
1765 hs_tune_param = <&usb_hs_tune>;
1766 };
1767
1768 &usbdrd3_phy {
1769 status = "okay";
1770 usb3phy-isolation = <1>;
1771
1772 hs_tune_param = <&usb3_hs_tune>;
1773 ss_tune_param = <&usb3_ss_tune>;
1774 };
1775
1776 &serial_0 {
1777 status = "okay";
1778 };
1779
1780 &dsim_0 {
1781 lcd_info = <&nt36672a>;
1782 /* reset, lcd_bias_enp, lcd_bias_enn, lcd_bl_en*/
1783 gpios = <&gpg1 4 0x1>, <&gpg3 1 0x1>, <&gpg3 0 0x1>, <&gpg2 1 0x1>;
1784 pinctrl-names = "lcd_reset";
1785 pinctrl-0 = <&lcd_reset>;
1786 };
1787
1788 /* USI_0_SHUB */
1789 &usi_0_shub {
1790 usi_v2_mode = "spi";
1791 status = "disabled";
1792 };
1793
1794 /* USI_SHUB_0_I2C */
1795 &usi_0_shub_i2c {
1796 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1797 status = "disabled";
1798 };
1799
1800 /* USI_0_CMGP */
1801 &usi_0_cmgp {
1802 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1803 usi_v2_mode = "i2c";
1804 status = "okay";
1805 };
1806
1807 /* USI_0_CMGP_I2C */
1808 &usi_0_cmgp_i2c {
1809 usi_v2_mode = "i2c";
1810 status = "okay";
1811 };
1812
1813 /* USI_1_CMGP */
1814 &usi_1_cmgp {
1815 usi_v2_mode = "i2c";
1816 status = "okay";
1817 };
1818
1819 /* USI_1_CMGP_I2C */
1820 &usi_1_cmgp_i2c {
1821 usi_v2_mode = "i2c";
1822 status = "okay";
1823 };
1824
1825 /* USI_2_CMGP */
1826 &usi_2_cmgp {
1827 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1828 usi_v2_mode = "i2c";
1829 status = "okay";
1830 };
1831
1832 /* USI_2_CMGP_I2C */
1833 &usi_2_cmgp_i2c {
1834 usi_v2_mode = "i2c";
1835 status = "okay";
1836 };
1837
1838 /* USI_3_CMGP */
1839 &usi_3_cmgp {
1840 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1841 status = "disabled";
1842 };
1843
1844 /* USI_3_CMGP_I2C */
1845 &usi_3_cmgp_i2c {
1846 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1847 status = "disabled";
1848 };
1849
1850 /* USI_4_CMGP */
1851 &usi_4_cmgp {
1852 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1853 status = "disabled";
1854 };
1855
1856 /* USI_4_CMGP_I2C */
1857 &usi_4_cmgp_i2c {
1858 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1859 status = "disabled";
1860 };
1861
1862 /* USI_PERI_UART */
1863 &usi_peri_uart {
1864 usi_v2_mode = "uart";
1865 status = "okay";
1866 };
1867
1868 /* USI_PERI_CAMI2C_0 */
1869 &usi_peri_cami2c_0 {
1870 usi_v2_mode = "i2c";
1871 status = "okay";
1872 };
1873
1874 /* USI_PERI_CAMI2C_1 */
1875 &usi_peri_cami2c_1 {
1876 usi_v2_mode = "i2c";
1877 status = "okay";
1878 };
1879
1880 /* USI_PERI_CAMI2C_2 */
1881 &usi_peri_cami2c_2 {
1882 usi_v2_mode = "i2c";
1883 status = "okay";
1884 };
1885
1886 /* USI_PERI_CAMI2C_3 */
1887 &usi_peri_cami2c_3 {
1888 usi_v2_mode = "i2c";
1889 status = "okay";
1890 };
1891
1892 /* USI_PERI_SPI_0 */
1893 &usi_peri_spi_0 {
1894 usi_v2_mode = "spi";
1895 status = "okay";
1896 };
1897
1898 /* USI_PERI_SPI_1 */
1899 &usi_peri_spi_1 {
1900 usi_v2_mode = "spi";
1901 status = "okay";
1902 };
1903
1904 /* USI_PERI_USI_0 */
1905 &usi_peri_usi_0 {
1906 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1907 status = "disabled";
1908 };
1909
1910 /* USI_PERI_USI_0_I2C */
1911 &usi_peri_usi_0_i2c {
1912 /* usi_v2_mode = "i2c" or "spi" or "uart" */
1913 status = "disabled";
1914 };
1915
1916 /* USI_PERI_SPI_2 */
1917 &usi_peri_spi_2 {
1918 usi_v2_mode = "spi";
1919 status = "okay";
1920 };
1921
1922 &spi_6 {
1923 status = "okay";
1924 pinctrl-names = "default";
1925 pinctrl-0 = <&spi6_bus &spi6_cs_func &pa_reset>;
1926 /*cs-gpios = <&gpp2 3 0>;*/
1927 /*gpp2[3]*/
1928 /*num-cs = <1>;*/
1929 #address-cells = <1>;
1930 #size-cells = <0>;
1931 cs35l41_left: cs35l41@0 {
1932 compatible = "cirrus,cs35l41";
1933 reg = <0x0>;
1934
1935 spi-max-frequency = <9600000>;
1936
1937 interrupts = <2 0 0>;
1938 interrupt-controller;
1939 interrupt-parent = <&gpa0>;
1940 reset-gpios = <&gpg3 3 0>;
1941 #sound-dai-cells = <1>;
1942
1943 VA-supply = <&l42_reg>;
1944 VP-supply = <&V_SYS>;
1945
1946 cirrus,boost-peak-milliamp = <4500>;
1947 cirrus,boost-ind-nanohenry = <1000>;
1948 cirrus,boost-cap-microfarad = <15>;
1949 cirrus,asp-sdout-hiz = <0x1>;
1950 cirrus,gpio-config2 {
1951 cirrus,gpio-src-select = <0x4>;
1952 cirrus,gpio-output-enable;
1953 };
1954
1955 adsps {
1956 #address-cells = <1>;
1957 #size-cells = <0>;
1958 prince_l_dsp: adsp@2b80000 {
1959 reg = <0x2b80000>;
1960 firmware {
1961 protectionsp_default {
1962 cirrus,full-name;
1963 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
1964 cirrus,bin-file = "cs35l41-dsp1-spk-prot-music-aac.bin";
1965 };
1966 protectionsp_music_aac {
1967 cirrus,full-name;
1968 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
1969 cirrus,bin-file = "cs35l41-dsp1-spk-prot-music-aac.bin";
1970 };
1971 protectionsp_indmusic_aac {
1972 cirrus,full-name;
1973 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
1974 cirrus,bin-file = "cs35l41-dsp1-spk-prot-indmusic-aac.bin";
1975 };
1976 protectionsp_voice_aac {
1977 cirrus,full-name;
1978 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
1979 cirrus,bin-file = "cs35l41-dsp1-spk-prot-voice-aac.bin";
1980 };
1981 protectionsp_ringtone_aac {
1982 cirrus,full-name;
1983 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
1984 cirrus,bin-file = "cs35l41-dsp1-spk-prot-ringtone-aac.bin";
1985 };
1986 protectionsp_notification_aac {
1987 cirrus,full-name;
1988 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
1989 cirrus,bin-file = "cs35l41-dsp1-spk-prot-notification-aac.bin";
1990 };
1991 protectionsp_music_qisheng {
1992 cirrus,full-name;
1993 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
1994 cirrus,bin-file = "cs35l41-dsp1-spk-prot-music-qisheng.bin";
1995 };
1996 protectionsp_indmusic_qisheng {
1997 cirrus,full-name;
1998 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
1999 cirrus,bin-file = "cs35l41-dsp1-spk-prot-indmusic-qisheng.bin";
2000 };
2001 protectionsp_voice_qisheng {
2002 cirrus,full-name;
2003 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
2004 cirrus,bin-file = "cs35l41-dsp1-spk-prot-voice-qisheng.bin";
2005 };
2006 protectionsp_ringtone_qisheng{
2007 cirrus,full-name;
2008 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
2009 cirrus,bin-file = "cs35l41-dsp1-spk-prot-ringtone-qisheng.bin";
2010 };
2011 protectionsp_notification_qisheng {
2012 cirrus,full-name;
2013 cirrus,wmfw-file = "cs35l41-dsp1-prot.wmfw";
2014 cirrus,bin-file = "cs35l41-dsp1-spk-prot-notification-qisheng.bin";
2015 };
2016 calibration_aac {
2017 cirrus,full-name;
2018 cirrus,wmfw-file = "cs35l41-dsp1-diag.wmfw";
2019 cirrus,bin-file = "cs35l41-dsp1-aac-cali.bin";
2020 };
2021 calibration_qisheng{
2022 cirrus,full-name;
2023 cirrus,wmfw-file = "cs35l41-dsp1-diag.wmfw";
2024 cirrus,bin-file = "cs35l41-dsp1-qissheng-cali.bin";
2025 };
2026 };
2027 };
2028 };
2029 controller-data {
2030 /*cs-gpio = <gpm8 0 0>*/
2031 /*cs-gpios = <&gpp2 3 0>;*/
2032 samsung,spi-feedback-delay = <1>;
2033 samsung,spi-chip-select-mode = <0>;
2034 };
2035 };
2036 };
2037
2038 &spi_9 {
2039 pinctrl-names = "default";
2040 pinctrl-0 = <&spi9_bus &spi9_cs_func &codec_en>;
2041 status = "okay";
2042 #address-cells = <1>;
2043 #size-cells = <0>;
2044 cs47l35: cs47l35@0 {
2045 compatible = "cirrus,cs47l35";
2046 reg = <0x0>;
2047
2048 spi-max-frequency = <11000000>;
2049
2050 interrupts = <6 8 0>;
2051 interrupt-controller;
2052 #interrupt-cells = <2>;
2053 interrupt-parent = <&gpa0>;
2054 gpio-controller;
2055 #gpio-cells = <2>;
2056 #sound-dai-cells = <1>;
2057
2058 AVDD-supply = <&l42_reg>;
2059 DBVDD1-supply = <&l42_reg>;
2060 DBVDD2-supply = <&l42_reg>;
2061 CPVDD1-supply = <&l42_reg>;
2062 /*Not used LDO44*/
2063 /*CPVDD2-supply = <&l44_reg>;*/
2064 /*DCVDD-supply = <&l44_reg>;*/
2065 SPKVDD-supply = <&V_SYS>;
2066
2067 reset-gpios = <&gpg3 2 0>;
2068
2069 cirrus,dmic-ref = <0 0 0>;
2070 cirrus,inmode = <
2071 0 0 0 0 /* IN1 */
2072 0 0 0 0 /* IN2 */
2073 >;
2074
2075 cirrus,gpsw = <1 0>;
2076
2077 pinctrl-names = "probe", "active";
2078 pinctrl-0 = <&codec_reset>;
2079 pinctrl-1 = <&codec_reset &cs47l35_defaults>;
2080
2081 madera_pinctrl: madera-pinctrl {
2082 compatible = "cirrus,madera-pinctrl";
2083 cs47l35_defaults: cs47l35-gpio-defaults {
2084 aif1 {
2085 groups = "aif1";
2086 function = "aif1";
2087 bias-bus-hold;
2088 };
2089
2090 aif2 {
2091 groups = "aif2";
2092 function = "aif2";
2093 bias-bus-hold;
2094 };
2095
2096 aif3 {
2097 groups = "aif3";
2098 function = "aif3";
2099 bias-bus-hold;
2100 };
2101
2102 gpio6 { /* Amp Clock */
2103 groups = "gpio6";
2104 function = "opclk";
2105 bias-pull-up;
2106 output-low;
2107 };
2108
2109 gpio5 { /* Mic Polarity Flip */
2110 groups = "gpio5";
2111 function = "io";
2112 };
2113 };
2114 };
2115
2116
2117 micvdd {
2118 regulator-min-microvolt = <3000000>;
2119 regulator-max-microvolt = <3000000>;
2120 };
2121
2122 audio_micbias1:MICBIAS1 {
2123 regulator-min-microvolt = <2800000>;
2124 regulator-max-microvolt = <2800000>;
2125 cirrus,ext-cap = <1>;
2126 };
2127 MICBIAS1A {
2128 regulator-active-discharge = <1>;
2129 };
2130 MICBIAS1B {
2131 regulator-active-discharge = <1>;
2132 };
2133
2134 MICBIAS2 {
2135 regulator-min-microvolt = <2800000>;
2136 regulator-max-microvolt = <2800000>;
2137 cirrus,ext-cap = <1>;
2138 };
2139
2140 MICBIAS2A {
2141 regulator-active-discharge = <1>;
2142 };
2143 MICBIAS2B {
2144 regulator-active-discharge = <1>;
2145 };
2146
2147 cirrus,accdet {
2148 #address-cells = <1>;
2149 #size-cells = <0>;
2150
2151 acc@1 {
2152 reg = <1>;
2153
2154 cirrus,micd-configs = <
2155 0 0 2 0 0
2156 >;
2157 cirrus,micd-bias-start-time = <8>;
2158 cirrus,micd-rate = <6>;
2159 /*cirrus,micd-pol-gpios = <&cs47l35 4 0>;*/
2160 cirrus,micd-detect-debounce-ms = <700>;
2161 /*cirrus,jd-use-jd2;*/
2162 /*cirrus,micd-clamp-mode = <0x8>;*/
2163 cirrus,micd-manual-debounce = <2>;
2164 };
2165 };
2166
2167 adsps {
2168 #address-cells = <1>;
2169 #size-cells = <0>;
2170 adsp@17fe00 {
2171 reg = <0x17fe00>;
2172 firmware {
2173 frontend {
2174 cirrus,wmfw-file = "marley-dsp2-aov-frontend.wmfw";
2175 cirrus,bin-file = "marley-dsp2-aov-vrgain.bin";
2176 cirrus,full-name;
2177 cirrus,compr-caps = <14 1 4 1 16000>;
2178 };
2179 };
2180 };
2181 adsp@1ffe00 {
2182 reg = <0x1ffe00>;
2183 firmware {
2184 aov {
2185 cirrus,wmfw-file = "marley-dsp3-aov-control.wmfw";
2186 cirrus,bin-file = "None";
2187 cirrus,full-name;
2188 cirrus,compr-caps = <14 1 4 1 16000>;
2189 };
2190 };
2191 };
2192 };
2193
2194 controller-data {
2195 samsung,spi-feedback-delay = <1>;
2196 samsung,spi-chip-select-mode = <0>;
2197 };
2198 };
2199 };