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arm64: dts: sabrina: Add reserved ion-fb-mem space to ion_dev
[GitHub/LineageOS/G12/android_kernel_amlogic_linux-4.9.git] / arch / arm64 / boot / dts / amlogic / mesonsm1_sabrina.dtsi
1 /*
2 * arch/arm64/boot/dts/amlogic/mesonsm1.dtsi
3 *
4 * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/clock/amlogic,g12a-clkc.h>
20 #include <dt-bindings/clock/amlogic,sm1-audio-clk.h>
21 #include <dt-bindings/iio/adc/amlogic-saradc.h>
22 #include <dt-bindings/gpio/meson-g12a-gpio.h>
23 #include <dt-bindings/pwm/pwm.h>
24 #include <dt-bindings/pwm/meson.h>
25 #include <dt-bindings/gpio/gpio.h>
26 #include <dt-bindings/input/input.h>
27 #include <dt-bindings/input/meson_rc.h>
28 #include <dt-bindings/phy/phy-amlogic-pcie.h>
29 #include "mesong12a-bifrost.dtsi"
30
31 / {
32 cpus:cpus {
33 #address-cells = <2>;
34 #size-cells = <0>;
35
36 cpu-map {
37 cluster0:cluster0 {
38 core0 {
39 cpu = <&CPU0>;
40 };
41 core1 {
42 cpu = <&CPU1>;
43 };
44 core2 {
45 cpu = <&CPU2>;
46 };
47 core3 {
48 cpu = <&CPU3>;
49 };
50 };
51 };
52
53 CPU0:cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a53","arm,armv8";
56 reg = <0x0 0x0>;
57 enable-method = "psci";
58 //cpu-idle-states = <&CPU_SLEEP_0>;
59 clocks = <&clkc CLKID_CPU_CLK>,
60 <&clkc CLKID_CPU_FCLK_P>,
61 <&clkc CLKID_SYS_PLL>;
62 clock-names = "core_clk",
63 "low_freq_clk_parent",
64 "high_freq_clk_parent";
65 operating-points-v2 = <&cpu_opp_table0>;
66 cpu-supply = <&vddcpu0>;
67 voltage-tolerance = <0>;
68 clock-latency = <50000>;
69 };
70
71 CPU1:cpu@1 {
72 device_type = "cpu";
73 compatible = "arm,cortex-a53","arm,armv8";
74 reg = <0x0 0x1>;
75 enable-method = "psci";
76 //cpu-idle-states = <&CPU_SLEEP_0>;
77 clocks = <&clkc CLKID_CPU_CLK>,
78 <&clkc CLKID_CPU_FCLK_P>,
79 <&clkc CLKID_SYS_PLL>;
80 clock-names = "core_clk",
81 "low_freq_clk_parent",
82 "high_freq_clk_parent";
83 operating-points-v2 = <&cpu_opp_table0>;
84 cpu-supply = <&vddcpu0>;
85 voltage-tolerance = <0>;
86 clock-latency = <50000>;
87 };
88
89 CPU2:cpu@2 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a53","arm,armv8";
92 reg = <0x0 0x2>;
93 enable-method = "psci";
94 //cpu-idle-states = <&CPU_SLEEP_0>;
95 clocks = <&clkc CLKID_CPU_CLK>,
96 <&clkc CLKID_CPU_FCLK_P>,
97 <&clkc CLKID_SYS_PLL>;
98 clock-names = "core_clk",
99 "low_freq_clk_parent",
100 "high_freq_clk_parent";
101 operating-points-v2 = <&cpu_opp_table0>;
102 cpu-supply = <&vddcpu0>;
103 voltage-tolerance = <0>;
104 clock-latency = <50000>;
105 };
106
107 CPU3:cpu@3 {
108 device_type = "cpu";
109 compatible = "arm,cortex-a53","arm,armv8";
110 reg = <0x0 0x3>;
111 enable-method = "psci";
112 cpu-idle-states = <&CPU_SLEEP_0>;
113 clocks = <&clkc CLKID_CPU_CLK>,
114 <&clkc CLKID_CPU_FCLK_P>,
115 <&clkc CLKID_SYS_PLL>,
116 <&clkc CLKID_DSU_CLK>,
117 <&clkc CLKID_DSU_PRE_CLK>;
118 clock-names = "core_clk",
119 "low_freq_clk_parent",
120 "high_freq_clk_parent",
121 "dsu_clk",
122 "dsu_pre_parent";
123 operating-points-v2 = <&cpu_opp_table0>;
124 cpu-supply = <&vddcpu0>;
125 voltage-tolerance = <0>;
126 clock-latency = <50000>;
127 };
128
129 idle-states {
130 entry-method = "arm,psci-0.2";
131 CPU_SLEEP_0: cpu-sleep-0 {
132 compatible = "arm,idle-state";
133 arm,psci-suspend-param = <0x0010000>;
134 local-timer-stop;
135 entry-latency-us = <4000>;
136 exit-latency-us = <5000>;
137 min-residency-us = <10000>;
138 };
139 };
140 };
141
142 timer {
143 compatible = "arm,armv8-timer";
144 interrupts = <GIC_PPI 13 0xff08>,
145 <GIC_PPI 14 0xff08>,
146 <GIC_PPI 11 0xff08>,
147 <GIC_PPI 10 0xff08>;
148 };
149
150 timer_bc {
151 compatible = "arm, meson-bc-timer";
152 reg= <0x0 0xffd0f190 0x0 0x4 0x0 0xffd0f194 0x0 0x4>;
153 timer_name = "Meson TimerF";
154 clockevent-rating=<300>;
155 clockevent-shift=<20>;
156 clockevent-features=<0x23>;
157 interrupts = <0 60 1>;
158 bit_enable=<16>;
159 bit_mode=<12>;
160 bit_resolution=<0>;
161 };
162
163 arm_pmu {
164 compatible = "arm,armv8-pmuv3";
165 /* clusterb-enabled; */
166 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
167 reg = <0x0 0xff634680 0x0 0x4>;
168 cpumasks = <0xf>;
169 /* default 10ms */
170 relax-timer-ns = <10000000>;
171 /* default 10000us */
172 max-wait-cnt = <10000>;
173 };
174
175 gic: interrupt-controller@2c001000 {
176 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
177 #interrupt-cells = <3>;
178 #address-cells = <0>;
179 interrupt-controller;
180 reg = <0x0 0xffc01000 0 0x1000>,
181 <0x0 0xffc02000 0 0x0100>;
182 interrupts = <GIC_PPI 9 0xf04>;
183 };
184
185 psci {
186 compatible = "arm,psci-0.2";
187 method = "smc";
188 };
189
190 aml_pm {
191 compatible = "amlogic, pm";
192 status = "okay";
193 device_name = "aml_pm";
194 debug_reg = <0xff8000a8>;
195 exit_reg = <0xff80023c>;
196 };
197
198 secmon {
199 compatible = "amlogic, secmon";
200 memory-region = <&secmon_reserved>;
201 in_base_func = <0x82000020>;
202 out_base_func = <0x82000021>;
203 reserve_mem_size = <0x00300000>;
204 };
205
206 securitykey {
207 compatible = "aml, securitykey";
208 storage_query = <0x82000060>;
209 storage_read = <0x82000061>;
210 storage_write = <0x82000062>;
211 storage_tell = <0x82000063>;
212 storage_verify = <0x82000064>;
213 storage_status = <0x82000065>;
214 storage_list = <0x82000067>;
215 storage_remove = <0x82000068>;
216 storage_in_func = <0x82000023>;
217 storage_out_func = <0x82000024>;
218 storage_block_func = <0x82000025>;
219 storage_size_func = <0x82000027>;
220 storage_set_enctype = <0x8200006A>;
221 storage_get_enctype = <0x8200006B>;
222 storage_version = <0x8200006C>;
223 };
224
225 mailbox: mhu@c883c400 {
226 compatible = "amlogic, meson_mhu";
227 reg = <0x0 0xff63c400 0x0 0x4c>, /* MHU registers */
228 <0x0 0xfffe7000 0x0 0x800>; /* Payload area */
229 interrupts = <0 209 1>, /* low priority interrupt */
230 <0 210 1>; /* b interrupt */
231 #mbox-cells = <1>;
232 mbox-names = "cpu_to_scp_low", "cpu_to_scp_high";
233 mboxes = <&mailbox 0 &mailbox 1>;
234 };
235
236 cpu_iomap {
237 compatible = "amlogic, iomap";
238 #address-cells=<2>;
239 #size-cells=<2>;
240 ranges;
241 io_cbus_base {
242 reg = <0x0 0xffd00000 0x0 0x26fff>;
243 };
244 io_apb_base {
245 reg = <0x0 0xffe01000 0x0 0x7f000>;
246 };
247 io_aobus_base {
248 reg = <0x0 0xff800000 0x0 0xb000>;
249 };
250 io_vapb_base {
251 reg = <0x0 0xff900000 0x0 0x50000>;
252 };
253 io_hiu_base {
254 reg = <0x0 0xff63c000 0x0 0x2000>;
255 };
256 };
257
258 xtal: xtal-clk {
259 compatible = "fixed-clock";
260 clock-frequency = <24000000>;
261 clock-output-names = "xtal";
262 #clock-cells = <0>;
263 };
264
265 rtc{
266 compatible = "amlogic, aml_vrtc";
267 alarm_reg_addr = <0xff8000a8>;
268 timer_e_addr = <0xffd0f188>;
269 init_date = "2015/01/01";
270 status = "okay";
271 };
272
273 cpu_info {
274 compatible = "amlogic, cpuinfo";
275 status = "okay";
276 cpuinfo_cmd = <0x82000044>;
277 };
278
279 aml_reboot{
280 compatible = "aml, reboot";
281 sys_reset = <0x84000009>;
282 sys_poweroff = <0x84000008>;
283 reboot_reason_addr = <0xff80023c>;
284 };
285
286 vpu: vpu {
287 compatible = "amlogic, vpu-sm1";
288 dev_name = "vpu";
289 status = "okay";
290 clocks = <&clkc CLKID_VAPB_MUX>,
291 <&clkc CLKID_VPU_INTR>,
292 <&clkc CLKID_VPU_P0_COMP>,
293 <&clkc CLKID_VPU_P1_COMP>,
294 <&clkc CLKID_VPU_MUX>;
295 clock-names = "vapb_clk",
296 "vpu_intr_gate",
297 "vpu_clk0",
298 "vpu_clk1",
299 "vpu_clk";
300 clk_level = <7>;
301 /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
302 /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */
303 };
304
305 meson_uvm{
306 compatible = "amlogic, meson_uvm";
307 status = "okay";
308 };
309
310 meson_videotunnel{
311 compatible = "amlogic, meson_videotunnel";
312 status = "okay";
313 };
314
315 ethmac: ethernet@ff3f0000 {
316 compatible = "amlogic, g12a-eth-dwmac","snps,dwmac";
317 reg = <0x0 0xff3f0000 0x0 0x10000
318 0x0 0xff634540 0x0 0x8
319 0x0 0xff64c000 0x0 0xa0
320 0x0 0xffd01008 0x0 0x4>;
321 reg-names = "eth_base", "eth_cfg", "eth_pll", "eth_reset";
322 interrupts = <0 8 1>;
323 interrupt-names = "macirq";
324 status = "disabled";
325 clocks = <&clkc CLKID_ETH_CORE>;
326 clock-names = "ethclk81";
327 pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>;
328 analog_val = <0x20200000 0x0000c000 0x00000023>;
329 };
330
331 pinctrl_aobus: pinctrl@ff800014{
332 compatible = "amlogic,meson-g12a-aobus-pinctrl";
333 #address-cells = <2>;
334 #size-cells = <2>;
335 ranges;
336
337 gpio_ao: ao-bank@ff800014{
338 reg = <0x0 0xff800014 0x0 0x8>,
339 <0x0 0xff800024 0x0 0x14>,
340 <0x0 0xff80001c 0x0 0x8>;
341 reg-names = "mux","gpio", "drive-strength";
342 gpio-controller;
343 #gpio-cells = <2>;
344 };
345 };
346
347 pinctrl_periphs: pinctrl@ff634480{
348 compatible = "amlogic,meson-g12a-periphs-pinctrl";
349 #address-cells = <2>;
350 #size-cells = <2>;
351 ranges;
352
353 gpio: banks@ff6346c0{
354 reg = <0x0 0xff6346c0 0x0 0x40>,
355 <0x0 0xff6344e8 0x0 0x18>,
356 <0x0 0xff634520 0x0 0x18>,
357 <0x0 0xff634440 0x0 0x4c>,
358 <0x0 0xff634740 0x0 0x1c>;
359 reg-names = "mux",
360 "pull",
361 "pull-enable",
362 "gpio",
363 "drive-strength";
364 gpio-controller;
365 #gpio-cells = <2>;
366 };
367 };
368
369 audio_data: audio_data {
370 compatible = "amlogic, audio_data";
371 query_licence_cmd = <0x82000050>;
372 status = "disabled";
373 };
374
375 dwc3: dwc3@ff500000 {
376 compatible = "synopsys, dwc3";
377 status = "disable";
378 reg = <0x0 0xff500000 0x0 0x100000>;
379 interrupts = <0 30 4>;
380 usb-phy = <&usb2_phy_v2>, <&usb3_phy_v2>;
381 cpu-type = "gxl";
382 clock-src = "usb3.0";
383 clocks = <&clkc CLKID_USB_GENERAL>;
384 clock-names = "dwc_general";
385 };
386
387 usb2_phy_v2: usb2phy@ffe09000 {
388 compatible = "amlogic, amlogic-new-usb2-v2";
389 status = "disable";
390 reg = <0x0 0xffe09000 0x0 0x80
391 0x0 0xffd01008 0x0 0x100
392 0x0 0xff636000 0x0 0x2000
393 0x0 0xff63a000 0x0 0x2000>;
394 pll-setting-1 = <0x09400414>;
395 pll-setting-2 = <0x927E0000>;
396 pll-setting-3 = <0xac5f69e5>;
397 pll-setting-4 = <0xfe18>;
398 pll-setting-5 = <0x8000fff>;
399 pll-setting-6 = <0x78000>;
400 pll-setting-7 = <0xe0004>;
401 pll-setting-8 = <0xe000c>;
402 version = <2>;
403 pwr-ctl = <1>;
404 u2-ctrl-sleep-shift = <17>;
405 u2-hhi-mem-pd-shift = <30>;
406 u2-hhi-mem-pd-mask = <0x3>;
407 u2-ctrl-iso-shift = <17>;
408 };
409
410 usb3_phy_v2: usb3phy@ffe09080 {
411 compatible = "amlogic, amlogic-new-usb3-v2";
412 status = "disable";
413 reg = <0x0 0xffe09080 0x0 0x20
414 0x0 0xffd01008 0x0 0x100>;
415 phy-reg = <0xff646000>;
416 phy-reg-size = <0x2000>;
417 usb2-phy-reg = <0xffe09000>;
418 usb2-phy-reg-size = <0x80>;
419 interrupts = <0 16 4>;
420 clocks = <&clkc CLKID_PCIE_PLL>;
421 clock-names = "pcie_refpll";
422 pwr-ctl = <1>;
423 u3-ctrl-sleep-shift = <18>;
424 u3-hhi-mem-pd-shift = <26>;
425 u3-hhi-mem-pd-mask = <0xf>;
426 u3-ctrl-iso-shift = <18>;
427 };
428
429 dwc2_a: dwc2_a@ff400000 {
430 compatible = "amlogic, dwc2";
431 status = "disable";
432 device_name = "dwc2_a";
433 reg = <0x0 0xff400000 0x0 0x40000>;
434 interrupts = <0 31 4>;
435 pl-periph-id = <0>; /** lm name */
436 clock-src = "usb0"; /** clock src */
437 port-id = <0>; /** ref to mach/usb.h */
438 port-type = <2>; /** 0: otg, 1: host, 2: slave */
439 port-speed = <0>; /** 0: default, high, 1: full */
440 port-config = <0>; /** 0: default */
441 /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/
442 port-dma = <0>;
443 port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/
444 usb-fifo = <728>;
445 cpu-type = "v2";
446 phy-reg = <0xffe09000>;
447 phy-reg-size = <0xa0>;
448 /** phy-interface: 0x0: amlogic phy, 0x1: synopsys phy **/
449 phy-interface = <0x2>;
450 clocks = <&clkc CLKID_USB_GENERAL
451 &clkc CLKID_USB1_TO_DDR>;
452 clock-names = "usb_general",
453 "usb1";
454 };
455
456 wdt: watchdog@0xffd0f0d0 {
457 compatible = "amlogic, meson-wdt";
458 status = "okay";
459 default_timeout=<10>;
460 reset_watchdog_method=<1>; /* 0:sysfs,1:kernel */
461 reset_watchdog_time=<2>;
462 shutdown_timeout=<10>;
463 firmware_timeout=<6>;
464 suspend_timeout=<6>;
465 reg = <0x0 0xffd0f0d0 0x0 0x10>;
466 clock-names = "xtal";
467 clocks = <&xtal>;
468 };
469
470 ram-dump {
471 compatible = "amlogic, ram_dump";
472 status = "okay";
473 reg = <0x0 0xFF6345E0 0x0 4>;
474 reg-names = "PREG_STICKY_REG8";
475 };
476
477 jtag {
478 compatible = "amlogic, jtag";
479 status = "okay";
480 select = "disable"; /* disable/apao/apee */
481 pinctrl-names="jtag_apao_pins", "jtag_apee_pins";
482 pinctrl-0=<&jtag_apao_pins>;
483 pinctrl-1=<&jtag_apee_pins>;
484 };
485
486 saradc:saradc {
487 compatible = "amlogic,meson-g12a-saradc";
488 status = "okay";
489 #io-channel-cells = <1>;
490 clocks = <&xtal>, <&clkc CLKID_SARADC_GATE>;
491 clock-names = "xtal", "saradc_clk";
492 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
493 reg = <0x0 0xff809000 0x0 0x48>;
494 };
495
496 power_ctrl: power_ctrl@ff8000e8 {
497 compatible = "amlogic, sm1-powerctrl";
498 reg = <0x0 0xff8000e8 0x0 0x10>,
499 <0x0 0xff63c100 0x0 0x10>;
500 };
501
502 bl40: bl40 {
503 compatible = "amlogic, bl40-bootup";
504 status = "okay";
505 };
506
507 soc {
508 compatible = "simple-bus";
509 #address-cells = <2>;
510 #size-cells = <2>;
511 ranges;
512
513 cbus: cbus@ffd00000 {
514 compatible = "simple-bus";
515 reg = <0x0 0xffd00000 0x0 0x26000>;
516 #address-cells = <2>;
517 #size-cells = <2>;
518 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x26000>;
519
520 gpio_intc: interrupt-controller@f080 {
521 compatible = "amlogic,meson-gpio-intc",
522 "amlogic,meson-sm1-gpio-intc";
523 reg = <0x0 0xf080 0x0 0x10>;
524 interrupt-controller;
525 #interrupt-cells = <2>;
526 amlogic,channel-interrupts =
527 <64 65 66 67 68 69 70 71>;
528 status = "okay";
529 };
530
531 meson_clk_msr {
532 compatible = "amlogic, sm1-measure";
533 reg = <0x0 0x18004 0x0 0x4
534 0x0 0x1800c 0x0 0x4>;
535 ringctrl = <0xff6345fc>;
536 };
537
538 pwm_ab: pwm@1b000 {
539 compatible = "amlogic,g12a-ee-pwm";
540 reg = <0x0 0x1b000 0x0 0x20>;
541 #pwm-cells = <3>;
542 clocks = <&xtal>,
543 <&xtal>,
544 <&xtal>,
545 <&xtal>;
546 clock-names = "clkin0",
547 "clkin1",
548 "clkin2",
549 "clkin3";
550 /* default xtal 24m clkin0-clkin2 and
551 * clkin1-clkin3 should be set the same
552 */
553 status = "disabled";
554 };
555
556 pwm_cd: pwm@1a000 {
557 compatible = "amlogic,g12a-ee-pwm";
558 reg = <0x0 0x1a000 0x0 0x20>;
559 #pwm-cells = <3>;
560 clocks = <&xtal>,
561 <&xtal>,
562 <&xtal>,
563 <&xtal>;
564 clock-names = "clkin0",
565 "clkin1",
566 "clkin2",
567 "clkin3";
568 status = "disabled";
569 };
570
571 pwm_ef: pwm@19000 {
572 compatible = "amlogic,g12a-ee-pwm";
573 reg = <0x0 0x19000 0x0 0x20>;
574 #pwm-cells = <3>;
575 clocks = <&xtal>,
576 <&xtal>,
577 <&xtal>,
578 <&xtal>;
579 clock-names = "clkin0",
580 "clkin1",
581 "clkin2",
582 "clkin3";
583 status = "disabled";
584 };
585
586 i2c0: i2c@1f000 {
587 compatible = "amlogic,meson-g12a-i2c";
588 status = "disabled";
589 reg = <0x0 0x1f000 0x0 0x20>;
590 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
591 <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>;
592 #address-cells = <1>;
593 #size-cells = <0>;
594 clocks = <&clkc CLKID_I2C>;
595 clock-names = "clk_i2c";
596 };
597
598 i2c1: i2c@1e000 {
599 compatible = "amlogic,meson-g12a-i2c";
600 status = "disabled";
601 reg = <0x0 0x1e000 0x0 0x20>;
602 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>,
603 <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>;
604 #address-cells = <1>;
605 #size-cells = <0>;
606 clocks = <&clkc CLKID_I2C>;
607 clock-names = "clk_i2c";
608 };
609
610 i2c2: i2c@1d000 {
611 compatible = "amlogic,meson-g12a-i2c";
612 status = "disabled";
613 reg = <0x0 0x1d000 0x0 0x20>;
614 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>,
615 <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>;
616 #address-cells = <1>;
617 #size-cells = <0>;
618 clocks = <&clkc CLKID_I2C>;
619 clock-names = "clk_i2c";
620 };
621
622 i2c3: i2c@1c000 {
623 compatible = "amlogic,meson-g12a-i2c";
624 status = "disabled";
625 reg = <0x0 0x1c000 0x0 0x20>;
626 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
627 <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>;
628 #address-cells = <1>;
629 #size-cells = <0>;
630 clocks = <&clkc CLKID_I2C>;
631 clock-names = "clk_i2c";
632 };
633
634 spicc0: spi@13000 {
635 compatible = "amlogic,meson-g12a-spicc";
636 reg = <0x0 0x13000 0x0 0x44>;
637 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&clkc CLKID_SPICC0>,
639 <&clkc CLKID_SPICC0_COMP>;
640 clock-names = "core", "comp";
641 #address-cells = <1>;
642 #size-cells = <0>;
643 status = "disabled";
644 };
645
646 spicc1: spi@15000 {
647 compatible = "amlogic,meson-g12a-spicc";
648 reg = <0x0 0x15000 0x0 0x44>;
649 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
650 clocks = <&clkc CLKID_SPICC1>,
651 <&clkc CLKID_SPICC1_COMP>;
652 clock-names = "core", "comp";
653 #address-cells = <1>;
654 #size-cells = <0>;
655 status = "disabled";
656 };
657 }; /* end of cbus */
658
659 aobus: aobus@ff800000 {
660 compatible = "simple-bus";
661 reg = <0x0 0xff800000 0x0 0xb000>;
662 #address-cells = <2>;
663 #size-cells = <2>;
664 ranges = <0x0 0x0 0x0 0xff800000 0x0 0xb000>;
665
666 cpu_version {
667 reg=<0x0 0x220 0x0 0x4>;
668 };
669
670 aoclkc: clock-controller@0 {
671 compatible = "amlogic,sm1-aoclkc";
672 #clock-cells = <1>;
673 reg = <0x0 0x0 0x0 0x3dc>;
674 };
675
676 pwm_AO_ab: pwm@7000 {
677 compatible = "amlogic,g12a-ao-pwm";
678 reg = <0x0 0x7000 0x0 0x20>;
679 #pwm-cells = <3>;
680 clocks = <&xtal>,
681 <&xtal>,
682 <&xtal>,
683 <&xtal>;
684 clock-names = "clkin0",
685 "clkin1",
686 "clkin2",
687 "clkin3";
688 status = "disabled";
689 };
690
691 pwm_AO_cd: pwm@2000 {
692 compatible = "amlogic,g12a-ao-pwm";
693 reg = <0x0 0x2000 0x0 0x20>;
694 #pwm-cells = <3>;
695 clocks = <&xtal>,
696 <&xtal>,
697 <&xtal>,
698 <&xtal>;
699 clock-names = "clkin0",
700 "clkin1",
701 "clkin2",
702 "clkin3";
703 status = "disabled";
704 };
705
706 i2c_AO: i2c@5000 {
707 compatible = "amlogic,meson-g12a-i2c";
708 status = "disabled";
709 reg = <0x0 0x05000 0x0 0x20>;
710 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
711 <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>;
712 #address-cells = <1>;
713 #size-cells = <0>;
714 clocks = <&clkc CLKID_I2C>;
715 clock-names = "clk_i2c";
716 };
717
718 i2c_AO_slave:i2c_slave@6000 {
719 compatible = "amlogic, meson-i2c-slave";
720 status = "disabled";
721 reg = <0x0 0x6000 0x0 0x20>;
722 interrupts = <0 194 1>;
723 pinctrl-names="default";
724 pinctrl-0=<&ao_i2c_slave_pins>;
725 };
726
727 uart_AO: serial@3000 {
728 compatible = "amlogic, meson-uart";
729 reg = <0x0 0x3000 0x0 0x18>;
730 interrupts = <0 193 1>;
731 status = "okay";
732 clocks = <&xtal>;
733 clock-names = "clk_uart";
734 xtal_tick_en = <2>;
735 fifosize = < 64 >;
736 pinctrl-names = "default";
737 /*pinctrl-0 = <&ao_uart_pins>;*/
738 support-sysrq = <1>; /* 0 not support*/
739 };
740
741 uart_AO_B: serial@4000 {
742 compatible = "amlogic, meson-uart";
743 reg = <0x0 0x4000 0x0 0x18>;
744 interrupts = <0 197 1>;
745 status = "disabled";
746 clocks = <&xtal>;
747 clock-names = "clk_uart";
748 fifosize = < 64 >;
749 pinctrl-names = "default";
750 pinctrl-0 = <&ao_b_uart_pins>;
751 };
752
753 };/* end of aobus */
754
755 periphs: periphs@ff634400 {
756 compatible = "simple-bus";
757 reg = <0x0 0xff634400 0x0 0x400>;
758 #address-cells = <2>;
759 #size-cells = <2>;
760 ranges = <0x0 0x0 0x0 0xff634400 0x0 0x400>;
761
762 };/* end of periphs */
763
764 hiubus: hiubus@ff63c000 {
765 compatible = "simple-bus";
766 reg = <0x0 0xff63c000 0x0 0x2000>;
767 #address-cells = <2>;
768 #size-cells = <2>;
769 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>;
770
771 clkc: clock-controller@0 {
772 compatible = "amlogic,sm1-clkc-1";
773 #clock-cells = <1>;
774 reg = <0x0 0x0 0x0 0x3dc>;
775 };
776
777 clkc_b: clock-controller@1 {
778 compatible = "amlogic,sm1-clkc-2";
779 #clock-cells = <1>;
780 reg = <0x0 0x0 0x0 0x3dc>;
781 clocks = <&clkc CLKID_FCLK_DIV2>;
782 clock-names = "clkin0";
783 };
784 };/* end of hiubus*/
785
786 ion_dev {
787 compatible = "amlogic, ion_dev";
788 memory-region = <&ion_cma_reserved
789 &ion_fb_reserved>;
790 };/* end of ion_dev*/
791
792 audiobus: audiobus@0xFF660000 {
793 compatible = "amlogic, audio-controller", "simple-bus";
794 reg = <0x0 0xFF660000 0x0 0x3000>;
795 #address-cells = <2>;
796 #size-cells = <2>;
797 ranges = <0x0 0x0 0x0 0xFF660000 0x0 0x3000>;
798 clkaudio: audio_clocks {
799 compatible = "amlogic, sm1-audio-clocks";
800 #clock-cells = <1>;
801 reg = <0x0 0x0 0x0 0xb0>;
802 };
803 ddr_manager {
804 compatible = "amlogic, sm1-audio-ddr-manager";
805 interrupts = <
806 GIC_SPI 148 IRQ_TYPE_EDGE_RISING
807 GIC_SPI 149 IRQ_TYPE_EDGE_RISING
808 GIC_SPI 150 IRQ_TYPE_EDGE_RISING
809 GIC_SPI 49 IRQ_TYPE_EDGE_RISING
810 GIC_SPI 152 IRQ_TYPE_EDGE_RISING
811 GIC_SPI 153 IRQ_TYPE_EDGE_RISING
812 GIC_SPI 154 IRQ_TYPE_EDGE_RISING
813 GIC_SPI 50 IRQ_TYPE_EDGE_RISING
814 >;
815 interrupt-names =
816 "toddr_a", "toddr_b", "toddr_c",
817 "toddr_d",
818 "frddr_a", "frddr_b", "frddr_c",
819 "frddr_d";
820 };
821 };/* end of audiobus*/
822
823 /* eARC */
824 audio_earc: bus@ff663000 {
825 compatible = "simple-bus";
826 reg = <0x0 0xff663000 0x0 0x1000>;
827 #address-cells = <2>;
828 #size-cells = <2>;
829 ranges = <0x0 0x0 0x0 0xff663000 0x0 0x1000>;
830
831 earc: earc@0 {
832 compatible = "amlogic, sm1-snd-earc";
833 #sound-dai-cells = <0>;
834
835 status = "disabled";
836
837 reg =
838 <0x0 0x800 0x0 0x400>,
839 <0x0 0xc00 0x0 0x200>,
840 <0x0 0xe00 0x0 0x200>;
841 reg-names =
842 "rx_cmdc",
843 "rx_dmac",
844 "rx_top";
845
846 clocks = < &clkaudio CLKID_EARCRX_CMDC
847 &clkaudio CLKID_EARCRX_DMAC
848 &clkc CLKID_FCLK_DIV4
849 &clkc CLKID_FCLK_DIV4
850 &clkaudio CLKID_EARCTX_CMDC
851 &clkaudio CLKID_EARCTX_DMAC
852 &clkc CLKID_FCLK_DIV4
853 &clkc CLKID_MPLL1
854 >;
855 clock-names =
856 "rx_cmdc",
857 "rx_dmac",
858 "rx_cmdc_srcpll",
859 "rx_dmac_srcpll";
860
861 interrupts = <
862 GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
863 interrupt-names = "earc_rx";
864 };
865 };
866
867 /* Sound iomap */
868 aml_snd_iomap {
869 compatible = "amlogic, snd-iomap";
870 status = "okay";
871 #address-cells=<2>;
872 #size-cells=<2>;
873 ranges;
874 pdm_bus {
875 reg = <0x0 0xFF661000 0x0 0x400>;
876 };
877 audiobus_base {
878 reg = <0x0 0xFF660000 0x0 0x1000>;
879 };
880 audiolocker_base {
881 reg = <0x0 0xFF661400 0x0 0x400>;
882 };
883 eqdrc_base {
884 reg = <0x0 0xFF662000 0x0 0x1000>;
885 };
886 reset_base {
887 reg = <0x0 0xFFD01000 0x0 0x1000>;
888 };
889 vad_base {
890 reg = <0x0 0xFF661800 0x0 0x400>;
891 };
892 };
893 }; /* end of soc*/
894
895 remote:rc@0xff808040 {
896 compatible = "amlogic, aml_remote";
897 dev_name = "meson-remote";
898 reg = <0x0 0xff808040 0x00 0x44>, /*Multi-format IR controller*/
899 <0x0 0xff808000 0x00 0x20>; /*Legacy IR controller*/
900 status = "disabled";
901 protocol = <REMOTE_TYPE_NEC>;
902 led_blink = <1>;
903 led_blink_frq = <100>;
904 interrupts = <0 196 1>;
905 pinctrl-names = "default";
906 pinctrl-0 = <&remote_pins>;
907 map = <&custom_maps>;
908 max_frame_time = <200>; /*set software decoder max frame time*/
909 };
910
911 custom_maps:custom_maps {
912 mapnum = <3>;
913 map0 = <&map_0>;
914 map1 = <&map_1>;
915 map2 = <&map_2>;
916 map_0: map_0{
917 mapname = "amlogic-remote-1";
918 customcode = <0xfb04>;
919 release_delay = <80>;
920 size = <50>; /*keymap size*/
921 keymap = <REMOTE_KEY(0x47, KEY_0)
922 REMOTE_KEY(0x13, KEY_1)
923 REMOTE_KEY(0x10, KEY_2)
924 REMOTE_KEY(0x11, KEY_3)
925 REMOTE_KEY(0x0F, KEY_4)
926 REMOTE_KEY(0x0C, KEY_5)
927 REMOTE_KEY(0x0D, KEY_6)
928 REMOTE_KEY(0x0B, KEY_7)
929 REMOTE_KEY(0x08, KEY_8)
930 REMOTE_KEY(0x09, KEY_9)
931 REMOTE_KEY(0x5C, KEY_RIGHTCTRL)
932 REMOTE_KEY(0x51, KEY_F3)
933 REMOTE_KEY(0x50, KEY_F4)
934 REMOTE_KEY(0x40, KEY_F5)
935 REMOTE_KEY(0x4d, KEY_F6)
936 REMOTE_KEY(0x43, KEY_F7)
937 REMOTE_KEY(0x17, KEY_F8)
938 REMOTE_KEY(0x00, KEY_F9)
939 REMOTE_KEY(0x01, KEY_F10)
940 REMOTE_KEY(0x16, KEY_F11)
941 REMOTE_KEY(0x49, KEY_BACKSPACE)
942 REMOTE_KEY(0x06, KEY_PROPS)
943 REMOTE_KEY(0x14, KEY_UNDO)
944 REMOTE_KEY(0x44, KEY_UP)
945 REMOTE_KEY(0x1D, KEY_DOWN)
946 REMOTE_KEY(0x1C, KEY_LEFT)
947 REMOTE_KEY(0x48, KEY_RIGHT)
948 REMOTE_KEY(0x53, KEY_LEFTMETA)
949 REMOTE_KEY(0x45, KEY_PAGEUP)
950 REMOTE_KEY(0x19, KEY_PAGEDOWN)
951 REMOTE_KEY(0x52, KEY_PAUSE)
952 REMOTE_KEY(0x05, KEY_HANGEUL)
953 REMOTE_KEY(0x59, KEY_HANJA)
954 REMOTE_KEY(0x1b, KEY_SCALE)
955 REMOTE_KEY(0x04, KEY_KPCOMMA)
956 REMOTE_KEY(0x1A, KEY_POWER)
957 REMOTE_KEY(0x0A, KEY_TAB)
958 REMOTE_KEY(0x0e, KEY_MUTE)
959 REMOTE_KEY(0x1F, KEY_HOME)
960 REMOTE_KEY(0x1e, KEY_FRONT)
961 REMOTE_KEY(0x07, KEY_COPY)
962 REMOTE_KEY(0x12, KEY_OPEN)
963 REMOTE_KEY(0x54, KEY_PASTE)
964 REMOTE_KEY(0x02, KEY_FIND)
965 REMOTE_KEY(0x4f, KEY_A)
966 REMOTE_KEY(0x42, KEY_B)
967 REMOTE_KEY(0x5d, KEY_C)
968 REMOTE_KEY(0x4c, KEY_D)
969 REMOTE_KEY(0x58, KEY_CUT)
970 REMOTE_KEY(0x55, KEY_CALC)>;
971 };
972 map_1: map_1{
973 mapname = "amlogic-remote-2";
974 customcode = <0xfe01>;
975 release_delay = <80>;
976 size = <53>;
977 keymap = <REMOTE_KEY(0x01, KEY_1)
978 REMOTE_KEY(0x02, KEY_2)
979 REMOTE_KEY(0x03, KEY_3)
980 REMOTE_KEY(0x04, KEY_4)
981 REMOTE_KEY(0x05, KEY_5)
982 REMOTE_KEY(0x06, KEY_6)
983 REMOTE_KEY(0x07, KEY_7)
984 REMOTE_KEY(0x08, KEY_8)
985 REMOTE_KEY(0x09, KEY_9)
986 REMOTE_KEY(0x0a, KEY_0)
987 REMOTE_KEY(0x1F, KEY_FN_F1)
988 REMOTE_KEY(0x15, KEY_MENU)
989 REMOTE_KEY(0x16, KEY_TAB)
990 REMOTE_KEY(0x0c, KEY_CHANNELUP)
991 REMOTE_KEY(0x0d, KEY_CHANNELDOWN)
992 REMOTE_KEY(0x0e, KEY_VOLUMEUP)
993 REMOTE_KEY(0x0f, KEY_VOLUMEDOWN)
994 REMOTE_KEY(0x11, KEY_HOME)
995 REMOTE_KEY(0x1c, KEY_RIGHT)
996 REMOTE_KEY(0x1b, KEY_LEFT)
997 REMOTE_KEY(0x19, KEY_UP)
998 REMOTE_KEY(0x1a, KEY_DOWN)
999 REMOTE_KEY(0x1d, KEY_ENTER)
1000 REMOTE_KEY(0x17, KEY_MUTE)
1001 REMOTE_KEY(0x49, KEY_FINANCE)
1002 REMOTE_KEY(0x43, KEY_BACK)
1003 REMOTE_KEY(0x12, KEY_FN_F4)
1004 REMOTE_KEY(0x14, KEY_FN_F5)
1005 REMOTE_KEY(0x18, KEY_FN_F6)
1006 REMOTE_KEY(0x59, KEY_INFO)
1007 REMOTE_KEY(0x5a, KEY_STOPCD)
1008 REMOTE_KEY(0x10, KEY_POWER)
1009 REMOTE_KEY(0x42, KEY_PREVIOUSSONG)
1010 REMOTE_KEY(0x44, KEY_NEXTSONG)
1011 REMOTE_KEY(0x1e, KEY_REWIND)
1012 REMOTE_KEY(0x4b, KEY_FASTFORWARD)
1013 REMOTE_KEY(0x58, KEY_PLAYPAUSE)
1014 REMOTE_KEY(0x46, KEY_PROPS)
1015 REMOTE_KEY(0x40, KEY_UNDO)
1016 REMOTE_KEY(0x38, KEY_SCROLLLOCK)
1017 REMOTE_KEY(0x57, KEY_FN)
1018 REMOTE_KEY(0x5b, KEY_FN_ESC)
1019 REMOTE_KEY(0x54, KEY_RED)
1020 REMOTE_KEY(0x4c, KEY_GREEN)
1021 REMOTE_KEY(0x4e, KEY_YELLOW)
1022 REMOTE_KEY(0x55, KEY_BLUE)
1023 REMOTE_KEY(0x53, KEY_BLUETOOTH)
1024 REMOTE_KEY(0x52, KEY_WLAN)
1025 REMOTE_KEY(0x39, KEY_CAMERA)
1026 REMOTE_KEY(0x41, KEY_SOUND)
1027 REMOTE_KEY(0x0b, KEY_QUESTION)
1028 REMOTE_KEY(0x00, KEY_CHAT)
1029 REMOTE_KEY(0x13, KEY_SEARCH)>;
1030 };
1031 map_2: map_2{
1032 mapname = "amlogic-remote-3";
1033 customcode = <0xbd02>;
1034 release_delay = <80>;
1035 size = <17>;
1036 keymap = <REMOTE_KEY(0xca,103)
1037 REMOTE_KEY(0xd2,108)
1038 REMOTE_KEY(0x99,105)
1039 REMOTE_KEY(0xc1,106)
1040 REMOTE_KEY(0xce,97)
1041 REMOTE_KEY(0x45,116)
1042 REMOTE_KEY(0xc5,133)
1043 REMOTE_KEY(0x80,113)
1044 REMOTE_KEY(0xd0,15)
1045 REMOTE_KEY(0xd6,125)
1046 REMOTE_KEY(0x95,102)
1047 REMOTE_KEY(0xdd,104)
1048 REMOTE_KEY(0x8c,109)
1049 REMOTE_KEY(0x89,131)
1050 REMOTE_KEY(0x9c,130)
1051 REMOTE_KEY(0x9a,120)
1052 REMOTE_KEY(0xcd,121)>;
1053 };
1054 };
1055
1056 uart_A: serial@ffd24000 {
1057 compatible = "amlogic, meson-uart";
1058 reg = <0x0 0xffd24000 0x0 0x18>;
1059 interrupts = <0 26 1>;
1060 status = "disabled";
1061 clocks = <&xtal
1062 &clkc CLKID_UART0>;
1063 clock-names = "clk_uart",
1064 "clk_gate";
1065 fifosize = < 128 >;
1066 pinctrl-names = "default";
1067 pinctrl-0 = <&a_uart_pins>;
1068 };
1069
1070 uart_B: serial@ffd23000 {
1071 compatible = "amlogic, meson-uart";
1072 reg = <0x0 0xffd23000 0x0 0x18>;
1073 interrupts = <0 75 1>;
1074 status = "disabled";
1075 clocks = <&xtal
1076 &clkc CLKID_UART1>;
1077 clock-names = "clk_uart",
1078 "clk_gate";
1079 fifosize = < 64 >;
1080 pinctrl-names = "default";
1081 pinctrl-0 = <&b_uart_pins>;
1082 };
1083
1084 uart_C: serial@ffd22000 {
1085 compatible = "amlogic, meson-uart";
1086 reg = <0x0 0xffd22000 0x0 0x18>;
1087 interrupts = <0 93 1>;
1088 status = "disabled";
1089 clocks = <&xtal
1090 &clkc CLKID_UART1>;
1091 clock-names = "clk_uart",
1092 "clk_gate";
1093 fifosize = < 64 >;
1094 pinctrl-names = "default";
1095 pinctrl-0 = <&c_uart_pins>;
1096 };
1097
1098
1099 pcie_A: pcieA@fc000000 {
1100 compatible = "amlogic, amlogic-pcie-v2", "snps,dw-pcie";
1101 reg = <0x0 0xfc000000 0x0 0x400000
1102 0x0 0xff648000 0x0 0x2000
1103 0x0 0xfc400000 0x0 0x200000
1104 0x0 0xff646000 0x0 0x2000
1105 0x0 0xffd01080 0x0 0x10>;
1106 reg-names = "elbi", "cfg", "config", "phy", "reset";
1107 interrupts = <0 221 0>;
1108 #interrupt-cells = <1>;
1109 bus-range = <0x0 0xff>;
1110 #address-cells = <3>;
1111 #size-cells = <2>;
1112 interrupt-map-mask = <0 0 0 0>;
1113 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_EDGE_RISING>;
1114 device_type = "pci";
1115 ranges = <0x81000000 0 0 0 0xfc600000 0x0 0x100000
1116 /* downstream I/O */
1117 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
1118 /* non-prefetchable memory */
1119 num-lanes = <1>;
1120 pcie-num = <1>;
1121
1122 clocks = <&clkc CLKID_PCIE_PLL
1123 &clkc CLKID_PCIE_COMB
1124 &clkc CLKID_PCIE_PHY>;
1125 clock-names = "pcie_refpll",
1126 "pcie",
1127 "pcie_phy";
1128 /*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
1129 gpio-type = <2>;
1130 pcie-apb-rst-bit = <15>;
1131 pcie-phy-rst-bit = <14>;
1132 pcie-ctrl-a-rst-bit = <12>;
1133 pwr-ctl = <1>;
1134 pcie-ctrl-sleep-shift = <18>;
1135 pcie-hhi-mem-pd-shift = <26>;
1136 pcie-hhi-mem-pd-mask = <0xf>;
1137 pcie-ctrl-iso-shift = <18>;
1138 status = "disabled";
1139 };
1140
1141 amhdmitx: amhdmitx{
1142 compatible = "amlogic, amhdmitx";
1143 dev_name = "amhdmitx";
1144 status = "okay";
1145 vend-data = <&vend_data>;
1146 pinctrl-names="default", "hdmitx_i2c";
1147 pinctrl-0=<&hdmitx_hpd &hdmitx_ddc>;
1148 pinctrl-1=<&hdmitx_hpd_gpio &i2c3_master_pins1>;
1149 clocks = <&clkc CLKID_VCLK2_ENCI
1150 &clkc CLKID_VCLK2_VENCI0
1151 &clkc CLKID_VCLK2_VENCI1
1152 &clkc CLKID_VAPB_MUX
1153 &clkc CLKID_VPU_MUX>;
1154 clock-names = "venci_top_gate",
1155 "venci_0_gate",
1156 "venci_1_gate",
1157 "hdmi_vapb_clk",
1158 "hdmi_vpu_clk";
1159 /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
1160 interrupts = <0 57 1>;
1161 interrupt-names = "hdmitx_hpd";
1162 /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
1163 * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
1164 * 10:G12A 11:G12B 12:SM1
1165 */
1166 ic_type = <12>;
1167 cedst_en = <1>;
1168 vend_data: vend_data{ /* Should modified by Customer */
1169 vendor_name = "Google"; /* Max Chars: 8 */
1170 product_desc = "Chromecast"; /* Max Chars: 16 */
1171 /* standards.ieee.org/develop/regauth/oui/oui.txt */
1172 vendor_id = <0x001a11>;
1173 };
1174 };
1175
1176 galcore {
1177 compatible = "amlogic, galcore";
1178 dev_name = "galcore";
1179 status = "okay";
1180 clocks = <&clkc CLKID_VNANOQ_AXI_CLK_COMP>,
1181 <&clkc CLKID_VNANOQ_CORE_CLK_COMP>;
1182 clock-names = "cts_vipnanoq_axi_clk_composite",
1183 "cts_vipnanoq_core_clk_composite";
1184 interrupts = <0 186 4>;
1185 interrupt-names = "galcore";
1186 reg = <0x0 0xff100000 0x0 0x800
1187 0x0 0xff000000 0x0 0x400000
1188 0x0 0xff63c118 0x0 0x0
1189 0x0 0xff63c11c 0x0 0x0
1190 0x0 0xffd01088 0x0 0x0
1191 0x0 0xff63c1c8 0x0 0x0
1192 >;
1193 reg-names = "NN_REG","NN_SRAM","NN_MEM0",
1194 "NN_MEM1","NN_RESET","NN_CLK";
1195 nn_power_version = <3>;
1196 nn_efuse = <0xff63003c 0x20>;
1197 };
1198 aocec: aocec {
1199 compatible = "amlogic, aocec-sm1";
1200 device_name = "aocec";
1201 status = "okay";
1202 vendor_name = "Google"; /* Max Chars: 8 */
1203 /* Refer to the following URL at:
1204 * http://standards.ieee.org/develop/regauth/oui/oui.txt
1205 */
1206 vendor_id = <0x001a11>;
1207 product_desc = "Chromecast"; /* Max Chars: 16 */
1208 cec_osd_string = "Chromecast"; /* Max Chars: 14 */
1209 cec_version = <5>;/*5:1.4;6:2.0*/
1210 port_num = <1>;
1211 output = <1>;
1212 ee_cec;
1213 arc_port_mask = <0x2>;
1214 interrupts = <0 203 1
1215 0 199 1>; /*0:snps 1:ts*/
1216 interrupt-names = "hdmi_aocecb","hdmi_aocec";
1217 pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep";
1218 pinctrl-0=<&eecec_a>;
1219 pinctrl-1=<&eecec_b>;
1220 pinctrl-2=<&eecec_b>;
1221 reg = <0x0 0xFF80023c 0x0 0x4
1222 0x0 0xFF800000 0x0 0x400
1223 0x0 0xFF634400 0x0 0x70>;
1224 reg-names = "ao_exit","ao","periphs";
1225 };
1226
1227 /*if you want to use vdin just modify status to "ok"*/
1228 vdin0: vdin0 {
1229 compatible = "amlogic, vdin";
1230 dev_name = "vdin0";
1231 status = "disabled";
1232 reserve-iomap = "true";
1233 flag_cma = <0>;/*1:share with codec_mm;2:cma alone*/
1234 /*MByte, if 10bit disable: 64M(YUV422),
1235 *if 10bit enable: 64*1.5 = 96M(YUV422)
1236 *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M
1237 *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M
1238 *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M
1239 *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M
1240 */
1241 /*cma_size = <16>;*/
1242 interrupts = <0 83 1>;
1243 rdma-irq = <2>;
1244 /*clocks = <&clock CLK_FPLL_DIV5>,
1245 * <&clock CLK_VDIN_MEAS_CLK>;
1246 *clock-names = "fclk_div5", "cts_vdin_meas_clk";
1247 */
1248 vdin_id = <0>;
1249 };
1250 vdin1: vdin1 {
1251 compatible = "amlogic, vdin";
1252 dev_name = "vdin1";
1253 status = "disabled";
1254 reserve-iomap = "true";
1255 flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/
1256 interrupts = <0 85 1>;
1257 rdma-irq = <4>;
1258 /*clocks = <&clock CLK_FPLL_DIV5>,
1259 * <&clock CLK_VDIN_MEAS_CLK>;
1260 *clock-names = "fclk_div5", "cts_vdin_meas_clk";
1261 */
1262 vdin_id = <1>;
1263 };
1264
1265 vout {
1266 compatible = "amlogic, vout";
1267 dev_name = "vout";
1268 status = "okay";
1269
1270 /* fr_policy:
1271 * 0: disable
1272 * 1: nearby (only for 60->59.94 and 30->29.97)
1273 * 2: force (60/50/30/24/59.94/23.97)
1274 */
1275 fr_policy = <2>;
1276 };
1277
1278 vout2 {
1279 compatible = "amlogic, vout2";
1280 dev_name = "vout";
1281 status = "okay";
1282 clocks = <&clkc CLKID_VPU_CLKC_P0_COMP>,
1283 <&clkc CLKID_VPU_CLKC_MUX>;
1284 clock-names = "vpu_clkc0",
1285 "vpu_clkc";
1286
1287 /* fr_policy:
1288 * 0: disable
1289 * 1: nearby (only for 60->59.94 and 30->29.97)
1290 * 2: force (60/50/30/24/59.94/23.97)
1291 */
1292 fr_policy = <2>;
1293 };
1294
1295 dummy_venc: dummy_venc {
1296 compatible = "amlogic, dummy_venc";
1297 status = "okay";
1298 clocks = <&clkc CLKID_VCLK2_ENCP
1299 &clkc CLKID_VCLK2_VENCP0
1300 &clkc CLKID_VCLK2_VENCP1
1301 &clkc CLKID_VCLK2_ENCI
1302 &clkc CLKID_VCLK2_VENCI0
1303 &clkc CLKID_VCLK2_VENCI1
1304 &clkc CLKID_VCLK2_ENCL
1305 &clkc CLKID_VCLK2_VENCL>;
1306 clock-names = "encp_top_gate",
1307 "encp_int_gate0",
1308 "encp_int_gate1",
1309 "venci_top_gate",
1310 "enci_int_gate0",
1311 "enci_int_gate1",
1312 "encl_top_gate",
1313 "encl_int_gate";
1314 };
1315
1316 vdac {
1317 compatible = "amlogic, vdac-sm1";
1318 status = "okay";
1319 };
1320
1321 canvas: canvas{
1322 compatible = "amlogic, meson, canvas";
1323 dev_name = "amlogic-canvas";
1324 status = "okay";
1325 reg = <0x0 0xff638000 0x0 0x2000>;
1326 };
1327
1328 ge2d {
1329 compatible = "amlogic, ge2d-sm1";
1330 dev_name = "ge2d";
1331 status = "okay";
1332 interrupts = <0 146 1>;
1333 interrupt-names = "ge2d";
1334 clocks = <&clkc CLKID_VAPB_MUX>,
1335 <&clkc CLKID_G2D>,
1336 <&clkc CLKID_GE2D_GATE>;
1337 clock-names = "clk_vapb_0",
1338 "clk_ge2d",
1339 "clk_ge2d_gate";
1340 reg = <0x0 0xff940000 0x0 0x10000>;
1341 };
1342
1343 meson-amvideom {
1344 compatible = "amlogic, amvideom";
1345 dev_name = "amvideom";
1346 status = "okay";
1347 interrupts = <0 3 1>;
1348 interrupt-names = "vsync";
1349 };
1350
1351 codec_io: codec_io {
1352 compatible = "amlogic, codec_io";
1353 status = "okay";
1354 #address-cells=<2>;
1355 #size-cells=<2>;
1356 ranges;
1357 io_cbus_base{
1358 reg = <0x0 0xffd00000 0x0 0x100000>;
1359 };
1360 io_dos_base{
1361 reg = <0x0 0xff620000 0x0 0x10000>;
1362 };
1363 io_hiubus_base{
1364 reg = <0x0 0xff63c000 0x0 0x2000>;
1365 };
1366 io_aobus_base{
1367 reg = <0x0 0xff800000 0x0 0x10000>;
1368 };
1369 io_vcbus_base{
1370 reg = <0x0 0xff900000 0x0 0x40000>;
1371 };
1372 io_dmc_base{
1373 reg = <0x0 0xff638000 0x0 0x2000>;
1374 };
1375 io_efuse_base{
1376 reg = <0x0 0xff630000 0x0 0x2000>;
1377 };
1378 };
1379
1380 mesonstream {
1381 compatible = "amlogic, codec, streambuf";
1382 dev_name = "mesonstream";
1383 status = "okay";
1384 clocks = <&clkc CLKID_DOS_PARSER
1385 &clkc CLKID_DEMUX
1386 &clkc CLKID_AHB_ARB0
1387 &clkc CLKID_DOS
1388 &clkc CLKID_CLK81
1389 &clkc CLKID_VDEC_MUX
1390 &clkc CLKID_HCODEC_MUX
1391 &clkc CLKID_HEVC_MUX
1392 &clkc CLKID_HEVCF_MUX>;
1393 clock-names = "parser_top",
1394 "demux",
1395 "ahbarb0",
1396 "vdec",
1397 "clk_81",
1398 "clk_vdec_mux",
1399 "clk_hcodec_mux",
1400 "clk_hevc_mux",
1401 "clk_hevcb_mux";
1402 };
1403
1404 vdec {
1405 compatible = "amlogic, vdec";
1406 dev_name = "vdec.0";
1407 status = "okay";
1408 interrupts = <0 3 1
1409 0 23 1
1410 0 32 1
1411 0 43 1
1412 0 44 1
1413 0 45 1>;
1414 interrupt-names = "vsync",
1415 "demux",
1416 "parser",
1417 "mailbox_0",
1418 "mailbox_1",
1419 "mailbox_2";
1420 };
1421
1422 vcodec_dec {
1423 compatible = "amlogic, vcodec-dec";
1424 dev_name = "aml-vcodec-dec";
1425 status = "okay";
1426 };
1427
1428 video_composer {
1429 compatible = "amlogic, video_composer";
1430 dev_name = "video_composer";
1431 status = "okay";
1432 };
1433
1434 amvenc_avc{
1435 compatible = "amlogic, amvenc_avc";
1436 dev_name = "amvenc_avc";
1437 status = "okay";
1438 interrupts = <0 45 1>;
1439 interrupt-names = "mailbox_2";
1440 };
1441
1442 hevc_enc{
1443 compatible = "cnm, HevcEnc";
1444 //memory-region = <&hevc_enc_reserved>;
1445 dev_name = "HevcEnc";
1446 status = "okay";
1447 interrupts = <0 187 1>;
1448 interrupt-names = "wave420l_irq";
1449 #address-cells=<2>;
1450 #size-cells=<2>;
1451 ranges;
1452 io_reg_base{
1453 reg = <0x0 0xff610000 0x0 0x4000>;
1454 };
1455 };
1456
1457 rdma{
1458 compatible = "amlogic, meson, rdma";
1459 dev_name = "amlogic-rdma";
1460 status = "okay";
1461 interrupts = <0 89 1>;
1462 interrupt-names = "rdma";
1463 };
1464
1465 meson_fb: fb {
1466 compatible = "amlogic, meson-sm1";
1467 memory-region = <&logo_reserved>;
1468 dev_name = "meson-fb";
1469 status = "disable";
1470 interrupts = <0 3 1
1471 0 56 1
1472 0 89 1>;
1473 interrupt-names = "viu-vsync", "viu2-vsync", "rdma";
1474 /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/
1475 display_mode_default = "1080p60hz";
1476 scale_mode = <1>;
1477 /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */
1478 display_size_default = <1920 1080 1920 2160 32>;
1479 /*1920*1080*4*3 = 0x17BB000*/
1480 clocks = <&clkc CLKID_VPU_CLKC_MUX>;
1481 clock-names = "vpu_clkc";
1482 };
1483
1484 irblaster: meson-irblaster {
1485 compatible = "amlogic, meson_irblaster";
1486 reg = <0x0 0xff80014c 0x0 0x10>,
1487 <0x0 0xff800040 0x0 0x4>;
1488 pinctrl-names = "default";
1489 pinctrl-0 = <&irblaster_pins>;
1490 interrupts = <0 198 1>;
1491 status = "okay";
1492 };
1493
1494 sd_emmc_c: emmc@ffe07000 {
1495 status = "disabled";
1496 compatible = "amlogic, meson-mmc-sm1";
1497 reg = <0x0 0xffe07000 0x0 0x800>;
1498 interrupts = <0 191 1>;
1499 pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins";
1500 pinctrl-0 = <&emmc_clk_cmd_pins>;
1501 pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>;
1502 clocks = <&clkc CLKID_SD_EMMC_C>,
1503 <&clkc CLKID_SD_EMMC_C_P0_COMP>,
1504 <&clkc CLKID_FCLK_DIV2>,
1505 <&clkc CLKID_FCLK_DIV2P5>,
1506 <&xtal>;
1507 clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal";
1508
1509 bus-width = <8>;
1510 cap-sd-highspeed;
1511 cap-mmc-highspeed;
1512 /* mmc-ddr-1_8v; */
1513 /* mmc-hs200-1_8v; */
1514
1515 max-frequency = <200000000>;
1516 non-removable;
1517 disable-wp;
1518 emmc {
1519 pinname = "emmc";
1520 ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */
1521 /*caps defined in dts*/
1522 tx_delay = <0x13>;
1523 co_phase = <3>;
1524 max_req_size = <0x20000>; /**128KB*/
1525 gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>;
1526 hw_reset = <&gpio BOOT_12 GPIO_ACTIVE_HIGH>;
1527 card_type = <1>;
1528 /* 1:mmc card(include eMMC),
1529 * 2:sd card(include tSD)
1530 */
1531 };
1532 };
1533
1534 sd_emmc_b:sd@ffe05000 {
1535 status = "disabled";
1536 compatible = "amlogic, meson-mmc-sm1";
1537 reg = <0x0 0xffe05000 0x0 0x800>;
1538 interrupts = <0 190 1>;
1539
1540 pinctrl-names = "sd_all_pins",
1541 "sd_clk_cmd_pins",
1542 "sd_1bit_pins",
1543 "sd_clk_cmd_uart_pins",
1544 "sd_1bit_uart_pins",
1545 "sd_to_ao_uart_pins",
1546 "ao_to_sd_uart_pins",
1547 "sd_to_ao_jtag_pins",
1548 "ao_to_sd_jtag_pins";
1549
1550 pinctrl-0 = <&sd_all_pins>;
1551 pinctrl-1 = <&sd_clk_cmd_pins>;
1552 pinctrl-2 = <&sd_1bit_pins>;
1553 pinctrl-3 = <&sd_to_ao_uart_clr_pins
1554 &sd_clk_cmd_pins &ao_to_sd_uart_pins>;
1555 pinctrl-4 = <&sd_to_ao_uart_clr_pins
1556 &sd_1bit_pins &ao_to_sd_uart_pins>;
1557 pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>;
1558 pinctrl-6 = <&sd_to_ao_uart_clr_pins
1559 &ao_to_sd_uart_pins>;
1560 pinctrl-7 = <&sd_all_pins &sd_to_ao_uart_pins>;
1561 pinctrl-8 = <&sd_to_ao_uart_clr_pins
1562 &ao_to_sd_uart_pins>;
1563
1564 clocks = <&clkc CLKID_SD_EMMC_B>,
1565 <&clkc CLKID_SD_EMMC_B_P0_COMP>,
1566 <&clkc CLKID_FCLK_DIV2>,
1567 <&clkc CLKID_FCLK_DIV5>,
1568 <&xtal>;
1569 clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal";
1570
1571 bus-width = <4>;
1572 cap-sd-highspeed;
1573 cap-mmc-highspeed;
1574 max-frequency = <100000000>;
1575 disable-wp;
1576 sd {
1577 pinname = "sd";
1578 ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */
1579 max_req_size = <0x20000>; /**128KB*/
1580 gpio_dat3 = <&gpio GPIOC_3 GPIO_ACTIVE_HIGH>;
1581 jtag_pin = <&gpio GPIOC_0 GPIO_ACTIVE_HIGH>;
1582 gpio_cd = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
1583 card_type = <5>;
1584 /* 3:sdio device(ie:sdio-wifi),
1585 * 4:SD combo (IO+mem) card
1586 */
1587 };
1588 };
1589
1590
1591 sd_emmc_a:sdio@ffe03000 {
1592 status = "disabled";
1593 compatible = "amlogic, meson-mmc-sm1";
1594 reg = <0x0 0xffe03000 0x0 0x800>;
1595 interrupts = <0 189 4>;
1596
1597 pinctrl-names = "sdio_all_pins",
1598 "sdio_clk_cmd_pins";
1599 pinctrl-0 = <&sdio_all_pins>;
1600 pinctrl-1 = <&sdio_clk_cmd_pins>;
1601
1602 clocks = <&clkc CLKID_SD_EMMC_A>,
1603 <&clkc CLKID_SD_EMMC_A_P0_COMP>,
1604 <&clkc CLKID_FCLK_DIV2>,
1605 <&clkc CLKID_FCLK_DIV5>,
1606 <&xtal>;
1607 clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal";
1608
1609 bus-width = <4>;
1610 cap-sd-highspeed;
1611 cap-mmc-highspeed;
1612 max-frequency = <100000000>;
1613 disable-wp;
1614 sdio {
1615 pinname = "sdio";
1616 ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */
1617 max_req_size = <0x20000>; /**128KB*/
1618 card_type = <3>;
1619 /* 3:sdio device(ie:sdio-wifi),
1620 * 4:SD combo (IO+mem) card
1621 */
1622 };
1623 };
1624
1625 nand: nfc@0 {
1626 compatible = "amlogic, aml_mtd_nand";
1627 dev_name = "mtdnand";
1628 status = "disabled";
1629 reg = <0x0 0xFFE07800 0x0 0x200>;
1630 interrupts = <0 34 1>;
1631 pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only";
1632 pinctrl-0 = <&all_nand_pins>;
1633 pinctrl-1 = <&all_nand_pins>;
1634 pinctrl-2 = <&nand_cs_pins>;
1635 device_id = <0>;
1636 clocks = <&clkc CLKID_SD_EMMC_C>,
1637 <&clkc CLKID_FCLK_DIV2>;
1638 clock-names = "gate", "fdiv2pll";
1639 bl_mode = <1>;
1640 fip_copies = <4>;
1641 fip_size = <0x200000>;
1642 nand_clk_ctrl = <0xFFE07000>;
1643 };
1644
1645 vddcpu0: pwmao_d-regulator {
1646 compatible = "pwm-regulator";
1647 pwms = <&pwm_AO_cd MESON_PWM_1 1500 0>;
1648 regulator-name = "vddcpu0";
1649 regulator-min-microvolt = <690000>;
1650 regulator-max-microvolt = <1050000>;
1651 regulator-always-on;
1652 max-duty-cycle = <1500>;
1653 /* Voltage Duty-Cycle */
1654 voltage-table = <1050000 0>,
1655 <1040000 3>,
1656 <1030000 6>,
1657 <1020000 8>,
1658 <1010000 11>,
1659 <1000000 14>,
1660 <990000 17>,
1661 <980000 20>,
1662 <970000 23>,
1663 <960000 26>,
1664 <950000 29>,
1665 <940000 31>,
1666 <930000 34>,
1667 <920000 37>,
1668 <910000 40>,
1669 <900000 43>,
1670 <890000 45>,
1671 <880000 48>,
1672 <870000 51>,
1673 <860000 54>,
1674 <850000 56>,
1675 <840000 59>,
1676 <830000 62>,
1677 <820000 65>,
1678 <810000 68>,
1679 <800000 70>,
1680 <790000 73>,
1681 <780000 76>,
1682 <770000 79>,
1683 <760000 81>,
1684 <750000 84>,
1685 <740000 87>,
1686 <730000 89>,
1687 <720000 92>,
1688 <710000 95>,
1689 <700000 98>,
1690 <690000 100>;
1691 status = "okay";
1692 };
1693
1694 ddr_bandwidth {
1695 compatible = "amlogic, ddr-bandwidth";
1696 status = "okay";
1697 reg = <0x0 0xff638000 0x0 0x100
1698 0x0 0xff638c00 0x0 0x100>;
1699 sec_base = <0xff639000>;
1700 interrupts = <0 52 1>;
1701 interrupt-names = "ddr_bandwidth";
1702 };
1703 dmc_monitor {
1704 compatible = "amlogic, dmc_monitor";
1705 status = "okay";
1706 reg_base = <0xff639000>;
1707 interrupts = <0 51 1>;
1708 };
1709
1710 defendkey: defendkey {
1711 compatible = "amlogic, defendkey";
1712 reg = <0x0 0xff630218 0x0 0x4>; /*RNG_USR_DATA*/
1713 mem_size = <0x0 0x100000>;
1714 status = "okay";
1715 };
1716
1717 aml_dma {
1718 compatible = "amlogic,aml_txlx_dma";
1719 reg = <0x0 0xff63e000 0x0 0x48>;
1720 interrupts = <0 180 1>;
1721
1722 aml_aes {
1723 compatible = "amlogic,aes_g12a_dma";
1724 dev_name = "aml_aes_dma";
1725 status = "okay";
1726 };
1727
1728 aml_sha {
1729 compatible = "amlogic,sha_dma";
1730 dev_name = "aml_sha_dma";
1731 status = "okay";
1732 };
1733 };
1734
1735 rng {
1736 compatible = "amlogic,meson-rng";
1737 status = "okay";
1738 #address-cells = <2>;
1739 #size-cells = <2>;
1740 reg = <0x0 0xff630218 0x0 0x4>;
1741 quality = /bits/ 16 <1000>;
1742 };
1743
1744 efuse: efuse{
1745 compatible = "amlogic, efuse";
1746 read_cmd = <0x82000030>;
1747 write_cmd = <0x82000031>;
1748 get_max_cmd = <0x82000033>;
1749 key = <&efusekey>;
1750 clocks = <&clkc CLKID_EFUSE>;
1751 clock-names = "efuse_clk";
1752 status = "disabled";
1753 };
1754
1755 cpu_ver_name {
1756 compatible = "amlogic, cpu-major-id-sm1";
1757 };
1758
1759 p_tsensor: p_tsensor@ff634800 {
1760 compatible = "amlogic, r1p1-tsensor";
1761 device_name = "meson-pthermal";
1762 status = "okay";
1763 reg = <0x0 0xff634800 0x0 0x50>,
1764 <0x0 0xff800268 0x0 0x4>;
1765 cal_type = <0x1>;
1766 cal_a = <324>;
1767 cal_b = <424>;
1768 cal_c = <3159>;
1769 cal_d = <9411>;
1770 rtemp = <115000>;
1771 interrupts = <0 35 0>;
1772 clocks = <&clkc CLKID_TS_COMP>; /* CLKID_TS_COMP>;*/
1773 clock-names = "ts_comp";
1774 #thermal-sensor-cells = <1>;
1775 };
1776
1777 d_tsensor: d_tsensor@ff634c00 {
1778 compatible = "amlogic, r1p1-tsensor";
1779 device_name = "meson-dthermal";
1780 status = "okay";
1781 reg = <0x0 0xff634c00 0x0 0x50>,
1782 <0x0 0xff800230 0x0 0x4>;
1783 cal_type = <0x1>;
1784 cal_a = <324>;
1785 cal_b = <424>;
1786 cal_c = <3159>;
1787 cal_d = <9411>;
1788 rtemp = <115000>;
1789 interrupts = <0 36 0>;
1790 clocks = <&clkc CLKID_TS_COMP>; /* CLKID_TS_COMP>;*/
1791 clock-names = "ts_comp";
1792 #thermal-sensor-cells = <1>;
1793 };
1794
1795 meson_cooldev: meson-cooldev@0 {
1796 status = "okay";
1797 compatible = "amlogic, meson-cooldev";
1798 device_name = "mcooldev";
1799 cooling_devices {
1800 cpufreq_cool_cluster0 {
1801 min_state = <1000000>;
1802 dyn_coeff = <125>;
1803 gpu_pp = <2>;
1804 cluster_id = <0>;
1805 node_name = "cpufreq_cool0";
1806 device_type = "cpufreq";
1807 };
1808 cpucore_cool_cluster0 {
1809 min_state = <1>;
1810 dyn_coeff = <0>;
1811 gpu_pp = <2>;
1812 cluster_id = <0>;
1813 node_name = "cpucore_cool0";
1814 device_type = "cpucore";
1815 };
1816 gpufreq_cool {
1817 min_state = <500>;
1818 dyn_coeff = <215>;
1819 gpu_pp = <2>;
1820 cluster_id = <0>;
1821 node_name = "gpufreq_cool0";
1822 device_type = "gpufreq";
1823 };
1824 gpucore_cool {
1825 min_state = <1>;
1826 dyn_coeff = <0>;
1827 gpu_pp = <2>;
1828 cluster_id = <0>;
1829 node_name = "gpucore_cool0";
1830 device_type = "gpucore";
1831 };
1832 };
1833 cpufreq_cool0:cpufreq_cool0 {
1834 #cooling-cells = <2>; /* min followed by max */
1835 };
1836 cpucore_cool0:cpucore_cool0 {
1837 #cooling-cells = <2>; /* min followed by max */
1838 };
1839 gpufreq_cool0:gpufreq_cool0 {
1840 #cooling-cells = <2>; /* min followed by max */
1841 };
1842 gpucore_cool0:gpucore_cool0 {
1843 #cooling-cells = <2>; /* min followed by max */
1844 };
1845 };
1846 /*meson cooling devices end*/
1847
1848 thermal-zones {
1849 soc_thermal: soc_thermal {
1850 polling-delay = <1000>;
1851 polling-delay-passive = <100>;
1852 sustainable-power = <1410>;
1853 thermal-sensors = <&p_tsensor 0>;
1854 trips {
1855 pswitch_on: trip-point@0 {
1856 temperature = <60000>;
1857 hysteresis = <5000>;
1858 type = "passive";
1859 };
1860 pcontrol: trip-point@1 {
1861 temperature = <75000>;
1862 hysteresis = <5000>;
1863 type = "passive";
1864 };
1865 phot: trip-point@2 {
1866 temperature = <85000>;
1867 hysteresis = <5000>;
1868 type = "hot";
1869 };
1870 pcritical: trip-point@3 {
1871 temperature = <110000>;
1872 hysteresis = <1000>;
1873 type = "critical";
1874 };
1875 };
1876
1877 cooling-maps {
1878 cpufreq_cooling_map {
1879 trip = <&pcontrol>;
1880 cooling-device = <&cpufreq_cool0 0 4>;
1881 contribution = <1024>;
1882 };
1883 cpucore_cooling_map {
1884 trip = <&pcontrol>;
1885 cooling-device = <&cpucore_cool0 0 3>;
1886 contribution = <1024>;
1887 };
1888 gpufreq_cooling_map {
1889 trip = <&pcontrol>;
1890 cooling-device = <&gpufreq_cool0 0 3>;
1891 contribution = <1024>;
1892 };
1893 gpucore_cooling_map {
1894 trip = <&pcontrol>;
1895 cooling-device = <&gpucore_cool0 0 2>;
1896 contribution = <1024>;
1897 };
1898 };
1899 };
1900 ddr_thermal: ddr_thermal {
1901 polling-delay = <2000>;
1902 polling-delay-passive = <1000>;
1903 sustainable-power = <1410>;
1904 thermal-sensors = <&d_tsensor 1>;
1905 trips {
1906 dswitch_on: trip-point@0 {
1907 temperature = <60000>;
1908 hysteresis = <5000>;
1909 type = "passive";
1910 };
1911 dcontrol: trip-point@1 {
1912 temperature = <75000>;
1913 hysteresis = <5000>;
1914 type = "passive";
1915 };
1916 dhot: trip-point@2 {
1917 temperature = <85000>;
1918 hysteresis = <5000>;
1919 type = "hot";
1920 };
1921 dcritical: trip-point@3 {
1922 temperature = <110000>;
1923 hysteresis = <1000>;
1924 type = "critical";
1925 };
1926 };
1927 };
1928 };/*thermal zone end*/
1929 };/* end of / */
1930
1931 &pinctrl_aobus {
1932 sd_to_ao_uart_clr_pins:sd_to_ao_uart_clr_pins {
1933 mux {
1934 groups = "GPIOAO_0",
1935 "GPIOAO_1";
1936 function = "gpio_aobus";
1937 };
1938 };
1939
1940 sd_to_ao_uart_pins:sd_to_ao_uart_pins {
1941 mux {
1942 groups = "uart_ao_tx_a",
1943 "uart_ao_rx_a";
1944 function = "uart_ao_a";
1945 bias-pull-up;
1946 input-enable;
1947 };
1948 };
1949
1950 ao_uart_pins:ao_uart {
1951 mux {
1952 groups = "uart_ao_tx_a",
1953 "uart_ao_rx_a";
1954 function = "uart_ao_a";
1955 };
1956 };
1957
1958 ao_b_uart_pins:ao_b_uart {
1959 mux {
1960 groups = "uart_ao_tx_b_2",
1961 "uart_ao_rx_b_3";
1962 function = "uart_ao_b";
1963 };
1964 };
1965
1966 ao_i2c_master_pins1:ao_i2c_pins1 {
1967 mux {
1968 groups = "i2c_ao_sck",
1969 "i2c_ao_sda";
1970 function = "i2c_ao";
1971 drive-strength = <2>;
1972 };
1973 };
1974
1975 ao_i2c_master_pins2:ao_i2c_pins2 {
1976 mux {
1977 groups = "i2c_ao_sck_e",
1978 "i2c_ao_sda_e";
1979 function = "i2c_ao";
1980 drive-strength = <2>;
1981 };
1982 };
1983
1984 ao_i2c_slave_pins:ao_i2c_slave_pins {
1985 mux {
1986 groups = "i2c_ao_slave_sck",
1987 "i2c_ao_slave_sda";
1988 function = "i2c_ao_slave";
1989 };
1990 };
1991
1992 pwm_ao_a_pins: pwm_ao_a {
1993 mux {
1994 groups = "pwm_ao_a";
1995 function = "pwm_ao_a";
1996 };
1997 };
1998
1999 pwm_ao_a_hiz_pins: pwm_ao_a_hiz {
2000 mux {
2001 groups = "pwm_ao_a_hiz";
2002 function = "pwm_ao_a";
2003 };
2004 };
2005
2006 pwm_ao_b_pins: pwm_ao_b {
2007 mux {
2008 groups = "pwm_ao_b";
2009 function = "pwm_ao_b";
2010 };
2011 };
2012
2013 pwm_ao_c_pins1: pwm_ao_c_pins1 {
2014 mux {
2015 groups = "pwm_ao_c_4";
2016 function = "pwm_ao_c";
2017 };
2018 };
2019
2020 pwm_ao_c_pins2: pwm_ao_c_pins2 {
2021 mux {
2022 groups = "pwm_ao_c_6";
2023 function = "pwm_ao_c";
2024 };
2025 };
2026
2027 pwm_ao_c_hiz_pins: pwm_ao_c_hiz {
2028 mux {
2029 groups = "pwm_ao_c_hiz_4";
2030 function = "pwm_ao_c";
2031 };
2032 };
2033
2034 pwm_ao_d_pins1: pwm_ao_d_pins1 {
2035 mux {
2036 groups = "pwm_ao_d_5";
2037 function = "pwm_ao_d";
2038 };
2039 };
2040
2041 pwm_ao_d_pins2: pwm_ao_d_pins2 {
2042 mux {
2043 groups = "pwm_ao_d_10";
2044 function = "pwm_ao_d";
2045 };
2046 };
2047
2048 pwm_ao_d_pins3: pwm_ao_d_pins3 {
2049 mux {
2050 groups = "pwm_ao_d_e";
2051 function = "pwm_ao_d";
2052 };
2053 };
2054
2055 aocec_a: ao_ceca {
2056 mux {
2057 groups = "cec_ao_a";
2058 function = "cec_ao";
2059 };
2060 };
2061
2062 aocec_b: ao_cecb {
2063 mux {
2064 groups = "cec_ao_b";
2065 function = "cec_ao";
2066 };
2067 };
2068
2069 jtag_apao_pins:jtag_apao_pin {
2070 mux {
2071 groups = "jtag_a_tdi",
2072 "jtag_a_tdo",
2073 "jtag_a_clk",
2074 "jtag_a_tms";
2075 function = "jtag_a";
2076 };
2077 };
2078 };
2079
2080 &pinctrl_periphs {
2081 /* sdemmc portC */
2082 emmc_clk_cmd_pins:emmc_clk_cmd_pins {
2083 mux {
2084 groups = "emmc_clk",
2085 "emmc_cmd";
2086 function = "emmc";
2087 input-enable;
2088 bias-pull-up;
2089 drive-strength = <3>;
2090 };
2091 };
2092
2093 emmc_conf_pull_up:emmc_conf_pull_up {
2094 mux {
2095 groups = "emmc_nand_d7",
2096 "emmc_nand_d6",
2097 "emmc_nand_d5",
2098 "emmc_nand_d4",
2099 "emmc_nand_d3",
2100 "emmc_nand_d2",
2101 "emmc_nand_d1",
2102 "emmc_nand_d0",
2103 "emmc_clk",
2104 "emmc_cmd";
2105 function = "emmc";
2106 input-enable;
2107 bias-pull-up;
2108 drive-strength = <3>;
2109 };
2110 };
2111
2112 emmc_conf_pull_done:emmc_conf_pull_done {
2113 mux {
2114 groups = "emmc_nand_ds";
2115 function = "emmc";
2116 input-enable;
2117 bias-pull-down;
2118 drive-strength = <3>;
2119 };
2120 };
2121
2122 /* sdemmc portB */
2123 sd_clk_cmd_pins:sd_clk_cmd_pins {
2124 mux {
2125 groups = "sdcard_cmd_c";
2126 function = "sdcard";
2127 input-enable;
2128 bias-pull-up;
2129 drive-strength = <3>;
2130 };
2131 mux1 {
2132 groups = "sdcard_clk_c";
2133 function = "sdcard";
2134 bias-pull-up;
2135 output-high;
2136 drive-strength = <3>;
2137 };
2138 };
2139
2140 sd_all_pins:sd_all_pins {
2141 mux {
2142 groups = "sdcard_d0_c",
2143 "sdcard_d1_c",
2144 "sdcard_d2_c",
2145 "sdcard_d3_c",
2146 "sdcard_cmd_c";
2147 function = "sdcard";
2148 input-enable;
2149 bias-pull-up;
2150 drive-strength = <3>;
2151 };
2152 mux1 {
2153 groups = "sdcard_clk_c";
2154 function = "sdcard";
2155 bias-pull-up;
2156 output-high;
2157 drive-strength = <3>;
2158 };
2159 };
2160
2161 sd_1bit_pins:sd_1bit_pins {
2162 mux {
2163 groups = "sdcard_d0_c",
2164 "sdcard_cmd_c";
2165 function = "sdcard";
2166 input-enable;
2167 bias-pull-up;
2168 drive-strength = <3>;
2169 };
2170 mux1 {
2171 groups = "sdcard_clk_c";
2172 function = "sdcard";
2173 bias-pull-up;
2174 output-high;
2175 drive-strength = <3>;
2176 };
2177 };
2178
2179 sd_clr_all_pins:sd_clr_all_pins {
2180 mux {
2181 groups = "GPIOC_0",
2182 "GPIOC_1",
2183 "GPIOC_2",
2184 "GPIOC_3",
2185 "GPIOC_5";
2186 function = "gpio_periphs";
2187 output-high;
2188 };
2189 mux1 {
2190 groups = "GPIOC_4";
2191 function = "gpio_periphs";
2192 output-low;
2193 };
2194 };
2195
2196 sd_clr_noall_pins:sd_clr_noall_pins {
2197 mux {
2198 groups = "GPIOC_0",
2199 "GPIOC_1",
2200 "GPIOC_4",
2201 "GPIOC_5";
2202 function = "gpio_periphs";
2203 output-high;
2204 };
2205 };
2206
2207 ao_to_sd_uart_pins:ao_to_sd_uart_pins {
2208 mux {
2209 groups = "uart_ao_tx_a_c3",
2210 "uart_ao_rx_a_c2";
2211 function = "uart_ao_a_ee";
2212 bias-pull-up;
2213 input-enable;
2214 };
2215 };
2216
2217 /* sdemmc portA */
2218 sdio_clk_cmd_pins:sdio_clk_cmd_pins {
2219 mux {
2220 groups = "sdio_clk",
2221 "sdio_cmd";
2222 function = "sdio";
2223 input-enable;
2224 bias-pull-up;
2225 drive-strength = <3>;
2226 };
2227 };
2228
2229 sdio_all_pins:sdio_all_pins {
2230 mux {
2231 groups = "sdio_d0",
2232 "sdio_d1",
2233 "sdio_d2",
2234 "sdio_d3",
2235 "sdio_clk",
2236 "sdio_cmd";
2237 function = "sdio";
2238 input-enable;
2239 bias-pull-up;
2240 drive-strength = <3>;
2241 };
2242 };
2243
2244 sdio_x_clk_cmd_pins:sdio_x_clk_cmd_pins {
2245 mux {
2246 groups = "GPIOX_5";
2247 function = "gpio_periphs";
2248 input-enable;
2249 bias-pull-up;
2250 drive-strength = <3>;
2251 };
2252 mux1 {
2253 groups = "GPIOX_4";
2254 function = "gpio_periphs";
2255 bias-pull-up;
2256 output-high;
2257 drive-strength = <3>;
2258 };
2259 };
2260
2261 sdio_x_all_pins:sdio_x_all_pins {
2262 mux {
2263 groups = "GPIOX_0",
2264 "GPIOX_1",
2265 "GPIOX_2",
2266 "GPIOX_3",
2267 "GPIOX_5";
2268 function = "gpio_periphs";
2269 input-enable;
2270 bias-pull-up;
2271 drive-strength = <3>;
2272 };
2273 mux1 {
2274 groups = "GPIOX_4";
2275 function = "gpio_periphs";
2276 bias-pull-up;
2277 output-high;
2278 drive-strength = <3>;
2279 };
2280 };
2281
2282 sdio_x_en_pins:sdio_x_en_pins {
2283 mux {
2284 groups = "sdio_dummy";
2285 function = "sdio";
2286 bias-pull-up;
2287 output-high;
2288 };
2289 };
2290
2291 sdio_x_clr_pins:sdio_x_clr_pins {
2292 mux {
2293 groups = "GPIOV_0";
2294 function = "gpio_periphs";
2295 bias-pull-up;
2296 output-low;
2297 };
2298 mux1 {
2299 groups = "GPIOX_4";
2300 function = "gpio_periphs";
2301 output-low;
2302 };
2303 };
2304
2305 all_nand_pins: all_nand_pins {
2306 mux {
2307 groups = "emmc_nand_d0",
2308 "emmc_nand_d1",
2309 "emmc_nand_d2",
2310 "emmc_nand_d3",
2311 "emmc_nand_d4",
2312 "emmc_nand_d5",
2313 "emmc_nand_d6",
2314 "emmc_nand_d7",
2315 "nand_ce0",
2316 "nand_ale",
2317 "nand_cle",
2318 "nand_wen_clk",
2319 "nand_ren_wr",
2320 "nand_rb0";
2321 function = "nand";
2322 input-enable;
2323 };
2324 };
2325
2326 nand_cs_pins: nand_cs {
2327 mux {
2328 groups = "nand_ce0";
2329 function = "nand";
2330 };
2331 };
2332
2333 i2c0_master_pins1:i2c0_pins1 {
2334 mux {
2335 groups = "i2c0_sda_c",
2336 "i2c0_sck_c";
2337 function = "i2c0";
2338 drive-strength = <2>;
2339 };
2340 };
2341
2342 i2c0_master_pins2:i2c0_pins2 {
2343 mux {
2344 groups = "i2c0_sda_z0",
2345 "i2c0_sck_z1";
2346 function = "i2c0";
2347 drive-strength = <2>;
2348 };
2349 };
2350
2351 i2c0_master_pins3:i2c0_pins3 {
2352 mux {
2353 groups = "i2c0_sda_z7",
2354 "i2c0_sck_z8";
2355 function = "i2c0";
2356 drive-strength = <2>;
2357 };
2358 };
2359
2360 i2c1_master_pins1:i2c1_pins1 {
2361 mux {
2362 groups = "i2c1_sda_x",
2363 "i2c1_sck_x";
2364 function = "i2c1";
2365 drive-strength = <2>;
2366 };
2367 };
2368
2369 i2c1_master_pins2:i2c1_pins2 {
2370 mux {
2371 groups = "i2c1_sda_h2",
2372 "i2c1_sck_h3";
2373 function = "i2c1";
2374 drive-strength = <2>;
2375 };
2376 };
2377
2378 i2c1_master_pins3:i2c1_pins3 {
2379 mux {
2380 groups = "i2c1_sda_h6",
2381 "i2c1_sck_h7";
2382 function = "i2c1";
2383 drive-strength = <2>;
2384 };
2385 };
2386
2387 i2c2_master_pins1:i2c2_pins1 {
2388 mux {
2389 groups = "i2c2_sda_x",
2390 "i2c2_sck_x";
2391 function = "i2c2";
2392 drive-strength = <2>;
2393 };
2394 };
2395
2396 i2c2_master_pins2:i2c2_pins2 {
2397 mux {
2398 groups = "i2c2_sda_z",
2399 "i2c2_sck_z";
2400 function = "i2c2";
2401 drive-strength = <2>;
2402 };
2403 };
2404
2405 i2c2_master_pins3:i2c2_pins3 {
2406 mux {
2407 groups = "i2c2_sda_z10",
2408 "i2c2_sck_z11";
2409 function = "i2c2";
2410 drive-strength = <2>;
2411 };
2412 };
2413
2414 i2c3_master_pins1:i2c3_pins1 {
2415 mux {
2416 groups = "i2c3_sda_h",
2417 "i2c3_sck_h";
2418 function = "i2c3";
2419 drive-strength = <2>;
2420 };
2421 };
2422
2423 i2c3_master_pins2:i2c3_pins2 {
2424 mux {
2425 groups = "i2c3_sda_a",
2426 "i2c3_sck_a";
2427 function = "i2c3";
2428 drive-strength = <2>;
2429 };
2430 };
2431
2432 /*dvb_p_ts1_pins: dvb_p_ts1_pins {
2433 * tsin_b {
2434 * groups = "tsin_b_sop_z",
2435 * "tsin_b_valid_z",
2436 * "tsin_b_clk_z",
2437 * "tsin_b_din0_z",
2438 * "tsin_b_din1",
2439 * "tsin_b_din2",
2440 * "tsin_b_din3",
2441 * "tsin_b_din4",
2442 * "tsin_b_din5",
2443 * "tsin_b_din6",
2444 * "tsin_b_din7";
2445 * function = "tsin_b";
2446 * };
2447 *};
2448 */
2449
2450 pwm_a_pins: pwm_a {
2451 mux {
2452 groups = "pwm_a";
2453 function = "pwm_a";
2454 };
2455 };
2456
2457 pwm_b_pins1: pwm_b_pins1 {
2458 mux {
2459 groups = "pwm_b_x7";
2460 function = "pwm_b";
2461 };
2462 };
2463
2464 pwm_b_pins2: pwm_b_pins2 {
2465 mux {
2466 groups = "pwm_b_x19";
2467 function = "pwm_b";
2468 };
2469 };
2470
2471 pwm_c_pins1: pwm_c_pins1 {
2472 mux {
2473 groups = "pwm_c_c4";
2474 function = "pwm_c";
2475 };
2476 };
2477
2478 pwm_c_pins2: pwm_c_pins2 {
2479 mux {
2480 groups = "pwm_c_x5";
2481 function = "pwm_c";
2482 };
2483 };
2484
2485 pwm_c_pins3: pwm_c_pins3 {
2486 mux {
2487 groups = "pwm_c_x8";
2488 function = "pwm_c";
2489 };
2490 };
2491
2492 pwm_d_pins1: pwm_d_pins1 {
2493 mux {
2494 groups = "pwm_d_x3";
2495 function = "pwm_d";
2496 };
2497 };
2498
2499 pwm_d_pins2: pwm_d_pins2 {
2500 mux {
2501 groups = "pwm_d_x6";
2502 function = "pwm_d";
2503 };
2504 };
2505
2506 pwm_e_pins: pwm_e {
2507 mux {
2508 groups = "pwm_e";
2509 function = "pwm_e";
2510 drive-strength = <0>;
2511 };
2512 };
2513
2514 pwm_f_pins1: pwm_f_pins1 {
2515 mux {
2516 groups = "pwm_f_x";
2517 function = "pwm_f";
2518 };
2519 };
2520
2521 pwm_f_pins2: pwm_f_pins2 {
2522 mux {
2523 groups = "pwm_f_h";
2524 function = "pwm_f";
2525 };
2526 };
2527
2528 spicc0_pins_x: spicc0_pins_x {
2529 mux {
2530 groups = "spi0_mosi_x",
2531 "spi0_miso_x",
2532 //"spi0_ss0_x",
2533 "spi0_clk_x";
2534 function = "spi0";
2535 drive-strength = <1>;
2536 };
2537 };
2538
2539 spicc0_pins_c: spicc0_pins_c {
2540 mux {
2541 groups = "spi0_mosi_c",
2542 "spi0_miso_c",
2543 "spi0_ss0_c",
2544 "spi0_clk_c";
2545 function = "spi0";
2546 drive-strength = <1>;
2547 };
2548 };
2549
2550 spicc1_pins: spicc1_pins {
2551 mux {
2552 groups = "spi1_mosi",
2553 "spi1_miso",
2554 //"spi1_ss0",
2555 "spi1_clk";
2556 function = "spi1";
2557 drive-strength = <1>;
2558 };
2559 };
2560
2561 a_uart_pins:a_uart {
2562 mux {
2563 groups = "uart_tx_a",
2564 "uart_rx_a",
2565 "uart_cts_a",
2566 "uart_rts_a";
2567 function = "uart_a";
2568 };
2569 };
2570
2571 b_uart_pins:b_uart {
2572 mux {
2573 groups = "uart_tx_b",
2574 "uart_rx_b";
2575 function = "uart_b";
2576 };
2577 };
2578
2579 c_uart_pins:c_uart {
2580 mux {
2581 groups = "uart_tx_c",
2582 "uart_rx_c";
2583 function = "uart_c";
2584 };
2585 };
2586
2587 hdmitx_hpd: hdmitx_hpd {
2588 mux {
2589 groups = "hdmitx_hpd_in";
2590 function = "hdmitx";
2591 bias-disable;
2592 };
2593 };
2594
2595 hdmitx_hpd_gpio: hdmitx_hpd_gpio {
2596 mux {
2597 groups = "GPIOH_1";
2598 function = "gpio_periphs";
2599 bias-disable;
2600 };
2601 };
2602
2603 hdmitx_ddc: hdmitx_ddc {
2604 mux {
2605 groups = "hdmitx_sda",
2606 "hdmitx_sck";
2607 function = "hdmitx";
2608 bias-disable;
2609 drive-strength = <3>;
2610 };
2611 };
2612
2613 eecec_a: ee_ceca {
2614 mux {
2615 groups = "cec_ao_a_ee";
2616 function = "cec_ao_ee";
2617 };
2618 };
2619
2620 eecec_b: ee_cecb {
2621 mux {
2622 groups = "cec_ao_b_ee";
2623 function = "cec_ao_ee";
2624 };
2625 };
2626
2627 internal_eth_pins: internal_eth_pins {
2628 mux {
2629 groups = "eth_link_led",
2630 "eth_act_led";
2631 function = "eth";
2632 };
2633 };
2634
2635 internal_gpio_pins: internal_gpio_pins {
2636 mux {
2637 groups = "GPIOZ_14",
2638 "GPIOZ_15";
2639 function = "gpio_periphs";
2640 bias-disable;
2641 input-enable;
2642 };
2643 };
2644
2645 external_eth_pins: external_eth_pins {
2646 mux {
2647 groups = "eth_mdio",
2648 "eth_mdc",
2649 "eth_rgmii_rx_clk",
2650 "eth_rx_dv",
2651 "eth_rxd0",
2652 "eth_rxd1",
2653 "eth_rxd2_rgmii",
2654 "eth_rxd3_rgmii",
2655 "eth_rgmii_tx_clk",
2656 "eth_txen",
2657 "eth_txd0",
2658 "eth_txd1",
2659 "eth_txd2_rgmii",
2660 "eth_txd3_rgmii";
2661 function = "eth";
2662 drive-strength = <3>;
2663 };
2664 };
2665
2666 jtag_apee_pins:jtag_apee_pin {
2667 mux {
2668 groups = "jtag_b_tdi",
2669 "jtag_b_tdo",
2670 "jtag_b_clk",
2671 "jtag_b_tms";
2672 function = "jtag_b";
2673 };
2674 };
2675 };
2676
2677 &pinctrl_aobus {
2678 remote_pins:remote_pin {
2679 mux {
2680 groups = "remote_input_ao";
2681 function = "remote_input_ao";
2682 };
2683 };
2684
2685 irblaster_pins:irblaster_pin {
2686 mux {
2687 groups = "remote_out_ao";
2688 function = "remote_out_ao";
2689 };
2690 };
2691 }; /* end of pinctrl_aobus */